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Add CC3220SF_Launchxl to Mbed OS

pull/11063/head
Lin Gao 2019-07-17 13:19:32 -05:00
parent 3d5489a6f8
commit e74fbcd79e
189 changed files with 111504 additions and 0 deletions
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6
components/storage/blockdevice/COMPONENT_SD/mbed_lib.json
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"SPI_MISO": "D12",
"SPI_CLK": "D13",
"SPI_CS": "D10"
},
"CC3220SF_LAUNCHXL": {
"SPI_MOSI": "D11",
"SPI_MISO": "D12",
"SPI_CLK": "D13",
"SPI_CS": "D10"
}
}
}

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralPins.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
/************GPIO***************/
extern const PinMap PinMap_GPIO[];
/************PWM****************/
extern const PinMap PinMap_PWM[];
/************UART***************/
extern const PinMap PinMap_UART_TX[];
extern const PinMap PinMap_UART_RX[];
extern const PinMap PinMap_UART_CTS[];
extern const PinMap PinMap_UART_RTS[];
#endif

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PortNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0,
Port1 = 1,
Port2 = 2,
Port3 = 3
} PortName;
#ifdef __cplusplus
}
#endif
#endif

286
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c Executable file
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/*
* Copyright (c) 2016-2018, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== CC3220SF_LAUNCHXL.c ========
* This file is responsible for setting up the board specific items for the
* CC3220SF_LAUNCHXL board.
*/
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <ti/devices/cc32xx/inc/hw_ints.h>
#include <ti/devices/cc32xx/inc/hw_memmap.h>
#include <ti/devices/cc32xx/inc/hw_types.h>
#include <ti/devices/cc32xx/driverlib/rom.h>
#include <ti/devices/cc32xx/driverlib/rom_map.h>
#include <ti/devices/cc32xx/driverlib/adc.h>
#include <ti/devices/cc32xx/driverlib/gpio.h>
#include <ti/devices/cc32xx/driverlib/pin.h>
#include <ti/devices/cc32xx/driverlib/prcm.h>
#include <ti/devices/cc32xx/driverlib/ti_spi_driverlib.h>
#include <ti/devices/cc32xx/driverlib/sdhost.h>
#include <ti/devices/cc32xx/driverlib/ti_timer.h>
#include <ti/devices/cc32xx/driverlib/uart.h>
#include <ti/devices/cc32xx/driverlib/udma.h>
#include <ti/devices/cc32xx/driverlib/interrupt.h>
#include <ti/devices/cc32xx/driverlib/wdt.h>
#include <ti/drivers/Power.h>
#include <ti/drivers/power/PowerCC32XX.h>
#include "CC3220SF_LAUNCHXL.h"
/*
* =============================== Power ===============================
*/
/*
* This table defines the parking state to be set for each parkable pin
* during LPDS. (Device pins must be parked during LPDS to achieve maximum
* power savings.) If the pin should be left unparked, specify the state
* PowerCC32XX_DONT_PARK. For example, for a UART TX pin, the device
* will automatically park the pin in a high state during transition to LPDS,
* so the Power Manager does not need to explictly park the pin. So the
* corresponding entries in this table should indicate PowerCC32XX_DONT_PARK.
*/
PowerCC32XX_ParkInfo parkInfo[] = {
/* PIN PARK STATE PIN ALIAS (FUNCTION)
----------------- ------------------------------ -------------------- */
{PowerCC32XX_PIN01, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO10 */
{PowerCC32XX_PIN02, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO11 */
{PowerCC32XX_PIN03, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO12 */
{PowerCC32XX_PIN04, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO13 */
{PowerCC32XX_PIN05, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO14 */
{PowerCC32XX_PIN06, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO15 */
{PowerCC32XX_PIN07, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO16 */
{PowerCC32XX_PIN08, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO17 */
{PowerCC32XX_PIN13, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* FLASH_SPI_DIN */
{PowerCC32XX_PIN15, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO22 */
{PowerCC32XX_PIN16, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDI (JTAG DEBUG) */
{PowerCC32XX_PIN17, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDO (JTAG DEBUG) */
{PowerCC32XX_PIN19, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TCK (JTAG DEBUG) */
{PowerCC32XX_PIN20, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TMS (JTAG DEBUG) */
{PowerCC32XX_PIN18, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO28 */
{PowerCC32XX_PIN21, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* SOP2 */
{PowerCC32XX_PIN29, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL1 */
{PowerCC32XX_PIN30, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL2 */
{PowerCC32XX_PIN45, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* DCDC_ANA2_SW_P */
{PowerCC32XX_PIN50, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO0 */
{PowerCC32XX_PIN52, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* RTC_XTAL_N */
{PowerCC32XX_PIN53, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO30 */
{PowerCC32XX_PIN55, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO1 (XDS_UART_RX) */
{PowerCC32XX_PIN57, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO2 (XDS_UART_TX) */
{PowerCC32XX_PIN58, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO3 */
{PowerCC32XX_PIN59, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO4 */
{PowerCC32XX_PIN60, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO5 */
{PowerCC32XX_PIN61, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO6 */
{PowerCC32XX_PIN62, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO7 */
{PowerCC32XX_PIN63, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO8 */
{PowerCC32XX_PIN64, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO9 */
};
/*
* This structure defines the configuration for the Power Manager.
*
* In this configuration the Power policy is disabled by default (because
* enablePolicy is set to false). The Power policy can be enabled dynamically
* at runtime by calling Power_enablePolicy(), or at build time, by changing
* enablePolicy to true in this structure.
*/
const PowerCC32XX_ConfigV1 PowerCC32XX_config = {
.policyInitFxn = &PowerCC32XX_initPolicy,
.policyFxn = &PowerCC32XX_sleepPolicy,
.enterLPDSHookFxn = NULL,
.resumeLPDSHookFxn = NULL,
.enablePolicy = false,
.enableGPIOWakeupLPDS = true,
.enableGPIOWakeupShutdown = true,
.enableNetworkWakeupLPDS = true,
.wakeupGPIOSourceLPDS = PRCM_LPDS_GPIO13,
.wakeupGPIOTypeLPDS = PRCM_LPDS_FALL_EDGE,
.wakeupGPIOFxnLPDS = NULL,
.wakeupGPIOFxnLPDSArg = 0,
.wakeupGPIOSourceShutdown = PRCM_HIB_GPIO13,
.wakeupGPIOTypeShutdown = PRCM_HIB_RISE_EDGE,
.ramRetentionMaskLPDS = PRCM_SRAM_COL_1 | PRCM_SRAM_COL_2 |
PRCM_SRAM_COL_3 | PRCM_SRAM_COL_4,
.keepDebugActiveDuringLPDS = false,
.ioRetentionShutdown = PRCM_IO_RET_GRP_1,
.pinParkDefs = parkInfo,
.numPins = sizeof(parkInfo) / sizeof(PowerCC32XX_ParkInfo)
};
/*
* =============================== SPI ===============================
*/
#include <ti/drivers/ti_SPI.h>
#include <ti/drivers/spi/SPICC32XXDMA.h>
SPICC32XXDMA_Object spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPICOUNT];
#ifdef TOOLCHAIN_GCC_ARM
__attribute__ ((aligned (32)))
#elif defined TOOLCHAIN_ARM
__attribute__ ((aligned (32)))
#elif defined TOOLCHAIN_IAR
#pragma data_alignment=32
#endif
uint32_t spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPICOUNT];
const SPICC32XXDMA_HWAttrsV1 spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPICOUNT] = {
/* index 0 is reserved for LSPI that links to the NWP */
{
.baseAddr = LSPI_BASE,
.intNum = INT_LSPI,
.intPriority = (~0),
.spiPRCM = PRCM_LSPI,
.csControl = SPI_SW_CTRL_CS,
.csPolarity = SPI_CS_ACTIVEHIGH,
.pinMode = SPI_4PIN_MODE,
.turboMode = SPI_TURBO_OFF,
.scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI0],
.defaultTxBufValue = 0,
.rxChannelIndex = UDMA_CH12_LSPI_RX,
.txChannelIndex = UDMA_CH13_LSPI_TX,
.minDmaTransferSize = 100,
.mosiPin = SPICC32XXDMA_PIN_NO_CONFIG,
.misoPin = SPICC32XXDMA_PIN_NO_CONFIG,
.clkPin = SPICC32XXDMA_PIN_NO_CONFIG,
.csPin = SPICC32XXDMA_PIN_NO_CONFIG
},
{
.baseAddr = GSPI_BASE,
.intNum = INT_GSPI,
.intPriority = (~0),
.spiPRCM = PRCM_GSPI,
.csControl = SPI_HW_CTRL_CS,
.csPolarity = SPI_CS_ACTIVELOW,
.pinMode = SPI_4PIN_MODE,
.turboMode = SPI_TURBO_OFF,
.scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI1],
.defaultTxBufValue = 0,
.rxChannelIndex = UDMA_CH6_GSPI_RX,
.txChannelIndex = UDMA_CH7_GSPI_TX,
.minDmaTransferSize = 10,
.mosiPin = SPICC32XXDMA_PIN_07_MOSI,
.misoPin = SPICC32XXDMA_PIN_06_MISO,
.clkPin = SPICC32XXDMA_PIN_05_CLK,
.csPin = SPICC32XXDMA_PIN_08_CS
}
};
const SPI_Config SPI_config[CC3220SF_LAUNCHXL_SPICOUNT] = {
{
.fxnTablePtr = &SPICC32XXDMA_fxnTable,
.object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI0],
.hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI0]
},
{
.fxnTablePtr = &SPICC32XXDMA_fxnTable,
.object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI1],
.hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI1]
}
};
const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT;
/*
* =============================== DMA ===============================
*/
#include <ti/drivers/dma/UDMACC32XX.h>
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_ALIGN(dmaControlTable, 1024)
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma data_alignment=1024
#elif defined(__GNUC__)
__attribute__ ((aligned (1024)))
#endif
static tDMAControlTable dmaControlTable[64];
/*
* ======== dmaErrorFxn ========
* This is the handler for the uDMA error interrupt.
*/
static void dmaErrorFxn(uintptr_t arg)
{
int status = MAP_uDMAErrorStatusGet();
MAP_uDMAErrorStatusClear();
/* Suppress unused variable warning */
(void)status;
while (1);
}
UDMACC32XX_Object udmaCC3220SObject;
const UDMACC32XX_HWAttrs udmaCC3220SHWAttrs = {
.controlBaseAddr = (void *)dmaControlTable,
.dmaErrorFxn = (UDMACC32XX_ErrorFxn)dmaErrorFxn,
.intNum = INT_UDMAERR,
.intPriority = (~0)
};
const UDMACC32XX_Config UDMACC32XX_config = {
.object = &udmaCC3220SObject,
.hwAttrs = &udmaCC3220SHWAttrs
};
/*
* =============================== General ===============================
*/
/*
* ======== CC3220SF_LAUNCHXL_initGeneral ========
*/
void CC3220SF_LAUNCHXL_initGeneral(void)
{
MAP_IntMasterEnable();
//MAP_IntEnable(FAULT_SYSTICK);
PRCMCC3200MCUInit();
//Power_init();
}
#if defined TOOLCHAIN_ARM
__attribute__((section("signature_section")))
#elif defined TOOLCHAIN_IAR
#pragma default_variable_attributes = @ ".dbghdr"
#elif defined TOOLCHAIN_GCC_ARM
__attribute__ ((section (".dbghdr")))
#endif
const unsigned long ulDebugHeader[]=
{
0x5AA5A55A,
0x000FF800,
0xEFA3247D
};

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h Executable file
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/*
* Copyright (c) 2016-2018, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file C3220SF_LAUNCHXL.h
*
* @brief CC3220 Board Specific APIs
*
* The CC3220SF_LAUNCHXL header file should be included in an application as
* follows:
* @code
* #include <CC3220SF_LAUNCHXL.h>
* @endcode
*
* ============================================================================
*/
#ifndef __CC3220SF_LAUNCHXL_H
#define __CC3220SF_LAUNCHXL_H
#ifdef __cplusplus
extern "C" {
#endif
#define CC3220SF_LAUNCHXL_GPIO_LED_OFF (0)
#define CC3220SF_LAUNCHXL_GPIO_LED_ON (1)
/*!
* @def CC3220SF_LAUNCHXL_ADCName
* @brief Enum of ADC names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_ADCName {
CC3220SF_LAUNCHXL_ADC0 = 0,
CC3220SF_LAUNCHXL_ADC1,
CC3220SF_LAUNCHXL_ADCCOUNT
} CC3220SF_LAUNCHXL_ADCName;
/*!
* @def CC3220SF_LAUNCHXL_CaptureName
* @brief Enum of Capture names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_CaptureName {
CC3220SF_LAUNCHXL_CAPTURE0 = 0,
CC3220SF_LAUNCHXL_CAPTURE1,
CC3220SF_LAUNCHXL_CAPTURECOUNT
} CC3220SF_LAUNCHXL_CaptureName;
/*!
* @def CC3220SF_LAUNCHXL_CryptoName
* @brief Enum of Crypto names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_CryptoName {
CC3220SF_LAUNCHXL_CRYPTO0 = 0,
CC3220SF_LAUNCHXL_CRYPTOCOUNT
} CC3220SF_LAUNCHXL_CryptoName;
/*!
* @def CC3220SF_LAUNCHXL_GPIOName
* @brief Enum of GPIO names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_GPIOName {
CC3220SF_LAUNCHXL_GPIO_SW2 = 0,
CC3220SF_LAUNCHXL_GPIO_SW3,
CC3220SF_LAUNCHXL_SPI_MASTER_READY,
CC3220SF_LAUNCHXL_SPI_SLAVE_READY,
CC3220SF_LAUNCHXL_GPIO_LED_D7,
/*
* CC3220SF_LAUNCHXL_GPIO_LED_D5 and CC3220SF_LAUNCHXL_GPIO_LED_D6 are shared with the
* I2C and PWM peripherals. In order for those examples to work, these
* LEDs are taken out of gpioPinCOnfig[]
*/
/* CC3220SF_LAUNCHXL_GPIO_LED_D6, */
/* CC3220SF_LAUNCHXL_GPIO_LED_D5, */
/* Sharp 96x96 LCD Pins */
CC3220SF_LAUNCHXL_LCD_CS,
CC3220SF_LAUNCHXL_LCD_POWER,
CC3220SF_LAUNCHXL_LCD_ENABLE,
CC3220SF_LAUNCHXL_GPIOCOUNT
} CC3220SF_LAUNCHXL_GPIOName;
/*!
* @def CC3220SF_LAUNCHXL_I2CName
* @brief Enum of I2C names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_I2CName {
CC3220SF_LAUNCHXL_I2C0 = 0,
CC3220SF_LAUNCHXL_I2CCOUNT
} CC3220SF_LAUNCHXL_I2CName;
/*!
* @def CC3220SF_LAUNCHXL_I2SName
* @brief Enum of I2S names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_I2SName {
CC3220SF_LAUNCHXL_I2S0 = 0,
CC3220SF_LAUNCHXL_I2SCOUNT
} CC3220SF_LAUNCHXL_I2SName;
/*!
* @def CC3220SF_LAUNCHXL_PWMName
* @brief Enum of PWM names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_PWMName {
CC3220SF_LAUNCHXL_PWM6 = 0,
CC3220SF_LAUNCHXL_PWM7,
CC3220SF_LAUNCHXL_PWMCOUNT
} CC3220SF_LAUNCHXL_PWMName;
/*!
* @def CC3220SF_LAUNCHXL_SDFatFSName
* @brief Enum of SDFatFS names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_SDFatFSName {
CC3220SF_LAUNCHXL_SDFatFS0 = 0,
CC3220SF_LAUNCHXL_SDFatFSCOUNT
} CC3220SF_LAUNCHXL_SDFatFSName;
/*!
* @def CC3220SF_LAUNCHXL_SDName
* @brief Enum of SD names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_SDName {
CC3220SF_LAUNCHXL_SD0 = 0,
CC3220SF_LAUNCHXL_SDCOUNT
} CC3220SF_LAUNCHXL_SDName;
/*!
* @def CC3220SF_LAUNCHXL_SPIName
* @brief Enum of SPI names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_SPIName {
CC3220SF_LAUNCHXL_SPI0 = 0,
CC3220SF_LAUNCHXL_SPI1,
CC3220SF_LAUNCHXL_SPICOUNT
} CC3220SF_LAUNCHXL_SPIName;
/*!
* @def CC3220SF_LAUNCHXL_TimerName
* @brief Enum of Timer names on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_TimerName {
CC3220SF_LAUNCHXL_TIMER0 = 0,
CC3220SF_LAUNCHXL_TIMER1,
CC3220SF_LAUNCHXL_TIMER2,
CC3220SF_LAUNCHXL_TIMERCOUNT
} CC3220SF_LAUNCHXL_TimerName;
/*!
* @def CC3220SF_LAUNCHXL_UARTName
* @brief Enum of UARTs on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_UARTName {
CC3220SF_LAUNCHXL_UART0 = 0,
CC3220SF_LAUNCHXL_UART1,
CC3220SF_LAUNCHXL_UARTCOUNT
} CC3220SF_LAUNCHXL_UARTName;
/*!
* @def CC3220SF_LAUNCHXL_WatchdogName
* @brief Enum of Watchdogs on the CC3220SF_LAUNCHXL dev board
*/
typedef enum CC3220SF_LAUNCHXL_WatchdogName {
CC3220SF_LAUNCHXL_WATCHDOG0 = 0,
CC3220SF_LAUNCHXL_WATCHDOGCOUNT
} CC3220SF_LAUNCHXL_WatchdogName;
/*!
* @brief Initialize the general board specific settings
*
* This function initializes the general board specific settings.
*/
extern void CC3220SF_LAUNCHXL_initGeneral(void);
#ifdef __cplusplus
}
#endif
#endif /* __CC3220SF_LAUNCHXL_H */

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/TARGET_CC3220SF_LAUNCHXL/PeripheralNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)CC3220SF_UARTA0_BASE,
UART_1 = (int)CC3220SF_UARTA1_BASE
} UARTName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3
} ADCName;
typedef enum {
PWM_1 = 1,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6
} PWMName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
#define MBED_UART0 P55, P57
#define MBED_UART1 P07, P08
#define MBED_UARTUSB USBTX, USBRX
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************GPIO***************/
const PinMap PinMap_GPIO[] = {
{PIN_50, CC3220SF_GPIOA0_BASE, 0}, //GPIO_00 (PM/Dig Mux)
{PIN_55, CC3220SF_GPIOA0_BASE, 1}, //GPIO_01
{PIN_57, CC3220SF_GPIOA0_BASE, 2}, //GPIO_02 (Dig/ADC Mux)
{PIN_58, CC3220SF_GPIOA0_BASE, 3}, //GPIO_03 (Dig/ADC Mux)
{PIN_59, CC3220SF_GPIOA0_BASE, 4}, //GPIO_04 (Dig/ADC Mux)
{PIN_60, CC3220SF_GPIOA0_BASE, 5}, //GPIO_05 (Dig/ADC Mux)
{PIN_61, CC3220SF_GPIOA0_BASE, 6}, //GPIO_06
{PIN_62, CC3220SF_GPIOA0_BASE, 7}, //GPIO_07
{PIN_63, CC3220SF_GPIOA1_BASE, 8}, //GPIO_08
{PIN_64, CC3220SF_GPIOA1_BASE, 9}, //GPIO_09
{PIN_01, CC3220SF_GPIOA1_BASE, 10}, //GPIO_10
{PIN_02, CC3220SF_GPIOA1_BASE, 11}, //GPIO_11
{PIN_03, CC3220SF_GPIOA1_BASE, 12}, //GPIO_12
{PIN_04, CC3220SF_GPIOA1_BASE, 13}, //GPIO_13
{PIN_05, CC3220SF_GPIOA1_BASE, 14}, //GPIO_14
{PIN_06, CC3220SF_GPIOA1_BASE, 15}, //GPIO_15
{PIN_07, CC3220SF_GPIOA2_BASE, 16}, //GPIO_16
{PIN_08, CC3220SF_GPIOA2_BASE, 17}, //GPIO_17
//this is only here for reference
{PIN_XX, CC3220SF_GPIOA2_BASE, 18}, //GPIO_18 (Reserved) No package pin associate with this GPIO
{PIN_XX, CC3220SF_GPIOA2_BASE, 19}, //GPIO_19 (Reserved) No package pin associate with this GPIO
{PIN_XX, CC3220SF_GPIOA2_BASE, 20}, //GPIO_20 (Reserved) No package pin associate with this GPIO
{PIN_XX, CC3220SF_GPIOA2_BASE, 21}, //GPIO_21 (Reserved) No package pin associate with this GPIO
{PIN_15, CC3220SF_GPIOA2_BASE, 22}, //GPIO_22
{PIN_16, CC3220SF_GPIOA2_BASE, 23}, //GPIO_23
{PIN_17, CC3220SF_GPIOA3_BASE, 24}, //GPIO_24
// pin 21 is one of three that must have a passive pullup or pulldown resistor
// on board to configure the chip hardware power-up mode. Because of this,
// if this pin is used for digital functions, it must be output only.
{PIN_21, CC3220SF_GPIOA3_BASE, 25}, //GPIO_25
//this is only here for reference
{PIN_XX, CC3220SF_GPIOA3_BASE, 26}, //GPIO_26 (Restricted Use; Antenna Selection 1 Only) No package pin associate with this GPIO
{PIN_XX, CC3220SF_GPIOA3_BASE, 27}, //GPIO_27 (Restricted Use; Antenna Selection 1 Only) No package pin associate with this GPIO
{PIN_18, CC3220SF_GPIOA3_BASE, 28}, //GPIO_28
{PIN_20, CC3220SF_GPIOA3_BASE, 29}, //GPIO_29
{PIN_53, CC3220SF_GPIOA3_BASE, 30}, //GPIO_30 (PM/Dig Mux)
{PIN_45, CC3220SF_GPIOA3_BASE, 31}, //GPIO_31 (PM/Dig Mux)
{NC, NC, 0}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{PIN_01, PWM_1, 3},
{PIN_02, PWM_2, 3},
{PIN_17, PWM_3, 5},
{PIN_19, PWM_4, 8},
{PIN_21, PWM_5, 9},
{PIN_64, PWM_6, 3},
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{PIN_01, UART_1, 7},
{PIN_03, UART_0, 7},
{PIN_07, UART_1, 5},
{PIN_16, UART_1, 2},
{PIN_53, UART_0, 9},
{PIN_55, UART_0, 3},
{PIN_55, UART_1, 6},
{PIN_58, UART_1, 6},
{PIN_62, UART_0, 11},
{NC, NC, 0}
};
const PinMap PinMap_UART_RX[] = {
{PIN_02, UART_1, 7},
{PIN_04, UART_0, 7},
{PIN_08, UART_1, 5},
{PIN_17, UART_1, 2},
{PIN_45, UART_0, 9},
{PIN_45, UART_1, 2},
{PIN_57, UART_0, 3},
{PIN_57, UART_1, 6},
{PIN_59, UART_1, 6},
{NC, NC, 0}
};
const PinMap PinMap_UART_RTS[] = {
{PIN_50, UART_0, 3},
{PIN_50, UART_1, 10},
{PIN_52, UART_0, 6},
{PIN_61, UART_0, 5},
{PIN_62, UART_0, 10},
{PIN_62, UART_1, 3},
{NC, NC, 0}
};
const PinMap PinMap_UART_CTS[] = {
{PIN_50, UART_0, 12},
{PIN_61, UART_0, 6},
{PIN_61, UART_1, 3},
{NC, NC, 0}
};

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
P01 = 0x00000000,
P02 = 0x00000001,
P03 = 0x00000002,
P04 = 0x00000003,
P05 = 0x00000004,
P06 = 0x00000005,
P07 = 0x00000006,
P08 = 0x00000007,
P11 = 0x0000000A,
P12 = 0x0000000B,
P13 = 0x0000000C,
P14 = 0x0000000D,
P15 = 0x0000000E,
P16 = 0x0000000F,
P17 = 0x00000010,
P18 = 0x00000011,
P19 = 0x00000012,
P20 = 0x00000013,
P21 = 0x00000014,
P29 = 0x0000001C,
P30 = 0x0000001D,
P45 = 0x0000002C,
P46 = 0x0000002D,
P47 = 0x0000002E,
P48 = 0x0000002F,
P49 = 0x00000030,
P50 = 0x00000031,
P52 = 0x00000033,
P53 = 0x00000034,
P55 = 0x00000036,
P56 = 0x00000037,
P57 = 0x00000038,
P58 = 0x00000039,
P59 = 0x0000003A,
P60 = 0x0000003B,
P61 = 0x0000003C,
P62 = 0x0000003D,
P63 = 0x0000003E,
P64 = 0x0000003F,
PIN_01 = P01,
PIN_02 = P02,
PIN_03 = P03,
PIN_04 = P04,
PIN_05 = P05,
PIN_06 = P06,
PIN_07 = P07,
PIN_08 = P08,
PIN_11 = P11,
PIN_12 = P12,
PIN_13 = P13,
PIN_14 = P14,
PIN_15 = P15,
PIN_16 = P16,
PIN_17 = P17,
PIN_18 = P18,
PIN_19 = P19,
PIN_20 = P20,
PIN_21 = P21,
PIN_29 = P29,
PIN_30 = P30,
PIN_45 = P45,
PIN_46 = P46,
PIN_47 = P47,
PIN_48 = P48,
PIN_49 = P49,
PIN_50 = P50,
PIN_52 = P52,
PIN_53 = P53,
PIN_55 = P55,
PIN_56 = P56,
PIN_57 = P57,
PIN_58 = P58,
PIN_59 = P59,
PIN_60 = P60,
PIN_61 = P61,
PIN_62 = P62,
PIN_63 = P63,
PIN_64 = P64,
//LED 1 => RED, LED 2 => YELLOW, LED 3 = GREEN
LED1 = PIN_64,
LED2 = PIN_01,
LED3 = PIN_02,
LED_RED = LED1,
LED_YELLOW = LED2,
LED_GREEN = LED3,
// UART0
USBTX = PIN_55,
USBRX = PIN_57,
//Button
BUTTON1 = PIN_04,
BUTTON2 = PIN_15,
//SPI1
SPICC32XXDMA_MOSI = P07,
SPICC32XXDMA_MISO = P06,
SPICC32XXDMA_CLK = P05,
SPICC32XXDMA_CS = P08,
// CI Shield
D10 = SPICC32XXDMA_CS,
D11 = SPICC32XXDMA_MOSI,
D12 = SPICC32XXDMA_MISO,
D13 = SPICC32XXDMA_CLK,
// Not connected
NC = (int)0xFFFFFFFF,
PIN_RESERVED = NC,
PIN_XX = NC
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
OpenDrain = 3,
OpenDrainPullUp = 4,
OpenDrainPullDown = 5,
Analog = 6,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<configurations XML_version="1.2" id="configurations_0">
<configuration XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
<instance XML_version="1.2" desc="Texas Instruments XDS110 USB Debug Probe_0" href="connections/TIXDS110_Connection.xml" id="Texas Instruments XDS110 USB Debug Probe_0" xml="TIXDS110_Connection.xml" xmlpath="connections"/>
<connection XML_version="1.2" id="Texas Instruments XDS110 USB Debug Probe_0">
<instance XML_version="1.2" href="drivers/tixds510icepick_c.xml" id="drivers" xml="tixds510icepick_c.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cs_dap.xml" id="drivers" xml="tixds510cs_dap.xml" xmlpath="drivers"/>
<instance XML_version="1.2" href="drivers/tixds510cortexM.xml" id="drivers" xml="tixds510cortexM.xml" xmlpath="drivers"/>
<platform XML_version="1.2" id="platform_0">
<instance XML_version="1.2" desc="CC3220SF_0" href="devices/CC3220SF.xml" id="CC3220SF_0" xml="CC3220SF.xml" xmlpath="devices"/>
</platform>
</connection>
</configuration>
</configurations>

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogin_api.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "PinNames.h"
#include "cmsis.h"
#include <ti/devices/cc32xx/inc/hw_types.h>
#include <ti/devices/cc32xx/driverlib/adc.h>
#include <ti/devices/cc32xx/driverlib/prcm.h>
#include <ti/devices/cc32xx/driverlib/pin.h>
#include <ti/devices/cc32xx/inc/hw_memmap.h>
#define ADC_DATA_MASK 0x3FFC //the data is from bit [13:2]
#define ADC_RESOLUTION 0xFFF
void analogin_init(analogin_t *obj, PinName pin) {
ADCEnable(CC3220SF_ADC_BASE);
obj->pin = pin;
pin_mode(pin, Analog);
switch(pin){
case PIN_57:obj->adc_ch = ADC_CH_0;break;
case PIN_58:obj->adc_ch = ADC_CH_1;break;
case PIN_59:obj->adc_ch = ADC_CH_2;break;
case PIN_60:obj->adc_ch = ADC_CH_3;break;
default: MBED_ASSERT(NC != (PinName)NC);
}
ADCChannelEnable(CC3220SF_ADC_BASE, obj->adc_ch);
}
uint16_t analogin_read_u16(analogin_t *obj) {
unsigned long adc_raw = ADCFIFORead(CC3220SF_ADC_BASE, obj->adc_ch);
return (uint16_t) ((adc_raw & ADC_DATA_MASK) >> 2);
}
float analogin_read(analogin_t *obj) {
uint16_t value = analogin_read_u16(obj);
return (float)value * (1.0f / (float)ADC_RESOLUTION);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

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/**************************************************************************//**
* @file CC3220SF.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
* Device CC3220SF
* @version V5.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef CC3220SF_H
#define CC3220SF_H
#ifdef __cplusplus
extern "C" {
#endif
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
// mbed-os core_cm4.h adds offset of 16. Deduct 16 from the IRQ enums
#define INT_IRQn_OFFSET 16
typedef enum IRQn
{
/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation
and No Match */
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
related Fault */
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* =========================================== CC3220SF Specific Interrupt Numbers ========================================= */
INT_GPIOA0_IRQn = 16 - INT_IRQn_OFFSET, // GPIO Port S0
INT_GPIOA1_IRQn = 17 - INT_IRQn_OFFSET, // GPIO Port S1
INT_GPIOA2_IRQn = 18 - INT_IRQn_OFFSET, // GPIO Port S2
INT_GPIOA3_IRQn = 19 - INT_IRQn_OFFSET, // GPIO Port S3
INT_UARTA0_IRQn = 21 - INT_IRQn_OFFSET, // UART0 Rx and Tx
INT_UARTA1_IRQn = 22 - INT_IRQn_OFFSET, // UART1 Rx and Tx
INT_I2CA0_IRQn = 24 - INT_IRQn_OFFSET, // I2C controller
INT_ADCCH0_IRQn = 30 - INT_IRQn_OFFSET, // ADC Sequence 0
INT_ADCCH1_IRQn = 31 - INT_IRQn_OFFSET, // ADC Sequence 1
INT_ADCCH2_IRQn = 32 - INT_IRQn_OFFSET, // ADC Sequence 2
INT_ADCCH3_IRQn = 33 - INT_IRQn_OFFSET, // ADC Sequence 3
INT_WDT_IRQn = 34 - INT_IRQn_OFFSET, // Watchdog Timer0
INT_TIMERA0A_IRQn = 35 - INT_IRQn_OFFSET, // Timer 0 subtimer A
INT_TIMERA0B_IRQn = 36 - INT_IRQn_OFFSET, // Timer 0 subtimer B
INT_TIMERA1A_IRQn = 37 - INT_IRQn_OFFSET, // Timer 1 subtimer A
INT_TIMERA1B_IRQn = 38 - INT_IRQn_OFFSET, // Timer 1 subtimer B
INT_TIMERA2A_IRQn = 39 - INT_IRQn_OFFSET, // Timer 2 subtimer A
INT_TIMERA2B_IRQn = 40 - INT_IRQn_OFFSET, // Timer 2 subtimer B
INT_FLASH_IRQn = 45 - INT_IRQn_OFFSET, // FLASH Control
INT_TIMERA3A_IRQn = 51 - INT_IRQn_OFFSET, // Timer 3 subtimer A
INT_TIMERA3B_IRQn = 52 - INT_IRQn_OFFSET, // Timer 3 subtimer B
INT_UDMA_IRQn = 62 - INT_IRQn_OFFSET, // uDMA controller
INT_UDMAERR_IRQn = 63 - INT_IRQn_OFFSET, // uDMA Error
INT_SHA_IRQn = 164 - INT_IRQn_OFFSET, // SHA
INT_AES_IRQn = 167 - INT_IRQn_OFFSET, // AES
INT_DES_IRQn = 169 - INT_IRQn_OFFSET, // DES
INT_MMCHS_IRQn = 175 - INT_IRQn_OFFSET, // SDIO
INT_I2S_IRQn = 177 - INT_IRQn_OFFSET, // McAPS
INT_CAMERA_IRQn = 179 - INT_IRQn_OFFSET, // Camera
INT_NWPIC_IRQn = 187 - INT_IRQn_OFFSET, // Interprocessor communication
INT_PRCM_IRQn = 188 - INT_IRQn_OFFSET, // Power, Reset and Clock Module
INT_SSPI_IRQn = 191 - INT_IRQn_OFFSET, // Shared SPI
INT_GSPI_IRQn = 192 - INT_IRQn_OFFSET, // Generic SPI
INT_LSPI_IRQn = 193 - INT_IRQn_OFFSET // Link SPI
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
/* =========================== Configuration of the Arm Cortex-M4 Processor and Core Peripherals =========================== */
#define __CM4_REV 0x0201 /*!< Core Revision r2p1 */
/* ToDo: define the correct core features for the CC3220SF */
#define __MPU_PRESENT 1 /*!< Set to 1 if MPU is present */
#define __VTOR_PRESENT 1 /*!< Set to 1 if VTOR is present */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0 /*!< Set to 1 if FPU is present */
#define __FPU_DP 0 /*!< Set to 1 if FPU is double precision FPU (default is single precision FPU) */
#define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */
#define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */
#define __DTCM_PRESENT 0 /*!< Set to 1 if DTCM is present */
/** @} */ /* End of group Configuration_of_CMSIS */
#include <core_cm4.h> /*!< Arm Cortex-M4 processor and core peripherals */
#include "system_CC3220SF.h" /*!< CC3220SF System */
/* ======================================== Start of section using anonymous unions ======================================== */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */
/* =========================================================================================================================== */
/* ================ GPIO ================ */
/* =========================================================================================================================== */
/**
* @brief GPIO
*/
typedef struct
{
__IO uint32_t DATA; /*!< Address offset : 0x00000000 */
uint32_t RESERVED0[255];
__IO uint32_t DIR; /*!< Address offset : 0x00000400 */
__IO uint32_t IS; /*!< Address offset : 0x00000404 */
__IO uint32_t IBE; /*!< Address offset : 0x00000408 */
__IO uint32_t IEV; /*!< Address offset : 0x0000040C */
__IO uint32_t IM; /*!< Address offset : 0x00000410 */
__IO uint32_t RIS; /*!< Address offset : 0x00000414 */
__IO uint32_t MIS; /*!< Address offset : 0x00000418 */
__O uint32_t ICR; /*!< Address offset : 0x0000041C */
__IO uint32_t AFSEL; /*!< Address offset : 0x00000420 */
uint32_t RESERVED1[55];
__IO uint32_t DR2R; /*!< Address offset : 0x00000500 */
__IO uint32_t DR4R; /*!< Address offset : 0x00000504 */
__IO uint32_t DR8R; /*!< Address offset : 0x00000508 */
__IO uint32_t ODR; /*!< Address offset : 0x0000050C */
__IO uint32_t PUR; /*!< Address offset : 0x00000510 */
__IO uint32_t PDR; /*!< Address offset : 0x00000514 */
__IO uint32_t SLR; /*!< Address offset : 0x00000518 */
__IO uint32_t DEN; /*!< Address offset : 0x0000051C */
__IO uint32_t LOCK; /*!< Address offset : 0x00000520 */
__IO uint32_t CR; /*!< Address offset : 0x00000524 */
__IO uint32_t AMSEL; /*!< Address offset : 0x00000528 */
__IO uint32_t PCTL; /*!< Address offset : 0x0000052C ! This register is not used in cc3xx. ! */
__IO uint32_t ADCCTL; /*!< Address offset : 0x00000530 ! This register is not used in cc3xx. ! */
__IO uint32_t DMACTL; /*!< Address offset : 0x00000534 */
__IO uint32_t SI; /*!< Address offset : 0x00000538 */
uint32_t RESERVED2[677];
__IO uint32_t PERIPHID4; /*!< Address offset : 0x00000FD0 */
__IO uint32_t PERIPHID5; /*!< Address offset : 0x00000FD4 */
__IO uint32_t PERIPHID6; /*!< Address offset : 0x00000FD8 */
__IO uint32_t PERIPHID7; /*!< Address offset : 0x00000FDC */
__IO uint32_t PERIPHID0; /*!< Address offset : 0x00000FE0 */
__IO uint32_t PERIPHID1; /*!< Address offset : 0x00000FE4 */
__IO uint32_t PERIPHID2; /*!< Address offset : 0x00000FE8 */
__IO uint32_t PERIPHID3; /*!< Address offset : 0x00000FEC */
__IO uint32_t PCELLID0; /*!< Address offset : 0x00000FF0 */
__IO uint32_t PCELLID1; /*!< Address offset : 0x00000FF4 */
__IO uint32_t PCELLID2; /*!< Address offset : 0x00000FF8 */
__IO uint32_t PCELLID3; /*!< Address offset : 0x00000FFC */
} CC3220SF_GPIO_TypeDef;
/* =========================================================================================================================== */
/* ================ UART ================ */
/* =========================================================================================================================== */
/**
* @brief UART
*/
typedef struct
{
__IO uint32_t DR; /*!< Data, Address offset : 0x00 */
union {
__I uint32_t RSR; /*!< Receive Status, Address offset : 0x04 */
__O uint32_t ECR; /*!< Error Clear, Address offset : 0x04 */
};
uint32_t RESERVED0[4];
__IO uint32_t FR; /*!< Flags, Address offset : 0x18 */
uint32_t RESERVED1[1];
__IO uint32_t ILPR; /*!< IrDA Low-power Counter, Address offset : 0x20 */
__IO uint32_t IBRD; /*!< Integer Baud Rate, Address offset : 0x24 */
__IO uint32_t FBRD; /*!< Fractional Baud Rate, Address offset : 0x28 */
__IO uint32_t LCRH; /*!< Line Control, Address offset : 0x2C */
__IO uint32_t CTL; /*!< Control, Address offset : 0x30 */
__IO uint32_t IFLS; /*!< Interrupt FIFO Level Select, Address offset : 0x34 */
__IO uint32_t IM; /*!< Interrupt Mask Set / Clear, Address offset : 0x38 */
__IO uint32_t RIS; /*!< Raw Interrupt Status , Address offset : 0x3C */
__IO uint32_t MIS; /*!< Masked Interrupt Status , Address offset : 0x40 */
__O uint32_t ICR; /*!< Interrupt Clear, Address offset : 0x44 */
__IO uint32_t DMACTL; /*!< DMA Control, Address offset : 0x48 */
__IO uint32_t LCTL; /*!< Address offset : 0x90 */
__IO uint32_t LSS; /*!< Address offset : 0x94 */
__IO uint32_t LTIM; /*!< Address offset : 0x98 */
__IO uint32_t BITADDR; /*!< 9BITADDR Address offset : 0xA4 */
__IO uint32_t BITMASK; /*!< 9BITMASK Address offset : 0xA8 */
__IO uint32_t PP; /*!< Address offset : 0xFC0 */
__IO uint32_t CC; /*!< Address offset : 0xFC8 */
} CC3220SF_UART_TypeDef;
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */
/** @addtogroup Peripheral_memory_map
* @{
*/
/* Peripheral and SRAM base address */
#define CC3220SF_FLASH_BASE 0x01000000
#define CC3220SF_SRAM_BASE 0x20000000
#define CC3220SF_WDT_BASE 0x40000000
#define CC3220SF_GPIOA0_BASE 0x40004000
#define CC3220SF_GPIOA1_BASE 0x40005000
#define CC3220SF_GPIOA2_BASE 0x40006000
#define CC3220SF_GPIOA3_BASE 0x40007000
#define CC3220SF_GPIOA4_BASE 0x40024000
#define CC3220SF_UARTA0_BASE 0x4000C000
#define CC3220SF_UARTA1_BASE 0x4000D000
#define CC3220SF_I2CA0_BASE 0x40020000
#define CC3220SF_TIMERA0_BASE 0x40030000
#define CC3220SF_TIMERA1_BASE 0x40031000
#define CC3220SF_TIMERA2_BASE 0x40032000
#define CC3220SF_TIMERA3_BASE 0x40033000
#define CC3220SF_STACKDIE_CTRL_BASE 0x400F5000
#define CC3220SF_COMMON_REG_BASE 0x400F7000
#define CC3220SF_FLASH_CONTROL_BASE 0x400FD000
#define CC3220SF_SYSTEM_CONTROL_BASE 0x400FE000
#define CC3220SF_UDMA_BASE 0x400FF000
#define CC3220SF_SDHOST_BASE 0x44010000
#define CC3220SF_CAMERA_BASE 0x44018000
#define CC3220SF_I2S_BASE 0x4401C000
#define CC3220SF_SSPI_BASE 0x44020000
#define CC3220SF_GSPI_BASE 0x44021000
#define CC3220SF_LSPI_BASE 0x44022000
#define CC3220SF_ARCM_BASE 0x44025000
#define CC3220SF_APPS_CONFIG_BASE 0x44026000
#define CC3220SF_GPRCM_BASE 0x4402D000
#define CC3220SF_OCP_SHARED_BASE 0x4402E000
#define CC3220SF_ADC_BASE 0x4402E800
#define CC3220SF_HIB1P2_BASE 0x4402F000
#define CC3220SF_HIB3P3_BASE 0x4402F800
#define CC3220SF_DTHE_BASE 0x44030000
#define CC3220SF_SHAMD5_BASE 0x44035000
#define CC3220SF_AES_BASE 0x44037000
#define CC3220SF_DES_BASE 0x44039000
/**
* @}
*/
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/** @addtogroup Peripheral_declaration
* @{
*/
/******************************************************************************/
/* */
/* GPIO */
/* */
/******************************************************************************/
#define CC3220SF_GPIO0 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA0_BASE)
#define CC3220SF_GPIO1 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA1_BASE)
#define CC3220SF_GPIO2 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA2_BASE)
#define CC3220SF_GPIO3 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA3_BASE)
#define CC3220SF_GPIO4 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA4_BASE)
/******************************************************************************/
/* */
/* UART */
/* */
/******************************************************************************/
#define CC3220SF_UART0 ((CC3220SF_UART_TypeDef *) CC3220SF_UARTA0_BASE)
#define CC3220SF_UART1 ((CC3220SF_UART_TypeDef *) CC3220SF_UARTA1_BASE)
/**
* @}
*/
/* ========================================= End of section using anonymous unions ========================================= */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
#ifdef __cplusplus
}
#endif
#endif /* CC3220SF_H */

160
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.cpp Executable file
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/* CC3220SF_Init.cpp
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <assert.h>
#include "nsapi_types.h"
#include "ti/drivers/net/wifi/netcfg.h"
#include "ti/drivers/ti_SPI.h"
#include "ti/drivers/dma/UDMACC32XX.h"
#include "ti/drivers/net/wifi/sl_socket.h"
#include "ti/drivers/net/wifi/netapp.h"
#include "ti/drivers/net/wifi/wlan.h"
#include "mbed.h"
#include "cc3200_simplelink.h"
#include "CC3220SF_Init.h"
#define CHANNEL_MASK_ALL (0x1FFF)
#define RSSI_TH_MAX (-95)
#define TASK_STACK_SIZE (2048)
/* The SimpleLink host driver architecture mandate spawn thread to be created prior to calling Sl_start (turning the NWP on). */
/* The purpose of this thread is to handle asynchronous events sent from the NWP.
* Every event is classified and later handled by the Host driver event handlers. */
Thread sl_Task_thread(osPriorityNormal, TASK_STACK_SIZE, NULL, "sl_task_thread");
Mutex sl_init_mutex;
void sl_task_entry()
{
sl_Task(NULL);
}
int CC3220SF_initSimplelink(void)
{
uint8_t ucConfigOpt;
uint8_t ucPower;
int32_t RetVal = -1;
int32_t Mode = -1;
uint32_t IfBitmap = 0;
SlWlanScanParamCommand_t ScanDefault = {0};
SlWlanRxFilterOperationCommandBuff_t RxFilterIdMask = {{0}};
static bool simplelink_powered = false;
sl_init_mutex.lock();
if (!simplelink_powered)
{
if (sl_Task_thread.start(callback(sl_task_entry)) != osOK)
{
printf("sl_Task failed\n");
sl_init_mutex.unlock();
return -1;
}
UDMACC32XX_init();
SPI_init();
/* Turn NWP on */
Mode = sl_Start(0, 0, 0);
if(Mode != ROLE_STA)
{
/* Set NWP role as STA */
RetVal = sl_WlanSetMode(ROLE_STA);
assert(RetVal == 0);
/* For changes to take affect, we restart the NWP */
RetVal = sl_Stop(0);
assert(RetVal == 0);
Mode = sl_Start(0, 0, 0);
assert(RetVal == 0);
}
if(Mode != ROLE_STA)
{
printf("Failed to configure device to it's default state");
sl_init_mutex.unlock();
return -1;
}
/* Set policy to auto only */
RetVal = sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION, SL_WLAN_CONNECTION_POLICY(1,0,0,0), NULL ,0);
assert(RetVal == 0);
/* Disable Auto Provisioning */
RetVal = sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_STOP, 0xFF, 0, NULL, 0x0);
assert(RetVal == 0);
/* Delete existing profiles */
RetVal = sl_WlanProfileDel(0xFF);
assert(RetVal == 0);
/* enable DHCP client */
RetVal = sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE, SL_NETCFG_ADDR_DHCP, 0, 0);
assert(RetVal == 0);
/* Disable ipv6 */
IfBitmap = !(SL_NETCFG_IF_IPV6_STA_LOCAL | SL_NETCFG_IF_IPV6_STA_GLOBAL);
RetVal = sl_NetCfgSet(SL_NETCFG_IF, SL_NETCFG_IF_STATE, sizeof(IfBitmap),(const unsigned char *)&IfBitmap);
assert(RetVal == 0);
/* Configure scan parameters to default */
ScanDefault.ChannelsMask = CHANNEL_MASK_ALL;
ScanDefault.RssiThreshold = RSSI_TH_MAX;
RetVal = sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS, sizeof(ScanDefault), (uint8_t *)&ScanDefault);
assert(RetVal == 0);
/* Disable scans */
ucConfigOpt = SL_WLAN_SCAN_POLICY(0, 0);
RetVal = sl_WlanPolicySet(SL_WLAN_POLICY_SCAN , ucConfigOpt, NULL, 0);
assert(RetVal == 0);
/* Set TX power lvl to max */
ucPower = 0;
RetVal = sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER, 1, (uint8_t *)&ucPower);
assert(RetVal == 0);
/* Set NWP Power policy to 'normal' */
RetVal = sl_WlanPolicySet(SL_WLAN_POLICY_PM, SL_WLAN_NORMAL_POLICY, NULL, 0);
assert(RetVal == 0);
/* Unregister mDNS services */
RetVal = sl_NetAppMDNSUnRegisterService(0, 0, 0);
assert(RetVal == 0);
/* Remove all 64 RX filters (8*8) */
memset(RxFilterIdMask.FilterBitmap , 0xFF, 8);
RetVal = sl_WlanSet(SL_WLAN_RX_FILTERS_ID, SL_WLAN_RX_FILTER_REMOVE, sizeof(SlWlanRxFilterOperationCommandBuff_t),(uint8_t *)&RxFilterIdMask);
assert(RetVal == 0);
/* Set NWP role as STA */
RetVal = sl_WlanSetMode(ROLE_STA);
assert(RetVal == 0);
/* For changes to take affect, we restart the NWP */
RetVal = sl_Stop(0/*SL_STOP_TIMEOUT*/);
assert(RetVal == 0);
Mode = sl_Start(0, 0, 0);
if(ROLE_STA != Mode)
{
printf("Failed to configure device to its default state\n");
sl_init_mutex.unlock();
return -1;
}
simplelink_powered = true;
}
sl_init_mutex.unlock();
return 0;
}

30
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_Init.h Executable file
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/* CC3220SF_Init.h
*
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CC3220SF_INIT_H
#define __CC3220SF_INIT_H
#ifdef __cplusplus
extern "C" {
#endif
int CC3220SF_initSimplelink(void);
#ifdef __cplusplus
}
#endif
#endif /* __CC3220SF_INIT_H */

674
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF_WiFiInterface.cpp Normal file
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/* CC3220SF implementation of NetworkInterfaceAPI
* Copyright (c) 2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "cc3200_simplelink.h"
#include "CC3220SF_WiFiInterface.h"
#define CONNECT_TIMEOUT_MS (4000)
#define IP_SET_TIMEOUT_MS (2000)
#define READ_THREAD_SLEEP_MS (50)
#define SOCKET_TASK_STACK_SIZE (2048)
CC3220SFInterface * CC3220SFInterface::cc3200sf_wifi_instance;
CC3220SFInterface::CC3220SFInterface():
_thread_read_socket(osPriorityNormal, SOCKET_TASK_STACK_SIZE, NULL, "read_socket_thread"),
_initialized(false),
_started(false),
_channel(6),
_connect_sem(0, 1),
_ip_set_sem(0, 1)
{
memset(_id_in_use, 0, sizeof(_id_in_use));
memset(_socket_obj, 0, sizeof(_socket_obj));
memset(_cbs, 0, sizeof(_cbs));
memset(_ssid, 0, sizeof(_ssid));
memset(_pass, 0, sizeof(_pass));
_security = NSAPI_SECURITY_UNKNOWN;
cc3200sf_wifi_instance = this;
_cc3200_simplelink.initialize();
_thread_read_socket.start(callback(this, &CC3220SFInterface::_socket_background_thread));
}
nsapi_error_t CC3220SFInterface::connect(const char *ssid, const char *pass, nsapi_security_t security,
uint8_t channel)
{
nsapi_error_t ret_code;
ret_code = set_credentials(ssid, pass, security);
if(ret_code)
{
printf ("set_credentials failed with 0x%x\n", ret_code);
return ret_code;
}
return connect();
}
nsapi_error_t CC3220SFInterface::connect()
{
nsapi_error_t status;
if (strlen(_ssid) == 0)
{
return NSAPI_ERROR_NO_SSID;
}
if(get_ip_address())
{
return NSAPI_ERROR_IS_CONNECTED;
}
_cc3200_simplelink.set_connection_status(NSAPI_STATUS_CONNECTING);
status = _startup(CC3200_SIMPLELINK::WIFI_ROLE_STATION);
if(status != NSAPI_ERROR_OK)
{
return status;
}
_started = true;
if (!_cc3200_simplelink.dhcp(true, CC3200_SIMPLELINK::WIFI_ROLE_STATION))
{
return NSAPI_ERROR_DHCP_FAILURE;
}
int connect_error = _cc3200_simplelink.connect(_ssid, _pass, _security);
if (connect_error)
{
return connect_error;
}
// Connect is async call. Wait till connection completes
if (_connect_sem.try_acquire_for(CONNECT_TIMEOUT_MS) == false)
{
printf("Connection timed out\n");
return NSAPI_ERROR_CONNECTION_TIMEOUT;
}
if (_ip_set_sem.try_acquire_for(IP_SET_TIMEOUT_MS) == false)
{
printf("IP address set timed out\n");
}
else
{
_cc3200_simplelink.set_connection_status(NSAPI_STATUS_GLOBAL_UP);
}
if (!get_ip_address())
{
return NSAPI_ERROR_DHCP_FAILURE;
}
return NSAPI_ERROR_OK;
}
nsapi_error_t CC3220SFInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security)
{
if (!ssid) {
return NSAPI_ERROR_PARAMETER;
}
if ((strlen(ssid) == 0) || (strlen(ssid) > 32)) {
return NSAPI_ERROR_PARAMETER;
}
if ((security != NSAPI_SECURITY_NONE) && (strcmp(pass, "") == 0)) {
return NSAPI_ERROR_PARAMETER;
}
switch (security)
{
case NSAPI_SECURITY_WPA:
case NSAPI_SECURITY_WPA2:
case NSAPI_SECURITY_WPA_WPA2:
case NSAPI_SECURITY_WEP:
if ((strlen(pass) < 8) || (strlen(pass) > 63)) { // 802.11 password 8-63 characters
return NSAPI_ERROR_PARAMETER;
}
break;
case NSAPI_SECURITY_NONE:
break;
default:
return NSAPI_ERROR_PARAMETER;
}
if (security != NSAPI_SECURITY_NONE)
{
if(!pass)
{
return NSAPI_ERROR_PARAMETER;
}
}
strncpy(_ssid, ssid, sizeof(_ssid));
strncpy(_pass, pass, sizeof(_pass));
_security = security;
return NSAPI_ERROR_OK;
}
nsapi_error_t CC3220SFInterface::set_channel(uint8_t channel)
{
return NSAPI_ERROR_UNSUPPORTED;
}
nsapi_error_t CC3220SFInterface::disconnect()
{
nsapi_error_t status;
_started = false;
_initialized = false;
if (_cc3200_simplelink.disconnect())
{
status = NSAPI_ERROR_OK;
_cc3200_simplelink.set_connection_status(NSAPI_STATUS_DISCONNECTED);
}
else
{
status = NSAPI_ERROR_DEVICE_ERROR;
}
return status;
}
const char *CC3220SFInterface::get_ip_address()
{
if(!_started) {
return NULL;
}
const char *ip_buff = _cc3200_simplelink.getIPAddress();
if(!ip_buff || std::strcmp(ip_buff, "0.0.0.0") == 0) {
return NULL;
}
return ip_buff;
}
const char *CC3220SFInterface::get_mac_address()
{
return _cc3200_simplelink.getMACAddress();
}
const char *CC3220SFInterface::get_gateway()
{
return _started ? _cc3200_simplelink.getGateway() : NULL;
}
const char *CC3220SFInterface::get_netmask()
{
return _started ? _cc3200_simplelink.getNetmask() : NULL;
}
int8_t CC3220SFInterface::get_rssi()
{
return _started ? _cc3200_simplelink.getRSSI() : 0;
}
int CC3220SFInterface::scan(WiFiAccessPoint *res, unsigned count)
{
nsapi_error_t status;
status = _startup(CC3200_SIMPLELINK::WIFI_ROLE_STATION);
if(status != NSAPI_ERROR_OK) {
return status;
}
return _cc3200_simplelink.scan(res, count);
}
nsapi_error_t CC3220SFInterface::_startup(const int8_t wifi_mode)
{
if (!_started) {
if (!_cc3200_simplelink.startup(wifi_mode)) {
return NSAPI_ERROR_DEVICE_ERROR;
}
}
return NSAPI_ERROR_OK;
}
void CC3220SFInterface::attach(mbed::Callback<void(nsapi_event_t, intptr_t)> status_cb)
{
_cc3200_simplelink.attach(status_cb);
}
nsapi_connection_status_t CC3220SFInterface::get_connection_status() const
{
return _cc3200_simplelink.get_connection_status();
}
nsapi_error_t CC3220SFInterface::socket_open(void **handle, nsapi_protocol_t proto)
{
int32_t sd, i, ret = NSAPI_ERROR_PARAMETER;
if (!handle)
{
return ret;
}
_mutex.lock();
for (i = 0; i < CC3220SF_SOCKET_COUNT; i++) {
if (_id_in_use[i] == false)
{
_id_in_use[i] = true;
break;
}
}
if (i == CC3220SF_SOCKET_COUNT) {
_mutex.unlock();
return NSAPI_ERROR_NO_SOCKET;
}
struct cc3200_socket *socket = new struct cc3200_socket;
if (!socket)
{
_mutex.unlock();
return NSAPI_ERROR_NO_SOCKET;
}
sd = _cc3200_simplelink.open_socket(proto);
if (sd >= 0) // socket open succeeded
{
socket->id = i;
socket->sd = sd;
socket->proto = proto;
socket->connected = false;
socket->read_data_available = 0;
socket->data_to_read = 0;
socket->callback_pending = false;
*handle = socket;
_socket_obj[i] = (void *)socket;
ret = NSAPI_ERROR_OK;
}
else
{
delete socket;
*handle = NULL;
ret = NSAPI_ERROR_NO_SOCKET;
}
_mutex.unlock();
return ret;
}
nsapi_error_t CC3220SFInterface::socket_close(void *handle)
{
struct cc3200_socket *socket = (struct cc3200_socket *)handle;
int err = NSAPI_ERROR_OK;
if (!socket) {
return NSAPI_ERROR_NO_SOCKET;
}
_mutex.lock();
if (!_cc3200_simplelink.close_socket(socket->sd))
{
err = NSAPI_ERROR_DEVICE_ERROR;
}
socket->connected = false;
socket->callback_pending = false;
_id_in_use[socket->id] = false;
_socket_obj[socket->id] = 0;
_mutex.unlock();
delete socket;
return err;
}
#if 0
nsapi_error_t CC3220SFInterface::gethostbyname(const char *name, SocketAddress *address, nsapi_version_t version)
{
nsapi_addr_t ip_address;
ip_address.version = NSAPI_IPv4;
if (_cc3200_simplelink.dns_lookup(name, (char*)ip_address.bytes, sizeof(ip_address.bytes), version) == NSAPI_ERROR_OK)
{
address->set_addr(ip_address);
return NSAPI_ERROR_OK;
}
else
{
return NSAPI_ERROR_DNS_FAILURE;
}
}
#endif
nsapi_error_t CC3220SFInterface::get_dns_server(int index, SocketAddress *address, const char *interface_name)
{
nsapi_addr_t dns_address;
dns_address.version = NSAPI_IPv4;
if (_cc3200_simplelink.getDNS(dns_address.bytes, sizeof(dns_address.bytes)) == NSAPI_ERROR_OK)
{
address->set_addr(dns_address);
return NSAPI_ERROR_OK;
}
else
{
return NSAPI_ERROR_DNS_FAILURE;
}
}
nsapi_error_t CC3220SFInterface::setsockopt(nsapi_socket_t handle, int level,
int optname, const void *optval, unsigned optlen)
{
struct cc3200_socket *socket = (struct cc3200_socket *)handle;
if (!socket)
{
return NSAPI_ERROR_NO_SOCKET;
}
_mutex.lock();
nsapi_error_t retcode = _cc3200_simplelink.setsockopt(socket->sd, level, optname, optval, optlen);
_mutex.unlock();
return retcode;
}
nsapi_error_t CC3220SFInterface::getsockopt(nsapi_socket_t handle, int level, int optname,
void *optval, unsigned *optlen)
{
struct cc3200_socket *socket = (struct cc3200_socket *)handle;
if (!socket)
{
return NSAPI_ERROR_NO_SOCKET;
}
_mutex.lock();
nsapi_error_t retcode = _cc3200_simplelink.getsockopt(socket->sd, level, optname, optval, optlen);
_mutex.unlock();
return retcode;
}
int CC3220SFInterface::socket_bind(void *handle, const SocketAddress &address)
{
struct cc3200_socket *socket = (struct cc3200_socket *)handle;
if (!socket)
{
return NSAPI_ERROR_NO_SOCKET;
}
_mutex.lock();
int ret = _cc3200_simplelink.bind_socket(socket->sd, address);
_mutex.unlock();
return ret;
}
int CC3220SFInterface::socket_listen(void *handle, int backlog)
{
return NSAPI_ERROR_UNSUPPORTED;
}
int CC3220SFInterface::socket_connect(void *handle, const SocketAddress &addr)
{
struct cc3200_socket *socket = (struct cc3200_socket *)handle;
if (!socket)
{
return NSAPI_ERROR_NO_SOCKET;
}
_mutex.lock();
int ret;
if (_cc3200_simplelink.connect_socket(socket->sd, addr) == NSAPI_ERROR_OK)
{
socket->connected= true;
ret = NSAPI_ERROR_OK;
}
else
{
printf("socket_connect failed\n");
ret = NSAPI_ERROR_DEVICE_ERROR;
}
_mutex.unlock();
return ret;
}
int CC3220SFInterface::socket_accept(void *handle, void **socket, SocketAddress *address)
{
// TODO
return NSAPI_ERROR_UNSUPPORTED;
}
int CC3220SFInterface::socket_send(void *handle, const void *data, unsigned size)
{
struct cc3200_socket *socket = (struct cc3200_socket *)handle;
if (!socket)
{
return NSAPI_ERROR_NO_SOCKET;
}
_mutex.lock();
int ret = _cc3200_simplelink.send(socket->sd, data, size);
if (ret > 0)
{
socket->callback_pending = true;
}
_mutex.unlock();
return ret;
}
int CC3220SFInterface::socket_recv(void *handle, void *data, unsigned size)
{
struct cc3200_socket *socket = (struct cc3200_socket *)handle;
if (!socket)
{
return NSAPI_ERROR_NO_SOCKET;
}
_mutex.lock();
socket->data_to_read = size;
int ret = _socket_receive_data(socket, data);
_mutex.unlock();
return ret;
}
int CC3220SFInterface::socket_sendto(void *handle, const SocketAddress &address, const void *data, unsigned size)
{
struct cc3200_socket *socket = (struct cc3200_socket *)handle;
if (!socket)
{
return NSAPI_ERROR_NO_SOCKET;
}
_mutex.lock();
// Sending a datagram of length 0 is OK
int ret = _cc3200_simplelink.sendto_socket(socket->sd, data, size, address);
if (ret >= 0)
{
socket->callback_pending = true;
}
_mutex.unlock();
return ret;
}
int CC3220SFInterface::socket_recvfrom(void *handle, SocketAddress *address, void *buffer, unsigned size)
{
struct cc3200_socket *socket = (struct cc3200_socket *)handle;
if (!socket)
{
return NSAPI_ERROR_NO_SOCKET;
}
_mutex.lock();
// It's okay to receive 0 for a datagram protocol. Unlike TCP, it doesn't mean the peer has closed the connection.
socket->data_to_read = size;
int ret = _socket_receive_data(socket, buffer);
if (ret >= 0 && address)
{
*address = socket->addr;
}
_mutex.unlock();
return ret;
}
void CC3220SFInterface::socket_attach(void *handle, void (*callback)(void *), void *data)
{
struct cc3200_socket *socket = (struct cc3200_socket *)handle;
if (socket)
{
_mutex.lock();
_cbs[socket->id].callback = callback;
_cbs[socket->id].data = data;
_mutex.unlock();
}
}
void CC3220SFInterface::_socket_background_thread()
{
while (1)
{
for (int i = 0; i < CC3220SF_SOCKET_COUNT; i++)
{
_mutex.lock();
if (_socket_obj[i])
{
struct cc3200_socket *socket = (struct cc3200_socket *)_socket_obj[i];
/* Check if an async event needs to be sent*/
if ((socket->callback_pending) && _cbs[socket->id].callback)
{
_cbs[socket->id].callback(_cbs[socket->id].data);
socket->callback_pending = false;
}
/* Check if there is something to read for this socket. But if it */
/* has already been read : don't read again */
if ((socket->read_data_available == 0) && (socket->data_to_read) && _cbs[socket->id].callback)
{
int read_amount, bytes_to_receive = socket->data_to_read;
if (bytes_to_receive > MAX_RECV_PACKET_SIZE)
{
bytes_to_receive = MAX_RECV_PACKET_SIZE;
}
if (socket->proto == NSAPI_UDP)
{
read_amount = _cc3200_simplelink.recvfrom(socket->sd, socket->read_data_internal_buffer, bytes_to_receive, socket->addr);
}
else
{
read_amount= _cc3200_simplelink.recv(socket->sd, socket->read_data_internal_buffer, bytes_to_receive);
}
//printf("background receive %d %d\n", bytes_to_receive, read_amount);
if (read_amount > 0)
{
socket->read_data_available = read_amount;
// For UDP packet, no packet fragmentation, so none or all
if (socket->proto == NSAPI_UDP)
{
socket->data_to_read = 0;
}
else
{
socket->data_to_read -= read_amount;
}
}
else if ((read_amount < 0 && read_amount != NSAPI_ERROR_WOULD_BLOCK) || (read_amount == 0))
{
/* Mark connection has been lost or closed */
printf("Connection lost\n");
socket->connected = false;
socket->data_to_read = 0;
}
if (read_amount >= 0)
{
/* There is something to read in this socket*/
_cbs[socket->id].callback(_cbs[socket->id].data);
}
}
}
_mutex.unlock();
}
wait_ms(READ_THREAD_SLEEP_MS);
}
}
// This function is expected to run with mutex protection
int CC3220SFInterface::_socket_receive_data(void *obj, void *data)
{
int recv = 0;
char *ptr = (char *)data;
int bytes_to_receive = 0;
cc3200_socket *socket = (cc3200_socket *)obj;
if (socket->read_data_available == 0)
{
// Need to receive
int read_amount;
// Simplelink can receive up to MAX_RECV_PACKET_SIZE
bytes_to_receive = socket->data_to_read;
if (bytes_to_receive > MAX_RECV_PACKET_SIZE)
{
bytes_to_receive = MAX_RECV_PACKET_SIZE;
}
if (socket->proto == NSAPI_UDP) // TODO: is this good enough to distinguish recvfrom and recv?
{
read_amount = _cc3200_simplelink.recvfrom(socket->sd, socket->read_data_internal_buffer, bytes_to_receive, socket->addr);
}
else
{
read_amount= _cc3200_simplelink.recv(socket->sd, socket->read_data_internal_buffer, bytes_to_receive);
}
//printf("foreground receive %d %d\n", bytes_to_receive, read_amount);
if (read_amount == 0)
{
// No data to read
socket->data_to_read = 0;
return 0;
}
if (read_amount > 0)
{
socket->read_data_available = read_amount;
}
else // read_amount < 0
{
if (read_amount == NSAPI_ERROR_WOULD_BLOCK)
{
return NSAPI_ERROR_WOULD_BLOCK;
}
else
{
socket->connected = false;
printf("connection lost\n");
socket->data_to_read = 0;
return NSAPI_ERROR_CONNECTION_LOST;
}
}
}
if (socket->read_data_available > 0)
{
// Data has been received or there's already data waiting to be copied into the buffer provided
uint32_t i = 0;
while (i < socket->read_data_available)
{
*ptr++ = socket->read_data_internal_buffer[i];
i++;
}
recv += i;
/* All the stored data has been read, reset buffer */
memset(socket->read_data_internal_buffer, 0, sizeof(socket->read_data_internal_buffer));
// For UDP packet, no packet fragmentation, so none or all
if (socket->proto == NSAPI_UDP)
{
socket->data_to_read = 0;
}
else
{
socket->data_to_read -= socket->read_data_available;
}
socket->read_data_available = 0;
}
return recv;
}

373
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/* CC3220 implementation of NetworkInterfaceAPI
* Copyright (c) 2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef CC3220SF_INTERFACE_H
#define CC3220SF_INTERFACE_H
#include "mbed.h"
#include "cc3200_simplelink.h"
#define CC3220SF_SOCKET_COUNT (MAX_CONCURRENT_ACTIONS)
#define MAX_RECV_PACKET_SIZE (1544)
/** TI (CC3220SF) interface class
* Implementation of the NetworkStack for TI CC3200 Simplelink stack
*/
class CC3220SFInterface: public NetworkStack, public WiFiInterface
{
public:
/**
* @brief CC3220SFInterface default constructor
*/
CC3220SFInterface();
/** Start the interface
* @return 0 on success, negative on failure
*/
virtual nsapi_error_t connect();
/** Start the interface
*
* Attempts to connect to a WiFi network.
*
* @param ssid Name of the network to connect to
* @param pass Security passphrase to connect to the network
* @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE)
* @param channel Channel on which the connection is to be made, or 0 for any (Default: 0)
* @return 0 on success, or error code on failure
*/
virtual nsapi_error_t connect(const char *ssid, const char *pass,
nsapi_security_t security = NSAPI_SECURITY_NONE,
uint8_t channel = 0);
/** Set the WiFi network credentials
*
* @param ssid Name of the network to connect to
* @param pass Security passphrase to connect to the network
* @param security Type of encryption for connection
* (defaults to NSAPI_SECURITY_NONE)
* @return 0 on success, or error code on failure
*/
virtual nsapi_error_t set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE);
/** Set the WiFi network channel
*
*
* @param channel Channel on which the connection is to be made, or 0 for any (Default: 0)
* @return 0 on success, or error code on failure
*/
virtual nsapi_error_t set_channel(uint8_t channel);
/** Stop the interface
* @return 0 on success, negative on failure
*/
virtual int disconnect();
/** Set a static IP address
*
* Configures this network interface to use a static IP address.
* Implicitly disables DHCP, which can be enabled in set_dhcp.
* Requires that the network is disconnected.
*
* @param address Null-terminated representation of the local IP address
* @param netmask Null-terminated representation of the local network mask
* @param gateway Null-terminated representation of the local gateway
* @return 0 on success, negative error code on failure
*/
//virtual nsapi_error_t set_network(const char *ip_address, const char *netmask, const char *gateway);
/** Enable or disable DHCP on the network
*
* Requires that the network is disconnected
*
* @param dhcp False to disable dhcp (defaults to enabled)
* @return 0 on success, negative error code on failure
*/
//virtual nsapi_error_t set_dhcp(bool dhcp);
/** Get the internally stored IP address
* @return IP address of the interface or null if not yet connected
*/
virtual const char *get_ip_address();
/** Get the internally stored MAC address
* @return MAC address of the interface
*/
virtual const char *get_mac_address();
/** Get the local gateway
*
* @return Null-terminated representation of the local gateway
* or null if no network mask has been recieved
*/
virtual const char *get_gateway();
/** Get the local network mask
*
* @return Null-terminated representation of the local network mask
* or null if no network mask has been recieved
*/
virtual const char *get_netmask();
/** Gets the current radio signal strength for active connection
*
* @return Connection strength in dBm (negative value)
*/
virtual int8_t get_rssi();
/** Scan for available networks
*
* The scan will
* If the network interface is set to non-blocking mode, scan will attempt to scan
* for WiFi networks asynchronously and return NSAPI_ERROR_WOULD_BLOCK. If a callback
* is attached, the callback will be called when the operation has completed.
* @param res Pointer to allocated array to store discovered AP
* @param count Size of allocated @a res array, or 0 to only count available AP
* @return Number of entries in @a, or if @a count was 0 number of available networks, negative on error
* see @a nsapi_error
*/
virtual nsapi_size_or_error_t scan(WiFiAccessPoint *res, unsigned count);
/** Translates a hostname to an IP address with specific version
*
* The hostname may be either a domain name or an IP address. If the
* hostname is an IP address, no network transactions will be performed.
*
* If no stack-specific DNS resolution is provided, the hostname
* will be resolve using a UDP socket on the stack.
*
* @param address Destination for the host SocketAddress
* @param host Hostname to resolve
* @param version IP version of address to resolve, NSAPI_UNSPEC indicates
* version is chosen by the stack (defaults to NSAPI_UNSPEC)
* @return 0 on success, negative error code on failure
*/
using NetworkInterface::gethostbyname;
//virtual nsapi_error_t gethostbyname(const char *name, SocketAddress *address, nsapi_version_t version);
/** Add a domain name server to list of servers to query
*
* @param addr Destination for the host address
* @return 0 on success, negative error code on failure
*/
using NetworkInterface::add_dns_server;
virtual nsapi_error_t get_dns_server(int index, SocketAddress *address, const char* interface_name = NULL);
/** Set socket options
*
* The setsockopt allow an application to pass stack-specific hints
* to the underlying stack. For unsupported options,
* NSAPI_ERROR_UNSUPPORTED is returned and the socket is unmodified.
*
* @param handle Socket handle
* @param level Stack-specific protocol level
* @param optname Stack-specific option identifier
* @param optval Option value
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
virtual nsapi_error_t setsockopt(nsapi_socket_t handle, int level,
int optname, const void *optval, unsigned optlen);
/** Get socket options
*
* getsockopt allows an application to retrieve stack-specific options
* from the underlying stack using stack-specific level and option names,
* or to request generic options using levels from nsapi_socket_level_t.
*
* For unsupported options, NSAPI_ERROR_UNSUPPORTED is returned
* and the socket is unmodified.
*
* @param level Stack-specific protocol level or nsapi_socket_level_t
* @param optname Level-specific option name
* @param optval Destination for option value
* @param optlen Length of the option value
* @return 0 on success, negative error code on failure
*/
virtual nsapi_error_t getsockopt(nsapi_socket_t handle, int level, int optname,
void *optval, unsigned *optlen);
/** Register callback for status reporting
*
* The specified status callback function will be called on status changes
* on the network. The parameters on the callback are the event type and
* event-type dependent reason parameter.
*
* @param status_cb The callback for status changes
*/
virtual void attach(mbed::Callback<void(nsapi_event_t, intptr_t)> status_cb);
/** Get the connection status
*
* @return The connection status according to ConnectionStatusType
*/
virtual nsapi_connection_status_t get_connection_status() const;
protected:
/** Open a socket
* @param handle Handle in which to store new socket
* @param proto Type of socket to open, NSAPI_TCP or NSAPI_UDP
* @return 0 on success, negative on failure
*/
virtual int socket_open(void **handle, nsapi_protocol_t proto);
/** Close the socket
* @param handle Socket handle
* @return 0 on success, negative on failure
* @note On failure, any memory associated with the socket must still
* be cleaned up
*/
virtual int socket_close(void *handle);
/** Bind a server socket to a specific port
* @param handle Socket handle
* @param address Local address to listen for incoming connections on
* @return 0 on success, negative on failure.
*/
virtual int socket_bind(void *handle, const SocketAddress &address);
/** Start listening for incoming connections
* @param handle Socket handle
* @param backlog Number of pending connections that can be queued up at any
* one time [Default: 1]
* @return 0 on success, negative on failure
*/
virtual int socket_listen(void *handle, int backlog);
/** Connects this TCP socket to the server
* @param handle Socket handle
* @param address SocketAddress to connect to
* @return 0 on success, negative on failure
*/
virtual int socket_connect(void *handle, const SocketAddress &address);
/** Accept a new connection.
* @param handle Handle in which to store new socket
* @param server Socket handle to server to accept from
* @return 0 on success, negative on failure
* @note This call is not-blocking, if this call would block, must
* immediately return NSAPI_ERROR_WOULD_WAIT
*/
virtual int socket_accept(void *handle, void **socket, SocketAddress *address);
/** Send data to the remote host
* @param handle Socket handle
* @param data The buffer to send to the host
* @param size The length of the buffer to send
* @return Number of written bytes on success, negative on failure
* @note This call is not-blocking, if this call would block, must
* immediately return NSAPI_ERROR_WOULD_WAIT
*/
virtual int socket_send(void *handle, const void *data, unsigned size);
/** Receive data from the remote host
* @param handle Socket handle
* @param data The buffer in which to store the data received from the host
* @param size The maximum length of the buffer
* @return Number of received bytes on success, negative on failure
* @note This call is not-blocking, if this call would block, must
* immediately return NSAPI_ERROR_WOULD_WAIT
*/
virtual int socket_recv(void *handle, void *data, unsigned size);
/** Send a packet to a remote endpoint
* @param handle Socket handle
* @param address The remote SocketAddress
* @param data The packet to be sent
* @param size The length of the packet to be sent
* @return The number of written bytes on success, negative on failure
* @note This call is not-blocking, if this call would block, must
* immediately return NSAPI_ERROR_WOULD_WAIT
*/
virtual int socket_sendto(void *handle, const SocketAddress &address, const void *data, unsigned size);
/** Receive a packet from a remote endpoint
* @param handle Socket handle
* @param address Destination for the remote SocketAddress or null
* @param buffer The buffer for storing the incoming packet data
* If a packet is too long to fit in the supplied buffer,
* excess bytes are discarded
* @param size The length of the buffer
* @return The number of received bytes on success, negative on failure
* @note This call is not-blocking, if this call would block, must
* immediately return NSAPI_ERROR_WOULD_WAIT
*/
virtual int socket_recvfrom(void *handle, SocketAddress *address, void *buffer, unsigned size);
/** Register a callback on state change of the socket
* @param handle Socket handle
* @param callback Function to call on state change
* @param data Argument to pass to callback
* @note Callback may be called in an interrupt context.
*/
virtual void socket_attach(void *handle, void (*callback)(void *), void *data);
/** Provide access to the NetworkStack object
*
* @return The underlying NetworkStack object
*/
virtual NetworkStack *get_stack()
{
return this;
}
private:
static const int CC3220SF_SSID_MAX_LENGTH = 32; /* 32 is what 802.11 defines as longest possible name */
static const int CC3220SF_PASSPHRASE_MAX_LENGTH = 63; /* The longest allowed passphrase */
static const int CC3220SF_PASSPHRASE_MIN_LENGTH = 8; /* The shortest allowed passphrase */
struct {
void (*callback)(void *);
void *data;
} _cbs[CC3220SF_SOCKET_COUNT];
struct cc3200_socket {
int id;
int sd;
nsapi_protocol_t proto;
volatile bool connected;
char read_data_internal_buffer[MAX_RECV_PACKET_SIZE];
volatile uint32_t read_data_available;
uint32_t data_to_read;
bool callback_pending;
SocketAddress addr;
};
bool _id_in_use[CC3220SF_SOCKET_COUNT];
void * _socket_obj[CC3220SF_SOCKET_COUNT]; // store addresses of socket handles
Mutex _mutex;
Thread _thread_read_socket;
CC3200_SIMPLELINK _cc3200_simplelink;
int _initialized;
int _started;
char _ssid[CC3220SF_SSID_MAX_LENGTH + 1]; /* 32 is what 802.11 defines as longest possible name; +1 for the \0 */
nsapi_security_t _security;
uint8_t _channel;
char _pass[CC3220SF_PASSPHRASE_MAX_LENGTH + 1];
void _socket_background_thread();
int _socket_receive_data(void *obj, void *data);
nsapi_error_t _init(void);
nsapi_error_t _startup(const int8_t wifi_mode);
Semaphore _connect_sem;
Semaphore _ip_set_sem;
static CC3220SFInterface * cc3200sf_wifi_instance;
friend void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent);
friend void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent);
};
#endif

104
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/CC3220SF.sct Normal file
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#! armcc -E
/* Device specific values */
#define ROM_START 0x01000000
#define ROM_SIZE 0x100000
#define FLASH_HDR_START ROM_START
#define FLASH_HDR_SIZE 0x800
#define RAM_START 0x20000000
#define RAM_SIZE 0x40000
#define VECTORS 195 /* This value must match NVIC_NUM_VECTORS */
/* Round up VECTORS_SIZE to 8 bytes */
#define VECTORS_SIZE (((VECTORS * 4) + 7) & ~7)
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
#if defined(MBED_APP_START)
/*
* There're two cases if MBED_APP_START is defined.
* Case 1: MBED_APP_START is defined as ROM_START, this happens when restrict_size is turned on, most likely for bootloader build.
* In this build, include FLASH_HDR region.
*/
#define FLASH_HDR_INCLUDED 1
#if MBED_APP_START == ROM_START
#if defined(MBED_APP_SIZE)
#define ROM_EXEC_START (ROM_START + FLASH_HDR_SIZE)
#define ROM_EXEC_SIZE (MBED_APP_SIZE - FLASH_HDR_SIZE)
#endif
#else
/*
* Case 2: MBED_APP_START is defined as a value greater than ROM_START, this is most likely a build other than the bootloader. E.g., the MCC build.
* In this build, exclude FLASH_HDR region. This workarounds an issue in managed boodloader MCC build where the jump address and stack pointer point to the cookie area
*/
#undef FLASH_HDR_INCLUDED
#define FLASH_HDR_INCLUDED 0
#define ROM_EXEC_START MBED_APP_START
#if defined(MBED_APP_SIZE)
#define ROM_EXEC_SIZE MBED_APP_SIZE
#else
#define ROM_EXEC_SIZE (ROM_SIZE- (MBED_APP_START - ROM_START))
#endif
#endif
#else
/*
* MBED_APP_START is not defined. This is most likely a bootloader build, or other apps that do not require boodloader.
* In this build, include FLASH_HDR region
*/
#define FLASH_HDR_INCLUDED 1
#define ROM_EXEC_START (ROM_START + FLASH_HDR_SIZE)
#if defined(MBED_APP_SIZE)
#define ROM_EXEC_SIZE (MBED_APP_SIZE - FLASH_HDR_SIZE)
#else
#define ROM_EXEC_SIZE (ROM_SIZE - FLASH_HDR_SIZE)
#endif
#endif
#if FLASH_HDR_INCLUDED == 1
;#warning include cookie
LR_IROM1 ROM_START ROM_SIZE {
ER_FLASH FLASH_HDR_START FLASH_HDR_SIZE {
*(signature_section, +Last)
}
ER_IROM1 ROM_EXEC_START FIXED {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
;RW_IRAM1 (RAM_START + VECTORS_SIZE) (RAM_SIZE - VECTORS_SIZE) { ; RW data
RW_IRAM1 (0x20000000+0x308) (0x00040000-0x308) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -Stack_Size { ; stack
}
}
#else
;#warning exclude cookie
LR_IROM1 ROM_EXEC_START ROM_EXEC_SIZE {
ER_IROM1 ROM_EXEC_START ROM_EXEC_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
;RW_IRAM1 (RAM_START + VECTORS_SIZE) (RAM_SIZE - VECTORS_SIZE) { ; RW data
RW_IRAM1 (0x20000000+0x308) (0x00040000-0x308) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (RAM_START + RAM_SIZE) EMPTY -Stack_Size { ; stack
}
}
#endif

371
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_ARM_STD/startup_CC3220SF.S Normal file
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;/*
; * Copyright (c) 2018-2019 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
__initial_sp EQU 0x20040000 ; Top of RAM
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD INT_GPIOA0_IRQHandler ; /* 16 */
DCD INT_GPIOA1_IRQHandler ; /* 17 */
DCD INT_GPIOA2_IRQHandler ; /* 18 */
DCD INT_GPIOA3_IRQHandler ; /* 19 */
DCD 0 ; /* 20 Reserved interrupt */
DCD INT_UARTA0_IRQHandler ; /* 21 */
DCD INT_UARTA1_IRQHandler ; /* 22 */
DCD 0 ; /* 23 Reserved interrupt */
DCD INT_I2CA0_IRQHandler ; /* 24 */
DCD 0 ; /* 25 Reserved interrupt */
DCD 0 ; /* 26 Reserved interrupt */
DCD 0 ; /* 27 Reserved interrupt */
DCD 0 ; /* 28 Reserved interrupt */
DCD 0 ; /* 29 Reserved interrupt */
DCD INT_ADCCH0_IRQHandler ; /* 30 */
DCD INT_ADCCH1_IRQHandler ; /* 31 */
DCD INT_ADCCH2_IRQHandler ; /* 32 */
DCD INT_ADCCH3_IRQHandler ; /* 33 */
DCD INT_WDT_IRQHandler ; /* 34 */
DCD INT_TIMERA0A_IRQHandler ; /* 35 */
DCD INT_TIMERA0B_IRQHandler ; /* 36 */
DCD INT_TIMERA1A_IRQHandler ; /* 37 */
DCD INT_TIMERA1B_IRQHandler ; /* 38 */
DCD INT_TIMERA2A_IRQHandler ; /* 39 */
DCD INT_TIMERA2B_IRQHandler ; /* 40 */
DCD 0 ; /* 41 Reserved interrupt */
DCD 0 ; /* 42 Reserved interrupt */
DCD 0 ; /* 43 Reserved interrupt */
DCD 0 ; /* 44 Reserved interrupt */
DCD INT_FLASH_IRQHandler ; /* 45 */
DCD 0 ; /* 46 Reserved interrupt */
DCD 0 ; /* 47 Reserved interrupt */
DCD 0 ; /* 48 Reserved interrupt */
DCD 0 ; /* 49 Reserved interrupt */
DCD 0 ; /* 50 Reserved interrupt */
DCD INT_TIMERA3A_IRQHandler ; /* 51 */
DCD INT_TIMERA3B_IRQHandler ; /* 52 */
DCD 0 ; /* 53 Reserved interrupt */
DCD 0 ; /* 54 Reserved interrupt */
DCD 0 ; /* 55 Reserved interrupt */
DCD 0 ; /* 56 Reserved interrupt */
DCD 0 ; /* 57 Reserved interrupt */
DCD 0 ; /* 58 Reserved interrupt */
DCD 0 ; /* 59 Reserved interrupt */
DCD 0 ; /* 60 Reserved interrupt */
DCD 0 ; /* 61 Reserved interrupt */
DCD INT_UDMA_IRQHandler ; /* 62 */
DCD INT_UDMAERR_IRQHandler ; /* 63 */
DCD 0 ; /* 64 Reserved interrupt */
DCD 0 ; /* 65 Reserved interrupt */
DCD 0 ; /* 66 Reserved interrupt */
DCD 0 ; /* 67 Reserved interrupt */
DCD 0 ; /* 68 Reserved interrupt */
DCD 0 ; /* 69 Reserved interrupt */
DCD 0 ; /* 70 Reserved interrupt */
DCD 0 ; /* 71 Reserved interrupt */
DCD 0 ; /* 72 Reserved interrupt */
DCD 0 ; /* 73 Reserved interrupt */
DCD 0 ; /* 74 Reserved interrupt */
DCD 0 ; /* 75 Reserved interrupt */
DCD 0 ; /* 76 Reserved interrupt */
DCD 0 ; /* 77 Reserved interrupt */
DCD 0 ; /* 78 Reserved interrupt */
DCD 0 ; /* 79 Reserved interrupt */
DCD 0 ; /* 80 Reserved interrupt */
DCD 0 ; /* 81 Reserved interrupt */
DCD 0 ; /* 82 Reserved interrupt */
DCD 0 ; /* 83 Reserved interrupt */
DCD 0 ; /* 84 Reserved interrupt */
DCD 0 ; /* 85 Reserved interrupt */
DCD 0 ; /* 86 Reserved interrupt */
DCD 0 ; /* 87 Reserved interrupt */
DCD 0 ; /* 88 Reserved interrupt */
DCD 0 ; /* 89 Reserved interrupt */
DCD 0 ; /* 90 Reserved interrupt */
DCD 0 ; /* 91 Reserved interrupt */
DCD 0 ; /* 92 Reserved interrupt */
DCD 0 ; /* 93 Reserved interrupt */
DCD 0 ; /* 94 Reserved interrupt */
DCD 0 ; /* 95 Reserved interrupt */
DCD 0 ; /* 96 Reserved interrupt */
DCD 0 ; /* 97 Reserved interrupt */
DCD 0 ; /* 98 Reserved interrupt */
DCD 0 ; /* 99 Reserved interrupt */
DCD 0 ; /* 100 Reserved interrupt */
DCD 0 ; /* 101 Reserved interrupt */
DCD 0 ; /* 102 Reserved interrupt */
DCD 0 ; /* 103 Reserved interrupt */
DCD 0 ; /* 104 Reserved interrupt */
DCD 0 ; /* 105 Reserved interrupt */
DCD 0 ; /* 106 Reserved interrupt */
DCD 0 ; /* 107 Reserved interrupt */
DCD 0 ; /* 108 Reserved interrupt */
DCD 0 ; /* 109 Reserved interrupt */
DCD 0 ; /* 110 Reserved interrupt */
DCD 0 ; /* 111 Reserved interrupt */
DCD 0 ; /* 112 Reserved interrupt */
DCD 0 ; /* 113 Reserved interrupt */
DCD 0 ; /* 114 Reserved interrupt */
DCD 0 ; /* 115 Reserved interrupt */
DCD 0 ; /* 116 Reserved interrupt */
DCD 0 ; /* 117 Reserved interrupt */
DCD 0 ; /* 118 Reserved interrupt */
DCD 0 ; /* 119 Reserved interrupt */
DCD 0 ; /* 120 Reserved interrupt */
DCD 0 ; /* 121 Reserved interrupt */
DCD 0 ; /* 122 Reserved interrupt */
DCD 0 ; /* 123 Reserved interrupt */
DCD 0 ; /* 124 Reserved interrupt */
DCD 0 ; /* 125 Reserved interrupt */
DCD 0 ; /* 126 Reserved interrupt */
DCD 0 ; /* 127 Reserved interrupt */
DCD 0 ; /* 128 Reserved interrupt */
DCD 0 ; /* 129 Reserved interrupt */
DCD 0 ; /* 130 Reserved interrupt */
DCD 0 ; /* 131 Reserved interrupt */
DCD 0 ; /* 132 Reserved interrupt */
DCD 0 ; /* 133 Reserved interrupt */
DCD 0 ; /* 134 Reserved interrupt */
DCD 0 ; /* 135 Reserved interrupt */
DCD 0 ; /* 136 Reserved interrupt */
DCD 0 ; /* 137 Reserved interrupt */
DCD 0 ; /* 138 Reserved interrupt */
DCD 0 ; /* 139 Reserved interrupt */
DCD 0 ; /* 140 Reserved interrupt */
DCD 0 ; /* 141 Reserved interrupt */
DCD 0 ; /* 142 Reserved interrupt */
DCD 0 ; /* 143 Reserved interrupt */
DCD 0 ; /* 144 Reserved interrupt */
DCD 0 ; /* 145 Reserved interrupt */
DCD 0 ; /* 146 Reserved interrupt */
DCD 0 ; /* 147 Reserved interrupt */
DCD 0 ; /* 148 Reserved interrupt */
DCD 0 ; /* 149 Reserved interrupt */
DCD 0 ; /* 150 Reserved interrupt */
DCD 0 ; /* 151 Reserved interrupt */
DCD 0 ; /* 152 Reserved interrupt */
DCD 0 ; /* 153 Reserved interrupt */
DCD 0 ; /* 154 Reserved interrupt */
DCD 0 ; /* 155 Reserved interrupt */
DCD 0 ; /* 156 Reserved interrupt */
DCD 0 ; /* 157 Reserved interrupt */
DCD 0 ; /* 158 Reserved interrupt */
DCD 0 ; /* 159 Reserved interrupt */
DCD 0 ; /* 160 Reserved interrupt */
DCD 0 ; /* 161 Reserved interrupt */
DCD 0 ; /* 162 Reserved interrupt */
DCD 0 ; /* 163 Reserved interrupt */
DCD INT_SHA_IRQHandler ; /* 164 */
DCD 0 ; /* 165 Reserved interrupt */
DCD 0 ; /* 166 Reserved interrupt */
DCD INT_AES_IRQHandler ; /* 167 */
DCD 0 ; /* 168 Reserved interrupt */
DCD INT_DES_IRQHandler ; /* 169 */
DCD 0 ; /* 170 Reserved interrupt */
DCD 0 ; /* 171 Reserved interrupt */
DCD 0 ; /* 172 Reserved interrupt */
DCD 0 ; /* 173 Reserved interrupt */
DCD 0 ; /* 174 Reserved interrupt */
DCD INT_MMCHS_IRQHandler ; /* 175 */
DCD 0 ; /* 176 Reserved interrupt */
DCD INT_I2S_IRQHandler ; /* 177 */
DCD 0 ; /* 178 Reserved interrupt */
DCD INT_CAMERA_IRQHandler ; /* 179 */
DCD 0 ; /* 180 Reserved interrupt */
DCD 0 ; /* 181 Reserved interrupt */
DCD 0 ; /* 182 Reserved interrupt */
DCD 0 ; /* 183 Reserved interrupt */
DCD 0 ; /* 184 Reserved interrupt */
DCD 0 ; /* 185 Reserved interrupt */
DCD 0 ; /* 186 Reserved interrupt */
DCD INT_NWPIC_IRQHandler ; /* 187 */
DCD INT_PRCM_IRQHandler ; /* 188 */
DCD 0 ; /* 189 Reserved interrupt */
DCD 0 ; /* 190 Reserved interrupt */
DCD INT_SSPI_IRQHandler ; /* 191 */
DCD INT_GSPI_IRQHandler ; /* 192 */
DCD INT_LSPI_IRQHandler ; /* 193 */
DCD 0 ; /* 194 Reserved interrupt */
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT INT_GPIOA0_IRQHandler [WEAK]
EXPORT INT_GPIOA1_IRQHandler [WEAK]
EXPORT INT_GPIOA2_IRQHandler [WEAK]
EXPORT INT_GPIOA3_IRQHandler [WEAK]
EXPORT INT_UARTA0_IRQHandler [WEAK]
EXPORT INT_UARTA1_IRQHandler [WEAK]
EXPORT INT_I2CA0_IRQHandler [WEAK]
EXPORT INT_ADCCH0_IRQHandler [WEAK]
EXPORT INT_ADCCH1_IRQHandler [WEAK]
EXPORT INT_ADCCH2_IRQHandler [WEAK]
EXPORT INT_ADCCH3_IRQHandler [WEAK]
EXPORT INT_WDT_IRQHandler [WEAK]
EXPORT INT_TIMERA0A_IRQHandler [WEAK]
EXPORT INT_TIMERA0B_IRQHandler [WEAK]
EXPORT INT_TIMERA1A_IRQHandler [WEAK]
EXPORT INT_TIMERA1B_IRQHandler [WEAK]
EXPORT INT_TIMERA2A_IRQHandler [WEAK]
EXPORT INT_TIMERA2B_IRQHandler [WEAK]
EXPORT INT_FLASH_IRQHandler [WEAK]
EXPORT INT_TIMERA3A_IRQHandler [WEAK]
EXPORT INT_TIMERA3B_IRQHandler [WEAK]
EXPORT INT_UDMA_IRQHandler [WEAK]
EXPORT INT_UDMAERR_IRQHandler [WEAK]
EXPORT INT_SHA_IRQHandler [WEAK]
EXPORT INT_AES_IRQHandler [WEAK]
EXPORT INT_DES_IRQHandler [WEAK]
EXPORT INT_MMCHS_IRQHandler [WEAK]
EXPORT INT_I2S_IRQHandler [WEAK]
EXPORT INT_CAMERA_IRQHandler [WEAK]
EXPORT INT_NWPIC_IRQHandler [WEAK]
EXPORT INT_PRCM_IRQHandler [WEAK]
EXPORT INT_SSPI_IRQHandler [WEAK]
EXPORT INT_GSPI_IRQHandler [WEAK]
EXPORT INT_LSPI_IRQHandler [WEAK]
INT_GPIOA0_IRQHandler
INT_GPIOA1_IRQHandler
INT_GPIOA2_IRQHandler
INT_GPIOA3_IRQHandler
INT_UARTA0_IRQHandler
INT_UARTA1_IRQHandler
INT_I2CA0_IRQHandler
INT_ADCCH0_IRQHandler
INT_ADCCH1_IRQHandler
INT_ADCCH2_IRQHandler
INT_ADCCH3_IRQHandler
INT_WDT_IRQHandler
INT_TIMERA0A_IRQHandler
INT_TIMERA0B_IRQHandler
INT_TIMERA1A_IRQHandler
INT_TIMERA1B_IRQHandler
INT_TIMERA2A_IRQHandler
INT_TIMERA2B_IRQHandler
INT_FLASH_IRQHandler
INT_TIMERA3A_IRQHandler
INT_TIMERA3B_IRQHandler
INT_UDMA_IRQHandler
INT_UDMAERR_IRQHandler
INT_SHA_IRQHandler
INT_AES_IRQHandler
INT_DES_IRQHandler
INT_MMCHS_IRQHandler
INT_I2S_IRQHandler
INT_CAMERA_IRQHandler
INT_NWPIC_IRQHandler
INT_PRCM_IRQHandler
INT_SSPI_IRQHandler
INT_GSPI_IRQHandler
INT_LSPI_IRQHandler
B .
ENDP
ALIGN
END

218
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/gcc_arm.ld Normal file
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@ -0,0 +1,218 @@
/* Device specific values */
#define ROM_START 0x01000000
#define ROM_SIZE 0x100000
#define FLASH_HDR_START ROM_START
#define FLASH_HDR_SIZE 0x800
#define RAM_START 0x20000000
#define RAM_SIZE 0x40000
#define VECTORS 195 /* This value must match NVIC_NUM_VECTORS */
/* Round up VECTORS_SIZE to 8 bytes */
#define VECTORS_SIZE (((VECTORS * 4) + 7) & 0xFFFFFFF8)
#if defined(MBED_APP_START)
/*
* There're two cases if MBED_APP_START is defined.
* Case 1: MBED_APP_START is defined as ROM_START, this happens when restrict_size is turned on, most likely for bootloader build.
* In this build, include FLASH_HDR region.
*/
#define FLASH_HDR_INCLUDED 1
#if MBED_APP_START == ROM_START
#if defined(MBED_APP_SIZE)
#define ROM_EXEC_START (ROM_START + FLASH_HDR_SIZE)
#define ROM_EXEC_SIZE (MBED_APP_SIZE - FLASH_HDR_SIZE)
#endif
#else
/*
* Case 2: MBED_APP_START is defined as a value greater than ROM_START, this is most likely a build other than the bootloader. E.g., the MCC build.
* In this build, exclude FLASH_HDR region. This workarounds an issue in managed boodloader MCC build where the jump address and stack pointer point to the cookie area
*/
#undef FLASH_HDR_INCLUDED
#define FLASH_HDR_INCLUDED 0
#define ROM_EXEC_START MBED_APP_START
#if defined(MBED_APP_SIZE)
#define ROM_EXEC_SIZE MBED_APP_SIZE
#else
#define ROM_EXEC_SIZE (ROM_SIZE- (MBED_APP_START - ROM_START))
#endif
#endif
#else
/*
* MBED_APP_START is not defined. This is most likely a bootloader build, or other apps that do not require boodloader.
* In this build, include FLASH_HDR region
*/
#define FLASH_HDR_INCLUDED 1
#define ROM_EXEC_START (ROM_START + FLASH_HDR_SIZE)
#if defined(MBED_APP_SIZE)
#define ROM_EXEC_SIZE (MBED_APP_SIZE - FLASH_HDR_SIZE)
#else
#define ROM_EXEC_SIZE (ROM_SIZE - FLASH_HDR_SIZE)
#endif
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
MEMORY
{
FLASH_HDR (rx) : ORIGIN = FLASH_HDR_START, LENGTH = FLASH_HDR_SIZE
FLASH (rx) : ORIGIN = ROM_EXEC_START, LENGTH = ROM_EXEC_SIZE
RAM (rwx) : ORIGIN = RAM_START + VECTORS_SIZE, LENGTH = RAM_SIZE - VECTORS_SIZE
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
#if FLASH_HDR_INCLUDED == 1
.dbghdr : ALIGN (2048) {
KEEP (*(.dbghdr))
} > FLASH_HDR
#endif
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
/* Location counter can end up 2byte aligned with narrow Thumb code but
__etext is assumed by startup code to be the LMA of a section in RAM
which must be 4byte aligned */
__etext = ALIGN (4);
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
. = ALIGN(4);
__end__ = .;
end = __end__;
*(.heap*)
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

451
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_GCC_ARM/startup_CC3220SF.S Normal file
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@ -0,0 +1,451 @@
/**************************************************************************//**
* @file startup_CC3220SF.S
* @brief CMSIS Cortex-M4 Core Device Startup File for
* Device CC3220SF
* @version V5.00
* @date 02. March 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
/*
// <h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x1000
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .isr_vector
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long INT_GPIOA0_IRQHandler /* 16 */
.long INT_GPIOA1_IRQHandler /* 17 */
.long INT_GPIOA2_IRQHandler /* 18 */
.long INT_GPIOA3_IRQHandler /* 19 */
.long 0 /* 20 Reserved interrupt */
.long INT_UARTA0_IRQHandler /* 21 */
.long INT_UARTA1_IRQHandler /* 22 */
.long 0 /* 23 Reserved interrupt */
.long INT_I2CA0_IRQHandler /* 24 */
.long 0 /* 25 Reserved interrupt */
.long 0 /* 26 Reserved interrupt */
.long 0 /* 27 Reserved interrupt */
.long 0 /* 28 Reserved interrupt */
.long 0 /* 29 Reserved interrupt */
.long INT_ADCCH0_IRQHandler /* 30 */
.long INT_ADCCH1_IRQHandler /* 31 */
.long INT_ADCCH2_IRQHandler /* 32 */
.long INT_ADCCH3_IRQHandler /* 33 */
.long INT_WDT_IRQHandler /* 34 */
.long INT_TIMERA0A_IRQHandler /* 35 */
.long INT_TIMERA0B_IRQHandler /* 36 */
.long INT_TIMERA1A_IRQHandler /* 37 */
.long INT_TIMERA1B_IRQHandler /* 38 */
.long INT_TIMERA2A_IRQHandler /* 39 */
.long INT_TIMERA2B_IRQHandler /* 40 */
.long 0 /* 41 Reserved interrupt */
.long 0 /* 42 Reserved interrupt */
.long 0 /* 43 Reserved interrupt */
.long 0 /* 44 Reserved interrupt */
.long INT_FLASH_IRQHandler /* 45 */
.long 0 /* 46 Reserved interrupt */
.long 0 /* 47 Reserved interrupt */
.long 0 /* 48 Reserved interrupt */
.long 0 /* 49 Reserved interrupt */
.long 0 /* 50 Reserved interrupt */
.long INT_TIMERA3A_IRQHandler /* 51 */
.long INT_TIMERA3B_IRQHandler /* 52 */
.long 0 /* 53 Reserved interrupt */
.long 0 /* 54 Reserved interrupt */
.long 0 /* 55 Reserved interrupt */
.long 0 /* 56 Reserved interrupt */
.long 0 /* 57 Reserved interrupt */
.long 0 /* 58 Reserved interrupt */
.long 0 /* 59 Reserved interrupt */
.long 0 /* 60 Reserved interrupt */
.long 0 /* 61 Reserved interrupt */
.long INT_UDMA_IRQHandler /* 62 */
.long INT_UDMAERR_IRQHandler /* 63 */
.long 0 /* 64 Reserved interrupt */
.long 0 /* 65 Reserved interrupt */
.long 0 /* 66 Reserved interrupt */
.long 0 /* 67 Reserved interrupt */
.long 0 /* 68 Reserved interrupt */
.long 0 /* 69 Reserved interrupt */
.long 0 /* 70 Reserved interrupt */
.long 0 /* 71 Reserved interrupt */
.long 0 /* 72 Reserved interrupt */
.long 0 /* 73 Reserved interrupt */
.long 0 /* 74 Reserved interrupt */
.long 0 /* 75 Reserved interrupt */
.long 0 /* 76 Reserved interrupt */
.long 0 /* 77 Reserved interrupt */
.long 0 /* 78 Reserved interrupt */
.long 0 /* 79 Reserved interrupt */
.long 0 /* 80 Reserved interrupt */
.long 0 /* 81 Reserved interrupt */
.long 0 /* 82 Reserved interrupt */
.long 0 /* 83 Reserved interrupt */
.long 0 /* 84 Reserved interrupt */
.long 0 /* 85 Reserved interrupt */
.long 0 /* 86 Reserved interrupt */
.long 0 /* 87 Reserved interrupt */
.long 0 /* 88 Reserved interrupt */
.long 0 /* 89 Reserved interrupt */
.long 0 /* 90 Reserved interrupt */
.long 0 /* 91 Reserved interrupt */
.long 0 /* 92 Reserved interrupt */
.long 0 /* 93 Reserved interrupt */
.long 0 /* 94 Reserved interrupt */
.long 0 /* 95 Reserved interrupt */
.long 0 /* 96 Reserved interrupt */
.long 0 /* 97 Reserved interrupt */
.long 0 /* 98 Reserved interrupt */
.long 0 /* 99 Reserved interrupt */
.long 0 /* 100 Reserved interrupt */
.long 0 /* 101 Reserved interrupt */
.long 0 /* 102 Reserved interrupt */
.long 0 /* 103 Reserved interrupt */
.long 0 /* 104 Reserved interrupt */
.long 0 /* 105 Reserved interrupt */
.long 0 /* 106 Reserved interrupt */
.long 0 /* 107 Reserved interrupt */
.long 0 /* 108 Reserved interrupt */
.long 0 /* 109 Reserved interrupt */
.long 0 /* 110 Reserved interrupt */
.long 0 /* 111 Reserved interrupt */
.long 0 /* 112 Reserved interrupt */
.long 0 /* 113 Reserved interrupt */
.long 0 /* 114 Reserved interrupt */
.long 0 /* 115 Reserved interrupt */
.long 0 /* 116 Reserved interrupt */
.long 0 /* 117 Reserved interrupt */
.long 0 /* 118 Reserved interrupt */
.long 0 /* 119 Reserved interrupt */
.long 0 /* 120 Reserved interrupt */
.long 0 /* 121 Reserved interrupt */
.long 0 /* 122 Reserved interrupt */
.long 0 /* 123 Reserved interrupt */
.long 0 /* 124 Reserved interrupt */
.long 0 /* 125 Reserved interrupt */
.long 0 /* 126 Reserved interrupt */
.long 0 /* 127 Reserved interrupt */
.long 0 /* 128 Reserved interrupt */
.long 0 /* 129 Reserved interrupt */
.long 0 /* 130 Reserved interrupt */
.long 0 /* 131 Reserved interrupt */
.long 0 /* 132 Reserved interrupt */
.long 0 /* 133 Reserved interrupt */
.long 0 /* 134 Reserved interrupt */
.long 0 /* 135 Reserved interrupt */
.long 0 /* 136 Reserved interrupt */
.long 0 /* 137 Reserved interrupt */
.long 0 /* 138 Reserved interrupt */
.long 0 /* 139 Reserved interrupt */
.long 0 /* 140 Reserved interrupt */
.long 0 /* 141 Reserved interrupt */
.long 0 /* 142 Reserved interrupt */
.long 0 /* 143 Reserved interrupt */
.long 0 /* 144 Reserved interrupt */
.long 0 /* 145 Reserved interrupt */
.long 0 /* 146 Reserved interrupt */
.long 0 /* 147 Reserved interrupt */
.long 0 /* 148 Reserved interrupt */
.long 0 /* 149 Reserved interrupt */
.long 0 /* 150 Reserved interrupt */
.long 0 /* 151 Reserved interrupt */
.long 0 /* 152 Reserved interrupt */
.long 0 /* 153 Reserved interrupt */
.long 0 /* 154 Reserved interrupt */
.long 0 /* 155 Reserved interrupt */
.long 0 /* 156 Reserved interrupt */
.long 0 /* 157 Reserved interrupt */
.long 0 /* 158 Reserved interrupt */
.long 0 /* 159 Reserved interrupt */
.long 0 /* 160 Reserved interrupt */
.long 0 /* 161 Reserved interrupt */
.long 0 /* 162 Reserved interrupt */
.long 0 /* 163 Reserved interrupt */
.long INT_SHA_IRQHandler /* 164 */
.long 0 /* 165 Reserved interrupt */
.long 0 /* 166 Reserved interrupt */
.long INT_AES_IRQHandler /* 167 */
.long 0 /* 168 Reserved interrupt */
.long INT_DES_IRQHandler /* 169 */
.long 0 /* 170 Reserved interrupt */
.long 0 /* 171 Reserved interrupt */
.long 0 /* 172 Reserved interrupt */
.long 0 /* 173 Reserved interrupt */
.long 0 /* 174 Reserved interrupt */
.long INT_MMCHS_IRQHandler /* 175 */
.long 0 /* 176 Reserved interrupt */
.long INT_I2S_IRQHandler /* 177 */
.long 0 /* 178 Reserved interrupt */
.long INT_CAMERA_IRQHandler /* 179 */
.long 0 /* 180 Reserved interrupt */
.long 0 /* 181 Reserved interrupt */
.long 0 /* 182 Reserved interrupt */
.long 0 /* 183 Reserved interrupt */
.long 0 /* 184 Reserved interrupt */
.long 0 /* 185 Reserved interrupt */
.long 0 /* 186 Reserved interrupt */
.long INT_NWPIC_IRQHandler /* 187 */
.long INT_PRCM_IRQHandler /* 188 */
.long 0 /* 189 Reserved interrupt */
.long 0 /* 190 Reserved interrupt */
.long INT_SSPI_IRQHandler /* 191 */
.long INT_GSPI_IRQHandler /* 192 */
.long INT_LSPI_IRQHandler /* 193 */
.long 0 /* 194 Reserved interrupt */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler INT_GPIOA0_IRQHandler
def_irq_handler INT_GPIOA1_IRQHandler
def_irq_handler INT_GPIOA2_IRQHandler
def_irq_handler INT_GPIOA3_IRQHandler
def_irq_handler INT_UARTA0_IRQHandler
def_irq_handler INT_UARTA1_IRQHandler
def_irq_handler INT_I2CA0_IRQHandler
def_irq_handler INT_ADCCH0_IRQHandler
def_irq_handler INT_ADCCH1_IRQHandler
def_irq_handler INT_ADCCH2_IRQHandler
def_irq_handler INT_ADCCH3_IRQHandler
def_irq_handler INT_WDT_IRQHandler
def_irq_handler INT_TIMERA0A_IRQHandler
def_irq_handler INT_TIMERA0B_IRQHandler
def_irq_handler INT_TIMERA1A_IRQHandler
def_irq_handler INT_TIMERA1B_IRQHandler
def_irq_handler INT_TIMERA2A_IRQHandler
def_irq_handler INT_TIMERA2B_IRQHandler
def_irq_handler INT_FLASH_IRQHandler
def_irq_handler INT_TIMERA3A_IRQHandler
def_irq_handler INT_TIMERA3B_IRQHandler
def_irq_handler INT_UDMA_IRQHandler
def_irq_handler INT_UDMAERR_IRQHandler
def_irq_handler INT_SHA_IRQHandler
def_irq_handler INT_AES_IRQHandler
def_irq_handler INT_DES_IRQHandler
def_irq_handler INT_MMCHS_IRQHandler
def_irq_handler INT_I2S_IRQHandler
def_irq_handler INT_CAMERA_IRQHandler
def_irq_handler INT_NWPIC_IRQHandler
def_irq_handler INT_PRCM_IRQHandler
def_irq_handler INT_SSPI_IRQHandler
def_irq_handler INT_GSPI_IRQHandler
def_irq_handler INT_LSPI_IRQHandler
.end

100
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/CC3220SF.icf Normal file
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/* Device specific values */
define symbol ROM_START = 0x01000000;
define symbol ROM_SIZE = 0x100000;
define symbol FLASH_HDR_START = ROM_START;
define symbol FLASH_HDR_SIZE = 0x800;
define symbol RAM_START = 0x20000000;
define symbol RAM_SIZE = 0x40000;
define symbol VECTORS = 195; /* This value must match NVIC_NUM_VECTORS */
/* Common - Do not change */
if (isdefinedsymbol(MBED_APP_START)) {
/*
* There're two cases if MBED_APP_START is defined.
* Case 1: MBED_APP_START is defined as ROM_START, this happens when restrict_size is turned on, most likely for bootloader build.
* In this build, include FLASH_HDR region.
*/
if (MBED_APP_START == ROM_START) {
define symbol FLASH_HDR_INCLUDED = 1;
if (isdefinedsymbol(MBED_APP_SIZE)) {
define symbol ROM_EXEC_START = (ROM_START + FLASH_HDR_SIZE);
define symbol ROM_EXEC_SIZE = (MBED_APP_SIZE - FLASH_HDR_SIZE);
}
}
else {
/*
* Case 2: MBED_APP_START is defined as a value greater than ROM_START, this is most likely a build other than the bootloader. E.g., the MCC build.
* In this build, exclude FLASH_HDR region. This workarounds an issue in managed boodloader MCC build where the jump address and stack pointer point to the cookie area
*/
define symbol FLASH_HDR_INCLUDED = 0;
define symbol ROM_EXEC_START = MBED_APP_START;
if (isdefinedsymbol(MBED_APP_SIZE)) {
define symbol ROM_EXEC_SIZE= MBED_APP_SIZE;
}
else {
define symbol ROM_EXEC_SIZE = (ROM_SIZE- (MBED_APP_START - ROM_START));
}
}
}
else {
/*
* MBED_APP_START is not defined. This is most likely a bootloader build, or other apps that do not require boodloader.
* In this build, include FLASH_HDR region
*/
define symbol FLASH_HDR_INCLUDED = 1;
define symbol ROM_EXEC_START = (ROM_START + FLASH_HDR_SIZE);
if (isdefinedsymbol (MBED_APP_SIZE)) {
define symbol ROM_EXEC_SIZE = (MBED_APP_SIZE - FLASH_HDR_SIZE);
}
else {
define symbol ROM_EXEC_SIZE = (ROM_SIZE - FLASH_HDR_SIZE);
}
}
/* Round up VECTORS_SIZE to 8 bytes */
define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
/* boot stack size*/
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
/* Place the boot stack at the top of the RAM */
define symbol CSTACK_START = (RAM_START + RAM_SIZE - MBED_BOOT_STACK_SIZE);
define symbol CSTACK_SIZE = MBED_BOOT_STACK_SIZE;
/* The rest of RAM */
define symbol RAM_REGION_START = (RAM_START + VECTORS_SIZE);
define symbol RAM_REGION_SIZE = (RAM_SIZE - VECTORS_SIZE - MBED_BOOT_STACK_SIZE);
define memory mem with size = 4G;
/* ROM regions */
define region FLASH_HDR_region = mem:[from FLASH_HDR_START size FLASH_HDR_SIZE];
define region FLASH_region = mem:[from ROM_EXEC_START size ROM_EXEC_SIZE];
/* RAM regions */
define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
define region CSTACK_region = mem:[from CSTACK_START size CSTACK_SIZE];
if (FLASH_HDR_INCLUDED == 1) {
keep {section .dbghdr};
place in FLASH_HDR_region { readonly section .dbghdr };
}
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem: ROM_EXEC_START { readonly section .intvec };
place in FLASH_region { readonly };
define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
place in CSTACK_region { block CSTACK };
define symbol __size_heap__ = 0x10000;
define block HEAP with expanding size, alignment = 8, minimum size = __size_heap__ { };
place in RAM_region { block HEAP, readwrite, zeroinit };

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/TOOLCHAIN_IAR/startup_CC3220SF.S Normal file
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;/**************************************************************************//**
; * @file startup_CC3220SF.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * Device CC3220SF
; * @version V5.00
; * @date 07. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __Vectors
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD INT_GPIOA0_IRQHandler /* 16 */
DCD INT_GPIOA1_IRQHandler /* 17 */
DCD INT_GPIOA2_IRQHandler /* 18 */
DCD INT_GPIOA3_IRQHandler /* 19 */
DCD 0 /* 20 Reserved interrupt */
DCD INT_UARTA0_IRQHandler /* 21 */
DCD INT_UARTA1_IRQHandler /* 22 */
DCD 0 /* 23 Reserved interrupt */
DCD INT_I2CA0_IRQHandler /* 24 */
DCD 0 /* 25 Reserved interrupt */
DCD 0 /* 26 Reserved interrupt */
DCD 0 /* 27 Reserved interrupt */
DCD 0 /* 28 Reserved interrupt */
DCD 0 /* 29 Reserved interrupt */
DCD INT_ADCCH0_IRQHandler /* 30 */
DCD INT_ADCCH1_IRQHandler /* 31 */
DCD INT_ADCCH2_IRQHandler /* 32 */
DCD INT_ADCCH3_IRQHandler /* 33 */
DCD INT_WDT_IRQHandler /* 34 */
DCD INT_TIMERA0A_IRQHandler /* 35 */
DCD INT_TIMERA0B_IRQHandler /* 36 */
DCD INT_TIMERA1A_IRQHandler /* 37 */
DCD INT_TIMERA1B_IRQHandler /* 38 */
DCD INT_TIMERA2A_IRQHandler /* 39 */
DCD INT_TIMERA2B_IRQHandler /* 40 */
DCD 0 /* 41 Reserved interrupt */
DCD 0 /* 42 Reserved interrupt */
DCD 0 /* 43 Reserved interrupt */
DCD 0 /* 44 Reserved interrupt */
DCD INT_FLASH_IRQHandler /* 45 */
DCD 0 /* 46 Reserved interrupt */
DCD 0 /* 47 Reserved interrupt */
DCD 0 /* 48 Reserved interrupt */
DCD 0 /* 49 Reserved interrupt */
DCD 0 /* 50 Reserved interrupt */
DCD INT_TIMERA3A_IRQHandler /* 51 */
DCD INT_TIMERA3B_IRQHandler /* 52 */
DCD 0 /* 53 Reserved interrupt */
DCD 0 /* 54 Reserved interrupt */
DCD 0 /* 55 Reserved interrupt */
DCD 0 /* 56 Reserved interrupt */
DCD 0 /* 57 Reserved interrupt */
DCD 0 /* 58 Reserved interrupt */
DCD 0 /* 59 Reserved interrupt */
DCD 0 /* 60 Reserved interrupt */
DCD 0 /* 61 Reserved interrupt */
DCD INT_UDMA_IRQHandler /* 62 */
DCD INT_UDMAERR_IRQHandler /* 63 */
DCD 0 /* 64 Reserved interrupt */
DCD 0 /* 65 Reserved interrupt */
DCD 0 /* 66 Reserved interrupt */
DCD 0 /* 67 Reserved interrupt */
DCD 0 /* 68 Reserved interrupt */
DCD 0 /* 69 Reserved interrupt */
DCD 0 /* 70 Reserved interrupt */
DCD 0 /* 71 Reserved interrupt */
DCD 0 /* 72 Reserved interrupt */
DCD 0 /* 73 Reserved interrupt */
DCD 0 /* 74 Reserved interrupt */
DCD 0 /* 75 Reserved interrupt */
DCD 0 /* 76 Reserved interrupt */
DCD 0 /* 77 Reserved interrupt */
DCD 0 /* 78 Reserved interrupt */
DCD 0 /* 79 Reserved interrupt */
DCD 0 /* 80 Reserved interrupt */
DCD 0 /* 81 Reserved interrupt */
DCD 0 /* 82 Reserved interrupt */
DCD 0 /* 83 Reserved interrupt */
DCD 0 /* 84 Reserved interrupt */
DCD 0 /* 85 Reserved interrupt */
DCD 0 /* 86 Reserved interrupt */
DCD 0 /* 87 Reserved interrupt */
DCD 0 /* 88 Reserved interrupt */
DCD 0 /* 89 Reserved interrupt */
DCD 0 /* 90 Reserved interrupt */
DCD 0 /* 91 Reserved interrupt */
DCD 0 /* 92 Reserved interrupt */
DCD 0 /* 93 Reserved interrupt */
DCD 0 /* 94 Reserved interrupt */
DCD 0 /* 95 Reserved interrupt */
DCD 0 /* 96 Reserved interrupt */
DCD 0 /* 97 Reserved interrupt */
DCD 0 /* 98 Reserved interrupt */
DCD 0 /* 99 Reserved interrupt */
DCD 0 /* 100 Reserved interrupt */
DCD 0 /* 101 Reserved interrupt */
DCD 0 /* 102 Reserved interrupt */
DCD 0 /* 103 Reserved interrupt */
DCD 0 /* 104 Reserved interrupt */
DCD 0 /* 105 Reserved interrupt */
DCD 0 /* 106 Reserved interrupt */
DCD 0 /* 107 Reserved interrupt */
DCD 0 /* 108 Reserved interrupt */
DCD 0 /* 109 Reserved interrupt */
DCD 0 /* 110 Reserved interrupt */
DCD 0 /* 111 Reserved interrupt */
DCD 0 /* 112 Reserved interrupt */
DCD 0 /* 113 Reserved interrupt */
DCD 0 /* 114 Reserved interrupt */
DCD 0 /* 115 Reserved interrupt */
DCD 0 /* 116 Reserved interrupt */
DCD 0 /* 117 Reserved interrupt */
DCD 0 /* 118 Reserved interrupt */
DCD 0 /* 119 Reserved interrupt */
DCD 0 /* 120 Reserved interrupt */
DCD 0 /* 121 Reserved interrupt */
DCD 0 /* 122 Reserved interrupt */
DCD 0 /* 123 Reserved interrupt */
DCD 0 /* 124 Reserved interrupt */
DCD 0 /* 125 Reserved interrupt */
DCD 0 /* 126 Reserved interrupt */
DCD 0 /* 127 Reserved interrupt */
DCD 0 /* 128 Reserved interrupt */
DCD 0 /* 129 Reserved interrupt */
DCD 0 /* 130 Reserved interrupt */
DCD 0 /* 131 Reserved interrupt */
DCD 0 /* 132 Reserved interrupt */
DCD 0 /* 133 Reserved interrupt */
DCD 0 /* 134 Reserved interrupt */
DCD 0 /* 135 Reserved interrupt */
DCD 0 /* 136 Reserved interrupt */
DCD 0 /* 137 Reserved interrupt */
DCD 0 /* 138 Reserved interrupt */
DCD 0 /* 139 Reserved interrupt */
DCD 0 /* 140 Reserved interrupt */
DCD 0 /* 141 Reserved interrupt */
DCD 0 /* 142 Reserved interrupt */
DCD 0 /* 143 Reserved interrupt */
DCD 0 /* 144 Reserved interrupt */
DCD 0 /* 145 Reserved interrupt */
DCD 0 /* 146 Reserved interrupt */
DCD 0 /* 147 Reserved interrupt */
DCD 0 /* 148 Reserved interrupt */
DCD 0 /* 149 Reserved interrupt */
DCD 0 /* 150 Reserved interrupt */
DCD 0 /* 151 Reserved interrupt */
DCD 0 /* 152 Reserved interrupt */
DCD 0 /* 153 Reserved interrupt */
DCD 0 /* 154 Reserved interrupt */
DCD 0 /* 155 Reserved interrupt */
DCD 0 /* 156 Reserved interrupt */
DCD 0 /* 157 Reserved interrupt */
DCD 0 /* 158 Reserved interrupt */
DCD 0 /* 159 Reserved interrupt */
DCD 0 /* 160 Reserved interrupt */
DCD 0 /* 161 Reserved interrupt */
DCD 0 /* 162 Reserved interrupt */
DCD 0 /* 163 Reserved interrupt */
DCD INT_SHA_IRQHandler /* 164 */
DCD 0 /* 165 Reserved interrupt */
DCD 0 /* 166 Reserved interrupt */
DCD INT_AES_IRQHandler /* 167 */
DCD 0 /* 168 Reserved interrupt */
DCD INT_DES_IRQHandler /* 169 */
DCD 0 /* 170 Reserved interrupt */
DCD 0 /* 171 Reserved interrupt */
DCD 0 /* 172 Reserved interrupt */
DCD 0 /* 173 Reserved interrupt */
DCD 0 /* 174 Reserved interrupt */
DCD INT_MMCHS_IRQHandler /* 175 */
DCD 0 /* 176 Reserved interrupt */
DCD INT_I2S_IRQHandler /* 177 */
DCD 0 /* 178 Reserved interrupt */
DCD INT_CAMERA_IRQHandler /* 179 */
DCD 0 /* 180 Reserved interrupt */
DCD 0 /* 181 Reserved interrupt */
DCD 0 /* 182 Reserved interrupt */
DCD 0 /* 183 Reserved interrupt */
DCD 0 /* 184 Reserved interrupt */
DCD 0 /* 185 Reserved interrupt */
DCD 0 /* 186 Reserved interrupt */
DCD INT_NWPIC_IRQHandler /* 187 */
DCD INT_PRCM_IRQHandler /* 188 */
DCD 0 /* 189 Reserved interrupt */
DCD 0 /* 190 Reserved interrupt */
DCD INT_SSPI_IRQHandler /* 191 */
DCD INT_GSPI_IRQHandler /* 192 */
DCD INT_LSPI_IRQHandler /* 193 */
DCD 0 /* 194 Reserved interrupt */
__Vectors EQU __vector_table
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK INT_GPIOA0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_GPIOA0_IRQHandler
B INT_GPIOA0_IRQHandler
PUBWEAK INT_GPIOA1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_GPIOA1_IRQHandler
B INT_GPIOA1_IRQHandler
PUBWEAK INT_GPIOA2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_GPIOA2_IRQHandler
B INT_GPIOA2_IRQHandler
PUBWEAK INT_GPIOA3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_GPIOA3_IRQHandler
B INT_GPIOA3_IRQHandler
PUBWEAK INT_UARTA0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_UARTA0_IRQHandler
B INT_UARTA0_IRQHandler
PUBWEAK INT_UARTA1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_UARTA1_IRQHandler
B INT_UARTA1_IRQHandler
PUBWEAK INT_I2CA0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_I2CA0_IRQHandler
B INT_I2CA0_IRQHandler
PUBWEAK INT_ADCCH0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_ADCCH0_IRQHandler
B INT_ADCCH0_IRQHandler
PUBWEAK INT_ADCCH1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_ADCCH1_IRQHandler
B INT_ADCCH1_IRQHandler
PUBWEAK INT_ADCCH2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_ADCCH2_IRQHandler
B INT_ADCCH2_IRQHandler
PUBWEAK INT_ADCCH3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_ADCCH3_IRQHandler
B INT_ADCCH3_IRQHandler
PUBWEAK INT_WDT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_WDT_IRQHandler
B INT_WDT_IRQHandler
PUBWEAK INT_TIMERA0A_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_TIMERA0A_IRQHandler
B INT_TIMERA0A_IRQHandler
PUBWEAK INT_TIMERA0B_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_TIMERA0B_IRQHandler
B INT_TIMERA0B_IRQHandler
PUBWEAK INT_TIMERA1A_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_TIMERA1A_IRQHandler
B INT_TIMERA1A_IRQHandler
PUBWEAK INT_TIMERA1B_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_TIMERA1B_IRQHandler
B INT_TIMERA1B_IRQHandler
PUBWEAK INT_TIMERA2A_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_TIMERA2A_IRQHandler
B INT_TIMERA2A_IRQHandler
PUBWEAK INT_TIMERA2B_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_TIMERA2B_IRQHandler
B INT_TIMERA2B_IRQHandler
PUBWEAK INT_FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_FLASH_IRQHandler
B INT_FLASH_IRQHandler
PUBWEAK INT_TIMERA3A_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_TIMERA3A_IRQHandler
B INT_TIMERA3A_IRQHandler
PUBWEAK INT_TIMERA3B_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_TIMERA3B_IRQHandler
B INT_TIMERA3B_IRQHandler
PUBWEAK INT_UDMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_UDMA_IRQHandler
B INT_UDMA_IRQHandler
PUBWEAK INT_UDMAERR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_UDMAERR_IRQHandler
B INT_UDMAERR_IRQHandler
PUBWEAK INT_SHA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_SHA_IRQHandler
B INT_SHA_IRQHandler
PUBWEAK INT_AES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_AES_IRQHandler
B INT_AES_IRQHandler
PUBWEAK INT_DES_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_DES_IRQHandler
B INT_DES_IRQHandler
PUBWEAK INT_MMCHS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_MMCHS_IRQHandler
B INT_MMCHS_IRQHandler
PUBWEAK INT_I2S_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_I2S_IRQHandler
B INT_I2S_IRQHandler
PUBWEAK INT_CAMERA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_CAMERA_IRQHandler
B INT_CAMERA_IRQHandler
PUBWEAK INT_NWPIC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_NWPIC_IRQHandler
B INT_NWPIC_IRQHandler
PUBWEAK INT_PRCM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_PRCM_IRQHandler
B INT_PRCM_IRQHandler
PUBWEAK INT_SSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_SSPI_IRQHandler
B INT_SSPI_IRQHandler
PUBWEAK INT_GSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_GSPI_IRQHandler
B INT_GSPI_IRQHandler
PUBWEAK INT_LSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
INT_LSPI_IRQHandler
B INT_LSPI_IRQHandler
END

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cc3200_simplelink.cpp Normal file
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/* CC3200_SIMPLELINK Class
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdlib.h>
#include "cc3200_simplelink.h"
#include "nsapi_types.h"
#include "ip4string.h"
#include "CC3220SF_Init.h"
#define SOCKET_IS_NON_BLOCKING (1)
#define SL_STOP_TIMEOUT (200)
CC3200_SIMPLELINK::CC3200_SIMPLELINK()
: _connect_error(0),
_initialized(false),
_current_role(0),
_fail(false),
_closed(false),
_connection_status(NSAPI_STATUS_DISCONNECTED),
_connected_ssid(),
_connected_channel(0),
_timeout(CC3200_SIMPLELINK_MISC_TIMEOUT)
{
memset(_ip_buffer, 0, sizeof(_ip_buffer));
memset(_gateway_buffer, 0, sizeof(_gateway_buffer));
memset(_netmask_buffer, 0, sizeof(_netmask_buffer));
memset(_mac_buffer, 0, sizeof(_mac_buffer));
}
/*!
\brief Configure SimpleLink to default state.
This routine configures the device to a default state.
It's important to note that this is one example for a 'restore to default state'
function, which meet the needs of this application, 'Network Terminal'. User who
wish to incorporate this function into he's app, must adjust the implementation
and make sure it meets he's needs.
\return Upon successful completion, the function shall return 0.
In case of failure, this function would return -1.
*/
nsapi_error_t CC3200_SIMPLELINK::initialize()
{
int ret = NSAPI_ERROR_OK;
if (!_initialized)
{
ret = CC3220SF_initSimplelink();
if (ret == 0)
{
_current_role = WIFI_ROLE_STATION;
_initialized = true;
}
else
{
printf("simplelink_powerup failed with %d", ret);
return NSAPI_ERROR_DEVICE_ERROR;
}
}
return NSAPI_ERROR_OK;
}
bool CC3200_SIMPLELINK::startup(int role)
{
int32_t ret_val = -1;
if (role != WIFI_ROLE_STATION && role != WIFI_ROLE_AP && role != WIFI_ROLE_P2P)
{
return false;
}
if (role != _current_role)
{
ret_val = sl_WlanSetMode(role);
assert(ret_val == 0);
/* For changes to take affect, we restart the NWP */
ret_val = sl_Stop(SL_STOP_TIMEOUT);
assert(ret_val == 0);
ret_val = sl_Start(0, 0, 0);
assert(ret_val == 0);
_current_role = role;
}
return true;
}
// TODO: This will involve file system write
bool CC3200_SIMPLELINK::dhcp(bool enabled, int role)
{
#ifdef FILE_SYSTEM_ENABLE
int32_t ret_val = -1;
uint32_t config_id, config_option;
if (role != WIFI_ROLE_STATION && role != WIFI_ROLE_AP)
{
return false;
}
if (role == WIFI_ROLE_STATION)
{
config_id = SL_NETCFG_IPV4_STA_ADDR_MODE;
}
else
{
config_id = SL_NETCFG_IPV4_AP_ADDR_MODE;
}
if (enabled)
{
config_option = SL_NETCFG_ADDR_DHCP;
ret_val = sl_NetCfgSet(config_id, config_option, 0, 0);
}
else
{
config_option = SL_NETCFG_ADDR_STATIC;
SlNetCfgIpV4Args_t ipV4;
ipV4.Ip = (_u32)SL_IPV4_VAL(_ip_buffer[0],_ip_buffer[1],_ip_buffer[2],_ip_buffer[3]); // _u32 IP address
ipV4.IpMask = (_u32)SL_IPV4_VAL(_netmask_buffer[0],_netmask_buffer[1],_netmask_buffer[2],_netmask_buffer[3]); // _u32 Subnet mask for this STA/P2P
ipV4.IpGateway = (_u32)SL_IPV4_VAL(_gateway_buffer[0],_gateway_buffer[1],_gateway_buffer[2],_gateway_buffer[3]); // _u32 Default gateway address
ipV4.IpDnsServer = (_u32)SL_IPV4_VAL(_dns_server_buffer[0],_dns_server_buffer[1],_dns_server_buffer[2],_dns_server_buffer[3]); // _u32 DNS server address
ret_val = sl_NetCfgSet(config_id, config_option, sizeof(SlNetCfgIpV4Args_t), (_u8 *)&ipV4);
}
if (ret_val == 0)
{
sl_Stop(0);
sl_Start(NULL,NULL,NULL);
return true;
}
else
{
return false;
}
#else
return true;
#endif
}
nsapi_error_t CC3200_SIMPLELINK::connect(const char *ssid, const char *passPhrase, nsapi_security_t security)
{
nsapi_error_t status;
_i16 ret;
SlWlanSecParams_t sec_params;
if (!ssid || (!passPhrase && security != NSAPI_SECURITY_NONE))
{
printf("Invalid credentials\r\n");
return NSAPI_ERROR_PARAMETER;
}
status = initialize();
if(status != NSAPI_ERROR_OK)
{
return status;
}
strncpy(_connected_ssid, ssid, sizeof(_connected_ssid));
memset((void*)&sec_params, 0, sizeof(sec_params));
startup(CC3200_SIMPLELINK::WIFI_ROLE_STATION);
if(status != NSAPI_ERROR_OK)
{
return status;
}
sec_params.Key = (signed char*)passPhrase;
sec_params.KeyLen = strlen(passPhrase);
switch (security) {
case NSAPI_SECURITY_WPA:
case NSAPI_SECURITY_WPA2:
case NSAPI_SECURITY_WPA_WPA2:
sec_params.Type = SL_WLAN_SEC_TYPE_WPA_WPA2;
break;
case NSAPI_SECURITY_WEP:
sec_params.Type = SL_WLAN_SEC_TYPE_WEP;
break;
case NSAPI_SECURITY_NONE:
sec_params.Type = SL_WLAN_SEC_TYPE_OPEN;
break;
default:
return NSAPI_ERROR_PARAMETER;
}
ret = sl_WlanConnect((const _i8*)ssid,(const _i16)(strlen(ssid)),(const _u8 *)NULL,
(const SlWlanSecParams_t*)&sec_params ,(const SlWlanSecParamsExt_t*)NULL);
if (ret != SL_RET_CODE_OK) {
return NSAPI_ERROR_NO_CONNECTION;
}
return NSAPI_ERROR_OK;
}
bool CC3200_SIMPLELINK::disconnect()
{
return (sl_WlanDisconnect() == 0);
}
const char *CC3200_SIMPLELINK::getIPAddress()
{
int i;
_u16 config_id;
_u8 ip4addr[4];
if (_current_role == WIFI_ROLE_STATION) // TODO: Station or P2P client
{
config_id = SL_NETCFG_IPV4_STA_ADDR_MODE;
}
else
{
config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; // AP or P2P go
}
_u16 len = sizeof(SlNetCfgIpV4Args_t);
_u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC
SlNetCfgIpV4Args_t ipV4 = {0};
sl_NetCfgGet(config_id,&ConfigOpt,&len,(_u8 *)&ipV4);
/*printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n",
(ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF",
(int)SL_IPV4_BYTE(ipV4.Ip,3),(int)SL_IPV4_BYTE(ipV4.Ip,2),(int)SL_IPV4_BYTE(ipV4.Ip,1),(int)SL_IPV4_BYTE(ipV4.Ip,0),
(int)SL_IPV4_BYTE(ipV4.IpMask,3),(int)SL_IPV4_BYTE(ipV4.IpMask,2),(int)SL_IPV4_BYTE(ipV4.IpMask,1),(int)SL_IPV4_BYTE(ipV4.IpMask,0),
(int)SL_IPV4_BYTE(ipV4.IpGateway,3),(int)SL_IPV4_BYTE(ipV4.IpGateway,2),(int)SL_IPV4_BYTE(ipV4.IpGateway,1),(int)SL_IPV4_BYTE(ipV4.IpGateway,0),
(int)SL_IPV4_BYTE(ipV4.IpDnsServer,3),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,2),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,1),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,0));*/
for (i = 0; i < 4; i ++)
{
ip4addr[i] = SL_IPV4_BYTE(ipV4.Ip,(3-i));
}
ip4tos((const void *)ip4addr, (char *)_ip_buffer);
return _ip_buffer;
}
const char *CC3200_SIMPLELINK::getMACAddress()
{
_u16 macAddressLen = SL_MAC_ADDR_LEN;
_u16 ConfigOpt = 0;
_u8 macAddress[SL_MAC_ADDR_LEN];
sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET,&ConfigOpt,&macAddressLen,macAddress);
// Format this into xx:xx:xx:xx:xx:xx
sprintf(_mac_buffer, "%2x:%2x:%2x:%2x:%2x:%2x",macAddress[0], macAddress[1], macAddress[2], macAddress[3], macAddress[4], macAddress[5]);
return _mac_buffer;
}
const char *CC3200_SIMPLELINK::getGateway()
{
int i;
_u16 config_id;
_u8 ip4addr[4];
if (_current_role == WIFI_ROLE_STATION) // TODO: Station or P2P client
{
config_id = SL_NETCFG_IPV4_STA_ADDR_MODE;
}
else
{
config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; // AP or P2P go
}
_u16 len = sizeof(SlNetCfgIpV4Args_t);
_u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC
SlNetCfgIpV4Args_t ipV4 = {0};
sl_NetCfgGet(config_id,&ConfigOpt,&len,(_u8 *)&ipV4);
/*printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n",
(ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF",
(int)SL_IPV4_BYTE(ipV4.Ip,3),(int)SL_IPV4_BYTE(ipV4.Ip,2),(int)SL_IPV4_BYTE(ipV4.Ip,1),(int)SL_IPV4_BYTE(ipV4.Ip,0),
(int)SL_IPV4_BYTE(ipV4.IpMask,3),(int)SL_IPV4_BYTE(ipV4.IpMask,2),(int)SL_IPV4_BYTE(ipV4.IpMask,1),(int)SL_IPV4_BYTE(ipV4.IpMask,0),
(int)SL_IPV4_BYTE(ipV4.IpGateway,3),(int)SL_IPV4_BYTE(ipV4.IpGateway,2),(int)SL_IPV4_BYTE(ipV4.IpGateway,1),(int)SL_IPV4_BYTE(ipV4.IpGateway,0),
(int)SL_IPV4_BYTE(ipV4.IpDnsServer,3),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,2),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,1),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,0));*/
for (i = 0; i < 4; i ++)
{
ip4addr[i] = SL_IPV4_BYTE(ipV4.IpGateway,(3-i));
}
ip4tos((const void *)ip4addr, (char *)_gateway_buffer);
return _gateway_buffer;
}
const char *CC3200_SIMPLELINK::getNetmask()
{
int i;
_u16 config_id;
_u8 ip4addr[4];
if (_current_role == WIFI_ROLE_STATION) // TODO: Station or P2P client
{
config_id = SL_NETCFG_IPV4_STA_ADDR_MODE;
}
else
{
config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; // AP or P2P go
}
_u16 len = sizeof(SlNetCfgIpV4Args_t);
_u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC
SlNetCfgIpV4Args_t ipV4 = {0};
sl_NetCfgGet(config_id,&ConfigOpt,&len,(_u8 *)&ipV4);
/*printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n",
(ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF",
(int)SL_IPV4_BYTE(ipV4.Ip,3),(int)SL_IPV4_BYTE(ipV4.Ip,2),(int)SL_IPV4_BYTE(ipV4.Ip,1),(int)SL_IPV4_BYTE(ipV4.Ip,0),
(int)SL_IPV4_BYTE(ipV4.IpMask,3),(int)SL_IPV4_BYTE(ipV4.IpMask,2),(int)SL_IPV4_BYTE(ipV4.IpMask,1),(int)SL_IPV4_BYTE(ipV4.IpMask,0),
(int)SL_IPV4_BYTE(ipV4.IpGateway,3),(int)SL_IPV4_BYTE(ipV4.IpGateway,2),(int)SL_IPV4_BYTE(ipV4.IpGateway,1),(int)SL_IPV4_BYTE(ipV4.IpGateway,0),
(int)SL_IPV4_BYTE(ipV4.IpDnsServer,3),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,2),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,1),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,0));*/
for (i = 0; i < 4; i ++)
{
ip4addr[i] = SL_IPV4_BYTE(ipV4.IpMask,(3-i));
}
ip4tos((const void *)ip4addr, (char *)_netmask_buffer);
return _netmask_buffer;
}
nsapi_error_t CC3200_SIMPLELINK::getDNS(unsigned char* ip4addr, uint32_t size)
{
int i;
_u16 config_id;
if (ip4addr == NULL || size < 4)
{
return NSAPI_ERROR_PARAMETER;
}
if (_current_role == WIFI_ROLE_STATION) // TODO: Station or P2P client
{
config_id = SL_NETCFG_IPV4_STA_ADDR_MODE;
}
else
{
config_id = SL_NETCFG_IPV4_AP_ADDR_MODE; // AP or P2P go
}
_u16 len = sizeof(SlNetCfgIpV4Args_t);
_u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC
SlNetCfgIpV4Args_t ipV4 = {0};
sl_NetCfgGet(config_id,&ConfigOpt,&len,(_u8 *)&ipV4);
/*printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n",
(ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF",
(int)SL_IPV4_BYTE(ipV4.Ip,3),(int)SL_IPV4_BYTE(ipV4.Ip,2),(int)SL_IPV4_BYTE(ipV4.Ip,1),(int)SL_IPV4_BYTE(ipV4.Ip,0),
(int)SL_IPV4_BYTE(ipV4.IpMask,3),(int)SL_IPV4_BYTE(ipV4.IpMask,2),(int)SL_IPV4_BYTE(ipV4.IpMask,1),(int)SL_IPV4_BYTE(ipV4.IpMask,0),
(int)SL_IPV4_BYTE(ipV4.IpGateway,3),(int)SL_IPV4_BYTE(ipV4.IpGateway,2),(int)SL_IPV4_BYTE(ipV4.IpGateway,1),(int)SL_IPV4_BYTE(ipV4.IpGateway,0),
(int)SL_IPV4_BYTE(ipV4.IpDnsServer,3),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,2),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,1),(int)SL_IPV4_BYTE(ipV4.IpDnsServer,0));*/
for (i = 0; i < 4; i ++)
{
ip4addr[i] = SL_IPV4_BYTE(ipV4.IpDnsServer,(3-i));
}
return NSAPI_ERROR_OK;
}
int CC3200_SIMPLELINK::scan(WiFiAccessPoint *res, unsigned count)
{
_u8 entries_count = MAX_SCAN_ENTRIES;
uint8_t triggeredScanTrials = 0;
_i16 ret = 0;
if ((count != 0) && (count < MAX_SCAN_ENTRIES))
{
entries_count = count;
}
/* Get scan results from NWP - results would be placed inside the local buffer first */
ret = sl_WlanGetNetworkList(0, entries_count, netEntries);
/* If scan policy isn't set, invoking 'sl_WlanGetNetworkList()' for the first time triggers 'one shot' scan.
* The scan parameters would be according to the system persistent settings on enabled channels.
* For more information, see: <simplelink user guide, page: pr.>
*/
if(SL_ERROR_WLAN_GET_NETWORK_LIST_EAGAIN == ret)
{
while(triggeredScanTrials < MAX_SCAN_ATTEMPTS)
{
/* We wait for one second for the NWP to complete the initiated scan and collect results */
wait_ms(1000);
/* Collect results form one-shot scans.*/
ret = sl_WlanGetNetworkList(0, entries_count, netEntries);
if(ret > 0)
{
break;
}
else
{
/* If NWP results aren't ready, try 'MAX_SCAN_ATTEMPTS' to get results */
triggeredScanTrials++ ;
printf("Tried %d times", triggeredScanTrials);
}
}
if (count == 0 || res == NULL)
{
if (ret > 0)
{
return ret;
}
else
{
printf("\n\r[scan] : Unable to retrieve the network list\n\r");
return 0;
}
}
}
if (ret <= 0)
{
printf("\n\r[scan] : Unable to retrieve the network list\n\r");
return 0;
}
// scan is successful if code reaches here.
if (res && count)
{
unsigned i;
for (i = 0; i < count; i ++)
{
nsapi_wifi_ap_t ap;
netEntries[i].Ssid[netEntries[i].SsidLen] = 0; /* Ensure the SSID is null terminated */
memset((void*)&ap, 0x00, sizeof(nsapi_wifi_ap_t));
memcpy(ap.ssid, netEntries[i].Ssid, netEntries[i].SsidLen);
memcpy(ap.bssid, netEntries[i].Bssid, 6);
switch (SL_WLAN_SCAN_RESULT_SEC_TYPE_BITMAP(netEntries[i].SecurityInfo))
{
case SL_WLAN_SECURITY_TYPE_BITMAP_OPEN:
ap.security = NSAPI_SECURITY_NONE;
break;
case SL_WLAN_SECURITY_TYPE_BITMAP_WEP:
ap.security = NSAPI_SECURITY_WEP;
break;
case SL_WLAN_SECURITY_TYPE_BITMAP_WPA:
ap.security = NSAPI_SECURITY_WPA;
break;
case SL_WLAN_SECURITY_TYPE_BITMAP_WPA2:
ap.security = NSAPI_SECURITY_WPA2;
break;
case (SL_WLAN_SECURITY_TYPE_BITMAP_WPA | SL_WLAN_SECURITY_TYPE_BITMAP_WPA2):
ap.security = NSAPI_SECURITY_WPA_WPA2;
break;
default:
ap.security = NSAPI_SECURITY_UNKNOWN;
break;
}
ap.rssi = netEntries[i].Rssi;
ap.channel = netEntries[i].Channel;
res[i] = WiFiAccessPoint(ap);
}
return count;
}
else // Either res == NULL or count == 0, return the number of scanned networks
{
return ret;
}
}
nsapi_error_t CC3200_SIMPLELINK::set_channel(int channel)
{
if (_current_role == WIFI_ROLE_STATION)
{
return NSAPI_ERROR_UNSUPPORTED;
}
_i16 Status = sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_CHANNEL, 1, (unsigned char*)&channel);
if (Status == SL_RET_CODE_OK)
{
_connected_channel = channel;
return NSAPI_ERROR_OK;
}
else if (Status == SL_ERROR_INVALID_PARAM)
{
return NSAPI_ERROR_PARAMETER;
}
else
{
return NSAPI_ERROR_DEVICE_ERROR;
}
}
nsapi_error_t CC3200_SIMPLELINK::dns_lookup(const char *name, char *ip, uint32_t ip_size, nsapi_version_t version)
{
_i16 Status;
SlNetAppDnsClientTime_t Time;
Time.MaxResponseTime = 2000; // Max DNS retry timeout, DNS request timeout changed every retry, start with 100Ms up to MaxResponseTime Ms
Time.NumOfRetries = 30; // number DNS retries before sl_NetAppDnsGetHostByName failed
Status = sl_NetAppSet(SL_NETAPP_DNS_CLIENT_ID, SL_NETAPP_DNS_CLIENT_TIME, sizeof(Time), (_u8*)&Time);
if( Status )
{
return NSAPI_ERROR_DNS_FAILURE;
}
if (name && ip)
{
if ((version == NSAPI_IPv4 || version == NSAPI_UNSPEC) && ip_size >= NSAPI_IPv4_BYTES)
{
if (sl_NetAppDnsGetHostByName((_i8*)name, strlen(name), (_u32 *)ip, SL_AF_INET) == 0)
{
printf("%s has ip %d.%d.%d.%d\n", name, (int)SL_IPV4_BYTE(*(_u32 *)ip,3),(int)SL_IPV4_BYTE(*(_u32 *)ip,2),(int)SL_IPV4_BYTE(*(_u32 *)ip,1),(int)SL_IPV4_BYTE(*(_u32 *)ip,0));
return NSAPI_ERROR_OK;
}
else
{
printf("sl_NetAppDnsGetHostByName failed\n");
return NSAPI_ERROR_DNS_FAILURE;
}
}
if (version == NSAPI_IPv6 && ip_size >= NSAPI_IPv6_BYTES)
{
if (sl_NetAppDnsGetHostByName((_i8*)name, strlen(name), (_u32 *)ip, SL_AF_INET6) == 0)
{
return NSAPI_ERROR_OK;
}
else
{
return NSAPI_ERROR_DNS_FAILURE;
}
}
}
return NSAPI_ERROR_DNS_FAILURE;
}
int8_t CC3200_SIMPLELINK::getRSSI()
{
int i;
// Match connected network
for (i = 0; i < MAX_SCAN_ENTRIES; i++)
{
if (strcmp((char*)netEntries[i].Ssid, _connected_ssid) == 0 && netEntries[i].Channel == _connected_channel)
{
break;
}
}
if (i < MAX_SCAN_ENTRIES)
{
return netEntries[i].Rssi;
}
else
{
printf("Unscanned network, initiate network scan to get valid RSSI.\n");
return 0;
}
}
int8_t CC3200_SIMPLELINK::get_current_wifi_mode()
{
return _current_role;
}
nsapi_connection_status_t CC3200_SIMPLELINK::get_connection_status() const
{
return _connection_status;
}
void CC3200_SIMPLELINK::set_connection_status(nsapi_connection_status_t status)
{
_connection_status = status;
if(_connection_status_cb)
{
_connection_status_cb(NSAPI_EVENT_CONNECTION_STATUS_CHANGE, _connection_status);
}
}
void CC3200_SIMPLELINK::attach(mbed::Callback<void(nsapi_event_t, intptr_t)> status_cb)
{
_connection_status_cb = status_cb;
}
nsapi_error_t CC3200_SIMPLELINK::open_socket(nsapi_protocol_t proto)
{
int32_t sock = 0;
if (proto == NSAPI_TCP)
{
sock = sl_Socket(SL_AF_INET, SL_SOCK_STREAM, 0);
}
else if (proto == NSAPI_UDP)
{
sock = sl_Socket(SL_AF_INET, SL_SOCK_DGRAM, 0);
}
if (sock >= 0)
{
return sock;
}
else
{
printf("open_socket failed with %d\n", (int)sock);
return NSAPI_ERROR_NO_SOCKET;
}
}
bool CC3200_SIMPLELINK::close_socket(uint32_t sock)
{
int32_t retcode = 0;
retcode = sl_Close(sock);
if (retcode == 0)
{
return true;
}
else
{
printf("close_socket failed with %d\n", (int)retcode);
return false;
}
}
nsapi_error_t CC3200_SIMPLELINK::setsockopt(uint32_t sd, int level,
int optname, const void *optval, unsigned optlen)
{
_i16 retcode = sl_SetSockOpt((_i16)sd, level, optname, optval, optlen);
if (retcode == 0)
{
return NSAPI_ERROR_OK;
}
else
{
printf ("sl_SetSockOpt failed with %d\n", (int)retcode);
return NSAPI_ERROR_DEVICE_ERROR;
}
}
nsapi_error_t CC3200_SIMPLELINK::getsockopt(uint32_t sd, int level,
int optname, void *optval, unsigned* optlen)
{
_i16 retcode =sl_GetSockOpt((_i16)sd, level, optname, optval, (SlSocklen_t*)optlen);
if (retcode == 0)
{
return NSAPI_ERROR_OK;
}
else
{
printf ("sl_GetSockOpt failed with %d\n", (int)retcode);
return NSAPI_ERROR_DEVICE_ERROR;
}
}
nsapi_error_t CC3200_SIMPLELINK::connect_socket(uint32_t sd, const SocketAddress &sock_addr)
{
sockAddr_t sAddr;
SlSockAddr_t* sa;
int32_t addrSize;
int32_t status = -1;
short int nonBlocking = SOCKET_IS_NON_BLOCKING;
_fill_sl_address(sAddr, sa, addrSize, sock_addr);
if (1 == nonBlocking)
{
// non-blocking
status = sl_SetSockOpt((short int)sd, SL_SOL_SOCKET, SL_SO_NONBLOCKING, &nonBlocking, sizeof(nonBlocking));
if(status < 0)
{
printf("sl_SetSockOpt failed with %d\n\r", (int)status);
return NSAPI_ERROR_DEVICE_ERROR;
}
}
status = -1;
while (status < 0)
{
status = sl_Connect((short int)sd, sa, (short int)addrSize);
// on a non-blocking connect, retry if SL_ERROR_BSD_EALREADY is returned
{
if (status == SL_ERROR_BSD_EALREADY && 1 == nonBlocking)
{
wait_ms(1);
continue;
}
else if (status < 0)
{
printf("sl_Connect failed with %d\n", (int)status);
return NSAPI_ERROR_DEVICE_ERROR;
}
}
}
return NSAPI_ERROR_OK;
}
nsapi_error_t CC3200_SIMPLELINK::bind_socket(uint32_t sd, const SocketAddress &sock_addr)
{
sockAddr_t sAddr;
SlSockAddr_t* sa;
int32_t addrSize;
int32_t status = -1;
_fill_sl_address(sAddr, sa, addrSize, sock_addr);
status = sl_Bind(sd, sa, addrSize);
if (status == 0)
{
return NSAPI_ERROR_OK;
}
else
{
printf ("sl_Bind failed with %d\n", (int)status);
return NSAPI_ERROR_DEVICE_ERROR;
}
}
int CC3200_SIMPLELINK::sendto_socket(uint32_t sd, const void * buf, uint32_t bufLen, const SocketAddress &sock_addr)
{
sockAddr_t sAddr;
SlSockAddr_t* sa;
int32_t addrSize;
int32_t status = -1;
_fill_sl_address(sAddr, sa, addrSize, sock_addr);
while (1)
{
status = sl_SendTo(sd, buf, bufLen, 0, sa, addrSize);
if (status == SL_ERROR_BSD_EAGAIN && 1 == SOCKET_IS_NON_BLOCKING)
{
wait_ms(1);
continue;
}
else if (status < 0)
{
printf ("sl_SendTo failed with %d\n", (int)status);
return NSAPI_ERROR_DEVICE_ERROR;
}
break;
}
return status;
}
int32_t CC3200_SIMPLELINK::send(int sd, const void *data, uint32_t size)
{
int32_t status = -1;
while (1)
{
status = sl_Send(sd, data, size, 0);
if (status == SL_ERROR_BSD_EAGAIN && 1 == SOCKET_IS_NON_BLOCKING)
{
wait_ms(1);
continue;
}
else if (status < 0)
{
printf ("sl_Send failed with %d\n", (int)status);
return NSAPI_ERROR_DEVICE_ERROR;
}
break;
}
return status;
}
int32_t CC3200_SIMPLELINK::recv(int sd, void *data, uint32_t size)
{
int32_t status = -1;
SlSockNonblocking_t BlockingOption;
struct SlTimeval_t TimeVal;
BlockingOption.NonBlockingEnabled = SOCKET_IS_NON_BLOCKING;
if (1 == SOCKET_IS_NON_BLOCKING)
{
// non-blocking
status = sl_SetSockOpt((short int)sd, SL_SOL_SOCKET, SL_SO_NONBLOCKING, (_u8*)&BlockingOption,sizeof(BlockingOption));
if(status < 0)
{
printf("sl_SetSockOpt failed with %d\n\r", (int)status);
return NSAPI_ERROR_DEVICE_ERROR;
}
}
else
{
/* In case of blocking, a timeout for sl_RecvFrom will be set to TimeVal
* When timeout is expired sl_Recv will return SL_ERROR_BSD_EAGAIN */
TimeVal.tv_sec = _timeout;
TimeVal.tv_usec = 0;
status = sl_SetSockOpt(sd,SL_SOL_SOCKET,SL_SO_RCVTIMEO,
(uint8_t *)&TimeVal,
sizeof(TimeVal));
if(status < 0)
{
printf ("sl_SetSockOpt failed with %d\n", (int)status);
return NSAPI_ERROR_DEVICE_ERROR;
}
}
memset((void *)data, 0, size);
status = sl_Recv(sd, data, size, 0);
if(status == SL_ERROR_BSD_EAGAIN)
{
if (1 == SOCKET_IS_NON_BLOCKING)
{
return NSAPI_ERROR_WOULD_BLOCK;
}
else
{
printf ("Timeout expired before receiving packet\n");
return NSAPI_ERROR_TIMEOUT;
}
}
else if(status < 0)
{
printf ("sl_Recv failed with %d\n", (int)status);
return NSAPI_ERROR_DEVICE_ERROR;
}
else
{
return status;
}
}
int32_t CC3200_SIMPLELINK::recvfrom(uint32_t sd, void * buf, uint32_t size, SocketAddress &sock_addr)
{
sockAddr_t sAddr;
SlSockAddr_t* sa;
int32_t addrSize;
int32_t status = -1;
SlSockNonblocking_t BlockingOption;
struct SlTimeval_t TimeVal;
nsapi_addr_t nsapi_addr = sock_addr.get_addr();
BlockingOption.NonBlockingEnabled = SOCKET_IS_NON_BLOCKING;
if (1 == SOCKET_IS_NON_BLOCKING)
{
// non-blocking
status = sl_SetSockOpt((short int)sd, SL_SOL_SOCKET, SL_SO_NONBLOCKING, (_u8*)&BlockingOption,sizeof(BlockingOption));
if(status < 0)
{
printf("sl_SetSockOpt failed with %d\n\r", (int)status);
return NSAPI_ERROR_DEVICE_ERROR;
}
}
else
{
/* In case of blocking, a timeout for sl_RecvFrom will be set to TimeVal
* When timeout is expired sl_RecvFrom will return SL_ERROR_BSD_EAGAIN */
TimeVal.tv_sec = _timeout;
TimeVal.tv_usec = 0;
status = sl_SetSockOpt(sd,SL_SOL_SOCKET,SL_SO_RCVTIMEO,
(uint8_t *)&TimeVal,
sizeof(TimeVal));
if(status < 0)
{
printf ("sl_SetSockOpt failed with %d\n", (int)status);
return NSAPI_ERROR_DEVICE_ERROR;
}
}
memset((void*)buf, 0, size);
_fill_sl_address(sAddr, sa, addrSize, sock_addr);
// sl_RecvFrom requires size to be 1-16000 bytes. Can't pass 0
if (size == 0)
{
status = sl_RecvFrom(sd, buf, 1, 0, sa, (SlSocklen_t*)&addrSize);
}
else
{
status = sl_RecvFrom(sd, buf, size, 0, sa, (SlSocklen_t*)&addrSize);
}
if(status == SL_ERROR_BSD_EAGAIN)
{
if (1 == SOCKET_IS_NON_BLOCKING)
{
return NSAPI_ERROR_WOULD_BLOCK;
}
else
{
printf ("Timeout expired before receiving packet\n");
return NSAPI_ERROR_TIMEOUT;
}
}
else if(status < 0)
{
printf ("sl_RecvFrom failed with %d\n", (int)status);
return NSAPI_ERROR_DEVICE_ERROR;
}
else if ((status > 0 && size > 0) || (status == 0 && size == 0))
{
// Fill the ip and port
memset((void*)&nsapi_addr, 0, sizeof(nsapi_addr));
bool ipv6 = (sock_addr.get_ip_version() == NSAPI_IPv6);
if (ipv6)
{
sock_addr.set_port(sl_Ntohs(sAddr.in6.sin6_port));
nsapi_addr.version = NSAPI_IPv6;
*(unsigned long *)&nsapi_addr.bytes[0] = sAddr.in6.sin6_addr._S6_un._S6_u32[0];
*(unsigned long *)&nsapi_addr.bytes[4] = sAddr.in6.sin6_addr._S6_un._S6_u32[1];
*(unsigned long *)&nsapi_addr.bytes[8] = sAddr.in6.sin6_addr._S6_un._S6_u32[2];
*(unsigned long *)&nsapi_addr.bytes[12] = sAddr.in6.sin6_addr._S6_un._S6_u32[3];
sock_addr.set_addr(nsapi_addr);
}
else
{
sock_addr.set_port(sl_Ntohs(sAddr.in4.sin_port));
nsapi_addr.version = NSAPI_IPv4;
*(unsigned int*)nsapi_addr.bytes = sAddr.in4.sin_addr.s_addr;
sock_addr.set_addr(nsapi_addr);
}
}
return status;
}
void CC3200_SIMPLELINK::setTimeout(uint32_t timeout_ms)
{
_timeout = timeout_ms;
}
void CC3200_SIMPLELINK::_fill_sl_address(sockAddr_t &sAddr, SlSockAddr_t* &sa, int32_t &addrSize, const SocketAddress &sock_addr)
{
nsapi_addr_t nsapi_addr = sock_addr.get_addr();
bool ipv6 = (sock_addr.get_ip_version() == NSAPI_IPv6);
memset((void*)&sAddr, 0, sizeof(sAddr));
if (ipv6)
{
sAddr.in6.sin6_family = SL_AF_INET6;
sAddr.in6.sin6_port = sl_Htons(sock_addr.get_port());
sAddr.in6.sin6_flowinfo = 0;
sAddr.in6.sin6_addr._S6_un._S6_u32[0] = *(unsigned long *)&nsapi_addr.bytes[0];
sAddr.in6.sin6_addr._S6_un._S6_u32[1] = *(unsigned long *)&nsapi_addr.bytes[4];
sAddr.in6.sin6_addr._S6_un._S6_u32[2] = *(unsigned long *)&nsapi_addr.bytes[8];
sAddr.in6.sin6_addr._S6_un._S6_u32[3] = *(unsigned long *)&nsapi_addr.bytes[12];
sa = (SlSockAddr_t*)&sAddr.in6;
addrSize = sizeof(SlSockAddrIn6_t);
}
else
{
sAddr.in4.sin_family = SL_AF_INET;
sAddr.in4.sin_port = sl_Htons(sock_addr.get_port());
sAddr.in4.sin_addr.s_addr = *(unsigned int*)nsapi_addr.bytes;
sa = (SlSockAddr_t*)&sAddr.in4;
addrSize = sizeof(SlSockAddrIn_t);
}
}

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/* CC3200_SIMPLELINK Class
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef CC3200_SIMPLELINK_H
#define CC3200_SIMPLELINK_H
#include "mbed.h"
#include <assert.h>
#include "nsapi_types.h"
#include "nsapi.h"
#include "rtos.h"
#include "netsocket/WiFiAccessPoint.h"
#include "ti/drivers/net/wifi/netcfg.h"
#include "ti/drivers/ti_SPI.h"
#include "ti/drivers/dma/UDMACC32XX.h"
#include "ti/drivers/net/wifi/sl_socket.h"
#include "ti/drivers/net/wifi/netapp.h"
#include "ti/drivers/net/wifi/wlan.h"
#define MAX_SCAN_TIMEOUT (15000)
#define MAX_SCAN_ENTRIES (15)
#define MAX_SCAN_ATTEMPTS (10)
#ifndef CC3200_SIMPLELINK_MISC_TIMEOUT
#define CC3200_SIMPLELINK_MISC_TIMEOUT 2000
#endif
/**
* This is the interface class to CC3200 Simplelink
*/
class CC3200_SIMPLELINK
{
public:
CC3200_SIMPLELINK();
/**
* Initialize CC3200_SIMPLELINK to default state (STATION mode)
*/
nsapi_error_t initialize();
/**
* Startup the CC3200_SIMPLELINK
*
* @param role role of WIFI 0-Station, 2-AP, 3-P2P
* @return true only if it was setup correctly
*/
bool startup(int role);
/**
* Reset CC3200_SIMPLELINK
*
* @return true only if CC3200_SIMPLELINK resets successfully
*/
//bool reset(void);
/**
* Enable/Disable DHCP
*
* @param enabled DHCP enabled when true
* @param mode mode of DHCP 0-softAP, 1-station, 2-both
* @return true only if CC3200_SIMPLELINK enables/disables DHCP successfully
*/
bool dhcp(bool enabled, int mode);
/**
* Connect CC3200 SimpleLink to AP
*
* @param ap the name of the AP
* @param passPhrase the password of AP
* @param security security type
* @return NSAPI_ERROR_OK only if CC3200 SimpleLink is connected successfully
*/
nsapi_error_t connect(const char *ap, const char *passPhrase, nsapi_security_t security);
/**
* Disconnect CC3200 SimpleLink from AP
*
* @return true only if CC3200_SIMPLELINK is disconnected successfully
*/
bool disconnect(void);
/**
* Get the IP address of CC3200 SimpleLink
*
* @return null-teriminated IP address or null if no IP address is assigned
*/
const char *getIPAddress(void);
/**
* Get the MAC address of CC3200 SimpleLink
*
* @return null-terminated MAC address or null if no MAC address is assigned
*/
const char *getMACAddress(void);
/** Get the local gateway
*
* @return Null-terminated representation of the local gateway
* or null if no network mask has been received
*/
const char *getGateway();
/** Get the local network mask
*
* @return Null-terminated representation of the local network mask
* or null if no network mask has been recieved
*/
const char *getNetmask();
/** Get DNS server address
*
* @param ipaddr Pointer to allocated array to store DNS server raw address
* @param len Size of the storage area
* @return NSAPI_ERROR_OK on success or other error codes on failure
*/
nsapi_error_t getDNS(unsigned char* ip4addr, uint32_t len);
/* Return RSSI for active connection
*
* @return Measured RSSI
*/
int8_t getRSSI();
/** Scan for available networks
*
* @param ap Pointer to allocated array to store discovered AP
* @param limit Size of allocated @a res array, or 0 to only count available AP
* @return Number of entries in @a res, or if @a count was 0 number of available networks, negative on error
* see @a nsapi_error
*/
int scan(WiFiAccessPoint *res, unsigned count);
/** Set channel
*
* @param channel channel to set
* @return NSAPI error code
*/
nsapi_error_t set_channel(int channel);
/**Perform a dns query
*
* @param name Hostname to resolve
* @param ip Buffer to store IP address
* @return NSAPI error code
*/
nsapi_error_t dns_lookup(const char *name, char *ip, uint32_t ip_size, nsapi_version_t version);
/**
* Open a socket
*
* @return handle of the opened socket only if socket opened successfully, 0 or error otherwise
*/
nsapi_error_t open_socket(nsapi_protocol_t proto);
/**
* Close a socket
*
* @return true if socket was closed successfully, false otherwise
*/
bool close_socket(uint32_t sock);
/**
* Set socket options
*
* @param sd socket descritor
* @param level protocol level for this option
* @param optname option name to interrogate
* @param optval points to the value for the option
* @param optlen length of the option value
* @return nsapi status
*/
nsapi_error_t setsockopt(uint32_t sd, int level,
int optname, const void *optval, unsigned optlen);
/**
* Get socket options
*
* @param sd socket descriptor
* @param level protocol level for this option
* @param optname option name to interrogate
* @param optval points to the value for the option
* @param optlen length of the option value
* @return nsapi status
*/
nsapi_error_t getsockopt(uint32_t sd, int level,
int optname, void *optval, unsigned* optlen);
/**
* Initiate a connection on a socket (blocking)
*
* @param sd socket handle
* @param sock_addr SocketAddress structure
* @return nsapi status
*/
nsapi_error_t connect_socket(uint32_t sd, const SocketAddress &sock_addr);
/**
* Assigns a socket an local address
*
* @param sd socket handle
* @param sock_addr SocketAddress structure
*
* @return nsapi status
*/
nsapi_error_t bind_socket(uint32_t sd, const SocketAddress &sock_addr);
/**
* Write data to socket Initiate a connection on a socket (nonblocking)
*
* @param sd socket handle
* @param buf pointer to a buffer containing the data to be sent
* @param bufLen data length in bytes
* @param sock_addr SocketAddress structure
* @return a socket handle
*/
int sendto_socket(uint32_t sd, const void * buf, uint32_t bufLen, const SocketAddress &sock_addr);
/**
* Sends data to an open socket (nonblocking)
*
* @param sd sd of socket to send to
* @param data data to be sent
* @param size number of bytes to be sent - max 1024
* @return number of sent bytes on success, negative error code on failure
*/
int32_t send(int id, const void *data, uint32_t size);
/**
* Receives stream data from an open TCP socket (nonblocking)
*
* @param sd sd to receive from
* @param data placeholder for returned information
* @param size number of bytes to be received
* @return the number of bytes received
*/
int32_t recv(int sd, void *data, uint32_t size);
/**
* Receives data from socket
*
* @param sd sd to receive from
* @param buf placeholder for returned information
* @param size number of bytes to be received
* @param sock_addr SocketAddress structure
* @return the number of bytes received
*/
int32_t recvfrom(uint32_t sd, void * buf, uint32_t size, SocketAddress &sock_addr);
/**
* Allows timeout to be changed between commands
*
* @param timeout_ms timeout of the connection
*/
void setTimeout(uint32_t timeout_ms=CC3200_SIMPLELINK_MISC_TIMEOUT);
/**
* Attach a function to call whenever network state has changed
*
* @param func A pointer to a void function, or 0 to set as none
*/
void attach(mbed::Callback<void(nsapi_event_t, intptr_t)> status_cb);
/**
* Read default Wifi role
*
* return Station, AP or P2P
*/
int8_t get_current_wifi_mode();
/**
* Write default Wifi
*/
//bool set_default_wifi_mode(const int8_t mode);
/** Get the connection status
*
* @return The connection status according to ConnectionStatusType
*/
nsapi_connection_status_t get_connection_status() const;
/** Set the connection status
*
* @param status The connection status to set
*/
void set_connection_status(nsapi_connection_status_t status);
static const int8_t WIFI_ROLE_STATION = 1;
static const int8_t WIFI_ROLE_AP = 2;
static const int8_t WIFI_ROLE_P2P = 3;
private:
typedef union{
SlSockAddrIn6_t in6; /* Socket info for Ipv6 */
SlSockAddrIn_t in4; /* Socket info for Ipv4 */
}sockAddr_t;
char _ip_buffer[NSAPI_IPv4_SIZE];
char _gateway_buffer[NSAPI_IPv4_SIZE];
char _netmask_buffer[NSAPI_IPv4_SIZE];
char _mac_buffer[NSAPI_MAC_SIZE];
char _dns_server_buffer[NSAPI_IPv4_SIZE];
int _connect_error;
bool _initialized;
int _current_role;
bool _fail;
bool _closed;
nsapi_connection_status_t _connection_status;
mbed::Callback<void(nsapi_event_t, intptr_t)> _connection_status_cb;
char _connected_ssid[SL_WLAN_SSID_MAX_LENGTH+1]; /* 32 is what 802.11 defines as longest possible name; +1 for the \0 */
int _connected_channel;
SlWlanNetworkEntry_t netEntries[MAX_SCAN_ENTRIES];
int _timeout;
void _fill_sl_address(sockAddr_t &sAddr, SlSockAddr_t* &sa, int32_t &addrSize, const SocketAddress &sock_addr);
};
#endif /* CC3200_SIMPLELINK_H_ */

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/* CC3220SF CMSIS Library
*
* Copyright (c) 2006-2018 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* A generic CMSIS include header, pulling in CC3220SF specifics
*******************************************************************************/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "CC3220SF.h"
#include "cmsis_nvic.h"
#endif

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/cmsis_nvic.h Normal file
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/* CC3220SF CMSIS Library
*
* Copyright (c) 2006-2018 ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (195)
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
#endif

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/default_wifi_interface.cpp Normal file
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/*
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "CC3220SF_WiFiInterface.h"
WiFiInterface *WiFiInterface::get_target_default_instance()
{
static CC3220SFInterface wifi;
return &wifi;
}

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/**************************************************************************//**
* @file system_CC3220SF.c
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for
* Device CC3220SF
* @version V5.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdint.h>
#include "CC3220SF.h"
#include "../inc/hw_types.h"
#include "CC3220SF_LAUNCHXL.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
/* ToDo: add here your necessary defines for device initialization
following is an example for different system frequencies */
#define XTAL (40000000U) /* Oscillator frequency */
#define SYSTEM_CLOCK (2 * XTAL)
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
/* ToDo: initialize SystemCoreClock with the system core clock frequency value
achieved after system intitialization.
This means system core clock frequency after call to SystemInit() */
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
}
void SystemInit (void)
{
extern void *__Vectors;
SCB->VTOR = (uint32_t) &__Vectors;
CC3220SF_LAUNCHXL_initGeneral();
}

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/**************************************************************************//**
* @file system_CC3220SF.h
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
* Device CC3220SF
* @version V5.00
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SYSTEM_CC3220SF_H /* ToDo: replace '<Device>' with your device name */
#define SYSTEM_CC3220SF_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdio.h>
#include "ti/drivers/net/wifi/wlan.h"
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
extern void PRCMMCUReset(unsigned char bIncludeSubsystem);
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void __CC3200_SystemReset(void)
{
/* Stop the NWP */
_i16 retcode = sl_Stop(0);
if (retcode != 0 && retcode != SL_RET_CODE_DEV_NOT_STARTED)
{
printf("sl_stop failed with 0x%x\n", retcode);
}
PRCMMCUReset(0);
}
#ifdef NVIC_SystemReset
#undef NVIC_SystemReset
#endif
#define NVIC_SystemReset __CC3200_SystemReset
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_<Device>_H */

514
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/wifi_event_handler.cpp Executable file
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/*
* Copyright (c) 2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*****************************************************************************
Application Name - Network terminal
Application Overview - Network Terminal is a command line interface (cli) based application,
used to demonstrate the CC32XX/CC31XX networking capabilities.
It does that by offering a list of commands, divided into four silos:
Wlan : Contains link layer functions like scan, connect, etc.
NetApp : Demonstrates the usage of networking applications.
Socket : Shows variety of socket API and responsible for sending and receiving packets.
Transceiver : Gives the user a direct interface to the NWP radio for RF tests, raw sockets (L1) and more.
Application Details - Refer to 'Network Terminal' README.html
*****************************************************************************/
/* Standard includes */
#include <string.h>
#include <stdio.h>
#include <stdarg.h>
#include "rtos.h"
#include <CC3220SF_WiFiInterface.h>
#include <ti/drivers/net/wifi/simplelink.h>
#define HANDLER_TRACE_ENABLE 0
/****************************************************************************
LOCAL FUNCTION PROTOTYPES
****************************************************************************/
/****************************************************************************
GLOBAL VARIABLES
****************************************************************************/
/*****************************************************************************
Callback Functions
*****************************************************************************/
/*!
\brief SimpleLinkWlanEventHandler
This handler gets called whenever a WLAN event is reported
by the host driver / NWP. Here user can implement he's own logic
for any of these events. This handler is used by 'network_terminal'
application to show case the following scenarios:
1. Handling connection / Disconnection.
2. Handling Addition of station / removal.
3. RX filter match handler.
4. P2P connection establishment.
\param pWlanEvent - pointer to Wlan event data.
\return void
\note For more information, please refer to: user.h in the porting
folder of the host driver and the CC3120/CC3220 NWP programmer's
guide (SWRU455) sections 4.3.4, 4.4.5 and 4.5.5.
\sa cmdWlanConnectCallback, cmdEnableFilterCallback, cmdWlanDisconnectCallback,
cmdP2PModecallback.
*/
void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent)
{
if(!pWlanEvent)
{
return;
}
switch(pWlanEvent->Id)
{
case SL_WLAN_EVENT_CONNECT:
{
#if HANDLER_TRACE_ENABLE == 1
printf("\n\r[WLAN EVENT] STA Connected to the AP: %s , "
"BSSID: %x:%x:%x:%x:%x:%x\n\r",
pWlanEvent->Data.Connect.SsidName, pWlanEvent->Data.Connect.Bssid[0],
pWlanEvent->Data.Connect.Bssid[1],pWlanEvent->Data.Connect.Bssid[2],
pWlanEvent->Data.Connect.Bssid[3],pWlanEvent->Data.Connect.Bssid[4],
pWlanEvent->Data.Connect.Bssid[5]);
#endif
CC3220SFInterface::cc3200sf_wifi_instance->_connect_sem.release();
}
break;
case SL_WLAN_EVENT_DISCONNECT:
{
SlWlanEventDisconnect_t *pEventData = NULL;
pEventData = &pWlanEvent->Data.Disconnect;
/* If the user has initiated 'Disconnect' request,
'reason_code' is SL_WLAN_DISCONNECT_USER_INITIATED */
if(SL_WLAN_DISCONNECT_USER_INITIATED == pEventData->ReasonCode)
{
#if HANDLER_TRACE_ENABLE == 1
printf("\n\r[WLAN EVENT] Device disconnected from the AP\n\r");
#endif
}
else
{
printf("\n\r[WLAN ERROR] Device disconnected from the AP\n\r");
}
}
break;
case SL_WLAN_EVENT_PROVISIONING_STATUS:
{
/* Do nothing, this suppress provisioning event is because simplelink is configured to default state. */
}
break;
case SL_WLAN_EVENT_STA_ADDED:
{
printf("\n\r[WLAN EVENT] STA was added to AP: BSSID: %x:%x:%x:%x:%x:%x\n\r",
pWlanEvent->Data.STAAdded.Mac[0],pWlanEvent->Data.STAAdded.Mac[1],
pWlanEvent->Data.STAAdded.Mac[2],pWlanEvent->Data.STAAdded.Mac[3],
pWlanEvent->Data.STAAdded.Mac[4],pWlanEvent->Data.STAAdded.Mac[5]);
}
break;
case SL_WLAN_EVENT_STA_REMOVED:
{
printf("\n\r[WLAN EVENT] STA was removed from AP\n\r");
}
break;
case SL_WLAN_EVENT_RXFILTER:
{
SlWlanEventRxFilterInfo_t *triggred_filter = NULL;
triggred_filter = &(pWlanEvent->Data.RxFilterInfo) ;
printf("\n\r[WLAN EVENT] Rx filter match triggered. Set filters in filter bitmap :0x%x.\n\r", triggred_filter->UserActionIdBitmap[0]);
/*
* User can write he's / her's rx filter match handler here.
* Be advised, you can use the 'triggred_filter' structure info to determine which filter
* has received a match. (Bit X is set if user action id X was passed to a filter that matched a packet.)
*/
}
break;
case SL_WLAN_EVENT_P2P_DEVFOUND:
{
printf("\n\r[WLAN EVENT] P2P Remote device found\n\r");
}
break;
case SL_WLAN_EVENT_P2P_REQUEST:
{
printf("\n\r[WLAN EVENT] P2P Negotiation request received\n\r");
}
break;
case SL_WLAN_EVENT_P2P_CONNECT:
{
printf("n\r[WLAN EVENT] P2P connection was successfully completed as CLIENT\n\r");
printf("n\rBSSID is %02x:%02x:%02x:%02x:%02x:%02x\n\r",
pWlanEvent->Data.STAAdded.Mac[0],
pWlanEvent->Data.STAAdded.Mac[1],
pWlanEvent->Data.STAAdded.Mac[2],
pWlanEvent->Data.STAAdded.Mac[3],
pWlanEvent->Data.STAAdded.Mac[4],
pWlanEvent->Data.STAAdded.Mac[5]);
}
break;
case SL_WLAN_EVENT_P2P_CLIENT_ADDED:
{
printf("n\r[WLAN EVENT] P2P connection was successfully completed as GO\n\r");
printf("n\rBSSID is %02x:%02x:%02x:%02x:%02x:%02x\n\r",
pWlanEvent->Data.P2PClientAdded.Mac[0],
pWlanEvent->Data.P2PClientAdded.Mac[1],
pWlanEvent->Data.P2PClientAdded.Mac[2],
pWlanEvent->Data.P2PClientAdded.Mac[3],
pWlanEvent->Data.P2PClientAdded.Mac[4],
pWlanEvent->Data.P2PClientAdded.Mac[5]);
}
break;
case SL_WLAN_EVENT_P2P_DISCONNECT:
{
printf("\n\r[WLAN EVENT] STA disconnected from device.\n\r");
}
break;
default:
{
printf("\n\r[WLAN EVENT] Unexpected event [0x%x]\n\r", (unsigned int)pWlanEvent->Id);
}
break;
}
}
/*!
\brief SimpleLinkNetAppEventHandler
This handler gets called whenever a Netapp event is reported
by the host driver / NWP. Here user can implement he's own logic
for any of these events. This handler is used by 'network_terminal'
application to show case the following scenarios:
1. Handling IPv4 / IPv6 IP address acquisition.
2. Handling IPv4 / IPv6 IP address Dropping.
\param pNetAppEvent - pointer to Netapp event data.
\return void
\note For more information, please refer to: user.h in the porting
folder of the host driver and the CC3120/CC3220 NWP programmer's
guide (SWRU455) section 5.7
*/
void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent)
{
if(!pNetAppEvent)
{
return;
}
switch(pNetAppEvent->Id)
{
case SL_NETAPP_EVENT_IPV4_ACQUIRED:
{
#if HANDLER_TRACE_ENABLE == 1
SlIpV4AcquiredAsync_t *pEventData = NULL;
/* Ip Acquired Event Data */
pEventData = &pNetAppEvent->Data.IpAcquiredV4;
printf("\n\r[NETAPP EVENT] IP set to: IPv4=%d.%d.%d.%d , "
"Gateway=%d.%d.%d.%d\n\r",
(unsigned int)SL_IPV4_BYTE(pEventData->Ip,3),
(unsigned int)SL_IPV4_BYTE(pEventData->Ip,2),
(unsigned int)SL_IPV4_BYTE(pEventData->Ip,1),
(unsigned int)SL_IPV4_BYTE(pEventData->Ip,0),
(unsigned int)SL_IPV4_BYTE(pEventData->Gateway,3),
(unsigned int)SL_IPV4_BYTE(pEventData->Gateway,2),
(unsigned int)SL_IPV4_BYTE(pEventData->Gateway,1),
(unsigned int)SL_IPV4_BYTE(pEventData->Gateway,0));
#endif
CC3220SFInterface::cc3200sf_wifi_instance->_ip_set_sem.release();
}
break;
case SL_NETAPP_EVENT_IPV6_ACQUIRED:
{
uint32_t i = 0;
printf("\n\r[NETAPP EVENT] IP Acquired: IPv6=");
for(i = 0; i < 3 ; i++)
{
printf("%04x:%04x:\n", ((unsigned int)(pNetAppEvent->Data.IpAcquiredV6.Ip[i]>>16) & 0xffff), (unsigned int)pNetAppEvent->Data.IpAcquiredV6.Ip[i] & 0xffff);
}
printf("%04x:%04x\n", ((unsigned int)(pNetAppEvent->Data.IpAcquiredV6.Ip[3]>>16) & 0xffff), (unsigned int)pNetAppEvent->Data.IpAcquiredV6.Ip[3] & 0xffff);
}
break;
case SL_NETAPP_EVENT_DHCPV4_LEASED:
{
printf("\n\r[NETAPP EVENT] IP Leased to Client: IP=%d.%d.%d.%d \n\r",
(unsigned int)SL_IPV4_BYTE(pNetAppEvent->Data.IpLeased.IpAddress ,3), (unsigned int)SL_IPV4_BYTE(pNetAppEvent->Data.IpLeased.IpAddress ,2),
(unsigned int)SL_IPV4_BYTE(pNetAppEvent->Data.IpLeased.IpAddress ,1), (unsigned int)SL_IPV4_BYTE(pNetAppEvent->Data.IpLeased.IpAddress ,0));
}
break;
case SL_NETAPP_EVENT_DHCPV4_RELEASED:
{
printf("\n\r[NETAPP EVENT] IP is released.\n\r");
}
break;
default:
{
printf("\n\r[NETAPP EVENT] Unexpected event [0x%x] \n\r", (unsigned int)pNetAppEvent->Id);
}
break;
}
}
/*!
\brief SimpleLinkHttpServerEventHandler
This handler gets called whenever a HTTP event is reported
by the NWP internal HTTP server.
\param pHttpEvent - pointer to http event data.
\param pHttpEvent - pointer to http response.
\return void
\note For more information, please refer to: user.h in the porting
folder of the host driver and the CC3120/CC3220 NWP programmer's
guide (SWRU455) chapter 9.
*/
void SimpleLinkHttpServerEventHandler(SlNetAppHttpServerEvent_t *pHttpEvent,
SlNetAppHttpServerResponse_t *pHttpResponse)
{
/* Unused in this application */
}
/*!
\brief SimpleLinkGeneralEventHandler
This handler gets called whenever a general error is reported
by the NWP / Host driver. Since these errors are not fatal,
application can handle them.
\param pDevEvent - pointer to device error event.
\return void
\note For more information, please refer to: user.h in the porting
folder of the host driver and the CC3120/CC3220 NWP programmer's
guide (SWRU455) section 17.9.
*/
void SimpleLinkGeneralEventHandler(SlDeviceEvent_t *pDevEvent)
{
if(!pDevEvent)
{
return;
}
/*
Most of the general errors are not FATAL are are to be handled
appropriately by the application
*/
printf("\n\r[GENERAL EVENT] - ID=[%d] Sender=[%d]\n\n",
pDevEvent->Data.Error.Code,
pDevEvent->Data.Error.Source);
}
/*!
\brief SimpleLinkSockEventHandler
This handler gets called whenever a socket event is reported
by the NWP / Host driver.
\param SlSockEvent_t - pointer to socket event data.
\return void
\note For more information, please refer to: user.h in the porting
folder of the host driver and the CC3120/CC3220 NWP programmer's
guide (SWRU455) section 7.6.
*/
void SimpleLinkSockEventHandler(SlSockEvent_t *pSock)
{
#if HANDLER_TRACE_ENABLE == 1
printf("\n\r[INFO] - event detected: "
"Event=%d, AbortData=0x%x\n\r",
(unsigned int)pSock->Event,
(unsigned int)pSock->SocketAsyncEvent.SockTxFailData.Status);
#endif
}
/*!
\brief SimpleLinkFatalErrorEventHandler
This handler gets called whenever a socket event is reported
by the NWP / Host driver. After this routine is called, the user's
application must restart the device in order to recover.
\param slFatalErrorEvent - pointer to fatal error event.
\return void
\note For more information, please refer to: user.h in the porting
folder of the host driver and the CC3120/CC3220 NWP programmer's
guide (SWRU455) section 17.9.
*/
void SimpleLinkFatalErrorEventHandler(SlDeviceFatal_t *slFatalErrorEvent)
{
switch (slFatalErrorEvent->Id)
{
case SL_DEVICE_EVENT_FATAL_DEVICE_ABORT:
{
printf("\n\r[ERROR] - FATAL ERROR: Abort NWP event detected: "
"AbortType=%d, AbortData=0x%x\n\r",
(unsigned int)slFatalErrorEvent->Data.DeviceAssert.Code,
(unsigned int)slFatalErrorEvent->Data.DeviceAssert.Value);
}
break;
case SL_DEVICE_EVENT_FATAL_DRIVER_ABORT:
{
printf("\n\r[ERROR] - FATAL ERROR: Driver Abort detected. \n\r");
}
break;
case SL_DEVICE_EVENT_FATAL_NO_CMD_ACK:
{
printf("\n\r[ERROR] - FATAL ERROR: No Cmd Ack detected "
"[cmd opcode = 0x%x] \n\r",
(unsigned int)slFatalErrorEvent->Data.NoCmdAck.Code);
}
break;
case SL_DEVICE_EVENT_FATAL_SYNC_LOSS:
{
printf("\n\r[ERROR] - FATAL ERROR: Sync loss detected n\r");
}
break;
case SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT:
{
printf("\n\r[ERROR] - FATAL ERROR: Async event timeout detected "
"[event opcode =0x%x] \n\r",
(unsigned int)slFatalErrorEvent->Data.CmdTimeout.Code);
}
break;
default:
printf("\n\r[ERROR] - FATAL ERROR: Unspecified error detected \n\r");
break;
}
}
/*!
\brief SimpleLinkNetAppRequestEventHandler
This handler gets called whenever a NetApp event is reported
by the NWP / Host driver. User can write he's logic to handle
the event here.
\param pNetAppRequest - Pointer to NetApp request structure.
\param pNetAppResponse - Pointer to NetApp request Response.
\note For more information, please refer to: user.h in the porting
folder of the host driver and the CC3120/CC3220 NWP programmer's
guide (SWRU455) section 17.9.
\return void
*/
void SimpleLinkNetAppRequestEventHandler(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse)
{
/* Unused in this application */
}
/*!
\brief SimpleLinkNetAppRequestMemFreeEventHandler
This handler gets called whenever the NWP is done handling with
the buffer used in a NetApp request. This allows the use of
dynamic memory with these requests.
\param pNetAppRequest - Pointer to NetApp request structure.
\param pNetAppResponse - Pointer to NetApp request Response.
\note For more information, please refer to: user.h in the porting
folder of the host driver and the CC3120/CC3220 NWP programmer's
guide (SWRU455) section 17.9.
\return void
*/
void SimpleLinkNetAppRequestMemFreeEventHandler(uint8_t *buffer)
{
/* Unused in this application */
}

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/flash_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if DEVICE_FLASH
#include "stdbool.h"
#include "ti/devices/cc32xx/inc/hw_types.h"
#include "flash_api.h"
#include "ti/devices/cc32xx/driverlib/flash.h"
#define CC3200_FLASH_SECTOR_SIZE 0x800
#define CC3200_FLASH_PAGE_SIZE 0x4
#define CC3200_FLASH_START_ADDRESS 0x01000000
#define CC3200_FLASH_SIZE (1024*1024)
int32_t flash_init(flash_t *obj)
{
return 0;
}
int32_t flash_free(flash_t *obj)
{
//FlashDisable();
return 0;
}
int32_t flash_erase_sector(flash_t *obj, uint32_t address)
{
return FlashErase(address);
}
int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
{
return FlashProgram((unsigned long *)data, (unsigned long)address,
(unsigned long)size);
}
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
{
if ((address >= CC3200_FLASH_START_ADDRESS) && address < (CC3200_FLASH_START_ADDRESS + CC3200_FLASH_SIZE))
{
return CC3200_FLASH_SECTOR_SIZE;
}
else
{
return MBED_FLASH_INVALID_SIZE;
}
}
uint32_t flash_get_page_size(const flash_t *obj)
{
return CC3200_FLASH_PAGE_SIZE;
}
uint32_t flash_get_start_address(const flash_t *obj)
{
return CC3200_FLASH_START_ADDRESS;
}
uint32_t flash_get_size(const flash_t *obj)
{
return CC3200_FLASH_SIZE;
}
uint8_t flash_get_erase_value(const flash_t *obj)
{
(void)obj;
return 0xFF;
}
#endif

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "mbed_error.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include <ti/devices/cc32xx/inc/hw_types.h>
#include <ti/devices/cc32xx/driverlib/pin.h>
#include <ti/devices/cc32xx/driverlib/gpio.h>
#include <ti/devices/cc32xx/inc/hw_ints.h>
#include <ti/devices/cc32xx/driverlib/prcm.h>
uint32_t gpio_set(PinName pin)
{
pin_function(pin, 0);
return (1);
}
// function to initialise the gpio pin
// this links the board control bits for each pin
// with the object created for the pin
void gpio_init(gpio_t *obj, PinName pin)
{
obj->pin = pin;
if (pin == (PinName)NC)
return;
unsigned long gpio_base = (unsigned long)pinmap_peripheral(pin, PinMap_GPIO);
obj->baseAddr = gpio_base;
obj->pin_mask = 1<<(pinmap_find_function(pin, PinMap_GPIO)%8);
// determine PRCM GPIO CLOCK index
unsigned short prcm_peripheral = 0;
switch (gpio_base)
{
case CC3220SF_GPIOA0_BASE:
prcm_peripheral = PRCM_GPIOA0;
break;
case CC3220SF_GPIOA1_BASE:
prcm_peripheral = PRCM_GPIOA1;
break;
case CC3220SF_GPIOA2_BASE:
prcm_peripheral = PRCM_GPIOA2;
break;
case CC3220SF_GPIOA3_BASE:
prcm_peripheral = PRCM_GPIOA3;
break;
default:
break;
}
// initialize GPIO PORT clock
PRCMPeripheralClkEnable(prcm_peripheral, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
// wait for GPIO clock to settle
while(!PRCMPeripheralStatusGet(prcm_peripheral));
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
obj->mode = mode;
//set the pin mux to be GPIO which is PIN MODE 0
pin_mode(obj->pin, mode);
PinModeSet(obj->pin, PIN_MODE_0);
}
void gpio_dir(gpio_t *obj, PinDirection direction)
{
obj->dir = direction;
GPIODirModeSet(obj->baseAddr, obj->pin_mask, direction);
}
int gpio_is_connected(const gpio_t *obj)
{
return (obj->pin == NC);
}
void gpio_write(gpio_t *obj, int value)
{
GPIOPinWrite(obj->baseAddr, obj->pin_mask, value*obj->pin_mask);
}
int gpio_read(gpio_t *obj)
{
return (GPIOPinRead(obj->baseAddr, obj->pin_mask) != 0);
}

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_irq_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "gpio_irq_api.h"
#include "mbed_error.h"
#include "cmsis.h"
#include "PeripheralPins.h"
#include <ti/devices/cc32xx/inc/hw_types.h>
#include <ti/devices/cc32xx/inc/hw_gpio.h>
#include <ti/devices/cc32xx/driverlib/gpio.h>
#include <ti/devices/cc32xx/inc/hw_ints.h>
#include <ti/devices/cc32xx/inc/hw_memmap.h>
#include <ti/devices/cc32xx/inc/hw_common_reg.h>
#define CHANNEL_NUM 32
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler;
static void handle_interrupt_in(unsigned long gpio_port) {
uint32_t chan_base = 0;
switch ((unsigned long) gpio_port)
{
case CC3220SF_GPIOA0_BASE:
chan_base = 0;
break;
case CC3220SF_GPIOA1_BASE:
chan_base = 8;
break;
case CC3220SF_GPIOA2_BASE:
chan_base = 16;
break;
case CC3220SF_GPIOA3_BASE:
chan_base = 24;
break;
default:
return;
break;
}
uint16_t pin_mask = 0x01;
for(int i = 0; i < 8; i++){
//checking for interrupt on each GPIO pin
if((GPIOIntStatus((unsigned long)gpio_port, true) & pin_mask) > 0){
gpio_irq_event event = (gpio_irq_event)GPIOIntTypeGet((unsigned long)gpio_port, pin_mask);
if(event == GPIO_RISING_EDGE){
event = IRQ_RISE;
}
else if(event == GPIO_FALLING_EDGE){
event = IRQ_FALL;
}
if(channel_ids[chan_base+i] == 0)
continue;
irq_handler(channel_ids[chan_base+i], (gpio_irq_event)event);
}
GPIOIntClear((unsigned long)gpio_port, pin_mask);
pin_mask = pin_mask<<1;
}
}
void gpio_irqA0(void) {
handle_interrupt_in(CC3220SF_GPIOA0_BASE);
}
void gpio_irqA1(void)
{
handle_interrupt_in(CC3220SF_GPIOA1_BASE);
}
void gpio_irqA2(void)
{
handle_interrupt_in(CC3220SF_GPIOA2_BASE);
}
void gpio_irqA3(void)
{
handle_interrupt_in(CC3220SF_GPIOA3_BASE);
}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
if (pin == NC) return -1;
unsigned long gpio_base = (unsigned long)pinmap_peripheral(pin, PinMap_GPIO);
unsigned long ch_num = pinmap_find_function(pin, PinMap_GPIO);
obj->baseAddr = gpio_base;
obj->pin = pin;
obj->ch = ch_num;
obj->pin_mask = 1<<(ch_num%8);
irq_handler = handler;
uint32_t vector = (uint32_t)gpio_irqA0;
switch (gpio_base)
{
case CC3220SF_GPIOA0_BASE:
vector = (uint32_t)gpio_irqA0;
obj->irq_offset = INT_GPIOA0_IRQn;
break;
case CC3220SF_GPIOA1_BASE:
vector = (uint32_t)gpio_irqA1;
obj->irq_offset = INT_GPIOA1_IRQn;
break;
case CC3220SF_GPIOA2_BASE:
vector = (uint32_t)gpio_irqA2;
obj->irq_offset = INT_GPIOA2_IRQn;
break;
case CC3220SF_GPIOA3_BASE:
vector = (uint32_t)gpio_irqA3;
obj->irq_offset = INT_GPIOA3_IRQn;
break;
default:
break;
}
channel_ids[obj->ch] = id;
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_offset);
NVIC_DisableIRQ((IRQn_Type)obj->irq_offset);
NVIC_SetVector((IRQn_Type)obj->irq_offset, vector);
NVIC_EnableIRQ((IRQn_Type)obj->irq_offset);
return 0;
}
void gpio_irq_free(gpio_irq_t *obj) {
channel_ids[obj->ch] = 0;
GPIOIntDisable(obj->baseAddr, obj->pin_mask);
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
if(enable){
GPIOIntEnable(obj->baseAddr, obj->pin_mask);
}
else{
GPIOIntDisable(obj->baseAddr, obj->pin_mask);
}
switch(event){
case IRQ_RISE:GPIOIntTypeSet(obj->baseAddr,obj->pin_mask, GPIO_RISING_EDGE); break;
case IRQ_FALL: GPIOIntTypeSet(obj->baseAddr,obj->pin_mask, GPIO_FALLING_EDGE); break;
default: break;
}
}
void gpio_irq_enable(gpio_irq_t *obj) {
GPIOIntEnable(obj->baseAddr, obj->pin_mask);
}
void gpio_irq_disable(gpio_irq_t *obj) {
GPIOIntDisable(obj->baseAddr, obj->pin_mask);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if DEVICE_LPTICKER
#include "ti/devices/cc32xx/inc/hw_types.h"
#include "ti/devices/cc32xx/driverlib/prcm.h"
/*******************************************************************************
* lp_ticker implementation on this target is mapped on top of the sleep clock counter
* that is running in the lowest energy modes. The sleep clock counter is 48b running
* at 32.768KHz. This gives 0.03ms resolution for the low power timer which requires
* millisecond accuracy.
*
******************************************************************************/
#include "lp_ticker_api.h"
#include "mbed_critical.h"
// There's actually 48b but Mbed OS supports 32b only.
#define RTC_BITS 32u
#define RTC_FREQ 32768u
static bool rtc_inited = false;
const ticker_info_t* lp_ticker_get_info()
{
static const ticker_info_t info = {
RTC_FREQ, // 32KHz
RTC_BITS // 32 bit counter
};
return &info;
}
void lp_ticker_init()
{
if (PRCMRTCInUseGet() == true)
// When RTC is in use, slow clock counter can't be accessed
{
return;
}
if (!rtc_inited) {
NVIC_SetVector(INT_PRCM_IRQn, (uint32_t)lp_ticker_irq_handler);
NVIC_ClearPendingIRQ(INT_PRCM_IRQn);
NVIC_EnableIRQ(INT_PRCM_IRQn);
PRCMIntStatus(); // Read clears pending interrupts
rtc_inited = true;
} else {
PRCMIntDisable(PRCM_INT_SLOW_CLK_CTR);
}
}
void lp_ticker_free()
{
/* Disable the RTC if it was inited and is no longer in use by anyone. */
if (rtc_inited) {
NVIC_DisableIRQ(INT_PRCM_IRQn);
rtc_inited = false;
}
}
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
// timestamp is defined as 32b.
core_util_critical_section_enter();
// Clear pending interrupt
PRCMIntStatus();
PRCMSlowClkCtrMatchSet(timestamp);
PRCMIntEnable(PRCM_INT_SLOW_CLK_CTR);
core_util_critical_section_exit();
}
void lp_ticker_fire_interrupt(void)
{
core_util_critical_section_enter();
NVIC_SetPendingIRQ(INT_PRCM_IRQn);
core_util_critical_section_exit();
}
void lp_ticker_disable_interrupt()
{
PRCMIntDisable(PRCM_INT_SLOW_CLK_CTR);
}
void lp_ticker_clear_interrupt()
{
PRCMIntStatus(); // Read clears pending interrupts
}
timestamp_t lp_ticker_read()
{
// Read forever until reaching two of the same
volatile unsigned long long read_previous, read_current;
do
{
read_previous = PRCMSlowClkCtrFastGet();
read_current = PRCMSlowClkCtrFastGet();
} while (read_previous != read_current);
return read_current;
}
#endif /* DEVICE_LPTICKER */

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "stdbool.h"
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#include "serial_object.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
unsigned long baseAddr;
PinName pin;
PinMode mode;
PinDirection dir;
unsigned long pin_mask;
} gpio_t;
struct gpio_irq_s {
unsigned long baseAddr;
uint32_t port;
PinName pin;
uint32_t ch;
unsigned long pin_mask;
unsigned long irq_offset;
};
struct port_s {
unsigned long baseAddr;
unsigned long peripheralId;
PortName port;
uint32_t mask;
};
struct pwmout_s {
uint32_t pwmPin;
PWMName pwm;
};
struct serial_s {
CC3220SF_UART_TypeDef *uart;
int index;
uint32_t baudRate; /*!< Baud rate for UART */
unsigned int baseAddr; /*! UART Peripheral's base address */
unsigned int intNum; /*! UART Peripheral's interrupt vector */
unsigned int powerMgrId; /* Determined from base address */
unsigned long peripheralId; /* Value that can be passed to PRCM functions */
UART_LEN dataLength; /* Data length for UART */
UART_STOP stopBits; /* Stop bits for UART */
UART_PAR parityType; /* Parity bit type for UART */
};
struct analogin_s{
PinName pin;
unsigned long adc_ch;
};
struct trng_s {
uint32_t placeholder;
};
struct flash_s {
uint32_t placeholder;
};
typedef struct spi_clock_config_s {
//! \param ulSPIClk is the rate of clock supplied to the SPI module.
uint32_t ulSPIClk;
//! \param ulBitRate is the desired bit rate.(master mode)
uint32_t ulBitRate;
//!
//! The SPI module can operate in either master or slave mode. The parameter
//! \e ulMode can be one of the following
//! -\b SPI_MODE_MASTER
//! -\b SPI_MODE_SLAVE
uint32_t ulMode;
//!
//! The SPI module supports 4 sub modes based on SPI clock polarity and phase.
//!
//! <pre>
//! Polarity Phase Sub-Mode
//! 0 0 0
//! 0 1 1
//! 1 0 2
//! 1 1 3
//! </pre>
//! Required sub mode can be select by setting \e ulSubMode parameter to one
//! of the following
//! - \b SPI_SUB_MODE_0
//! - \b SPI_SUB_MODE_1
//! - \b SPI_SUB_MODE_2
//! - \b SPI_SUB_MODE_3
uint32_t ulSubMode;
//! The parameter \e ulConfig is logical OR of five values: the word length,
//! active level for chip select, software or hardware controlled chip select,
//! 3 or 4 pin mode and turbo mode.
//! mode.
//!
//! SPI support 8, 16 and 32 bit word lengths defined by:-
//! - \b SPI_WL_8
//! - \b SPI_WL_16
//! - \b SPI_WL_32
//!
//! Active state of Chip Select can be defined by:-
//! - \b SPI_CS_ACTIVELOW
//! - \b SPI_CS_ACTIVEHIGH
//!
//! SPI chip select can be configured to be controlled either by hardware or
//! software:-
//! - \b SPI_SW_CS
//! - \b SPI_HW_CS
//!
//! The module can work in 3 or 4 pin mode defined by:-
//! - \b SPI_3PIN_MODE
//! - \b SPI_4PIN_MODE
//!
//! Turbo mode can be set on or turned off using:-
//! - \b SPI_TURBO_MODE_ON
//! - \b SPI_TURBO_MODE_OFF
uint32_t ulConfig;
} spi_clock_config_t;
struct spi_s {
/*! SPI module number */
uint32_t instance;
/*! SPICC32XXDMA Peripheral's base address */
uint32_t baseAddr;
/*! SPI Word lengh */
uint32_t word_length;
/*! SPI clock configuration */
spi_clock_config_t clock_config;
/*! Is clock update needed */
bool clock_update;
/*! Is CS controlled by GPIO */
bool cs_control_gpio;
#if DEVICE_SPI_ASYNCH
uint32_t handler;
uint32_t mask;
uint32_t event;
#endif
};
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "mbed_error.h"
#include <ti/devices/cc32xx/inc/hw_types.h>
#include <ti/devices/cc32xx/inc/hw_memmap.h>
#include <ti/devices/cc32xx/inc/hw_ocp_shared.h>
#include <ti/devices/cc32xx/driverlib/pin.h>
/**
* Configure pin (mode, speed, output type and pull-up/pull-down)
*/
void pin_function(PinName pin, int function)
{
MBED_ASSERT(pin != (PinName)NC);
}
/**
* Configure pin pull-up/pull-down
*/
void pin_mode(PinName pin, PinMode mode)
{
MBED_ASSERT(pin != (PinName)NC);
switch(mode) {
case PullNone: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD); break;
case PullUp: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD_PU); break;
case PullDown: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD_PD); break;
case OpenDrain: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD); break;
case OpenDrainPullUp: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD_PU); break;
case OpenDrainPullDown: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_OD_PD); break;
case Analog: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_ANALOG); break;
default: PinConfigSet(pin, PIN_STRENGTH_2MA, PIN_TYPE_STD); break;
}
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
#include "PeripheralPins.h"
#include <ti/devices/cc32xx/inc/hw_types.h>
#include <ti/devices/cc32xx/driverlib/pin.h>
#include <ti/devices/cc32xx/driverlib/gpio.h>
#include <ti/devices/cc32xx/inc/hw_ints.h>
#include <ti/devices/cc32xx/driverlib/prcm.h>
#define NUM_PORTS 4
#define NUM_PINS_PER_PORT 8
#define PORT_MASK 0x3
static const uint8_t pinTable[] = {
/* 00 01 02 03 04 05 06 07 */
PIN_50, PIN_55, PIN_57, PIN_58, PIN_59, PIN_60, PIN_61, PIN_62,
/* 08 09 10 11 12 13 14 15 */
PIN_63, PIN_64, PIN_01, PIN_02, PIN_03, PIN_04, PIN_05, PIN_06,
/* 16 17 18 19 20 21 22 23 */
PIN_07, PIN_08, PIN_XX, PIN_XX, PIN_XX, PIN_XX, PIN_15, PIN_16,
/* 24 25 26 27 28 29 30 31 */
PIN_17, PIN_21, PIN_29, PIN_30, PIN_18, PIN_20, PIN_53, PIN_45,
/* 32 */
PIN_52
};
const uint16_t PortPinTypes[] = {
PIN_TYPE_STD, /* GPIO_CFG_IN_NOPULL */
PIN_TYPE_STD_PU, /* GPIO_CFG_IN_PU */
PIN_TYPE_STD_PD, /* GPIO_CFG_IN_PD */
PIN_TYPE_OD, /* GPIO_CFG_OUT_OD_NOPULL */
PIN_TYPE_OD_PU, /* GPIO_CFG_OUT_OD_PU */
PIN_TYPE_OD_PD, /* GPIO_CFG_OUT_OD_PD */
(uint16_t)PIN_TYPE_ANALOG // Revisit this, PIN_TYPE_ANALOG gets truncated to 16b
};
PinName port_pin(PortName port, int pin_n) {
int gpio_num = (port * 8) + pin_n;
PinName pin = (PinName)pinTable[gpio_num];
return pin;
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
obj->port = port;
obj->mask = mask;
switch(port) {
case Port0: obj->baseAddr = CC3220SF_GPIOA0_BASE; obj->peripheralId = PRCM_GPIOA0; break;
case Port1: obj->baseAddr = CC3220SF_GPIOA1_BASE; obj->peripheralId = PRCM_GPIOA1; break;
case Port2: obj->baseAddr = CC3220SF_GPIOA2_BASE; obj->peripheralId = PRCM_GPIOA2; break;
case Port3: obj->baseAddr = CC3220SF_GPIOA3_BASE; obj->peripheralId = PRCM_GPIOA3; break;
}
// initialize GPIO PORT clock
PRCMPeripheralClkEnable(obj->peripheralId, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
// wait for GPIO clock to settle
while(!PRCMPeripheralStatusGet(obj->peripheralId));
for (int i = 0; i < 8; i++) {
if (obj->mask & (1 << i)) {
PinName pin = port_pin(obj->port, i);
PinModeSet(pin, PIN_MODE_0);
pin_mode(pin, PullNone);
}
}
port_dir(obj, dir);
}
void port_mode(port_t *obj, PinMode mode) {
for (int i = 0; i < 8; i++) {
if (obj->mask & (1 << i)) {
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir) {
switch (dir) {
case PIN_INPUT: GPIODirModeSet(obj->baseAddr, obj->mask, GPIO_DIR_MODE_IN); break;
case PIN_OUTPUT: GPIODirModeSet(obj->baseAddr, obj->mask, GPIO_DIR_MODE_OUT); break;
}
}
void port_write(port_t *obj, int value) {
GPIOPinWrite(obj->baseAddr, obj->mask, value);
}
int port_read(port_t *obj) {
return (int)(GPIOPinRead(obj->baseAddr, obj->mask));
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pwmout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include <ti/devices/cc32xx/inc/hw_apps_config.h>
#include <ti/devices/cc32xx/inc/hw_ocp_shared.h>
#include <ti/devices/cc32xx/inc/hw_types.h>
#include <ti/devices/cc32xx/inc/hw_timer.h>
#include <ti/devices/cc32xx/inc/hw_memmap.h>
#include <ti/devices/cc32xx/driverlib/rom.h>
#include <ti/devices/cc32xx/driverlib/rom_map.h>
#include <ti/devices/cc32xx/driverlib/gpio.h>
#include <ti/devices/cc32xx/driverlib/pin.h>
#include <ti/devices/cc32xx/driverlib/ti_timer.h>
static const uint32_t timerBaseAddresses[4] = {
CC3220SF_TIMERA0_BASE,
CC3220SF_TIMERA1_BASE,
CC3220SF_TIMERA2_BASE,
CC3220SF_TIMERA3_BASE,
};
static const uint32_t timerHalves[2] = {
TIMER_A,
TIMER_B,
};
/*static const uint32_t gpioBaseAddresses[4] = {
CC3220SF_GPIOA0_BASE,
CC3220SF_GPIOA1_BASE,
CC3220SF_GPIOA2_BASE,
CC3220SF_GPIOA3_BASE,
};*/
/*static const uint32_t gpioPinIndexes[8] = {
GPIO_PIN_0,
GPIO_PIN_1,
GPIO_PIN_2,
GPIO_PIN_3,
GPIO_PIN_4,
GPIO_PIN_5,
GPIO_PIN_6,
GPIO_PIN_7,
};*/
#define PinConfigTimerPort(config) (((config) >> 28) & 0xF)
#define PinConfigTimerHalf(config) (((config) >> 24) & 0xF)
#define PinConfigGPIOPort(config) (((config) >> 20) & 0xF)
#define PinConfigGPIOPinIndex(config) (((config) >> 16) & 0xF)
#define PinConfigPinMode(config) (((config) >> 8) & 0xF)
#define PinConfigPin(config) (((config) >> 0) & 0x3F)
#define PWMTimerCC32XX_T0A (0x00 << 24)
#define PWMTimerCC32XX_T0B (0x01 << 24)
#define PWMTimerCC32XX_T1A (0x10 << 24)
#define PWMTimerCC32XX_T1B (0x11 << 24)
#define PWMTimerCC32XX_T2A (0x20 << 24)
#define PWMTimerCC32XX_T2B (0x21 << 24)
#define PWMTimerCC32XX_T3A (0x30 << 24)
#define PWMTimerCC32XX_T3B (0x31 << 24)
#define PWMTimerCC32XX_GPIO9 (0x11 << 16)
#define PWMTimerCC32XX_GPIO10 (0x12 << 16)
#define PWMTimerCC32XX_GPIO11 (0x13 << 16)
#define PWMTimerCC32XX_GPIO24 (0x30 << 16)
#define PWMTimerCC32XX_GPIO25 (0x31 << 16)
#define PWMTimerCC32XX_GPIONONE (0xFF << 16)
#define PWMTimerCC32XX_PIN_01 (PWMTimerCC32XX_T3A | PWMTimerCC32XX_GPIO10 | 0x0300)
#define PWMTimerCC32XX_PIN_02 (PWMTimerCC32XX_T3B | PWMTimerCC32XX_GPIO11 | 0x0301)
#define PWMTimerCC32XX_PIN_17 (PWMTimerCC32XX_T0A | PWMTimerCC32XX_GPIO24 | 0x0510)
#define PWMTimerCC32XX_PIN_19 (PWMTimerCC32XX_T1B | PWMTimerCC32XX_GPIONONE | 0x0812)
#define PWMTimerCC32XX_PIN_21 (PWMTimerCC32XX_T1A | PWMTimerCC32XX_GPIO25 | 0x0914)
#define PWMTimerCC32XX_PIN_64 (PWMTimerCC32XX_T2B | PWMTimerCC32XX_GPIO9 | 0x033F)
//static unsigned int pwm_clock_mhz;
void pwmout_init(pwmout_t* obj, PinName pin) {
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
obj->pwm = pwm;
switch(pin) {
case PIN_01: obj->pwmPin = PWMTimerCC32XX_PIN_01; break;
case PIN_02: obj->pwmPin = PWMTimerCC32XX_PIN_02; break;
case PIN_17: obj->pwmPin = PWMTimerCC32XX_PIN_17; break;
case PIN_19: obj->pwmPin = PWMTimerCC32XX_PIN_19; break;
case PIN_21: obj->pwmPin = PWMTimerCC32XX_PIN_21; break;
case PIN_64: obj->pwmPin = PWMTimerCC32XX_PIN_64; break;
default: break;
}
uint32_t timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(obj->pwmPin)];
uint16_t halfTimer = timerHalves[PinConfigTimerHalf(obj->pwmPin)];
MAP_TimerDisable(timerBaseAddr, halfTimer);
/*
* The CC32XX SDK TimerConfigure API halts both timers when it is
* used to configure a single half timer. The code below performs
* the register operations necessary to configure each half timer
* individually.
*/
/* Enable CCP to IO path */
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_GPT_TRIG_SEL) = 0xFF;
/* Split the timer and configure it as a PWM */
uint32_t timerConfigVal = ((halfTimer & (TIMER_CFG_A_PWM | TIMER_CFG_B_PWM)) |
TIMER_CFG_SPLIT_PAIR);
HWREG(timerBaseAddr + TIMER_O_CFG) |= (timerConfigVal >> 24);
if (halfTimer & TIMER_A) {
HWREG(timerBaseAddr + TIMER_O_TAMR) = timerConfigVal & 255;
}
else {
HWREG(timerBaseAddr + TIMER_O_TBMR) = (timerConfigVal >> 8) & 255;
}
/* Set the peripheral output to active-high */
MAP_TimerControlLevel(timerBaseAddr, halfTimer, true);
uint16_t mode = PinConfigPinMode(obj->pwmPin);
/* Start the timer & set pinmux to PWM mode */
MAP_TimerEnable(timerBaseAddr, halfTimer);
MAP_PinTypeTimer((unsigned long)pin, (unsigned long)mode);
}
void pwmout_free(pwmout_t* obj) {
// [TODO]
}
void pwmout_write(pwmout_t* obj, float value) {
}
float pwmout_read(pwmout_t* obj) {
return 0;
}
void pwmout_period(pwmout_t* obj, float seconds) {
pwmout_period_us(obj, seconds * 1000000.0f);
}
void pwmout_period_ms(pwmout_t* obj, int ms) {
pwmout_period_us(obj, ms * 1000);
}
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t* obj, int us) {
}
void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
pwmout_pulsewidth_us(obj, ms * 1000);
}
void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
}

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/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "rtc_api.h"
#if DEVICE_RTC
#include "ti/devices/cc32xx/inc/hw_types.h"
#include "ti/devices/cc32xx/driverlib/prcm.h"
void rtc_init(void) {
static bool rtc_initialized = false;
if (!rtc_initialized)
{
if (!PRCMRTCInUseGet())
{
PRCMRTCInUseSet();
}
rtc_initialized = true;
}
}
void rtc_free(void) {
}
int rtc_isenabled(void) {
return PRCMRTCInUseGet();
}
time_t rtc_read(void) {
unsigned long ulSecs = 0;
unsigned short usMsec = 0;
PRCMRTCGet(&ulSecs, &usMsec);
return ulSecs;
}
void rtc_write(time_t t) {
PRCMRTCSet(t, 0);
}
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// math.h required for floating point operations for baud rate calculation
#include <math.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "mbed_assert.h"
#include "serial_api.h"
#include "serial_object.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "gpio_api.h"
#include "PeripheralPins.h"
#include <ti/devices/cc32xx/inc/hw_memmap.h>
#include <ti/devices/cc32xx/inc/hw_ocp_shared.h>
#include <ti/devices/cc32xx/inc/hw_ints.h>
#include <ti/devices/cc32xx/inc/hw_types.h>
#include <ti/devices/cc32xx/inc/hw_uart.h>
#include <ti/devices/cc32xx/inc/hw_common_reg.h>
#include <ti/devices/cc32xx/driverlib/rom.h>
#include <ti/devices/cc32xx/driverlib/rom_map.h>
#include <ti/devices/cc32xx/driverlib/uart.h>
#include <ti/devices/cc32xx/driverlib/pin.h>
#include <ti/devices/cc32xx/driverlib/prcm.h>
#include <ti/devices/cc32xx/driverlib/interrupt.h>
#include <ti/devices/cc32xx/driverlib/utils.h>
/******************************************************************************
* INITIALIZATION
******************************************************************************/
#define UART_NUM 2
static const uint32_t dataLength[] = {
UART_CONFIG_WLEN_5, /* UART_LEN_5 */
UART_CONFIG_WLEN_6, /* UART_LEN_6 */
UART_CONFIG_WLEN_7, /* UART_LEN_7 */
UART_CONFIG_WLEN_8 /* UART_LEN_8 */
};
static const uint32_t stopBits[] = {
UART_CONFIG_STOP_ONE, /* UART_STOP_ONE */
UART_CONFIG_STOP_TWO /* UART_STOP_TWO */
};
static const uint32_t parityType[] = {
UART_CONFIG_PAR_NONE, /* UART_PAR_NONE */
UART_CONFIG_PAR_EVEN, /* UART_PAR_EVEN */
UART_CONFIG_PAR_ODD, /* UART_PAR_ODD */
UART_CONFIG_PAR_ZERO, /* UART_PAR_ZERO */
UART_CONFIG_PAR_ONE /* UART_PAR_ONE */
};
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
struct serial_global_data_s {
uint32_t serial_irq_id;
gpio_t sw_rts, sw_cts;
uint8_t count, rx_irq_set_flow, rx_irq_set_api;
};
static struct serial_global_data_s uart_data[UART_NUM];
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
int is_stdio_uart = 0;
// determine the UART to use
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)uart != NC);
obj->uart = (CC3220SF_UART_TypeDef *)uart;
// Set default values for UART
obj->dataLength = UART_LEN_8;
obj->stopBits = UART_STOP_ONE;
obj->parityType = UART_PAR_NONE;
switch (uart) {
case UART_0: {
obj->index = 0;
obj->baseAddr = CC3220SF_UARTA0_BASE;
obj->powerMgrId = 12; /*!< Resource ID: UART 0 */
obj->intNum = INT_UARTA0_IRQn;
obj->peripheralId = PRCM_UARTA0;
}
break;
case UART_1: {
obj->index = 1;
obj->baseAddr = CC3220SF_UARTA1_BASE;
obj->powerMgrId = 13; /*!< Resource ID: UART 1 */
obj->intNum = INT_UARTA1_IRQn;
obj->peripheralId = PRCM_UARTA1;
}
break;
}
PRCMPeripheralClkEnable(obj->peripheralId, PRCM_RUN_MODE_CLK);
// Pinout the chosen uart
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
MAP_PinTypeUART(tx, pinmap_function(tx, PinMap_UART_TX));
MAP_PinTypeUART(rx, pinmap_function(rx, PinMap_UART_RX));
MAP_UARTEnable(obj->baseAddr);
// Set default baud rate and format
serial_baud(obj, 9600);
serial_format(obj, 8, ParityNone, 1);
// set rx/tx pins in PullUp mode
if (tx != NC) {
pin_mode(tx, PullUp);
}
if (rx != NC) {
pin_mode(rx, PullUp);
}
/* Set flow control */
uart_data[obj->index].sw_rts.pin = NC;
uart_data[obj->index].sw_cts.pin = NC;
serial_set_flow_control(obj, FlowControlNone, NC, NC);
is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
if (is_stdio_uart) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj)
{
uart_data[obj->index].serial_irq_id = 0;
}
void serial_baud(serial_t *obj, int baudrate)
{
obj->baudRate = baudrate;
MAP_UARTConfigSetExpClk(obj->baseAddr, MAP_PRCMPeripheralClockGet(obj->peripheralId),
obj->baudRate, (dataLength[obj->dataLength] |
stopBits[obj->stopBits] | parityType[obj->parityType]));
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
(parity == ParityForced1) || (parity == ParityForced0));
stop_bits -= 1;
data_bits -= 5;
switch (parity) {
case ParityNone:
obj->parityType = UART_PAR_NONE;
break;
case ParityOdd :
obj->parityType = UART_PAR_ODD;
break;
case ParityEven:
obj->parityType = UART_PAR_EVEN;
break;
case ParityForced1:
obj->parityType = UART_PAR_ONE;
break;
case ParityForced0:
obj->parityType = UART_PAR_ZERO;
break;
default:
obj->parityType = UART_PAR_NONE;
break;
}
switch (data_bits) {
case 0:
obj->dataLength = UART_LEN_5;
break;
case 1:
obj->dataLength = UART_LEN_6;
break;
case 2:
obj->dataLength = UART_LEN_7;
break;
case 3:
obj->dataLength = UART_LEN_8;
break;
default:
obj->dataLength = UART_LEN_8;
break;
}
switch (stop_bits) {
case 0:
obj->stopBits = UART_STOP_ONE;
break;
case 1:
obj->stopBits = UART_STOP_TWO;
break;
default:
obj->stopBits = UART_STOP_ONE;
break;
}
MAP_UARTConfigSetExpClk(obj->baseAddr, MAP_PRCMPeripheralClockGet(obj->peripheralId),
obj->baudRate, (dataLength[obj->dataLength] |
stopBits[obj->stopBits] | parityType[obj->parityType]));
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static inline void uart_irq(uint32_t intstatus, uint32_t index, CC3220SF_UART_TypeDef *puart)
{
SerialIrq irq_type;
if (intstatus & UART_INT_TX) {
irq_type = TxIrq;
} else {
irq_type = RxIrq;
}
uint32_t rxErrors = puart->RSR & 0x0000000F;
if (rxErrors) {
puart->ECR = 0;
}
if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
gpio_write(&uart_data[index].sw_rts, 1);
// Disable interrupt if it wasn't enabled by other part of the application
if (!uart_data[index].rx_irq_set_api) {
puart->IM &= ~(UART_INT_RX | UART_INT_RT);
}
}
if (uart_data[index].serial_irq_id != 0) {
if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) {
irq_handler(uart_data[index].serial_irq_id, irq_type);
}
}
if (irq_type == TxIrq) {
puart->ICR = UART_INT_TX; // clear TX interrupt
} else {
puart->ICR = UART_INT_RX; // clear RX interrupt
}
}
void uart0_irq()
{
uart_irq(CC3220SF_UART0->MIS, 0, (CC3220SF_UART_TypeDef *)CC3220SF_UART0);
}
void uart1_irq()
{
uart_irq(CC3220SF_UART1->MIS, 1, (CC3220SF_UART_TypeDef *)CC3220SF_UART1);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
uart_data[obj->index].serial_irq_id = id;
}
void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable)
{
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
/* Clear interrupts */
uint32_t status = MAP_UARTIntStatus(obj->baseAddr, true);
MAP_UARTIntClear(obj->baseAddr, status);
switch ((int)obj->uart) {
case UART_0:
irq_n = INT_UARTA0_IRQn;
vector = (uint32_t)&uart0_irq;
break;
case UART_1:
irq_n = INT_UARTA1_IRQn;
vector = (uint32_t)&uart1_irq;
break;
}
if (enable) {
if (irq == TxIrq) {
MAP_UARTIntEnable(obj->baseAddr, UART_INT_TX);
} else {
MAP_UARTIntEnable(obj->baseAddr, UART_INT_RX);
}
NVIC_SetVector(irq_n, vector);
NVIC_EnableIRQ(irq_n);
} else {
/* Disable IRQ */
MAP_UARTIntDisable(obj->baseAddr, UART_INT_TX | UART_INT_RX);
NVIC_DisableIRQ(irq_n);
}
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
if (RxIrq == irq) {
uart_data[obj->index].rx_irq_set_api = enable;
}
serial_irq_set_internal(obj, irq, enable);
}
/*static void serial_flow_irq_set(serial_t *obj, uint32_t enable)
{
uart_data[obj->index].rx_irq_set_flow = enable;
serial_irq_set_internal(obj, RxIrq, enable);
}*/
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj)
{
while (!serial_readable(obj));
return obj->uart->DR;
}
void serial_putc(serial_t *obj, int c)
{
while (!serial_writable(obj));
obj->uart->DR = c;
}
int serial_readable(serial_t *obj)
{
return ((obj->uart->FR & UART_FR_RXFE) ? 0 : 1);
}
int serial_writable(serial_t *obj)
{
return ((obj->uart->FR & UART_FR_TXFF) ? 0 : 1);
}
void serial_clear(serial_t *obj)
{
obj->uart->DR = 0x00;
}
void serial_pinout_tx(PinName tx)
{
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj)
{
MAP_UARTBreakCtl(obj->baseAddr, true);
}
void serial_break_clear(serial_t *obj)
{
MAP_UARTBreakCtl(obj->baseAddr, false);
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
switch (type) {
case FlowControlRTS:
pinmap_pinout(rxflow, PinMap_UART_RTS);
MAP_UARTFlowControlSet(obj->baseAddr, UART_FLOWCONTROL_RX);
MAP_UARTModemControlSet(obj->baseAddr, UART_OUTPUT_RTS);
break;
case FlowControlCTS:
pinmap_pinout(txflow, PinMap_UART_CTS);
MAP_UARTFlowControlSet(obj->baseAddr, UART_FLOWCONTROL_TX);
MAP_UARTModemControlClear(obj->baseAddr, UART_OUTPUT_RTS);
break;
case FlowControlRTSCTS:
pinmap_pinout(rxflow, PinMap_UART_RTS);
pinmap_pinout(txflow, PinMap_UART_CTS);
MAP_UARTFlowControlSet(obj->baseAddr, UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX);
MAP_UARTModemControlSet(obj->baseAddr, UART_OUTPUT_RTS);
break;
case FlowControlNone:
MAP_UARTFlowControlSet(obj->baseAddr, UART_FLOWCONTROL_NONE);
MAP_UARTModemControlClear(obj->baseAddr, UART_OUTPUT_RTS);
break;
}
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_SERIAL_OBJECT_H
#define MBED_SERIAL_OBJECT_H
#include "mbed_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum UART_LEN_ {
UART_LEN_5 = 0, /*!< Data length is 5 bits */
UART_LEN_6 = 1, /*!< Data length is 6 bits */
UART_LEN_7 = 2, /*!< Data length is 7 bits */
UART_LEN_8 = 3 /*!< Data length is 8 bits */
} UART_LEN;
typedef enum UART_STOP_ {
UART_STOP_ONE = 0, /*!< One stop bit */
UART_STOP_TWO = 1 /*!< Two stop bits */
} UART_STOP;
typedef enum UART_PAR_ {
UART_PAR_NONE = 0, /*!< No parity */
UART_PAR_EVEN = 1, /*!< Parity bit is even */
UART_PAR_ODD = 2, /*!< Parity bit is odd */
UART_PAR_ZERO = 3, /*!< Parity bit is always zero */
UART_PAR_ONE = 4 /*!< Parity bit is always one */
} UART_PAR;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if DEVICE_SPI
#include <stdlib.h>
#include "hal/spi_api.h"
#include "objects.h"
#include "ti/devices/cc32xx/inc/hw_ints.h"
#include "ti/devices/cc32xx/inc/hw_memmap.h"
#include "ti/devices/cc32xx/inc/hw_types.h"
#include "ti/devices/cc32xx/driverlib/pin.h"
#include "ti/devices/cc32xx/driverlib/rom_map.h"
#include "ti/devices/cc32xx/driverlib/ti_spi_driverlib.h"
#include "ti/devices/cc32xx/driverlib/prcm.h"
#define PIN_MODE_SPI 7
#define SPI_WL_MASK 0xF80
/**
* Brief Reconfigure peripheral.
*
* If the peripheral has changed ownership clear old configuration and
* re-initialize the peripheral with the new settings.
*
* Parameter obj The object
*/
static void spi_configure_driver_instance(spi_t *obj)
{
#if DEVICE_SPI_ASYNCH
struct spi_s *spi_inst = &obj->spi;
#else
struct spi_s *spi_inst = obj;
#endif
if (spi_inst->clock_update)
{
SPIReset(spi_inst->baseAddr);
SPIConfigSetExpClk(spi_inst->baseAddr, spi_inst->clock_config.ulSPIClk,
spi_inst->clock_config.ulBitRate, spi_inst->clock_config.ulMode,
spi_inst->clock_config.ulSubMode, spi_inst->clock_config.ulConfig);
spi_inst->clock_update = false;
SPIEnable(spi_inst->baseAddr);
}
}
/** Initialize the SPI peripheral
*
* Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
* Parameter obj The SPI object to initialize
* Parameter mosi The pin to use for MOSI
* Parameter miso The pin to use for MISO
* Parameter sclk The pin to use for SCLK
* Parameter ssel The pin to use for SSEL
*/
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
#if DEVICE_SPI_ASYNCH
struct spi_s *spi_inst = &obj->spi;
#else
struct spi_s *spi_inst = obj;
#endif
/* Get instance based on requested pins. */
spi_inst->instance = 1;
spi_inst->baseAddr = GSPI_BASE;
spi_inst->clock_config.ulConfig = SPI_4PIN_MODE;
spi_inst->clock_config.ulConfig |= SPI_HW_CTRL_CS;
spi_inst->clock_config.ulConfig |= SPI_CS_ACTIVELOW;
if (ssel == NC)
{
spi_inst->cs_control_gpio = true;
}
else
{
spi_inst->cs_control_gpio = false;
}
spi_inst->clock_config.ulConfig |= SPI_TURBO_OFF;
#if DEVICE_SPI_ASYNCH
/* Set default values for asynchronous variables. */
spi_inst->handler = 0;
spi_inst->mask = 0;
spi_inst->event = 0;
#endif
/* Configure GPIO pin if chip select has been set. */
MAP_PinTypeSPI((unsigned long) mosi & 0xff, (unsigned long) PIN_MODE_SPI);
MAP_PinTypeSPI((unsigned long) miso & 0xff, (unsigned long) PIN_MODE_SPI);
MAP_PinTypeSPI((unsigned long) sclk & 0xff, (unsigned long) PIN_MODE_SPI);
if (ssel != NC)
{
MAP_PinTypeSPI((unsigned long) ssel & 0xff, (unsigned long) PIN_MODE_SPI);
}
spi_inst->clock_update = true;
}
/** Release a SPI object
*
* TODO: spi_free is currently unimplemented
* This will require reference counting at the C++ level to be safe
*
* Return the pins owned by the SPI object to their reset state
* Disable the SPI peripheral
* Disable the SPI clock
* Parameter obj The SPI object to deinitialize
*/
void spi_free(spi_t *obj)
{
}
/** Configure the SPI format
*
* Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
* The default bit order is MSB.
* Parameter obj The SPI object to configure
* Parameter bits The number of bits per frame
* Parameter mode The SPI mode (clock polarity, phase, and shift direction)
* Parameter slave Zero for master mode or non-zero for slave mode
*/
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
/* SPI module supports 8/16/32 bit transfers. */
MBED_ASSERT(bits == 8 || bits == 16 || bits == 32);
/* SPI module doesn't support Mbed HAL Slave API. */
MBED_ASSERT(slave == 0);
#if DEVICE_SPI_ASYNCH
struct spi_s *spi_inst = &obj->spi;
#else
struct spi_s *spi_inst = obj;
#endif
if ((uint32_t)bits != spi_inst->word_length)
{
spi_inst->word_length = bits;
spi_inst->clock_update = true;
}
spi_inst->clock_config.ulConfig &= ~SPI_WL_MASK;
spi_inst->clock_config.ulConfig |= (bits - 1) << 7;
spi_inst->clock_config.ulMode = SPI_MODE_MASTER;
// TI calls it submode
// SPI_SUB_MODE_0 - clk active high, sampling on the rising edge
// SPI_SUB_MODE_1 - clk active high, sampling on the falling edge
// SPI_SUB_MODE_2 - clk active low, sampling on the falling edge
// SPI_SUB_MODE_3 - clk active low, sampling on the rising edge
/* Convert Mbed HAL mode to TI mode. */
if(mode == 0) {
if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_0)
{
spi_inst->clock_update = true;
}
spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_0;
} else if(mode == 1) {
if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_1)
{
spi_inst->clock_update = true;
}
spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_1;
} else if(mode == 2) {
if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_2)
{
spi_inst->clock_update = true;
}
spi_inst->clock_config.ulSubMode = SPI_SUB_MODE_2;
} else if(mode == 3) {
if (spi_inst->clock_config.ulSubMode != SPI_SUB_MODE_3)
{
spi_inst->clock_update = true;
}
spi_inst->clock_config.ulSubMode= SPI_SUB_MODE_3;
}
spi_configure_driver_instance(spi_inst);
}
/** Set the SPI baud rate
*
* Actual frequency may differ from the desired frequency due to available dividers and bus clock
* Configures the SPI peripheral's baud rate
* Parameter obj The SPI object to configure
* Parameter hz The baud rate in Hz
*/
void spi_frequency(spi_t *obj, int hz)
{
#if DEVICE_SPI_ASYNCH
struct spi_s *spi_inst = &obj->spi;
#else
struct spi_s *spi_inst = obj;
#endif
spi_inst->clock_config.ulSPIClk = PRCMPeripheralClockGet(PRCM_GSPI);
if (spi_inst->clock_config.ulBitRate != (uint32_t)hz)
{
spi_inst->clock_update = true;
spi_inst->clock_config.ulBitRate = hz;
}
spi_configure_driver_instance(spi_inst);
}
/** Write a byte out in master mode and receive a value
*
* Parameter obj The SPI peripheral to use for sending
* Parameter value The value to send
* Return Returns the value received during send
*/
int spi_master_write(spi_t *obj, int value)
{
#if DEVICE_SPI_ASYNCH
struct spi_s *spi_inst = &obj->spi;
#else
struct spi_s *spi_inst = obj;
#endif
uint32_t data_read = 0;
/* Configure peripheral if necessary. */
spi_configure_driver_instance(obj);
if (!spi_inst->cs_control_gpio)
{
SPICSEnable(spi_inst->baseAddr);
}
/* Transfer a data word. */
SPIDataPut(spi_inst->baseAddr, value);
SPIDataGet(spi_inst->baseAddr, (unsigned long *)&data_read);
if (!spi_inst->cs_control_gpio)
{
SPICSDisable(spi_inst->baseAddr);
}
return data_read & ((1 << spi_inst->word_length) - 1);
}
/** Write a block out in master mode and receive a value
*
* The total number of bytes sent and received will be the maximum of
* tx_length and rx_length. The bytes written will be padded with the
* value 0xff.
*
* Parameter obj The SPI peripheral to use for sending
* Parameter tx_buffer Pointer to the byte-array of data to write to the device
* Parameter tx_length Number of bytes to write, may be zero
* Parameter rx_buffer Pointer to the byte-array of data to read from the device
* Parameter rx_length Number of bytes to read, may be zero
* Parameter write_fill Default data transmitted while performing a read
* @returns
* The number of bytes written and read from the device. This is
* maximum of tx_length and rx_length.
*/
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill)
{
#if DEVICE_SPI_ASYNCH
struct spi_s *spi_inst = &obj->spi;
#else
struct spi_s *spi_inst = obj;
#endif
int i, spi_words = 0, cs_flags = 0;;
/* Configure peripheral if necessary. */
spi_configure_driver_instance(obj);
if (tx_length >= rx_length)
{
if (spi_inst->word_length == 16)
{
spi_words = (tx_length >> 1);
}
else if (spi_inst->word_length == 32)
{
spi_words = (tx_length >> 2);
}
else if (spi_inst->word_length == 8)
{
spi_words = tx_length;
}
unsigned char *rx_temp = malloc(tx_length);
SPITransfer(spi_inst->baseAddr, (unsigned char *)tx_buffer,
(unsigned char *)rx_temp, (unsigned long) spi_words,
SPI_CS_ENABLE | SPI_CS_DISABLE);
// Copy the desired data from temp_rx
for (i = 0; i < rx_length; i ++)
{
rx_buffer[i] = rx_temp[i];
}
free(rx_temp);
return (tx_length);
}
else // tx_length < rx_length
// Copy the data from tx_buffer to a temp buffer and fill the the rest of the tx_buffer with write_fill)
{
if (spi_inst->word_length == 16)
{
spi_words = (rx_length >> 1);
}
else if (spi_inst->word_length == 32)
{
spi_words = (rx_length >> 2);
}
else if (spi_inst->word_length == 8)
{
spi_words = rx_length;
}
unsigned char *tx_temp = malloc(rx_length);
for (i = 0; i < tx_length; i ++)
{
tx_temp[i] = tx_buffer[i];
}
for (i = tx_length; i < rx_length; i ++)
{
tx_temp[i] = write_fill;
}
if (!spi_inst->cs_control_gpio)
{
cs_flags = SPI_CS_ENABLE | SPI_CS_DISABLE;
}
SPITransfer(spi_inst->baseAddr, (unsigned char *)tx_temp,
(unsigned char *)rx_buffer, (unsigned long) spi_words,
cs_flags);
free(tx_temp);
return rx_length;
}
}
/** Checks if the specified SPI peripheral is in use
*
* Parameter obj The SPI peripheral to check
* Return non-zero if the peripheral is currently transmitting
*/
int spi_busy(spi_t *obj)
{
/* Legacy API call. Always return zero. */
return 0;
}
/** Get the module number
*
* Parameter obj The SPI peripheral to check
* Return The module number
*/
uint8_t spi_get_module(spi_t *obj)
{
#if DEVICE_SPI_ASYNCH
struct spi_s *spi_inst = &obj->spi;
#else
struct spi_s *spi_inst = obj;
#endif
return spi_inst->instance;
}
#if DEVICE_SPISLAVE
/** Check if a value is available to read
*
* Parameter obj The SPI peripheral to check
* Return non-zero if a value is available
*/
int spi_slave_receive(spi_t *obj)
{
return 0;
}
/** Get a received value out of the SPI receive buffer in slave mode
*
* Blocks until a value is available
* Parameter obj The SPI peripheral to read
* Return The value received
*/
int spi_slave_read(spi_t *obj)
{
return 0;
}
/** Write a value to the SPI peripheral in slave mode
*
* Blocks until the SPI peripheral can be written to
* Parameter obj The SPI peripheral to write
* Parameter value The value to write
*/
void spi_slave_write(spi_t *obj, int value)
{
return;
}
#endif
#if DEVICE_SPI_ASYNCH
/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
*
* Parameter obj The SPI object that holds the transfer information
* Parameter tx The transmit buffer
* Parameter tx_length The number of bytes to transmit
* Parameter rx The receive buffer
* Parameter rx_length The number of bytes to receive
* Parameter bit_width The bit width of buffer words
* Parameter event The logical OR of events to be registered
* Parameter handler SPI interrupt handler
* Parameter hint A suggestion for how to use DMA with this transfer
*/
void spi_master_transfer(spi_t *obj,
const void *tx,
size_t tx_length,
void *rx,
size_t rx_length,
uint8_t bit_width,
uint32_t handler,
uint32_t mask,
DMAUsage hint)
{
}
/** The asynchronous IRQ handler
*
* Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
* conditions, such as buffer overflows or transfer complete.
* Parameter obj The SPI object that holds the transfer information
* Return Event flags if a transfer termination condition was met; otherwise 0.
*/
uint32_t spi_irq_handler_asynch(spi_t *obj)
{
/* Return latest event. */
return obj->spi.event;
}
/** Attempts to determine if the SPI peripheral is already in use
*
* If a temporary DMA channel has been allocated, peripheral is in use.
* If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
* channel were allocated.
* If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
* if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
* there are any bytes in the FIFOs.
* Parameter obj The SPI object to check for activity
* Return Non-zero if the SPI port is active or zero if it is not.
*/
uint8_t spi_active(spi_t *obj)
{
/* Callback handler is non-zero when a transfer is in progress. */
return (obj->spi.handler != 0);
}
/** Abort an SPI transfer
*
* Parameter obj The SPI peripheral to stop
*/
void spi_abort_asynch(spi_t *obj)
{
}
#endif // DEVICE_SPI_ASYNCH
#endif // DEVICE_SPI

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/DeviceFamily.h Executable file
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/*
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file DeviceFamily.h
*
* @brief Infrastructure to select correct driverlib path and identify devices
*
* This module enables the selection of the correct driverlib path for the current
* device. It also facilitates the use of per-device conditional compilation
* to enable minor variations in drivers between devices.
*
* In order to use this functionality, DeviceFamily_XYZ must be defined as one of
* the supported values. The DeviceFamily_ID and DeviceFamily_DIRECTORY defines
* are set based on DeviceFamily_XYZ.
*/
#ifndef ti_devices_DeviceFamily__include
#define ti_devices_DeviceFamily__include
#ifdef __cplusplus
extern "C" {
#endif
/*
* DeviceFamily_ID_XYZ values.
*
* DeviceFamily_ID may be used in the preprocessor for conditional compilation.
* DeviceFamily_ID is set to one of these values based on the top level
* DeviceFamily_XYZ define.
*/
#define DeviceFamily_ID_CC13X0 1
#define DeviceFamily_ID_CC26X0 2
#define DeviceFamily_ID_CC26X0R2 3
#define DeviceFamily_ID_CC13X2_V1 4
#define DeviceFamily_ID_CC13X2_V2 5
#define DeviceFamily_ID_CC13X2 DeviceFamily_ID_CC13X2_V1
#define DeviceFamily_ID_CC26X2_V1 6
#define DeviceFamily_ID_CC26X2_V2 7
#define DeviceFamily_ID_CC26X2 DeviceFamily_ID_CC26X2_V1
#define DeviceFamily_ID_CC3200 8
#define DeviceFamily_ID_CC3220 9
#define DeviceFamily_ID_MSP432P401x 10
#define DeviceFamily_ID_MSP432P4x1xI 11
#define DeviceFamily_ID_MSP432P4x1xT 12
#define DeviceFamily_ID_MSP432E401Y 13
#define DeviceFamily_ID_MSP432E411Y 14
/*
* DeviceFamily_PARENT_XYZ values.
*
* DeviceFamily_PARENT may be used in the preprocessor for conditional
* compilation. DeviceFamily_PARENT is set to one of these values based
* on the top-level DeviceFamily_XYZ define.
*/
#define DeviceFamily_PARENT_CC13X0_CC26X0 1
#define DeviceFamily_PARENT_CC13X2_CC26X2 2
#define DeviceFamily_PARENT_MSP432P401R 3
#define DeviceFamily_PARENT_MSP432P4111 4
/*
* Lookup table that sets DeviceFamily_ID, DeviceFamily_DIRECTORY, and
* DeviceFamily_PARENT based on the DeviceFamily_XYZ define.
* If DeviceFamily_XYZ is undefined, a compiler error is thrown. If
* multiple DeviceFamily_XYZ are defined, the first one encountered is used.
*/
#if defined(DeviceFamily_CC13X0)
#define DeviceFamily_ID DeviceFamily_ID_CC13X0
#define DeviceFamily_DIRECTORY cc13x0
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0
#elif defined(DeviceFamily_CC13X2)
#define DeviceFamily_ID DeviceFamily_ID_CC13X2
#define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2
#elif defined(DeviceFamily_CC13X2_V1)
#define DeviceFamily_ID DeviceFamily_ID_CC13X2_V1
#define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2
#elif defined(DeviceFamily_CC13X2_V2)
#define DeviceFamily_ID DeviceFamily_ID_CC13X2_V2
#define DeviceFamily_DIRECTORY cc13x2_cc26x2_v2
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2
#elif defined(DeviceFamily_CC26X0)
#define DeviceFamily_ID DeviceFamily_ID_CC26X0
#define DeviceFamily_DIRECTORY cc26x0
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0
#elif defined(DeviceFamily_CC26X0R2)
#define DeviceFamily_ID DeviceFamily_ID_CC26X0R2
#define DeviceFamily_DIRECTORY cc26x0r2
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0
#elif defined(DeviceFamily_CC26X2)
#define DeviceFamily_ID DeviceFamily_ID_CC26X2
#define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2
#elif defined(DeviceFamily_CC26X2_V1)
#define DeviceFamily_ID DeviceFamily_ID_CC26X2_V1
#define DeviceFamily_DIRECTORY cc13x2_cc26x2_v1
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2
#elif defined(DeviceFamily_CC26X2_V2)
#define DeviceFamily_ID DeviceFamily_ID_CC26X2_V2
#define DeviceFamily_DIRECTORY cc13x2_cc26x2_v2
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2
#elif defined(DeviceFamily_CC3200)
#define DeviceFamily_ID DeviceFamily_ID_CC3200
#define DeviceFamily_DIRECTORY cc32xx
#elif defined(DeviceFamily_CC3220)
#define DeviceFamily_ID DeviceFamily_ID_CC3220
#define DeviceFamily_DIRECTORY cc32xx
#elif defined(DeviceFamily_MSP432P401x) || defined(__MSP432P401R__)
#define DeviceFamily_ID DeviceFamily_ID_MSP432P401x
#define DeviceFamily_DIRECTORY msp432p4xx
#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P401R
#if !defined(__MSP432P401R__)
#define __MSP432P401R__
#endif
#elif defined(DeviceFamily_MSP432P4x1xI)
#define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xI
#define DeviceFamily_DIRECTORY msp432p4xx
#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111
#if !defined(__MSP432P4111__)
#define __MSP432P4111__
#endif
#elif defined(DeviceFamily_MSP432P4x1xT)
#define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xT
#define DeviceFamily_DIRECTORY msp432p4xx
#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111
#if !defined(__MSP432P4111__)
#define __MSP432P4111__
#endif
#elif defined(DeviceFamily_MSP432E401Y)
#define DeviceFamily_ID DeviceFamily_ID_MSP432E401Y
#define DeviceFamily_DIRECTORY msp432e4
#if !defined(__MSP432E401Y__)
#define __MSP432E401Y__
#endif
#elif defined(DeviceFamily_MSP432E411Y)
#define DeviceFamily_ID DeviceFamily_ID_MSP432E411Y
#define DeviceFamily_DIRECTORY msp432e4
#if !defined(__MSP432E411Y__)
#define __MSP432E411Y__
#endif
#else
#error "DeviceFamily_XYZ undefined. You must defined DeviceFamily_XYZ!"
#endif
/*!
* @brief Macro to include correct driverlib path.
*
* @pre DeviceFamily_XYZ which sets DeviceFamily_DIRECTORY must be defined
* first.
*
* @param x A token containing the path of the file to include based on
* the root device folder. The preceding forward slash must be
* omitted. For example:
* - #include DeviceFamily_constructPath(inc/hw_memmap.h)
* - #include DeviceFamily_constructPath(driverlib/ssi.h)
*
* @return Returns an include path.
*
*/
#define DeviceFamily_constructPath(x) <ti/devices/DeviceFamily_DIRECTORY/x>
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_DeviceFamily__include */

693
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// adc.c
//
// Driver for the ADC module.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup ADC_Analog_to_Digital_Converter_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ints.h"
#include "inc/hw_adc.h"
#include "inc/hw_apps_config.h"
#include "interrupt.h"
#include "adc.h"
//*****************************************************************************
//
//! Enables the ADC
//!
//! \param ulBase is the base address of the ADC
//!
//! This function sets the ADC global enable
//!
//! \return None.
//
//*****************************************************************************
void ADCEnable(unsigned long ulBase)
{
//
// Set the global enable bit in the control register.
//
HWREG(ulBase + ADC_O_ADC_CTRL) |= 0x1;
}
//*****************************************************************************
//
//! Disable the ADC
//!
//! \param ulBase is the base address of the ADC
//!
//! This function clears the ADC global enable
//!
//! \return None.
//
//*****************************************************************************
void ADCDisable(unsigned long ulBase)
{
//
// Clear the global enable bit in the control register.
//
HWREG(ulBase + ADC_O_ADC_CTRL) &= ~0x1 ;
}
//*****************************************************************************
//
//! Enables specified ADC channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//!
//! This function enables specified ADC channel and configures the
//! pin as analog pin.
//!
//! \return None.
//
//*****************************************************************************
void ADCChannelEnable(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulCh;
ulCh = (ulChannel == ADC_CH_0)? 0x02 :
(ulChannel == ADC_CH_1)? 0x04 :
(ulChannel == ADC_CH_2)? 0x08 : 0x10;
HWREG(ulBase + ADC_O_ADC_CH_ENABLE) |= ulCh;
}
//*****************************************************************************
//
//! Disables specified ADC channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channelsber
//!
//! This function disables specified ADC channel.
//!
//! \return None.
//
//*****************************************************************************
void ADCChannelDisable(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulCh;
ulCh = (ulChannel == ADC_CH_0)? 0x02 :
(ulChannel == ADC_CH_1)? 0x04 :
(ulChannel == ADC_CH_2)? 0x08 : 0x10;
HWREG(ulBase + ADC_O_ADC_CH_ENABLE) &= ~ulCh;
}
//*****************************************************************************
//
//! Enables and registers ADC interrupt handler for specified channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//! \param pfnHandler is a pointer to the function to be called when the
//! ADC channel interrupt occurs.
//!
//! This function enables and registers ADC interrupt handler for specified
//! channel. Individual interrupt for each channel should be enabled using
//! \sa ADCIntEnable(). It is the interrupt handler's responsibility to clear
//! the interrupt source.
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! \return None.
//
//*****************************************************************************
void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel,
void (*pfnHandler)(void))
{
unsigned long ulIntNo;
//
// Get the interrupt number associted with the specified channel
//
ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 :
(ulChannel == ADC_CH_1)? INT_ADCCH1 :
(ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3;
//
// Register the interrupt handler
//
IntRegister(ulIntNo,pfnHandler);
//
// Enable ADC interrupt
//
IntEnable(ulIntNo);
}
//*****************************************************************************
//
//! Disables and unregisters ADC interrupt handler for specified channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//!
//! This function disables and unregisters ADC interrupt handler for specified
//! channel. This function also masks off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! \return None.
//
//*****************************************************************************
void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulIntNo;
//
// Get the interrupt number associted with the specified channel
//
ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 :
(ulChannel == ADC_CH_1)? INT_ADCCH1 :
(ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3;
//
// Disable ADC interrupt
//
IntDisable(ulIntNo);
//
// Unregister the interrupt handler
//
IntUnregister(ulIntNo);
}
//*****************************************************************************
//
//! Enables individual interrupt sources for specified channel
//!
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated ADC interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//! - \b ADC_DMA_DONE for DMA done
//! - \b ADC_FIFO_OVERFLOW for FIFO over flow
//! - \b ADC_FIFO_UNDERFLOW for FIFO under flow
//! - \b ADC_FIFO_EMPTY for FIFO empty
//! - \b ADC_FIFO_FULL for FIFO full
//!
//! \return None.
//
//*****************************************************************************
void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags)
{
unsigned long ulOffset;
unsigned long ulDmaMsk;
//
// Enable DMA Done interrupt
//
if(ulIntFlags & ADC_DMA_DONE)
{
ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
(ulChannel == ADC_CH_1)?0x00002000:
(ulChannel == ADC_CH_2)?0x00004000:0x00008000;
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
}
ulIntFlags = ulIntFlags & 0x0F;
//
// Get the interrupt enable register offset for specified channel
//
ulOffset = ADC_O_adc_ch0_irq_en + ulChannel;
//
// Unmask the specified interrupts
//
HWREG(ulBase + ulOffset) |= (ulIntFlags & 0xf);
}
//*****************************************************************************
//
//! Disables individual interrupt sources for specified channel
//!
//!
//! \param ulBase is the base address of the ADC.
//! \param ulChannel is one of the valid ADC channels
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! This function disables the indicated ADC interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The parameters\e ulIntFlags and \e ulChannel should be as explained in
//! ADCIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags)
{
unsigned long ulOffset;
unsigned long ulDmaMsk;
//
// Disable DMA Done interrupt
//
if(ulIntFlags & ADC_DMA_DONE)
{
ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
(ulChannel == ADC_CH_1)?0x00002000:
(ulChannel == ADC_CH_2)?0x00004000:0x00008000;
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
}
//
// Get the interrupt enable register offset for specified channel
//
ulOffset = ADC_O_adc_ch0_irq_en + ulChannel;
//
// Unmask the specified interrupts
//
HWREG(ulBase + ulOffset) &= ~ulIntFlags;
}
//*****************************************************************************
//
//! Gets the current channel interrupt status
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//!
//! This function returns the interrupt status of the specified ADC channel.
//!
//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable().
//!
//! \return Return the ADC channel interrupt status, enumerated as a bit
//! field of values described in ADCIntEnable()
//
//*****************************************************************************
unsigned long ADCIntStatus(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulOffset;
unsigned long ulDmaMsk;
unsigned long ulIntStatus;
//
// Get DMA Done interrupt status
//
ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
(ulChannel == ADC_CH_1)?0x00002000:
(ulChannel == ADC_CH_2)?0x00004000:0x00008000;
ulIntStatus = HWREG(APPS_CONFIG_BASE +
APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED)& ulDmaMsk;
//
// Get the interrupt enable register offset for specified channel
//
ulOffset = ADC_O_adc_ch0_irq_status + ulChannel;
//
// Read ADC interrupt status
//
ulIntStatus |= HWREG(ulBase + ulOffset) & 0xf;
//
// Return the current interrupt status
//
return(ulIntStatus);
}
//*****************************************************************************
//
//! Clears the current channel interrupt sources
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
//!
//! This function clears individual interrupt source for the specified
//! ADC channel.
//!
//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void ADCIntClear(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags)
{
unsigned long ulOffset;
unsigned long ulDmaMsk;
//
// Clear DMA Done interrupt
//
if(ulIntFlags & ADC_DMA_DONE)
{
ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
(ulChannel == ADC_CH_1)?0x00002000:
(ulChannel == ADC_CH_2)?0x00004000:0x00008000;
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
}
//
// Get the interrupt enable register offset for specified channel
//
ulOffset = ADC_O_adc_ch0_irq_status + ulChannel;
//
// Clear the specified interrupts
//
HWREG(ulBase + ulOffset) = (ulIntFlags & ~(ADC_DMA_DONE));
}
//*****************************************************************************
//
//! Enables the ADC DMA operation for specified channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//!
//! This function enables the DMA operation for specified ADC channel
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! \return None.
//
//*****************************************************************************
void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulBitMask;
//
// Get the bit mask for enabling DMA for specified channel
//
ulBitMask = (ulChannel == ADC_CH_0)?0x01:
(ulChannel == ADC_CH_1)?0x04:
(ulChannel == ADC_CH_2)?0x10:0x40;
//
// Enable DMA request for the specified channel
//
HWREG(ulBase + ADC_O_adc_dma_mode_en) |= ulBitMask;
}
//*****************************************************************************
//
//! Disables the ADC DMA operation for specified channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//!
//! This function disables the DMA operation for specified ADC channel
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! \return None.
//
//*****************************************************************************
void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulBitMask;
//
// Get the bit mask for disabling DMA for specified channel
//
ulBitMask = (ulChannel == ADC_CH_0)?0x01:
(ulChannel == ADC_CH_1)?0x04:
(ulChannel == ADC_CH_2)?0x10:0x40;
//
// Disable DMA request for the specified channel
//
HWREG(ulBase + ADC_O_adc_dma_mode_en) &= ~ulBitMask;
}
//*****************************************************************************
//
//! Configures the ADC internal timer
//!
//! \param ulBase is the base address of the ADC
//! \param ulValue is wrap arround value of the timer
//!
//! This function Configures the ADC internal timer. The ADC timer is a 17 bit
//! used to timestamp the ADC data samples internally.
//! User can read the timestamp along with the sample from the FIFO register(s).
//! Each sample in the FIFO contains 14 bit actual data and 18 bit timestamp
//!
//! The parameter \e ulValue can take any value between 0 - 2^17
//!
//! \returns None.
//
//*****************************************************************************
void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue)
{
unsigned long ulReg;
//
// Read the currrent config
//
ulReg = HWREG(ulBase + ADC_O_adc_timer_configuration);
//
// Mask and set timer count field
//
ulReg = ((ulReg & ~0x1FFFF) | (ulValue & 0x1FFFF));
//
// Set the timer count value
//
HWREG(ulBase + ADC_O_adc_timer_configuration) = ulReg;
}
//*****************************************************************************
//
//! Resets ADC internal timer
//!
//! \param ulBase is the base address of the ADC
//!
//! This function resets 17-bit ADC internal timer
//!
//! \returns None.
//
//*****************************************************************************
void ADCTimerReset(unsigned long ulBase)
{
//
// Reset the timer
//
HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 24);
}
//*****************************************************************************
//
//! Enables ADC internal timer
//!
//! \param ulBase is the base address of the ADC
//!
//! This function enables 17-bit ADC internal timer
//!
//! \returns None.
//
//*****************************************************************************
void ADCTimerEnable(unsigned long ulBase)
{
//
// Enable the timer
//
HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 25);
}
//*****************************************************************************
//
//! Disables ADC internal timer
//!
//! \param ulBase is the base address of the ADC
//!
//! This function disables 17-bit ADC internal timer
//!
//! \returns None.
//
//*****************************************************************************
void ADCTimerDisable(unsigned long ulBase)
{
//
// Disable the timer
//
HWREG(ulBase + ADC_O_adc_timer_configuration) &= ~(1 << 25);
}
//*****************************************************************************
//
//! Gets the current value of ADC internal timer
//!
//! \param ulBase is the base address of the ADC
//!
//! This function the current value of 17-bit ADC internal timer
//!
//! \returns Return the current value of ADC internal timer.
//
//*****************************************************************************
unsigned long ADCTimerValueGet(unsigned long ulBase)
{
return(HWREG(ulBase + ADC_O_adc_timer_current_count));
}
//*****************************************************************************
//
//! Gets the current FIFO level for specified ADC channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels.
//!
//! This function returns the current FIFO level for specified ADC channel.
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! \returns Return the current FIFO level for specified channel
//
//*****************************************************************************
unsigned char ADCFIFOLvlGet(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulOffset;
//
// Get the fifo level register offset for specified channel
//
ulOffset = ADC_O_adc_ch0_fifo_lvl + ulChannel;
//
// Return FIFO level
//
return(HWREG(ulBase + ulOffset) & 0x7);
}
//*****************************************************************************
//
//! Reads FIFO for specified ADC channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels.
//!
//! This function returns one data sample from the channel fifo as specified by
//! \e ulChannel parameter.
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! \returns Return one data sample from the channel fifo.
//
//*****************************************************************************
unsigned long ADCFIFORead(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulOffset;
//
// Get the fifo register offset for specified channel
//
ulOffset = ADC_O_channel0FIFODATA + ulChannel;
//
// Return FIFO level
//
return(HWREG(ulBase + ulOffset));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

118
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/adc.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// adc.h
//
// Defines and Macros for the ADC.
//
//*****************************************************************************
#ifndef __ADC_H__
#define __ADC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// Values that can be passed to APIs as ulChannel parameter
//*****************************************************************************
#define ADC_CH_0 0x00000000
#define ADC_CH_1 0x00000008
#define ADC_CH_2 0x00000010
#define ADC_CH_3 0x00000018
//*****************************************************************************
//
// Values that can be passed to ADCIntEnable(), ADCIntDisable()
// and ADCIntClear() as ulIntFlags, and returned from ADCIntStatus()
//
//*****************************************************************************
#define ADC_DMA_DONE 0x00000010
#define ADC_FIFO_OVERFLOW 0x00000008
#define ADC_FIFO_UNDERFLOW 0x00000004
#define ADC_FIFO_EMPTY 0x00000002
#define ADC_FIFO_FULL 0x00000001
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void ADCEnable(unsigned long ulBase);
extern void ADCDisable(unsigned long ulBase);
extern void ADCChannelEnable(unsigned long ulBase,unsigned long ulChannel);
extern void ADCChannelDisable(unsigned long ulBase,unsigned long ulChannel);
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel,
void (*pfnHandler)(void));
extern void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel);
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags);
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags);
extern unsigned long ADCIntStatus(unsigned long ulBase,unsigned long ulChannel);
extern void ADCIntClear(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags);
extern void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel);
extern void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel);
extern void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue);
extern void ADCTimerEnable(unsigned long ulBase);
extern void ADCTimerDisable(unsigned long ulBase);
extern void ADCTimerReset(unsigned long ulBase);
extern unsigned long ADCTimerValueGet(unsigned long ulBase);
extern unsigned char ADCFIFOLvlGet(unsigned long ulBase,
unsigned long ulChannel);
extern unsigned long ADCFIFORead(unsigned long ulBase,
unsigned long ulChannel);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __ADC_H__

603
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/camera.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// camera.c
//
// Driver for the camera controller module
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup camera_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_camera.h"
#include "inc/hw_apps_config.h"
#include "interrupt.h"
#include "camera.h"
//******************************************************************************
//
//! Resets the Camera core
//!
//! \param ulBase is the base address of the camera module.
//!
//! This function resets the camera core
//!
//! \return None.
//
//******************************************************************************
void CameraReset(unsigned long ulBase)
{
//
// Reset the camera
//
HWREG(ulBase + CAMERA_O_CC_SYSCONFIG) = CAMERA_CC_SYSCONFIG_SOFT_RESET;
//
// Wait for reset completion
//
while(!(HWREG(ulBase + CAMERA_O_CC_SYSSTATUS)&
CAMERA_CC_SYSSTATUS_RESET_DONE2))
{
}
}
//******************************************************************************
//
//! Configures camera parameters
//!
//! \param ulBase is the base address of the camera module.
//! \param ulHSPol sets the HSync polarity
//! \param ulVSPol sets the VSync polarity
//! \param ulFlags are configuration flags
//!
//! This function sets different camera parameters.
//!
//! The parameter \e ulHSPol should be on the follwoing:
//! - \b CAM_HS_POL_HI
//! - \b CAM_HS_POL_LO
//!
//! The parameter \e ulVSPol should be on the follwoing:
//! - \b CAM_VS_POL_HI
//! - \b CAM_VS_POL_LO
//!
//! The parameter \e ulFlags can be logical OR of one or more of the follwoing
//! or 0:
//! - \b CAM_PCLK_RISE_EDGE
//! - \b CAM_PCLK_FALL_EDGE
//! - \b CAM_ORDERCAM_SWAP
//! - \b CAM_NOBT_SYNCHRO
//! - \b CAM_IF_SYNCHRO
//!
//! \return None.
//
//******************************************************************************
void CameraParamsConfig(unsigned long ulBase, unsigned long ulHSPol,
unsigned long ulVSPol, unsigned long ulFlags)
{
unsigned long ulReg;
//
// Read the register
//
ulReg = HWREG(ulBase + CAMERA_O_CC_CTRL);
//
// Set the requested parameter
//
ulFlags = (ulFlags|ulHSPol|ulVSPol);
ulReg = ((ulReg & ~(CAMERA_CC_CTRL_NOBT_SYNCHRO |
CAMERA_CC_CTRL_NOBT_HS_POL |
CAMERA_CC_CTRL_NOBT_VS_POL |
CAMERA_CC_CTRL_BT_CORRECT |
CAMERA_CC_CTRL_PAR_ORDERCAM |
CAMERA_CC_CTRL_PAR_CLK_POL )) | ulFlags);
//
// Write the configuration
//
HWREG(ulBase + CAMERA_O_CC_CTRL)=ulReg;
}
//******************************************************************************
//
//! Set the internal clock divider
//!
//! \param ulBase is the base address of the camera module.
//! \param ulCamClkIn is input to camera module
//! \param ulXClk defines the output required
//!
//! This function sets the internal clock divider based on \e ulCamClkIn to
//! generate XCLK as specified be \e ulXClk. Maximum suppoter division is 30
//!
//! \return None.
//
//******************************************************************************
void CameraXClkConfig(unsigned long ulBase, unsigned long ulCamClkIn,
unsigned long ulXClk)
{
unsigned long ulReg;
unsigned long ucDiv;
//
// Read the register
//
ulReg = HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK);
//
// Mask XCLK divider value
//
ulReg &= ~(CAMERA_CC_CTRL_XCLK_XCLK_DIV_M);
//
// Compute the divider
//
ucDiv = ((ulCamClkIn)/ulXClk);
//
// Max supported division is 30
//
if(ucDiv > 30)
{
return;
}
//
// Set and write back the configuration
//
ulReg |= ucDiv;
HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) = ulReg;
}
//******************************************************************************
//
//! Sets the internal divide in specified mode
//!
//! \param ulBase is the base address of the camera module.
//! \param bXClkFlags decides the divide mode
//!
//! This function sets the internal divide in specified mode.
//!
//! The parameter \e bXClkFlags should be one of the following :
//!
//! - \b CAM_XCLK_STABLE_LO
//! - \b CAM_XCLK_STABLE_HI
//! - \b CAM_XCLK_DIV_BYPASS
//!
//! \return None.
//
//******************************************************************************
void CameraXClkSet(unsigned long ulBase, unsigned char bXClkFlags)
{
unsigned long ulReg;
//
// Read and Mask XTAL Divider config.
//
ulReg = (HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) &
~(CAMERA_CC_CTRL_XCLK_XCLK_DIV_M));
//
// Set config. base on parameter flag
//
switch(bXClkFlags)
{
case CAM_XCLK_STABLE_HI : ulReg |= 0x00000001;
break;
case CAM_XCLK_DIV_BYPASS: ulReg |= 0x0000001F;
break;
}
//
// Write the config.
//
HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) = ulReg;
}
//******************************************************************************
//
//! Enable camera DMA
//!
//! \param ulBase is the base address of the camera module.
//!
//! This function enables transfer request to DMA from camera. DMA specific
//! configuration has to be done seperately.
//!
//! \return None.
//
//******************************************************************************
void CameraDMAEnable(unsigned long ulBase)
{
//
// Enable DMA
//
HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) |= CAMERA_CC_CTRL_DMA_DMA_EN;
}
//******************************************************************************
//
//! Disable camera DMA
//!
//! \param ulBase is the base address of the camera module.
//!
//! This function masks transfer request to DMA from camera.
//!
//! \return None.
//
//******************************************************************************
void CameraDMADisable(unsigned long ulBase)
{
//
// Disable DMA
//
HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) &= ~CAMERA_CC_CTRL_DMA_DMA_EN;
}
//******************************************************************************
//
//! Sets the FIFO threshold for DMA transfer request
//!
//! \param ulBase is the base address of the camera module.
//! \param ulThreshold specifies the FIFO threshold
//!
//! This function sets the FIFO threshold for DMA transfer request.
//! Parameter \e ulThreshold can range from 1 - 64
//!
//! \return None.
//
//******************************************************************************
void CameraThresholdSet(unsigned long ulBase, unsigned long ulThreshold)
{
//
// Read and Mask DMA threshold field
//
HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) &= ~CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M;
//
// Write the new threshold value
//
HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) |= (ulThreshold -1);
}
//******************************************************************************
//
//! Register camera interrupt handler
//!
//! \param ulBase is the base address of the camera module.
//! \param pfnHandler hold pointer to interrupt handler
//!
//! This function registers and enables global camera interrupt from the
//! interrupt controller. Individual camera interrupts source
//! should be enabled using \sa CameraIntEnable().
//!
//! \return None.
//
//******************************************************************************
void CameraIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Register the interrupt handler.
//
IntRegister(INT_CAMERA, pfnHandler);
//
// Enable the Camera interrupt.
//
IntEnable(INT_CAMERA);
}
//******************************************************************************
//
//! Un-Register camera interrupt handler
//!
//! \param ulBase is the base address of the camera module.
//!
//! This function unregisters and disables global camera interrupt from the
//! interrupt controller.
//!
//! \return None.
//
//******************************************************************************
void CameraIntUnregister(unsigned long ulBase)
{
//
// Disable the interrupt.
//
IntDisable(INT_CAMERA);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_CAMERA);
}
//******************************************************************************
//! Enables individual camera interrupt sources.
//!
//! \param ulBase is the base address of the camera module.
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! This function enables individual camera interrupt sources.
//!
//! the parameter \e ulIntFlags should be logical OR of one or more of the
//! following:
//!
//! - \b CAM_INT_DMA
//! - \b CAM_INT_FE
//! - \b CAM_INT_FSC_ERR
//! - \b CAM_INT_FIFO_NOEMPTY
//! - \b CAM_INT_FIFO_FULL
//! - \b CAM_INT_FIFO_THR
//! - \b CAM_INT_FIFO_OF
//! - \b CAN_INT_FIFO_UR
//!
//! \return None.
//
//******************************************************************************
void CameraIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// unmask Camera DMA done interrupt
//
if(ulIntFlags & CAM_INT_DMA)
{
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ((1<<8));
}
//
// Enable specific camera interrupts
//
HWREG(ulBase + CAMERA_O_CC_IRQENABLE) |= ulIntFlags;
}
//******************************************************************************
//! Disables individual camera interrupt sources.
//!
//! \param ulBase is the base address of the camera module.
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
//!
//! This function disables individual camera interrupt sources.
//!
//! The parameter \e ulIntFlags should be logical OR of one or more of the
//! values as defined in CameraIntEnable().
//!
//! \return None.
//
//******************************************************************************
void CameraIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Mask Camera DMA done interrupt
//
if(ulIntFlags & CAM_INT_DMA)
{
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ((1<<8));
}
//
// Disable specific camera interrupts
//
HWREG(ulBase + CAMERA_O_CC_IRQENABLE) &= ~ulIntFlags;
}
//******************************************************************************
//
//! Returns the current interrupt status,
//!
//! \param ulBase is the base address of the camera module.
//! \param ulBase is the base address of the camera module.
//!
//! This functions returns the current interrupt status for the camera.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! values described in CameraIntEnable().
//******************************************************************************
unsigned long CameraIntStatus(unsigned long ulBase)
{
unsigned ulIntFlag;
//
// Read camera interrupt
//
ulIntFlag = HWREG(ulBase + CAMERA_O_CC_IRQSTATUS);
//
//
// Read camera DMA doner interrupt
//
if(HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED) & (1<<8))
{
ulIntFlag |= CAM_INT_DMA;
}
//
// Return status
//
return(ulIntFlag);
}
//******************************************************************************
//! Clears individual camera interrupt sources.
//!
//! \param ulBase is the base address of the camera module.
//! \param ulIntFlags is the bit mask of the interrupt sources to be Clears.
//!
//! This function Clears individual camera interrupt sources.
//!
//! The parameter \e ulIntFlags should be logical OR of one or more of the
//! values as defined in CameraIntEnable().
//!
//! \return None.
//
//******************************************************************************
void CameraIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Clear DMA done int status
//
if(ulIntFlags & CAM_INT_DMA)
{
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ((1<<8));
}
//
// Clear the interrupts
//
HWREG(ulBase + CAMERA_O_CC_IRQSTATUS) = ulIntFlags;
}
//******************************************************************************
//
//! Starts image capture
//!
//! \param ulBase is the base address of the camera module.
//!
//! This function starts the image capture over the configured camera interface
//! This function should be called after configuring the camera module
//! completele
//!
//! \return None.
//
//******************************************************************************
void CameraCaptureStart(unsigned long ulBase)
{
//
// Set the mode
//
HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~0xF;
//
// Enable image capture
//
HWREG(ulBase + CAMERA_O_CC_CTRL) |= CAMERA_CC_CTRL_CC_EN;
}
//******************************************************************************
//
//! Stops image capture
//!
//! \param ulBase is the base address of the camera module.
//! \param bImmediate is \b true to stop capture imeediately else \b flase.
//!
//! This function stops the image capture over the camera interface.
//! The capture is stopped either immediatelt or at the end of current frame
//! based on \e bImmediate parameter.
//!
//! \return None.
//
//******************************************************************************
void CameraCaptureStop(unsigned long ulBase, tBoolean bImmediate)
{
if(bImmediate)
{
//
// Stop capture immediately
//
HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~CAMERA_CC_CTRL_CC_FRAME_TRIG;
}
else
{
//
// Stop capture at the end of frame
//
HWREG(ulBase + CAMERA_O_CC_CTRL) |= CAMERA_CC_CTRL_CC_FRAME_TRIG;
}
//
// Request camera to stop capture
//
HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~CAMERA_CC_CTRL_CC_EN;
}
//******************************************************************************
//
//! Reads the camera buffer (FIFO)
//!
//! \param ulBase is the base address of the camera module.
//! \param pBuffer is the pointer to the read buffer
//! \param ucSize specifies the size to data to be read
//!
//! This function reads the camera buffer (FIFO).
//!
//! \return None.
//
//******************************************************************************
void CameraBufferRead(unsigned long ulBase, unsigned long *pBuffer,
unsigned char ucSize)
{
unsigned char *pCamBuff;
unsigned char i;
//
// Initilize a pointer to ecamera buffer
//
pCamBuff = (unsigned char *)CAM_BUFFER_ADDR;
//
// Read out requested data
//
for(i=0; i < ucSize; i++)
{
*(pBuffer+i) = *(pCamBuff + i);
}
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

132
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// camera.h
//
// Prototypes and macros for the camera controller module.
//
//*****************************************************************************
#ifndef __CAMERA_H__
#define __CAMERA_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// Macro defining Camera buffer address
//*****************************************************************************
#define CAM_BUFFER_ADDR 0x44018100
//*****************************************************************************
// Value that can be passed to CameraXClkSet().
//*****************************************************************************
#define CAM_XCLK_STABLE_LO 0x00
#define CAM_XCLK_STABLE_HI 0x01
#define CAM_XCLK_DIV_BYPASS 0x02
//*****************************************************************************
// Value that can be passed to CameraIntEnable(), CameraIntDisable,
// CameraIntClear() or returned from CameraIntStatus().
//*****************************************************************************
#define CAM_INT_DMA 0x80000000
#define CAM_INT_FE 0x00010000
#define CAM_INT_FIFO_NOEMPTY 0x00000010
#define CAM_INT_FIFO_FULL 0x00000008
#define CAM_INT_FIFO_THR 0x00000004
#define CAM_INT_FIFO_OF 0x00000002
#define CAN_INT_FIFO_UR 0x00000001
//*****************************************************************************
// Value that can be passed to CameraXClkConfig().
//*****************************************************************************
#define CAM_HS_POL_HI 0x00000000
#define CAM_HS_POL_LO 0x00000200
#define CAM_VS_POL_HI 0x00000000
#define CAM_VS_POL_LO 0x00000100
#define CAM_PCLK_RISE_EDGE 0x00000000
#define CAM_PCLK_FALL_EDGE 0x00000400
#define CAM_ORDERCAM_SWAP 0x00000800
#define CAM_NOBT_SYNCHRO 0x00002000
#define CAM_IF_SYNCHRO 0x00080000
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void CameraReset(unsigned long ulBase);
extern void CameraParamsConfig(unsigned long ulBase, unsigned long ulHSPol,
unsigned long ulVSPol, unsigned long ulFlags);
extern void CameraXClkConfig(unsigned long ulBase, unsigned long ulCamClkIn,
unsigned long ulXClk);
extern void CameraXClkSet(unsigned long ulBase, unsigned char bXClkFlags);
extern void CameraDMAEnable(unsigned long ulBase);
extern void CameraDMADisable(unsigned long ulBase);
extern void CameraThresholdSet(unsigned long ulBase, unsigned long ulThreshold);
extern void CameraIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void CameraIntUnregister(unsigned long ulBase);
extern void CameraIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void CameraIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long CameraIntStatus(unsigned long ulBase);
extern void CameraIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void CameraCaptureStop(unsigned long ulBase, tBoolean bImmediate);
extern void CameraCaptureStart(unsigned long ulBase);
extern void CameraBufferRead(unsigned long ulBase,unsigned long *pBuffer,
unsigned char ucSize);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif //__CAMERA_H__

356
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// cpu.c
//
// Instruction wrappers for special CPU instructions needed by the
//
//
//*****************************************************************************
#include "cpu.h"
//*****************************************************************************
//
// Wrapper function for the CPSID instruction. Returns the state of PRIMASK
// on entry.
//
//*****************************************************************************
#if defined(gcc)
unsigned long __attribute__((naked))
CPUcpsid(void)
{
unsigned long ulRet;
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" dsb \n"
" isb \n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUcpsid(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" dsb \n"
" isb \n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(arm_cc)
unsigned long
CPUcpsid(void)
{
// TODO: Implement it!
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function returning the state of PRIMASK (indicating whether
// interrupts are enabled or disabled).
//
//*****************************************************************************
#if defined(gcc)
unsigned long __attribute__((naked))
CPUprimask(void)
{
unsigned long ulRet;
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUprimask(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(arm_cc)
unsigned long
CPUprimask(void)
{
// TODO: Implement it!
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK
// on entry.
//
//*****************************************************************************
#if defined(gcc)
unsigned long __attribute__((naked))
CPUcpsie(void)
{
unsigned long ulRet;
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" dsb \n"
" isb \n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUcpsie(void)
{
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" dsb \n"
" isb \n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(arm_cc)
unsigned long
CPUcpsie(void)
{
// TODO: Implement it!
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function for the WFI instruction.
//
//*****************************************************************************
#if defined(gcc)
void __attribute__((naked))
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" dsb \n"
" isb \n"
" wfi \n"
" bx lr\n");
}
#endif
#if defined(ewarm)
void
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" dsb \n"
" isb \n"
" wfi \n");
}
#endif
#if defined(arm_cc)
void
CPUwfi(void)
{
// TODO: Implement it!
}
#endif
//*****************************************************************************
//
// Wrapper function for writing the BASEPRI register.
//
//*****************************************************************************
#if defined(gcc)
void __attribute__((naked))
CPUbasepriSet(unsigned long ulNewBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n"
" dsb \n"
" isb \n"
" bx lr\n");
}
#endif
#if defined(ewarm)
void
CPUbasepriSet(unsigned long ulNewBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n"
" dsb \n"
" isb \n");
}
#endif
#if defined(arm_cc)
void
CPUbasepriSet(unsigned long ulNewBasepri)
{
//
// Set the BASEPRI register
//
// TODO: Implement it!
}
#endif
//*****************************************************************************
//
// Wrapper function for reading the BASEPRI register.
//
//*****************************************************************************
#if defined(gcc)
unsigned long __attribute__((naked))
CPUbasepriGet(void)
{
unsigned long ulRet;
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUbasepriGet(void)
{
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(arm_cc)
unsigned long
CPUbasepriGet(void)
{
//
// Read BASEPRI
//
// TODO: Implement it
return(0);
}
#endif

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// cpu.h
//
// Prototypes for the CPU instruction wrapper functions.
//
//*****************************************************************************
#ifndef __CPU_H__
#define __CPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
// TODO, move this to tools
#ifdef TOOLCHAIN_GCC_ARM
#define gcc
#elif TOOLCHAIN_ARM
#define arm_cc
#elif defined TOOLCHAIN_IAR
#define ewarm
#endif
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern unsigned long CPUcpsid(void);
extern unsigned long CPUcpsie(void);
extern unsigned long CPUprimask(void);
extern void CPUwfi(void);
extern unsigned long CPUbasepriGet(void);
extern void CPUbasepriSet(unsigned long ulNewBasepri);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __CPU_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// crc.c
//
// Driver for the CRC module.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup CRC_Cyclic_Redundancy_Check_api
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_dthe.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/crc.h"
#include "driverlib/debug.h"
//*****************************************************************************
//
//! Set the configuration of CRC functionality with the EC module.
//!
//! \param ui32Base is the base address of the EC module.
//! \param ui32CRCConfig is the configuration of the CRC engine.
//!
//! This function configures the operation of the CRC engine within the EC
//! module. The configuration is specified with the \e ui32CRCConfig argument.
//! It is the logical OR of any of the following options:
//!
//! CRC Initialization Value
//! - \b EC_CRC_CFG_INIT_SEED - Initialize with seed value
//! - \b EC_CRC_CFG_INIT_0 - Initialize to all '0s'
//! - \b EC_CRC_CFG_INIT_1 - Initialize to all '1s'
//!
//! Input Data Size
//! - \b EC_CRC_CFG_SIZE_8BIT - Input data size of 8 bits
//! - \b EC_CRC_CFG_SIZE_32BIT - Input data size of 32 bits
//!
//! Post Process Reverse/Inverse
//! - \b EC_CRC_CFG_RESINV - Result inverse enable
//! - \b EC_CRC_CFG_OBR - Output reverse enable
//!
//! Input Bit Reverse
//! - \b EC_CRC_CFG_IBR - Bit reverse enable
//!
//! Endian Control
//! - \b EC_CRC_CFG_ENDIAN_SBHW - Swap byte in half-word
//! - \b EC_CRC_CFG_ENDIAN_SHW - Swap half-word
//!
//! Operation Type
//! - \b EC_CRC_CFG_TYPE_P8005 - Polynomial 0x8005
//! - \b EC_CRC_CFG_TYPE_P1021 - Polynomial 0x1021
//! - \b EC_CRC_CFG_TYPE_P4C11DB7 - Polynomial 0x4C11DB7
//! - \b EC_CRC_CFG_TYPE_P1EDC6F41 - Polynomial 0x1EDC6F41
//! - \b EC_CRC_CFG_TYPE_TCPCHKSUM - TCP checksum
//!
//! \return None.
//
//*****************************************************************************
void
CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DTHE_BASE);
ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) ||
(ui32CRCConfig & CRC_CFG_INIT_0) ||
(ui32CRCConfig & CRC_CFG_INIT_1) ||
(ui32CRCConfig & CRC_CFG_SIZE_8BIT) ||
(ui32CRCConfig & CRC_CFG_SIZE_32BIT) ||
(ui32CRCConfig & CRC_CFG_RESINV) ||
(ui32CRCConfig & CRC_CFG_OBR) ||
(ui32CRCConfig & CRC_CFG_IBR) ||
(ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) ||
(ui32CRCConfig & CRC_CFG_ENDIAN_SHW) ||
(ui32CRCConfig & CRC_CFG_TYPE_P8005) ||
(ui32CRCConfig & CRC_CFG_TYPE_P1021) ||
(ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) ||
(ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) ||
(ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM));
//
// Write the control register with the configuration.
//
HWREG(ui32Base + DTHE_O_CRC_CTRL) = ui32CRCConfig;
}
//*****************************************************************************
//
//! Write the seed value for CRC operations in the EC module.
//!
//! \param ui32Base is the base address of the EC module.
//! \param ui32Seed is the seed value.
//!
//! This function writes the seed value for use with CRC operations in the
//! EC module. This value is the start value for CRC operations. If this
//! value is not written, then the residual seed from the previous operation
//! is used as the starting value.
//!
//! \note The seed must be written only if \b EC_CRC_CFG_INIT_SEED is
//! set with the CRCConfigSet() function.
//
//*****************************************************************************
void
CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DTHE_BASE);
//
// Write the seed value to the seed register.
//
HWREG(ui32Base + DTHE_O_CRC_SEED) = ui32Seed;
}
//*****************************************************************************
//
//! Write data into the EC module for CRC operations.
//!
//! \param ui32Base is the base address of the EC module.
//! \param ui32Data is the data to be written.
//!
//! This function writes either 8 or 32 bits of data into the EC module for
//! CRC operations. The distinction between 8 and 32 bits of data is made
//! when the \b EC_CRC_CFG_SIZE_8BIT or \b EC_CRC_CFG_SIZE_32BIT flag
//! is set using the CRCConfigSet() function.
//!
//! When writing 8 bits of data, ensure the data is in the least signficant
//! byte position. The remaining bytes should be written with zero. For
//! example, when writing 0xAB, \e ui32Data should be 0x000000AB.
//!
//! \return None
//
//*****************************************************************************
void
CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DTHE_BASE);
//
// Write the data
//
HWREG(DTHE_BASE + DTHE_O_CRC_DIN) = ui32Data;
}
//*****************************************************************************
//
//! Reads the result of a CRC operation in the EC module.
//!
//! \param ui32Base is the base address of the EC module.
//!
//! This function reads either the unmodified CRC result or the post
//! processed CRC result from the EC module. The post-processing options
//! are selectable through \b EC_CRC_CFG_RESINV and \b EC_CRC_CFG_OBR
//! parameters in the CRCConfigSet() function.
//!
//! \return The CRC result.
//
//*****************************************************************************
uint32_t
CRCResultRead(uint32_t ui32Base)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DTHE_BASE);
//
// return value.
//
return(HWREG(DTHE_BASE + DTHE_O_CRC_RSLT_PP));
}
//*****************************************************************************
//
//! Process data to generate a CRC with the EC module.
//!
//! \param ui32Base is the base address of the EC module.
//! \param puiDataIn is a pointer to an array of data that is processed.
//! \param ui32DataLength is the number of data items that are processed
//! to produce the CRC.
//! \param ui32Config the config parameter to determine the CRC mode
//!
//! This function processes an array of data to produce a CRC result.
//! This function takes the CRC mode as the parameter.
//!
//! The data in the array pointed to be \e pui32DataIn is either an array
//! of bytes or an array or words depending on the selection of the input
//! data size options \b EC_CRC_CFG_SIZE_8BIT and
//! \b EC_CRC_CFG_SIZE_32BIT.
//!
//! This function returns either the unmodified CRC result or the
//! post- processed CRC result from the EC module. The post-processing
//! options are selectable through \b EC_CRC_CFG_RESINV and
//! \b EC_CRC_CFG_OBR parameters.
//!
//! \return The CRC result.
//
//*****************************************************************************
uint32_t
CRCDataProcess(uint32_t ui32Base, void *puiDataIn,
uint32_t ui32DataLength, uint32_t ui32Config)
{
uint8_t *pui8DataIn;
uint32_t *pui32DataIn;
//
// Check the arguments.
//
ASSERT(ui32Base == DTHE_BASE);
//
// See if the CRC is operating in 8-bit or 32-bit mode.
//
if(ui32Config & DTHE_CRC_CTRL_SIZE)
{
//
// The CRC is operating in 8-bit mode, so create an 8-bit pointer to
// the data.
//
pui8DataIn = (uint8_t *)puiDataIn;
//
// Loop through the input data.
//
while(ui32DataLength--)
{
//
// Write the next data byte.
//
HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui8DataIn++;
}
}
else
{
//
// The CRC is operating in 32-bit mode, so loop through the input data.
//
pui32DataIn = (uint32_t *)puiDataIn;
while(ui32DataLength--)
{
//
// Write the next data word.
//
HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui32DataIn++;
}
}
//
// Return the result.
//
return(CRCResultRead(ui32Base));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// crc.h
//
// Defines and Macros for CRC module.
//
//*****************************************************************************
#ifndef __DRIVERLIB_CRC_H__
#define __DRIVERLIB_CRC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used in the ui32Config argument of the
// ECConfig function.
//
//*****************************************************************************
#define CRC_CFG_INIT_SEED 0x00000000 // Initialize with seed
#define CRC_CFG_INIT_0 0x00004000 // Initialize to all '0s'
#define CRC_CFG_INIT_1 0x00006000 // Initialize to all '1s'
#define CRC_CFG_SIZE_8BIT 0x00001000 // Input Data Size
#define CRC_CFG_SIZE_32BIT 0x00000000 // Input Data Size
#define CRC_CFG_RESINV 0x00000200 // Result Inverse Enable
#define CRC_CFG_OBR 0x00000100 // Output Reverse Enable
#define CRC_CFG_IBR 0x00000080 // Bit reverse enable
#define CRC_CFG_ENDIAN_SBHW 0x00000000 // Swap byte in half-word
#define CRC_CFG_ENDIAN_SHW 0x00000010 // Swap half-word
#define CRC_CFG_TYPE_P8005 0x00000000 // Polynomial 0x8005
#define CRC_CFG_TYPE_P1021 0x00000001 // Polynomial 0x1021
#define CRC_CFG_TYPE_P4C11DB7 0x00000002 // Polynomial 0x4C11DB7
#define CRC_CFG_TYPE_P1EDC6F41 0x00000003 // Polynomial 0x1EDC6F41
#define CRC_CFG_TYPE_TCPCHKSUM 0x00000008 // TCP checksum
//*****************************************************************************
//
// Function prototypes.
//
//*****************************************************************************
extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig);
extern uint32_t CRCDataProcess(uint32_t ui32Base, void *puiDataIn,
uint32_t ui32DataLength, uint32_t ui32Config);
extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data);
extern uint32_t CRCResultRead(uint32_t ui32Base);
extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_CRC_H__

68
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/debug.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// debug.h
//
// Macros for assisting debug of the driver library.
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, unsigned long ulLine);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
#else
#define ASSERT(expr)
#endif
#endif // __DEBUG_H__

864
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/flash.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// flash.c
//
// Driver for programming the on-chip flash.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup flash_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_flash_ctrl.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ints.h"
#include "inc/hw_gprcm.h"
#include "inc/hw_hib1p2.h"
#include "inc/hw_hib3p3.h"
#include "inc/hw_common_reg.h"
#include "inc/hw_stack_die_ctrl.h"
#include "debug.h"
#include "flash.h"
#include "utils.h"
#include "interrupt.h"
#define HAVE_WRITE_BUFFER 1
//*****************************************************************************
//
// An array that maps the specified memory bank to the appropriate Flash
// Memory Protection Program Enable (FMPPE) register.
//
//*****************************************************************************
static const unsigned long g_pulFMPPERegs[] =
{
FLASH_FMPPE0,
FLASH_FMPPE1,
FLASH_FMPPE2,
FLASH_FMPPE3,
FLASH_FMPPE4,
FLASH_FMPPE5,
FLASH_FMPPE6,
FLASH_FMPPE7,
FLASH_FMPPE8,
FLASH_FMPPE9,
FLASH_FMPPE10,
FLASH_FMPPE11,
FLASH_FMPPE12,
FLASH_FMPPE13,
FLASH_FMPPE14,
FLASH_FMPPE15
};
//*****************************************************************************
//
// An array that maps the specified memory bank to the appropriate Flash
// Memory Protection Read Enable (FMPRE) register.
//
//*****************************************************************************
static const unsigned long g_pulFMPRERegs[] =
{
FLASH_FMPRE0,
FLASH_FMPRE1,
FLASH_FMPRE2,
FLASH_FMPRE3,
FLASH_FMPRE4,
FLASH_FMPRE5,
FLASH_FMPRE6,
FLASH_FMPRE7,
FLASH_FMPRE8,
FLASH_FMPRE9,
FLASH_FMPRE10,
FLASH_FMPRE11,
FLASH_FMPRE12,
FLASH_FMPRE13,
FLASH_FMPRE14,
FLASH_FMPRE15,
};
//*****************************************************************************
//
//! Flash Disable
//!
//! This function Disables the internal Flash.
//!
//! \return None.
//
//*****************************************************************************
void
FlashDisable()
{
//
// Wait for Flash Busy to get cleared
//
while((HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE)
& GPRCM_TOP_DIE_ENABLE_FLASH_BUSY))
{
}
//
// Assert reset
//
HWREG(HIB1P2_BASE + HIB1P2_O_PORPOL_SPARE) = 0xFFFF0000;
//
// 50 usec Delay Loop
//
UtilsDelay((50*80)/3);
//
// Disable TDFlash
//
HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) = 0x0;
//
// 50 usec Delay Loop
//
UtilsDelay((50*80)/3);
HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1;
//
// 50 usec Delay Loop
//
UtilsDelay((50*80)/3);
}
//*****************************************************************************
//
//! Erases a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be erased.
//!
//! This function will erase a 2 kB block of the on-chip flash. After erasing,
//! the block will be filled with 0xFF bytes. Read-only and execute-only
//! blocks cannot be erased.
//!
//! This function will not return until the block has been erased.
//!
//! \return Returns 0 on success, or -1 if an invalid block address was
//! specified or the block is write-protected.
//
//*****************************************************************************
long
FlashErase(unsigned long ulAddress)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1)));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)
= (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_ERMISC);
// Erase the block.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC)
= FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE;
//
// Wait until the block has been erased.
//
while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_ERASE)
{
}
//
// Return an error if an access violation or erase error occurred.
//
if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS)
& (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS |
FLASH_CTRL_FCRIS_ERRIS))
{
return(-1);
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Erases a block of flash but does not wait for completion.
//!
//! \param ulAddress is the start address of the flash block to be erased.
//!
//! This function will erase a 2 kB block of the on-chip flash. After erasing,
//! the block will be filled with 0xFF bytes. Read-only and execute-only
//! blocks cannot be erased.
//!
//! This function will return immediately after commanding the erase operation.
//! Applications making use of the function can determine completion state by
//! using a flash interrupt handler or by polling FlashIntStatus.
//!
//! \return None.
//
//*****************************************************************************
void
FlashEraseNonBlocking(unsigned long ulAddress)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1)));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) =
(FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_ERMISC);
//
// Command the flash controller to erase the block.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE;
}
//*****************************************************************************
//
//! Erases a complele flash at shot.
//!
//! This function erases a complele flash at shot
//!
//! \return Returns 0 on success, or -1 if the block is write-protected.
//
//*****************************************************************************
long
FlashMassErase()
{
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) =
(FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_ERMISC);
//
// Command the flash controller for mass erase.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) =
FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1;
//
// Wait until mass erase completes.
//
while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_MERASE1)
{
}
//
// Return an error if an access violation or erase error occurred.
//
if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS)
& (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS |
FLASH_CTRL_FCRIS_ERRIS))
{
return -1;
}
//
// Success.
//
return 0;
}
//*****************************************************************************
//
//! Erases a complele flash at shot but does not wait for completion.
//!
//!
//! This function will not return until the Flash has been erased.
//!
//! \return None.
//
//*****************************************************************************
void
FlashMassEraseNonBlocking()
{
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) =
(FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_ERMISC);
//
// Command the flash controller for mass erase.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) =
FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1;
}
//*****************************************************************************
//
//! Programs flash.
//!
//! \param pulData is a pointer to the data to be programmed.
//! \param ulAddress is the starting address in flash to be programmed. Must
//! be a multiple of four.
//! \param ulCount is the number of bytes to be programmed. Must be a multiple
//! of four.
//!
//! This function will program a sequence of words into the on-chip flash.
//! Each word in a page of flash can only be programmed one time between an
//! erase of that page; programming a word multiple times will result in an
//! unpredictable value in that word of flash.
//!
//! Since the flash is programmed one word at a time, the starting address and
//! byte count must both be multiples of four. It is up to the caller to
//! verify the programmed contents, if such verification is required.
//!
//! This function will not return until the data has been programmed.
//!
//! \return Returns 0 on success, or -1 if a programming error is encountered.
//
//*****************************************************************************
long
FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & 3));
ASSERT(!(ulCount & 3));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)
= (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC);
//
// See if this device has a write buffer.
//
#if HAVE_WRITE_BUFFER
{
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Set the address of this block of words. for 1 MB
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F);
//
// Loop over the words in this 32-word block.
//
while(((ulAddress & 0x7C) ||
(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) &&
(ulCount != 0))
{
//
// Write this word into the write buffer.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN
+ (ulAddress & 0x7C)) = *pulData++;
ulAddress += 4;
ulCount -= 4;
}
//
// Program the contents of the write buffer into flash.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2)
= FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF;
//
// Wait until the write buffer has been programmed.
//
while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) & FLASH_CTRL_FMC2_WRBUF)
{
}
}
}
#else
{
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Program the next word.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE;
//
// Wait until the word has been programmed.
//
while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_WRITE)
{
}
//
// Increment to the next word.
//
pulData++;
ulAddress += 4;
ulCount -= 4;
}
}
#endif
//
// Return an error if an access violation occurred.
//
if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS |
FLASH_CTRL_FCRIS_INVDRIS | FLASH_CTRL_FCRIS_PROGRIS))
{
return(-1);
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Programs flash but does not poll for completion.
//!
//! \param pulData is a pointer to the data to be programmed.
//! \param ulAddress is the starting address in flash to be programmed. Must
//! be a multiple of four.
//! \param ulCount is the number of bytes to be programmed. Must be a multiple
//! of four.
//!
//! This function will start programming one or more words into the on-chip
//! flash and return immediately. The number of words that can be programmed
//! in a single call depends the part on which the function is running. For
//! parts without support for a flash write buffer, only a single word may be
//! programmed on each call to this function (\e ulCount must be 1). If a
//! write buffer is present, up to 32 words may be programmed on condition
//! that the block being programmed does not straddle a 32 word address
//! boundary. For example, wherease 32 words can be programmed if the address
//! passed is 0x100 (a multiple of 128 bytes or 32 words), only 31 words could
//! be programmed at 0x104 since attempting to write 32 would cross the 32
//! word boundary at 0x180.
//!
//! Since the flash is programmed one word at a time, the starting address and
//! byte count must both be multiples of four. It is up to the caller to
//! verify the programmed contents, if such verification is required.
//!
//! This function will return immediately after commanding the erase operation.
//! Applications making use of the function can determine completion state by
//! using a flash interrupt handler or by polling FlashIntStatus.
//!
//! \return 0 if the write was started successfully, -1 if there was an error.
//
//*****************************************************************************
long
FlashProgramNonBlocking(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & 3));
ASSERT(!(ulCount & 3));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)
= (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC);
//
// See if this device has a write buffer.
//
#if HAVE_WRITE_BUFFER
{
//
// Make sure the address/count specified doesn't straddle a 32 word
// boundary.
//
if(((ulAddress + (ulCount - 1)) & ~0x7F) != (ulAddress & ~0x7F))
{
return(-1);
}
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Set the address of this block of words.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F);
//
// Loop over the words in this 32-word block.
//
while(((ulAddress & 0x7C) || (HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) &&
(ulCount != 0))
{
//
// Write this word into the write buffer.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN + (ulAddress & 0x7C)) = *pulData++;
ulAddress += 4;
ulCount -= 4;
}
//
// Program the contents of the write buffer into flash.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) = FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF;
}
}
#else
{
//
// We don't have a write buffer so we can only write a single word.
//
if(ulCount > 1)
{
return(-1);
}
//
// Write a single word.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE;
}
#endif
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Gets the protection setting for a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be queried.
//!
//! This function gets the current protection for the specified 2-kB block
//! of flash. Each block can be read/write, read-only, or execute-only.
//! Read/write blocks can be read, executed, erased, and programmed. Read-only
//! blocks can be read and executed. Execute-only blocks can only be executed;
//! processor and debugger data reads are not allowed.
//!
//! \return Returns the protection setting for this block. See
//! FlashProtectSet() for possible values.
//
//*****************************************************************************
tFlashProtection
FlashProtectGet(unsigned long ulAddress)
{
unsigned long ulFMPRE, ulFMPPE;
unsigned long ulBank;
//
// Check the argument.
//
ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
//
// Calculate the Flash Bank from Base Address, and mask off the Bank
// from ulAddress for subsequent reference.
//
ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 16);
ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1);
//
// Read the appropriate flash protection registers for the specified
// flash bank.
//
ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]);
ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]);
//
// Check the appropriate protection bits for the block of memory that
// is specified by the address.
//
switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) &
FLASH_FMP_BLOCK_0) << 1) |
((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0))
{
//
// This block is marked as execute only (that is, it can not be erased
// or programmed, and the only reads allowed are via the instruction
// fetch interface).
//
case 0:
case 1:
{
return(FlashExecuteOnly);
}
//
// This block is marked as read only (that is, it can not be erased or
// programmed).
//
case 2:
{
return(FlashReadOnly);
}
//
// This block is read/write; it can be read, erased, and programmed.
//
case 3:
default:
{
return(FlashReadWrite);
}
}
}
//*****************************************************************************
//
//! Registers an interrupt handler for the flash interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the flash
//! interrupt occurs.
//!
//! This sets the handler to be called when the flash interrupt occurs. The
//! flash controller can generate an interrupt when an invalid flash access
//! occurs, such as trying to program or erase a read-only block, or trying to
//! read from an execute-only block. It can also generate an interrupt when a
//! program or erase operation has completed. The interrupt will be
//! automatically enabled when the handler is registered.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(INT_FLASH, pfnHandler);
//
// Enable the flash interrupt.
//
IntEnable(INT_FLASH);
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for the flash interrupt.
//!
//! This function will clear the handler to be called when the flash interrupt
//! occurs. This will also mask off the interrupt in the interrupt controller
//! so that the interrupt handler is no longer called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntUnregister(void)
{
//
// Disable the interrupt.
//
IntDisable(INT_FLASH);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_FLASH);
}
//*****************************************************************************
//
//! Enables individual flash controller interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values.
//!
//! Enables the indicated flash controller interrupt sources. Only the sources
//! that are enabled can be reflected to the processor interrupt; disabled
//! sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntEnable(unsigned long ulIntFlags)
{
//
// Enable the specified interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables individual flash controller interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values.
//!
//! Disables the indicated flash controller interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntDisable(unsigned long ulIntFlags)
{
//
// Disable the specified interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the flash controller. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b FLASH_CTRL_PROGRAM and \b FLASH_CTRL_ACCESS.
//
//*****************************************************************************
unsigned long
FlashIntStatus(tBoolean bMasked)
{
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC));
}
else
{
return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS));
}
}
//*****************************************************************************
//
//! Clears flash controller interrupt sources.
//!
//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_AMISC values.
//!
//! The specified flash controller interrupt sources are cleared, so that they
//! no longer assert. This must be done in the interrupt handler to keep it
//! from being called again immediately upon exit.
//!
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntClear(unsigned long ulIntFlags)
{
//
// Clear the flash interrupt.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = ulIntFlags;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// flash.h
//
// Prototypes for the flash driver.
//
//*****************************************************************************
#ifndef __FLASH_H__
#define __FLASH_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FlashProtectSet(), and returned by
// FlashProtectGet().
//
//*****************************************************************************
typedef enum
{
FlashReadWrite, // Flash can be read and written
FlashReadOnly, // Flash can only be read
FlashExecuteOnly // Flash can only be executed
}
tFlashProtection;
//*****************************************************************************
//
// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and
// returned from FlashIntStatus().
//
//*****************************************************************************
#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask
#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask
#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask
#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask
#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask
#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask
#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void FlashDisable(void);
extern long FlashErase(unsigned long ulAddress);
extern void FlashEraseNonBlocking(unsigned long ulAddress);
extern long FlashMassErase(void);
extern void FlashMassEraseNonBlocking(void);
extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount);
extern long FlashProgramNonBlocking(unsigned long *pulData,
unsigned long ulAddress,
unsigned long ulCount);
extern void FlashIntRegister(void (*pfnHandler)(void));
extern void FlashIntUnregister(void);
extern void FlashIntEnable(unsigned long ulIntFlags);
extern void FlashIntDisable(unsigned long ulIntFlags);
extern unsigned long FlashIntStatus(tBoolean bMasked);
extern void FlashIntClear(unsigned long ulIntFlags);
extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __FLASH_H__

717
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// gpio.c
//
// Driver for the GPIO module.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup GPIO_General_Purpose_InputOutput_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_gpio.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_common_reg.h"
#include "debug.h"
#include "gpio.h"
#include "interrupt.h"
//*****************************************************************************
//
//! \internal
//! Checks a GPIO base address.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! This function determines if a GPIO port base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
#ifdef DEBUG
static tBoolean
GPIOBaseValid(unsigned long ulPort)
{
return((ulPort == GPIOA0_BASE) ||
(ulPort == GPIOA1_BASE) ||
(ulPort == GPIOA2_BASE) ||
(ulPort == GPIOA3_BASE) ||
(ulPort == GPIOA4_BASE));
}
#endif
//*****************************************************************************
//
//! \internal
//! Gets the GPIO interrupt number.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! Given a GPIO base address, returns the corresponding interrupt number.
//!
//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid.
//
//*****************************************************************************
long
GPIOGetIntNumber(unsigned long ulPort)
{
unsigned int ulInt;
//
// Determine the GPIO interrupt number for the given module.
//
switch(ulPort)
{
case GPIOA0_BASE:
{
ulInt = INT_GPIOA0;
break;
}
case GPIOA1_BASE:
{
ulInt = INT_GPIOA1;
break;
}
case GPIOA2_BASE:
{
ulInt = INT_GPIOA2;
break;
}
case GPIOA3_BASE:
{
ulInt = INT_GPIOA3;
break;
}
default:
{
return(-1);
}
}
//
// Return GPIO interrupt number.
//
return(ulInt);
}
//*****************************************************************************
//
//! Sets the direction and mode of the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port
//! \param ucPins is the bit-packed representation of the pin(s).
//! \param ulPinIO is the pin direction and/or mode.
//!
//! This function will set the specified pin(s) on the selected GPIO port
//! as either an input or output under software control, or it will set the
//! pin to be under hardware control.
//!
//! The parameter \e ulPinIO is an enumerated data type that can be one of
//! the following values:
//!
//! - \b GPIO_DIR_MODE_IN
//! - \b GPIO_DIR_MODE_OUT
//!
//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as
//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin
//! will be programmed as a software controlled output.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \note GPIOPadConfigSet() must also be used to configure the corresponding
//! pad(s) in order for them to propagate the signal to/from the GPIO.
//!
//! \return None.
//
//*****************************************************************************
void
GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT));
//
// Set the pin direction and mode.
//
HWREG(ulPort + GPIO_O_GPIO_DIR) = ((ulPinIO & 1) ?
(HWREG(ulPort + GPIO_O_GPIO_DIR) | ucPins) :
(HWREG(ulPort + GPIO_O_GPIO_DIR) & ~(ucPins)));
}
//*****************************************************************************
//
//! Gets the direction and mode of a pin.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPin is the pin number.
//!
//! This function gets the direction and control mode for a specified pin on
//! the selected GPIO port. The pin can be configured as either an input or
//! output under software control, or it can be under hardware control. The
//! type of control and direction are returned as an enumerated data type.
//!
//! \return Returns one of the enumerated data types described for
//! GPIODirModeSet().
//
//*****************************************************************************
unsigned long
GPIODirModeGet(unsigned long ulPort, unsigned char ucPin)
{
unsigned long ulDir;
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
ASSERT(ucPin < 8);
//
// Convert from a pin number to a bit position.
// Not needed because pin mask is pass in directly
//ucPin = 1 << ucPin;
//
// Return the pin direction and mode.
//
ulDir = HWREG(ulPort + GPIO_O_GPIO_DIR);
return(((ulDir & ucPin) ? 1 : 0));
}
//*****************************************************************************
//
//! Sets the interrupt type for the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPins is the bit-packed representation of the pin(s).
//! \param ulIntType specifies the type of interrupt trigger mechanism.
//!
//! This function sets up the various interrupt trigger mechanisms for the
//! specified pin(s) on the selected GPIO port.
//!
//! The parameter \e ulIntType is an enumerated data type that can be one of
//! the following values:
//!
//! - \b GPIO_FALLING_EDGE
//! - \b GPIO_RISING_EDGE
//! - \b GPIO_BOTH_EDGES
//! - \b GPIO_LOW_LEVEL
//! - \b GPIO_HIGH_LEVEL
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \note In order to avoid any spurious interrupts, the user must
//! ensure that the GPIO inputs remain stable for the duration of
//! this function.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
ASSERT((ulIntType == GPIO_FALLING_EDGE) ||
(ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) ||
(ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL));
//
// Set the pin interrupt type.
//
HWREG(ulPort + GPIO_O_GPIO_IBE) = ((ulIntType & 1) ?
(HWREG(ulPort + GPIO_O_GPIO_IBE) | ucPins) :
(HWREG(ulPort + GPIO_O_GPIO_IBE) & ~(ucPins)));
HWREG(ulPort + GPIO_O_GPIO_IS) = ((ulIntType & 2) ?
(HWREG(ulPort + GPIO_O_GPIO_IS) | ucPins) :
(HWREG(ulPort + GPIO_O_GPIO_IS) & ~(ucPins)));
HWREG(ulPort + GPIO_O_GPIO_IEV) = ((ulIntType & 4) ?
(HWREG(ulPort + GPIO_O_GPIO_IEV) | ucPins) :
(HWREG(ulPort + GPIO_O_GPIO_IEV) & ~(ucPins)));
}
//*****************************************************************************
//
//! Gets the interrupt type for a pin.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPin is the pin number.
//!
//! This function gets the interrupt type for a specified pin on the selected
//! GPIO port. The pin can be configured as a falling edge, rising edge, or
//! both edge detected interrupt, or it can be configured as a low level or
//! high level detected interrupt. The type of interrupt detection mechanism
//! is returned as an enumerated data type.
//!
//! \return Returns one of the enumerated data types described for
//! GPIOIntTypeSet().
//
//*****************************************************************************
unsigned long
GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin)
{
unsigned long ulIBE, ulIS, ulIEV;
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
ASSERT(ucPin < 8);
//
// Convert from a pin number to a bit position.
// Not needed because using the pin mask is pass in directly
//ucPin = 1 << ucPin;
//
// Return the pin interrupt type.
//
ulIBE = HWREG(ulPort + GPIO_O_GPIO_IBE);
ulIS = HWREG(ulPort + GPIO_O_GPIO_IS);
ulIEV = HWREG(ulPort + GPIO_O_GPIO_IEV);
return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) |
((ulIEV & ucPin) ? 4 : 0));
}
//*****************************************************************************
//
//! Enables the specified GPIO interrupts.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ulIntFlags is the bit mask of the interrupt sources to enable.
//!
//! This function enables the indicated GPIO interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done
//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Enable the interrupts.
//
HWREG(ulPort + GPIO_O_GPIO_IM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables the specified GPIO interrupts.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ulIntFlags is the bit mask of the interrupt sources to disable.
//!
//! This function disables the indicated GPIO interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done
//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Disable the interrupts.
//
HWREG(ulPort + GPIO_O_GPIO_IM) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets interrupt status for the specified GPIO port.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param bMasked specifies whether masked or raw interrupt status is
//! returned.
//!
//! If \e bMasked is set as \b true, then the masked interrupt status is
//! returned; otherwise, the raw interrupt status will be returned.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! values described in GPIOIntEnable().
//
//*****************************************************************************
long
GPIOIntStatus(unsigned long ulPort, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Return the interrupt status.
//
if(bMasked)
{
return(HWREG(ulPort + GPIO_O_GPIO_MIS));
}
else
{
return(HWREG(ulPort + GPIO_O_GPIO_RIS));
}
}
//*****************************************************************************
//
//! Clears the interrupt for the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! Clears the interrupt for the specified pin(s).
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to GPIOIntEnable().
//!
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Clear the interrupts.
//
HWREG(ulPort + GPIO_O_GPIO_ICR) = ulIntFlags;
}
//*****************************************************************************
//
//! Registers an interrupt handler for a GPIO port.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling
//! function.
//!
//! This function will ensure that the interrupt handler specified by
//! \e pfnIntHandler is called when an interrupt is detected from the selected
//! GPIO port. This function will also enable the corresponding GPIO interrupt
//! in the interrupt controller; individual pin interrupts and interrupt
//! sources must be enabled with GPIOIntEnable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void))
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Get the interrupt number associated with the specified GPIO.
//
ulPort = GPIOGetIntNumber(ulPort);
//
// Register the interrupt handler.
//
IntRegister(ulPort, pfnIntHandler);
//
// Enable the GPIO interrupt.
//
IntEnable(ulPort);
}
//*****************************************************************************
//
//! Removes an interrupt handler for a GPIO port.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! This function will unregister the interrupt handler for the specified
//! GPIO port. This function will also disable the corresponding
//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts
//! and interrupt sources must be disabled with GPIOIntDisable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntUnregister(unsigned long ulPort)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Get the interrupt number associated with the specified GPIO.
//
ulPort = GPIOGetIntNumber(ulPort);
//
// Disable the GPIO interrupt.
//
IntDisable(ulPort);
//
// Unregister the interrupt handler.
//
IntUnregister(ulPort);
}
//*****************************************************************************
//
//! Reads the values present of the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPins is the bit-packed representation of the pin(s).
//!
//! The values at the specified pin(s) are read, as specified by \e ucPins.
//! Values are returned for both input and output pin(s), and the value
//! for pin(s) that are not specified by \e ucPins are set to 0.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \return Returns a bit-packed byte providing the state of the specified
//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents
//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins
//! is returned as a 0. Bits 31:8 should be ignored.
//
//*****************************************************************************
long
GPIOPinRead(unsigned long ulPort, unsigned char ucPins)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Return the pin value(s).
//
return(HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))));
}
//*****************************************************************************
//
//! Writes a value to the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPins is the bit-packed representation of the pin(s).
//! \param ucVal is the value to write to the pin(s).
//!
//! Writes the corresponding bit values to the output pin(s) specified by
//! \e ucPins. Writing to a pin configured as an input pin has no effect.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Write the pins.
//
HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))) = ucVal;
}
//*****************************************************************************
//
//! Enables a GPIO port as a trigger to start a DMA transaction.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! This function enables a GPIO port to be used as a trigger to start a uDMA
//! transaction. The GPIO pin will still generate interrupts if the interrupt is
//! enabled for the selected pin.
//!
//! \return None.
//
//*****************************************************************************
void
GPIODMATriggerEnable(unsigned long ulPort)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Set the pin as a DMA trigger.
//
if(ulPort == GPIOA0_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x1;
}
else if(ulPort == GPIOA1_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x2;
}
else if(ulPort == GPIOA2_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x4;
}
else if(ulPort == GPIOA3_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x8;
}
}
//*****************************************************************************
//
//! Disables a GPIO port as a trigger to start a DMA transaction.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! This function disables a GPIO port to be used as a trigger to start a uDMA
//! transaction. This function can be used to disable this feature if it was
//! enabled via a call to GPIODMATriggerEnable().
//!
//! \return None.
//
//*****************************************************************************
void
GPIODMATriggerDisable(unsigned long ulPort)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Set the pin as a DMA trigger.
//
if(ulPort == GPIOA0_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x1;
}
else if(ulPort == GPIOA1_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x2;
}
else if(ulPort == GPIOA2_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x4;
}
else if(ulPort == GPIOA3_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x8;
}
}
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

141
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// gpio.h
//
// Defines and Macros for GPIO API.
//
//*****************************************************************************
#ifndef __GPIO_H__
#define __GPIO_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following values define the bit field for the ucPins argument to several
// of the APIs.
//
//*****************************************************************************
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
//*****************************************************************************
//
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
// returned from GPIODirModeGet.
//
//*****************************************************************************
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
//*****************************************************************************
//
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
// returned from GPIOIntTypeGet.
//
//*****************************************************************************
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level
//*****************************************************************************
//
// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions
// in the ulIntFlags parameter.
//
//*****************************************************************************
#define GPIO_INT_DMA 0x00000100
#define GPIO_INT_PIN_0 0x00000001
#define GPIO_INT_PIN_1 0x00000002
#define GPIO_INT_PIN_2 0x00000004
#define GPIO_INT_PIN_3 0x00000008
#define GPIO_INT_PIN_4 0x00000010
#define GPIO_INT_PIN_5 0x00000020
#define GPIO_INT_PIN_6 0x00000040
#define GPIO_INT_PIN_7 0x00000080
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO);
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType);
extern void GPIODMATriggerEnable(unsigned long ulPort);
extern void GPIODMATriggerDisable(unsigned long ulPort);
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
extern void GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags);
extern void GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags);
extern long GPIOIntStatus(unsigned long ulPort, tBoolean bMasked);
extern void GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags);
extern void GPIOIntRegister(unsigned long ulPort,
void (*pfnIntHandler)(void));
extern void GPIOIntUnregister(unsigned long ulPort);
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
unsigned char ucVal);
extern long GPIOGetIntNumber(unsigned long ulPort);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __GPIO_H__

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/hwspinlock.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// hwspinlock.c
//
// Driver for the Apps-NWP spinlock
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup HwSpinLock_api
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ints.h"
#include "inc/hw_common_reg.h"
#include "hwspinlock.h"
//*****************************************************************************
// Global semaphore register list
//*****************************************************************************
static const uint32_t HwSpinLock_RegLst[]=
{
COMMON_REG_BASE + COMMON_REG_O_SPI_Properties_Register
};
//*****************************************************************************
//
//! Acquire specified spin lock.
//!
//! \param ui32LockID is one of the valid spin lock.
//!
//! This function acquires specified spin lock and will not retun util the
//! specified lock is acquired.
//!
//! The parameter \e ui32LockID should \b HWSPINLOCK_MCSPIS0.
//!
//! return None.
//
//*****************************************************************************
void HwSpinLockAcquire(uint32_t ui32LockID)
{
uint32_t ui32BitPos;
uint32_t ui32SemVal;
uint32_t ui32RegAddr;
//
// Extract the bit position from the
// LockID
//
ui32BitPos = ((ui32LockID >> 16) & 0x0FFF);
ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF];
//
// Set the corresponding
// ownership bits to 'b01
//
ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos));
//
// Retry untill we succeed
//
do
{
HWREG(ui32RegAddr) = ui32SemVal;
}
while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) );
}
//*****************************************************************************
//
//! Try to acquire specified spin lock.
//!
//! \param ui32LockID is one of the valid spin lock.
//! \param ui32Retry is the number of reties.
//!
//! This function tries acquire specified spin lock in \e ui32Retry retries.
//!
//! The parameter \e ui32Retry can be any value between 0 and 2^32.
//!
//! return Returns 0 on success, -1 otherwise.
//
//*****************************************************************************
int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry)
{
uint32_t ui32BitPos;
uint32_t ui32SemVal;
uint32_t ui32RegAddr;
//
// Extract the bit position from the
// LockID
//
ui32BitPos = ((ui32LockID >> 16) & 0x0FFF);
ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF];
//
// Set the corresponding
// ownership bits to 'b01
//
ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos));
//
// Check for 0 retry.
//
if(ui32Retry == 0)
{
ui32Retry = 1;
}
//
// Retry the number of times specified
//
do
{
HWREG(ui32RegAddr) = ui32SemVal;
ui32Retry--;
}
while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) && ui32Retry );
//
// Check the semaphore status
//
if(HWREG(ui32RegAddr) & (1 << ui32BitPos ))
{
return 0;
}
else
{
return -1;
}
}
//*****************************************************************************
//
//! Release a previously owned spin lock
//!
//! \param ui32LockID is one of the valid spin lock.
//!
//! This function releases previously owned spin lock.
//!
//! \return None.
//
//*****************************************************************************
void HwSpinLockRelease(uint32_t ui32LockID)
{
uint32_t ui32BitPos;
uint32_t ui32SemVal;
//
// Extract the bit position from the
// lock id.
//
ui32BitPos = ((ui32LockID >> 16) & 0x00FF);
//
// Release the spin lock, only if already owned
//
if(HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) & (1 << ui32BitPos ))
{
ui32SemVal = (0xFFFFFFFF & ~(0x3 << ui32BitPos));
HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) = ui32SemVal;
}
}
//*****************************************************************************
//
//! Get the current or previous ownership status.
//!
//! \param ui32LockID is one of the valid spin lock.
//! \param bCurrentStatus is \b true for current status, \b flase otherwise
//!
//! This function gets the current or previous ownership status of the
//! specified spin lock based on \e bCurrentStatus parameter.
//!
//! \return Returns \b HWSPINLOCK_OWNER_APPS, \b HWSPINLOCK_OWNER_NWP or
//! \b HWSPINLOCK_OWNER_NONE.
//
//*****************************************************************************
uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus)
{
uint32_t ui32BitPos;
uint32_t ui32SemVal;
if(bCurrentStatus)
{
//
// Extract the bit position from the
// lock id.
//
ui32BitPos = ((ui32LockID >> 16) & 0x00FF);
//
// return semaphore
//
return((HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) >> ui32BitPos ) & 0x3 );
}
else
{
//
// Extract the bit position
//
ui32BitPos = ((ui32LockID >> 24) & 0xFF);
//
// Identify which register to read
//
if((ui32LockID & 0xF) > 4)
{
ui32SemVal = ((HWREG(COMMON_REG_BASE +
COMMON_REG_O_SEMAPHORE_PREV_OWNER1) >> ui32BitPos ) & 0x3);
}
else
{
ui32SemVal = ((HWREG(COMMON_REG_BASE +
COMMON_REG_O_SEMAPHORE_PREV_OWNER2) >> ui32BitPos ) & 0x3);
}
//
// return the owner
//
return ui32SemVal;
}
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// hwspinlock.h
//
// Prototypes for the Apps-NWP spinlock.
//
//*****************************************************************************
#ifndef __HWSPINLOCK_H__
#define __HWSPINLOCK_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// values that can be passed to API as ui32LockID parameter
//*****************************************************************************
#define HWSPINLOCK_SSPI 0x02000000
//*****************************************************************************
// Values that are returned from HwSpinLockTest()
//*****************************************************************************
#define HWSPINLOCK_OWNER_APPS 0x00000001
#define HWSPINLOCK_OWNER_NWP 0x00000002
#define HWSPINLOCK_OWNER_NONE 0x00000000
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void HwSpinLockAcquire(uint32_t ui32LockID);
extern int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry);
extern void HwSpinLockRelease(uint32_t ui32LockID);
extern uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __HWSPINLOCK_H__

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/i2s.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// i2s.h
//
// Defines and Macros for the I2S.
//
//*****************************************************************************
#ifndef __I2S_H__
#define __I2S_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// I2S DMA ports.
//
//*****************************************************************************
#define I2S_TX_DMA_PORT 0x4401E200
#define I2S_RX_DMA_PORT 0x4401E280
//*****************************************************************************
//
// Values that can be passed to I2SConfigSetExpClk() as the ulConfig parameter.
//
//*****************************************************************************
#define I2S_SLOT_SIZE_8 0x00300032
#define I2S_SLOT_SIZE_16 0x00700074
#define I2S_SLOT_SIZE_24 0x00B000B6
#define I2S_PORT_CPU 0x00080008
#define I2S_PORT_DMA 0x00000000
#define I2S_MODE_MASTER 0x00000000
#define I2S_MODE_SLAVE 0x00008000
//*****************************************************************************
//
// Values that can be passed as ulDataLine parameter.
//
//*****************************************************************************
#define I2S_DATA_LINE_0 0x00000001
#define I2S_DATA_LINE_1 0x00000002
//*****************************************************************************
//
// Values that can be passed to I2SSerializerConfig() as the ulSerMode
// parameter.
//
//*****************************************************************************
#define I2S_SER_MODE_TX 0x00000001
#define I2S_SER_MODE_RX 0x00000002
#define I2S_SER_MODE_DISABLE 0x00000000
//*****************************************************************************
//
// Values that can be passed to I2SSerializerConfig() as the ulInActState
// parameter.
//
//*****************************************************************************
#define I2S_INACT_TRI_STATE 0x00000000
#define I2S_INACT_LOW_LEVEL 0x00000008
#define I2S_INACT_HIGH_LEVEL 0x0000000C
//*****************************************************************************
//
// Values that can be passed to I2SIntEnable() and I2SIntDisable() as the
// ulIntFlags parameter.
//
//*****************************************************************************
#define I2S_INT_XUNDRN 0x00000001
#define I2S_INT_XSYNCERR 0x00000002
#define I2S_INT_XLAST 0x00000010
#define I2S_INT_XDATA 0x00000020
#define I2S_INT_XSTAFRM 0x00000080
#define I2S_INT_XDMA 0x80000000
#define I2S_INT_ROVRN 0x00010000
#define I2S_INT_RSYNCERR 0x00020000
#define I2S_INT_RLAST 0x00100000
#define I2S_INT_RDATA 0x00200000
#define I2S_INT_RSTAFRM 0x00800000
#define I2S_INT_RDMA 0x40000000
//*****************************************************************************
//
// Values that can be passed to I2SRxActiveSlotSet() and I2STxActiveSlotSet
//
//*****************************************************************************
#define I2S_ACT_SLOT_EVEN 0x00000001
#define I2S_ACT_SLOT_ODD 0x00000002
//*****************************************************************************
//
// Values that can be passed to I2SIntClear() as the
// ulIntFlags parameter and returned from I2SIntStatus().
//
//*****************************************************************************
#define I2S_STS_XERR 0x00000100
#define I2S_STS_XDMAERR 0x00000080
#define I2S_STS_XSTAFRM 0x00000040
#define I2S_STS_XDATA 0x00000020
#define I2S_STS_XLAST 0x00000010
#define I2S_STS_XSYNCERR 0x00000002
#define I2S_STS_XUNDRN 0x00000001
#define I2S_STS_XDMA 0x80000000
#define I2S_STS_RERR 0x01000000
#define I2S_STS_RDMAERR 0x00800000
#define I2S_STS_RSTAFRM 0x00400000
#define I2S_STS_RDATA 0x00200000
#define I2S_STS_RLAST 0x00100000
#define I2S_STS_RSYNCERR 0x00020000
#define I2S_STS_ROVERN 0x00010000
#define I2S_STS_RDMA 0x40000000
//*****************************************************************************
//
// Values that can be passed to I2SEnable() as the ulMode parameter.
//
//*****************************************************************************
#define I2S_MODE_TX_ONLY 0x00000001
#define I2S_MODE_TX_RX_SYNC 0x00000003
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void I2SEnable(unsigned long ulBase, unsigned long ulMode);
extern void I2SDisable(unsigned long ulBase);
extern void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine,
unsigned long ulData);
extern long I2SDataPutNonBlocking(unsigned long ulBase,
unsigned long ulDataLine, unsigned long ulData);
extern void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine,
unsigned long *pulData);
extern long I2SDataGetNonBlocking(unsigned long ulBase,
unsigned long ulDataLine, unsigned long *pulData);
extern void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk,
unsigned long ulBitClk, unsigned long ulConfig);
extern void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulWordsPerTransfer);
extern void I2STxFIFODisable(unsigned long ulBase);
extern void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel,
unsigned long ulWordsPerTransfer);
extern void I2SRxFIFODisable(unsigned long ulBase);
extern unsigned long I2STxFIFOStatusGet(unsigned long ulBase);
extern unsigned long I2SRxFIFOStatusGet(unsigned long ulBase);
extern void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine,
unsigned long ulSerMode, unsigned long ulInActState);
extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long I2SIntStatus(unsigned long ulBase);
extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void I2SIntUnregister(unsigned long ulBase);
extern void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot);
extern void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif //__I2S_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// interrupt.c
//
// Driver for the NVIC Interrupt Controller.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup interrupt_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "cpu.h"
#include "debug.h"
#include "interrupt.h"
//*****************************************************************************
//
// This is a mapping between priority grouping encodings and the number of
// preemption priority bits.
//
//*****************************************************************************
static const unsigned long g_pulPriority[] =
{
NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
};
//*****************************************************************************
//
// This is a mapping between interrupt number and the register that contains
// the priority encoding for that interrupt.
//
//*****************************************************************************
static const unsigned long g_pulRegs[] =
{
0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,
NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,
NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,
NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,
NVIC_PRI32, NVIC_PRI33, NVIC_PRI34, NVIC_PRI35, NVIC_PRI36, NVIC_PRI37,
NVIC_PRI38, NVIC_PRI39, NVIC_PRI40, NVIC_PRI41, NVIC_PRI42, NVIC_PRI43,
NVIC_PRI44, NVIC_PRI45, NVIC_PRI46, NVIC_PRI47, NVIC_PRI48
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt enable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulEnRegs[] =
{
NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4, NVIC_EN5
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt disable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulDisRegs[] =
{
NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4, NVIC_DIS5
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt pend for that interrupt.
//
//*****************************************************************************
static const unsigned long g_pulPendRegs[] =
{
NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4, NVIC_PEND5
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt unpend for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulUnpendRegs[] =
{
NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4,
NVIC_UNPEND5
};
//*****************************************************************************
//
//! \internal
//! The default interrupt handler.
//!
//! This is the default interrupt handler for all interrupts. It simply loops
//! forever so that the system state is preserved for observation by a
//! debugger. Since interrupts should be disabled before unregistering the
//! corresponding handler, this should never be called.
//!
//! \return None.
//
//*****************************************************************************
static void
IntDefaultHandler(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
//! Enables the processor interrupt.
//!
//! Allows the processor to respond to interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were disabled when the function was
//! called or \b false if they were initially enabled.
//
//*****************************************************************************
tBoolean
IntMasterEnable(void)
{
//
// Enable processor interrupts.
//
return(CPUcpsie());
}
//*****************************************************************************
//
//! Disables the processor interrupt.
//!
//! Prevents the processor from receiving interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were already disabled when the
//! function was called or \b false if they were initially enabled.
//
//*****************************************************************************
tBoolean
IntMasterDisable(void)
{
//
// Disable processor interrupts.
//
return(CPUcpsid());
}
//*****************************************************************************
//
//! Sets the NVIC VTable base.
//!
//! \param ulVtableBase specifies the new base address of VTable
//!
//! This function is used to specify a new base address for the VTable.
//! This function must be called before using IntRegister() for registering
//! any interrupt handler.
//!
//!
//! \return None.
//
//*****************************************************************************
void
IntVTableBaseSet(unsigned long ulVtableBase)
{
HWREG(NVIC_VTABLE) = ulVtableBase;
}
//*****************************************************************************
//
//! Registers a function to be called when an interrupt occurs.
//!
//! \param ulInterrupt specifies the interrupt in question.
//! \param pfnHandler is a pointer to the function to be called.
//!
//! This function is used to specify the handler function to be called when the
//! given interrupt is asserted to the processor. When the interrupt occurs,
//! if it is enabled (via IntEnable()), the handler function will be called in
//! interrupt context. Since the handler function can preempt other code, care
//! must be taken to protect memory or peripherals that are accessed by the
//! handler and other non-handler code.
//!
//!
//! \return None.
//
//*****************************************************************************
void
IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
{
unsigned long *ulNvicTbl;
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE);
ulNvicTbl[ulInterrupt]= (unsigned long)pfnHandler;
}
//*****************************************************************************
//
//! Unregisters the function to be called when an interrupt occurs.
//!
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function is used to indicate that no handler should be called when the
//! given interrupt is asserted to the processor. The interrupt source will be
//! automatically disabled (via IntDisable()) if necessary.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
IntUnregister(unsigned long ulInterrupt)
{
unsigned long *ulNvicTbl;
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE);
ulNvicTbl[ulInterrupt]= (unsigned long)IntDefaultHandler;
}
//*****************************************************************************
//
//! Sets the priority grouping of the interrupt controller.
//!
//! \param ulBits specifies the number of bits of preemptable priority.
//!
//! This function specifies the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification. The range of
//! the grouping values are dependent upon the hardware implementation; on
//! the CC3200 , three bits are available for hardware interrupt
//! prioritization and therefore priority grouping values of three through
//! seven have the same effect.
//!
//! \return None.
//
//*****************************************************************************
void
IntPriorityGroupingSet(unsigned long ulBits)
{
//
// Check the arguments.
//
ASSERT(ulBits < NUM_PRIORITY);
//
// Set the priority grouping.
//
HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
}
//*****************************************************************************
//
//! Gets the priority grouping of the interrupt controller.
//!
//! This function returns the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification.
//!
//! \return The number of bits of preemptable priority.
//
//*****************************************************************************
unsigned long
IntPriorityGroupingGet(void)
{
unsigned long ulLoop, ulValue;
//
// Read the priority grouping.
//
ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
//
// Loop through the priority grouping values.
//
for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
{
//
// Stop looping if this value matches.
//
if(ulValue == g_pulPriority[ulLoop])
{
break;
}
}
//
// Return the number of priority bits.
//
return(ulLoop);
}
//*****************************************************************************
//
//! Sets the priority of an interrupt.
//!
//! \param ulInterrupt specifies the interrupt in question.
//! \param ucPriority specifies the priority of the interrupt.
//!
//! This function is used to set the priority of an interrupt. When multiple
//! interrupts are asserted simultaneously, the ones with the highest priority
//! are processed before the lower priority interrupts. Smaller numbers
//! correspond to higher interrupt priorities; priority 0 is the highest
//! interrupt priority.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3), so any prioritization must be performed in
//! those bits. The remaining bits can be used to sub-prioritize the interrupt
//! sources, and may be used by the hardware priority mechanism on a future
//! part. This arrangement allows priorities to migrate to different NVIC
//! implementations without changing the gross prioritization of the
//! interrupts.
//!
//! The parameter \e ucPriority can be any one of the following
//! -\b INT_PRIORITY_LVL_0
//! -\b INT_PRIORITY_LVL_1
//! -\b INT_PRIORITY_LVL_2
//! -\b INT_PRIORITY_LVL_3
//! -\b INT_PRIORITY_LVL_4
//! -\b INT_PRIORITY_LVL_5
//! -\b INT_PRIORITY_LVL_6
//! -\b INT_PRIORITY_LVL_7
//!
//! \return None.
//
//*****************************************************************************
void
IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
{
unsigned long ulTemp;
//
// Check the arguments.
//
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
//
// Set the interrupt priority.
//
ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
}
//*****************************************************************************
//
//! Gets the priority of an interrupt.
//!
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function gets the priority of an interrupt. See IntPrioritySet() for
//! a definition of the priority value.
//!
//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
//! specified.
//
//*****************************************************************************
long
IntPriorityGet(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
//
// Return the interrupt priority.
//
return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
0xFF);
}
//*****************************************************************************
//
//! Enables an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be enabled.
//!
//! The specified interrupt is enabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! \return None.
//
//*****************************************************************************
void
IntEnable(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to enable.
//
if(ulInterrupt == FAULT_MPU)
{
//
// Enable the MemManage interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_BUS)
{
//
// Enable the bus fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_USAGE)
{
//
// Enable the usage fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Enable the System Tick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt >= 16)
{
//
// Enable the general interrupt.
//
HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
__asm(" dsb ");
__asm(" isb ");
}
}
//*****************************************************************************
//
//! Disables an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be disabled.
//!
//! The specified interrupt is disabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! \return None.
//
//*****************************************************************************
void
IntDisable(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to disable.
//
if(ulInterrupt == FAULT_MPU)
{
//
// Disable the MemManage interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_BUS)
{
//
// Disable the bus fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_USAGE)
{
//
// Disable the usage fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Disable the System Tick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt >= 16)
{
//
// Disable the general interrupt.
//
HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
__asm(" dsb ");
__asm(" isb ");
}
}
//*****************************************************************************
//
//! Pends an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be pended.
//!
//! The specified interrupt is pended in the interrupt controller. This will
//! cause the interrupt controller to execute the corresponding interrupt
//! handler at the next available time, based on the current interrupt state
//! priorities. For example, if called by a higher priority interrupt handler,
//! the specified interrupt handler will not be called until after the current
//! interrupt handler has completed execution. The interrupt must have been
//! enabled for it to be called.
//!
//! \return None.
//
//*****************************************************************************
void
IntPendSet(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to pend.
//
if(ulInterrupt == FAULT_NMI)
{
//
// Pend the NMI interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_PENDSV)
{
//
// Pend the PendSV interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Pend the SysTick interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt >= 16)
{
//
// Pend the general interrupt.
//
HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
__asm(" dsb ");
__asm(" isb ");
}
}
//*****************************************************************************
//
//! Unpends an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be unpended.
//!
//! The specified interrupt is unpended in the interrupt controller. This will
//! cause any previously generated interrupts that have not been handled yet
//! (due to higher priority interrupts or the interrupt no having been enabled
//! yet) to be discarded.
//!
//! \return None.
//
//*****************************************************************************
void
IntPendClear(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to unpend.
//
if(ulInterrupt == FAULT_PENDSV)
{
//
// Unpend the PendSV interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Unpend the SysTick interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
}
else if(ulInterrupt >= 16)
{
//
// Unpend the general interrupt.
//
HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
//*****************************************************************************
//
//! Sets the priority masking level
//!
//! \param ulPriorityMask is the priority level that will be masked.
//!
//! This function sets the interrupt priority masking level so that all
//! interrupts at the specified or lesser priority level is masked. This
//! can be used to globally disable a set of interrupts with priority below
//! a predetermined threshold. A value of 0 disables priority
//! masking.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3), so any
//! prioritization must be performed in those bits.
//!
//! \return None.
//
//*****************************************************************************
void
IntPriorityMaskSet(unsigned long ulPriorityMask)
{
CPUbasepriSet(ulPriorityMask);
}
//*****************************************************************************
//
//! Gets the priority masking level
//!
//! This function gets the current setting of the interrupt priority masking
//! level. The value returned is the priority level such that all interrupts
//! of that and lesser priority are masked. A value of 0 means that priority
//! masking is disabled.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3), so any
//! prioritization must be performed in those bits.
//!
//! \return Returns the value of the interrupt priority level mask.
//
//*****************************************************************************
unsigned long
IntPriorityMaskGet(void)
{
return(CPUbasepriGet());
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

121
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/interrupt.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// interrupt.h
//
// Prototypes for the NVIC Interrupt Controller Driver.
//
//*****************************************************************************
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// A union that describes the entries of the vector table. The union is needed
// since the first entry is the stack pointer and the remainder are function
// pointers.
//
//*****************************************************************************
typedef union
{
void (*pfnHandler)(void);
unsigned long ulPtr;
}
uVectorEntry;
//*****************************************************************************
//
// Macro to generate an interrupt priority mask based on the number of bits
// of priority supported by the hardware.
//
//*****************************************************************************
#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
//*****************************************************************************
// Interrupt priority levels
//*****************************************************************************
#define INT_PRIORITY_LVL_0 0x00
#define INT_PRIORITY_LVL_1 0x20
#define INT_PRIORITY_LVL_2 0x40
#define INT_PRIORITY_LVL_3 0x60
#define INT_PRIORITY_LVL_4 0x80
#define INT_PRIORITY_LVL_5 0xA0
#define INT_PRIORITY_LVL_6 0xC0
#define INT_PRIORITY_LVL_7 0xE0
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean IntMasterEnable(void);
extern tBoolean IntMasterDisable(void);
extern void IntVTableBaseSet(unsigned long ulVtableBase);
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
extern void IntUnregister(unsigned long ulInterrupt);
extern void IntPriorityGroupingSet(unsigned long ulBits);
extern unsigned long IntPriorityGroupingGet(void);
extern void IntPrioritySet(unsigned long ulInterrupt,
unsigned char ucPriority);
extern long IntPriorityGet(unsigned long ulInterrupt);
extern void IntEnable(unsigned long ulInterrupt);
extern void IntDisable(unsigned long ulInterrupt);
extern void IntPendSet(unsigned long ulInterrupt);
extern void IntPendClear(unsigned long ulInterrupt);
extern void IntPriorityMaskSet(unsigned long ulPriorityMask);
extern unsigned long IntPriorityMaskGet(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __INTERRUPT_H__

884
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// pin.c
//
// Mapping of peripherals to pins.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup pin_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ocp_shared.h"
#include "pin.h"
//*****************************************************************************
// Macros
//*****************************************************************************
#define PAD_MODE_MASK 0x0000000F
#define PAD_STRENGTH_MASK 0x000000E0
#define PAD_TYPE_MASK 0x00000310
#define PAD_CONFIG_BASE ((OCP_SHARED_BASE + \
OCP_SHARED_O_GPIO_PAD_CONFIG_0))
//*****************************************************************************
// PIN to PAD matrix
//*****************************************************************************
static const unsigned long g_ulPinToPadMap[64] =
{
10,11,12,13,14,15,16,17,255,255,18,
19,20,21,22,23,24,40,28,29,25,255,
255,255,255,255,255,255,255,255,255,255,255,
255,255,255,255,255,255,255,255,255,255,255,
31,255,255,255,255,0,255,32,30,255,1,
255,2,3,4,5,6,7,8,9
};
//*****************************************************************************
//
//! Configures pin mux for the specified pin.
//!
//! \param ulPin is a valid pin.
//! \param ulPinMode is one of the valid mode
//!
//! This function configures the pin mux that selects the peripheral function
//! associated with a particular SOC pin. Only one peripheral function at a
//! time can be associated with a pin, and each peripheral function should
//! only be associated with a single pin at a time.
//!
//! \return none
//
//*****************************************************************************
void PinModeSet(unsigned long ulPin,unsigned long ulPinMode)
{
unsigned long ulPad;
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
//
// Set the mode.
//
HWREG(ulPad) = (((HWREG(ulPad) & ~PAD_MODE_MASK) | ulPinMode) & ~(3<<10));
}
//*****************************************************************************
//
//! Gets current pin mux configuration of specified pin.
//!
//! \param ulPin is a valid pin.
//!
//! This function get the current configuration of the pin mux.
//!
//! \return Returns current pin mode if \e ulPin is valid, 0xFF otherwise.
//
//*****************************************************************************
unsigned long PinModeGet(unsigned long ulPin)
{
unsigned long ulPad;
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE) ;
//
// return the mode.
//
return (HWREG(ulPad) & PAD_MODE_MASK);
}
//*****************************************************************************
//
//! Sets the direction of the specified pin(s).
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinIO is the pin direction and/or mode.
//!
//! This function configures the specified pin(s) as either input only or
//! output only or it configures the pin to be under hardware control.
//!
//! The parameter \e ulPinIO is an enumerated data type that can be one of
//! the following values:
//!
//! - \b PIN_DIR_MODE_IN
//! - \b PIN_DIR_MODE_OUT
//! - \b PIN_DIR_MODE_HW
//!
//! where \b PIN_DIR_MODE_IN specifies that the pin is programmed as a
//! input only, \b PIN_DIR_MODE_OUT specifies that the pin is
//! programmed output only, and \b PIN_DIR_MODE_HW specifies that the pin is
//! placed under hardware control.
//!
//!
//! \return None.
//
//*****************************************************************************
void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO)
{
unsigned long ulPad;
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
//
// Set the direction
//
HWREG(ulPad) = ((HWREG(ulPad) & ~0xC00) | ulPinIO);
}
//*****************************************************************************
//
//! Gets the direction of a pin.
//!
//! \param ulPin is one of the valid pin.
//!
//! This function gets the direction and control mode for a specified pin on
//! the selected GPIO port. The pin can be configured as either an input only
//! or output only, or it can be under hardware control. The type of control
//! and direction are returned as an enumerated data type.
//!
//! \return Returns one of the enumerated data types described for
//! GPIODirModeSet().
//
//*****************************************************************************
unsigned long PinDirModeGet(unsigned long ulPin)
{
unsigned long ulPad;
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
//
// Return the direction
//
return ((HWREG(ulPad) & 0xC00));
}
//*****************************************************************************
//
//! Gets Pin output drive strength and Type
//!
//! \param ulPin is one of the valid pin
//! \param pulPinStrength is pointer to storage for output drive strength
//! \param pulPinType is pinter to storage for pin type
//!
//! This function gets the pin type and output drive strength for the pin
//! specified by \e ulPin parameter. Parameters \e pulPinStrength and
//! \e pulPinType corresponds to the values used in PinConfigSet().
//!
//!
//! \return None.
//
//*****************************************************************************
void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength,
unsigned long *pulPinType)
{
unsigned long ulPad;
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
//
// Get the type
//
*pulPinType = (HWREG(ulPad) & PAD_TYPE_MASK);
//
// Get the output drive strength
//
*pulPinStrength = (HWREG(ulPad) & PAD_STRENGTH_MASK);
}
//*****************************************************************************
//
//! Configure Pin output drive strength and Type
//!
//! \param ulPin is one of the valid pin
//! \param ulPinStrength is logical OR of valid output drive strengths.
//! \param ulPinType is one of the valid pin type.
//!
//! This function sets the pin type and strength for the pin specified by
//! \e ulPin parameter.
//!
//! The parameter \e ulPinStrength should be one of the following
//! - \b PIN_STRENGTH_2MA
//! - \b PIN_STRENGTH_4MA
//! - \b PIN_STRENGTH_6MA
//!
//!
//! The parameter \e ulPinType should be one of the following
//! For standard type
//!
//! - \b PIN_TYPE_STD
//! - \b PIN_TYPE_STD_PU
//! - \b PIN_TYPE_STD_PD
//!
//! And for Open drain type
//!
//! - \b PIN_TYPE_OD
//! - \b PIN_TYPE_OD_PU
//! - \b PIN_TYPE_OD_PD
//!
//! \return None.
//
//*****************************************************************************
void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength,
unsigned long ulPinType)
{
unsigned long ulPad;
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Write the register
//
if(ulPinType == PIN_TYPE_ANALOG)
{
//
// Isolate the input
//
HWREG(0x4402E144) |= ((0x80 << ulPad) & (0x1E << 8));
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
//
// Isolate the output
//
HWREG(ulPad) = 0xC00;
}
else
{
//
// Enable the input
//
HWREG(0x4402E144) &= ~((0x80 << ulPad) & (0x1E << 8));
//
// Calculate the register address
//
ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
//
// Write the configuration
//
HWREG(ulPad) = ((HWREG(ulPad) & ~(PAD_STRENGTH_MASK | PAD_TYPE_MASK)) |
(ulPinStrength | ulPinType ));
}
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by UART peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The UART pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin(s); other configurations may work as well depending upon the
//! board setup (for example, using the on-chip pull-ups).
//!
//!
//! \note This function cannot be used to turn any pin into a UART pin; it
//! only sets the pin mode and configures it for proper UART operation.
//!
//!
//! \return None.
//
//*****************************************************************************
void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set the pin to specified mode
//
PinModeSet(ulPin,ulPinMode);
//
// Set the pin for standard operation
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by I2C peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The I2C pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! the pin.
//!
//!
//! \note This function cannot be used to turn any pin into a I2C pin; it
//! only sets the pin mode and configures it for proper I2C operation.
//!
//!
//! \return None.
//
//*****************************************************************************
void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set the pin to specified mode
//
PinModeSet(ulPin,ulPinMode);
//
// Set the pin for open-drain operation with a weak pull-up.
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_OD_PU);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by SPI peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The SPI pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin.
//!
//!
//! \note This function cannot be used to turn any pin into a SPI pin; it
//! only sets the pin mode and configures it for proper SPI operation.
//!
//!
//! \return None.
//
//*****************************************************************************
void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set the pin to specified mode
//
PinModeSet(ulPin,ulPinMode);
//
// Set the pin for standard operation
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by I2S peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The I2S pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin.
//!
//!
//! \note This function cannot be used to turn any pin into a I2S pin; it
//! only sets the pin mode and configures it for proper I2S operation.
//!
//! \return None.
//
//*****************************************************************************
void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set the pin to specified mode
//
PinModeSet(ulPin,ulPinMode);
//
// Set the pin for standard operation
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by Timer peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The timer PWM pins must be properly configured for the Timer peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin; other configurations may work as well depending upon the
//! board setup (for example, using the on-chip pull-ups).
//!
//!
//! \note This function cannot be used to turn any pin into a timer PWM pin; it
//! only sets the pin mode and configures it for proper timer PWM operation.
//!
//! \return None.
//
//*****************************************************************************
void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set the pin to specified mode
//
PinModeSet(ulPin,ulPinMode);
//
// Set the pin for standard operation
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by Camera peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The Camera pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin.
//!
//!
//! \note This function cannot be used to turn any pin into a Camera pin; it
//! only sets the pin mode and configures it for proper Camera operation.
//!
//! \return None.
//
//*****************************************************************************
void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set the pin to specified mode
//
PinModeSet(ulPin,ulPinMode);
//
// Set the pin for standard operation
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by GPIO peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//! \param bOpenDrain is one to decide either OpenDrain or STD
//!
//! The GPIO pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin.
//!
//!
//! \return None.
//
//*****************************************************************************
void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode,tBoolean bOpenDrain)
{
//
// Set the pin for standard push-pull operation.
//
if(bOpenDrain)
{
PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_OD);
}
else
{
PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_STD);
}
//
// Set the pin to specified mode
//
PinModeSet(ulPin, ulPinMode);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by ADC
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The ADC pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin.
//!
//!
//! \note This function cannot be used to turn any pin into a ADC pin; it
//! only sets the pin mode and configures it for proper ADC operation.
//!
//! \return None.
//
//*****************************************************************************
void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Configure the Pin
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_ANALOG);
}
//*****************************************************************************
//
//! Sets the pin mode and configures the pin for use by SD Host peripheral
//!
//! \param ulPin is one of the valid pin.
//! \param ulPinMode is one of the valid pin mode.
//!
//! The MMC pins must be properly configured for the peripheral to
//! function correctly. This function provides a typical configuration for
//! those pin.
//!
//!
//! \note This function cannot be used to turn any pin into a SD Host pin; it
//! only sets the pin mode and configures it for proper SD Host operation.
//!
//! \return None.
//
//*****************************************************************************
void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode)
{
//
// Set pin mode
//
PinModeSet(ulPin,ulPinMode);
//
// Configure the Pin
//
PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD);
}
//*****************************************************************************
//
//! Sets the hysteresis for all the pins
//!
//! \param ulHysteresis is one of the valid predefined hysterisys values
//!
//! This function sets the hysteresis vlaue for all the pins. The parameter
//! \e ulHysteresis can be on one the following:
//! -\b PIN_HYSTERESIS_OFF - To turn Off hysteresis, default on POR
//! -\b PIN_HYSTERESIS_10 - To turn On hysteresis, 10%
//! -\b PIN_HYSTERESIS_20 - To turn On hysteresis, 20%
//! -\b PIN_HYSTERESIS_30 - To turn On hysteresis, 30%
//! -\b PIN_HYSTERESIS_40 - To turn On hysteresis, 40%
//!
//! \return None.
//
//*****************************************************************************
void PinHysteresisSet(unsigned long ulHysteresis)
{
unsigned long ulRegValue;
//
// Read the current value
//
ulRegValue = (HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG )
& ~(0x0000001C));
//
// Set the new Hysteresis
//
if( ulHysteresis != PIN_HYSTERESIS_OFF )
{
ulRegValue |= (ulHysteresis & 0x0000001C);
}
//
// Write the new value
//
HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG ) = ulRegValue;
}
//*****************************************************************************
//
//! Sets the level of the pin when locked
//!
//! \param ulPin is one of the valid pin.
//! \param ucLevel is the level the pin drives when locked
//!
//! This function sets the pin level when the pin is locked using
//! \sa PinLock() API.
//!
//! By default all pins are set to drive 0.
//!
//! \note Use case is to park the pins when entering LPDS
//!
//! \return None.
//
//*****************************************************************************
void PinLockLevelSet(unsigned long ulPin, unsigned char ucLevel)
{
unsigned long ulPad;
//
// Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater
//
if( (HWREG(0x00000400) & 0xFFFF) >= 2 )
{
//
// Get the corresponding Pad
//
ulPad = g_ulPinToPadMap[ulPin & 0x3F];
//
// Get the required bit
//
ulPad = 1 << ulPad;
if(ucLevel)
{
HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) |= ulPad;
}
else
{
HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) &= ~ulPad;
}
}
}
//*****************************************************************************
//
//! Locks all the pins to configured level(s).
//!
//! \param ulOutEnable the bit-packed representation of pins to be set as output
//!
//! This function locks all the pins to the pre-configure level. By default
//! the pins are set to drive 0. Default level can be changed using
//! \sa PinLockLevelSet() API.
//!
//! The \e ulOutEnable paramter is bit-packed representation of pins that
//! are required to be enabled as output. If a bit is set 1, the corresponding
//! pin (as shown below) are set and locked as output.
//!
//! |------|-----------------------------------------------|
//! | Bit |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
//! |------|-----------------------------------------------|
//! | Pin |xx|xx|20|19|30|29|21|17|16|15|14|13|12|11|08|07|
//! |------|-----------------------------------------------|
//!
//! |------|-----------------------------------------------|
//! | Bit |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
//! |------|-----------------------------------------------|
//! | Pin |06|05|04|03|02|01|64|63|62|61|60|59|58|57|55|50|
//! |------|-----------------------------------------------|
//!
//!
//! \note Use case is to park the pins when entering LPDS
//!
//! \return None.
//
//*****************************************************************************
void PinLock(unsigned long ulOutEnable)
{
//
// Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater
//
if( (HWREG(0x00000400) & 0xFFFF) >= 2 )
{
//
// Enable/disable the pin(s) output
//
HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_7 ) = ~ulOutEnable;
//
// Lock the pins to selected levels
//
HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) |= (3 << 24);
}
}
//*****************************************************************************
//
//! Unlocks all the pins.
//!
//! This function unlocks all the pins and can be used for peripheral function.
//!
//! By default all the pins are in unlocked state.
//!
//! \note Use case is to un-park the pins when exiting LPDS
//!
//! \return None.
//
//*****************************************************************************
void PinUnlock()
{
//
// Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater
//
if( (HWREG(0x00000400) & 0xFFFF) >= 2 )
{
//
// Unlock the pins
//
HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) &= ~(3 << 24);
}
}
//*****************************************************************************
//
// Gets pad number from pin number
//
// \param ulPin is a valid pin number
//
// This function return the pad corresponding to the specified pin
//
// \return Pad number on success, 0xFF otherwise
//
//*****************************************************************************
unsigned long PinToPadGet(unsigned long ulPin)
{
//
// Return the corresponding Pad
//
return g_ulPinToPadMap[ulPin & 0x3F];
}
//*****************************************************************************
//
// Gets pin number from pad number
//
// \param ulPad is a valid pad number
//
// This function return the pin corresponding to the specified pad
//
// \return Pin number on success, 0xFF otherwise
//
//*****************************************************************************
unsigned long PinFromPadGet(unsigned long ulPad)
{
unsigned long ulPin;
//
// search and return the pin number
//
for(ulPin=0; ulPin < sizeof(g_ulPinToPadMap)/4; ulPin++)
{
if(g_ulPinToPadMap[ulPin] == ulPad)
{
return ulPin;
}
}
return 0xFF;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

192
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/pin.h Executable file
View File

@ -0,0 +1,192 @@
/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// pin.h
//
// Defines and Macros for the pin mux module
//
//*****************************************************************************
#ifndef __PIN_H__
#define __PIN_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// Macros Defining Pins
//*****************************************************************************
#define PIN_01 0x00000000
#define PIN_02 0x00000001
#define PIN_03 0x00000002
#define PIN_04 0x00000003
#define PIN_05 0x00000004
#define PIN_06 0x00000005
#define PIN_07 0x00000006
#define PIN_08 0x00000007
#define PIN_11 0x0000000A
#define PIN_12 0x0000000B
#define PIN_13 0x0000000C
#define PIN_14 0x0000000D
#define PIN_15 0x0000000E
#define PIN_16 0x0000000F
#define PIN_17 0x00000010
#define PIN_18 0x00000011
#define PIN_19 0x00000012
#define PIN_20 0x00000013
#define PIN_21 0x00000014
#define PIN_29 0x0000001C
#define PIN_30 0x0000001D
#define PIN_45 0x0000002C
#define PIN_46 0x0000002D
#define PIN_47 0x0000002E
#define PIN_48 0x0000002F
#define PIN_49 0x00000030
#define PIN_50 0x00000031
#define PIN_52 0x00000033
#define PIN_53 0x00000034
#define PIN_55 0x00000036
#define PIN_56 0x00000037
#define PIN_57 0x00000038
#define PIN_58 0x00000039
#define PIN_59 0x0000003A
#define PIN_60 0x0000003B
#define PIN_61 0x0000003C
#define PIN_62 0x0000003D
#define PIN_63 0x0000003E
#define PIN_64 0x0000003F
//*****************************************************************************
// Macros that can be used with PinConfigSet(), PinTypeGet(), PinStrengthGet()
//*****************************************************************************
#define PIN_MODE_0 0x00000000
#define PIN_MODE_1 0x00000001
#define PIN_MODE_2 0x00000002
#define PIN_MODE_3 0x00000003
#define PIN_MODE_4 0x00000004
#define PIN_MODE_5 0x00000005
#define PIN_MODE_6 0x00000006
#define PIN_MODE_7 0x00000007
#define PIN_MODE_8 0x00000008
#define PIN_MODE_9 0x00000009
#define PIN_MODE_10 0x0000000A
#define PIN_MODE_11 0x0000000B
#define PIN_MODE_12 0x0000000C
#define PIN_MODE_13 0x0000000D
#define PIN_MODE_14 0x0000000E
#define PIN_MODE_15 0x0000000F
// Note : PIN_MODE_255 is a dummy define for pinmux utility code generation
// PIN_MODE_255 should never be used in any user code.
#define PIN_MODE_255 0x000000FF
//*****************************************************************************
// Macros that can be used with PinDirModeSet() and returned from
// PinDirModeGet().
//*****************************************************************************
#define PIN_DIR_MODE_IN 0x00000C00 // Pin is input
#define PIN_DIR_MODE_OUT 0x00000800 // Pin is output
#define PIN_DIR_MODE_HW 0x00000000 // Pin is peripheral function
//*****************************************************************************
// Macros that can be used with PinConfigSet()
//*****************************************************************************
#define PIN_STRENGTH_2MA 0x00000020
#define PIN_STRENGTH_4MA 0x00000040
#define PIN_STRENGTH_6MA 0x00000060
#define PIN_TYPE_STD 0x00000000
#define PIN_TYPE_STD_PU 0x00000100
#define PIN_TYPE_STD_PD 0x00000200
#define PIN_TYPE_OD 0x00000010
#define PIN_TYPE_OD_PU 0x00000110
#define PIN_TYPE_OD_PD 0x00000210
#define PIN_TYPE_ANALOG 0x10000000
//*****************************************************************************
// Macros that can be used with PinHysteresisSet()
//*****************************************************************************
#define PIN_HYSTERESIS_OFF 0x00000000
#define PIN_HYSTERESIS_10 0x00000004
#define PIN_HYSTERESIS_20 0x0000000C
#define PIN_HYSTERESIS_30 0x00000014
#define PIN_HYSTERESIS_40 0x0000001C
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void PinModeSet(unsigned long ulPin, unsigned long ulPinMode);
extern void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO);
extern unsigned long PinDirModeGet(unsigned long ulPin);
extern unsigned long PinModeGet(unsigned long ulPin);
extern void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength,
unsigned long *pulPinType);
extern void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength,
unsigned long ulPinType);
extern void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode,
tBoolean bOpenDrain);
extern void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode);
extern void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode);
extern void PinHysteresisSet(unsigned long ulHysteresis);
extern void PinLockLevelSet(unsigned long ulPin, unsigned char ucLevel);
extern void PinLock(unsigned long ulOutEnable);
extern void PinUnlock(void);
extern unsigned long PinToPadGet(unsigned long ulPin);
extern unsigned long PinFromPadGet(unsigned long ulPad);
#ifdef __cplusplus
}
#endif
#endif //__PIN_H__

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/prcm.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// prcm.h
//
// Prototypes for the PRCM control driver.
//
//*****************************************************************************
#ifndef __PRCM_H__
#define __PRCM_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Peripheral clock and reset control registers
//
//*****************************************************************************
typedef struct _PRCM_PeripheralRegs_
{
unsigned long ulClkReg;
unsigned long ulRstReg;
}PRCM_PeriphRegs_t;
//*****************************************************************************
// Values that can be passed to PRCMPeripheralEnable() and
// PRCMPeripheralDisable()
//*****************************************************************************
#define PRCM_RUN_MODE_CLK 0x00000001
#define PRCM_SLP_MODE_CLK 0x00000100
//*****************************************************************************
// Values that can be passed to PRCMSRAMRetentionEnable() and
// PRCMSRAMRetentionDisable() as ulSramColSel.
//*****************************************************************************
#define PRCM_SRAM_COL_1 0x00000001
#define PRCM_SRAM_COL_2 0x00000002
#define PRCM_SRAM_COL_3 0x00000004
#define PRCM_SRAM_COL_4 0x00000008
//*****************************************************************************
// Values that can be passed to PRCMSRAMRetentionEnable() and
// PRCMSRAMRetentionDisable() as ulModeFlags.
//*****************************************************************************
#define PRCM_SRAM_LPDS_RET 0x00000002
//*****************************************************************************
// Values that can be passed to PRCMLPDSWakeupSourceEnable(),
// PRCMLPDSWakeupCauseGet() and PRCMLPDSWakeupSourceDisable().
//*****************************************************************************
#define PRCM_LPDS_HOST_IRQ 0x00000080
#define PRCM_LPDS_GPIO 0x00000010
#define PRCM_LPDS_TIMER 0x00000001
//*****************************************************************************
// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() as Type
//*****************************************************************************
#define PRCM_LPDS_LOW_LEVEL 0x00000002
#define PRCM_LPDS_HIGH_LEVEL 0x00000000
#define PRCM_LPDS_FALL_EDGE 0x00000001
#define PRCM_LPDS_RISE_EDGE 0x00000003
//*****************************************************************************
// Values that can be passed to PRCMLPDSWakeUpGPIOSelect()
//*****************************************************************************
#define PRCM_LPDS_GPIO2 0x00000000
#define PRCM_LPDS_GPIO4 0x00000001
#define PRCM_LPDS_GPIO13 0x00000002
#define PRCM_LPDS_GPIO17 0x00000003
#define PRCM_LPDS_GPIO11 0x00000004
#define PRCM_LPDS_GPIO24 0x00000005
#define PRCM_LPDS_GPIO26 0x00000006
//*****************************************************************************
// Values that can be passed to PRCMHibernateWakeupSourceEnable(),
// PRCMHibernateWakeupSourceDisable().
//*****************************************************************************
#define PRCM_HIB_SLOW_CLK_CTR 0x00000001
//*****************************************************************************
// Values that can be passed to PRCMHibernateWakeUpGPIOSelect() as ulType
//*****************************************************************************
#define PRCM_HIB_LOW_LEVEL 0x00000000
#define PRCM_HIB_HIGH_LEVEL 0x00000001
#define PRCM_HIB_FALL_EDGE 0x00000002
#define PRCM_HIB_RISE_EDGE 0x00000003
//*****************************************************************************
// Values that can be passed to PRCMHibernateWakeupSourceEnable(),
// PRCMHibernateWakeupSourceDisable(), PRCMHibernateWakeUpGPIOSelect()
//*****************************************************************************
#define PRCM_HIB_GPIO2 0x00010000
#define PRCM_HIB_GPIO4 0x00020000
#define PRCM_HIB_GPIO13 0x00040000
#define PRCM_HIB_GPIO17 0x00080000
#define PRCM_HIB_GPIO11 0x00100000
#define PRCM_HIB_GPIO24 0x00200000
#define PRCM_HIB_GPIO26 0x00400000
//*****************************************************************************
// Values that will be returned from PRCMSysResetCauseGet().
//*****************************************************************************
#define PRCM_POWER_ON 0x00000000
#define PRCM_LPDS_EXIT 0x00000001
#define PRCM_CORE_RESET 0x00000003
#define PRCM_MCU_RESET 0x00000004
#define PRCM_WDT_RESET 0x00000005
#define PRCM_SOC_RESET 0x00000006
#define PRCM_HIB_EXIT 0x00000007
//*****************************************************************************
// Values that can be passed to PRCMHibernateWakeupCauseGet().
//*****************************************************************************
#define PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK 0x00000002
#define PRCM_HIB_WAKEUP_CAUSE_GPIO 0x00000004
//*****************************************************************************
// Values that can be passed to PRCMSEnableInterrupt
//*****************************************************************************
#define PRCM_INT_SLOW_CLK_CTR 0x00004000
//*****************************************************************************
// Values that can be passed to PRCMPeripheralClkEnable(),
// PRCMPeripheralClkDisable(), PRCMPeripheralReset()
//*****************************************************************************
#define PRCM_CAMERA 0x00000000
#define PRCM_I2S 0x00000001
#define PRCM_SDHOST 0x00000002
#define PRCM_GSPI 0x00000003
#define PRCM_LSPI 0x00000004
#define PRCM_UDMA 0x00000005
#define PRCM_GPIOA0 0x00000006
#define PRCM_GPIOA1 0x00000007
#define PRCM_GPIOA2 0x00000008
#define PRCM_GPIOA3 0x00000009
#define PRCM_GPIOA4 0x0000000A
#define PRCM_WDT 0x0000000B
#define PRCM_UARTA0 0x0000000C
#define PRCM_UARTA1 0x0000000D
#define PRCM_TIMERA0 0x0000000E
#define PRCM_TIMERA1 0x0000000F
#define PRCM_TIMERA2 0x00000010
#define PRCM_TIMERA3 0x00000011
#define PRCM_DTHE 0x00000012
#define PRCM_SSPI 0x00000013
#define PRCM_I2CA0 0x00000014
// Note : PRCM_ADC is a dummy define for pinmux utility code generation
// PRCM_ADC should never be used in any user code.
#define PRCM_ADC 0x000000FF
//*****************************************************************************
// Values that can be passed to PRCMIORetEnable() and PRCMIORetDisable()
//*****************************************************************************
#define PRCM_IO_RET_GRP_0 0x00000001
#define PRCM_IO_RET_GRP_1 0x00000002
#define PRCM_IO_RET_GRP_2 0x00000004
#define PRCM_IO_RET_GRP_3 0x00000008
//*****************************************************************************
// Macros definig the device type
//*****************************************************************************
#define PRCM_DEV_TYPE_FLAG_R 0x00000001
#define PRCM_DEV_TYPE_FLAG_F 0x00000002
#define PRCM_DEV_TYPE_FLAG_Z 0x00000004
#define PRCM_DEV_TYPE_FLAG_SECURE 0x00000008
#define PRCM_DEV_TYPE_FLAG_PRE_PROD 0x00000010
#define PRCM_DEV_TYPE_FLAG_3200 0x00000020
#define PRCM_DEV_TYPE_FLAG_3220 0x00000040
#define PRCM_DEV_TYPE_FLAG_REV1 0x00010000
#define PRCM_DEV_TYPE_FLAG_REV2 0x00020000
//*****************************************************************************
// Pre-defined helper macros
//*****************************************************************************
#define PRCM_DEV_TYPE_PRE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3200| \
PRCM_DEV_TYPE_FLAG_R)
#define PRCM_DEV_TYPE_PRE_CC3200F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3200| \
PRCM_DEV_TYPE_FLAG_F)
#define PRCM_DEV_TYPE_PRE_CC3200Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3200| \
PRCM_DEV_TYPE_FLAG_Z)
#define PRCM_DEV_TYPE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3200| \
PRCM_DEV_TYPE_FLAG_R)
#define PRCM_DEV_TYPE_PRE_CC3220R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_R)
#define PRCM_DEV_TYPE_PRE_CC3220F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_F)
#define PRCM_DEV_TYPE_PRE_CC3220Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_Z)
#define PRCM_DEV_TYPE_CC3220R (PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_R)
#define PRCM_DEV_TYPE_PRE_CC3220RS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_R| \
PRCM_DEV_TYPE_FLAG_SECURE)
#define PRCM_DEV_TYPE_PRE_CC3220FS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_F| \
PRCM_DEV_TYPE_FLAG_SECURE)
#define PRCM_DEV_TYPE_PRE_CC3220ZS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_Z| \
PRCM_DEV_TYPE_FLAG_SECURE)
#define PRCM_DEV_TYPE_CC3220RS (PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_R| \
PRCM_DEV_TYPE_FLAG_SECURE)
#define PRCM_DEV_TYPE_CC3220FS (PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_F| \
PRCM_DEV_TYPE_FLAG_SECURE)
#define PRCM_DEV_TYPE_PRE_CC3220Z1 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_Z| \
PRCM_DEV_TYPE_FLAG_REV1)
#define PRCM_DEV_TYPE_PRE_CC3220Z2 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
PRCM_DEV_TYPE_FLAG_3220| \
PRCM_DEV_TYPE_FLAG_Z| \
PRCM_DEV_TYPE_FLAG_REV2)
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void PRCMMCUReset(tBoolean bIncludeSubsystem);
extern unsigned long PRCMSysResetCauseGet(void);
extern void PRCMPeripheralClkEnable(unsigned long ulPeripheral,
unsigned long ulClkFlags);
extern void PRCMPeripheralClkDisable(unsigned long ulPeripheral,
unsigned long ulClkFlags);
extern void PRCMPeripheralReset(unsigned long ulPeripheral);
extern tBoolean PRCMPeripheralStatusGet(unsigned long ulPeripheral);
extern void PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq);
extern unsigned long PRCMPeripheralClockGet(unsigned long ulPeripheral);
extern void PRCMSleepEnter(void);
extern void PRCMSRAMRetentionEnable(unsigned long ulSramColSel,
unsigned long ulFlags);
extern void PRCMSRAMRetentionDisable(unsigned long ulSramColSel,
unsigned long ulFlags);
extern void PRCMLPDSRestoreInfoSet(unsigned long ulRestoreSP,
unsigned long ulRestorePC);
extern void PRCMLPDSEnter(void);
extern void PRCMLPDSIntervalSet(unsigned long ulTicks);
extern void PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc);
extern unsigned long PRCMLPDSWakeupCauseGet(void);
extern void PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin,
unsigned long ulType);
extern void PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc);
extern void PRCMHibernateEnter(void);
extern void PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc);
extern unsigned long PRCMHibernateWakeupCauseGet(void);
extern void PRCMHibernateWakeUpGPIOSelect(unsigned long ulMultiGPIOBitMap,
unsigned long ulType);
extern void PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc);
extern void PRCMHibernateIntervalSet(unsigned long long ullTicks);
extern unsigned long long PRCMSlowClkCtrGet(void);
extern unsigned long long PRCMSlowClkCtrFastGet(void);
extern void PRCMSlowClkCtrMatchSet(unsigned long long ullTicks);
extern unsigned long long PRCMSlowClkCtrMatchGet(void);
extern void PRCMOCRRegisterWrite(unsigned char ucIndex,
unsigned long ulRegValue);
extern unsigned long PRCMOCRRegisterRead(unsigned char ucIndex);
extern void PRCMIntRegister(void (*pfnHandler)(void));
extern void PRCMIntUnregister(void);
extern void PRCMIntEnable(unsigned long ulIntFlags);
extern void PRCMIntDisable(unsigned long ulIntFlags);
extern unsigned long PRCMIntStatus(void);
extern void PRCMRTCInUseSet(void);
extern tBoolean PRCMRTCInUseGet(void);
extern void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec);
extern void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec);
extern void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec);
extern void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec);
extern void PRCMCC3200MCUInit(void);
extern unsigned long PRCMHIBRegRead(unsigned long ulRegAddr);
extern void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue);
extern unsigned long PRCMCameraFreqSet(unsigned char ulDivider,
unsigned char ulWidth);
extern void PRCMIORetentionEnable(unsigned long ulIORetGrpFlags);
extern void PRCMIORetentionDisable(unsigned long ulIORetGrpFlags);
extern unsigned long PRCMDeviceTypeGet(void);
extern void PRCMLPDSEnterKeepDebugIf(void);
extern void PRCMHibernateCycleTrigger(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __PRCM_H__

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom.h Executable file
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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_map.h Executable file
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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/rom_patch.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// rom_patch.h - Macros to facilitate patching driverlib API's in the ROM.
//
//
//*****************************************************************************
//
// List of API's in the ROM that need to be patched.
// For e.g. to patch ROM_UARTCharPut add the line #undef ROM_UARTCharPut
//*****************************************************************************
#ifndef __ROM_PATCH_H__
#define __ROM_PATCH_H__
#if defined(TARGET_IS_CC3200) || defined(USE_CC3200_ROM_DRV_API)
#undef ROM_ADCIntClear
#undef ROM_IntEnable
#undef ROM_IntDisable
#undef ROM_IntPendSet
#undef ROM_SDHostCardErrorMaskSet
#undef ROM_SDHostCardErrorMaskGet
#undef ROM_TimerConfigure
#undef ROM_TimerDMAEventSet
#undef ROM_TimerDMAEventGet
#undef ROM_SDHostDataNonBlockingWrite
#undef ROM_SDHostDataWrite
#undef ROM_SDHostDataRead
#undef ROM_SDHostDataNonBlockingRead
#undef ROM_PRCMSysResetCauseGet
#undef ROM_PRCMPeripheralClkEnable
#undef ROM_PRCMLPDSWakeUpGPIOSelect
#undef ROM_PRCMHibernateWakeupSourceEnable
#undef ROM_PRCMHibernateWakeupSourceDisable
#undef ROM_PRCMHibernateWakeupCauseGet
#undef ROM_PRCMHibernateIntervalSet
#undef ROM_PRCMHibernateWakeUpGPIOSelect
#undef ROM_PRCMHibernateEnter
#undef ROM_PRCMSlowClkCtrGet
#undef ROM_PRCMSlowClkCtrMatchSet
#undef ROM_PRCMSlowClkCtrMatchGet
#undef ROM_PRCMOCRRegisterWrite
#undef ROM_PRCMOCRRegisterRead
#undef ROM_PRCMIntEnable
#undef ROM_PRCMIntDisable
#undef ROM_PRCMRTCInUseSet
#undef ROM_PRCMRTCInUseGet
#undef ROM_PRCMRTCSet
#undef ROM_PRCMRTCGet
#undef ROM_PRCMRTCMatchSet
#undef ROM_PRCMRTCMatchGet
#undef ROM_PRCMPeripheralClkDisable
#undef ROM_PRCMPeripheralReset
#undef ROM_PRCMPeripheralStatusGet
#undef ROM_SPIConfigSetExpClk
#undef ROM_AESDataProcess
#undef ROM_DESDataProcess
#undef ROM_I2SEnable
#undef ROM_I2SConfigSetExpClk
#undef ROM_PinConfigSet
#undef ROM_PRCMLPDSEnter
#undef ROM_PRCMCC3200MCUInit
#undef ROM_SDHostIntStatus
#undef ROM_SDHostBlockCountSet
#undef ROM_UARTModemControlSet
#undef ROM_UARTModemControlClear
#undef ROM_CameraXClkSet
#undef ROM_PRCMMCUReset
#undef ROM_PRCMPeripheralClkEnable
#undef ROM_SPIDmaDisable
#endif
#if defined(USE_CC3220_ROM_DRV_API)
#undef ROM_PRCMDeviceTypeGet
#undef ROM_SDHostDataNonBlockingRead
#undef ROM_PRCMIORetentionEnable
#undef ROM_PRCMIORetentionDisable
#undef ROM_PRCMCC3200MCUInit
#undef ROM_SHAMD5ConfigSet
#undef ROM_SHAMD5HMACKeySet
#endif
#endif // __ROM_PATCH_H__

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/sdhost.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// sdhost.c
//
// Driver for the SD Host (SDHost) Interface
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup Secure_Digital_Host_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_mmchs.h"
#include "inc/hw_ints.h"
#include "inc/hw_apps_config.h"
#include "interrupt.h"
#include "sdhost.h"
//*****************************************************************************
//
//! Configures SDHost module.
//!
//! \param ulBase is the base address of SDHost module.
//!
//! This function configures the SDHost module, enabling internal sub-modules.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostInit(unsigned long ulBase)
{
//
// Assert module reset
//
HWREG(ulBase + MMCHS_O_SYSCONFIG) = 0x2;
//
// Wait for soft reset to complete
//
while( !(HWREG(ulBase + MMCHS_O_SYSCONFIG) & 0x1) )
{
}
//
// Assert internal reset
//
HWREG(ulBase + MMCHS_O_SYSCTL) |= (1 << 24);
//
// Wait for Reset to complete
//
while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (0x1 << 24)) )
{
}
//
// Set capability register, 1.8 and 3.0 V
//
HWREG(ulBase + MMCHS_O_CAPA) = (0x7 <<24);
//
// Select bus voltage, 3.0 V
//
HWREG(ulBase + MMCHS_O_HCTL) |= 0x7 << 9;
//
// Power up the bus
//
HWREG(ulBase + MMCHS_O_HCTL) |= 1 << 8;
//
// Wait for power on
//
while( !(HWREG(ulBase + MMCHS_O_HCTL) & (1<<8)) )
{
}
HWREG(ulBase + MMCHS_O_CON) |= 1 << 21;
//
// Un-mask all events
//
HWREG(ulBase + MMCHS_O_IE) = 0xFFFFFFFF;
}
//*****************************************************************************
//
//! Resets SDHost command line
//!
//! \param ulBase is the base address of SDHost module.
//!
//! This function assers a soft reset for the command line
//!
//! \return None.
//
//*****************************************************************************
void
SDHostCmdReset(unsigned long ulBase)
{
HWREG(ulBase + MMCHS_O_SYSCTL) |= 1 << 25;
while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (1 << 25)) )
{
}
}
//*****************************************************************************
//
//! Sends command over SDHost interface
//!
//! \param ulBase is the base address of SDHost module.
//! \param ulCmd is the command to send.
//! \param ulArg is the argument for the command.
//!
//! This function send command to the attached card over the SDHost interface.
//!
//! The \e ulCmd parameter can be one of \b SDHOST_CMD_0 to \b SDHOST_CMD_63.
//! It can be logically ORed with one or more of the following:
//! - \b SDHOST_MULTI_BLK for multi-block transfer
//! - \b SDHOST_WR_CMD if command is followed by write data
//! - \b SDHOST_RD_CMD if command is followed by read data
//! - \b SDHOST_DMA_EN if SDHost need to generate DMA request.
//! - \b SDHOST_RESP_LEN_136 if 136 bit response is expected
//! - \b SDHOST_RESP_LEN_48 if 48 bit response is expected
//! - \b SDHOST_RESP_LEN_48B if 48 bit response with busy bit is expected
//!
//! The parameter \e ulArg is the argument for the command
//!
//! \return Returns 0 on success, -1 otherwise.
//
//*****************************************************************************
long
SDHostCmdSend(unsigned long ulBase, unsigned long ulCmd, unsigned ulArg)
{
//
// Set Data Timeout
//
HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x000E0000;
//
// Check for cmd inhabit
//
if( (HWREG(ulBase + MMCHS_O_PSTATE) & 0x1))
{
return -1;
}
//
// Set the argument
//
HWREG(ulBase + MMCHS_O_ARG) = ulArg;
//
// Send the command
//
HWREG(ulBase + MMCHS_O_CMD) = ulCmd;
return 0;
}
//*****************************************************************************
//
//! Writes a data word into the SDHost write buffer.
//!
//! \param ulBase is the base address of SDHost module.
//! \param ulData is data word to be transfered.
//!
//! This function writes a single data word into the SDHost write buffer. The
//! function returns \b true if there was a space available in the buffer else
//! returns \b false.
//!
//! \return Return \b true on success, \b false otherwise.
//
//*****************************************************************************
tBoolean
SDHostDataNonBlockingWrite(unsigned long ulBase, unsigned long ulData)
{
//
// See if there is a space in the write buffer
//
if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) )
{
//
// Write the data into the buffer
//
HWREG(ulBase + MMCHS_O_DATA) = ulData;
//
// Success.
//
return(true);
}
else
{
//
// No free sapce, failure.
//
return(false);
}
}
//*****************************************************************************
//
//! Waits to write a data word into the SDHost write buffer.
//!
//! \param ulBase is the base address of SDHost module.
//! \param ulData is data word to be transfered.
//!
//! This function writes \e ulData into the SDHost write buffer. If there is no
//! space in the write buffer this function waits until there is a space
//! available before returning.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostDataWrite(unsigned long ulBase, unsigned long ulData)
{
//
// Wait until space is available
//
while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) )
{
}
//
// Write the data
//
HWREG(ulBase + MMCHS_O_DATA) = ulData;
}
//*****************************************************************************
//
//! Waits for a data word from the SDHost read buffer
//!
//! \param ulBase is the base address of SDHost module.
//! \param pulData is pointer to read data variable.
//!
//! This function reads a single data word from the SDHost read buffer. If there
//! is no data available in the buffer the function will wait until a data
//! word is received before returning.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostDataRead(unsigned long ulBase, unsigned long *pulData)
{
//
// Wait until data is available
//
while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<11)) )
{
}
//
// Read the data
//
*pulData = HWREG(ulBase + MMCHS_O_DATA);
}
//*****************************************************************************
//
//! Reads single data word from the SDHost read buffer
//!
//! \param ulBase is the base address of SDHost module.
//! \param pulData is pointer to read data variable.
//!
//! This function reads a data word from the SDHost read buffer. The
//! function returns \b true if there was data available in to buffer else
//! returns \b false.
//!
//! \return Return \b true on success, \b false otherwise.
//
//*****************************************************************************
tBoolean
SDHostDataNonBlockingRead(unsigned long ulBase, unsigned long *pulData)
{
//
// See if there is any data in the read buffer.
//
if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<<11)) )
{
//
// Read the data word.
//
*pulData = HWREG(ulBase + MMCHS_O_DATA);
//
// Success
//
return(true);
}
else
{
//
// No data available, failure.
//
return(false);
}
}
//*****************************************************************************
//
//! Registers the interrupt handler for SDHost interrupt
//!
//! \param ulBase is the base address of SDHost module
//! \param pfnHandler is a pointer to the function to be called when the
//! SDHost interrupt occurs.
//!
//! This function does the actual registering of the interrupt handler. This
//! function enables the global interrupt in the interrupt controller; specific
//! SDHost interrupts must be enabled via SDHostIntEnable(). It is the
//! interrupt handler's responsibility to clear the interrupt source.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Register the interrupt handler.
//
IntRegister(INT_MMCHS, pfnHandler);
//
// Enable the SDHost interrupt.
//
IntEnable(INT_MMCHS);
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for SDHost interrupt
//!
//! \param ulBase is the base address of SDHost module
//!
//! This function does the actual unregistering of the interrupt handler. It
//! clears the handler to be called when a SDHost interrupt occurs. This
//! function also masks off the interrupt in the interrupt controller so that
//! the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostIntUnregister(unsigned long ulBase)
{
//
// Disable the SDHost interrupt.
//
IntDisable(INT_MMCHS);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_MMCHS);
}
//*****************************************************************************
//
//! Enable individual interrupt source for the specified SDHost
//!
//! \param ulBase is the base address of SDHost module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated SDHost interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//! - \b SDHOST_INT_CC Command Complete interrupt
//! - \b SDHOST_INT_TC Transfer Complete interrupt
//! - \b SDHOST_INT_BWR Buffer Write Ready interrupt
//! - \b SDHOST_INT_BRR Buffer Read Ready interrupt
//! - \b SDHOST_INT_ERRI Error interrupt
//! - \b SDHOST_INT_CTO Command Timeout error interrupt
//! - \b SDHOST_INT_CEB Command End Bit error interrupt
//! - \b SDHOST_INT_DTO Data Timeout error interrupt
//! - \b SDHOST_INT_DCRC Data CRC error interrupt
//! - \b SDHOST_INT_DEB Data End Bit error
//! - \b SDHOST_INT_CERR Cart Status Error interrupt
//! - \b SDHOST_INT_BADA Bad Data error interrupt
//! - \b SDHOST_INT_DMARD Read DMA done interrupt
//! - \b SDHOST_INT_DMAWR Write DMA done interrupt
//!
//! Note that SDHOST_INT_ERRI can only be used with \sa SDHostIntStatus()
//! and is internally logical OR of all error status bits. Setting this bit
//! alone as \e ulIntFlags doesn't generates any interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags)
{
//
// Enable DMA done interrupts
//
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) =
(ulIntFlags >> 30);
//
// Enable the individual interrupt sources
//
HWREG(ulBase + MMCHS_O_ISE) |= (ulIntFlags & 0x3FFFFFFF);
}
//*****************************************************************************
//
//! Enable individual interrupt source for the specified SDHost
//!
//! \param ulBase is the base address of SDHost module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//!
//! This function disables the indicated SDHost interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to SDHostIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void
SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags)
{
//
// Disable DMA done interrupts
//
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) =
(ulIntFlags >> 30);
//
// Disable the individual interrupt sources
//
HWREG(ulBase + MMCHS_O_ISE) &= ~(ulIntFlags & 0x3FFFFFFF);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase is the base address of SDHost module.
//!
//! This function returns the interrupt status for the specified SDHost.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! values described in SDHostIntEnable().
//
//*****************************************************************************
unsigned long
SDHostIntStatus(unsigned long ulBase)
{
unsigned long ulIntStatus;
//
// Get DMA done interrupt status
//
ulIntStatus = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW);
ulIntStatus = (ulIntStatus << 30);
//
// Return the status of individual interrupt sources
//
ulIntStatus |= (HWREG(ulBase + MMCHS_O_STAT) & 0x3FFFFFFF);
return(ulIntStatus);
}
//*****************************************************************************
//
//! Clears the individual interrupt sources.
//!
//! \param ulBase is the base address of SDHost module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified SDHost interrupt sources are cleared, so that they no longer
//! assert. This function must be called in the interrupt handler to keep the
//! interrupt from being recognized again immediately upon exit.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to SDHostIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void
SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags)
{
//
// Clear DMA done interrupts
//
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) =
(ulIntFlags >> 30);
//
// Clear the individual interrupt sources
//
HWREG(ulBase + MMCHS_O_STAT) = (ulIntFlags & 0x3FFFFFFF);
}
//*****************************************************************************
//
//! Sets the card status error mask.
//!
//! \param ulBase is the base address of SDHost module
//! \param ulErrMask is the bit mask of card status errors to be enabled
//!
//! This function sets the card status error mask for response type R1, R1b,
//! R5, R5b and R6 response. The parameter \e ulErrMask is the bit mask of card
//! status errors to be enabled, if the corresponding bits in the 'card status'
//! field of a respose are set then the host controller indicates a card error
//! interrupt status. Only bits referenced as type E (error) in status field in
//! the response can set a card status error.
//!
//! \return None
//
//*****************************************************************************
void
SDHostCardErrorMaskSet(unsigned long ulBase, unsigned long ulErrMask)
{
//
// Set the card status error mask
//
HWREG(ulBase + MMCHS_O_CSRE) = ulErrMask;
}
//*****************************************************************************
//
//! Gets the card status error mask.
//!
//! \param ulBase is the base address of SDHost module
//!
//! This function gets the card status error mask for response type R1, R1b,
//! R5, R5b and R6 response.
//!
//! \return Returns the current card status error.
//
//*****************************************************************************
unsigned long
SDHostCardErrorMaskGet(unsigned long ulBase)
{
//
// Return the card status error mask
//
return(HWREG(ulBase + MMCHS_O_CSRE));
}
//*****************************************************************************
//
//! Sets the SD Card clock.
//!
//! \param ulBase is the base address of SDHost module
//! \param ulSDHostClk is the rate of clock supplied to SDHost module
//! \param ulCardClk is the required SD interface clock
//!
//! This function configures the SDHost interface to supply the specified clock
//! to the connected card.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk,
unsigned long ulCardClk)
{
unsigned long ulDiv;
//
// Disable card clock
//
HWREG(ulBase + MMCHS_O_SYSCTL) &= ~0x4;
//
// Enable internal clock
//
HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x1;
ulDiv = ((ulSDHostClk/ulCardClk) & 0x3FF);
//
// Set clock divider,
//
HWREG(ulBase + MMCHS_O_SYSCTL) = ((HWREG(ulBase + MMCHS_O_SYSCTL) &
~0x0000FFC0)| (ulDiv) << 6);
//
// Wait for clock to stablize
//
while( !(HWREG(ulBase + MMCHS_O_SYSCTL) & 0x2) )
{
}
//
// Enable card clock
//
HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x4;
}
//*****************************************************************************
//
//! Get the response for the last command.
//!
//! \param ulBase is the base address of SDHost module
//! \param ulRespnse is 128-bit response.
//!
//! This function gets the response from the SD card for the last command
//! send.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4])
{
//
// Read the responses.
//
ulRespnse[0] = HWREG(ulBase + MMCHS_O_RSP10);
ulRespnse[1] = HWREG(ulBase + MMCHS_O_RSP32);
ulRespnse[2] = HWREG(ulBase + MMCHS_O_RSP54);
ulRespnse[3] = HWREG(ulBase + MMCHS_O_RSP76);
}
//*****************************************************************************
//
//! Set the block size for data transfer
//!
//! \param ulBase is the base address of SDHost module
//! \param ulBlkSize is the transfer block size in bytes
//!
//! This function sets the block size the data transfer.
//!
//! The parameter \e ulBlkSize is size of each data block in bytes.
//! This should be in range 0 - 2^10.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize)
{
//
// Set the block size
//
HWREG(ulBase + MMCHS_O_BLK) = ((HWREG(ulBase + MMCHS_O_BLK) & 0x00000FFF)|
(ulBlkSize & 0xFFF));
}
//*****************************************************************************
//
//! Set the block size and count for data transfer
//!
//! \param ulBase is the base address of SDHost module
//! \param ulBlkCount is the number of blocks
//!
//! This function sets block count for the data transfer. This needs to be set
//! for each block transfer. \sa SDHostBlockSizeSet()
//!
//! \return None.
//
//*****************************************************************************
void
SDHostBlockCountSet(unsigned long ulBase, unsigned short ulBlkCount)
{
unsigned long ulRegVal;
//
// Read the current value
//
ulRegVal = HWREG(ulBase + MMCHS_O_BLK);
//
// Set the number of blocks
//
HWREG(ulBase + MMCHS_O_BLK) = ((ulRegVal & 0x0000FFFF)|
(ulBlkCount << 16));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// sdhost.h
//
// Defines and Macros for the SDHost.
//
//*****************************************************************************
#ifndef __SDHOST_H__
#define __SDHOST_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
//{
#endif
//*****************************************************************************
// Values that can be passed to SDHostRespGet().
//*****************************************************************************
#define SDHOST_RESP_10 0x00000003
#define SDHOST_RESP_32 0x00000002
#define SDHOST_RESP_54 0x00000001
#define SDHOST_RESP_76 0x00000000
//*****************************************************************************
// Values that can be passed to SDHostIntEnable(), SDHostIntDisable(),
// SDHostIntClear() ,and returned from SDHostIntStatus().
//*****************************************************************************
#define SDHOST_INT_CC 0x00000001
#define SDHOST_INT_TC 0x00000002
#define SDHOST_INT_BWR 0x00000010
#define SDHOST_INT_BRR 0x00000020
#define SDHOST_INT_ERRI 0x00008000
#define SDHOST_INT_CTO 0x00010000
#define SDHOST_INT_CEB 0x00040000
#define SDHOST_INT_DTO 0x00100000
#define SDHOST_INT_DCRC 0x00200000
#define SDHOST_INT_DEB 0x00400000
#define SDHOST_INT_CERR 0x10000000
#define SDHOST_INT_BADA 0x20000000
#define SDHOST_INT_DMARD 0x40000000
#define SDHOST_INT_DMAWR 0x80000000
//*****************************************************************************
// Values that can be passed to SDHostCmdSend().
//*****************************************************************************
#define SDHOST_CMD_0 0x00000000
#define SDHOST_CMD_1 0x01000000
#define SDHOST_CMD_2 0x02000000
#define SDHOST_CMD_3 0x03000000
#define SDHOST_CMD_4 0x04000000
#define SDHOST_CMD_5 0x05000000
#define SDHOST_CMD_6 0x06000000
#define SDHOST_CMD_7 0x07000000
#define SDHOST_CMD_8 0x08000000
#define SDHOST_CMD_9 0x09000000
#define SDHOST_CMD_10 0x0A000000
#define SDHOST_CMD_11 0x0B000000
#define SDHOST_CMD_12 0x0C000000
#define SDHOST_CMD_13 0x0D000000
#define SDHOST_CMD_14 0x0E000000
#define SDHOST_CMD_15 0x0F000000
#define SDHOST_CMD_16 0x10000000
#define SDHOST_CMD_17 0x11000000
#define SDHOST_CMD_18 0x12000000
#define SDHOST_CMD_19 0x13000000
#define SDHOST_CMD_20 0x14000000
#define SDHOST_CMD_21 0x15000000
#define SDHOST_CMD_22 0x16000000
#define SDHOST_CMD_23 0x17000000
#define SDHOST_CMD_24 0x18000000
#define SDHOST_CMD_25 0x19000000
#define SDHOST_CMD_26 0x1A000000
#define SDHOST_CMD_27 0x1B000000
#define SDHOST_CMD_28 0x1C000000
#define SDHOST_CMD_29 0x1D000000
#define SDHOST_CMD_30 0x1E000000
#define SDHOST_CMD_31 0x1F000000
#define SDHOST_CMD_32 0x20000000
#define SDHOST_CMD_33 0x21000000
#define SDHOST_CMD_34 0x22000000
#define SDHOST_CMD_35 0x23000000
#define SDHOST_CMD_36 0x24000000
#define SDHOST_CMD_37 0x25000000
#define SDHOST_CMD_38 0x26000000
#define SDHOST_CMD_39 0x27000000
#define SDHOST_CMD_40 0x28000000
#define SDHOST_CMD_41 0x29000000
#define SDHOST_CMD_42 0x2A000000
#define SDHOST_CMD_43 0x2B000000
#define SDHOST_CMD_44 0x2C000000
#define SDHOST_CMD_45 0x2D000000
#define SDHOST_CMD_46 0x2E000000
#define SDHOST_CMD_47 0x2F000000
#define SDHOST_CMD_48 0x30000000
#define SDHOST_CMD_49 0x31000000
#define SDHOST_CMD_50 0x32000000
#define SDHOST_CMD_51 0x33000000
#define SDHOST_CMD_52 0x34000000
#define SDHOST_CMD_53 0x35000000
#define SDHOST_CMD_54 0x36000000
#define SDHOST_CMD_55 0x37000000
#define SDHOST_CMD_56 0x38000000
#define SDHOST_CMD_57 0x39000000
#define SDHOST_CMD_58 0x3A000000
#define SDHOST_CMD_59 0x3B000000
#define SDHOST_CMD_60 0x3C000000
#define SDHOST_CMD_61 0x3D000000
#define SDHOST_CMD_62 0x3E000000
#define SDHOST_CMD_63 0x3F000000
//*****************************************************************************
// Values that can be logically ORed with ulCmd parameter for SDHostCmdSend().
//*****************************************************************************
#define SDHOST_MULTI_BLK 0x00000022
#define SDHOST_DMA_EN 0x00000001
#define SDHOST_WR_CMD 0x00200000
#define SDHOST_RD_CMD 0x00200010
#define SDHOST_RESP_LEN_136 0x00010000
#define SDHOST_RESP_LEN_48 0x00020000
#define SDHOST_RESP_LEN_48B 0x00030000
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void SDHostCmdReset(unsigned long ulBase);
extern void SDHostInit(unsigned long ulBase);
extern long SDHostCmdSend(unsigned long ulBase,unsigned long ulCmd,
unsigned ulArg);
extern void SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void SDHostIntUnregister(unsigned long ulBase);
extern void SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags);
extern void SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags);
extern unsigned long SDHostIntStatus(unsigned long ulBase);
extern void SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags);
extern void SDHostCardErrorMaskSet(unsigned long ulBase,
unsigned long ulErrMask);
extern unsigned long SDHostCardErrorMaskGet(unsigned long ulBase);
extern void SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk,
unsigned long ulCardClk);
extern void SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4]);
extern void SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize);
extern void SDHostBlockCountSet(unsigned long ulBase,
unsigned short ulBlkCount);
extern tBoolean SDHostDataNonBlockingWrite(unsigned long ulBase,
unsigned long ulData);
extern tBoolean SDHostDataNonBlockingRead(unsigned long ulBase,
unsigned long *pulData);
extern void SDHostDataWrite(unsigned long ulBase, unsigned long ulData);
extern void SDHostDataRead(unsigned long ulBase, unsigned long *ulData);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
//}
#endif
#endif // __SDHOST_H__

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/shamd5.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// shamd5.h
//
// Defines and Macros for the SHA/MD5.
//
//*****************************************************************************
#ifndef __DRIVERLIB_SHAMD5_H__
#define __DRIVERLIB_SHAMD5_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the algorithm in use in the
// SHA/MD5 module.
//
//*****************************************************************************
#define SHAMD5_ALGO_MD5 0x00000000 // MD5
#define SHAMD5_ALGO_SHA1 0x00000002 // SHA-1
#define SHAMD5_ALGO_SHA224 0x00000004 // SHA-224
#define SHAMD5_ALGO_SHA256 0x00000006 // SHA-256
//*****************************************************************************
//
// The following definitions represent the number of bits to shift in order
// to configure the differnet bit fields in the SHAMD5_O_MODE register.
//
//*****************************************************************************
#define ALGO_CONSTANT_SHIFT 3
#define CLOSE_HASH_SHIFT 4
#define HMAC_KEY_PROC_SHIFT 5
#define HMAC_OUTER_HASH_SHIFT 7
//*****************************************************************************
//
// The following defines are used to represent the different interrupt sources
// in SHAMD5IntEnable(), SHAMD5IntDisable(), SHAMD5GetIntStatus(), and
// SHAMD5BlockOnIntStatus() functions.
//
//*****************************************************************************
#define SHAMD5_INT_CONTEXT_READY 0x00000008
#define SHAMD5_INT_PARTHASH_READY 0x00000004
#define SHAMD5_INT_INPUT_READY 0x00000002
#define SHAMD5_INT_OUTPUT_READY 0x00000001
#define SHAMD5_INT_DMA_CONTEXT_IN 0x00010000
#define SHAMD5_INT_DMA_DATA_IN 0x00020000
#define SHAMD5_INT_DMA_CONTEXT_OUT 0x00040000
//*****************************************************************************
//
// Function prototypes
//
//*****************************************************************************
extern void SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32CryptoMode, uint8_t algConstFlag, uint8_t closeHashFlag,
uint8_t HMACKeyFlag, uint8_t HMACOuterHashFlag);
extern bool SHAMD5DataProcess(uint32_t ui32Base, uint8_t *pui8DataSrc,
uint32_t ui32DataLength, uint8_t *pui8HashResult);
extern void SHAMD5DataWrite(uint32_t ui32Base, uint8_t *pui8Src);
extern bool SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src);
extern void SHAMD5DMADisable(uint32_t ui32Base);
extern void SHAMD5DMAEnable(uint32_t ui32Base);
extern void SHAMD5DataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
extern void SHAMD5HMACKeySet(uint32_t ui32Base, uint8_t *pui8Src);
extern void SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint8_t *pui8Key,
uint8_t *pui8PPKey);
extern void SHAMD5HMACPPKeySet(uint32_t ui32Base, uint8_t *pui8Src);
extern bool SHAMD5HMACProcess(uint32_t ui32Base, uint8_t *pui8DataSrc,
uint32_t ui32DataLength, uint8_t *pui8HashResult);
extern void SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SHAMD5IntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
extern uint32_t SHAMD5IntStatus(uint32_t ui32Base, bool bMasked);
extern void SHAMD5IntUnregister(uint32_t ui32Base);
extern void SHAMD5ResultRead(uint32_t ui32Base, uint8_t *pui8Dest);
extern void SHAMD5ResultWrite(uint32_t ui32Base, uint8_t *pui8Src);
extern void SHAMD5ReadDigestCount(uint32_t ui32Base, uint32_t *count);
extern void SHAMD5WriteDigestCount(uint32_t ui32Base, uint32_t count);
extern void SHAMD5DataWriteMultiple(uint32_t ui32Base, uint8_t *pui8DataSrc, uint32_t ui32DataLength);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_SHAMD5_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// systick.c
//
// Driver for the SysTick timer in NVIC.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup systick_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "debug.h"
#include "interrupt.h"
#include "systick.h"
//*****************************************************************************
//
//! Enables the SysTick counter.
//!
//! This function starts the SysTick counter. If an interrupt handler has been
//! registered, it is called when the SysTick counter rolls over.
//!
//! \note Calling this function causes the SysTick counter to (re)commence
//! counting from its current value. The counter is not automatically reloaded
//! with the period as specified in a previous call to SysTickPeriodSet(). If
//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
//! written to force the reload. Any write to this register clears the SysTick
//! counter to 0 and causes a reload with the supplied period on the next
//! clock.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickEnable(void)
{
//
// Enable SysTick.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
}
//*****************************************************************************
//
//! Disables the SysTick counter.
//!
//! This function stops the SysTick counter. If an interrupt handler has been
//! registered, it is not called until SysTick is restarted.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickDisable(void)
{
//
// Disable SysTick.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the SysTick interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the
//! SysTick interrupt occurs.
//!
//! This function registers the handler to be called when a SysTick interrupt
//! occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(FAULT_SYSTICK, pfnHandler);
//
// Enable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for the SysTick interrupt.
//!
//! This function unregisters the handler to be called when a SysTick interrupt
//! occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntUnregister(void)
{
//
// Disable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
//
// Unregister the interrupt handler.
//
IntUnregister(FAULT_SYSTICK);
}
//*****************************************************************************
//
//! Enables the SysTick interrupt.
//!
//! This function enables the SysTick interrupt, allowing it to be
//! reflected to the processor.
//!
//! \note The SysTick interrupt handler is not required to clear the SysTick
//! interrupt source because it is cleared automatically by the NVIC when the
//! interrupt handler is called.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntEnable(void)
{
//
// Enable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
//*****************************************************************************
//
//! Disables the SysTick interrupt.
//!
//! This function disables the SysTick interrupt, preventing it from being
//! reflected to the processor.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntDisable(void)
{
//
// Disable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
}
//*****************************************************************************
//
//! Sets the period of the SysTick counter.
//!
//! \param ulPeriod is the number of clock ticks in each period of the SysTick
//! counter and must be between 1 and 16,777,216, inclusive.
//!
//! This function sets the rate at which the SysTick counter wraps, which
//! equates to the number of processor clocks between interrupts.
//!
//! \note Calling this function does not cause the SysTick counter to reload
//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
//! register must be written. Any write to this register clears the SysTick
//! counter to 0 and causes a reload with the \e ulPeriod supplied here on
//! the next clock after SysTick is enabled.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickPeriodSet(unsigned long ulPeriod)
{
//
// Check the arguments.
//
ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216));
//
// Set the period of the SysTick counter.
//
HWREG(NVIC_ST_RELOAD) = ulPeriod - 1;
}
//*****************************************************************************
//
//! Gets the period of the SysTick counter.
//!
//! This function returns the rate at which the SysTick counter wraps, which
//! equates to the number of processor clocks between interrupts.
//!
//! \return Returns the period of the SysTick counter.
//
//*****************************************************************************
unsigned long
SysTickPeriodGet(void)
{
//
// Return the period of the SysTick counter.
//
return(HWREG(NVIC_ST_RELOAD) + 1);
}
//*****************************************************************************
//
//! Gets the current value of the SysTick counter.
//!
//! This function returns the current value of the SysTick counter, which is
//! a value between the period - 1 and zero, inclusive.
//!
//! \return Returns the current value of the SysTick counter.
//
//*****************************************************************************
unsigned long
SysTickValueGet(void)
{
//
// Return the current value of the SysTick counter.
//
return(HWREG(NVIC_ST_CURRENT));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// systick.h
//
// Prototypes for the SysTick driver.
//
//*****************************************************************************
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SysTickEnable(void);
extern void SysTickDisable(void);
extern void SysTickIntRegister(void (*pfnHandler)(void));
extern void SysTickIntUnregister(void);
extern void SysTickIntEnable(void);
extern void SysTickIntDisable(void);
extern void SysTickPeriodSet(unsigned long ulPeriod);
extern unsigned long SysTickPeriodGet(void);
extern unsigned long SysTickValueGet(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSTICK_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// aes.h
//
// Defines and Macros for the AES module.
//
//*****************************************************************************
#ifndef __DRIVERLIB_AES_H__
#define __DRIVERLIB_AES_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the operation direction in the
// ui32Config argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_DIR_ENCRYPT 0x00000004
#define AES_CFG_DIR_DECRYPT 0x00000000
//*****************************************************************************
//
// The following defines are used to specify the key size in the ui32Config
// argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_KEY_SIZE_128BIT 0x00000008
#define AES_CFG_KEY_SIZE_192BIT 0x00000010
#define AES_CFG_KEY_SIZE_256BIT 0x00000018
//*****************************************************************************
//
// The following defines are used to specify the mode of operation in the
// ui32Config argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_MODE_M 0x2007fe60
#define AES_CFG_MODE_ECB 0x00000000
#define AES_CFG_MODE_CBC 0x00000020
#define AES_CFG_MODE_CTR 0x00000040
#define AES_CFG_MODE_ICM 0x00000200
#define AES_CFG_MODE_CFB 0x00000400
#define AES_CFG_MODE_XTS_TWEAKJL \
0x00000800
#define AES_CFG_MODE_XTS_K2IJL \
0x00001000
#define AES_CFG_MODE_XTS_K2ILJ0 \
0x00001800
#define AES_CFG_MODE_F8 0x00002000
#define AES_CFG_MODE_F9 0x20004000
#define AES_CFG_MODE_CBCMAC 0x20008000
#define AES_CFG_MODE_GCM_HLY0ZERO \
0x20010040
#define AES_CFG_MODE_GCM_HLY0CALC \
0x20020040
#define AES_CFG_MODE_GCM_HY0CALC \
0x20030040
#define AES_CFG_MODE_CCM 0x20040040
//*****************************************************************************
//
// The following defines are used to specify the counter width in the
// ui32Config argument in the AESConfig function. It is only required to
// be defined when using CTR, CCM, or GCM modes. Only one length is permitted.
//
//*****************************************************************************
#define AES_CFG_CTR_WIDTH_32 0x00000000
#define AES_CFG_CTR_WIDTH_64 0x00000080
#define AES_CFG_CTR_WIDTH_96 0x00000100
#define AES_CFG_CTR_WIDTH_128 0x00000180
//*****************************************************************************
//
// The following defines are used to define the width of the length field for
// CCM operation through the ui32Config argument in the AESConfig function.
// This value is also known as L. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_CCM_L_2 0x00080000
#define AES_CFG_CCM_L_4 0x00180000
#define AES_CFG_CCM_L_8 0x00380000
//*****************************************************************************
//
// The following defines are used to define the length of the authentication
// field for CCM operations through the ui32Config argument in the AESConfig
// function. This value is also known as M. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_CCM_M_4 0x00400000
#define AES_CFG_CCM_M_6 0x00800000
#define AES_CFG_CCM_M_8 0x00c00000
#define AES_CFG_CCM_M_10 0x01000000
#define AES_CFG_CCM_M_12 0x01400000
#define AES_CFG_CCM_M_14 0x01800000
#define AES_CFG_CCM_M_16 0x01c00000
//*****************************************************************************
//
// Interrupt flags for use with the AESIntEnable, AESIntDisable, and
// AESIntStatus functions.
//
//*****************************************************************************
#define AES_INT_CONTEXT_IN 0x00000001
#define AES_INT_CONTEXT_OUT 0x00000008
#define AES_INT_DATA_IN 0x00000002
#define AES_INT_DATA_OUT 0x00000004
#define AES_INT_DMA_CONTEXT_IN 0x00010000
#define AES_INT_DMA_CONTEXT_OUT 0x00020000
#define AES_INT_DMA_DATA_IN 0x00040000
#define AES_INT_DMA_DATA_OUT 0x00080000
//*****************************************************************************
//
// Defines used when enabling and disabling DMA requests in the
// AESEnableDMA and AESDisableDMA functions.
//
//*****************************************************************************
#define AES_DMA_DATA_IN 0x00000040
#define AES_DMA_DATA_OUT 0x00000020
#define AES_DMA_CONTEXT_IN 0x00000080
#define AES_DMA_CONTEXT_OUT 0x00000100
//*****************************************************************************
//
// Function prototypes.
//
//*****************************************************************************
extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key,
uint32_t ui32Keysize);
extern void AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key,
uint32_t ui32Keysize);
extern void AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key);
extern void AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata);
extern void AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata);
extern void AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData);
extern void AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length);
extern void AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest,
uint8_t ui8Length);
extern void AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest,
uint8_t ui8Length);
extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t ui8Length);
extern void AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t ui8Length);
extern bool AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t *pui8Dest,
uint32_t ui32Length);
extern bool AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src,
uint32_t ui32Length,
uint8_t *pui8Tag);
extern bool AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t *pui8Dest, uint32_t ui32Length,
uint8_t *pui8AuthSrc, uint32_t ui32AuthLength,
uint8_t *pui8Tag);
extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked);
extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
extern void AESIntUnregister(uint32_t ui32Base);
extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_AES_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// des.c
//
// Driver for the DES data transformation.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup DES_Data_Encryption_Standard_api
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_des.h"
#include "inc/hw_dthe.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "debug.h"
#include "ti_des.h"
#include "interrupt.h"
//*****************************************************************************
//
//! Configures the DES module for operation.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32Config is the configuration of the DES module.
//!
//! This function configures the DES module for operation.
//!
//! The \e ui32Config parameter is a bit-wise OR of a number of configuration
//! flags. The valid flags are grouped below based on their function.
//!
//! The direction of the operation is specified with one of the following two
//! flags. Only one is permitted.
//!
//! - \b DES_CFG_DIR_ENCRYPT - Encryption
//! - \b DES_CFG_DIR_DECRYPT - Decryption
//!
//! The operational mode of the DES engine is specified with one of the
//! following flags. Only one is permitted.
//!
//! - \b DES_CFG_MODE_ECB - Electronic Codebook Mode
//! - \b DES_CFG_MODE_CBC - Cipher-Block Chaining Mode
//! - \b DES_CFG_MODE_CFB - Cipher Feedback Mode
//!
//! The selection of single DES or triple DES is specified with one of the
//! following two flags. Only one is permitted.
//!
//! - \b DES_CFG_SINGLE - Single DES
//! - \b DES_CFG_TRIPLE - Triple DES
//!
//! \return None.
//
//*****************************************************************************
void
DESConfigSet(uint32_t ui32Base, uint32_t ui32Config)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Backup the save context field.
//
ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT);
//
// Write the control register.
//
HWREG(ui32Base + DES_O_CTRL) = ui32Config;
}
//*****************************************************************************
//
//! Sets the key used for DES operations.
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8Key is a pointer to an array that holds the key
//!
//! This function sets the key used for DES operations.
//!
//! \e pui8Key should be 64 bits long (2 words) if single DES is being used or
//! 192 bits (6 words) if triple DES is being used.
//!
//! \return None.
//
//*****************************************************************************
void
DESKeySet(uint32_t ui32Base, uint8_t *pui8Key)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Write the first part of the key.
//
HWREG(ui32Base + DES_O_KEY1_L) = * ((uint32_t *)(pui8Key + 0));
HWREG(ui32Base + DES_O_KEY1_H) = * ((uint32_t *)(pui8Key + 4));
//
// If we are performing triple DES, then write the key registers for
// the second and third rounds.
//
if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE)
{
HWREG(ui32Base + DES_O_KEY2_L) = * ((uint32_t *)(pui8Key + 8));
HWREG(ui32Base + DES_O_KEY2_H) = * ((uint32_t *)(pui8Key + 12));
HWREG(ui32Base + DES_O_KEY3_L) = * ((uint32_t *)(pui8Key + 16));
HWREG(ui32Base + DES_O_KEY3_H) = * ((uint32_t *)(pui8Key + 20));
}
}
//*****************************************************************************
//
//! Sets the initialization vector in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8IVdata is a pointer to an array of 64 bits (2 words) of data to
//! be written into the initialization vectors registers.
//!
//! This function sets the initialization vector in the DES module. It returns
//! true if the registers were successfully written. If the context registers
//! cannot be written at the time the function was called, then false is
//! returned.
//!
//! \return True or false.
//
//*****************************************************************************
bool
DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Check to see if context registers can be overwritten. If not, return
// false.
//
if((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT) == 0)
{
return(false);
}
//
// Write the initialization vector registers.
//
HWREG(ui32Base + DES_O_IV_L) = *((uint32_t *) (pui8IVdata + 0));
HWREG(ui32Base + DES_O_IV_H) = *((uint32_t *) (pui8IVdata + 4));
//
// Return true to indicate the write was successful.
//
return(true);
}
//*****************************************************************************
//
//! Sets the crytographic data length in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32Length is the length of the data in bytes.
//!
//! This function writes the cryptographic data length into the DES module.
//! When this register is written, the engine is triggersed to start using
//! this context.
//!
//! \note Data lengths up to (2^32 - 1) bytes are allowed.
//!
//! \return None.
//
//*****************************************************************************
void
DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Write the length register.
//
HWREG(ui32Base + DES_O_LENGTH) = ui32Length;
}
//*****************************************************************************
//
//! Reads plaintext/ciphertext from data registers without blocking
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8Dest is a pointer to an array of 2 words.
//! \param ui8Length the length can be from 1 to 8
//!
//! This function returns true if the data was ready when the function was
//! called. If the data was not ready, false is returned.
//!
//! \return True or false.
//
//*****************************************************************************
bool
DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)
{
volatile uint32_t pui32Dest[2];
uint8_t ui8BytCnt;
uint8_t *pui8DestTemp;
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
if((ui8Length == 0)||(ui8Length>8))
{
return(false);
}
//
// Check to see if the data is ready to be read.
//
if((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
{
return(false);
}
//
// Read two words of data from the data registers.
//
pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L);
pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H);
//
//Copy the data to a block memory
//
pui8DestTemp = (uint8_t *)pui32Dest;
for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
{
*(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);
}
//
// Return true to indicate a successful write.
//
return(true);
}
//*****************************************************************************
//
//! Reads plaintext/ciphertext from data registers with blocking.
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8Dest is a pointer to an array of bytes.
//! \param ui8Length the length can be from 1 to 8
//!
//! This function waits until the DES module is finished and encrypted or
//! decrypted data is ready. The output data is then stored in the pui8Dest
//! array.
//!
//! \return None
//
//*****************************************************************************
void
DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)
{
volatile uint32_t pui32Dest[2];
uint8_t ui8BytCnt;
uint8_t *pui8DestTemp;
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
if((ui8Length == 0)||(ui8Length>8))
{
return;
}
//
// Wait for data output to be ready.
//
while((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_OUTPUT_READY) == 0)
{
}
//
// Read two words of data from the data registers.
//
pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L);
pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H);
//
//Copy the data to a block memory
//
pui8DestTemp = (uint8_t *)pui32Dest;
for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
{
*(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);
}
}
//*****************************************************************************
//
//! Writes plaintext/ciphertext to data registers without blocking
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8Src is a pointer to an array of 2 words.
//! \param ui8Length the length can be from 1 to 8
//!
//! This function returns false if the DES module is not ready to accept
//! data. It returns true if the data was written successfully.
//!
//! \return true or false.
//
//*****************************************************************************
bool
DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)
{
volatile uint32_t pui32Src[2]={0,0};
uint8_t ui8BytCnt;
uint8_t *pui8SrcTemp;
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
if((ui8Length == 0)||(ui8Length>8))
{
return(false);
}
//
// Check if the DES module is ready to encrypt or decrypt data. If it
// is not, return false.
//
if(!(DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))))
{
return(false);
}
//
// Copy the data to a block memory
//
pui8SrcTemp = (uint8_t *)pui32Src;
for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
{
*(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);
}
//
// Write the data.
//
HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0];
HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1];
//
// Return true to indicate a successful write.
//
return(true);
}
//*****************************************************************************
//
//! Writes plaintext/ciphertext to data registers without blocking
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8Src is a pointer to an array of bytes.
//! \param ui8Length the length can be from 1 to 8
//!
//! This function waits until the DES module is ready before writing the
//! data contained in the pui8Src array.
//!
//! \return None.
//
//*****************************************************************************
void
DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)
{
volatile uint32_t pui32Src[2]={0,0};
uint8_t ui8BytCnt;
uint8_t *pui8SrcTemp;
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
if((ui8Length == 0)||(ui8Length>8))
{
return;
}
//
// Wait for the input ready bit to go high.
//
while(((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_INPUT_READY)) == 0)
{
}
//
//Copy the data to a block memory
//
pui8SrcTemp = (uint8_t *)pui32Src;
for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
{
*(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);
}
//
// Write the data.
//
HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0];
HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1];
}
//*****************************************************************************
//
//! Processes blocks of data through the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8Src is a pointer to an array of words that contains the
//! source data for processing.
//! \param pui8Dest is a pointer to an array of words consisting of the
//! processed data.
//! \param ui32Length is the length of the cryptographic data in bytes.
//! It must be a multiple of eight.
//!
//! This function takes the data contained in the pui8Src array and processes
//! it using the DES engine. The resulting data is stored in the
//! pui8Dest array. The function blocks until all of the data has been
//! processed. If processing is successful, the function returns true.
//!
//! \note This functions assumes that the DES module has been configured,
//! and initialization values and keys have been written.
//!
//! \return true or false.
//
//*****************************************************************************
bool
DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest,
uint32_t ui32Length)
{
uint32_t ui32Count, ui32BlkCount, ui32ByteCount;
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
ASSERT((ui32Length % 8) == 0);
//
// Write the length register first. This triggers the engine to start
// using this context.
//
HWREG(ui32Base + DES_O_LENGTH) = ui32Length;
//
// Now loop until the blocks are written.
//
ui32BlkCount = ui32Length/8;
for(ui32Count = 0; ui32Count <ui32BlkCount; ui32Count ++)
{
//
// Check if the input ready is fine
//
while((DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
{
}
//
// Write the data registers.
//
DESDataWriteNonBlocking(ui32Base, pui8Src + ui32Count*8 ,8);
//
// Wait for the output ready
//
while((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
{
}
//
// Read the data registers.
//
DESDataReadNonBlocking(ui32Base, pui8Dest + ui32Count*8 ,8);
}
//
//Now handle the residue bytes
//
ui32ByteCount = ui32Length%8;
if(ui32ByteCount)
{
//
// Check if the input ready is fine
//
while((DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
{
}
//
// Write the data registers.
//
DESDataWriteNonBlocking(ui32Base, pui8Src + (8*ui32BlkCount) ,
ui32ByteCount);
//
// Wait for the output ready
//
while((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
{
}
//
// Read the data registers.
//
DESDataReadNonBlocking(ui32Base, pui8Dest + (8*ui32BlkCount) ,
ui32ByteCount);
}
//
// Return true to indicate the process was successful.
//
return(true);
}
//*****************************************************************************
//
//! Returns the current interrupt status of the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This function gets the current interrupt status of the DES module.
//! The value returned is a logical OR of the following values:
//!
//! - \b DES_INT_CONTEXT_IN - Context interrupt
//! - \b DES_INT_DATA_IN - Data input interrupt
//! - \b DES_INT_DATA_OUT_INT - Data output interrupt
//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt
//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt
//!
//! \return A bit mask of the current interrupt status.
//
//*****************************************************************************
uint32_t
DESIntStatus(uint32_t ui32Base, bool bMasked)
{
uint32_t ui32IntStatus;
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Read the status register and return the value.
//
if(bMasked)
{
ui32IntStatus = HWREG(ui32Base + DES_O_IRQSTATUS);
ui32IntStatus &= HWREG(ui32Base + DES_O_IRQENABLE);
ui32IntStatus |= ((HWREG(DTHE_BASE + DTHE_O_DES_MIS) & 0x7) << 16);
return(ui32IntStatus);
}
else
{
ui32IntStatus = HWREG(ui32Base + DES_O_IRQSTATUS);
ui32IntStatus |= ((HWREG(DTHE_BASE + DTHE_O_DES_MIS) & 0xD) << 16);
return(ui32IntStatus);
}
}
//*****************************************************************************
//
//! Enables interrupts in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32IntFlags is a bit mask of the interrupts to be enabled.
//!
//! \e ui32IntFlags should be a logical OR of one or more of the following
//! values:
//!
//! - \b DES_INT_CONTEXT_IN - Context interrupt
//! - \b DES_INT_DATA_IN - Data input interrupt
//! - \b DES_INT_DATA_OUT - Data output interrupt
//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt
//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt
//!
//! \return None.
//
//*****************************************************************************
void
DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) ||
(ui32IntFlags & DES_INT_DATA_IN) ||
(ui32IntFlags & DES_INT_DATA_OUT) ||
(ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
(ui32IntFlags & DES_INT_DMA_DATA_IN) ||
(ui32IntFlags & DES_INT_DMA_DATA_OUT));
//
// Enable the interrupts from the flags.
//
HWREG(DTHE_BASE + DTHE_O_DES_IM) &= ~((ui32IntFlags & 0x00070000) >> 16);
HWREG(ui32Base + DES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;
}
//*****************************************************************************
//
//! Disables interrupts in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32IntFlags is a bit mask of the interrupts to be disabled.
//!
//! This function disables interrupt sources in the DES module.
//! \e ui32IntFlags should be a logical OR of one or more of the following
//! values:
//!
//! - \b DES_INT_CONTEXT_IN - Context interrupt
//! - \b DES_INT_DATA_IN - Data input interrupt
//! - \b DES_INT_DATA_OUT - Data output interrupt
//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt
//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt
//!
//! \return None.
//
//*****************************************************************************
void
DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) ||
(ui32IntFlags & DES_INT_DATA_IN) ||
(ui32IntFlags & DES_INT_DATA_OUT) ||
(ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
(ui32IntFlags & DES_INT_DMA_DATA_IN) ||
(ui32IntFlags & DES_INT_DMA_DATA_OUT));
//
// Clear the interrupts from the flags.
//
HWREG(DTHE_BASE + DTHE_O_AES_IM) |= ((ui32IntFlags & 0x00070000) >> 16);
HWREG(ui32Base + DES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);
}
//*****************************************************************************
//
//! Clears interrupts in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32IntFlags is a bit mask of the interrupts to be disabled.
//!
//! This function disables interrupt sources in the DES module.
//! \e ui32IntFlags should be a logical OR of one or more of the following
//! values:
//!
//! - \b DES_INT_DMA_CONTEXT_IN - Context interrupt
//! - \b DES_INT_DMA_DATA_IN - Data input interrupt
//! - \b DES_INT_DMA_DATA_OUT - Data output interrupt
//!
//! \note The DMA done interrupts are the only interrupts that can be cleared.
//! The remaining interrupts can be disabled instead using DESIntDisable().
//!
//! \return None.
//
//*****************************************************************************
void
DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
ASSERT((ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
(ui32IntFlags & DES_INT_DMA_DATA_IN) ||
(ui32IntFlags & DES_INT_DMA_DATA_OUT));
HWREG(DTHE_BASE + DTHE_O_DES_IC) = ((ui32IntFlags & 0x00070000) >> 16);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param pfnHandler is a pointer to the function to be called when the
//! enabled DES interrupts occur.
//!
//! This function registers the interrupt handler in the interrupt vector
//! table, and enables DES interrupts on the interrupt controller; specific DES
//! interrupt sources must be enabled using DESIntEnable(). The interrupt
//! handler being registered must clear the source of the interrupt using
//! DESIntClear().
//!
//! If the application is using a static interrupt vector table stored in
//! flash, then it is not necessary to register the interrupt handler this way.
//! Instead, IntEnable() should be used to enable DES interrupts on the
//! interrupt controller.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Register the interrupt handler.
//
IntRegister(INT_DES, pfnHandler);
//
// Enable the interrupt.
//
IntEnable(INT_DES);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//!
//! This function unregisters the previously registered interrupt handler and
//! disables the interrupt in the interrupt controller.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
DESIntUnregister(uint32_t ui32Base)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Disable the interrupt.
//
IntDisable(INT_DES);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_DES);
}
//*****************************************************************************
//
//! Enables DMA request sources in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32Flags is a bit mask of the DMA requests to be enabled.
//!
//! This function enables DMA request sources in the DES module. The
//! \e ui32Flags parameter should be the logical OR of any of the following:
//!
//! - \b DES_DMA_CONTEXT_IN - Context In
//! - \b DES_DMA_DATA_OUT - Data Out
//! - \b DES_DMA_DATA_IN - Data In
//!
//! \return None.
//
//*****************************************************************************
void
DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) ||
(ui32Flags & DES_DMA_DATA_OUT) ||
(ui32Flags & DES_DMA_DATA_IN));
//
// Set the data in and data out DMA request enable bits.
//
HWREG(ui32Base + DES_O_SYSCONFIG) |= ui32Flags;
}
//*****************************************************************************
//
//! Disables DMA request sources in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32Flags is a bit mask of the DMA requests to be disabled.
//!
//! This function disables DMA request sources in the DES module. The
//! \e ui32Flags parameter should be the logical OR of any of the following:
//!
//! - \b DES_DMA_CONTEXT_IN - Context In
//! - \b DES_DMA_DATA_OUT - Data Out
//! - \b DES_DMA_DATA_IN - Data In
//!
//! \return None.
//
//*****************************************************************************
void
DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) ||
(ui32Flags & DES_DMA_DATA_OUT) ||
(ui32Flags & DES_DMA_DATA_IN));
//
// Disable the DMA sources.
//
HWREG(ui32Base + DES_O_SYSCONFIG) &= ~ui32Flags;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// des.h
//
// Defines and Macros for the DES module.
//
//*****************************************************************************
#ifndef __DRIVERLIB_DES_H__
#define __DRIVERLIB_DES_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the direction with the
// ui32Config argument in the DESConfig() function. Only one is permitted.
//
//*****************************************************************************
#define DES_CFG_DIR_DECRYPT 0x00000000
#define DES_CFG_DIR_ENCRYPT 0x00000004
//*****************************************************************************
//
// The following defines are used to specify the operational with the
// ui32Config argument in the DESConfig() function. Only one is permitted.
//
//*****************************************************************************
#define DES_CFG_MODE_ECB 0x00000000
#define DES_CFG_MODE_CBC 0x00000010
#define DES_CFG_MODE_CFB 0x00000020
//*****************************************************************************
//
// The following defines are used to select between single DES and triple DES
// with the ui32Config argument in the DESConfig() function. Only one is
// permitted.
//
//*****************************************************************************
#define DES_CFG_SINGLE 0x00000000
#define DES_CFG_TRIPLE 0x00000008
//*****************************************************************************
//
// The following defines are used with the DESIntEnable(), DESIntDisable() and
// DESIntStatus() functions.
//
//*****************************************************************************
#define DES_INT_CONTEXT_IN 0x00000001
#define DES_INT_DATA_IN 0x00000002
#define DES_INT_DATA_OUT 0x00000004
#define DES_INT_DMA_CONTEXT_IN 0x00010000
#define DES_INT_DMA_DATA_IN 0x00020000
#define DES_INT_DMA_DATA_OUT 0x00040000
//*****************************************************************************
//
// The following defines are used with the DESEnableDMA() and DESDisableDMA()
// functions.
//
//*****************************************************************************
#define DES_DMA_CONTEXT_IN 0x00000080
#define DES_DMA_DATA_OUT 0x00000040
#define DES_DMA_DATA_IN 0x00000020
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest,
uint8_t ui8Length);
extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest,
uint8_t ui8Length);
extern bool DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t *pui8Dest, uint32_t ui32Length);
extern void DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t ui8Length);
extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t ui8Length);
extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked);
extern void DESIntUnregister(uint32_t ui32Base);
extern bool DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata);
extern void DESKeySet(uint32_t ui32Base, uint8_t *pui8Key);
extern void DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_DES_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// i2c.h
//
// Prototypes for the I2C Driver.
//
//*****************************************************************************
#ifndef __DRIVERLIB_I2C_H__
#define __DRIVERLIB_I2C_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Interrupt defines.
//
//*****************************************************************************
#define I2C_INT_MASTER 0x00000001
#define I2C_INT_SLAVE 0x00000002
//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND \
0x00000007
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
0x00000007
#define I2C_MASTER_CMD_BURST_SEND_START \
0x00000003
#define I2C_MASTER_CMD_BURST_SEND_CONT \
0x00000001
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_SEND_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
0x0000000b
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
0x00000009
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_QUICK_COMMAND \
0x00000027
#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \
0x00000013
#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \
0x00000046
#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \
0x00000046
#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \
0x00000042
#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \
0x00000040
#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \
0x00000044
#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \
0x0000004a
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \
0x00000048
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \
0x00000044
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \
0x00000004
//*****************************************************************************
//
// I2C Master glitch filter configuration.
//
//*****************************************************************************
#define I2C_MASTER_GLITCH_FILTER_DISABLED \
0
#define I2C_MASTER_GLITCH_FILTER_1 \
0x00010000
#define I2C_MASTER_GLITCH_FILTER_2 \
0x00020000
#define I2C_MASTER_GLITCH_FILTER_3 \
0x00030000
#define I2C_MASTER_GLITCH_FILTER_4 \
0x00040000
#define I2C_MASTER_GLITCH_FILTER_8 \
0x00050000
#define I2C_MASTER_GLITCH_FILTER_16 \
0x00060000
#define I2C_MASTER_GLITCH_FILTER_32 \
0x00070000
//*****************************************************************************
//
// I2C Master error status.
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
#define I2C_MASTER_ERR_CLK_TOUT 0x00000080
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave
#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command
#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value
//*****************************************************************************
//
// Miscellaneous I2C driver definitions.
//
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// I2C Master interrupts.
//
//*****************************************************************************
#define I2C_MASTER_INT_RX_FIFO_FULL \
0x00000800 // RX FIFO Full Interrupt
#define I2C_MASTER_INT_TX_FIFO_EMPTY \
0x00000400 // TX FIFO Empty Interrupt
#define I2C_MASTER_INT_RX_FIFO_REQ \
0x00000200 // RX FIFO Request Interrupt
#define I2C_MASTER_INT_TX_FIFO_REQ \
0x00000100 // TX FIFO Request Interrupt
#define I2C_MASTER_INT_ARB_LOST \
0x00000080 // Arb Lost Interrupt
#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt
#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt
#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt
#define I2C_MASTER_INT_TX_DMA_DONE \
0x00000008 // TX DMA Complete Interrupt
#define I2C_MASTER_INT_RX_DMA_DONE \
0x00000004 // RX DMA Complete Interrupt
#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt
#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt
//*****************************************************************************
//
// I2C Slave interrupts.
//
//*****************************************************************************
#define I2C_SLAVE_INT_RX_FIFO_FULL \
0x00000100 // RX FIFO Full Interrupt
#define I2C_SLAVE_INT_TX_FIFO_EMPTY \
0x00000080 // TX FIFO Empty Interrupt
#define I2C_SLAVE_INT_RX_FIFO_REQ \
0x00000040 // RX FIFO Request Interrupt
#define I2C_SLAVE_INT_TX_FIFO_REQ \
0x00000020 // TX FIFO Request Interrupt
#define I2C_SLAVE_INT_TX_DMA_DONE \
0x00000010 // TX DMA Complete Interrupt
#define I2C_SLAVE_INT_RX_DMA_DONE \
0x00000008 // RX DMA Complete Interrupt
#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt
#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt
#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt
//*****************************************************************************
//
// I2C Slave FIFO configuration macros.
//
//*****************************************************************************
#define I2C_SLAVE_TX_FIFO_ENABLE \
0x00000002
#define I2C_SLAVE_RX_FIFO_ENABLE \
0x00000004
//*****************************************************************************
//
// I2C FIFO configuration macros.
//
//*****************************************************************************
#define I2C_FIFO_CFG_TX_MASTER 0x00000000
#define I2C_FIFO_CFG_TX_SLAVE 0x00008000
#define I2C_FIFO_CFG_RX_MASTER 0x00000000
#define I2C_FIFO_CFG_RX_SLAVE 0x80000000
#define I2C_FIFO_CFG_TX_MASTER_DMA \
0x00002000
#define I2C_FIFO_CFG_TX_SLAVE_DMA \
0x0000a000
#define I2C_FIFO_CFG_RX_MASTER_DMA \
0x20000000
#define I2C_FIFO_CFG_RX_SLAVE_DMA \
0xa0000000
#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000
#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001
#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002
#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003
#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004
#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005
#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006
#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007
#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008
#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000
#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000
#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000
#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000
#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000
#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000
#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000
#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000
#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000
//*****************************************************************************
//
// I2C FIFO status.
//
//*****************************************************************************
#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \
0x00040000
#define I2C_FIFO_RX_FULL 0x00020000
#define I2C_FIFO_RX_EMPTY 0x00010000
#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \
0x00000004
#define I2C_FIFO_TX_FULL 0x00000002
#define I2C_FIFO_TX_EMPTY 0x00000001
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void));
extern void I2CIntUnregister(uint32_t ui32Base);
extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void I2CTxFIFOFlush(uint32_t ui32Base);
extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void I2CRxFIFOFlush(uint32_t ui32Base);
extern uint32_t I2CFIFOStatus(uint32_t ui32Base);
extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data);
extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base,
uint8_t ui8Data);
extern uint32_t I2CFIFODataGet(uint32_t ui32Base);
extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base,
uint8_t *pui8Data);
extern void I2CMasterBurstLengthSet(uint32_t ui32Base,
uint8_t ui8Length);
extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base);
extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base,
uint32_t ui32Config);
extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config);
extern void I2CSlaveFIFODisable(uint32_t ui32Base);
extern bool I2CMasterBusBusy(uint32_t ui32Base);
extern bool I2CMasterBusy(uint32_t ui32Base);
extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd);
extern uint32_t I2CMasterDataGet(uint32_t ui32Base);
extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data);
extern void I2CMasterDisable(uint32_t ui32Base);
extern void I2CMasterEnable(uint32_t ui32Base);
extern uint32_t I2CMasterErr(uint32_t ui32Base);
extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
bool bFast);
extern void I2CMasterIntClear(uint32_t ui32Base);
extern void I2CMasterIntDisable(uint32_t ui32Base);
extern void I2CMasterIntEnable(uint32_t ui32Base);
extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked);
extern void I2CMasterIntEnableEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern void I2CMasterIntDisableEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base,
bool bMasked);
extern void I2CMasterIntClearEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value);
extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable);
extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK);
extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base);
extern void I2CMasterSlaveAddrSet(uint32_t ui32Base,
uint8_t ui8SlaveAddr,
bool bReceive);
extern uint32_t I2CSlaveDataGet(uint32_t ui32Base);
extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data);
extern void I2CSlaveDisable(uint32_t ui32Base);
extern void I2CSlaveEnable(uint32_t ui32Base);
extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr);
extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum,
uint8_t ui8SlaveAddr);
extern void I2CSlaveIntClear(uint32_t ui32Base);
extern void I2CSlaveIntDisable(uint32_t ui32Base);
extern void I2CSlaveIntEnable(uint32_t ui32Base);
extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void I2CSlaveIntDisableEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked);
extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base,
bool bMasked);
extern uint32_t I2CSlaveStatus(uint32_t ui32Base);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_I2C_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// spi.h
//
// Defines and Macros for the SPI.
//
//*****************************************************************************
#ifndef __SPI_H__
#define __SPI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// Values that can be passed to SPIConfigSetExpClk() as ulMode parameter
//*****************************************************************************
#define SPI_MODE_MASTER 0x00000000
#define SPI_MODE_SLAVE 0x00000004
//*****************************************************************************
// Values that can be passed to SPIConfigSetExpClk() as ulSubMode parameter
//*****************************************************************************
#define SPI_SUB_MODE_0 0x00000000
#define SPI_SUB_MODE_1 0x00000001
#define SPI_SUB_MODE_2 0x00000002
#define SPI_SUB_MODE_3 0x00000003
//*****************************************************************************
// Values that can be passed to SPIConfigSetExpClk() as ulConfigFlags parameter
//*****************************************************************************
#define SPI_SW_CTRL_CS 0x01000000
#define SPI_HW_CTRL_CS 0x00000000
#define SPI_3PIN_MODE 0x02000000
#define SPI_4PIN_MODE 0x00000000
#define SPI_TURBO_ON 0x00080000
#define SPI_TURBO_OFF 0x00000000
#define SPI_CS_ACTIVEHIGH 0x00000000
#define SPI_CS_ACTIVELOW 0x00000040
#define SPI_WL_8 0x00000380
#define SPI_WL_16 0x00000780
#define SPI_WL_32 0x00000F80
//*****************************************************************************
// Values that can be passed to SPIFIFOEnable() and SPIFIFODisable()
//*****************************************************************************
#define SPI_TX_FIFO 0x08000000
#define SPI_RX_FIFO 0x10000000
//*****************************************************************************
// Values that can be passed to SPIDMAEnable() and SPIDMADisable()
//*****************************************************************************
#define SPI_RX_DMA 0x00008000
#define SPI_TX_DMA 0x00004000
//*****************************************************************************
// Values that can be passed to SPIIntEnable(), SPIIntDiasble(),
// SPIIntClear() or returned from SPIStatus()
//*****************************************************************************
#define SPI_INT_DMATX 0x20000000
#define SPI_INT_DMARX 0x10000000
#define SPI_INT_EOW 0x00020000
#define SPI_INT_WKS 0x00010000
#define SPI_INT_RX_OVRFLOW 0x00000008
#define SPI_INT_RX_FULL 0x00000004
#define SPI_INT_TX_UDRFLOW 0x00000002
#define SPI_INT_TX_EMPTY 0x00000001
//*****************************************************************************
// Values that can be passed to SPITransfer()
//*****************************************************************************
#define SPI_CS_ENABLE 0x00000001
#define SPI_CS_DISABLE 0x00000002
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void SPIEnable(unsigned long ulBase);
extern void SPIDisable(unsigned long ulBase);
extern void SPIReset(unsigned long ulBase);
extern void SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,
unsigned long ulBitRate, unsigned long ulMode,
unsigned long ulSubMode, unsigned long ulConfig);
extern long SPIDataGetNonBlocking(unsigned long ulBase,
unsigned long * pulData);
extern void SPIDataGet(unsigned long ulBase, unsigned long *pulData);
extern long SPIDataPutNonBlocking(unsigned long ulBase,
unsigned long ulData);
extern void SPIDataPut(unsigned long ulBase, unsigned long ulData);
extern void SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags);
extern void SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags);
extern void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulRxLevel);
extern void SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
unsigned long *pulRxLevel);
extern void SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount);
extern void SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void SPIIntUnregister(unsigned long ulBase);
extern void SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long SPIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags);
extern void SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags);
extern void SPICSEnable(unsigned long ulBase);
extern void SPICSDisable(unsigned long ulBase);
extern long SPITransfer(unsigned long ulBase, unsigned char *ucDout,
unsigned char *ucDin, unsigned long ulSize,
unsigned long ulFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SPI_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// timer.h
//
// Prototypes for the timer module
//
//*****************************************************************************
#ifndef __TIMER_H__
#define __TIMER_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count
// timer
#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count
// timer
#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
//*****************************************************************************
//
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt
#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt
#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
//*****************************************************************************
//
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
//
//*****************************************************************************
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
//*****************************************************************************
//
// Values that can be passed to most of the timer APIs as the ulTimer
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Values that can be passed to TimerSynchronize as the ulTimers parameter.
//
//*****************************************************************************
#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A
#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B
#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A
#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B
#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A
#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B
#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A
#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B
//*****************************************************************************
//
// Values that can be passed to TimerDMAEventSet() or returned from
// TimerDMAEventGet().
//
//*****************************************************************************
#define TIMER_DMA_MODEMATCH_B 0x00000800
#define TIMER_DMA_CAPEVENT_B 0x00000400
#define TIMER_DMA_CAPMATCH_B 0x00000200
#define TIMER_DMA_TIMEOUT_B 0x00000100
#define TIMER_DMA_MODEMATCH_A 0x00000010
#define TIMER_DMA_CAPEVENT_A 0x00000004
#define TIMER_DMA_CAPMATCH_A 0x00000002
#define TIMER_DMA_TIMEOUT_A 0x00000001
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
tBoolean bInvert);
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulEvent);
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall);
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerValueSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent);
extern unsigned long TimerDMAEventGet(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __TIMER_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// uart.h
//
// Defines and Macros for the UART.
//
//*****************************************************************************
#ifndef __UART_H__
#define __UART_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
// as the ulIntFlags parameter, and returned from UARTIntStatus.
//
//*****************************************************************************
#define UART_INT_DMATX 0x20000 // DMA Tx Done interrupt Mask
#define UART_INT_DMARX 0x10000 // DMA Rx Done interrupt Mask
#define UART_INT_EOT 0x800 // End of transfer interrupt Mask
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
#define UART_INT_RX 0x010 // Receive Interrupt Mask
#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
//*****************************************************************************
//
// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
// and returned by UARTConfigGetExpClk in the pulConfig parameter.
// Additionally, the UART_CONFIG_PAR_* subset can be passed to
// UARTParityModeSet as the ulParity parameter, and are returned by
// UARTParityModeGet.
//
//*****************************************************************************
#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
// returned by UARTFIFOLevelGet in the pulTxLevel.
//
//*****************************************************************************
#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
// returned by UARTFIFOLevelGet in the pulRxLevel.
//
//*****************************************************************************
#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
//*****************************************************************************
//
// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
//
//*****************************************************************************
#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
#define UART_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Values returned from UARTRxErrorGet().
//
//*****************************************************************************
#define UART_RXERROR_OVERRUN 0x00000008
#define UART_RXERROR_BREAK 0x00000004
#define UART_RXERROR_PARITY 0x00000002
#define UART_RXERROR_FRAMING 0x00000001
//*****************************************************************************
//
// Values that can be passed to UARTModemControlSet()and UARTModemControlClear()
// or returned from UARTModemControlGet().
//
//*****************************************************************************
#define UART_OUTPUT_RTS 0x00000800
//*****************************************************************************
//
// Values that can be returned from UARTModemStatusGet().
//
//*****************************************************************************
#define UART_INPUT_CTS 0x00000001
//*****************************************************************************
//
// Values that can be passed to UARTFlowControl() or returned from
// UARTFlowControlGet().
//
//*****************************************************************************
#define UART_FLOWCONTROL_TX 0x00008000
#define UART_FLOWCONTROL_RX 0x00004000
#define UART_FLOWCONTROL_NONE 0x00000000
//*****************************************************************************
//
// Values that can be passed to UARTTxIntModeSet() or returned from
// UARTTxIntModeGet().
//
//*****************************************************************************
#define UART_TXINT_MODE_FIFO 0x00000000
#define UART_TXINT_MODE_EOT 0x00000010
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
extern unsigned long UARTParityModeGet(unsigned long ulBase);
extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulRxLevel);
extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
unsigned long *pulRxLevel);
extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long ulBaud, unsigned long ulConfig);
extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
unsigned long *pulBaud,
unsigned long *pulConfig);
extern void UARTEnable(unsigned long ulBase);
extern void UARTDisable(unsigned long ulBase);
extern void UARTFIFOEnable(unsigned long ulBase);
extern void UARTFIFODisable(unsigned long ulBase);
extern tBoolean UARTCharsAvail(unsigned long ulBase);
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
extern long UARTCharGetNonBlocking(unsigned long ulBase);
extern long UARTCharGet(unsigned long ulBase);
extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
unsigned char ucData);
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
extern tBoolean UARTBusy(unsigned long ulBase);
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void UARTIntUnregister(unsigned long ulBase);
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
extern unsigned long UARTRxErrorGet(unsigned long ulBase);
extern void UARTRxErrorClear(unsigned long ulBase);
extern void UARTModemControlSet(unsigned long ulBase,
unsigned long ulControl);
extern void UARTModemControlClear(unsigned long ulBase,
unsigned long ulControl);
extern unsigned long UARTModemControlGet(unsigned long ulBase);
extern unsigned long UARTModemStatusGet(unsigned long ulBase);
extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTFlowControlGet(unsigned long ulBase);
extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __UART_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// udma.h
//
// Prototypes and macros for the uDMA controller.
//
//*****************************************************************************
#ifndef __UDMA_H__
#define __UDMA_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup uDMA_Micro_Direct_Memory_Access_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// A structure that defines an entry in the channel control table. These
// fields are used by the uDMA controller and normally it is not necessary for
// software to directly read or write fields in the table.
//
//*****************************************************************************
typedef struct
{
//
// The ending source address of the data transfer.
//
volatile void *pvSrcEndAddr;
//
// The ending destination address of the data transfer.
//
volatile void *pvDstEndAddr;
//
// The channel control mode.
//
volatile unsigned long ulControl;
//
// An unused location.
//
volatile unsigned long ulSpare;
}
tDMAControlTable;
//*****************************************************************************
//
//! A helper macro for building scatter-gather task table entries.
//!
//! \param ulTransferCount is the count of items to transfer for this task.
//! \param ulItemSize is the bit size of the items to transfer for this task.
//! \param ulSrcIncrement is the bit size increment for source data.
//! \param pvSrcAddr is the starting address of the data to transfer.
//! \param ulDstIncrement is the bit size increment for destination data.
//! \param pvDstAddr is the starting address of the destination data.
//! \param ulArbSize is the arbitration size to use for the transfer task.
//! \param ulMode is the transfer mode for this task.
//!
//! This macro is intended to be used to help populate a table of uDMA tasks
//! for a scatter-gather transfer. This macro will calculate the values for
//! the fields of a task structure entry based on the input parameters.
//!
//! There are specific requirements for the values of each parameter. No
//! checking is done so it is up to the caller to ensure that correct values
//! are used for the parameters.
//!
//! The \e ulTransferCount parameter is the number of items that will be
//! transferred by this task. It must be in the range 1-1024.
//!
//! The \e ulItemSize parameter is the bit size of the transfer data. It must
//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32.
//!
//! The \e ulSrcIncrement parameter is the increment size for the source data.
//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
//!
//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source
//! data.
//!
//! The \e ulDstIncrement parameter is the increment size for the destination
//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16,
//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE.
//!
//! The \e pvDstAddr parameter is a void pointer to the beginning of the
//! location where the data will be transferred.
//!
//! The \e ulArbSize parameter is the arbitration size for the transfer, and
//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on
//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in
//! powers of 2, from 1 to 1024.
//!
//! The \e ulMode parameter is the mode to use for this transfer task. It
//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO,
//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note
//! that normally all tasks will be one of the scatter-gather modes while the
//! last task is a task list will be AUTO or BASIC.
//!
//! This macro is intended to be used to initialize individual entries of
//! a structure of tDMAControlTable type, like this:
//!
//! \verbatim
//! tDMAControlTable MyTaskList[] =
//! {
//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
//! UDMA_SRC_INC_8, MySourceBuf,
//! UDMA_DST_INC_8, MyDestBuf,
//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
//! uDMATaskStructEntry(Task2Count, ... ),
//! }
//! \endverbatim
//!
//! \return Nothing; this is not a function.
//
//*****************************************************************************
#define uDMATaskStructEntry(ulTransferCount, \
ulItemSize, \
ulSrcIncrement, \
pvSrcAddr, \
ulDstIncrement, \
pvDstAddr, \
ulArbSize, \
ulMode) \
{ \
(((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \
((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \
((ulSrcIncrement) >> 26)) - 1]))), \
(((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \
((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \
((ulDstIncrement) >> 30)) - 1]))), \
(ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \
(((ulTransferCount) - 1) << 4) | \
((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
(ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Flags that can be passed to uDMAChannelAttributeEnable(),
// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
//
//*****************************************************************************
#define UDMA_ATTR_USEBURST 0x00000001
#define UDMA_ATTR_ALTSELECT 0x00000002
#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
#define UDMA_ATTR_REQMASK 0x00000008
#define UDMA_ATTR_ALL 0x0000000F
//*****************************************************************************
//
// DMA control modes that can be passed to uDMAModeSet() and returned
// uDMAModeGet().
//
//*****************************************************************************
#define UDMA_MODE_STOP 0x00000000
#define UDMA_MODE_BASIC 0x00000001
#define UDMA_MODE_AUTO 0x00000002
#define UDMA_MODE_PINGPONG 0x00000003
#define UDMA_MODE_MEM_SCATTER_GATHER \
0x00000004
#define UDMA_MODE_PER_SCATTER_GATHER \
0x00000006
#define UDMA_MODE_ALT_SELECT 0x00000001
//*****************************************************************************
//
// Flags to be OR'd with the channel ID to indicate if the primary or alternate
// control structure should be used.
//
//*****************************************************************************
#define UDMA_PRI_SELECT 0x00000000
#define UDMA_ALT_SELECT 0x00000020
//*****************************************************************************
//
// uDMA interrupt sources, to be passed to uDMAIntRegister() and
// uDMAIntUnregister().
//
//*****************************************************************************
#define UDMA_INT_SW INT_UDMA
#define UDMA_INT_ERR INT_UDMAERR
//*****************************************************************************
//*****************************************************************************
//
// Channel configuration values that can be passed to uDMAControlSet().
//
//*****************************************************************************
#define UDMA_DST_INC_8 0x00000000
#define UDMA_DST_INC_16 0x40000000
#define UDMA_DST_INC_32 0x80000000
#define UDMA_DST_INC_NONE 0xc0000000
#define UDMA_SRC_INC_8 0x00000000
#define UDMA_SRC_INC_16 0x04000000
#define UDMA_SRC_INC_32 0x08000000
#define UDMA_SRC_INC_NONE 0x0c000000
#define UDMA_SIZE_8 0x00000000
#define UDMA_SIZE_16 0x11000000
#define UDMA_SIZE_32 0x22000000
#define UDMA_ARB_1 0x00000000
#define UDMA_ARB_2 0x00004000
#define UDMA_ARB_4 0x00008000
#define UDMA_ARB_8 0x0000c000
#define UDMA_ARB_16 0x00010000
#define UDMA_ARB_32 0x00014000
#define UDMA_ARB_64 0x00018000
#define UDMA_ARB_128 0x0001c000
#define UDMA_ARB_256 0x00020000
#define UDMA_ARB_512 0x00024000
#define UDMA_ARB_1024 0x00028000
#define UDMA_NEXT_USEBURST 0x00000008
//*****************************************************************************
//
// Values that can be passed to uDMAChannelAssign() to select peripheral
// mapping for each channel. The channels named RESERVED may be assigned
// to a peripheral in future parts.
//
//*****************************************************************************
//
// Channel 0
//
#define UDMA_CH0_TIMERA0_A 0x00000000
#define UDMA_CH0_SHAMD5_CIN 0x00010000
#define UDMA_CH0_SW 0x00030000
//
// Channel 1
//
#define UDMA_CH1_TIMERA0_B 0x00000001
#define UDMA_CH1_SHAMD5_DIN 0x00010001
#define UDMA_CH1_SW 0x00030001
//
// Channel 2
//
#define UDMA_CH2_TIMERA1_A 0x00000002
#define UDMA_CH2_SHAMD5_COUT 0x00010002
#define UDMA_CH2_SW 0x00030002
//
// Channel 3
//
#define UDMA_CH3_TIMERA1_B 0x00000003
#define UDMA_CH3_DES_CIN 0x00010003
#define UDMA_CH3_SW 0x00030003
//
// Channel 4
//
#define UDMA_CH4_TIMERA2_A 0x00000004
#define UDMA_CH4_DES_DIN 0x00010004
#define UDMA_CH4_I2S_RX 0x00020004
#define UDMA_CH4_SW 0x00030004
//
// Channel 5
//
#define UDMA_CH5_TIMERA2_B 0x00000005
#define UDMA_CH5_DES_DOUT 0x00010005
#define UDMA_CH5_I2S_TX 0x00020005
#define UDMA_CH5_SW 0x00030005
//
// Channel 6
//
#define UDMA_CH6_TIMERA3_A 0x00000006
#define UDMA_CH6_GSPI_RX 0x00010006
#define UDMA_CH6_GPIOA2 0x00020006
#define UDMA_CH6_SW 0x00030006
//
// Channel 7
//
#define UDMA_CH7_TIMERA3_B 0x00000007
#define UDMA_CH7_GSPI_TX 0x00010007
#define UDMA_CH7_GPIOA3 0x00020007
#define UDMA_CH7_SW 0x00030007
//
// Channel 8
//
#define UDMA_CH8_UARTA0_RX 0x00000008
#define UDMA_CH8_TIMERA0_A 0x00010008
#define UDMA_CH8_TIMERA2_A 0x00020008
#define UDMA_CH8_SW 0x00030008
//
// Channel 9
//
#define UDMA_CH9_UARTA0_TX 0x00000009
#define UDMA_CH9_TIMERA0_B 0x00010009
#define UDMA_CH9_TIMERA2_B 0x00020009
#define UDMA_CH9_SW 0x00030009
//
// Channel 10
//
#define UDMA_CH10_UARTA1_RX 0x0000000A
#define UDMA_CH10_TIMERA1_A 0x0001000A
#define UDMA_CH10_TIMERA3_A 0x0002000A
#define UDMA_CH10_SW 0x0003000A
//
// Channel 11
//
#define UDMA_CH11_UARTA1_TX 0x0000000B
#define UDMA_CH11_TIMERA1_B 0x0001000B
#define UDMA_CH11_TIMERA3_B 0x0002000B
#define UDMA_CH11_SW 0x0003000B
//
// Channel 12
//
#define UDMA_CH12_LSPI_RX 0x0000000C
#define UDMA_CH12_SW 0x0003000C
//
// Channel 13
//
#define UDMA_CH13_LSPI_TX 0x0000000D
#define UDMA_CH13_SW 0x0003000D
//
// Channel 14
//
#define UDMA_CH14_ADC_CH0 0x0000000E
#define UDMA_CH14_SDHOST_RX 0x0002000E
#define UDMA_CH14_SW 0x0003000E
//
// Channel 15
//
#define UDMA_CH15_ADC_CH1 0x0000000F
#define UDMA_CH15_SDHOST_TX 0x0002000F
#define UDMA_CH15_SW 0x0003000F
//
// Channel 16
//
#define UDMA_CH16_ADC_CH2 0x00000010
#define UDMA_CH16_TIMERA2_A 0x00010010
#define UDMA_CH16_SW 0x00030010
//
// Channel 17
//
#define UDMA_CH17_ADC_CH3 0x00000011
#define UDMA_CH17_TIMERA2_B 0x00010011
#define UDMA_CH17_SW 0x00030011
//
// Channel 18
//
#define UDMA_CH18_GPIOA0 0x00000012
#define UDMA_CH18_AES_CIN 0x00010012
#define UDMA_CH18_I2S_RX 0x00020012
#define UDMA_CH18_SW 0x00030012
//
// Channel 19
//
#define UDMA_CH19_GPOIA1 0x00000013
#define UDMA_CH19_AES_COUT 0x00010013
#define UDMA_CH19_I2S_TX 0x00020013
#define UDMA_CH19_SW 0x00030013
//
// Channel 20
//
#define UDMA_CH20_GPIOA2 0x00000014
#define UDMA_CH20_AES_DIN 0x00010014
#define UDMA_CH20_SW 0x00030014
//
// Channel 21
//
#define UDMA_CH21_GPIOA3 0x00000015
#define UDMA_CH21_AES_DOUT 0x00010015
#define UDMA_CH21_SW 0x00030015
//
// Channel 22
//
#define UDMA_CH22_CAMERA 0x00000016
#define UDMA_CH22_GPIOA4 0x00010016
#define UDMA_CH22_SW 0x00030016
//
// Channel 23
//
#define UDMA_CH23_SDHOST_RX 0x00000017
#define UDMA_CH23_TIMERA3_A 0x00010017
#define UDMA_CH23_TIMERA2_A 0x00020017
#define UDMA_CH23_SW 0x00030017
//
// Channel 24
//
#define UDMA_CH24_SDHOST_TX 0x00000018
#define UDMA_CH24_TIMERA3_B 0x00010018
#define UDMA_CH24_TIMERA2_B 0x00020018
#define UDMA_CH24_SW 0x00030018
//
// Channel 25
//
#define UDMA_CH25_SSPI_RX 0x00000019
#define UDMA_CH25_I2CA0_RX 0x00010019
#define UDMA_CH25_SW 0x00030019
//
// Channel 26
//
#define UDMA_CH26_SSPI_TX 0x0000001A
#define UDMA_CH26_I2CA0_TX 0x0001001A
#define UDMA_CH26_SW 0x0003001A
//
// Channel 27
//
#define UDMA_CH27_GPIOA0 0x0001001B
#define UDMA_CH27_SW 0x0003001B
//
// Channel 28
//
#define UDMA_CH28_GPIOA1 0x0001001C
#define UDMA_CH28_SW 0x0003001C
//
// Channel 29
//
#define UDMA_CH29_GPIOA4 0x0000001D
#define UDMA_CH29_SW 0x0003001D
//
// Channel 30
//
#define UDMA_CH30_GSPI_RX 0x0000001E
#define UDMA_CH30_SDHOST_RX 0x0001001E
#define UDMA_CH30_I2CA0_RX 0x0002001E
#define UDMA_CH30_SW 0x0003001E
//
// Channel 31
//
#define UDMA_CH31_GSPI_TX 0x0000001F
#define UDMA_CH31_SDHOST_TX 0x0001001F
#define UDMA_CH31_I2CA0_RX 0x0002001F
#define UDMA_CH31_SW 0x0003001F
//*****************************************************************************
//
// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
//
//*****************************************************************************
#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
// Pointer
#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
// End Pointer
#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
//
//*****************************************************************************
#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
#define UDMA_SRCENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
//
//*****************************************************************************
#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
#define UDMA_DSTENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHCTL register.
//
//*****************************************************************************
#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
#define UDMA_CHCTL_XFERMODE_STOP \
0x00000000 // Stop
#define UDMA_CHCTL_XFERMODE_BASIC \
0x00000001 // Basic
#define UDMA_CHCTL_XFERMODE_AUTO \
0x00000002 // Auto-Request
#define UDMA_CHCTL_XFERMODE_PINGPONG \
0x00000003 // Ping-Pong
#define UDMA_CHCTL_XFERMODE_MEM_SG \
0x00000004 // Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_MEM_SGA \
0x00000005 // Alternate Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SG \
0x00000006 // Peripheral Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SGA \
0x00000007 // Alternate Peripheral
// Scatter-Gather
#define UDMA_CHCTL_XFERSIZE_S 4
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void uDMAEnable(void);
extern void uDMADisable(void);
extern unsigned long uDMAErrorStatusGet(void);
extern void uDMAErrorStatusClear(void);
extern void uDMAChannelEnable(unsigned long ulChannelNum);
extern void uDMAChannelDisable(unsigned long ulChannelNum);
extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum);
extern void uDMAControlBaseSet(void *pControlTable);
extern void *uDMAControlBaseGet(void);
extern void *uDMAControlAlternateBaseGet(void);
extern void uDMAChannelRequest(unsigned long ulChannelNum);
extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum,
unsigned long ulAttr);
extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum,
unsigned long ulAttr);
extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum);
extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex,
unsigned long ulControl);
extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex,
unsigned long ulMode, void *pvSrcAddr,
void *pvDstAddr,
unsigned long ulTransferSize);
extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum,
unsigned ulTaskCount, void *pvTaskList,
unsigned long ulIsPeriphSG);
extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex);
extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex);
extern void uDMAIntRegister(unsigned long ulIntChannel,
void (*pfnHandler)(void));
extern void uDMAIntUnregister(unsigned long ulIntChannel);
extern unsigned long uDMAIntStatus(void);
extern void uDMAIntClear(unsigned long ulChanMask);
extern void uDMAChannelAssign(unsigned long ulMapping);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __UDMA_H__

99
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// utils.c
//
// Utility APIs
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup Utils_api
//! @{
//
//*****************************************************************************
#include "utils.h"
//*****************************************************************************
//
//! Provides a small delay.
//!
//! \param ulCount is the number of delay loop iterations to perform.
//!
//! This function provides a means of generating a constant length delay. It
//! is written in assembly to keep the delay consistent across tool chains,
//! avoiding the need to tune the delay based on the tool chain in use.
//!
//! The loop takes 3 cycles/loop.
//!
//! \return None.
//
//*****************************************************************************
#if defined(ewarm) || defined(DOXYGEN)
void
UtilsDelay(unsigned long ulCount)
{
__asm(" subs r0, #1\n"
" bne.n UtilsDelay\n");
}
#endif
#if defined(gcc)
void __attribute__((naked))
UtilsDelay(unsigned long ulCount)
{
__asm(" subs r0, #1\n"
" bne UtilsDelay\n"
" bx lr");
}
#endif
#if defined (arm_cc)
// Use C code for now. TODO, change to assembly if precision is needed.
void UtilsDelay(unsigned long ulCount)
{
volatile unsigned long delay = (ulCount >> 2);
while (delay --);
}
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

81
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// utils.h
//
// Prototypes and macros for utility APIs
//
//*****************************************************************************
#ifndef __UTILS_H__
#define __UTILS_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
// TODO, move this to tools
#ifdef TOOLCHAIN_GCC_ARM
#define gcc
#elif defined TOOLCHAIN_ARM
#define arm_cc
#elif defined TOOLCHAIN_IAR
#define ewarm
#endif
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void UtilsDelay(unsigned long ulCount);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif //__UTILS_H__

76
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// version.h
//
// Contains Driverlib version details
//
//*****************************************************************************
#ifndef __DRIVERLIB_VERSION_H__
#define __DRIVERLIB_VERSION_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#define DRIVERLIB_MAJOR_VERSION_NUM 01
#define DRIVERLIB_MINOR_VERSION_NUM 51
#define DRIVERLIB_PATCH_VERSION_NUM 03
#define DRIVERLIB_BUILD_VERSION_NUM 00
#define DRIVERLIB_RELEASE_DAY 15
#define DRIVERLIB_RELEASE_MONTH 01
#define DRIVERLIB_RELEASE_YEAR 2018
/////////////////////////////////////////////
// !!! Please update the changes.log file !!!
/////////////////////////////////////////////
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_VERSION_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// wdt.c
//
// Driver for the Watchdog Timer Module.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup WDT_Watchdog_Timer_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_wdt.h"
#include "debug.h"
#include "interrupt.h"
#include "wdt.h"
//*****************************************************************************
//
//! Determines if the watchdog timer is enabled.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This will check to see if the watchdog timer is enabled.
//!
//! \return Returns \b true if the watchdog timer is enabled, and \b false
//! if it is not.
//
//*****************************************************************************
tBoolean
WatchdogRunning(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// See if the watchdog timer module is enabled, and return.
//
return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);
}
//*****************************************************************************
//
//! Enables the watchdog timer.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This will enable the watchdog timer counter and interrupt.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Enable the watchdog timer module.
//
HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
}
//*****************************************************************************
//
//! Enables the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Locks out write access to the watchdog timer configuration registers.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogLock(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
// register causes the lock to go into effect.
//
HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;
}
//*****************************************************************************
//
//! Disables the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables write access to the watchdog timer configuration registers.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogUnlock(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Unlock watchdog register writes.
//
HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
}
//*****************************************************************************
//
//! Gets the state of the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Returns the lock state of the watchdog timer registers.
//!
//! \return Returns \b true if the watchdog timer registers are locked, and
//! \b false if they are not locked.
//
//*****************************************************************************
tBoolean
WatchdogLockState(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Get the lock state.
//
return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
}
//*****************************************************************************
//
//! Sets the watchdog timer reload value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param ulLoadVal is the load value for the watchdog timer.
//!
//! This function sets the value to load into the watchdog timer when the count
//! reaches zero for the first time; if the watchdog timer is running when this
//! function is called, then the value will be immediately loaded into the
//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an
//! interrupt is immediately generated.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Set the load register.
//
HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;
}
//*****************************************************************************
//
//! Gets the watchdog timer reload value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function gets the value that is loaded into the watchdog timer when
//! the count reaches zero for the first time.
//!
//! \sa WatchdogReloadSet()
//!
//! \return None.
//
//*****************************************************************************
unsigned long
WatchdogReloadGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Get the load register.
//
return(HWREG(ulBase + WDT_O_LOAD));
}
//*****************************************************************************
//
//! Gets the current watchdog timer value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function reads the current value of the watchdog timer.
//!
//! \return Returns the current value of the watchdog timer.
//
//*****************************************************************************
unsigned long
WatchdogValueGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Get the current watchdog timer register value.
//
return(HWREG(ulBase + WDT_O_VALUE));
}
//*****************************************************************************
//
//! Registers an interrupt handler for watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param pfnHandler is a pointer to the function to be called when the
//! watchdog timer interrupt occurs.
//!
//! This function does the actual registering of the interrupt handler. This
//! will enable the global interrupt in the interrupt controller; the watchdog
//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt
//! handler's responsibility to clear the interrupt source via
//! WatchdogIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \note This function will only register the standard watchdog interrupt
//! handler. To register the NMI watchdog handler, use IntRegister()
//! to register the handler for the \b FAULT_NMI interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Register the interrupt handler and
// Enable the watchdog timer interrupt.
//
IntRegister(INT_WDT, pfnHandler);
IntEnable(INT_WDT);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function does the actual unregistering of the interrupt handler. This
//! function will clear the handler to be called when a watchdog timer
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \note This function will only unregister the standard watchdog interrupt
//! handler. To unregister the NMI watchdog handler, use IntUnregister()
//! to unregister the handler for the \b FAULT_NMI interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntUnregister(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Disable the interrupt
IntDisable(INT_WDT);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_WDT);
}
//*****************************************************************************
//
//! Gets the current watchdog timer interrupt status.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the watchdog timer module. Either
//! the raw interrupt status or the status of interrupt that is allowed to
//! reflect to the processor can be returned.
//!
//! \return Returns the current interrupt status, where a 1 indicates that the
//! watchdog interrupt is active, and a 0 indicates that it is not active.
//
//*****************************************************************************
unsigned long
WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + WDT_O_MIS));
}
else
{
return(HWREG(ulBase + WDT_O_RIS));
}
}
//*****************************************************************************
//
//! Clears the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! The watchdog timer interrupt source is cleared, so that it no longer
//! asserts.
//!
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntClear(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Clear the interrupt source.
//
HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
}
//*****************************************************************************
//
//! Enables stalling of the watchdog timer during debug events.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function allows the watchdog timer to stop counting when the processor
//! is stopped by the debugger. By doing so, the watchdog is prevented from
//! expiring (typically almost immediately from a human time perspective) and
//! resetting the system (if reset is enabled). The watchdog will instead
//! expired after the appropriate number of processor cycles have been executed
//! while debugging (or at the appropriate time after the processor has been
//! restarted).
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogStallEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Enable timer stalling.
//
HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;
}
//*****************************************************************************
//
//! Disables stalling of the watchdog timer during debug events.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function disables the debug mode stall of the watchdog timer. By
//! doing so, the watchdog timer continues to count regardless of the processor
//! debug state.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogStallDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Disable timer stalling.
//
HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

83
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/driverlib/wdt.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// wdt.h - Prototypes for the Watchdog Timer API
//
//
#ifndef __WATCHDOG_H__
#define __WATCHDOG_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean WatchdogRunning(unsigned long ulBase);
extern void WatchdogEnable(unsigned long ulBase);
extern void WatchdogLock(unsigned long ulBase);
extern void WatchdogUnlock(unsigned long ulBase);
extern tBoolean WatchdogLockState(unsigned long ulBase);
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
extern unsigned long WatchdogReloadGet(unsigned long ulBase);
extern unsigned long WatchdogValueGet(unsigned long ulBase);
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void WatchdogIntUnregister(unsigned long ulBase);
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void WatchdogIntClear(unsigned long ulBase);
extern void WatchdogStallEnable(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __WATCHDOG_H__

227
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/asmdefs.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// asmdefs.h - Macros to allow assembly code be portable among toolchains.
//
//*****************************************************************************
#ifndef __ASMDEFS_H__
#define __ASMDEFS_H__
//*****************************************************************************
//
// The defines required for code_red.
//
//*****************************************************************************
#ifdef codered
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // codered
//*****************************************************************************
//
// The defines required for EW-ARM.
//
//*****************************************************************************
#ifdef ewarm
//
// Section headers.
//
#define __LIBRARY__ module
#define __TEXT__ rseg CODE:CODE(2)
#define __DATA__ rseg DATA:DATA(2)
#define __BSS__ rseg DATA:DATA(2)
#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2)
//
// Assembler nmenonics.
//
#define __ALIGN__ alignrom 2
#define __END__ end
#define __EXPORT__ export
#define __IMPORT__ import
#define __LABEL__
#define __STR__ dcb
#define __THUMB_LABEL__ thumb
#define __WORD__ dcd
#define __INLINE_DATA__ data
#endif // ewarm
//*****************************************************************************
//
// The defines required for GCC.
//
//*****************************************************************************
#if defined(gcc)
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // gcc
//*****************************************************************************
//
// The defines required for RV-MDK.
//
//*****************************************************************************
#ifdef rvmdk
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
thumb
require8
preserve8
//
// Section headers.
//
#define __LIBRARY__ ;
#define __TEXT__ area ||.text||, code, readonly, align=2
#define __DATA__ area ||.data||, data, align=2
#define __BSS__ area ||.bss||, noinit, align=2
#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2
//
// Assembler nmenonics.
//
#define __ALIGN__ align 4
#define __END__ end
#define __EXPORT__ export
#define __IMPORT__ import
#define __LABEL__
#define __STR__ dcb
#define __THUMB_LABEL__
#define __WORD__ dcd
#define __INLINE_DATA__
#endif // rvmdk
//*****************************************************************************
//
// The defines required for Sourcery G++.
//
//*****************************************************************************
#if defined(sourcerygxx)
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // sourcerygxx
#endif // __ASMDEF_H__

886
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_adc.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_ADC_H__
#define __HW_ADC_H__
//*****************************************************************************
//
// The following are defines for the ADC register offsets.
//
//*****************************************************************************
#define ADC_O_ADC_CTRL 0x00000000 // ADC control register.
#define ADC_O_adc_ch0_gain 0x00000004 // Channel 0 gain setting
#define ADC_O_adc_ch1_gain 0x00000008 // Channel 1 gain setting
#define ADC_O_adc_ch2_gain 0x0000000C // Channel 2 gain setting
#define ADC_O_adc_ch3_gain 0x00000010 // Channel 3 gain setting
#define ADC_O_adc_ch4_gain 0x00000014 // Channel 4 gain setting
#define ADC_O_adc_ch5_gain 0x00000018 // Channel 5 gain setting
#define ADC_O_adc_ch6_gain 0x0000001C // Channel 6 gain setting
#define ADC_O_adc_ch7_gain 0x00000020 // Channel 7 gain setting
#define ADC_O_adc_ch0_irq_en 0x00000024 // Channel 0 interrupt enable
// register
#define ADC_O_adc_ch1_irq_en 0x00000028 // Channel 1 interrupt enable
// register
#define ADC_O_adc_ch2_irq_en 0x0000002C // Channel 2 interrupt enable
// register
#define ADC_O_adc_ch3_irq_en 0x00000030 // Channel 3 interrupt enable
// register
#define ADC_O_adc_ch4_irq_en 0x00000034 // Channel 4 interrupt enable
// register
#define ADC_O_adc_ch5_irq_en 0x00000038 // Channel 5 interrupt enable
// register
#define ADC_O_adc_ch6_irq_en 0x0000003C // Channel 6 interrupt enable
// register
#define ADC_O_adc_ch7_irq_en 0x00000040 // Channel 7 interrupt enable
// register
#define ADC_O_adc_ch0_irq_status \
0x00000044 // Channel 0 interrupt status
// register
#define ADC_O_adc_ch1_irq_status \
0x00000048 // Channel 1 interrupt status
// register
#define ADC_O_adc_ch2_irq_status \
0x0000004C
#define ADC_O_adc_ch3_irq_status \
0x00000050 // Channel 3 interrupt status
// register
#define ADC_O_adc_ch4_irq_status \
0x00000054 // Channel 4 interrupt status
// register
#define ADC_O_adc_ch5_irq_status \
0x00000058
#define ADC_O_adc_ch6_irq_status \
0x0000005C // Channel 6 interrupt status
// register
#define ADC_O_adc_ch7_irq_status \
0x00000060 // Channel 7 interrupt status
// register
#define ADC_O_adc_dma_mode_en 0x00000064 // DMA mode enable register
#define ADC_O_adc_timer_configuration \
0x00000068 // ADC timer configuration register
#define ADC_O_adc_timer_current_count \
0x00000070 // ADC timer current count register
#define ADC_O_channel0FIFODATA 0x00000074 // CH0 FIFO DATA register
#define ADC_O_channel1FIFODATA 0x00000078 // CH1 FIFO DATA register
#define ADC_O_channel2FIFODATA 0x0000007C // CH2 FIFO DATA register
#define ADC_O_channel3FIFODATA 0x00000080 // CH3 FIFO DATA register
#define ADC_O_channel4FIFODATA 0x00000084 // CH4 FIFO DATA register
#define ADC_O_channel5FIFODATA 0x00000088 // CH5 FIFO DATA register
#define ADC_O_channel6FIFODATA 0x0000008C // CH6 FIFO DATA register
#define ADC_O_channel7FIFODATA 0x00000090 // CH7 FIFO DATA register
#define ADC_O_adc_ch0_fifo_lvl 0x00000094 // channel 0 FIFO Level register
#define ADC_O_adc_ch1_fifo_lvl 0x00000098 // Channel 1 interrupt status
// register
#define ADC_O_adc_ch2_fifo_lvl 0x0000009C
#define ADC_O_adc_ch3_fifo_lvl 0x000000A0 // Channel 3 interrupt status
// register
#define ADC_O_adc_ch4_fifo_lvl 0x000000A4 // Channel 4 interrupt status
// register
#define ADC_O_adc_ch5_fifo_lvl 0x000000A8
#define ADC_O_adc_ch6_fifo_lvl 0x000000AC // Channel 6 interrupt status
// register
#define ADC_O_adc_ch7_fifo_lvl 0x000000B0 // Channel 7 interrupt status
// register
#define ADC_O_ADC_CH_ENABLE 0x000000B8
//******************************************************************************
//
// The following are defines for the bit fields in the ADC_O_ADC_CTRL register.
//
//******************************************************************************
#define ADC_ADC_CTRL_adc_cap_scale \
0x00000020 // ADC CAP SCALE.
#define ADC_ADC_CTRL_adc_buf_bypass \
0x00000010 // ADC ANA CIO buffer bypass.
// Signal is modelled in ANA TOP.
// When '1': ADC buffer is bypassed.
#define ADC_ADC_CTRL_adc_buf_en 0x00000008 // ADC ANA buffer enable. When 1:
// ADC buffer is enabled.
#define ADC_ADC_CTRL_adc_core_en \
0x00000004 // ANA ADC core en. This signal act
// as glbal enable to ADC CIO. When
// 1: ADC core is enabled.
#define ADC_ADC_CTRL_adc_soft_reset \
0x00000002 // ADC soft reset. When '1' : reset
// ADC internal logic.
#define ADC_ADC_CTRL_adc_en 0x00000001 // ADC global enable. When set ADC
// module is enabled
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch0_gain register.
//
//******************************************************************************
#define ADC_adc_ch0_gain_adc_channel0_gain_M \
0x00000003 // gain setting for ADC channel 0.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch0_gain_adc_channel0_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch1_gain register.
//
//******************************************************************************
#define ADC_adc_ch1_gain_adc_channel1_gain_M \
0x00000003 // gain setting for ADC channel 1.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch1_gain_adc_channel1_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch2_gain register.
//
//******************************************************************************
#define ADC_adc_ch2_gain_adc_channel2_gain_M \
0x00000003 // gain setting for ADC channel 2.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch2_gain_adc_channel2_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch3_gain register.
//
//******************************************************************************
#define ADC_adc_ch3_gain_adc_channel3_gain_M \
0x00000003 // gain setting for ADC channel 3.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch3_gain_adc_channel3_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch4_gain register.
//
//******************************************************************************
#define ADC_adc_ch4_gain_adc_channel4_gain_M \
0x00000003 // gain setting for ADC channel 4
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch4_gain_adc_channel4_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch5_gain register.
//
//******************************************************************************
#define ADC_adc_ch5_gain_adc_channel5_gain_M \
0x00000003 // gain setting for ADC channel 5.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch5_gain_adc_channel5_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch6_gain register.
//
//******************************************************************************
#define ADC_adc_ch6_gain_adc_channel6_gain_M \
0x00000003 // gain setting for ADC channel 6
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch6_gain_adc_channel6_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch7_gain register.
//
//******************************************************************************
#define ADC_adc_ch7_gain_adc_channel7_gain_M \
0x00000003 // gain setting for ADC channel 7.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch7_gain_adc_channel7_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch0_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch1_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch2_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch3_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch4_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch5_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch6_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch7_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch0_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch1_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch2_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch3_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch4_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch5_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch6_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch7_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_dma_mode_en register.
//
//******************************************************************************
#define ADC_adc_dma_mode_en_DMA_MODEenable_M \
0x000000FF // this register enable DMA mode.
// when '1' respective ADC channel
// is enabled for DMA. When '0' only
// interrupt mode is enabled. Bit 0:
// channel 0 DMA mode enable. Bit 1:
// channel 1 DMA mode enable. Bit 2:
// channel 2 DMA mode enable. Bit 3:
// channel 3 DMA mode enable. bit 4:
// channel 4 DMA mode enable. bit 5:
// channel 5 DMA mode enable. bit 6:
// channel 6 DMA mode enable. bit 7:
// channel 7 DMA mode enable.
#define ADC_adc_dma_mode_en_DMA_MODEenable_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_timer_configuration register.
//
//******************************************************************************
#define ADC_adc_timer_configuration_timeren \
0x02000000 // when '1' timer is enabled.
#define ADC_adc_timer_configuration_timerreset \
0x01000000 // when '1' reset timer.
#define ADC_adc_timer_configuration_timercount_M \
0x00FFFFFF // Timer count configuration. 17
// bit counter is supported. Other
// MSB's are redundent.
#define ADC_adc_timer_configuration_timercount_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_timer_current_count register.
//
//******************************************************************************
#define ADC_adc_timer_current_count_timercurrentcount_M \
0x0001FFFF // Timer count configuration
#define ADC_adc_timer_current_count_timercurrentcount_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel0FIFODATA register.
//
//******************************************************************************
#define ADC_channel0FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel0FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel1FIFODATA register.
//
//******************************************************************************
#define ADC_channel1FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel1FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel2FIFODATA register.
//
//******************************************************************************
#define ADC_channel2FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel2FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel3FIFODATA register.
//
//******************************************************************************
#define ADC_channel3FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel3FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel4FIFODATA register.
//
//******************************************************************************
#define ADC_channel4FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel4FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel5FIFODATA register.
//
//******************************************************************************
#define ADC_channel5FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel5FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel6FIFODATA register.
//
//******************************************************************************
#define ADC_channel6FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel6FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel7FIFODATA register.
//
//******************************************************************************
#define ADC_channel7FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel7FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch0_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch1_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch2_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch3_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch4_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch5_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch6_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch7_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_S 0
#endif // __HW_ADC_H__

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_aes.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_AES_H__
#define __HW_AES_H__
//*****************************************************************************
//
// The following are defines for the AES_P register offsets.
//
//*****************************************************************************
#define AES_O_KEY2_6 0x00000000 // XTS second key / CBC-MAC third
// key
#define AES_O_KEY2_7 0x00000004 // XTS second key (MSW for 256-bit
// key) / CBC-MAC third key (MSW)
#define AES_O_KEY2_4 0x00000008 // XTS / CCM second key / CBC-MAC
// third key (LSW)
#define AES_O_KEY2_5 0x0000000C // XTS second key (MSW for 192-bit
// key) / CBC-MAC third key
#define AES_O_KEY2_2 0x00000010 // XTS / CCM / CBC-MAC second key /
// Hash Key input
#define AES_O_KEY2_3 0x00000014 // XTS second key (MSW for 128-bit
// key) + CCM/CBC-MAC second key
// (MSW) / Hash Key input (MSW)
#define AES_O_KEY2_0 0x00000018 // XTS / CCM / CBC-MAC second key
// (LSW) / Hash Key input (LSW)
#define AES_O_KEY2_1 0x0000001C // XTS / CCM / CBC-MAC second key /
// Hash Key input
#define AES_O_KEY1_6 0x00000020 // Key (LSW for 256-bit key)
#define AES_O_KEY1_7 0x00000024 // Key (MSW for 256-bit key)
#define AES_O_KEY1_4 0x00000028 // Key (LSW for 192-bit key)
#define AES_O_KEY1_5 0x0000002C // Key (MSW for 192-bit key)
#define AES_O_KEY1_2 0x00000030 // Key
#define AES_O_KEY1_3 0x00000034 // Key (MSW for 128-bit key)
#define AES_O_KEY1_0 0x00000038 // Key (LSW for 128-bit key)
#define AES_O_KEY1_1 0x0000003C // Key
#define AES_O_IV_IN_0 0x00000040 // Initialization Vector input
// (LSW)
#define AES_O_IV_IN_1 0x00000044 // Initialization vector input
#define AES_O_IV_IN_2 0x00000048 // Initialization vector input
#define AES_O_IV_IN_3 0x0000004C // Initialization Vector input
// (MSW)
#define AES_O_CTRL 0x00000050 // register determines the mode of
// operation of the AES Engine
#define AES_O_C_LENGTH_0 0x00000054 // Crypto data length registers
// (LSW and MSW) store the
// cryptographic data length in
// bytes for all modes. Once
// processing with this context is
// started@@ this length decrements
// to zero. Data lengths up to (2^61
// – 1) bytes are allowed. For GCM@@
// any value up to 2^36 - 32 bytes
// can be used. This is because a
// 32-bit counter mode is used; the
// maximum number of 128-bit blocks
// is 2^32 – 2@@ resulting in a
// maximum number of bytes of 2^36 -
// 32. A write to this register
// triggers the engine to start
// using this context. This is valid
// for all modes except GCM and CCM.
// Note that for the combined
// modes@@ this length does not
// include the authentication only
// data; the authentication length
// is specified in the
// AES_AUTH_LENGTH register below.
// All modes must have a length > 0.
// For the combined modes@@ it is
// allowed to have one of the
// lengths equal to zero. For the
// basic encryption modes
// (ECB/CBC/CTR/ICM/CFB128) it is
// allowed to program zero to the
// length field; in that case the
// length is assumed infinite. All
// data must be byte (8-bit)
// aligned; bit aligned data streams
// are not supported by the AES
// Engine. For a Host read
// operation@@ these registers
// return all-zeroes.
#define AES_O_C_LENGTH_1 0x00000058 // Crypto data length registers
// (LSW and MSW) store the
// cryptographic data length in
// bytes for all modes. Once
// processing with this context is
// started@@ this length decrements
// to zero. Data lengths up to (2^61
// – 1) bytes are allowed. For GCM@@
// any value up to 2^36 - 32 bytes
// can be used. This is because a
// 32-bit counter mode is used; the
// maximum number of 128-bit blocks
// is 2^32 – 2@@ resulting in a
// maximum number of bytes of 2^36 -
// 32. A write to this register
// triggers the engine to start
// using this context. This is valid
// for all modes except GCM and CCM.
// Note that for the combined
// modes@@ this length does not
// include the authentication only
// data; the authentication length
// is specified in the
// AES_AUTH_LENGTH register below.
// All modes must have a length > 0.
// For the combined modes@@ it is
// allowed to have one of the
// lengths equal to zero. For the
// basic encryption modes
// (ECB/CBC/CTR/ICM/CFB128) it is
// allowed to program zero to the
// length field; in that case the
// length is assumed infinite. All
// data must be byte (8-bit)
// aligned; bit aligned data streams
// are not supported by the AES
// Engine. For a Host read
// operation@@ these registers
// return all-zeroes.
#define AES_O_AUTH_LENGTH 0x0000005C // AAD data length. The
// authentication length register
// store the authentication data
// length in bytes for combined
// modes only (GCM or CCM) Supported
// AAD-lengths for CCM are from 0 to
// (2^16 - 2^8) bytes. For GCM any
// value up to (2^32 - 1) bytes can
// be used. Once processing with
// this context is started@@ this
// length decrements to zero. A
// write to this register triggers
// the engine to start using this
// context for GCM and CCM. For XTS
// this register is optionally used
// to load ‘j’. Loading of ‘j’ is
// only required if ‘j’ != 0. ‘j’ is
// a 28-bit value and must be
// written to bits [31-4] of this
// register. ‘j’ represents the
// sequential number of the 128-bit
// block inside the data unit. For
// the first block in a unit@@ this
// value is zero. It is not required
// to provide a ‘j’ for each new
// data block within a unit. Note
// that it is possible to start with
// a ‘j’ unequal to zero; refer to
// Table 4 for more details. For a
// Host read operation@@ these
// registers return all-zeroes.
#define AES_O_DATA_IN_0 0x00000060 // Data register to read and write
// plaintext/ciphertext (MSW)
#define AES_O_DATA_IN_1 0x00000064 // Data register to read and write
// plaintext/ciphertext
#define AES_O_DATA_IN_2 0x00000068 // Data register to read and write
// plaintext/ciphertext
#define AES_O_DATA_IN_3 0x0000006C // Data register to read and write
// plaintext/ciphertext (LSW)
#define AES_O_TAG_OUT_0 0x00000070
#define AES_O_TAG_OUT_1 0x00000074
#define AES_O_TAG_OUT_2 0x00000078
#define AES_O_TAG_OUT_3 0x0000007C
#define AES_O_REVISION 0x00000080 // Register AES_REVISION
#define AES_O_SYSCONFIG 0x00000084 // Register AES_SYSCONFIG.This
// register configures the DMA
// signals and controls the IDLE and
// reset logic
#define AES_O_SYSSTATUS 0x00000088
#define AES_O_IRQSTATUS 0x0000008C // This register indicates the
// interrupt status. If one of the
// interrupt bits is set the
// interrupt output will be asserted
#define AES_O_IRQENABLE 0x00000090 // This register contains an enable
// bit for each unique interrupt
// generated by the module. It
// matches the layout of
// AES_IRQSTATUS register. An
// interrupt is enabled when the bit
// in this register is set to ‘1’.
// An interrupt that is enabled is
// propagated to the SINTREQUEST_x
// output. All interrupts need to be
// enabled explicitly by writing
// this register.
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_6 register.
//
//******************************************************************************
#define AES_KEY2_6_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_6_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_7 register.
//
//******************************************************************************
#define AES_KEY2_7_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_7_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_4 register.
//
//******************************************************************************
#define AES_KEY2_4_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_4_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_5 register.
//
//******************************************************************************
#define AES_KEY2_5_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_5_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_2 register.
//
//******************************************************************************
#define AES_KEY2_2_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_2_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_3 register.
//
//******************************************************************************
#define AES_KEY2_3_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_3_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_0 register.
//
//******************************************************************************
#define AES_KEY2_0_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_0_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_1 register.
//
//******************************************************************************
#define AES_KEY2_1_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_1_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_6 register.
//
//******************************************************************************
#define AES_KEY1_6_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_6_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_7 register.
//
//******************************************************************************
#define AES_KEY1_7_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_7_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_4 register.
//
//******************************************************************************
#define AES_KEY1_4_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_4_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_5 register.
//
//******************************************************************************
#define AES_KEY1_5_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_5_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_2 register.
//
//******************************************************************************
#define AES_KEY1_2_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_2_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_3 register.
//
//******************************************************************************
#define AES_KEY1_3_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_3_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_0 register.
//
//******************************************************************************
#define AES_KEY1_0_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_0_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_1 register.
//
//******************************************************************************
#define AES_KEY1_1_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_1_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_0 register.
//
//******************************************************************************
#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // IV data
#define AES_IV_IN_0_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_1 register.
//
//******************************************************************************
#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // IV data
#define AES_IV_IN_1_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_2 register.
//
//******************************************************************************
#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // IV data
#define AES_IV_IN_2_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_3 register.
//
//******************************************************************************
#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // IV data
#define AES_IV_IN_3_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_CTRL register.
//
//******************************************************************************
#define AES_CTRL_CONTEXT_READY \
0x80000000 // If ‘1’@@ this read-only status
// bit indicates that the context
// data registers can be overwritten
// and the host is permitted to
// write the next context.
#define AES_CTRL_SVCTXTRDY \
0x40000000 // If ‘1’@@ this read-only status
// bit indicates that an AES
// authentication TAG and/or IV
// block(s) is/are available for the
// host to retrieve. This bit is
// only asserted if the
// ‘save_context’ bit is set to ‘1’.
// The bit is mutual exclusive with
// the ‘context_ready’ bit.
#define AES_CTRL_SAVE_CONTEXT 0x20000000 // This bit is used to indicate
// that an authentication TAG or
// result IV needs to be stored as a
// result context. If this bit is
// set@@ context output DMA and/or
// interrupt will be asserted if the
// operation is finished and related
// signals are enabled.
#define AES_CTRL_CCM_M 0x01C00000 // Defines “M� that indicated the
// length of the authentication
// field for CCM operations; the
// authentication field length
// equals two times (the value of
// CCM-M plus one). Note that the
// AES Engine always returns a
// 128-bit authentication field@@ of
// which the M least significant
// bytes are valid. All values are
// supported.
#define AES_CTRL_CCM_S 22
#define AES_CTRL_CCM_L_M 0x00380000 // Defines “L� that indicated the
// width of the length field for CCM
// operations; the length field in
// bytes equals the value of CMM-L
// plus one. Supported values for L
// are (programmed value): 2 (1)@@ 4
// (3) and 8 (7).
#define AES_CTRL_CCM_L_S 19
#define AES_CTRL_CCM 0x00040000 // AES-CCM is selected@@ this is a
// combined mode@@ using AES for
// both authentication and
// encryption. No additional mode
// selection is required. 0 Other
// mode selected 1 ccm mode selected
#define AES_CTRL_GCM_M 0x00030000 // AES-GCM mode is selected.this is
// a combined mode@@ using the
// Galois field multiplier GF(2^128)
// for authentication and AES-CTR
// mode for encryption@@ the bits
// specify the GCM mode. 0x0 No
// operation 0x1 GHASH with H loaded
// and Y0-encrypted forced to zero
// 0x2 GHASH with H loaded and
// Y0-encrypted calculated
// internally 0x3 Autonomous GHASH
// (both H and Y0-encrypted
// calculated internally)
#define AES_CTRL_GCM_S 16
#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC is selected@@ the
// Direction bit must be set to ‘1’
// for this mode. 0 Other mode
// selected 1 cbcmac mode selected
#define AES_CTRL_F9 0x00004000 // AES f9 mode is selected@@ the
// AES key size must be set to
// 128-bit for this mode. 0 Other
// mode selected 1 f9 selected
#define AES_CTRL_F8 0x00002000 // AES f8 mode is selected@@ the
// AES key size must be set to
// 128-bit for this mode. 0 Other
// mode selected 1 f8 selected
#define AES_CTRL_XTS_M 0x00001800 // AES-XTS operation is selected;
// the bits specify the XTS mode.01
// = Previous/intermediate tweak
// value and ‘j’ loaded (value is
// loaded via IV@@ j is loaded via
// the AAD length register) 0x0 No
// operation 0x1
// Previous/intermediate tweak value
// and ‘j’ loaded (value is loaded
// via IV@@ j is loaded via the AAD
// length register) 0x2 Key2@@ i and
// j loaded (i is loaded via IV@@ j
// is loaded via the AAD length
// register) 0x3 Key2 and i loaded@@
// j=0 (i is loaded via IV)
#define AES_CTRL_XTS_S 11
#define AES_CTRL_CFB 0x00000400 // full block AES cipher feedback
// mode (CFB128) is selected. 0
// other mode selected 1 cfb
// selected
#define AES_CTRL_ICM 0x00000200 // AES integer counter mode (ICM)
// is selected@@ this is a counter
// mode with a 16-bit wide counter.
// 0 Other mode selected. 1 ICM mode
// selected
#define AES_CTRL_CTR_WIDTH_M 0x00000180 // Specifies the counter width for
// AES-CTR mode 0x0 Counter is 32
// bits 0x1 Counter is 64 bits 0x2
// Counter is 128 bits 0x3 Counter
// is 192 bits
#define AES_CTRL_CTR_WIDTH_S 7
#define AES_CTRL_CTR 0x00000040 // Tthis bit must also be set for
// GCM and CCM@@ when
// encryption/decryption is
// required. 0 Other mode selected 1
// Counter mode
#define AES_CTRL_MODE 0x00000020 // ecb/cbc mode 0 ecb mode 1 cbc
// mode
#define AES_CTRL_KEY_SIZE_M 0x00000018 // key size 0x0 reserved 0x1 Key is
// 128 bits. 0x2 Key is 192 bits 0x3
// Key is 256
#define AES_CTRL_KEY_SIZE_S 3
#define AES_CTRL_DIRECTION 0x00000004 // If set to ‘1’ an encrypt
// operation is performed. If set to
// ‘0’ a decrypt operation is
// performed. Read 0 decryption is
// selected Read 1 Encryption is
// selected
#define AES_CTRL_INPUT_READY 0x00000002 // If ‘1’@@ this read-only status
// bit indicates that the 16-byte
// input buffer is empty@@ and the
// host is permitted to write the
// next block of data.
#define AES_CTRL_OUTPUT_READY 0x00000001 // If ‘1’@@ this read-only status
// bit indicates that an AES output
// block is available for the host
// to retrieve.
//******************************************************************************
//
// The following are defines for the bit fields in the
// AES_O_C_LENGTH_0 register.
//
//******************************************************************************
//******************************************************************************
//
// The following are defines for the bit fields in the
// AES_O_C_LENGTH_1 register.
//
//******************************************************************************
#define AES_C_LENGTH_1_LENGTH_M \
0x1FFFFFFF // Data length (MSW) length
// registers (LSW and MSW) store the
// cryptographic data length in
// bytes for all modes. Once
// processing with this context is
// started@@ this length decrements
// to zero. Data lengths up to (2^61
// – 1) bytes are allowed. For GCM@@
// any value up to 2^36 - 32 bytes
// can be used. This is because a
// 32-bit counter mode is used; the
// maximum number of 128-bit blocks
// is 2^32 – 2@@ resulting in a
// maximum number of bytes of 2^36 -
// 32. A write to this register
// triggers the engine to start
// using this context. This is valid
// for all modes except GCM and CCM.
// Note that for the combined
// modes@@ this length does not
// include the authentication only
// data; the authentication length
// is specified in the
// AES_AUTH_LENGTH register below.
// All modes must have a length > 0.
// For the combined modes@@ it is
// allowed to have one of the
// lengths equal to zero. For the
// basic encryption modes
// (ECB/CBC/CTR/ICM/CFB128) it is
// allowed to program zero to the
// length field; in that case the
// length is assumed infinite. All
// data must be byte (8-bit)
// aligned; bit aligned data streams
// are not supported by the AES
// Engine. For a Host read
// operation@@ these registers
// return all-zeroes.
#define AES_C_LENGTH_1_LENGTH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// AES_O_AUTH_LENGTH register.
//
//******************************************************************************
#define AES_AUTH_LENGTH_AUTH_M \
0xFFFFFFFF // data
#define AES_AUTH_LENGTH_AUTH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_0 register.
//
//******************************************************************************
#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
#define AES_DATA_IN_0_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_1 register.
//
//******************************************************************************
#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
#define AES_DATA_IN_1_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_2 register.
//
//******************************************************************************
#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
#define AES_DATA_IN_2_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_3 register.
//
//******************************************************************************
#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
#define AES_DATA_IN_3_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_0 register.
//
//******************************************************************************
#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash result (MSW)
#define AES_TAG_OUT_0_HASH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_1 register.
//
//******************************************************************************
#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash result (MSW)
#define AES_TAG_OUT_1_HASH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_2 register.
//
//******************************************************************************
#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash result (MSW)
#define AES_TAG_OUT_2_HASH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_3 register.
//
//******************************************************************************
#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash result (LSW)
#define AES_TAG_OUT_3_HASH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_REVISION register.
//
//******************************************************************************
#define AES_REVISION_SCHEME_M 0xC0000000
#define AES_REVISION_SCHEME_S 30
#define AES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software
// compatible module family. If
// there is no level of software
// compatibility a new Func number
// (and hence REVISION) should be
// assigned.
#define AES_REVISION_FUNC_S 16
#define AES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R)@@ maintained by
// IP design owner. RTL follows a
// numbering such as X.Y.R.Z which
// are explained in this table. R
// changes ONLY when: (1) PDS
// uploads occur which may have been
// due to spec changes (2) Bug fixes
// occur (3) Resets to '0' when X or
// Y changes. Design team has an
// internal 'Z' (customer invisible)
// number which increments on every
// drop that happens due to DV and
// RTL updates. Z resets to 0 when R
// increments.
#define AES_REVISION_R_RTL_S 11
#define AES_REVISION_X_MAJOR_M \
0x00000700 // Major Revision (X)@@ maintained
// by IP specification owner. X
// changes ONLY when: (1) There is a
// major feature addition. An
// example would be adding Master
// Mode to Utopia Level2. The Func
// field (or Class/Type in old PID
// format) will remain the same. X
// does NOT change due to: (1) Bug
// fixes (2) Change in feature
// parameters.
#define AES_REVISION_X_MAJOR_S 8
#define AES_REVISION_CUSTOM_M 0x000000C0
#define AES_REVISION_CUSTOM_S 6
#define AES_REVISION_Y_MINOR_M \
0x0000003F // Minor Revision (Y)@@ maintained
// by IP specification owner. Y
// changes ONLY when: (1) Features
// are scaled (up or down).
// Flexibility exists in that this
// feature scalability may either be
// represented in the Y change or a
// specific register in the IP that
// indicates which features are
// exactly available. (2) When
// feature creeps from Is-Not list
// to Is list. But this may not be
// the case once it sees silicon; in
// which case X will change. Y does
// NOT change due to: (1) Bug fixes
// (2) Typos or clarifications (3)
// major functional/feature
// change/addition/deletion. Instead
// these changes may be reflected
// via R@@ S@@ X as applicable. Spec
// owner maintains a
// customer-invisible number 'S'
// which changes due to: (1)
// Typos/clarifications (2) Bug
// documentation. Note that this bug
// is not due to a spec change but
// due to implementation.
// Nevertheless@@ the spec tracks
// the IP bugs. An RTL release (say
// for silicon PG1.1) that occurs
// due to bug fix should document
// the corresponding spec number
// (X.Y.S) in its release notes.
#define AES_REVISION_Y_MINOR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_SYSCONFIG register.
//
//******************************************************************************
#define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \
0x00000200 // If set to '1' the two context
// out requests
// (dma_req_context_out_en@@ Bit [8]
// above@@ and context_out interrupt
// enable@@ Bit [3] of AES_IRQENABLE
// register) are mapped on the
// corresponding data output request
// bit. In this case@@ the original
// ‘context out’ bit values are
// ignored.
#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \
0x00000100 // If set to ‘1’@@ the DMA context
// output request is enabled (for
// context data out@@ e.g. TAG for
// authentication modes). 0 Dma
// disabled 1 Dma enabled
#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
0x00000080 // If set to ‘1’@@ the DMA context
// request is enabled. 0 Dma
// disabled 1 Dma enabled
#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
0x00000040 // If set to ‘1’@@ the DMA output
// request is enabled. 0 Dma
// disabled 1 Dma enabled
#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
0x00000020 // If set to ‘1’@@ the DMA input
// request is enabled. 0 Dma
// disabled 1 Dma enabled
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_SYSSTATUS register.
//
//******************************************************************************
#define AES_SYSSTATUS_RESETDONE \
0x00000001
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IRQSTATUS register.
//
//******************************************************************************
#define AES_IRQSTATUS_CONTEXT_OUT \
0x00000008 // This bit indicates
// authentication tag (and IV)
// interrupt(s) is/are active and
// triggers the interrupt output.
#define AES_IRQSTATUS_DATA_OUT \
0x00000004 // This bit indicates data output
// interrupt is active and triggers
// the interrupt output.
#define AES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input
// interrupt is active and triggers
// the interrupt output.
#define AES_IRQSTATUS_CONTEX_IN \
0x00000001 // This bit indicates context
// interrupt is active and triggers
// the interrupt output.
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IRQENABLE register.
//
//******************************************************************************
#define AES_IRQENABLE_CONTEXT_OUT \
0x00000008 // This bit indicates
// authentication tag (and IV)
// interrupt(s) is/are active and
// triggers the interrupt output.
#define AES_IRQENABLE_DATA_OUT \
0x00000004 // This bit indicates data output
// interrupt is active and triggers
// the interrupt output.
#define AES_IRQENABLE_DATA_IN 0x00000002 // This bit indicates data input
// interrupt is active and triggers
// the interrupt output.
#define AES_IRQENABLE_CONTEX_IN \
0x00000001 // This bit indicates context
// interrupt is active and triggers
// the interrupt output.
#endif // __HW_AES_H__

745
targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_config.h Executable file
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@ -0,0 +1,745 @@
/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_APPS_CONFIG_H__
#define __HW_APPS_CONFIG_H__
//*****************************************************************************
//
// The following are defines for the APPS_CONFIG register offsets.
//
//*****************************************************************************
#define APPS_CONFIG_O_PATCH_TRAP_ADDR_REG \
0x00000000 // Patch trap address Register
// array
#define APPS_CONFIG_O_PATCH_TRAP_EN_REG \
0x00000078
#define APPS_CONFIG_O_FAULT_STATUS_REG \
0x0000007C
#define APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG \
0x00000080
#define APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG \
0x00000084
#define APPS_CONFIG_O_DMA_DONE_INT_MASK \
0x0000008C
#define APPS_CONFIG_O_DMA_DONE_INT_MASK_SET \
0x00000090
#define APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR \
0x00000094
#define APPS_CONFIG_O_DMA_DONE_INT_STS_CLR \
0x00000098
#define APPS_CONFIG_O_DMA_DONE_INT_ACK \
0x0000009C
#define APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED \
0x000000A0
#define APPS_CONFIG_O_DMA_DONE_INT_STS_RAW \
0x000000A4
#define APPS_CONFIG_O_FAULT_STATUS_CLR_REG \
0x000000A8
#define APPS_CONFIG_O_RESERVD_REG_0 \
0x000000AC
#define APPS_CONFIG_O_GPT_TRIG_SEL \
0x000000B0
#define APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG \
0x000000B4
#define APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG \
0x000000B8
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_PATCH_TRAP_ADDR_REG register.
//
//******************************************************************************
#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_M \
0xFFFFFFFF // When PATCH_TRAP_EN[n] is set bus
// fault is generated for the
// address
// PATCH_TRAP_ADDR_REG[n][31:0] from
// Idcode bus. The exception routine
// should take care to jump to the
// location where the patch
// correspond to this address is
// kept.
#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_PATCH_TRAP_EN_REG register.
//
//******************************************************************************
#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_M \
0x3FFFFFFF // When PATCH_TRAP_EN[n] is set bus
// fault is generated for the
// address PATCH_TRAP_ADD[n][31:0]
// from Idcode bus. The exception
// routine should take care to jump
// to the location where the patch
// correspond to this address is
// kept.
#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_FAULT_STATUS_REG register.
//
//******************************************************************************
#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_M \
0x0000003E // This field shows because of
// which patch trap address the
// bus_fault is generated. If the
// PATCH_ERR bit is set, then it
// means the bus fault is generated
// because of
// PATCH_TRAP_ADDR_REG[2^PATCH_ERR_INDEX]
#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_S 1
#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR \
0x00000001 // This bit is set when there is a
// bus fault because of patched
// address access to the Apps boot
// rom. Write 0 to clear this
// register.
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG register.
//
//******************************************************************************
#define APPS_CONFIG_MEMSS_WR_ERR_CLR_REG_MEMSS_WR_ERR_CLR \
0x00000001 // This bit is set when there is a
// an error in memss write access.
// And the address causing this
// error is captured in
// MEMSS_ERR_ADDR_REG. To capture
// the next error address one have
// to clear this bit.
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG register.
//
//******************************************************************************
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_MASK register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_M \
0x0000F000 // 1= disable corresponding
// interrupt;0 = interrupt enabled
// bit 14: ADC channel 7 interrupt
// enable/disable bit 13: ADC
// channel 5 interrupt
// enable/disable bit 12: ADC
// channel 3 interrupt
// enable/disable bit 11: ADC
// channel 1 interrupt
// enable/disable
#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_S 12
#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_WR_DMA_DONE_INT_MASK \
0x00000800 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_RD_DMA_DONE_INT_MASK \
0x00000400 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK \
0x00000200 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_THRESHHOLD_DMA_DONE_INT_MASK \
0x00000100 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK \
0x00000080 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_RD_DMA_DONE_INT_MASK \
0x00000040 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK \
0x00000020 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_RD_DMA_DONE_INT_MASK \
0x00000010 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK \
0x00000008 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_RD_DMA_DONE_INT_MASK \
0x00000004 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_WR_DMA_DONE_INT_MASK \
0x00000002 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_RD_DMA_DONE_INT_MASK \
0x00000001 // 1= disable corresponding
// interrupt;0 = interrupt enabled
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_MASK_SET register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_M \
0x0000F000 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect bit 14: ADC channel 7 DMA
// Done IRQ bit 13: ADC channel 5
// DMA Done IRQ bit 12: ADC channel
// 3 DMA Done IRQ bit 11: ADC
// channel 1 DMA Done IRQ
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_S 12
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_WR_DMA_DONE_INT_MASK_SET \
0x00000800 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_RD_DMA_DONE_INT_MASK_SET \
0x00000400 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET \
0x00000200 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET \
0x00000100 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_WR_DMA_DONE_INT_MASK_SET \
0x00000080 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_RD_DMA_DONE_INT_MASK_SET \
0x00000040 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_WR_DMA_DONE_INT_MASK_SET \
0x00000020 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_RD_DMA_DONE_INT_MASK_SET \
0x00000010 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_WR_DMA_DONE_INT_MASK_SET \
0x00000008 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_RD_DMA_DONE_INT_MASK_SET \
0x00000004 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_WR_DMA_DONE_INT_MASK_SET \
0x00000002 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_RD_DMA_DONE_INT_MASK_SET \
0x00000001 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_M \
0x0000F000 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect bit 14: ADC channel 7 DMA
// Done IRQ mask bit 13: ADC channel
// 5 DMA Done IRQ mask bit 12: ADC
// channel 3 DMA Done IRQ mask bit
// 11: ADC channel 1 DMA Done IRQ
// mask
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_S 12
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MACASP_WR_DMA_DONE_INT_MASK_CLR \
0x00000800 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MCASP_RD_DMA_DONE_INT_MASK_CLR \
0x00000400 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR \
0x00000200 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR \
0x00000100 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_WR_DMA_DONE_INT_MASK_CLR \
0x00000080 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_RD_DMA_DONE_INT_MASK_CLR \
0x00000040 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_WR_DMA_DONE_INT_MASK_CLR \
0x00000020 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_RD_DMA_DONE_INT_MASK_CLR \
0x00000010 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_WR_DMA_DONE_INT_MASK_CLR \
0x00000008 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_RD_DMA_DONE_INT_MASK_CLR \
0x00000004 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_WR_DMA_DONE_INT_MASK_CLR \
0x00000002 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_RD_DMA_DONE_INT_MASK_CLR \
0x00000001 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_STS_CLR register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_M \
0xFFFFFFFF // write 1 or 0 to clear all
// DMA_DONE interrupt;
#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_ACK register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_M \
0x0000F000 // write 1 to clear corresponding
// interrupt; 0 = no effect; bit 14:
// ADC channel 7 DMA Done IRQ bit
// 13: ADC channel 5 DMA Done IRQ
// bit 12: ADC channel 3 DMA Done
// IRQ bit 11: ADC channel 1 DMA
// Done IRQ
#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_S 12
#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_WR_DMA_DONE_INT_ACK \
0x00000800 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_RD_DMA_DONE_INT_ACK \
0x00000400 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_FIFO_EMPTY_DMA_DONE_INT_ACK \
0x00000200 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_THRESHHOLD_DMA_DONE_INT_ACK \
0x00000100 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_WR_DMA_DONE_INT_ACK \
0x00000080 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_RD_DMA_DONE_INT_ACK \
0x00000040 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_WR_DMA_DONE_INT_ACK \
0x00000020 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_RD_DMA_DONE_INT_ACK \
0x00000010 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_WR_DMA_DONE_INT_ACK \
0x00000008 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_RD_DMA_DONE_INT_ACK \
0x00000004 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_WR_DMA_DONE_INT_ACK \
0x00000002 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_RD_DMA_DONE_INT_ACK \
0x00000001 // write 1 to clear corresponding
// interrupt; 0 = no effect;
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_M \
0x0000F000 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask bit 14: ADC
// channel 7 DMA Done IRQ bit 13:
// ADC channel 5 DMA Done IRQ bit
// 12: ADC channel 3 DMA Done IRQ
// bit 11: ADC channel 1 DMA Done
// IRQ
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_S 12
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_WR_DMA_DONE_INT_STS_MASKED \
0x00000800 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_RD_DMA_DONE_INT_STS_MASKED \
0x00000400 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED \
0x00000200 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED \
0x00000100 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_WR_DMA_DONE_INT_STS_MASKED \
0x00000080 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_RD_DMA_DONE_INT_STS_MASKED \
0x00000040 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_WR_DMA_DONE_INT_STS_MASKED \
0x00000020 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_RD_DMA_DONE_INT_STS_MASKED \
0x00000010 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_WR_DMA_DONE_INT_STS_MASKED \
0x00000008 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_RD_DMA_DONE_INT_STS_MASKED \
0x00000004 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_WR_DMA_DONE_INT_STS_MASKED \
0x00000002 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_RD_DMA_DONE_INT_STS_MASKED \
0x00000001 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_STS_RAW register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_M \
0x0000F000 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive bit 14: ADC channel 7
// DMA Done IRQ bit 13: ADC channel
// 5 DMA Done IRQ bit 12: ADC
// channel 3 DMA Done IRQ bit 11:
// ADC channel 1 DMA Done IRQ
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_S 12
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_WR_DMA_DONE_INT_STS_RAW \
0x00000800 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_RD_DMA_DONE_INT_STS_RAW \
0x00000400 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_EPMTY_FIFO_DMA_DONE_INT_STS_RAW \
0x00000200 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW \
0x00000100 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_WR_DMA_DONE_INT_STS_RAW \
0x00000080 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_RD_DMA_DONE_INT_STS_RAW \
0x00000040 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_WR_DMA_DONE_INT_STS_RAW \
0x00000020 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_RD_DMA_DONE_INT_STS_RAW \
0x00000010 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_WR_DMA_DONE_INT_STS_RAW \
0x00000008 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_RD_DMA_DONE_INT_STS_RAW \
0x00000004 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_WR_DMA_DONE_INT_STS_RAW \
0x00000002 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_RD_DMA_DONE_INT_STS_RAW \
0x00000001 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_FAULT_STATUS_CLR_REG register.
//
//******************************************************************************
#define APPS_CONFIG_FAULT_STATUS_CLR_REG_PATCH_ERR_CLR \
0x00000001 // Write 1 to clear the LSB of
// FAULT_STATUS_REG
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_RESERVD_REG_0 register.
//
//******************************************************************************
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_GPT_TRIG_SEL register.
//
//******************************************************************************
#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_M \
0x000000FF // This bit is implemented for GPT
// trigger mode select. GPT IP
// support 2 modes: RTC mode and
// external trigger. When this bit
// is set to logic '1': enable
// external trigger mode for APPS
// GPT CP0 and CP1 pin. bit 0: when
// set '1' enable external GPT
// trigger 0 on GPIO0 CP0 pin else
// RTC mode is selected. bit 1: when
// set '1' enable external GPT
// trigger 1 on GPIO0 CP1 pin else
// RTC mode is selected. bit 2: when
// set '1' enable external GPT
// trigger 2 on GPIO1 CP0 pin else
// RTC mode is selected. bit 3: when
// set '1' enable external GPT
// trigger 3 on GPIO1 CP1 pin else
// RTC mode is selected. bit 4: when
// set '1' enable external GPT
// trigger 4 on GPIO2 CP0 pin else
// RTC mode is selected. bit 5: when
// set '1' enable external GPT
// trigger 5 on GPIO2 CP1 pin else
// RTC mode is selected. bit 6: when
// set '1' enable external GPT
// trigger 6 on GPIO3 CP0 pin else
// RTC mode is selected. bit 7: when
// set '1' enable external GPT
// trigger 7 on GPIO3 CP1 pin else
// RTC mode is selected.
#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG register.
//
//******************************************************************************
#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_M \
0x00000007 // Capture data from d2d_spare pads
#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG register.
//
//******************************************************************************
#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_M \
0x00000007 // Send data to d2d_spare pads -
// eventually this will get
// registered in top die
#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_S 0
#endif // __HW_APPS_CONFIG_H__

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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_apps_rcm.h Executable file
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targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/ti/devices/cc32xx/inc/hw_camera.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_CAMERA_H__
#define __HW_CAMERA_H__
//*****************************************************************************
//
// The following are defines for the CAMERA register offsets.
//
//*****************************************************************************
#define CAMERA_O_CC_REVISION 0x00000000 // This register contains the IP
// revision code ( Parallel Mode)
#define CAMERA_O_CC_SYSCONFIG 0x00000010 // This register controls the
// various parameters of the OCP
// interface (CCP and Parallel Mode)
#define CAMERA_O_CC_SYSSTATUS 0x00000014 // This register provides status
// information about the module
// excluding the interrupt status
// information (CCP and Parallel
// Mode)
#define CAMERA_O_CC_IRQSTATUS 0x00000018 // The interrupt status regroups
// all the status of the module
// internal events that can generate
// an interrupt (CCP & Parallel
// Mode)
#define CAMERA_O_CC_IRQENABLE 0x0000001C // The interrupt enable register
// allows to enable/disable the
// module internal sources of
// interrupt on an event-by-event
// basis (CCP & Parallel Mode)
#define CAMERA_O_CC_CTRL 0x00000040 // This register controls the
// various parameters of the Camera
// Core block (CCP & Parallel Mode)
#define CAMERA_O_CC_CTRL_DMA 0x00000044 // This register controls the DMA
// interface of the Camera Core
// block (CCP & Parallel Mode)
#define CAMERA_O_CC_CTRL_XCLK 0x00000048 // This register control the value
// of the clock divisor used to
// generate the external clock
// (Parallel Mode)
#define CAMERA_O_CC_FIFO_DATA 0x0000004C // This register allows to write to
// the FIFO and read from the FIFO
// (CCP & Parallel Mode)
#define CAMERA_O_CC_TEST 0x00000050 // This register shows the status
// of some important variables of
// the camera core module (CCP &
// Parallel Mode)
#define CAMERA_O_CC_GEN_PAR 0x00000054 // This register shows the values
// of the generic parameters of the
// module
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_REVISION register.
//
//******************************************************************************
#define CAMERA_CC_REVISION_REV_M \
0x000000FF // IP revision [7:4] Major revision
// [3:0] Minor revision Examples:
// 0x10 for 1.0 0x21 for 2.1
#define CAMERA_CC_REVISION_REV_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_SYSCONFIG register.
//
//******************************************************************************
#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \
0x00000018 // Slave interface power management
// req/ack control """00""
// Force-idle. An idle request is
// acknoledged unconditionally"
// """01"" No-idle. An idle request
// is never acknowledged" """10""
// reserved (Smart-idle not
// implemented)"
#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3
#define CAMERA_CC_SYSCONFIG_SOFT_RESET \
0x00000002 // Software reset. Set this bit to
// 1 to trigger a module reset. The
// bit is automatically reset by the
// hardware. During reset it always
// returns 0. 0 Normal mode 1 The
// module is reset
#define CAMERA_CC_SYSCONFIG_AUTO_IDLE \
0x00000001 // Internal OCP clock gating
// strategy 0 OCP clock is
// free-running 1 Automatic OCP
// clock gating strategy is applied
// based on the OCP interface
// activity
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_SYSSTATUS register.
//
//******************************************************************************
#define CAMERA_CC_SYSSTATUS_RESET_DONE2 \
0x00000001 // Internal Reset Monitoring 0
// Internal module reset is on-going
// 1 Reset completed
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_IRQSTATUS register.
//
//******************************************************************************
#define CAMERA_CC_IRQSTATUS_FS_IRQ \
0x00080000 // Frame Start has occurred 0 Event
// false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_LE_IRQ \
0x00040000 // Line End has occurred 0 Event
// false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_LS_IRQ \
0x00020000 // Line Start has occurred 0 Event
// false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FE_IRQ \
0x00010000 // Frame End has occurred 0 Event
// false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \
0x00000800 // FSP code error 0 Event false "1
// Event is true (""pending"")" 0
// Event status bit unchanged 1
// Event status bit is reset
#define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \
0x00000400 // Frame Height Error 0 Event false
// "1 Event is true (""pending"")" 0
// Event status bit unchanged 1
// Event status bit is reset
#define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \
0x00000200 // False Synchronization Code 0
// Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \
0x00000100 // Shifted Synchronization Code 0
// Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \
0x00000010 // FIFO is not empty 0 Event false
// "1 Event is true (""pending"")" 0
// Event status bit unchanged 1
// Event status bit is reset
#define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \
0x00000008 // FIFO is full 0 Event false "1
// Event is true (""pending"")" 0
// Event status bit unchanged 1
// Event status bit is reset
#define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \
0x00000004 // FIFO threshold has been reached
// 0 Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \
0x00000002 // FIFO overflow has occurred 0
// Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \
0x00000001 // FIFO underflow has occurred 0
// Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_IRQENABLE register.
//
//******************************************************************************
#define CAMERA_CC_IRQENABLE_FS_IRQ_EN \
0x00080000 // Frame Start Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_LE_IRQ_EN \
0x00040000 // Line End Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_LS_IRQ_EN \
0x00020000 // Line Start Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FE_IRQ_EN \
0x00010000 // Frame End Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \
0x00000800 // FSP code Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \
0x00000400 // Frame Height Error Interrupt
// Enable 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
#define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \
0x00000200 // False Synchronization Code
// Interrupt Enable 0 Event is
// masked 1 Event generates an
// interrupt when it occurs
#define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \
0x00000100 // False Synchronization Code
// Interrupt Enable 0 Event is
// masked 1 Event generates an
// interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \
0x00000010 // FIFO Threshold Interrupt Enable
// 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
#define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \
0x00000008 // FIFO Threshold Interrupt Enable
// 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
#define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \
0x00000004 // FIFO Threshold Interrupt Enable
// 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
#define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \
0x00000002 // FIFO Overflow Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \
0x00000001 // FIFO Underflow Interrupt Enable
// 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
//******************************************************************************
//
// The following are defines for the bit fields in the CAMERA_O_CC_CTRL register.
//
//******************************************************************************
#define CAMERA_CC_CTRL_CC_IF_SYNCHRO \
0x00080000 // Synchronize all camera sensor
// inputs This must be set during
// the configuration phase before
// CC_EN set to '1'. This can be
// used in very high frequency to
// avoid dependancy to the IO
// timings. 0 No synchro (most of
// applications) 1 Synchro enabled
// (should never be required)
#define CAMERA_CC_CTRL_CC_RST 0x00040000 // Resets all the internal finite
// states machines of the camera
// core module - by writing a 1 to
// this bit. must be applied when
// CC_EN = 0 Reads returns 0
#define CAMERA_CC_CTRL_CC_FRAME_TRIG \
0x00020000 // Set the modality in which CC_EN
// works when a disabling of the
// sensor camera core is wanted "If
// CC_FRAME_TRIG = 1 by writing
// ""0"" to CC_EN" the module is
// disabled at the end of the frame
// "If CC_FRAME_TRIG = 0 by writing
// ""0"" to CC_EN" the module is
// disabled immediately
#define CAMERA_CC_CTRL_CC_EN 0x00010000 // Enables the sensor interface of
// the camera core module "By
// writing ""1"" to this field the
// module is enabled." "By writing
// ""0"" to this field the module is
// disabled at" the end of the frame
// if CC_FRAM_TRIG =1 and is
// disabled immediately if
// CC_FRAM_TRIG = 0
#define CAMERA_CC_CTRL_NOBT_SYNCHRO \
0x00002000 // Enables to start at the
// beginning of the frame or not in
// NoBT 0 Acquisition starts when
// Vertical synchro is high 1
// Acquisition starts when Vertical
// synchro goes from low to high
// (beginning of the frame) -
// Recommended.
#define CAMERA_CC_CTRL_BT_CORRECT \
0x00001000 // Enables the correction within
// the sync codes in BT mode 0
// correction is not enabled 1
// correction is enabled
#define CAMERA_CC_CTRL_PAR_ORDERCAM \
0x00000800 // Enables swap between image-data
// in parallel mode 0 swap is not
// enabled 1 swap is enabled
#define CAMERA_CC_CTRL_PAR_CLK_POL \
0x00000400 // Inverts the clock coming from
// the sensor in parallel mode 0
// clock not inverted - data sampled
// on rising edge 1 clock inverted -
// data sampled on falling edge
#define CAMERA_CC_CTRL_NOBT_HS_POL \
0x00000200 // Sets the polarity of the
// synchronization signals in NOBT
// parallel mode 0 CAM_P_HS is
// active high 1 CAM_P_HS is active
// low
#define CAMERA_CC_CTRL_NOBT_VS_POL \
0x00000100 // Sets the polarity of the
// synchronization signals in NOBT
// parallel mode 0 CAM_P_VS is
// active high 1 CAM_P_VS is active
// low
#define CAMERA_CC_CTRL_PAR_MODE_M \
0x0000000E // Sets the Protocol Mode of the
// Camera Core module in parallel
// mode (when CCP_MODE = 0) """000""
// Parallel NOBT 8-bit" """001""
// Parallel NOBT 10-bit" """010""
// Parallel NOBT 12-bit" """011""
// reserved" """100"" Parallet BT
// 8-bit" """101"" Parallel BT
// 10-bit" """110"" reserved"
// """111"" FIFO test mode. Refer to
// Table 12 - FIFO Write and Read
// access"
#define CAMERA_CC_CTRL_PAR_MODE_S 1
#define CAMERA_CC_CTRL_CCP_MODE 0x00000001 // Set the Camera Core in CCP mode
// 0 CCP mode disabled 1 CCP mode
// enabled
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_CTRL_DMA register.
//
//******************************************************************************
#define CAMERA_CC_CTRL_DMA_DMA_EN \
0x00000100 // Sets the number of dma request
// lines 0 DMA interface disabled
// The DMA request line stays
// inactive 1 DMA interface enabled
// The DMA request line is
// operational
#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \
0x0000007F // Sets the threshold of the FIFO
// the assertion of the dmarequest
// line takes place when the
// threshold is reached.
// """0000000"" threshold set to 1"
// """0000001"" threshold set to 2"
// … """1111111"" threshold set to
// 128"
#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_CTRL_XCLK register.
//
//******************************************************************************
#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \
0x0000001F // Sets the clock divisor value for
// CAM_XCLK generation. based on
// CAM_MCK (value of CAM_MCLK is
// 96MHz) """00000"" CAM_XCLK Stable
// Low Level" Divider not enabled
// """00001"" CAM_XCLK Stable High
// Level" Divider not enabled from 2
// to 30 CAM_XCLK = CAM_MCLK /
// XCLK_DIV """11111"" Bypass -
// CAM_XCLK = CAM_MCLK"
#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_FIFO_DATA register.
//
//******************************************************************************
#define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \
0xFFFFFFFF // Writes the 32-bit word into the
// FIFO Reads the 32-bit word from
// the FIFO
#define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the CAMERA_O_CC_TEST register.
//
//******************************************************************************
#define CAMERA_CC_TEST_FIFO_RD_POINTER_M \
0xFF000000 // FIFO READ Pointer This field
// shows the value of the FIFO read
// pointer Expected value ranges
// from 0 to 127
#define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24
#define CAMERA_CC_TEST_FIFO_WR_POINTER_M \
0x00FF0000 // FIFO WRITE pointer This field
// shows the value of the FIFO write
// pointer Expected value ranges
// from 0 to 127
#define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16
#define CAMERA_CC_TEST_FIFO_LEVEL_M \
0x0000FF00 // FIFO level (how many 32-bit
// words the FIFO contains) This
// field shows the value of the FIFO
// level and can assume values from
// 0 to 128
#define CAMERA_CC_TEST_FIFO_LEVEL_S 8
#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \
0x000000FF // FIFO level peak This field shows
// the max value of the FIFO level
// and can assume values from 0 to
// 128
#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_GEN_PAR register.
//
//******************************************************************************
#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \
0x00000007 // Camera Core FIFO DEPTH generic
// parameter
#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0
#endif // __HW_CAMERA_H__

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