ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

added QSPI support to target RHOMBIO_L476DMW1K

pull/10610/head
Guillermo Alonso 2019-05-07 15:44:09 +02:00 committed by adbridge
parent c015bb3011
commit e6fcada930
3 changed files with 17 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
TESTS/mbed_hal/qspi/flash_configs/flash_configs.h
View File

@ -40,6 +40,14 @@
#undef QSPI_CMD_WRITE_DPI #undef QSPI_CMD_WRITE_DPI
#undef QSPI_CMD_WRITE_QPI #undef QSPI_CMD_WRITE_QPI
#elif defined(TARGET_RHOMBIO_L476DMW1K)
#include "MT25Q_config.h" // MT25QL128ABA1EW7
/* See STM32L476 Errata Sheet, it is not possible to use Dual-/Quad-mode for the command phase */
#undef QSPI_CMD_READ_DPI
#undef QSPI_CMD_READ_QPI
#undef QSPI_CMD_WRITE_DPI
#undef QSPI_CMD_WRITE_QPI
#elif defined(TARGET_DISCO_L496AG) #elif defined(TARGET_DISCO_L496AG)
#include "MX25RXX35F_config.h" // MX25R6435F #include "MX25RXX35F_config.h" // MX25R6435F

12
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_RHOMBIO_L476DMW1K/PeripheralPins.c
View File

@ -347,36 +347,36 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // rhomb.io NMI {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // rhomb.io NMI
{PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // rhomb.io QSPI_IO0 // Connected to W25Q128JVPIQ {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // rhomb.io QSPI_IO0 // Connected to MT25QL128ABA1EW7
{NC, NC, 0} {NC, NC, 0}
}; };
MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
{PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // rhomb.io AD3 {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // rhomb.io AD3
{PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // rhomb.io QSPI_IO1 // Connected to W25Q128JVPIQ {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // rhomb.io QSPI_IO1 // Connected to MT25QL128ABA1EW7
{NC, NC, 0} {NC, NC, 0}
}; };
MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // rhomb.io SPI_A_MOSI {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // rhomb.io SPI_A_MOSI
{PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // rhomb.io QSPI_IO2 // Connected to W25Q128JVPIQ {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2 // rhomb.io QSPI_IO2 // Connected to MT25QL128ABA1EW7
{NC, NC, 0} {NC, NC, 0}
}; };
MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // rhomb.io SPI_A_MISO {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // rhomb.io SPI_A_MISO
{PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // rhomb.io QSPI_IO3 // Connected to W25Q128JVPIQ {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3 // rhomb.io QSPI_IO3 // Connected to MT25QL128ABA1EW7
{NC, NC, 0} {NC, NC, 0}
}; };
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
{PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // rhomb.io IO2 {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // rhomb.io IO2
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // rhomb.io QSPI_CLK // Connected to W25Q128JVPIQ {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK // rhomb.io QSPI_CLK // Connected to MT25QL128ABA1EW7
{NC, NC, 0} {NC, NC, 0}
}; };
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
{PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // rhomb.io QSPI_CS0 {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // rhomb.io QSPI_CS0
{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // rhomb.io QSPI_MEM_CS // Connected to W25Q128JVPIQ {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_NCS // rhomb.io QSPI_MEM_CS // Connected to MT25QL128ABA1EW7
{NC, NC, 0} {NC, NC, 0}
}; };

5
targets/targets.json
View File

@ -4227,8 +4227,8 @@
"device_name": "STM32L476VG", "device_name": "STM32L476VG",
"bootloader_supported": true "bootloader_supported": true
}, },
"RHOMBIO_L476DMW1K": { "RHOMBIO_L476DMW1K": {
"components_add": ["FLASHIAP"], "components_add": ["QSPIF", "FLASHIAP"],
"inherits": ["FAMILY_STM32"], "inherits": ["FAMILY_STM32"],
"core": "Cortex-M4F", "core": "Cortex-M4F",
"extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476VG"], "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476VG"],
@ -4256,6 +4256,7 @@
"SERIAL_FC", "SERIAL_FC",
"TRNG", "TRNG",
"FLASH", "FLASH",
"QSPI",
"MPU" "MPU"
], ],
"release_versions": ["2", "5"], "release_versions": ["2", "5"],