mirror of https://github.com/ARMmbed/mbed-os.git
Updated DSP library + build system changes
Updated CMSIS DSP to latest version (CMSIS-SP-00300-r3p2-00rel1.zip) Build system changes to be able to preprocess assembler sources before compiling them: - GCC: use gcc '-x assembler-with-cpp' - ARM: preprocess first, then assemble (two separate commands) - IAR: added macro definitions and include directories to the assembler command line Removed CORTEX_ARM_SUPPORT restriction for the DSP libraries. Tested: LPC1768 with ARM, GCC_ARM and IAR, LPC11U24 with ARM.pull/106/head
Bogdan Marinescu
parent
d7d5954f59
commit
e69956aba2
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@ -1,8 +1,8 @@
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/* ----------------------------------------------------------------------
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010 ARM Limited. All rights reserved.
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* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
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*
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*
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* $Date: 15. February 2012
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* $Date: 17. January 2013
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* $Revision: V1.1.0
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* $Revision: V1.4.1
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*
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*
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* Project: CMSIS DSP Library
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* Project: CMSIS DSP Library
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* Title: arm_abs_f32.c
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* Title: arm_abs_f32.c
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@ -11,26 +11,31 @@
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*
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*
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* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
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* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
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*
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*
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* Version 1.1.0 2012/02/15
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* Redistribution and use in source and binary forms, with or without
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* Updated with more optimizations, bug fixes and minor API changes.
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* modification, are permitted provided that the following conditions
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||||||
*
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* are met:
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||||||
* Version 1.0.10 2011/7/15
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* - Redistributions of source code must retain the above copyright
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||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
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||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
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* notice, this list of conditions and the following disclaimer in
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* Re-organized the CMSIS folders and updated documentation.
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* the documentation and/or other materials provided with the
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||||||
*
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* distribution.
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||||||
* Version 1.0.2 2010/11/11
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* - Neither the name of ARM LIMITED nor the names of its contributors
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||||||
* Documentation updated.
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* may be used to endorse or promote products derived from this
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||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
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*
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||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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||||||
*
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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||||||
* Misra-C changes done
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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||||||
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* ---------------------------------------------------------------------------- */
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* ---------------------------------------------------------------------------- */
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#include "arm_math.h"
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#include "arm_math.h"
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@ -46,11 +51,12 @@
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* Computes the absolute value of a vector on an element-by-element basis.
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* Computes the absolute value of a vector on an element-by-element basis.
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*
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*
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* <pre>
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* <pre>
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* pDst[n] = abs(pSrcA[n]), 0 <= n < blockSize.
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* pDst[n] = abs(pSrc[n]), 0 <= n < blockSize.
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* </pre>
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* </pre>
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*
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*
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* The operation can be done in-place by setting the input and output pointers to the same buffer.
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* The functions support in-place computation allowing the source and
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* There are separate functions for floating-point, Q7, Q15, and Q31 data types.
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* destination pointers to reference the same memory buffer.
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* There are separate functions for floating-point, Q7, Q15, and Q31 data types.
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*/
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*/
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/**
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/**
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@ -73,7 +79,7 @@ void arm_abs_f32(
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{
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{
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uint32_t blkCnt; /* loop counter */
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uint32_t blkCnt; /* loop counter */
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#ifndef ARM_MATH_CM0
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#ifndef ARM_MATH_CM0_FAMILY
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/* Run the below code for Cortex-M4 and Cortex-M3 */
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/* Run the below code for Cortex-M4 and Cortex-M3 */
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float32_t in1, in2, in3, in4; /* temporary variables */
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float32_t in1, in2, in3, in4; /* temporary variables */
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@ -141,7 +147,7 @@ void arm_abs_f32(
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/* Initialize blkCnt with number of samples */
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/* Initialize blkCnt with number of samples */
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blkCnt = blockSize;
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blkCnt = blockSize;
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#endif /* #ifndef ARM_MATH_CM0 */
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#endif /* #ifndef ARM_MATH_CM0_FAMILY */
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while(blkCnt > 0u)
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while(blkCnt > 0u)
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{
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{
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@ -1,8 +1,8 @@
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/* ----------------------------------------------------------------------
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010 ARM Limited. All rights reserved.
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* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
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*
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*
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* $Date: 15. February 2012
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* $Date: 17. January 2013
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* $Revision: V1.1.0
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* $Revision: V1.4.1
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*
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*
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* Project: CMSIS DSP Library
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* Project: CMSIS DSP Library
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* Title: arm_abs_q15.c
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* Title: arm_abs_q15.c
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@ -11,26 +11,31 @@
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*
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*
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* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
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* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
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*
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*
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* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
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* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
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||||||
*
|
* are met:
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||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
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* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
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*
|
* distribution.
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* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
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||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
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||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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* -------------------------------------------------------------------- */
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* -------------------------------------------------------------------- */
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#include "arm_math.h"
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#include "arm_math.h"
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@ -64,7 +69,8 @@ void arm_abs_q15(
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{
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{
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uint32_t blkCnt; /* loop counter */
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uint32_t blkCnt; /* loop counter */
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#ifndef ARM_MATH_CM0
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#ifndef ARM_MATH_CM0_FAMILY
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__SIMD32_TYPE *simd;
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/* Run the below code for Cortex-M4 and Cortex-M3 */
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/* Run the below code for Cortex-M4 and Cortex-M3 */
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@ -77,6 +83,7 @@ void arm_abs_q15(
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/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
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/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
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** a second loop below computes the remaining 1 to 3 samples. */
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** a second loop below computes the remaining 1 to 3 samples. */
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simd = __SIMD32_CONST(pDst);
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while(blkCnt > 0u)
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while(blkCnt > 0u)
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{
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{
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/* C = |A| */
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/* C = |A| */
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@ -86,19 +93,17 @@ void arm_abs_q15(
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/* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */
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/* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */
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#ifndef ARM_MATH_BIG_ENDIAN
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#ifndef ARM_MATH_BIG_ENDIAN
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*simd++ =
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*__SIMD32(pDst)++ =
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__PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
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__PKHBT(((in1 > 0) ? in1 : __QSUB16(0, in1)),
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((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
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((in2 > 0) ? in2 : __QSUB16(0, in2)), 16);
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#else
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#else
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*__SIMD32(pDst)++ =
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*simd++ =
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__PKHBT(((in2 > 0) ? in2 : __QSUB16(0, in2)),
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__PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
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((in1 > 0) ? in1 : __QSUB16(0, in1)), 16);
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((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
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#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
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#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
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@ -108,23 +113,24 @@ void arm_abs_q15(
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#ifndef ARM_MATH_BIG_ENDIAN
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#ifndef ARM_MATH_BIG_ENDIAN
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*__SIMD32(pDst)++ =
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*simd++ =
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__PKHBT(((in1 > 0) ? in1 : __QSUB16(0, in1)),
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__PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
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((in2 > 0) ? in2 : __QSUB16(0, in2)), 16);
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((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
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#else
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#else
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*__SIMD32(pDst)++ =
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*simd++ =
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__PKHBT(((in2 > 0) ? in2 : __QSUB16(0, in2)),
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__PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
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((in1 > 0) ? in1 : __QSUB16(0, in1)), 16);
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((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
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#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
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#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
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/* Decrement the loop counter */
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/* Decrement the loop counter */
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blkCnt--;
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blkCnt--;
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}
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}
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pDst = (q15_t *)simd;
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/* If the blockSize is not a multiple of 4, compute any remaining output samples here.
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/* If the blockSize is not a multiple of 4, compute any remaining output samples here.
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** No loop unrolling is used. */
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** No loop unrolling is used. */
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blkCnt = blockSize % 0x4u;
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blkCnt = blockSize % 0x4u;
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in1 = *pSrc++;
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in1 = *pSrc++;
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/* Calculate absolute value of input and then store the result in the destination buffer. */
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/* Calculate absolute value of input and then store the result in the destination buffer. */
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*pDst++ = (in1 > 0) ? in1 : __QSUB16(0, in1);
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*pDst++ = (in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1);
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/* Decrement the loop counter */
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/* Decrement the loop counter */
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blkCnt--;
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blkCnt--;
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@ -164,7 +170,7 @@ void arm_abs_q15(
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blkCnt--;
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blkCnt--;
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}
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}
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#endif /* #ifndef ARM_MATH_CM0 */
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#endif /* #ifndef ARM_MATH_CM0_FAMILY */
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}
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}
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@ -1,8 +1,8 @@
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/* ----------------------------------------------------------------------
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010 ARM Limited. All rights reserved.
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* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
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*
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*
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* $Date: 15. February 2012
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* $Date: 17. January 2013
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* $Revision: V1.1.0
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* $Revision: V1.4.1
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*
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*
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* Project: CMSIS DSP Library
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* Project: CMSIS DSP Library
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* Title: arm_abs_q31.c
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* Title: arm_abs_q31.c
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@ -11,26 +11,31 @@
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*
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*
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* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
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* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
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*
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*
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* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
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* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
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|
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#include "arm_math.h"
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#include "arm_math.h"
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@ -66,7 +71,7 @@ void arm_abs_q31(
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uint32_t blkCnt; /* loop counter */
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uint32_t blkCnt; /* loop counter */
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q31_t in; /* Input value */
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q31_t in; /* Input value */
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#ifndef ARM_MATH_CM0
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#ifndef ARM_MATH_CM0_FAMILY
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/* Run the below code for Cortex-M4 and Cortex-M3 */
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/* Run the below code for Cortex-M4 and Cortex-M3 */
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q31_t in1, in2, in3, in4;
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q31_t in1, in2, in3, in4;
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@ -85,10 +90,10 @@ void arm_abs_q31(
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in3 = *pSrc++;
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in3 = *pSrc++;
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in4 = *pSrc++;
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in4 = *pSrc++;
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*pDst++ = (in1 > 0) ? in1 : __QSUB(0, in1);
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*pDst++ = (in1 > 0) ? in1 : (q31_t)__QSUB(0, in1);
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*pDst++ = (in2 > 0) ? in2 : __QSUB(0, in2);
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*pDst++ = (in2 > 0) ? in2 : (q31_t)__QSUB(0, in2);
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*pDst++ = (in3 > 0) ? in3 : __QSUB(0, in3);
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*pDst++ = (in3 > 0) ? in3 : (q31_t)__QSUB(0, in3);
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*pDst++ = (in4 > 0) ? in4 : __QSUB(0, in4);
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*pDst++ = (in4 > 0) ? in4 : (q31_t)__QSUB(0, in4);
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/* Decrement the loop counter */
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/* Decrement the loop counter */
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blkCnt--;
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blkCnt--;
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@ -105,14 +110,14 @@ void arm_abs_q31(
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/* Initialize blkCnt with number of samples */
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/* Initialize blkCnt with number of samples */
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blkCnt = blockSize;
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blkCnt = blockSize;
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|
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#endif /* #ifndef ARM_MATH_CM0 */
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#endif /* #ifndef ARM_MATH_CM0_FAMILY */
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|
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while(blkCnt > 0u)
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while(blkCnt > 0u)
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{
|
{
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/* C = |A| */
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/* C = |A| */
|
||||||
/* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
|
/* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
|
||||||
in = *pSrc++;
|
in = *pSrc++;
|
||||||
*pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in);
|
*pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
|
||||||
|
|
||||||
/* Decrement the loop counter */
|
/* Decrement the loop counter */
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_abs_q7.c
|
* Title: arm_abs_q7.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -69,7 +74,7 @@ void arm_abs_q7(
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
q7_t in; /* Input value1 */
|
q7_t in; /* Input value1 */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t in1, in2, in3, in4; /* temporary input variables */
|
q31_t in1, in2, in3, in4; /* temporary input variables */
|
||||||
|
|
@ -89,22 +94,22 @@ void arm_abs_q7(
|
||||||
in3 = (q31_t) * (pSrc + 2);
|
in3 = (q31_t) * (pSrc + 2);
|
||||||
|
|
||||||
/* find absolute value */
|
/* find absolute value */
|
||||||
out1 = (in1 > 0) ? in1 : __QSUB8(0, in1);
|
out1 = (in1 > 0) ? in1 : (q31_t)__QSUB8(0, in1);
|
||||||
|
|
||||||
/* read input */
|
/* read input */
|
||||||
in4 = (q31_t) * (pSrc + 3);
|
in4 = (q31_t) * (pSrc + 3);
|
||||||
|
|
||||||
/* find absolute value */
|
/* find absolute value */
|
||||||
out2 = (in2 > 0) ? in2 : __QSUB8(0, in2);
|
out2 = (in2 > 0) ? in2 : (q31_t)__QSUB8(0, in2);
|
||||||
|
|
||||||
/* store result to destination */
|
/* store result to destination */
|
||||||
*pDst = (q7_t) out1;
|
*pDst = (q7_t) out1;
|
||||||
|
|
||||||
/* find absolute value */
|
/* find absolute value */
|
||||||
out3 = (in3 > 0) ? in3 : __QSUB8(0, in3);
|
out3 = (in3 > 0) ? in3 : (q31_t)__QSUB8(0, in3);
|
||||||
|
|
||||||
/* find absolute value */
|
/* find absolute value */
|
||||||
out4 = (in4 > 0) ? in4 : __QSUB8(0, in4);
|
out4 = (in4 > 0) ? in4 : (q31_t)__QSUB8(0, in4);
|
||||||
|
|
||||||
/* store result to destination */
|
/* store result to destination */
|
||||||
*(pDst + 1) = (q7_t) out2;
|
*(pDst + 1) = (q7_t) out2;
|
||||||
|
|
@ -131,7 +136,7 @@ void arm_abs_q7(
|
||||||
/* Run the below code for Cortex-M0 */
|
/* Run the below code for Cortex-M0 */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif // #define ARM_MATH_CM0
|
#endif // #define ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_add_f32.c
|
* Title: arm_add_f32.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -73,7 +78,7 @@ void arm_add_f32(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */
|
float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */
|
||||||
|
|
@ -127,7 +132,7 @@ void arm_add_f32(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_add_q15.c
|
* Title: arm_add_q15.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -66,7 +71,7 @@ void arm_add_q15(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t inA1, inA2, inB1, inB2;
|
q31_t inA1, inA2, inB1, inB2;
|
||||||
|
|
@ -125,7 +130,7 @@ void arm_add_q15(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_add_q31.c
|
* Title: arm_add_q31.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -67,7 +72,7 @@ void arm_add_q31(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t inA1, inA2, inA3, inA4;
|
q31_t inA1, inA2, inA3, inA4;
|
||||||
|
|
@ -134,7 +139,7 @@ void arm_add_q31(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_add_q7.c
|
* Title: arm_add_q7.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -66,7 +71,7 @@ void arm_add_q7(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -119,7 +124,7 @@ void arm_add_q7(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_dot_prod_f32.c
|
* Title: arm_dot_prod_f32.c
|
||||||
|
|
@ -11,39 +11,49 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @ingroup groupMath
|
* @ingroup groupMath
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @defgroup dot_prod Vector Dot Product
|
* @defgroup dot_prod Vector Dot Product
|
||||||
*
|
*
|
||||||
* Computes the dot product of two vectors.
|
* Computes the dot product of two vectors.
|
||||||
* The vectors are multiplied element-by-element and then summed.
|
* The vectors are multiplied element-by-element and then summed.
|
||||||
|
*
|
||||||
|
* <pre>
|
||||||
|
* sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
|
||||||
|
* </pre>
|
||||||
|
*
|
||||||
* There are separate functions for floating-point, Q7, Q15, and Q31 data types.
|
* There are separate functions for floating-point, Q7, Q15, and Q31 data types.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
@ -72,7 +82,7 @@ void arm_dot_prod_f32(
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
/*loop Unrolling */
|
/*loop Unrolling */
|
||||||
|
|
@ -104,7 +114,7 @@ void arm_dot_prod_f32(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_dot_prod_q15.c
|
* Title: arm_dot_prod_q15.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -70,7 +75,7 @@ void arm_dot_prod_q15(
|
||||||
q63_t sum = 0; /* Temporary result storage */
|
q63_t sum = 0; /* Temporary result storage */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -123,7 +128,7 @@ void arm_dot_prod_q15(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
/* Store the result in the destination buffer in 34.30 format */
|
/* Store the result in the destination buffer in 34.30 format */
|
||||||
*result = sum;
|
*result = sum;
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_dot_prod_q31.c
|
* Title: arm_dot_prod_q31.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -72,7 +77,7 @@ void arm_dot_prod_q31(
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t inA1, inA2, inA3, inA4;
|
q31_t inA1, inA2, inA3, inA4;
|
||||||
|
|
@ -116,7 +121,7 @@ void arm_dot_prod_q31(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_dot_prod_q7.c
|
* Title: arm_dot_prod_q7.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -71,7 +76,7 @@ void arm_dot_prod_q7(
|
||||||
|
|
||||||
q31_t sum = 0; /* Temporary variables to store output */
|
q31_t sum = 0; /* Temporary variables to store output */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -142,7 +147,7 @@ void arm_dot_prod_q7(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
|
|
||||||
/* Store the result in the destination buffer in 18.14 format */
|
/* Store the result in the destination buffer in 18.14 format */
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_mult_f32.c
|
* Title: arm_mult_f32.c
|
||||||
|
|
@ -11,29 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.5 2010/04/26
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* incorporated review comments and updated with latest CMSIS layer
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.3 2010/03/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Initial version
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -75,7 +77,7 @@ void arm_mult_f32(
|
||||||
uint32_t blockSize)
|
uint32_t blockSize)
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counters */
|
uint32_t blkCnt; /* loop counters */
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
float32_t inA1, inA2, inA3, inA4; /* temporary input variables */
|
float32_t inA1, inA2, inA3, inA4; /* temporary input variables */
|
||||||
|
|
@ -154,7 +156,7 @@ void arm_mult_f32(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_mult_q15.c
|
* Title: arm_mult_q15.c
|
||||||
|
|
@ -11,29 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.5 2010/04/26
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* incorporated review comments and updated with latest CMSIS layer
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.3 2010/03/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Initial version
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -70,7 +72,7 @@ void arm_mult_q15(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counters */
|
uint32_t blkCnt; /* loop counters */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t inA1, inA2, inB1, inB2; /* temporary input variables */
|
q31_t inA1, inA2, inB1, inB2; /* temporary input variables */
|
||||||
|
|
@ -133,7 +135,7 @@ void arm_mult_q15(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_mult_q31.c
|
* Title: arm_mult_q31.c
|
||||||
|
|
@ -11,29 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.5 2010/04/26
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* incorporated review comments and updated with latest CMSIS layer
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.3 2010/03/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Initial version
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -69,7 +71,7 @@ void arm_mult_q31(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counters */
|
uint32_t blkCnt; /* loop counters */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t inA1, inA2, inA3, inA4; /* temporary input variables */
|
q31_t inA1, inA2, inA3, inA4; /* temporary input variables */
|
||||||
|
|
@ -124,7 +126,7 @@ void arm_mult_q31(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_mult_q7.c
|
* Title: arm_mult_q7.c
|
||||||
|
|
@ -11,32 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.5 2010/04/26
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* incorporated review comments and updated with latest CMSIS layer
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
*
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
* Version 0.0.3 2010/03/10 DP
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* Initial version
|
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -72,7 +71,7 @@ void arm_mult_q7(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counters */
|
uint32_t blkCnt; /* loop counters */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q7_t out1, out2, out3, out4; /* Temporary variables to store the product */
|
q7_t out1, out2, out3, out4; /* Temporary variables to store the product */
|
||||||
|
|
@ -109,7 +108,7 @@ void arm_mult_q7(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_negate_f32.c
|
* Title: arm_negate_f32.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -47,6 +52,10 @@
|
||||||
* <pre>
|
* <pre>
|
||||||
* pDst[n] = -pSrc[n], 0 <= n < blockSize.
|
* pDst[n] = -pSrc[n], 0 <= n < blockSize.
|
||||||
* </pre>
|
* </pre>
|
||||||
|
*
|
||||||
|
* The functions support in-place computation allowing the source and
|
||||||
|
* destination pointers to reference the same memory buffer.
|
||||||
|
* There are separate functions for floating-point, Q7, Q15, and Q31 data types.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -70,7 +79,7 @@ void arm_negate_f32(
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
float32_t in1, in2, in3, in4; /* temporary variables */
|
float32_t in1, in2, in3, in4; /* temporary variables */
|
||||||
|
|
@ -119,7 +128,7 @@ void arm_negate_f32(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_negate_q15.c
|
* Title: arm_negate_q15.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
||||||
|
|
@ -68,7 +73,7 @@ void arm_negate_q15(
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
q15_t in;
|
q15_t in;
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -118,7 +123,7 @@ void arm_negate_q15(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_negate_q31.c
|
* Title: arm_negate_q31.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -65,7 +70,7 @@ void arm_negate_q31(
|
||||||
q31_t in; /* Temporary variable */
|
q31_t in; /* Temporary variable */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t in1, in2, in3, in4;
|
q31_t in1, in2, in3, in4;
|
||||||
|
|
@ -104,7 +109,7 @@ void arm_negate_q31(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
|
|
@ -112,7 +117,7 @@ void arm_negate_q31(
|
||||||
/* C = -A */
|
/* C = -A */
|
||||||
/* Negate and then store the result in the destination buffer. */
|
/* Negate and then store the result in the destination buffer. */
|
||||||
in = *pSrc++;
|
in = *pSrc++;
|
||||||
*pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
|
*pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
|
||||||
|
|
||||||
/* Decrement the loop counter */
|
/* Decrement the loop counter */
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_negate_q7.c
|
* Title: arm_negate_q7.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -65,7 +70,7 @@ void arm_negate_q7(
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
q7_t in;
|
q7_t in;
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t input; /* Input values1-4 */
|
q31_t input; /* Input values1-4 */
|
||||||
|
|
@ -101,7 +106,7 @@ void arm_negate_q7(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_offset_f32.c
|
* Title: arm_offset_f32.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
||||||
|
|
@ -47,7 +52,9 @@
|
||||||
* pDst[n] = pSrc[n] + offset, 0 <= n < blockSize.
|
* pDst[n] = pSrc[n] + offset, 0 <= n < blockSize.
|
||||||
* </pre>
|
* </pre>
|
||||||
*
|
*
|
||||||
* There are separate functions for floating-point, Q7, Q15, and Q31 data types.
|
* The functions support in-place computation allowing the source and
|
||||||
|
* destination pointers to reference the same memory buffer.
|
||||||
|
* There are separate functions for floating-point, Q7, Q15, and Q31 data types.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -73,7 +80,7 @@ void arm_offset_f32(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
float32_t in1, in2, in3, in4;
|
float32_t in1, in2, in3, in4;
|
||||||
|
|
@ -140,7 +147,7 @@ void arm_offset_f32(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_offset_q15.c
|
* Title: arm_offset_q15.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -66,7 +71,7 @@ void arm_offset_q15(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t offset_packed; /* Offset packed to 32 bit */
|
q31_t offset_packed; /* Offset packed to 32 bit */
|
||||||
|
|
@ -122,7 +127,7 @@ void arm_offset_q15(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_offset_q31.c
|
* Title: arm_offset_q31.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -66,7 +71,7 @@ void arm_offset_q31(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t in1, in2, in3, in4;
|
q31_t in1, in2, in3, in4;
|
||||||
|
|
@ -126,7 +131,7 @@ void arm_offset_q31(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_offset_q7.c
|
* Title: arm_offset_q7.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -66,7 +71,7 @@ void arm_offset_q7(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t offset_packed; /* Offset packed to 32 bit */
|
q31_t offset_packed; /* Offset packed to 32 bit */
|
||||||
|
|
@ -121,7 +126,7 @@ void arm_offset_q7(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_scale_f32.c
|
* Title: arm_scale_f32.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -61,6 +66,9 @@
|
||||||
* <pre>
|
* <pre>
|
||||||
* scale = scaleFract * 2^shift.
|
* scale = scaleFract * 2^shift.
|
||||||
* </pre>
|
* </pre>
|
||||||
|
*
|
||||||
|
* The functions support in-place computation allowing the source and destination
|
||||||
|
* pointers to reference the same memory buffer.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -85,7 +93,7 @@ void arm_scale_f32(
|
||||||
uint32_t blockSize)
|
uint32_t blockSize)
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
float32_t in1, in2, in3, in4; /* temporary variabels */
|
float32_t in1, in2, in3, in4; /* temporary variabels */
|
||||||
|
|
@ -143,7 +151,7 @@ void arm_scale_f32(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_scale_q15.c
|
* Title: arm_scale_q15.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -70,7 +75,7 @@ void arm_scale_q15(
|
||||||
int8_t kShift = 15 - shift; /* shift to apply after scaling */
|
int8_t kShift = 15 - shift; /* shift to apply after scaling */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q15_t in1, in2, in3, in4;
|
q15_t in1, in2, in3, in4;
|
||||||
|
|
@ -148,7 +153,7 @@ void arm_scale_q15(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,62 +1,67 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. May 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_scale_q31.c
|
* Title: arm_scale_q31.c
|
||||||
*
|
*
|
||||||
* Description: Multiplies a Q31 vector by a scalar.
|
* Description: Multiplies a Q31 vector by a scalar.
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* - Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this
|
||||||
|
* software without specific prior written permission.
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
*
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Version 1.0.10 2011/7/15
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
*
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Version 1.0.3 2010/11/29
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
*
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Version 1.0.2 2010/11/11
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
* Documentation updated.
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
*
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* Version 1.0.1 2010/10/05
|
|
||||||
* Production release and review comments incorporated.
|
|
||||||
*
|
|
||||||
* Version 1.0.0 2010/09/20
|
|
||||||
* Production release and review comments incorporated
|
|
||||||
*
|
|
||||||
* Version 0.0.7 2010/06/10
|
|
||||||
* Misra-C changes done
|
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @ingroup groupMath
|
* @ingroup groupMath
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @addtogroup scale
|
* @addtogroup scale
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Multiplies a Q31 vector by a scalar.
|
* @brief Multiplies a Q31 vector by a scalar.
|
||||||
* @param[in] *pSrc points to the input vector
|
* @param[in] *pSrc points to the input vector
|
||||||
* @param[in] scaleFract fractional portion of the scale value
|
* @param[in] scaleFract fractional portion of the scale value
|
||||||
* @param[in] shift number of bits to shift the result by
|
* @param[in] shift number of bits to shift the result by
|
||||||
* @param[out] *pDst points to the output vector
|
* @param[out] *pDst points to the output vector
|
||||||
* @param[in] blockSize number of samples in the vector
|
* @param[in] blockSize number of samples in the vector
|
||||||
* @return none.
|
* @return none.
|
||||||
*
|
*
|
||||||
* <b>Scaling and Overflow Behavior:</b>
|
* <b>Scaling and Overflow Behavior:</b>
|
||||||
* \par
|
* \par
|
||||||
* The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.31 format.
|
* The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.31 format.
|
||||||
* These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
|
* These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
void arm_scale_q31(
|
void arm_scale_q31(
|
||||||
|
|
@ -71,7 +76,7 @@ void arm_scale_q31(
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
q31_t in, out;
|
q31_t in, out;
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -84,7 +89,7 @@ void arm_scale_q31(
|
||||||
|
|
||||||
if(sign == 0u)
|
if(sign == 0u)
|
||||||
{
|
{
|
||||||
/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
|
/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
|
||||||
** a second loop below computes the remaining 1 to 3 samples. */
|
** a second loop below computes the remaining 1 to 3 samples. */
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
@ -138,9 +143,7 @@ void arm_scale_q31(
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
kShift = -kShift;
|
/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
|
||||||
|
|
||||||
/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
|
|
||||||
** a second loop below computes the remaining 1 to 3 samples. */
|
** a second loop below computes the remaining 1 to 3 samples. */
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
@ -157,11 +160,11 @@ void arm_scale_q31(
|
||||||
in4 = ((q63_t) in4 * scaleFract) >> 32;
|
in4 = ((q63_t) in4 * scaleFract) >> 32;
|
||||||
|
|
||||||
/* apply shifting */
|
/* apply shifting */
|
||||||
out1 = in1 >> kShift;
|
out1 = in1 >> -kShift;
|
||||||
out2 = in2 >> kShift;
|
out2 = in2 >> -kShift;
|
||||||
|
|
||||||
out3 = in3 >> kShift;
|
out3 = in3 >> -kShift;
|
||||||
out4 = in4 >> kShift;
|
out4 = in4 >> -kShift;
|
||||||
|
|
||||||
/* Store result destination */
|
/* Store result destination */
|
||||||
*pDst = out1;
|
*pDst = out1;
|
||||||
|
|
@ -178,46 +181,59 @@ void arm_scale_q31(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
/* If the blockSize is not a multiple of 4, compute any remaining output samples here.
|
/* If the blockSize is not a multiple of 4, compute any remaining output samples here.
|
||||||
** No loop unrolling is used. */
|
** No loop unrolling is used. */
|
||||||
blkCnt = blockSize % 0x4u;
|
blkCnt = blockSize % 0x4u;
|
||||||
|
|
||||||
#else
|
#else
|
||||||
|
|
||||||
/* Run the below code for Cortex-M0 */
|
/* Run the below code for Cortex-M0 */
|
||||||
if(sign != 0u)
|
|
||||||
kShift = -kShift;
|
|
||||||
|
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
if(sign == 0)
|
||||||
{
|
{
|
||||||
/* C = A * scale */
|
while(blkCnt > 0u)
|
||||||
/* Scale the input and then store the result in the destination buffer. */
|
{
|
||||||
in = *pSrc++;
|
/* C = A * scale */
|
||||||
in = ((q63_t) in * scaleFract) >> 32;
|
/* Scale the input and then store the result in the destination buffer. */
|
||||||
|
in = *pSrc++;
|
||||||
|
in = ((q63_t) in * scaleFract) >> 32;
|
||||||
|
|
||||||
if(sign == 0)
|
out = in << kShift;
|
||||||
{
|
|
||||||
out = in << kShift;
|
if(in != (out >> kShift))
|
||||||
if(in != (out >> kShift))
|
out = 0x7FFFFFFF ^ (in >> 31);
|
||||||
out = 0x7FFFFFFF ^ (in >> 31);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
out = in >> kShift;
|
|
||||||
}
|
|
||||||
|
|
||||||
*pDst++ = out;
|
*pDst++ = out;
|
||||||
|
|
||||||
/* Decrement the loop counter */
|
/* Decrement the loop counter */
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
while(blkCnt > 0u)
|
||||||
|
{
|
||||||
|
/* C = A * scale */
|
||||||
|
/* Scale the input and then store the result in the destination buffer. */
|
||||||
|
in = *pSrc++;
|
||||||
|
in = ((q63_t) in * scaleFract) >> 32;
|
||||||
|
|
||||||
|
out = in >> -kShift;
|
||||||
|
|
||||||
|
*pDst++ = out;
|
||||||
|
|
||||||
|
/* Decrement the loop counter */
|
||||||
|
blkCnt--;
|
||||||
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @} end of scale group
|
* @} end of scale group
|
||||||
*/
|
*/
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_scale_q7.c
|
* Title: arm_scale_q7.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -69,7 +74,7 @@ void arm_scale_q7(
|
||||||
int8_t kShift = 7 - shift; /* shift to apply after scaling */
|
int8_t kShift = 7 - shift; /* shift to apply after scaling */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */
|
q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */
|
||||||
|
|
@ -135,7 +140,7 @@ void arm_scale_q7(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_shift_q15.c
|
* Title: arm_shift_q15.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -67,7 +72,7 @@ void arm_shift_q15(
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
uint8_t sign; /* Sign of shiftBits */
|
uint8_t sign; /* Sign of shiftBits */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -234,7 +239,7 @@ void arm_shift_q15(
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_shift_q31.c
|
* Title: arm_shift_q31.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -51,6 +56,9 @@
|
||||||
*
|
*
|
||||||
* If <code>shift</code> is positive then the elements of the vector are shifted to the left.
|
* If <code>shift</code> is positive then the elements of the vector are shifted to the left.
|
||||||
* If <code>shift</code> is negative then the elements of the vector are shifted to the right.
|
* If <code>shift</code> is negative then the elements of the vector are shifted to the right.
|
||||||
|
*
|
||||||
|
* The functions support in-place computation allowing the source and destination
|
||||||
|
* pointers to reference the same memory buffer.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -82,7 +90,7 @@ void arm_shift_q31(
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */
|
uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
q31_t in1, in2, in3, in4; /* Temporary input variables */
|
q31_t in1, in2, in3, in4; /* Temporary input variables */
|
||||||
q31_t out1, out2, out3, out4; /* Temporary output variables */
|
q31_t out1, out2, out3, out4; /* Temporary output variables */
|
||||||
|
|
@ -173,7 +181,7 @@ void arm_shift_q31(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_shift_q7.c
|
* Title: arm_shift_q7.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -72,7 +77,7 @@ void arm_shift_q7(
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
uint8_t sign; /* Sign of shiftBits */
|
uint8_t sign; /* Sign of shiftBits */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q7_t in1; /* Input value1 */
|
q7_t in1; /* Input value1 */
|
||||||
|
|
@ -207,7 +212,7 @@ void arm_shift_q7(
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_sub_f32.c
|
* Title: arm_sub_f32.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -74,7 +79,7 @@ void arm_sub_f32(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
float32_t inA1, inA2, inA3, inA4; /* temporary variables */
|
float32_t inA1, inA2, inA3, inA4; /* temporary variables */
|
||||||
|
|
@ -127,7 +132,7 @@ void arm_sub_f32(
|
||||||
/* Initialize blkCnt with number of samples */
|
/* Initialize blkCnt with number of samples */
|
||||||
blkCnt = blockSize;
|
blkCnt = blockSize;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_sub_q15.c
|
* Title: arm_sub_q15.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -67,7 +72,7 @@ void arm_sub_q15(
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t inA1, inA2;
|
q31_t inA1, inA2;
|
||||||
|
|
@ -125,7 +130,7 @@ void arm_sub_q15(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_sub_q31.c
|
* Title: arm_sub_q31.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -67,7 +72,7 @@ void arm_sub_q31(
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t inA1, inA2, inA3, inA4;
|
q31_t inA1, inA2, inA3, inA4;
|
||||||
|
|
@ -132,7 +137,7 @@ void arm_sub_q31(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_sub_q7.c
|
* Title: arm_sub_q7.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -66,7 +71,7 @@ void arm_sub_q7(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -116,7 +121,7 @@ void arm_sub_q7(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_conj_f32.c
|
* Title: arm_cmplx_conj_f32.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
||||||
|
|
@ -78,7 +86,7 @@ void arm_cmplx_conj_f32(
|
||||||
{
|
{
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
float32_t inR1, inR2, inR3, inR4;
|
float32_t inR1, inR2, inR3, inR4;
|
||||||
|
|
@ -155,7 +163,7 @@ void arm_cmplx_conj_f32(
|
||||||
/* Run the below code for Cortex-M0 */
|
/* Run the below code for Cortex-M0 */
|
||||||
blkCnt = numSamples;
|
blkCnt = numSamples;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_conj_q15.c
|
* Title: arm_cmplx_conj_q15.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -60,7 +68,7 @@ void arm_cmplx_conj_q15(
|
||||||
uint32_t numSamples)
|
uint32_t numSamples)
|
||||||
{
|
{
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
@ -144,7 +152,7 @@ void arm_cmplx_conj_q15(
|
||||||
numSamples--;
|
numSamples--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_conj_q31.c
|
* Title: arm_cmplx_conj_q31.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
||||||
|
|
@ -61,7 +69,7 @@ void arm_cmplx_conj_q31(
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
q31_t in; /* Input value */
|
q31_t in; /* Input value */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t inR1, inR2, inR3, inR4; /* Temporary real variables */
|
q31_t inR1, inR2, inR3, inR4; /* Temporary real variables */
|
||||||
|
|
@ -151,7 +159,7 @@ void arm_cmplx_conj_q31(
|
||||||
blkCnt = numSamples;
|
blkCnt = numSamples;
|
||||||
|
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
@ -160,7 +168,7 @@ void arm_cmplx_conj_q31(
|
||||||
/* Saturated to 0x7fffffff if the input is -1(0x80000000) */
|
/* Saturated to 0x7fffffff if the input is -1(0x80000000) */
|
||||||
*pDst++ = *pSrc++;
|
*pDst++ = *pSrc++;
|
||||||
in = *pSrc++;
|
in = *pSrc++;
|
||||||
*pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
|
*pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
|
||||||
|
|
||||||
/* Decrement the loop counter */
|
/* Decrement the loop counter */
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_dot_prod_f32.c
|
* Title: arm_cmplx_dot_prod_f32.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -86,7 +94,7 @@ void arm_cmplx_dot_prod_f32(
|
||||||
{
|
{
|
||||||
float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result storage */
|
float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result storage */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
@ -148,7 +156,7 @@ void arm_cmplx_dot_prod_f32(
|
||||||
numSamples--;
|
numSamples--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
/* Store the real and imaginary results in the destination buffers */
|
/* Store the real and imaginary results in the destination buffers */
|
||||||
*realResult = real_sum;
|
*realResult = real_sum;
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_dot_prod_q15.c
|
* Title: arm_cmplx_dot_prod_q15.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -68,7 +76,7 @@ void arm_cmplx_dot_prod_q15(
|
||||||
{
|
{
|
||||||
q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
|
q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
@ -130,7 +138,7 @@ void arm_cmplx_dot_prod_q15(
|
||||||
numSamples--;
|
numSamples--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
/* Store the real and imaginary results in 8.24 format */
|
/* Store the real and imaginary results in 8.24 format */
|
||||||
/* Convert real data in 34.30 to 8.24 by 6 right shifts */
|
/* Convert real data in 34.30 to 8.24 by 6 right shifts */
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_dot_prod_q31.c
|
* Title: arm_cmplx_dot_prod_q31.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -69,7 +77,7 @@ void arm_cmplx_dot_prod_q31(
|
||||||
{
|
{
|
||||||
q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
|
q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
@ -133,7 +141,7 @@ void arm_cmplx_dot_prod_q31(
|
||||||
numSamples--;
|
numSamples--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
/* Store the real and imaginary results in 16.48 format */
|
/* Store the real and imaginary results in 16.48 format */
|
||||||
*realResult = real_sum;
|
*realResult = real_sum;
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_mag_f32.c
|
* Title: arm_cmplx_mag_f32.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -80,7 +88,7 @@ void arm_cmplx_mag_f32(
|
||||||
{
|
{
|
||||||
float32_t realIn, imagIn; /* Temporary variables to hold input values */
|
float32_t realIn, imagIn; /* Temporary variables to hold input values */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
@ -148,7 +156,7 @@ void arm_cmplx_mag_f32(
|
||||||
numSamples--;
|
numSamples--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_mag_q15.c
|
* Title: arm_cmplx_mag_q15.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -61,7 +69,7 @@ void arm_cmplx_mag_q15(
|
||||||
{
|
{
|
||||||
q31_t acc0, acc1; /* Accumulators */
|
q31_t acc0, acc1; /* Accumulators */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
@ -136,7 +144,7 @@ void arm_cmplx_mag_q15(
|
||||||
numSamples--;
|
numSamples--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_mag_q31.c
|
* Title: arm_cmplx_mag_q31.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -63,7 +71,7 @@ void arm_cmplx_mag_q31(
|
||||||
q31_t acc0, acc1; /* Accumulators */
|
q31_t acc0, acc1; /* Accumulators */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
q31_t real1, real2, imag1, imag2; /* Temporary variables to hold input values */
|
q31_t real1, real2, imag1, imag2; /* Temporary variables to hold input values */
|
||||||
|
|
@ -155,7 +163,7 @@ void arm_cmplx_mag_q31(
|
||||||
/* Run the below code for Cortex-M0 */
|
/* Run the below code for Cortex-M0 */
|
||||||
blkCnt = numSamples;
|
blkCnt = numSamples;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_mag_squared_f32.c
|
* Title: arm_cmplx_mag_squared_f32.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
||||||
|
|
@ -81,7 +89,7 @@ void arm_cmplx_mag_squared_f32(
|
||||||
float32_t real, imag; /* Temporary variables to store real and imaginary values */
|
float32_t real, imag; /* Temporary variables to store real and imaginary values */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
float32_t real1, real2, real3, real4; /* Temporary variables to hold real values */
|
float32_t real1, real2, real3, real4; /* Temporary variables to hold real values */
|
||||||
float32_t imag1, imag2, imag3, imag4; /* Temporary variables to hold imaginary values */
|
float32_t imag1, imag2, imag3, imag4; /* Temporary variables to hold imaginary values */
|
||||||
float32_t mul1, mul2, mul3, mul4; /* Temporary variables */
|
float32_t mul1, mul2, mul3, mul4; /* Temporary variables */
|
||||||
|
|
@ -185,7 +193,7 @@ void arm_cmplx_mag_squared_f32(
|
||||||
|
|
||||||
blkCnt = numSamples;
|
blkCnt = numSamples;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_mag_squared_q15.c
|
* Title: arm_cmplx_mag_squared_q15.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -60,7 +68,7 @@ void arm_cmplx_mag_squared_q15(
|
||||||
{
|
{
|
||||||
q31_t acc0, acc1; /* Accumulators */
|
q31_t acc0, acc1; /* Accumulators */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
@ -131,7 +139,7 @@ void arm_cmplx_mag_squared_q15(
|
||||||
numSamples--;
|
numSamples--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_mag_squared_q31.c
|
* Title: arm_cmplx_mag_squared_q31.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------- */
|
* ---------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -63,7 +71,7 @@ void arm_cmplx_mag_squared_q31(
|
||||||
q31_t real, imag; /* Temporary variables to store real and imaginary values */
|
q31_t real, imag; /* Temporary variables to store real and imaginary values */
|
||||||
q31_t acc0, acc1; /* Accumulators */
|
q31_t acc0, acc1; /* Accumulators */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
uint32_t blkCnt; /* loop counter */
|
uint32_t blkCnt; /* loop counter */
|
||||||
|
|
@ -144,7 +152,7 @@ void arm_cmplx_mag_squared_q31(
|
||||||
numSamples--;
|
numSamples--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_mult_cmplx_f32.c
|
* Title: arm_cmplx_mult_cmplx_f32.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
||||||
|
|
@ -81,7 +89,7 @@ void arm_cmplx_mult_cmplx_f32(
|
||||||
float32_t a1, b1, c1, d1; /* Temporary variables to store real and imaginary values */
|
float32_t a1, b1, c1, d1; /* Temporary variables to store real and imaginary values */
|
||||||
uint32_t blkCnt; /* loop counters */
|
uint32_t blkCnt; /* loop counters */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
float32_t a2, b2, c2, d2; /* Temporary variables to store real and imaginary values */
|
float32_t a2, b2, c2, d2; /* Temporary variables to store real and imaginary values */
|
||||||
|
|
@ -174,7 +182,7 @@ void arm_cmplx_mult_cmplx_f32(
|
||||||
/* Run the below code for Cortex-M0 */
|
/* Run the below code for Cortex-M0 */
|
||||||
blkCnt = numSamples;
|
blkCnt = numSamples;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_mult_cmplx_q15.c
|
* Title: arm_cmplx_mult_cmplx_q15.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -62,7 +70,7 @@ void arm_cmplx_mult_cmplx_q15(
|
||||||
{
|
{
|
||||||
q15_t a, b, c, d; /* Temporary variables to store real and imaginary values */
|
q15_t a, b, c, d; /* Temporary variables to store real and imaginary values */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
uint32_t blkCnt; /* loop counters */
|
uint32_t blkCnt; /* loop counters */
|
||||||
|
|
@ -176,7 +184,7 @@ void arm_cmplx_mult_cmplx_q15(
|
||||||
numSamples--;
|
numSamples--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_mult_cmplx_q31.c
|
* Title: arm_cmplx_mult_cmplx_q31.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -67,7 +75,7 @@ void arm_cmplx_mult_cmplx_q31(
|
||||||
q31_t mul1, mul2, mul3, mul4;
|
q31_t mul1, mul2, mul3, mul4;
|
||||||
q31_t out1, out2;
|
q31_t out1, out2;
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -309,7 +317,7 @@ void arm_cmplx_mult_cmplx_q31(
|
||||||
blkCnt--;
|
blkCnt--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_mult_real_f32.c
|
* Title: arm_cmplx_mult_real_f32.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -83,7 +91,7 @@ void arm_cmplx_mult_real_f32(
|
||||||
float32_t in; /* Temporary variable to store input value */
|
float32_t in; /* Temporary variable to store input value */
|
||||||
uint32_t blkCnt; /* loop counters */
|
uint32_t blkCnt; /* loop counters */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
float32_t inA1, inA2, inA3, inA4; /* Temporary variables to hold input data */
|
float32_t inA1, inA2, inA3, inA4; /* Temporary variables to hold input data */
|
||||||
|
|
@ -196,7 +204,7 @@ void arm_cmplx_mult_real_f32(
|
||||||
/* Run the below code for Cortex-M0 */
|
/* Run the below code for Cortex-M0 */
|
||||||
blkCnt = numSamples;
|
blkCnt = numSamples;
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
while(blkCnt > 0u)
|
while(blkCnt > 0u)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_mult_real_q15.c
|
* Title: arm_cmplx_mult_real_q15.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -64,7 +72,7 @@ void arm_cmplx_mult_real_q15(
|
||||||
{
|
{
|
||||||
q15_t in; /* Temporary variable to store input value */
|
q15_t in; /* Temporary variable to store input value */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
uint32_t blkCnt; /* loop counters */
|
uint32_t blkCnt; /* loop counters */
|
||||||
|
|
@ -186,7 +194,7 @@ void arm_cmplx_mult_real_q15(
|
||||||
numSamples--;
|
numSamples--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cmplx_mult_real_q31.c
|
* Title: arm_cmplx_mult_real_q31.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -64,7 +72,7 @@ void arm_cmplx_mult_real_q31(
|
||||||
{
|
{
|
||||||
q31_t inA1; /* Temporary variable to store input value */
|
q31_t inA1; /* Temporary variable to store input value */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
uint32_t blkCnt; /* loop counters */
|
uint32_t blkCnt; /* loop counters */
|
||||||
|
|
@ -206,7 +214,7 @@ void arm_cmplx_mult_real_q31(
|
||||||
numSamples--;
|
numSamples--;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_pid_init_f32.c
|
* Title: arm_pid_init_f32.c
|
||||||
|
|
@ -12,23 +12,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ------------------------------------------------------------------- */
|
* ------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_pid_init_q15.c
|
* Title: arm_pid_init_q15.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -55,7 +63,7 @@ void arm_pid_init_q15(
|
||||||
int32_t resetStateFlag)
|
int32_t resetStateFlag)
|
||||||
{
|
{
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -105,7 +113,7 @@ void arm_pid_init_q15(
|
||||||
memset(S->state, 0, 3u * sizeof(q15_t));
|
memset(S->state, 0, 3u * sizeof(q15_t));
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_pid_init_q31.c
|
* Title: arm_pid_init_q31.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ------------------------------------------------------------------- */
|
* ------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -55,7 +63,7 @@ void arm_pid_init_q31(
|
||||||
int32_t resetStateFlag)
|
int32_t resetStateFlag)
|
||||||
{
|
{
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -80,7 +88,7 @@ void arm_pid_init_q31(
|
||||||
temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
|
temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
|
||||||
S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
|
S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
/* Derived coefficient A2 */
|
/* Derived coefficient A2 */
|
||||||
S->A2 = S->Kd;
|
S->A2 = S->Kd;
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_pid_reset_f32.c
|
* Title: arm_pid_reset_f32.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ------------------------------------------------------------------- */
|
* ------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_pid_reset_q15.c
|
* Title: arm_pid_reset_q15.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_pid_reset_q31.c
|
* Title: arm_pid_reset_q31.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ------------------------------------------------------------------- */
|
* ------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_sin_cos_f32.c
|
* Title: arm_sin_cos_f32.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_sin_cos_q31.c
|
* Title: arm_sin_cos_q31.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -272,7 +280,7 @@ void arm_sin_cos_q31(
|
||||||
q31_t x0; /* Nearest input value */
|
q31_t x0; /* Nearest input value */
|
||||||
q31_t y0, y1; /* Nearest output values */
|
q31_t y0, y1; /* Nearest output values */
|
||||||
q31_t xSpacing = INPUT_SPACING; /* Spaing between inputs */
|
q31_t xSpacing = INPUT_SPACING; /* Spaing between inputs */
|
||||||
int32_t i; /* Index */
|
uint32_t i; /* Index */
|
||||||
q31_t oneByXSpacing; /* 1/ xSpacing value */
|
q31_t oneByXSpacing; /* 1/ xSpacing value */
|
||||||
q31_t out; /* temporary variable */
|
q31_t out; /* temporary variable */
|
||||||
uint32_t sign_bits; /* No.of sign bits */
|
uint32_t sign_bits; /* No.of sign bits */
|
||||||
|
|
@ -282,11 +290,7 @@ void arm_sin_cos_q31(
|
||||||
i = ((uint32_t) theta - firstX) / (uint32_t) xSpacing;
|
i = ((uint32_t) theta - firstX) / (uint32_t) xSpacing;
|
||||||
|
|
||||||
/* Checking min and max index of table */
|
/* Checking min and max index of table */
|
||||||
if(i < 0)
|
if(i >= 359)
|
||||||
{
|
|
||||||
i = 0;
|
|
||||||
}
|
|
||||||
else if(i >= 359)
|
|
||||||
{
|
{
|
||||||
i = 358;
|
i = 358;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cos_f32.c
|
* Title: arm_cos_f32.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -43,7 +51,8 @@
|
||||||
* Q15, Q31, and floating-point data types.
|
* Q15, Q31, and floating-point data types.
|
||||||
* The input to the floating-point version is in radians while the
|
* The input to the floating-point version is in radians while the
|
||||||
* fixed-point Q15 and Q31 have a scaled input with the range
|
* fixed-point Q15 and Q31 have a scaled input with the range
|
||||||
* [0 +0.9999] mapping to [0 2*pi), Where range excludes 2*pi.
|
* [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
|
||||||
|
* value of 2*pi wraps around to 0.
|
||||||
*
|
*
|
||||||
* The implementation is based on table lookup using 256 values together with cubic interpolation.
|
* The implementation is based on table lookup using 256 values together with cubic interpolation.
|
||||||
* The steps used are:
|
* The steps used are:
|
||||||
|
|
@ -77,9 +86,10 @@
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* \par
|
* \par
|
||||||
* <b>Example code for Generation of Cos Table:</b>
|
* <b>Example code for Generation of Cos Table:</b>
|
||||||
|
* <pre>
|
||||||
* tableSize = 256;
|
* tableSize = 256;
|
||||||
* <pre>for(n = -1; n < (tableSize + 2); n++)
|
* for(n = -1; n < (tableSize + 2); n++)
|
||||||
* {
|
* {
|
||||||
* cosTable[n+1]= cos(2*pi*n/tableSize);
|
* cosTable[n+1]= cos(2*pi*n/tableSize);
|
||||||
* } </pre>
|
* } </pre>
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cos_q15.c
|
* Title: arm_cos_q15.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -43,21 +51,21 @@
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* \par
|
* \par
|
||||||
* Table Values are in Q15(1.15 Fixed point format) and generation is done in three steps
|
* Table values are in Q15 (1.15 fixed-point format) and generation is done in
|
||||||
* \par
|
* three steps. First, generate cos values in floating point:
|
||||||
* First Generate cos values in floating point:
|
* <pre>
|
||||||
* tableSize = 256;
|
* tableSize = 256;
|
||||||
* <pre>for(n = -1; n < (tableSize + 1); n++)
|
* for(n = -1; n < (tableSize + 1); n++)
|
||||||
* {
|
* {
|
||||||
* cosTable[n+1]= cos(2*pi*n/tableSize);
|
* cosTable[n+1]= cos(2*pi*n/tableSize);
|
||||||
* }</pre>
|
* } </pre>
|
||||||
* where pi value is 3.14159265358979
|
* where pi value is 3.14159265358979
|
||||||
* \par
|
* \par
|
||||||
* Secondly Convert Floating point to Q15(Fixed point):
|
* Second, convert floating-point to Q15 (fixed-point):
|
||||||
* (cosTable[i] * pow(2, 15))
|
* (cosTable[i] * pow(2, 15))
|
||||||
* \par
|
* \par
|
||||||
* Finally Rounding to nearest integer is done
|
* Finally, round to the nearest integer value:
|
||||||
* cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);
|
* cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static const q15_t cosTableQ15[259] = {
|
static const q15_t cosTableQ15[259] = {
|
||||||
|
|
@ -102,7 +110,8 @@ static const q15_t cosTableQ15[259] = {
|
||||||
* @param[in] x Scaled input value in radians.
|
* @param[in] x Scaled input value in radians.
|
||||||
* @return cos(x).
|
* @return cos(x).
|
||||||
*
|
*
|
||||||
* The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi.
|
* The Q15 input value is in the range [0 +0.9999] and is mapped to a radian
|
||||||
|
* value in the range [0 2*pi).
|
||||||
*/
|
*/
|
||||||
|
|
||||||
q15_t arm_cos_q15(
|
q15_t arm_cos_q15(
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_cos_q31.c
|
* Title: arm_cos_q31.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -43,19 +51,20 @@
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* \par
|
* \par
|
||||||
* Table Values are in Q31(1.31 Fixed point format) and generation is done in three steps
|
* Table values are in Q31 (1.31 fixed-point format) and generation is done in
|
||||||
* First Generate cos values in floating point:
|
* three steps. First, generate cos values in floating point:
|
||||||
|
* <pre>
|
||||||
* tableSize = 256;
|
* tableSize = 256;
|
||||||
* <pre>for(n = -1; n < (tableSize + 1); n++)
|
* for(n = -1; n < (tableSize + 1); n++)
|
||||||
* {
|
* {
|
||||||
* cosTable[n+1]= cos(2*pi*n/tableSize);
|
* cosTable[n+1]= cos(2*pi*n/tableSize);
|
||||||
* } </pre>
|
* } </pre>
|
||||||
* where pi value is 3.14159265358979
|
* where pi value is 3.14159265358979
|
||||||
* \par
|
* \par
|
||||||
* Secondly Convert Floating point to Q31(Fixed point):
|
* Second, convert floating-point to Q31 (Fixed point):
|
||||||
* (cosTable[i] * pow(2, 31))
|
* (cosTable[i] * pow(2, 31))
|
||||||
* \par
|
* \par
|
||||||
* Finally Rounding to nearest integer is done
|
* Finally, round to the nearest integer value:
|
||||||
* cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);
|
* cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
@ -133,7 +142,8 @@ static const q31_t cosTableQ31[259] = {
|
||||||
* @param[in] x Scaled input value in radians.
|
* @param[in] x Scaled input value in radians.
|
||||||
* @return cos(x).
|
* @return cos(x).
|
||||||
*
|
*
|
||||||
* The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi.
|
* The Q31 input value is in the range [0 +0.9999] and is mapped to a radian
|
||||||
|
* value in the range [0 2*pi).
|
||||||
*/
|
*/
|
||||||
|
|
||||||
q31_t arm_cos_q31(
|
q31_t arm_cos_q31(
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_sin_f32.c
|
* Title: arm_sin_f32.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -44,7 +52,8 @@
|
||||||
* Q15, Q31, and floating-point data types.
|
* Q15, Q31, and floating-point data types.
|
||||||
* The input to the floating-point version is in radians while the
|
* The input to the floating-point version is in radians while the
|
||||||
* fixed-point Q15 and Q31 have a scaled input with the range
|
* fixed-point Q15 and Q31 have a scaled input with the range
|
||||||
* [0 +0.9999] mapping to [0 2*pi), Where range excludes 2*pi.
|
* [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
|
||||||
|
* value of 2*pi wraps around to 0.
|
||||||
*
|
*
|
||||||
* The implementation is based on table lookup using 256 values together with cubic interpolation.
|
* The implementation is based on table lookup using 256 values together with cubic interpolation.
|
||||||
* The steps used are:
|
* The steps used are:
|
||||||
|
|
@ -78,9 +87,10 @@
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* \par
|
* \par
|
||||||
* Example code for Generation of Floating-point Sin Table:
|
* Example code for the generation of the floating-point sine table:
|
||||||
|
* <pre>
|
||||||
* tableSize = 256;
|
* tableSize = 256;
|
||||||
* <pre>for(n = -1; n < (tableSize + 1); n++)
|
* for(n = -1; n < (tableSize + 1); n++)
|
||||||
* {
|
* {
|
||||||
* sinTable[n+1]=sin(2*pi*n/tableSize);
|
* sinTable[n+1]=sin(2*pi*n/tableSize);
|
||||||
* }</pre>
|
* }</pre>
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_sin_q15.c
|
* Title: arm_sin_q15.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -42,24 +50,24 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* \par
|
* \par
|
||||||
* Example code for Generation of Q15 Sin Table:
|
* Table values are in Q15 (1.15 fixed-point format) and generation is done in
|
||||||
* \par
|
* three steps. First, generate sin values in floating point:
|
||||||
* <pre>tableSize = 256;
|
* <pre>
|
||||||
|
* tableSize = 256;
|
||||||
* for(n = -1; n < (tableSize + 1); n++)
|
* for(n = -1; n < (tableSize + 1); n++)
|
||||||
* {
|
* {
|
||||||
* sinTable[n+1]=sin(2*pi*n/tableSize);
|
* sinTable[n+1]= sin(2*pi*n/tableSize);
|
||||||
* } </pre>
|
* } </pre>
|
||||||
* where pi value is 3.14159265358979
|
* where pi value is 3.14159265358979
|
||||||
* \par
|
* \par
|
||||||
* Convert Floating point to Q15(Fixed point):
|
* Second, convert floating-point to Q15 (fixed-point):
|
||||||
* (sinTable[i] * pow(2, 15))
|
* (sinTable[i] * pow(2, 15))
|
||||||
* \par
|
* \par
|
||||||
* rounding to nearest integer is done
|
* Finally, round to the nearest integer value:
|
||||||
* sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
|
* sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
static const q15_t sinTableQ15[259] = {
|
static const q15_t sinTableQ15[259] = {
|
||||||
0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
|
0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
|
||||||
|
|
@ -103,7 +111,7 @@ static const q15_t sinTableQ15[259] = {
|
||||||
* @param[in] x Scaled input value in radians.
|
* @param[in] x Scaled input value in radians.
|
||||||
* @return sin(x).
|
* @return sin(x).
|
||||||
*
|
*
|
||||||
* The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi.
|
* The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi).
|
||||||
*/
|
*/
|
||||||
|
|
||||||
q15_t arm_sin_q15(
|
q15_t arm_sin_q15(
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_sin_q31.c
|
* Title: arm_sin_q31.c
|
||||||
|
|
@ -11,23 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -43,19 +51,20 @@
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* \par
|
* \par
|
||||||
* Tables generated are in Q31(1.31 Fixed point format)
|
* Table values are in Q31 (1.31 fixed-point format) and generation is done in
|
||||||
* Generation of sin values in floating point:
|
* three steps. First, generate sin values in floating point:
|
||||||
* <pre>tableSize = 256;
|
* <pre>
|
||||||
|
* tableSize = 256;
|
||||||
* for(n = -1; n < (tableSize + 1); n++)
|
* for(n = -1; n < (tableSize + 1); n++)
|
||||||
* {
|
* {
|
||||||
* sinTable[n+1]= sin(2*pi*n/tableSize);
|
* sinTable[n+1]= sin(2*pi*n/tableSize);
|
||||||
* } </pre>
|
* } </pre>
|
||||||
* where pi value is 3.14159265358979
|
* where pi value is 3.14159265358979
|
||||||
* \par
|
* \par
|
||||||
* Convert Floating point to Q31(Fixed point):
|
* Second, convert floating-point to Q31 (Fixed point):
|
||||||
* (sinTable[i] * pow(2, 31))
|
* (sinTable[i] * pow(2, 31))
|
||||||
* \par
|
* \par
|
||||||
* rounding to nearest integer is done
|
* Finally, round to the nearest integer value:
|
||||||
* sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
|
* sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
@ -129,12 +138,11 @@ static const q31_t sinTableQ31[259] = {
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Fast approximation to the trigonometric sine function for Q31 data.
|
* @brief Fast approximation to the trigonometric sine function for Q31 data.
|
||||||
* @param[in] x Scaled input value in radians.
|
* @param[in] x Scaled input value in radians.
|
||||||
* @return sin(x).
|
* @return sin(x).
|
||||||
*
|
*
|
||||||
* The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi.
|
* The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). */
|
||||||
*/
|
|
||||||
|
|
||||||
q31_t arm_sin_q31(
|
q31_t arm_sin_q31(
|
||||||
q31_t x)
|
q31_t x)
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2011 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_sqrt_q15.c
|
* Title: arm_sqrt_q15.c
|
||||||
|
|
@ -11,15 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.0 2011/03/08
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Alpha release.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.1 2011/09/30
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Beta release.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this
|
||||||
|
* software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
#include "arm_common_tables.h"
|
#include "arm_common_tables.h"
|
||||||
|
|
@ -38,8 +54,9 @@
|
||||||
* @brief Q15 square root function.
|
* @brief Q15 square root function.
|
||||||
* @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
|
* @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
|
||||||
* @param[out] *pOut square root of input value.
|
* @param[out] *pOut square root of input value.
|
||||||
* @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
|
* @return The function returns ARM_MATH_SUCCESS if the input value is positive
|
||||||
* <code>in</code> is negative value and returns zero output for negative values.
|
* and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
|
||||||
|
* negative inputs, the function returns *pOut = 0.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
arm_status arm_sqrt_q15(
|
arm_status arm_sqrt_q15(
|
||||||
|
|
@ -49,6 +66,11 @@ arm_status arm_sqrt_q15(
|
||||||
q15_t number, temp1, var1, signBits1, half;
|
q15_t number, temp1, var1, signBits1, half;
|
||||||
q31_t bits_val1;
|
q31_t bits_val1;
|
||||||
float32_t temp_float1;
|
float32_t temp_float1;
|
||||||
|
union
|
||||||
|
{
|
||||||
|
q31_t fracval;
|
||||||
|
float32_t floatval;
|
||||||
|
} tempconv;
|
||||||
|
|
||||||
number = in;
|
number = in;
|
||||||
|
|
||||||
|
|
@ -75,11 +97,13 @@ arm_status arm_sqrt_q15(
|
||||||
/*Convert to float */
|
/*Convert to float */
|
||||||
temp_float1 = number * 3.051757812500000e-005f;
|
temp_float1 = number * 3.051757812500000e-005f;
|
||||||
/*Store as integer */
|
/*Store as integer */
|
||||||
bits_val1 = *(int *) &temp_float1;
|
tempconv.floatval = temp_float1;
|
||||||
|
bits_val1 = tempconv.fracval;
|
||||||
/* Subtract the shifted value from the magic number to give intial guess */
|
/* Subtract the shifted value from the magic number to give intial guess */
|
||||||
bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess
|
bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess
|
||||||
/* Store as float */
|
/* Store as float */
|
||||||
temp_float1 = *(float *) &bits_val1;
|
tempconv.fracval = bits_val1;
|
||||||
|
temp_float1 = tempconv.floatval;
|
||||||
/* Convert to integer format */
|
/* Convert to integer format */
|
||||||
var1 = (q31_t) (temp_float1 * 16384);
|
var1 = (q31_t) (temp_float1 * 16384);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2011 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_sqrt_q31.c
|
* Title: arm_sqrt_q31.c
|
||||||
|
|
@ -11,15 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.0 2011/03/08
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Alpha release.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.1 2011/09/30
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Beta release.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this
|
||||||
|
* software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
#include "arm_common_tables.h"
|
#include "arm_common_tables.h"
|
||||||
|
|
@ -37,8 +53,9 @@
|
||||||
* @brief Q31 square root function.
|
* @brief Q31 square root function.
|
||||||
* @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
|
* @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
|
||||||
* @param[out] *pOut square root of input value.
|
* @param[out] *pOut square root of input value.
|
||||||
* @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
|
* @return The function returns ARM_MATH_SUCCESS if the input value is positive
|
||||||
* <code>in</code> is negative value and returns zero output for negative values.
|
* and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
|
||||||
|
* negative inputs, the function returns *pOut = 0.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
arm_status arm_sqrt_q31(
|
arm_status arm_sqrt_q31(
|
||||||
|
|
@ -47,6 +64,11 @@ arm_status arm_sqrt_q31(
|
||||||
{
|
{
|
||||||
q31_t number, temp1, bits_val1, var1, signBits1, half;
|
q31_t number, temp1, bits_val1, var1, signBits1, half;
|
||||||
float32_t temp_float1;
|
float32_t temp_float1;
|
||||||
|
union
|
||||||
|
{
|
||||||
|
q31_t fracval;
|
||||||
|
float32_t floatval;
|
||||||
|
} tempconv;
|
||||||
|
|
||||||
number = in;
|
number = in;
|
||||||
|
|
||||||
|
|
@ -73,11 +95,13 @@ arm_status arm_sqrt_q31(
|
||||||
/*Convert to float */
|
/*Convert to float */
|
||||||
temp_float1 = number * 4.6566128731e-010f;
|
temp_float1 = number * 4.6566128731e-010f;
|
||||||
/*Store as integer */
|
/*Store as integer */
|
||||||
bits_val1 = *(int *) &temp_float1;
|
tempconv.floatval = temp_float1;
|
||||||
|
bits_val1 = tempconv.fracval;
|
||||||
/* Subtract the shifted value from the magic number to give intial guess */
|
/* Subtract the shifted value from the magic number to give intial guess */
|
||||||
bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess
|
bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess
|
||||||
/* Store as float */
|
/* Store as float */
|
||||||
temp_float1 = *(float *) &bits_val1;
|
tempconv.fracval = bits_val1;
|
||||||
|
temp_float1 = tempconv.floatval;
|
||||||
/* Convert to integer format */
|
/* Convert to integer format */
|
||||||
var1 = (q31_t) (temp_float1 * 1073741824);
|
var1 = (q31_t) (temp_float1 * 1073741824);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_biquad_cascade_df1_32x64_init_q31.c
|
* Title: arm_biquad_cascade_df1_32x64_init_q31.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_biquad_cascade_df1_32x64_q31.c
|
* Title: arm_biquad_cascade_df1_32x64_q31.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -100,6 +105,9 @@
|
||||||
* There is also an associated initialization function which performs the following operations:
|
* There is also an associated initialization function which performs the following operations:
|
||||||
* - Sets the values of the internal structure fields.
|
* - Sets the values of the internal structure fields.
|
||||||
* - Zeros out the values in the state buffer.
|
* - Zeros out the values in the state buffer.
|
||||||
|
* To do this manually without calling the init function, assign the follow subfields of the instance structure:
|
||||||
|
* numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero.
|
||||||
|
*
|
||||||
* \par
|
* \par
|
||||||
* Use of the initialization function is optional.
|
* Use of the initialization function is optional.
|
||||||
* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
|
* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
|
||||||
|
|
@ -198,7 +206,7 @@ void arm_biquad_cas_df1_32x64_q31(
|
||||||
uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
|
uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -545,7 +553,7 @@ void arm_biquad_cas_df1_32x64_q31(
|
||||||
|
|
||||||
} while(--stage);
|
} while(--stage);
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_biquad_cascade_df1_f32.c
|
* Title: arm_biquad_cascade_df1_f32.c
|
||||||
|
|
@ -12,29 +12,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.5 2010/04/26
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* incorporated review comments and updated with latest CMSIS layer
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.3 2010/03/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Initial version
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -104,6 +106,8 @@
|
||||||
* The initialization function performs following operations:
|
* The initialization function performs following operations:
|
||||||
* - Sets the values of the internal structure fields.
|
* - Sets the values of the internal structure fields.
|
||||||
* - Zeros out the values in the state buffer.
|
* - Zeros out the values in the state buffer.
|
||||||
|
* To do this manually without calling the init function, assign the follow subfields of the instance structure:
|
||||||
|
* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
|
||||||
*
|
*
|
||||||
* \par
|
* \par
|
||||||
* Use of the initialization function is optional.
|
* Use of the initialization function is optional.
|
||||||
|
|
@ -188,7 +192,7 @@ void arm_biquad_cascade_df1_f32(
|
||||||
uint32_t sample, stage = S->numStages; /* loop counters */
|
uint32_t sample, stage = S->numStages; /* loop counters */
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -411,7 +415,7 @@ void arm_biquad_cascade_df1_f32(
|
||||||
|
|
||||||
} while(stage > 0u);
|
} while(stage > 0u);
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_biquad_cascade_df1_fast_q15.c
|
* Title: arm_biquad_cascade_df1_fast_q15.c
|
||||||
|
|
@ -12,28 +12,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
* Target Processor: Cortex-M4/Cortex-M3
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.9 2010/08/16
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Initial version
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
*
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_biquad_cascade_df1_fast_q31.c
|
* Title: arm_biquad_cascade_df1_fast_q31.c
|
||||||
|
|
@ -12,27 +12,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
* Target Processor: Cortex-M4/Cortex-M3
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.9 2010/08/27
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Initial version
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -76,7 +80,7 @@ void arm_biquad_cascade_df1_fast_q31(
|
||||||
q31_t * pDst,
|
q31_t * pDst,
|
||||||
uint32_t blockSize)
|
uint32_t blockSize)
|
||||||
{
|
{
|
||||||
q31_t acc; /* accumulator */
|
q31_t acc = 0; /* accumulator */
|
||||||
q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
|
q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
|
||||||
q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
|
q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
|
||||||
q31_t *pIn = pSrc; /* input pointer initialization */
|
q31_t *pIn = pSrc; /* input pointer initialization */
|
||||||
|
|
@ -120,15 +124,20 @@ void arm_biquad_cascade_df1_fast_q31(
|
||||||
|
|
||||||
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
|
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
|
||||||
/* acc = b0 * x[n] */
|
/* acc = b0 * x[n] */
|
||||||
acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);
|
//acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);
|
||||||
|
mult_32x32_keep32_R(acc, b1, Xn1);
|
||||||
/* acc += b1 * x[n-1] */
|
/* acc += b1 * x[n-1] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, b0, Xn);
|
||||||
/* acc += b[2] * x[n-2] */
|
/* acc += b[2] * x[n-2] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, b2, Xn2);
|
||||||
/* acc += a1 * y[n-1] */
|
/* acc += a1 * y[n-1] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, a1, Yn1);
|
||||||
/* acc += a2 * y[n-2] */
|
/* acc += a2 * y[n-2] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, a2, Yn2);
|
||||||
|
|
||||||
/* The result is converted to 1.31 , Yn2 variable is reused */
|
/* The result is converted to 1.31 , Yn2 variable is reused */
|
||||||
Yn2 = acc << shift;
|
Yn2 = acc << shift;
|
||||||
|
|
@ -141,15 +150,20 @@ void arm_biquad_cascade_df1_fast_q31(
|
||||||
|
|
||||||
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
|
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
|
||||||
/* acc = b0 * x[n] */
|
/* acc = b0 * x[n] */
|
||||||
acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);
|
//acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);
|
||||||
|
mult_32x32_keep32_R(acc, b0, Xn2);
|
||||||
/* acc += b1 * x[n-1] */
|
/* acc += b1 * x[n-1] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, b1, Xn);
|
||||||
/* acc += b[2] * x[n-2] */
|
/* acc += b[2] * x[n-2] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, b2, Xn1);
|
||||||
/* acc += a1 * y[n-1] */
|
/* acc += a1 * y[n-1] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, a1, Yn2);
|
||||||
/* acc += a2 * y[n-2] */
|
/* acc += a2 * y[n-2] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, a2, Yn1);
|
||||||
|
|
||||||
/* The result is converted to 1.31, Yn1 variable is reused */
|
/* The result is converted to 1.31, Yn1 variable is reused */
|
||||||
Yn1 = acc << shift;
|
Yn1 = acc << shift;
|
||||||
|
|
@ -162,15 +176,20 @@ void arm_biquad_cascade_df1_fast_q31(
|
||||||
|
|
||||||
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
|
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
|
||||||
/* acc = b0 * x[n] */
|
/* acc = b0 * x[n] */
|
||||||
acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);
|
//acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);
|
||||||
|
mult_32x32_keep32_R(acc, b0, Xn1);
|
||||||
/* acc += b1 * x[n-1] */
|
/* acc += b1 * x[n-1] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, b1, Xn2);
|
||||||
/* acc += b[2] * x[n-2] */
|
/* acc += b[2] * x[n-2] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, b2, Xn);
|
||||||
/* acc += a1 * y[n-1] */
|
/* acc += a1 * y[n-1] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, a1, Yn1);
|
||||||
/* acc += a2 * y[n-2] */
|
/* acc += a2 * y[n-2] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, a2, Yn2);
|
||||||
|
|
||||||
/* The result is converted to 1.31, Yn2 variable is reused */
|
/* The result is converted to 1.31, Yn2 variable is reused */
|
||||||
Yn2 = acc << shift;
|
Yn2 = acc << shift;
|
||||||
|
|
@ -184,15 +203,20 @@ void arm_biquad_cascade_df1_fast_q31(
|
||||||
|
|
||||||
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
|
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
|
||||||
/* acc = b0 * x[n] */
|
/* acc = b0 * x[n] */
|
||||||
acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
|
//acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
|
||||||
|
mult_32x32_keep32_R(acc, b0, Xn);
|
||||||
/* acc += b1 * x[n-1] */
|
/* acc += b1 * x[n-1] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, b1, Xn1);
|
||||||
/* acc += b[2] * x[n-2] */
|
/* acc += b[2] * x[n-2] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, b2, Xn2);
|
||||||
/* acc += a1 * y[n-1] */
|
/* acc += a1 * y[n-1] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, a1, Yn2);
|
||||||
/* acc += a2 * y[n-2] */
|
/* acc += a2 * y[n-2] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, a2, Yn1);
|
||||||
|
|
||||||
/* Every time after the output is computed state should be updated. */
|
/* Every time after the output is computed state should be updated. */
|
||||||
/* The states should be updated as: */
|
/* The states should be updated as: */
|
||||||
|
|
@ -217,22 +241,28 @@ void arm_biquad_cascade_df1_fast_q31(
|
||||||
** No loop unrolling is used. */
|
** No loop unrolling is used. */
|
||||||
sample = (blockSize & 0x3u);
|
sample = (blockSize & 0x3u);
|
||||||
|
|
||||||
while(sample > 0u)
|
while(sample > 0u)
|
||||||
{
|
{
|
||||||
/* Read the input */
|
/* Read the input */
|
||||||
Xn = *pIn++;
|
Xn = *pIn++;
|
||||||
|
|
||||||
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
|
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
|
||||||
/* acc = b0 * x[n] */
|
/* acc = b0 * x[n] */
|
||||||
acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
|
//acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
|
||||||
|
mult_32x32_keep32_R(acc, b0, Xn);
|
||||||
/* acc += b1 * x[n-1] */
|
/* acc += b1 * x[n-1] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, b1, Xn1);
|
||||||
/* acc += b[2] * x[n-2] */
|
/* acc += b[2] * x[n-2] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, b2, Xn2);
|
||||||
/* acc += a1 * y[n-1] */
|
/* acc += a1 * y[n-1] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, a1, Yn1);
|
||||||
/* acc += a2 * y[n-2] */
|
/* acc += a2 * y[n-2] */
|
||||||
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
|
//acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
|
||||||
|
multAcc_32x32_keep32_R(acc, a2, Yn2);
|
||||||
|
|
||||||
/* The result is converted to 1.31 */
|
/* The result is converted to 1.31 */
|
||||||
acc = acc << shift;
|
acc = acc << shift;
|
||||||
|
|
||||||
|
|
@ -252,7 +282,7 @@ void arm_biquad_cascade_df1_fast_q31(
|
||||||
|
|
||||||
/* decrement the loop counter */
|
/* decrement the loop counter */
|
||||||
sample--;
|
sample--;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* The first stage goes from the input buffer to the output buffer. */
|
/* The first stage goes from the input buffer to the output buffer. */
|
||||||
/* Subsequent stages occur in-place in the output buffer */
|
/* Subsequent stages occur in-place in the output buffer */
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/*-----------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_biquad_cascade_df1_init_f32.c
|
* Title: arm_biquad_cascade_df1_init_f32.c
|
||||||
|
|
@ -11,29 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.5 2010/04/26
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* incorporated review comments and updated with latest CMSIS layer
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.3 2010/03/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Initial version
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------*/
|
* ---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/*-----------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_biquad_cascade_df1_init_q15.c
|
* Title: arm_biquad_cascade_df1_init_q15.c
|
||||||
|
|
@ -11,29 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.5 2010/04/26
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* incorporated review comments and updated with latest CMSIS layer
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.3 2010/03/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Initial version
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------*/
|
* ---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_biquad_cascade_df1_init_q31.c
|
* Title: arm_biquad_cascade_df1_init_q31.c
|
||||||
|
|
@ -12,29 +12,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.5 2010/04/26
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* incorporated review comments and updated with latest CMSIS layer
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.3 2010/03/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Initial version
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_biquad_cascade_df1_q15.c
|
* Title: arm_biquad_cascade_df1_q15.c
|
||||||
|
|
@ -12,29 +12,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.5 2010/04/26
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* incorporated review comments and updated with latest CMSIS layer
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.3 2010/03/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Initial version
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -78,7 +80,7 @@ void arm_biquad_cascade_df1_q15(
|
||||||
{
|
{
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -327,6 +329,7 @@ void arm_biquad_cascade_df1_q15(
|
||||||
{
|
{
|
||||||
/* Reading the coefficients */
|
/* Reading the coefficients */
|
||||||
b0 = *pCoeffs++;
|
b0 = *pCoeffs++;
|
||||||
|
pCoeffs++; // skip the 0 coefficient
|
||||||
b1 = *pCoeffs++;
|
b1 = *pCoeffs++;
|
||||||
b2 = *pCoeffs++;
|
b2 = *pCoeffs++;
|
||||||
a1 = *pCoeffs++;
|
a1 = *pCoeffs++;
|
||||||
|
|
@ -398,7 +401,7 @@ void arm_biquad_cascade_df1_q15(
|
||||||
|
|
||||||
} while(--stage);
|
} while(--stage);
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_biquad_cascade_df1_q31.c
|
* Title: arm_biquad_cascade_df1_q31.c
|
||||||
|
|
@ -12,29 +12,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.5 2010/04/26
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* incorporated review comments and updated with latest CMSIS layer
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.3 2010/03/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Initial version
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -88,7 +90,7 @@ void arm_biquad_cascade_df1_q31(
|
||||||
uint32_t sample, stage = S->numStages; /* loop counters */
|
uint32_t sample, stage = S->numStages; /* loop counters */
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
q31_t acc_l, acc_h; /* temporary output variables */
|
q31_t acc_l, acc_h; /* temporary output variables */
|
||||||
|
|
||||||
|
|
@ -392,7 +394,7 @@ void arm_biquad_cascade_df1_q31(
|
||||||
|
|
||||||
} while(--stage);
|
} while(--stage);
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,7 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_biquad_cascade_df2T_f32.c
|
* Title: arm_biquad_cascade_df2T_f32.c
|
||||||
|
|
@ -12,366 +11,349 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @ingroup groupFilters
|
* @ingroup groupFilters
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
|
* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
|
||||||
*
|
*
|
||||||
* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
|
* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
|
||||||
* The filters are implemented as a cascade of second order Biquad sections.
|
* The filters are implemented as a cascade of second order Biquad sections.
|
||||||
* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
|
* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
|
||||||
* Only floating-point data is supported.
|
* Only floating-point data is supported.
|
||||||
*
|
*
|
||||||
* This function operate on blocks of input and output data and each call to the function
|
* This function operate on blocks of input and output data and each call to the function
|
||||||
* processes <code>blockSize</code> samples through the filter.
|
* processes <code>blockSize</code> samples through the filter.
|
||||||
* <code>pSrc</code> points to the array of input data and
|
* <code>pSrc</code> points to the array of input data and
|
||||||
* <code>pDst</code> points to the array of output data.
|
* <code>pDst</code> points to the array of output data.
|
||||||
* Both arrays contain <code>blockSize</code> values.
|
* Both arrays contain <code>blockSize</code> values.
|
||||||
*
|
*
|
||||||
* \par Algorithm
|
* \par Algorithm
|
||||||
* Each Biquad stage implements a second order filter using the difference equation:
|
* Each Biquad stage implements a second order filter using the difference equation:
|
||||||
* <pre>
|
* <pre>
|
||||||
* y[n] = b0 * x[n] + d1
|
* y[n] = b0 * x[n] + d1
|
||||||
* d1 = b1 * x[n] + a1 * y[n] + d2
|
* d1 = b1 * x[n] + a1 * y[n] + d2
|
||||||
* d2 = b2 * x[n] + a2 * y[n]
|
* d2 = b2 * x[n] + a2 * y[n]
|
||||||
* </pre>
|
* </pre>
|
||||||
* where d1 and d2 represent the two state values.
|
* where d1 and d2 represent the two state values.
|
||||||
*
|
*
|
||||||
* \par
|
* \par
|
||||||
* A Biquad filter using a transposed Direct Form II structure is shown below.
|
* A Biquad filter using a transposed Direct Form II structure is shown below.
|
||||||
* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
|
* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
|
||||||
* Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
|
* Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
|
||||||
* Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
|
* Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
|
||||||
* Pay careful attention to the sign of the feedback coefficients.
|
* Pay careful attention to the sign of the feedback coefficients.
|
||||||
* Some design tools flip the sign of the feedback coefficients:
|
* Some design tools flip the sign of the feedback coefficients:
|
||||||
* <pre>
|
* <pre>
|
||||||
* y[n] = b0 * x[n] + d1;
|
* y[n] = b0 * x[n] + d1;
|
||||||
* d1 = b1 * x[n] - a1 * y[n] + d2;
|
* d1 = b1 * x[n] - a1 * y[n] + d2;
|
||||||
* d2 = b2 * x[n] - a2 * y[n];
|
* d2 = b2 * x[n] - a2 * y[n];
|
||||||
* </pre>
|
* </pre>
|
||||||
* In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
|
* In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
|
||||||
*
|
*
|
||||||
* \par
|
* \par
|
||||||
* Higher order filters are realized as a cascade of second order sections.
|
* Higher order filters are realized as a cascade of second order sections.
|
||||||
* <code>numStages</code> refers to the number of second order stages used.
|
* <code>numStages</code> refers to the number of second order stages used.
|
||||||
* For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
|
* For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
|
||||||
* A 9th order filter would be realized with <code>numStages=5</code> second order stages with the
|
* A 9th order filter would be realized with <code>numStages=5</code> second order stages with the
|
||||||
* coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
|
* coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
|
||||||
*
|
*
|
||||||
* \par
|
* \par
|
||||||
* <code>pState</code> points to the state variable array.
|
* <code>pState</code> points to the state variable array.
|
||||||
* Each Biquad stage has 2 state variables <code>d1</code> and <code>d2</code>.
|
* Each Biquad stage has 2 state variables <code>d1</code> and <code>d2</code>.
|
||||||
* The state variables are arranged in the <code>pState</code> array as:
|
* The state variables are arranged in the <code>pState</code> array as:
|
||||||
* <pre>
|
* <pre>
|
||||||
* {d11, d12, d21, d22, ...}
|
* {d11, d12, d21, d22, ...}
|
||||||
* </pre>
|
* </pre>
|
||||||
* where <code>d1x</code> refers to the state variables for the first Biquad and
|
* where <code>d1x</code> refers to the state variables for the first Biquad and
|
||||||
* <code>d2x</code> refers to the state variables for the second Biquad.
|
* <code>d2x</code> refers to the state variables for the second Biquad.
|
||||||
* The state array has a total length of <code>2*numStages</code> values.
|
* The state array has a total length of <code>2*numStages</code> values.
|
||||||
* The state variables are updated after each block of data is processed; the coefficients are untouched.
|
* The state variables are updated after each block of data is processed; the coefficients are untouched.
|
||||||
*
|
*
|
||||||
* \par
|
* \par
|
||||||
* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
|
* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
|
||||||
* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
|
* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
|
||||||
* That is why the Direct Form I structure supports Q15 and Q31 data types.
|
* That is why the Direct Form I structure supports Q15 and Q31 data types.
|
||||||
* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables <code>d1</code> and <code>d2</code>.
|
* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables <code>d1</code> and <code>d2</code>.
|
||||||
* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
|
* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
|
||||||
* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
|
* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
|
||||||
*
|
*
|
||||||
* \par Instance Structure
|
* \par Instance Structure
|
||||||
* The coefficients and state variables for a filter are stored together in an instance data structure.
|
* The coefficients and state variables for a filter are stored together in an instance data structure.
|
||||||
* A separate instance structure must be defined for each filter.
|
* A separate instance structure must be defined for each filter.
|
||||||
* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
|
* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
|
||||||
*
|
*
|
||||||
* \par Init Functions
|
* \par Init Functions
|
||||||
* There is also an associated initialization function.
|
* There is also an associated initialization function.
|
||||||
* The initialization function performs following operations:
|
* The initialization function performs following operations:
|
||||||
* - Sets the values of the internal structure fields.
|
* - Sets the values of the internal structure fields.
|
||||||
* - Zeros out the values in the state buffer.
|
* - Zeros out the values in the state buffer.
|
||||||
*
|
* To do this manually without calling the init function, assign the follow subfields of the instance structure:
|
||||||
* \par
|
* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
|
||||||
* Use of the initialization function is optional.
|
*
|
||||||
* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
|
* \par
|
||||||
* To place an instance structure into a const data section, the instance structure must be manually initialized.
|
* Use of the initialization function is optional.
|
||||||
* Set the values in the state buffer to zeros before static initialization.
|
* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
|
||||||
* For example, to statically initialize the instance structure use
|
* To place an instance structure into a const data section, the instance structure must be manually initialized.
|
||||||
* <pre>
|
* Set the values in the state buffer to zeros before static initialization.
|
||||||
* arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
|
* For example, to statically initialize the instance structure use
|
||||||
* </pre>
|
* <pre>
|
||||||
* where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer.
|
* arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
|
||||||
* <code>pCoeffs</code> is the address of the coefficient buffer;
|
* </pre>
|
||||||
*
|
* where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer.
|
||||||
*/
|
* <code>pCoeffs</code> is the address of the coefficient buffer;
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @addtogroup BiquadCascadeDF2T
|
* @addtogroup BiquadCascadeDF2T
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
|
* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
|
||||||
* @param[in] *S points to an instance of the filter data structure.
|
* @param[in] *S points to an instance of the filter data structure.
|
||||||
* @param[in] *pSrc points to the block of input data.
|
* @param[in] *pSrc points to the block of input data.
|
||||||
* @param[out] *pDst points to the block of output data
|
* @param[out] *pDst points to the block of output data
|
||||||
* @param[in] blockSize number of samples to process.
|
* @param[in] blockSize number of samples to process.
|
||||||
* @return none.
|
* @return none.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
LOW_OPTIMIZATION_ENTER
|
||||||
void arm_biquad_cascade_df2T_f32(
|
void arm_biquad_cascade_df2T_f32(
|
||||||
const arm_biquad_cascade_df2T_instance_f32 * S,
|
const arm_biquad_cascade_df2T_instance_f32 * S,
|
||||||
float32_t * pSrc,
|
float32_t * pSrc,
|
||||||
float32_t * pDst,
|
float32_t * pDst,
|
||||||
uint32_t blockSize)
|
uint32_t blockSize)
|
||||||
{
|
{
|
||||||
|
|
||||||
float32_t *pIn = pSrc; /* source pointer */
|
float32_t *pIn = pSrc; /* source pointer */
|
||||||
float32_t *pOut = pDst; /* destination pointer */
|
float32_t *pOut = pDst; /* destination pointer */
|
||||||
float32_t *pState = S->pState; /* State pointer */
|
float32_t *pState = S->pState; /* State pointer */
|
||||||
float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
|
float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
|
||||||
float32_t acc0; /* accumulator */
|
float32_t acc1; /* accumulator */
|
||||||
float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
|
float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
|
||||||
float32_t Xn; /* temporary input */
|
float32_t Xn1; /* temporary input */
|
||||||
float32_t d1, d2; /* state variables */
|
float32_t d1, d2; /* state variables */
|
||||||
uint32_t sample, stage = S->numStages; /* loop counters */
|
uint32_t sample, stage = S->numStages; /* loop counters */
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY_FAMILY
|
||||||
|
|
||||||
float32_t Xn1, Xn2; /* Input State variables */
|
float32_t Xn2, Xn3, Xn4; /* Input State variables */
|
||||||
float32_t acc1; /* accumulator */
|
float32_t acc2, acc3, acc4; /* accumulator */
|
||||||
|
|
||||||
|
|
||||||
|
float32_t p0, p1, p2, p3, p4, A1;
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
do
|
do
|
||||||
{
|
{
|
||||||
/* Reading the coefficients */
|
/* Reading the coefficients */
|
||||||
b0 = *pCoeffs++;
|
b0 = *pCoeffs++;
|
||||||
b1 = *pCoeffs++;
|
b1 = *pCoeffs++;
|
||||||
b2 = *pCoeffs++;
|
b2 = *pCoeffs++;
|
||||||
a1 = *pCoeffs++;
|
a1 = *pCoeffs++;
|
||||||
a2 = *pCoeffs++;
|
a2 = *pCoeffs++;
|
||||||
|
|
||||||
|
|
||||||
/*Reading the state values */
|
/*Reading the state values */
|
||||||
d1 = pState[0];
|
d1 = pState[0];
|
||||||
d2 = pState[1];
|
d2 = pState[1];
|
||||||
|
|
||||||
/* Apply loop unrolling and compute 4 output values simultaneously. */
|
/* Apply loop unrolling and compute 4 output values simultaneously. */
|
||||||
sample = blockSize >> 2u;
|
sample = blockSize >> 2u;
|
||||||
|
|
||||||
/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
|
/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
|
||||||
** a second loop below computes the remaining 1 to 3 samples. */
|
** a second loop below computes the remaining 1 to 3 samples. */
|
||||||
while(sample > 0u)
|
while(sample > 0u) {
|
||||||
{
|
|
||||||
|
|
||||||
/* y[n] = b0 * x[n] + d1 */
|
/* y[n] = b0 * x[n] + d1 */
|
||||||
/* d1 = b1 * x[n] + a1 * y[n] + d2 */
|
/* d1 = b1 * x[n] + a1 * y[n] + d2 */
|
||||||
/* d2 = b2 * x[n] + a2 * y[n] */
|
/* d2 = b2 * x[n] + a2 * y[n] */
|
||||||
|
|
||||||
/* Read the first input */
|
/* Read the four inputs */
|
||||||
Xn1 = *pIn++;
|
Xn1 = pIn[0];
|
||||||
|
Xn2 = pIn[1];
|
||||||
|
Xn3 = pIn[2];
|
||||||
|
Xn4 = pIn[3];
|
||||||
|
pIn += 4;
|
||||||
|
|
||||||
/* y[n] = b0 * x[n] + d1 */
|
p0 = b0 * Xn1;
|
||||||
acc0 = (b0 * Xn1) + d1;
|
p1 = b1 * Xn1;
|
||||||
|
acc1 = p0 + d1;
|
||||||
|
p0 = b0 * Xn2;
|
||||||
|
p3 = a1 * acc1;
|
||||||
|
p2 = b2 * Xn1;
|
||||||
|
A1 = p1 + p3;
|
||||||
|
p4 = a2 * acc1;
|
||||||
|
d1 = A1 + d2;
|
||||||
|
d2 = p2 + p4;
|
||||||
|
|
||||||
/* d1 = b1 * x[n] + d2 */
|
p1 = b1 * Xn2;
|
||||||
d1 = (b1 * Xn1) + d2;
|
acc2 = p0 + d1;
|
||||||
|
p0 = b0 * Xn3;
|
||||||
|
p3 = a1 * acc2;
|
||||||
|
p2 = b2 * Xn2;
|
||||||
|
A1 = p1 + p3;
|
||||||
|
p4 = a2 * acc2;
|
||||||
|
d1 = A1 + d2;
|
||||||
|
d2 = p2 + p4;
|
||||||
|
|
||||||
/* d2 = b2 * x[n] */
|
p1 = b1 * Xn3;
|
||||||
d2 = (b2 * Xn1);
|
acc3 = p0 + d1;
|
||||||
|
p0 = b0 * Xn4;
|
||||||
|
p3 = a1 * acc3;
|
||||||
|
p2 = b2 * Xn3;
|
||||||
|
A1 = p1 + p3;
|
||||||
|
p4 = a2 * acc3;
|
||||||
|
d1 = A1 + d2;
|
||||||
|
d2 = p2 + p4;
|
||||||
|
|
||||||
/* Read the second input */
|
acc4 = p0 + d1;
|
||||||
Xn2 = *pIn++;
|
p1 = b1 * Xn4;
|
||||||
|
p3 = a1 * acc4;
|
||||||
|
p2 = b2 * Xn4;
|
||||||
|
A1 = p1 + p3;
|
||||||
|
p4 = a2 * acc4;
|
||||||
|
d1 = A1 + d2;
|
||||||
|
d2 = p2 + p4;
|
||||||
|
|
||||||
/* d1 = b1 * x[n] + a1 * y[n] */
|
pOut[0] = acc1;
|
||||||
d1 = (a1 * acc0) + d1;
|
pOut[1] = acc2;
|
||||||
|
pOut[2] = acc3;
|
||||||
|
pOut[3] = acc4;
|
||||||
|
pOut += 4;
|
||||||
|
|
||||||
|
sample--;
|
||||||
|
}
|
||||||
|
|
||||||
/* Store the result in the accumulator in the destination buffer. */
|
sample = blockSize & 0x3u;
|
||||||
*pOut++ = acc0;
|
while(sample > 0u) {
|
||||||
|
Xn1 = *pIn++;
|
||||||
|
|
||||||
d2 = (a2 * acc0) + d2;
|
p0 = b0 * Xn1;
|
||||||
|
p1 = b1 * Xn1;
|
||||||
|
acc1 = p0 + d1;
|
||||||
|
p3 = a1 * acc1;
|
||||||
|
p2 = b2 * Xn1;
|
||||||
|
A1 = p1 + p3;
|
||||||
|
p4 = a2 * acc1;
|
||||||
|
d1 = A1 + d2;
|
||||||
|
d2 = p2 + p4;
|
||||||
|
|
||||||
|
*pOut++ = acc1;
|
||||||
|
|
||||||
|
sample--;
|
||||||
|
}
|
||||||
|
|
||||||
/* y[n] = b0 * x[n] + d1 */
|
/* Store the updated state variables back into the state array */
|
||||||
acc1 = (b0 * Xn2) + d1;
|
*pState++ = d1;
|
||||||
|
*pState++ = d2;
|
||||||
|
|
||||||
/* Read the third input */
|
/* The current stage input is given as the output to the next stage */
|
||||||
Xn1 = *pIn++;
|
pIn = pDst;
|
||||||
|
|
||||||
d1 = (b1 * Xn2) + d2;
|
/*Reset the output working pointer */
|
||||||
|
pOut = pDst;
|
||||||
d2 = (b2 * Xn2);
|
|
||||||
|
|
||||||
/* Store the result in the accumulator in the destination buffer. */
|
|
||||||
*pOut++ = acc1;
|
|
||||||
|
|
||||||
d1 = (a1 * acc1) + d1;
|
|
||||||
|
|
||||||
d2 = (a2 * acc1) + d2;
|
|
||||||
|
|
||||||
/* y[n] = b0 * x[n] + d1 */
|
|
||||||
acc0 = (b0 * Xn1) + d1;
|
|
||||||
|
|
||||||
d1 = (b1 * Xn1) + d2;
|
|
||||||
|
|
||||||
d2 = (b2 * Xn1);
|
|
||||||
|
|
||||||
/* Read the fourth input */
|
|
||||||
Xn2 = *pIn++;
|
|
||||||
|
|
||||||
d1 = (a1 * acc0) + d1;
|
|
||||||
|
|
||||||
/* Store the result in the accumulator in the destination buffer. */
|
|
||||||
*pOut++ = acc0;
|
|
||||||
|
|
||||||
d2 = (a2 * acc0) + d2;
|
|
||||||
|
|
||||||
/* y[n] = b0 * x[n] + d1 */
|
|
||||||
acc1 = (b0 * Xn2) + d1;
|
|
||||||
|
|
||||||
d1 = (b1 * Xn2) + d2;
|
|
||||||
|
|
||||||
d2 = (b2 * Xn2);
|
|
||||||
|
|
||||||
/* Store the result in the accumulator in the destination buffer. */
|
|
||||||
*pOut++ = acc1;
|
|
||||||
|
|
||||||
d1 = (a1 * acc1) + d1;
|
|
||||||
|
|
||||||
d2 = (a2 * acc1) + d2;
|
|
||||||
|
|
||||||
/* decrement the loop counter */
|
/* decrement the loop counter */
|
||||||
sample--;
|
stage--;
|
||||||
|
|
||||||
}
|
} while(stage > 0u);
|
||||||
|
|
||||||
/* If the blockSize is not a multiple of 4, compute any remaining output samples here.
|
|
||||||
** No loop unrolling is used. */
|
|
||||||
sample = blockSize & 0x3u;
|
|
||||||
|
|
||||||
while(sample > 0u)
|
|
||||||
{
|
|
||||||
/* Read the input */
|
|
||||||
Xn = *pIn++;
|
|
||||||
|
|
||||||
/* y[n] = b0 * x[n] + d1 */
|
|
||||||
acc0 = (b0 * Xn) + d1;
|
|
||||||
|
|
||||||
/* Store the result in the accumulator in the destination buffer. */
|
|
||||||
*pOut++ = acc0;
|
|
||||||
|
|
||||||
/* Every time after the output is computed state should be updated. */
|
|
||||||
/* d1 = b1 * x[n] + a1 * y[n] + d2 */
|
|
||||||
d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
|
|
||||||
|
|
||||||
/* d2 = b2 * x[n] + a2 * y[n] */
|
|
||||||
d2 = (b2 * Xn) + (a2 * acc0);
|
|
||||||
|
|
||||||
/* decrement the loop counter */
|
|
||||||
sample--;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Store the updated state variables back into the state array */
|
|
||||||
*pState++ = d1;
|
|
||||||
*pState++ = d2;
|
|
||||||
|
|
||||||
/* The current stage input is given as the output to the next stage */
|
|
||||||
pIn = pDst;
|
|
||||||
|
|
||||||
/*Reset the output working pointer */
|
|
||||||
pOut = pDst;
|
|
||||||
|
|
||||||
/* decrement the loop counter */
|
|
||||||
stage--;
|
|
||||||
|
|
||||||
} while(stage > 0u);
|
|
||||||
|
|
||||||
#else
|
#else
|
||||||
|
|
||||||
/* Run the below code for Cortex-M0 */
|
/* Run the below code for Cortex-M0 */
|
||||||
|
|
||||||
do
|
do
|
||||||
{
|
{
|
||||||
/* Reading the coefficients */
|
/* Reading the coefficients */
|
||||||
b0 = *pCoeffs++;
|
b0 = *pCoeffs++;
|
||||||
b1 = *pCoeffs++;
|
b1 = *pCoeffs++;
|
||||||
b2 = *pCoeffs++;
|
b2 = *pCoeffs++;
|
||||||
a1 = *pCoeffs++;
|
a1 = *pCoeffs++;
|
||||||
a2 = *pCoeffs++;
|
a2 = *pCoeffs++;
|
||||||
|
|
||||||
/*Reading the state values */
|
/*Reading the state values */
|
||||||
d1 = pState[0];
|
d1 = pState[0];
|
||||||
d2 = pState[1];
|
d2 = pState[1];
|
||||||
|
|
||||||
|
|
||||||
sample = blockSize;
|
sample = blockSize;
|
||||||
|
|
||||||
while(sample > 0u)
|
while(sample > 0u)
|
||||||
{
|
{
|
||||||
/* Read the input */
|
/* Read the input */
|
||||||
Xn = *pIn++;
|
Xn1 = *pIn++;
|
||||||
|
|
||||||
/* y[n] = b0 * x[n] + d1 */
|
/* y[n] = b0 * x[n] + d1 */
|
||||||
acc0 = (b0 * Xn) + d1;
|
acc1 = (b0 * Xn1) + d1;
|
||||||
|
|
||||||
/* Store the result in the accumulator in the destination buffer. */
|
/* Store the result in the accumulator in the destination buffer. */
|
||||||
*pOut++ = acc0;
|
*pOut++ = acc1;
|
||||||
|
|
||||||
/* Every time after the output is computed state should be updated. */
|
/* Every time after the output is computed state should be updated. */
|
||||||
/* d1 = b1 * x[n] + a1 * y[n] + d2 */
|
/* d1 = b1 * x[n] + a1 * y[n] + d2 */
|
||||||
d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
|
d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
|
||||||
|
|
||||||
/* d2 = b2 * x[n] + a2 * y[n] */
|
/* d2 = b2 * x[n] + a2 * y[n] */
|
||||||
d2 = (b2 * Xn) + (a2 * acc0);
|
d2 = (b2 * Xn1) + (a2 * acc1);
|
||||||
|
|
||||||
|
/* decrement the loop counter */
|
||||||
|
sample--;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Store the updated state variables back into the state array */
|
||||||
|
*pState++ = d1;
|
||||||
|
*pState++ = d2;
|
||||||
|
|
||||||
|
/* The current stage input is given as the output to the next stage */
|
||||||
|
pIn = pDst;
|
||||||
|
|
||||||
|
/*Reset the output working pointer */
|
||||||
|
pOut = pDst;
|
||||||
|
|
||||||
/* decrement the loop counter */
|
/* decrement the loop counter */
|
||||||
sample--;
|
stage--;
|
||||||
}
|
|
||||||
|
|
||||||
/* Store the updated state variables back into the state array */
|
} while(stage > 0u);
|
||||||
*pState++ = d1;
|
|
||||||
*pState++ = d2;
|
|
||||||
|
|
||||||
/* The current stage input is given as the output to the next stage */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
pIn = pDst;
|
|
||||||
|
|
||||||
/*Reset the output working pointer */
|
|
||||||
pOut = pDst;
|
|
||||||
|
|
||||||
/* decrement the loop counter */
|
|
||||||
stage--;
|
|
||||||
|
|
||||||
} while(stage > 0u);
|
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
LOW_OPTIMIZATION_EXIT
|
||||||
|
|
||||||
|
/**
|
||||||
/**
|
|
||||||
* @} end of BiquadCascadeDF2T group
|
* @} end of BiquadCascadeDF2T group
|
||||||
*/
|
*/
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/*-----------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_biquad_cascade_df2T_init_f32.c
|
* Title: arm_biquad_cascade_df2T_init_f32.c
|
||||||
|
|
@ -12,26 +12,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.10 2011/7/15
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.3 2010/11/29
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.2 2010/11/11
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Documentation updated.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.1 2010/10/05
|
*
|
||||||
* Production release and review comments incorporated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.0 2010/09/20
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 0.0.7 2010/06/10
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Misra-C changes done
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* ---------------------------------------------------------------------------*/
|
* ---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------------
|
/* ----------------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_f32.c
|
* Title: arm_conv_f32.c
|
||||||
|
|
@ -11,30 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.10 2011/7/15
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.3 2010/11/29
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.2 2010/11/11
|
*
|
||||||
* Documentation updated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 1.0.0 2010/09/20
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Production release and review comments incorporated
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.7 2010/06/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Misra-C changes done
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
*
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------------- */
|
* -------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -129,7 +130,7 @@ void arm_conv_f32(
|
||||||
{
|
{
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -637,7 +638,7 @@ void arm_conv_f32(
|
||||||
pDst[i] = sum;
|
pDst[i] = sum;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_fast_opt_q15.c
|
* Title: arm_conv_fast_opt_q15.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
* Target Processor: Cortex-M4/Cortex-M3
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.10 2011/7/15
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.3 2010/11/29
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.2 2010/11/11
|
*
|
||||||
* Documentation updated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 1.0.0 2010/09/20
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Production release and review comments incorporated.
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_fast_q15.c
|
* Title: arm_conv_fast_q15.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
* Target Processor: Cortex-M4/Cortex-M3
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this
|
||||||
|
* software without specific prior written permission.
|
||||||
*
|
*
|
||||||
* Version 1.0.10 2011/7/15
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
*
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Version 1.0.3 2010/11/29
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
*
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Version 1.0.2 2010/11/11
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
* Documentation updated.
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
*
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
* Production release and review comments incorporated.
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
*
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* Version 1.0.0 2010/09/20
|
|
||||||
* Production release and review comments incorporated.
|
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_fast_q31.c
|
* Title: arm_conv_fast_q31.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
* Target Processor: Cortex-M4/Cortex-M3
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.10 2011/7/15
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.3 2010/11/29
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.2 2010/11/11
|
*
|
||||||
* Documentation updated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 1.0.0 2010/09/20
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Production release and review comments incorporated.
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_opt_q15.c
|
* Title: arm_conv_opt_q15.c
|
||||||
|
|
@ -11,30 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.10 2011/7/15
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.3 2010/11/29
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.2 2010/11/11
|
*
|
||||||
* Documentation updated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 1.0.0 2010/09/20
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Production release and review comments incorporated
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.7 2010/06/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Misra-C changes done
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
*
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_opt_q7.c
|
* Title: arm_conv_opt_q7.c
|
||||||
|
|
@ -11,30 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.10 2011/7/15
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.3 2010/11/29
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.2 2010/11/11
|
*
|
||||||
* Documentation updated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 1.0.0 2010/09/20
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Production release and review comments incorporated
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.7 2010/06/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Misra-C changes done
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
*
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------------
|
/* ----------------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_partial_f32.c
|
* Title: arm_conv_partial_f32.c
|
||||||
|
|
@ -11,30 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.10 2011/7/15
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.3 2010/11/29
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.2 2010/11/11
|
*
|
||||||
* Documentation updated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 1.0.0 2010/09/20
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Production release and review comments incorporated
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.7 2010/06/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Misra-C changes done
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
*
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------------- */
|
* -------------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -102,7 +103,7 @@ arm_status arm_conv_partial_f32(
|
||||||
{
|
{
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -652,7 +653,7 @@ arm_status arm_conv_partial_f32(
|
||||||
}
|
}
|
||||||
return (status);
|
return (status);
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_partial_fast_opt_q15.c
|
* Title: arm_conv_partial_fast_opt_q15.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
* Target Processor: Cortex-M4/Cortex-M3
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.10 2011/7/15
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.3 2010/11/29
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.2 2010/11/11
|
*
|
||||||
* Documentation updated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 1.0.0 2010/09/20
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Production release and review comments incorporated.
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_partial_fast_q15.c
|
* Title: arm_conv_partial_fast_q15.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
* Target Processor: Cortex-M4/Cortex-M3
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this
|
||||||
|
* software without specific prior written permission.
|
||||||
*
|
*
|
||||||
* Version 1.0.10 2011/7/15
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
*
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Version 1.0.3 2010/11/29
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
*
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Version 1.0.2 2010/11/11
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
* Documentation updated.
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
*
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
* Production release and review comments incorporated.
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
*
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* Version 1.0.0 2010/09/20
|
|
||||||
* Production release and review comments incorporated.
|
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_partial_fast_q31.c
|
* Title: arm_conv_partial_fast_q31.c
|
||||||
|
|
@ -11,26 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
* Target Processor: Cortex-M4/Cortex-M3
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.10 2011/7/15
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.3 2010/11/29
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.2 2010/11/11
|
*
|
||||||
* Documentation updated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 1.0.0 2010/09/20
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Production release and review comments incorporated.
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_partial_opt_q15.c
|
* Title: arm_conv_partial_opt_q15.c
|
||||||
|
|
@ -11,30 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
* Target Processor: Cortex-M4/Cortex-M3
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.10 2011/7/15
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.3 2010/11/29
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.2 2010/11/11
|
*
|
||||||
* Documentation updated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 1.0.0 2010/09/20
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Production release and review comments incorporated
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.7 2010/06/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Misra-C changes done
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
*
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_partial_opt_q7.c
|
* Title: arm_conv_partial_opt_q7.c
|
||||||
|
|
@ -11,30 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
* Target Processor: Cortex-M4/Cortex-M3
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.10 2011/7/15
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.3 2010/11/29
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.2 2010/11/11
|
*
|
||||||
* Documentation updated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 1.0.0 2010/09/20
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Production release and review comments incorporated
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.7 2010/06/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Misra-C changes done
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
*
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_partial_q15.c
|
* Title: arm_conv_partial_q15.c
|
||||||
|
|
@ -11,30 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this
|
||||||
|
* software without specific prior written permission.
|
||||||
*
|
*
|
||||||
* Version 1.0.10 2011/7/15
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
*
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Version 1.0.3 2010/11/29
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
*
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Version 1.0.2 2010/11/11
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
* Documentation updated.
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
*
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
* Production release and review comments incorporated.
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
*
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* Version 1.0.0 2010/09/20
|
|
||||||
* Production release and review comments incorporated
|
|
||||||
*
|
|
||||||
* Version 0.0.7 2010/06/10
|
|
||||||
* Misra-C changes done
|
|
||||||
*
|
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_partial_q31.c
|
* Title: arm_conv_partial_q31.c
|
||||||
|
|
@ -11,30 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.10 2011/7/15
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.3 2010/11/29
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.2 2010/11/11
|
*
|
||||||
* Documentation updated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 1.0.0 2010/09/20
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Production release and review comments incorporated
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.7 2010/06/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Misra-C changes done
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
*
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -73,7 +74,7 @@ arm_status arm_conv_partial_q31(
|
||||||
{
|
{
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -590,7 +591,7 @@ arm_status arm_conv_partial_q31(
|
||||||
}
|
}
|
||||||
return (status);
|
return (status);
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_partial_q7.c
|
* Title: arm_conv_partial_q7.c
|
||||||
|
|
@ -11,30 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this
|
||||||
|
* software without specific prior written permission.
|
||||||
*
|
*
|
||||||
* Version 1.0.10 2011/7/15
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
*
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Version 1.0.3 2010/11/29
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
*
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Version 1.0.2 2010/11/11
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
* Documentation updated.
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
*
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
* Production release and review comments incorporated.
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
*
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* Version 1.0.0 2010/09/20
|
|
||||||
* Production release and review comments incorporated
|
|
||||||
*
|
|
||||||
* Version 0.0.7 2010/06/10
|
|
||||||
* Misra-C changes done
|
|
||||||
*
|
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -75,7 +76,7 @@ arm_status arm_conv_partial_q7(
|
||||||
{
|
{
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -724,7 +725,7 @@ arm_status arm_conv_partial_q7(
|
||||||
}
|
}
|
||||||
return (status);
|
return (status);
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_q15.c
|
* Title: arm_conv_q15.c
|
||||||
|
|
@ -11,30 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this
|
||||||
|
* software without specific prior written permission.
|
||||||
*
|
*
|
||||||
* Version 1.0.10 2011/7/15
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
*
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Version 1.0.3 2010/11/29
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
*
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Version 1.0.2 2010/11/11
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
* Documentation updated.
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
*
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
* Production release and review comments incorporated.
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
*
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* Version 1.0.0 2010/09/20
|
|
||||||
* Production release and review comments incorporated
|
|
||||||
*
|
|
||||||
* Version 0.0.7 2010/06/10
|
|
||||||
* Misra-C changes done
|
|
||||||
*
|
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_q31.c
|
* Title: arm_conv_q31.c
|
||||||
|
|
@ -11,30 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
*
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
* Version 1.0.10 2011/7/15
|
* notice, this list of conditions and the following disclaimer in
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* the documentation and/or other materials provided with the
|
||||||
*
|
* distribution.
|
||||||
* Version 1.0.3 2010/11/29
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* may be used to endorse or promote products derived from this
|
||||||
*
|
* software without specific prior written permission.
|
||||||
* Version 1.0.2 2010/11/11
|
*
|
||||||
* Documentation updated.
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
*
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Production release and review comments incorporated.
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
*
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
* Version 1.0.0 2010/09/20
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Production release and review comments incorporated
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
*
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
* Version 0.0.7 2010/06/10
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Misra-C changes done
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
*
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -83,7 +84,7 @@ void arm_conv_q31(
|
||||||
{
|
{
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -555,7 +556,7 @@ void arm_conv_q31(
|
||||||
pDst[i] = (q31_t) (sum >> 31u);
|
pDst[i] = (q31_t) (sum >> 31u);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,8 +1,8 @@
|
||||||
/* ----------------------------------------------------------------------
|
/* ----------------------------------------------------------------------
|
||||||
* Copyright (C) 2010 ARM Limited. All rights reserved.
|
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
|
||||||
*
|
*
|
||||||
* $Date: 15. February 2012
|
* $Date: 17. January 2013
|
||||||
* $Revision: V1.1.0
|
* $Revision: V1.4.1
|
||||||
*
|
*
|
||||||
* Project: CMSIS DSP Library
|
* Project: CMSIS DSP Library
|
||||||
* Title: arm_conv_q7.c
|
* Title: arm_conv_q7.c
|
||||||
|
|
@ -11,30 +11,31 @@
|
||||||
*
|
*
|
||||||
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
|
||||||
*
|
*
|
||||||
* Version 1.1.0 2012/02/15
|
* Redistribution and use in source and binary forms, with or without
|
||||||
* Updated with more optimizations, bug fixes and minor API changes.
|
* modification, are permitted provided that the following conditions
|
||||||
*
|
* are met:
|
||||||
* Version 1.0.11 2011/10/18
|
* - Redistributions of source code must retain the above copyright
|
||||||
* Bug Fix in conv, correlation, partial convolution.
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* - Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||||
|
* may be used to endorse or promote products derived from this
|
||||||
|
* software without specific prior written permission.
|
||||||
*
|
*
|
||||||
* Version 1.0.10 2011/7/15
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
* Big Endian support added and Merged M0 and M3/M4 Source code.
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
*
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
* Version 1.0.3 2010/11/29
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
* Re-organized the CMSIS folders and updated documentation.
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
*
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
* Version 1.0.2 2010/11/11
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
* Documentation updated.
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
*
|
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
* Version 1.0.1 2010/10/05
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
* Production release and review comments incorporated.
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
*
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
* Version 1.0.0 2010/09/20
|
|
||||||
* Production release and review comments incorporated
|
|
||||||
*
|
|
||||||
* Version 0.0.7 2010/06/10
|
|
||||||
* Misra-C changes done
|
|
||||||
*
|
|
||||||
* -------------------------------------------------------------------- */
|
* -------------------------------------------------------------------- */
|
||||||
|
|
||||||
#include "arm_math.h"
|
#include "arm_math.h"
|
||||||
|
|
@ -81,7 +82,7 @@ void arm_conv_q7(
|
||||||
{
|
{
|
||||||
|
|
||||||
|
|
||||||
#ifndef ARM_MATH_CM0
|
#ifndef ARM_MATH_CM0_FAMILY
|
||||||
|
|
||||||
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
/* Run the below code for Cortex-M4 and Cortex-M3 */
|
||||||
|
|
||||||
|
|
@ -680,7 +681,7 @@ void arm_conv_q7(
|
||||||
pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
|
pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* #ifndef ARM_MATH_CM0 */
|
#endif /* #ifndef ARM_MATH_CM0_FAMILY */
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue