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MCUXpresso: Update the Kinetis Serial driver for MBED_TICKLESS 

We should not block in case the UART is busy transmitting. The
API has been updated to check the status of all UART's and return
1 in case any of them is busy transmitting.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
pull/11412/head
Mahesh Mahadevan 2019-09-04 10:42:51 -05:00
parent 6eca8d2e2e
commit e65012e549
10 changed files with 413 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/serial_api.c
View File

@ -37,7 +37,6 @@ static UART_Type *const uart_addrs[] = UART_BASE_PTRS;
/* Array of UART bus clock frequencies */
static clock_name_t const uart_clocks[] = UART_CLOCK_FREQS;
int stdio_uart_inited = 0;
serial_t stdio_uart;
@ -340,14 +339,55 @@ const PinMap *serial_rts_pinmap()
return PinMap_UART_RTS;
}
void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
UART_Type *base = uart_addrs[uart_index];
/* Wait till data is flushed out of transmit buffer */
while (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base)))
{
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT;
break;
case 2:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT;
break;
case 3:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART3_MASK) >> SIM_SCGC4_UART3_SHIFT;
break;
case 4:
clock_enabled = (SIM->SCGC1 & SIM_SCGC1_UART4_MASK) >> SIM_SCGC1_UART4_SHIFT;
break;
default:
break;
}
return clock_enabled;
}
bool serial_check_tx_ongoing()
{
UART_Type *base;
int i;
bool uart_tx_ongoing = false;
for (i = 0; i < FSL_FEATURE_SOC_UART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}
base = uart_addrs[i];
/* Check if data is waiting to be written out of transmit buffer */
if (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}
return uart_tx_ongoing;
}
#endif

53
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/serial_api.c
View File

@ -332,14 +332,55 @@ const PinMap *serial_rts_pinmap()
return PinMap_UART_RTS;
}
void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
LPUART_Type *base = uart_addrs[uart_index];
/* Wait till data is flushed out of transmit buffer */
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
{
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART0_MASK) >> SIM_SCGC2_LPUART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART1_MASK) >> SIM_SCGC2_LPUART1_SHIFT;
break;
case 2:
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART2_MASK) >> SIM_SCGC2_LPUART2_SHIFT;
break;
case 3:
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART3_MASK) >> SIM_SCGC2_LPUART3_SHIFT;
break;
case 4:
clock_enabled = (SIM->SCGC2 & SIM_SCGC2_LPUART4_MASK) >> SIM_SCGC2_LPUART4_SHIFT;
break;
default:
break;
}
return clock_enabled;
}
bool serial_check_tx_ongoing()
{
LPUART_Type *base;
int i;
bool uart_tx_ongoing = false;
for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}
base = uart_addrs[i];
/* Check if data is waiting to be written out of transmit buffer */
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}
return uart_tx_ongoing;
}
#endif

44
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/serial_api.c
View File

@ -288,14 +288,46 @@ const PinMap *serial_rts_pinmap()
return PinMap_UART_RTS;
}
void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
LPUART_Type *base = uart_addrs[uart_index];
/* Wait till data is flushed out of transmit buffer */
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
{
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART1_MASK) >> SIM_SCGC5_LPUART1_SHIFT;
break;
default:
break;
}
return clock_enabled;
}
bool serial_check_tx_ongoing()
{
LPUART_Type *base;
int i;
bool uart_tx_ongoing = false;
for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}
base = uart_addrs[i];
/* Check if data is waiting to be written out of transmit buffer */
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}
return uart_tx_ongoing;
}
#endif

44
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/serial_api.c
View File

@ -300,14 +300,46 @@ const PinMap *serial_rts_pinmap()
return PinMap_UART_RTS;
}
void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
LPUART_Type *base = uart_addrs[uart_index];
/* Wait till data is flushed out of transmit buffer */
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
{
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART1_MASK) >> SIM_SCGC5_LPUART1_SHIFT;
break;
default:
break;
}
return clock_enabled;
}
bool serial_check_tx_ongoing()
{
LPUART_Type *base;
int i;
bool uart_tx_ongoing = false;
for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}
base = uart_addrs[i];
/* Check if data is waiting to be written out of transmit buffer */
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}
return uart_tx_ongoing;
}
#endif

47
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/serial_api.c
View File

@ -328,14 +328,49 @@ const PinMap *serial_rts_pinmap()
return PinMap_UART_RTS;
}
void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
LPUART_Type *base = uart_addrs[uart_index];
/* Wait till data is flushed out of transmit buffer */
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
{
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART1_MASK) >> SIM_SCGC5_LPUART1_SHIFT;
break;
case 2:
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART2_MASK) >> SIM_SCGC5_LPUART2_SHIFT;
break;
default:
break;
}
return clock_enabled;
}
bool serial_check_tx_ongoing()
{
LPUART_Type *base;
int i;
bool uart_tx_ongoing = false;
for (i = 0; i < FSL_FEATURE_SOC_LPUART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}
base = uart_addrs[i];
/* Check if data is waiting to be written out of transmit buffer */
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}
return uart_tx_ongoing;
}
#endif

47
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/serial_api.c
View File

@ -327,14 +327,49 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi
#endif
void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
UART_Type *base = uart_addrs[uart_index];
/* Wait till data is flushed out of transmit buffer */
while (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base)))
{
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT;
break;
case 2:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT;
break;
default:
break;
}
return clock_enabled;
}
bool serial_check_tx_ongoing()
{
UART_Type *base;
int i;
bool uart_tx_ongoing = false;
for (i = 0; i < FSL_FEATURE_SOC_UART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}
base = uart_addrs[i];
/* Check if data is waiting to be written out of transmit buffer */
if (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}
return uart_tx_ongoing;
}
#endif

25
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/serial_api.c
View File

@ -282,14 +282,29 @@ const PinMap *serial_rts_pinmap()
return PinMap_UART_RTS;
}
void serial_wait_tx_complete(uint32_t uart_index)
bool serial_check_tx_ongoing()
{
LPUART_Type *base = uart_addrs[uart_index];
LPUART_Type *base;
int i;
bool uart_tx_ongoing = false;
int clock_enabled = 0;
/* Wait till data is flushed out of transmit buffer */
while (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base)))
{
/* First check if UART is enabled */
clock_enabled = (SIM->SCGC5 & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT;
if (!clock_enabled) {
/* UART is not enabled return */
return uart_tx_ongoing;
}
base = uart_addrs[i];
/* Check if data is waiting to be written out of transmit buffer */
if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) {
uart_tx_ongoing = true;
}
return uart_tx_ongoing;
}
#endif

47
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/serial_api.c
View File

@ -302,14 +302,49 @@ const PinMap *serial_rts_pinmap()
return PinMap_UART_RTS;
}
void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
UART_Type *base = uart_addrs[uart_index];
/* Wait till data is flushed out of transmit buffer */
while (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base)))
{
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT;
break;
case 2:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT;
break;
default:
break;
}
return clock_enabled;
}
bool serial_check_tx_ongoing()
{
UART_Type *base;
int i;
bool uart_tx_ongoing = false;
for (i = 0; i < FSL_FEATURE_SOC_UART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}
base = uart_addrs[i];
/* Check if data is waiting to be written out of transmit buffer */
if (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}
return uart_tx_ongoing;
}
#endif

56
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/serial_api.c
View File

@ -723,14 +723,58 @@ void serial_rx_abort_asynch(serial_t *obj)
}
}
void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
UART_Type *base = uart_addrs[uart_index];
/* Wait till data is flushed out of transmit buffer */
while (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base)))
{
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT;
break;
case 2:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT;
break;
case 3:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART3_MASK) >> SIM_SCGC4_UART3_SHIFT;
break;
case 4:
clock_enabled = (SIM->SCGC1 & SIM_SCGC1_UART4_MASK) >> SIM_SCGC1_UART4_SHIFT;
break;
case 5:
clock_enabled = (SIM->SCGC1 & SIM_SCGC1_UART5_MASK) >> SIM_SCGC1_UART5_SHIFT;
break;
default:
break;
}
return clock_enabled;
}
bool serial_check_tx_ongoing()
{
UART_Type *base;
int i;
bool uart_tx_ongoing = false;
for (i = 0; i < FSL_FEATURE_SOC_UART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}
base = uart_addrs[i];
/* Check if data is waiting to be written out of transmit buffer */
if (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}
return uart_tx_ongoing;
}
#endif

56
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/serial_api.c
View File

@ -766,14 +766,58 @@ void serial_rx_abort_asynch(serial_t *obj)
sleep_manager_unlock_deep_sleep();
}
void serial_wait_tx_complete(uint32_t uart_index)
static int serial_is_enabled(uint32_t uart_index)
{
UART_Type *base = uart_addrs[uart_index];
/* Wait till data is flushed out of transmit buffer */
while (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base)))
{
int clock_enabled = 0;
switch (uart_index) {
case 0:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART0_MASK) >> SIM_SCGC4_UART0_SHIFT;
break;
case 1:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART1_MASK) >> SIM_SCGC4_UART1_SHIFT;
break;
case 2:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART2_MASK) >> SIM_SCGC4_UART2_SHIFT;
break;
case 3:
clock_enabled = (SIM->SCGC4 & SIM_SCGC4_UART3_MASK) >> SIM_SCGC4_UART3_SHIFT;
break;
case 4:
clock_enabled = (SIM->SCGC1 & SIM_SCGC1_UART4_MASK) >> SIM_SCGC1_UART4_SHIFT;
break;
case 5:
clock_enabled = (SIM->SCGC1 & SIM_SCGC1_UART5_MASK) >> SIM_SCGC1_UART5_SHIFT;
break;
default:
break;
}
return clock_enabled;
}
bool serial_check_tx_ongoing()
{
UART_Type *base;
int i;
bool uart_tx_ongoing = false;
for (i = 0; i < FSL_FEATURE_SOC_UART_COUNT; i++) {
/* First check if UART is enabled */
if (!serial_is_enabled(i)) {
/* UART is not enabled, check the next instance */
continue;
}
base = uart_addrs[i];
/* Check if data is waiting to be written out of transmit buffer */
if (!(kUART_TransmissionCompleteFlag & UART_GetStatusFlags((UART_Type *)base))) {
uart_tx_ongoing = true;
break;
}
}
return uart_tx_ongoing;
}
#endif