diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct
index c018724bf7..395f105294 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct
@@ -27,10 +27,11 @@
 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
-LR_IROM1 0x08000000 0x80000  {    ; load region size_region
+; STM32F411RE: 480 KB FLASH (0x78000) + 128 KB SRAM (0x20000)
+; FIRST 32 KB FLASH FOR BOOTLOADER
+LR_IROM1 0x08008000 0x78000  {    ; load region size_region
 
-  ER_IROM1 0x08000000 0x80000  {  ; load address = execution address
+  ER_IROM1 0x08008000 0x78000  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct
index c018724bf7..395f105294 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct
@@ -27,10 +27,11 @@
 ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
-LR_IROM1 0x08000000 0x80000  {    ; load region size_region
+; STM32F411RE: 480 KB FLASH (0x78000) + 128 KB SRAM (0x20000)
+; FIRST 32 KB FLASH FOR BOOTLOADER
+LR_IROM1 0x08008000 0x78000  {    ; load region size_region
 
-  ER_IROM1 0x08000000 0x80000  {  ; load address = execution address
+  ER_IROM1 0x08008000 0x78000  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld
index 76a7538cde..b5ea4dd53e 100644
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld
@@ -3,7 +3,8 @@
 /* Linker script to configure memory regions. */
 MEMORY
 { 
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+  /* First 32kB of flash reserved for bootloader */
+  FLASH (rx) : ORIGIN = 0x08008000, LENGTH = 480K
 /*  CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K */
   RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
 }
diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index 69959e0749..c46b5aa65a 100644
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -711,7 +711,7 @@ class MTS_DRAGONFLY_F411RE(Target):
         Target.__init__(self)
         self.core = "Cortex-M4F"
         self.extra_labels = ['STM', 'STM32F4', 'STM32F411RE']
-        self.macros = ['HSE_VALUE=26000000']
+        self.macros = ['HSE_VALUE=26000000', 'VECT_TAB_OFFSET=0x08008000']
         self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"]
         self.default_toolchain = "ARM"