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Merge pull request #700 from masaohamanaka/master 

[RZ_A1H]Fixed a bug of CMSIS-RTOS RTX for Cortex-A9
pull/672/merge
Bogdan Marinescu 2014-11-14 11:51:11 +00:00
parent c4901dbb33 7e735c41b6
commit e53ae9e840
1 changed files with 2 additions and 2 deletions
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4
libraries/rtos/rtx/TARGET_CORTEX_A/rt_HAL_CA.h
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@ -108,7 +108,7 @@ extern const U32 GICInterface_BASE;
/* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c-
* OS_X_INIT enables the IRQ n in the GIC */ * OS_X_INIT enables the IRQ n in the GIC */
#define OS_X_INIT(n) char *reg; \ #define OS_X_INIT(n) volatile char *reg; \
reg = (char *)(&GICD_ICDIPR0 + n / 4); \ reg = (char *)(&GICD_ICDIPR0 + n / 4); \
reg += n % 4; \ reg += n % 4; \
*reg = (char)0xff; \ *reg = (char)0xff; \
@ -163,7 +163,7 @@ __inline static void rt_systick_init (void) {
__inline static void rt_svc_init (void) { __inline static void rt_svc_init (void) {
/* Register pendSV - through SGI */ /* Register pendSV - through SGI */
char *reg; volatile char *reg;
reg = (char *)(&GICD_ICDIPR0 + SGI_PENDSV/4); reg = (char *)(&GICD_ICDIPR0 + SGI_PENDSV/4);
reg += SGI_PENDSV % 4; reg += SGI_PENDSV % 4;