mirror of https://github.com/ARMmbed/mbed-os.git
Configure most modules to non-secure
All modules are configured to non-secure except: 1. TIMER0/1 hard-wired to secure and TIMER2/3 reserved for non-secure. 2. PDMA0 hard-wired to secure and PDMA1 reserved for non-secure. 3. RTC configured to secure and shared to non-secure through NSC. 4. CRYPTO configured to secure and shared to non-secure through NSC.pull/7631/head
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@ -326,7 +326,7 @@
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// <o.31> PWM1_P2 <0=> Secure <1=> Non-Secure
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// <o.31> PWM1_P2 <0=> Secure <1=> Non-Secure
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//
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//
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*/
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*/
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#define NVIC_INIT_ITNS0_VAL 0x3F0040
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#define NVIC_INIT_ITNS0_VAL 0xFFFFFFBF
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/*
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/*
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Initialize ITNS 1 (Interrupts 0..31)
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Initialize ITNS 1 (Interrupts 0..31)
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@ -367,7 +367,7 @@
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//
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//
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*/
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*/
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#define NVIC_INIT_ITNS1_VAL 0x1C
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#define NVIC_INIT_ITNS1_VAL 0xFFFFFEFC
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/*
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/*
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Initialize ITNS 2 (Interrupts 0..31)
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Initialize ITNS 2 (Interrupts 0..31)
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@ -408,7 +408,7 @@
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//
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//
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*/
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*/
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#define NVIC_INIT_ITNS2_VAL 0x000
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#define NVIC_INIT_ITNS2_VAL 0xFFFFFF7F
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/*
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/*
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@ -423,7 +423,7 @@
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// <o.4> LCD <0=> Secure <1=> Non-Secure
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// <o.4> LCD <0=> Secure <1=> Non-Secure
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// <o.5> TRNG <0=> Secure <1=> Non-Secure
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// <o.5> TRNG <0=> Secure <1=> Non-Secure
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*/
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*/
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#define NVIC_INIT_ITNS3_VAL 0x0
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#define NVIC_INIT_ITNS3_VAL 0xFFFFFFFF
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@ -556,7 +556,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
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// <o.16> EBI <0=> Secure <1=> Non-Secure
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// <o.16> EBI <0=> Secure <1=> Non-Secure
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// <o.24> PDMA1 <0=> Secure <1=> Non-Secure
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// <o.24> PDMA1 <0=> Secure <1=> Non-Secure
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*/
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*/
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#define SCU_INIT_PNSSET0_VAL 0x00000001
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#define SCU_INIT_PNSSET0_VAL 0xFFFFFFFF
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/*
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/*
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PNSSET1
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PNSSET1
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*/
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*/
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@ -565,7 +565,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
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// <o.17> CRC <0=> Secure <1=> Non-Secure
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// <o.17> CRC <0=> Secure <1=> Non-Secure
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// <o.18> CRPT <0=> Secure <1=> Non-Secure
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// <o.18> CRPT <0=> Secure <1=> Non-Secure
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*/
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*/
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#define SCU_INIT_PNSSET1_VAL 0x00040000
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#define SCU_INIT_PNSSET1_VAL 0xFFFBFFFF
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/*
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/*
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PNSSET2
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PNSSET2
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*/
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*/
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@ -584,7 +584,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
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// <o.26> BPWM0 <0=> Secure <1=> Non-Secure
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// <o.26> BPWM0 <0=> Secure <1=> Non-Secure
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// <o.27> BPWM1 <0=> Secure <1=> Non-Secure
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// <o.27> BPWM1 <0=> Secure <1=> Non-Secure
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*/
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*/
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#define SCU_INIT_PNSSET2_VAL 0x00020002
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#define SCU_INIT_PNSSET2_VAL 0xFFFFFFFD
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/*
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/*
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PNSSET3
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PNSSET3
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*/
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*/
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@ -603,7 +603,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
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// <o.20> UART4 <0=> Secure <1=> Non-Secure
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// <o.20> UART4 <0=> Secure <1=> Non-Secure
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// <o.21> UART5 <0=> Secure <1=> Non-Secure
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// <o.21> UART5 <0=> Secure <1=> Non-Secure
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*/
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*/
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#define SCU_INIT_PNSSET3_VAL 0x00010000
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#define SCU_INIT_PNSSET3_VAL 0xFFFFFFFF
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/*
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/*
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PNSSET4
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PNSSET4
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*/
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*/
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@ -616,7 +616,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
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// <o.17> SC1 <0=> Secure <1=> Non-Secure
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// <o.17> SC1 <0=> Secure <1=> Non-Secure
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// <o.18> SC2 <0=> Secure <1=> Non-Secure
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// <o.18> SC2 <0=> Secure <1=> Non-Secure
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*/
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*/
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#define SCU_INIT_PNSSET4_VAL 0x00000000
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#define SCU_INIT_PNSSET4_VAL 0xFFFFFFFF
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/*
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/*
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PNSSET5
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PNSSET5
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*/
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*/
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@ -631,7 +631,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
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// <o.24> LCD <0=> Secure <1=> Non-Secure
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// <o.24> LCD <0=> Secure <1=> Non-Secure
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// <o.25> TRNG <0=> Secure <1=> Non-Secure
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// <o.25> TRNG <0=> Secure <1=> Non-Secure
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*/
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*/
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#define SCU_INIT_PNSSET5_VAL 0x00000000
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#define SCU_INIT_PNSSET5_VAL 0xFFFFFFFF
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/*
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/*
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PNSSET6
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PNSSET6
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*/
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*/
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@ -641,7 +641,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
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// <o.16> USCI0 <0=> Secure <1=> Non-Secure
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// <o.16> USCI0 <0=> Secure <1=> Non-Secure
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// <o.17> USCI1 <0=> Secure <1=> Non-Secure
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// <o.17> USCI1 <0=> Secure <1=> Non-Secure
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*/
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*/
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#define SCU_INIT_PNSSET6_VAL 0x00000000
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#define SCU_INIT_PNSSET6_VAL 0xFFFFFFFF
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/*
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/*
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// </h>
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// </h>
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*/
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*/
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@ -665,7 +665,7 @@ __STATIC_INLINE void TZ_SAU_Setup(void)
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// <o.5> PF <0=> Secure <1=> Non-Secure
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// <o.5> PF <0=> Secure <1=> Non-Secure
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// <o.6> PG <0=> Secure <1=> Non-Secure
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// <o.6> PG <0=> Secure <1=> Non-Secure
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*/
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*/
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#define SCU_INIT_IONSSET_VAL 0x0000007F
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#define SCU_INIT_IONSSET_VAL 0xFFFFFFFF
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/*
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/*
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// </h>
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// </h>
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*/
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*/
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