From db389d4b4b3cf6cf080926399bef2584ab896ba1 Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Fri, 21 Feb 2020 10:54:42 +0200 Subject: [PATCH 01/49] Squashed 'features/frameworks/nanostack-libservice/' changes from 9af756886f..9a61e73787 9a61e73787 Merge pull request #89 from ARMmbed/update_from_mbedos 2a07f443ed Fixed typo: 'lenght' in ip6string.h 050aa7f31a Include ns_types.h before mbed_trace.h in Nanomesh git-subtree-dir: features/frameworks/nanostack-libservice git-subtree-split: 9a61e737872ba60fa73e9375011f63e9e266577a --- mbed-client-libservice/ip6string.h | 2 +- mbed-client-libservice/ns_trace.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/mbed-client-libservice/ip6string.h b/mbed-client-libservice/ip6string.h index 0f3cec5613..34ee097b34 100644 --- a/mbed-client-libservice/ip6string.h +++ b/mbed-client-libservice/ip6string.h @@ -57,7 +57,7 @@ uint_fast8_t ip6_prefix_tos(const void *prefix, uint_fast8_t prefix_len, char *p * IPv4 tunneling addresses are not covered. * * \param ip6addr IPv6 address in string format. - * \param len Lenght of ipv6 string, maximum of 41. + * \param len Length of ipv6 string, maximum of 41. * \param dest buffer for address. MUST be 16 bytes. Filled with 0 on error. * \return boolean set to true if conversion succeed, false if it didn't */ diff --git a/mbed-client-libservice/ns_trace.h b/mbed-client-libservice/ns_trace.h index 206e239982..2219f8b808 100644 --- a/mbed-client-libservice/ns_trace.h +++ b/mbed-client-libservice/ns_trace.h @@ -28,6 +28,7 @@ #define FEA_TRACE_SUPPORT #endif +#include "ns_types.h" #include "mbed-trace/mbed_trace.h" #endif /* NS_TRACE_H_ */ From c9610e1a78b2b94fb659539b30d7fb4e0f1e36c8 Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Fri, 21 Feb 2020 10:59:22 +0200 Subject: [PATCH 02/49] Squashed 'features/nanostack/coap-service/' changes from b919a3366f..e5e0c138e6 e5e0c138e6 Merge pull request #126 from ARMmbed/sync_from_mbedos 475b8f13fc Fixed typo: 'lenght' in coap_service_api.h git-subtree-dir: features/nanostack/coap-service git-subtree-split: e5e0c138e68bfd9a4687e1b02ec4c7c95b2617f6 --- coap-service/coap_service_api.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/coap-service/coap_service_api.h b/coap-service/coap_service_api.h index 99fcf03e4e..edacd971de 100644 --- a/coap-service/coap_service_api.h +++ b/coap-service/coap_service_api.h @@ -184,7 +184,7 @@ extern void coap_service_close_secure_connection(int8_t service_id, uint8_t dest * \param destination_addr_ptr Receiver IPv6 address. * \param port Receiver port number. * \param *data_ptr Pointer to the data. - * \param data_len Lenght of the data. + * \param data_len Length of the data. * * \return 0 for success / -1 for failure */ @@ -199,7 +199,7 @@ typedef int coap_service_virtual_socket_send_cb(int8_t service_id, uint8_t desti * \param source_addr_ptr Receiver IPv6 address. * \param port Receiver port number. * \param *data_ptr Pointer to the data - * \param data_len Lenght of the data + * \param data_len Length of the data * * \return 0 for success / -1 for failure */ @@ -257,7 +257,7 @@ extern int8_t coap_service_unregister_uri(int8_t service_id, const char *uri); * \param *uri Uri address. * \param cont_type Content type can be found from sn_coap_header. * \param payload_ptr Pointer to message content. - * \param payload_len Lenght of the message. + * \param payload_len Length of the message. * \param *request_response_cb Callback to inform result of the request. * * \return msg_id Id number of the current message. @@ -276,7 +276,7 @@ extern uint16_t coap_service_request_send(int8_t service_id, uint8_t options, co * \param message_code Message code can be found from sn_coap_header. * \param content_type Content type can be found from sn_coap_header. * \param payload_ptr Pointer to message content. - * \param payload_len Lenght of the message. + * \param payload_len Length of the message. * * \return -1 For failure *- 0 For success @@ -295,7 +295,7 @@ extern int8_t coap_service_response_send(int8_t service_id, uint8_t options, sn_ * \param message_code Message code can be found from sn_coap_header. * \param content_type Content type can be found from sn_coap_header. * \param payload_ptr Pointer to message content. - * \param payload_len Lenght of the message. + * \param payload_len Length of the message. * * \return -1 For failure *- 0 For success From 2792e61d87df13c64d8abaf30ccde13b6f75eeda Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Fri, 21 Feb 2020 10:59:35 +0200 Subject: [PATCH 03/49] Squashed 'features/nanostack/sal-stack-nanostack/' changes from 9b3e144f5b..fb7413b846 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fb7413b846 Merge branch 'release_internal' into release_external a9f6e88978 Merge branch 'master' into release_internal c536960fb0 DHCPv6 Server feature update 01e7e820d5 Merge pull request #2314 from ARMmbed/update_from_mbedos c906c43a8a Fixed typo: 'lenght' in ns_crc.h 2bd05584fe Wi-sun border router DHCPv6 server address alocation update 63e4680ca3 Allow buffer_dyn to handle more data (#2311) 9b82abff03 Copy IE unicast channel function from WS info instead of FHSS configu… (#2310) 18247d546f Wi-sun RPL memory soft and hard limit update c8560dbe01 Updated RPL default memory sof and hard limit to 2/4 from 1/2. 05aa54c464 Update MPL parameters to follow Specification f728d55920 Support for handle CRC error which will automatically change a channel. 6b6f535828 Corrected EUI-64 address bit flip on supplicant 015f3fe60e Corrected bitfield definition 7717ef8c60 Improved initial EAPOL-key send stop logic on supplicant 4185734223 Improved EAPOL key update retry logic 8bda176445 Wi-sun boot fix 6283dfd643 DIO advertisment fix 1acec7cdcc Aro Registation and Dao update 6cde17ad9c Iotthd 3963 2 (#2301) b9187daa62 Randomize fixed channel when making new parent selection 34d0339a4d Wi-sun address registartion update 5b3055904a Allow unicast TX to overlap with MC (#2298) d40b1c7d01 MAC: Updated calling FHSS TX done (#2295) aeb93a16ae Add support for bbr configuration that removes default route from DIO 9b941af4b5 Use default UC channel function in discovery, fixed BC schedule (#2284) d65fcc6bf2 Fix Wi-SUN network name comparison (#2294) f085132543 Made parent set size configuraple in RPL fd11ffae1a Added HAVE_WS flag to FHSS api (#2296) 4f275005fb Implemented optimal packet size test api (#2292) 87ee16a22b Call channel change after filtered out packet d196ffc4c5 Refactor Wi-SUN BBR stop function 35970d7ea9 Revert "Disabled temporarily tx slot check for testing purposes (#2287)" (#2289) 8cc0ff508b Disabled temporarily tx slot check for testing purposes (#2287) e306dc5adb Removed extra ";" 5642a4fe74 Free TX failed list when FHSS deleted (#2285) 9fcf718d22 Updated FHSS optimal packet length to 300 bytes (#2282) 427743f718 ETX and Source route validation update 7b6bcca842 Added TX/RX bytes in PHY statistics (#2281) a043f8dc30 Wi-sun FHSS Management update 2ff90e6c0f Configure TXRX slot length using given datarate (#2275) a126cb750d ETX sampling rule update d5cf8d52e2 Clean ARMC6/GCC compiler warnings (#2278) 807632dd94 DHCP server freed next free allocated id fd6ce049a3 Thread Child ml16 update clear old address queue's and registered address. 99e6efac6c Neighbour remove operation update 5cd094cd1d Corrected GTK update initial EAPOL-key trickle timer 7606ee87a9 Wi-sun NS Aro registration blacklisting update e3e5a00c55 Timed parent selection timer trigger update 71441212ea RPL DIO Multicast message update 588f202a51 Wi-Sun RPL bootstrap update 20289f675d Added periodic RPL version number increase d8dd18d89b Added ignoring of incoming security messages and improved EAP-TLS startup 73506346ca Corrected initial EAPOL-key trickle retries ac33518493 Wi-sun ETX and proping update 11c486f391 Implemented unregistering FHSS from MAC. FHSS deleted in ifdown call. (#2266) eabca172af Wi-Sun Border router DHCPV server SLAAC mode enabled by default. 1d6ce9c0a4 DHCPv6 Server feature update 46aa46042d Fixed unit test's. c65292e9eb Mac enhanced ACK pending update 11a1e1d2de Store TX start channel and black list if TX failed (#2261) 04946065e4 Adapatation layer unicast list entry free update 4481e8635a Updated trace level to info. c9e3d8ef74 Interface down update 1f77ad6964 Updated trace levels (#2258) 1d82fd5a5d Wi-sun BBR route update fix 33c48eb647 Removed NUD messages from registered children ec2ea92b71 Added RX and TX active times in PHY statistics (#2255) 49686ccb3c Wi-sun certification test setup update 1090430622 Trickle API update and Wi-SUN config sol state timeout update 38df5768c5 Wi-sun advertisment consistent update 81740b8b1d Wi-sun bootstarp update nad balck list trace level update 6919ba1301 Wi-sun New key index activate. 0aead9305a Wi-sun Probe functionality revert operation 4ff02f9770 Stop sending normal ACK if neighbour is Unknown. c387fda238 NS Probe limiter accept only 2 probe at 16 seconds period. a58c71b96b Trace level updates (#2247) 6867dd7b27 Suplicant EAP-TLS timeout is not incremented from retries 1f1c2a24fa Test purpose change. 1b99fe18df Added ETX to rpl_possible_better_candidate 3441594157 RPL parent candidate list update 96ffe92744 Adaptation layer to support multiple simultaneous unicast transmissions (#2243) 45f851997f On stop (ifdown) stores frame counters regardless of threshold 5c2fc55f0e Corrected frame counter handling on re-discovery 930741617f Added check to prevent installing new GTK to used index using GKH 385ae14284 WS bootstrap: print MAC address 2b1dfb90ed Slaac address can be recreated after root stop 74ff3cc503 Merge branch 'release_internal' into release_external 66bfd985fb Fixed trace printing warnings. 21d9c24acd DHCP server address allocated pointer init fix. e659a01241 Fixed compile warning for may uninitialized usage. cee8502783 Fixed trace printing warnings. bc9f07bd49 DHCP server address allocated pointer init fix. e3fddadccf Fixed compile warning for may uninitialized usage. bf909d29d3 Modified bbr restart mechanism when dodagid was lost git-subtree-dir: features/nanostack/sal-stack-nanostack git-subtree-split: fb7413b846f0052d72c506ebab2534bcafdfff60 --- nanostack/fhss_api.h | 3 +- nanostack/fhss_test_api.h | 46 ++ nanostack/platform/arm_hal_phy.h | 7 +- nanostack/sw_mac.h | 7 + nanostack/ws_bbr_api.h | 12 +- .../Generic/protocol_6lowpan_bootstrap.c | 4 +- .../Generic/protocol_6lowpan_interface.c | 23 +- .../Bootstraps/protocol_6lowpan_interface.h | 2 + source/6LoWPAN/MAC/mac_helper.c | 1 + source/6LoWPAN/MAC/mac_response_handler.c | 1 + source/6LoWPAN/ND/nd_router_object.c | 17 +- source/6LoWPAN/Thread/thread_bootstrap.c | 2 +- source/6LoWPAN/Thread/thread_common.c | 2 + source/6LoWPAN/Thread/thread_management_if.c | 2 +- .../Thread/thread_mle_message_handler.c | 2 +- source/6LoWPAN/Thread/thread_network_synch.c | 19 +- .../6LoWPAN/Thread/thread_router_bootstrap.c | 8 - source/6LoWPAN/Thread/thread_test_api.c | 3 +- source/6LoWPAN/adaptation_interface.c | 158 ++++-- source/6LoWPAN/lowpan_adaptation_interface.h | 4 +- source/6LoWPAN/ws/ws_bbr_api.c | 141 ++++-- source/6LoWPAN/ws/ws_bbr_api_internal.h | 4 +- source/6LoWPAN/ws/ws_bootstrap.c | 462 +++++++++++------- source/6LoWPAN/ws/ws_bootstrap.h | 3 - source/6LoWPAN/ws/ws_common.c | 42 +- source/6LoWPAN/ws/ws_common.h | 26 +- source/6LoWPAN/ws/ws_common_defines.h | 6 +- source/6LoWPAN/ws/ws_config.h | 13 +- source/6LoWPAN/ws/ws_llc_data_service.c | 2 +- source/6LoWPAN/ws/ws_management_api.c | 77 ++- source/6LoWPAN/ws/ws_neighbor_class.h | 1 - source/6LoWPAN/ws/ws_pae_auth.c | 32 +- source/6LoWPAN/ws/ws_pae_auth.h | 2 +- source/6LoWPAN/ws/ws_pae_controller.c | 62 ++- source/6LoWPAN/ws/ws_pae_lib.c | 14 + source/6LoWPAN/ws/ws_pae_lib.h | 19 + source/6LoWPAN/ws/ws_pae_nvm_data.c | 10 +- source/6LoWPAN/ws/ws_pae_supp.c | 246 ++++++++-- source/6LoWPAN/ws/ws_pae_supp.h | 12 +- source/Common_Protocols/icmpv6.c | 8 +- source/Common_Protocols/icmpv6.h | 1 + source/Common_Protocols/icmpv6_radv.c | 3 + source/Common_Protocols/ipv6.c | 6 + source/Core/buffer_dyn.c | 43 +- source/Core/include/ns_buffer.h | 2 +- source/Core/ns_socket.c | 8 +- source/DHCPv6_Server/DHCPv6_Server_service.c | 67 +-- source/DHCPv6_Server/DHCPv6_server_service.h | 3 +- source/MAC/IEEE802_15_4/mac_defines.h | 2 + source/MAC/IEEE802_15_4/mac_fhss_callbacks.c | 9 +- source/MAC/IEEE802_15_4/mac_mcps_sap.c | 15 +- source/MAC/IEEE802_15_4/mac_mlme.c | 2 + source/MAC/IEEE802_15_4/mac_pd_sap.c | 62 ++- source/MAC/IEEE802_15_4/mac_security_mib.c | 19 + source/MAC/IEEE802_15_4/sw_mac.c | 14 + source/NWK_INTERFACE/protocol_core.c | 5 +- source/RPL/rpl_control.c | 157 +++++- source/RPL/rpl_control.h | 24 +- source/RPL/rpl_downward.c | 16 +- source/RPL/rpl_mrhof.c | 22 + source/RPL/rpl_objective.h | 5 +- source/RPL/rpl_of0.c | 10 + source/RPL/rpl_policy.c | 11 +- source/RPL/rpl_policy.h | 1 + source/RPL/rpl_structures.h | 9 +- source/RPL/rpl_upward.c | 156 ++++-- source/RPL/rpl_upward.h | 11 +- source/Security/TLS/tls_lib.c | 1 + .../eap_tls_sec_prot/auth_eap_tls_sec_prot.c | 39 +- .../eap_tls_sec_prot/supp_eap_tls_sec_prot.c | 29 +- .../fwh_sec_prot/auth_fwh_sec_prot.c | 3 +- .../gkh_sec_prot/auth_gkh_sec_prot.c | 3 + .../protocols/key_sec_prot/key_sec_prot.c | 4 +- source/Security/protocols/sec_prot_keys.c | 72 ++- source/Security/protocols/sec_prot_keys.h | 50 +- source/Service_Libs/Trickle/trickle.c | 20 + source/Service_Libs/Trickle/trickle.h | 5 + source/Service_Libs/blacklist/blacklist.c | 8 +- source/Service_Libs/etx/etx.c | 133 ++--- source/Service_Libs/etx/etx.h | 27 +- source/Service_Libs/fhss/fhss.c | 5 +- source/Service_Libs/fhss/fhss_common.c | 3 + source/Service_Libs/fhss/fhss_common.h | 1 + source/Service_Libs/fhss/fhss_test_api.c | 46 ++ source/Service_Libs/fhss/fhss_ws.c | 92 +++- source/Service_Libs/fhss/fhss_ws.h | 7 +- source/Service_Libs/utils/ns_crc.h | 2 +- source/libDHCPv6/dhcp_service_api.c | 2 +- source/libDHCPv6/libDHCPv6_server.c | 330 ++++++++++--- source/libDHCPv6/libDHCPv6_server.h | 49 +- source/libNET/src/net_6lowpan_parameter_api.c | 5 + source/libNET/src/net_load_balance.c | 16 +- source/libNET/src/ns_net.c | 9 +- source/libNET/src/socket_api.c | 9 +- sources.mk | 1 + 95 files changed, 2328 insertions(+), 831 deletions(-) create mode 100644 nanostack/fhss_test_api.h create mode 100644 source/Service_Libs/fhss/fhss_test_api.c diff --git a/nanostack/fhss_api.h b/nanostack/fhss_api.h index 84c0c17c32..be5a90c1d2 100644 --- a/nanostack/fhss_api.h +++ b/nanostack/fhss_api.h @@ -122,9 +122,10 @@ typedef void fhss_data_tx_done(const fhss_api_t *api, bool waiting_ack, bool tx_ * @param api FHSS instance. * @param handle Handle of the data request. * @param frame_type Frame type of packet (Frames types are defined by FHSS api). + * @param channel Channel wanted to black list temporarily. * @return true if frame has to be queued for retransmission, false otherwise. */ -typedef bool fhss_data_tx_fail(const fhss_api_t *api, uint8_t handle, int frame_type); +typedef bool fhss_data_tx_fail(const fhss_api_t *api, uint8_t handle, int frame_type, uint8_t channel); /** * @brief Change synchronization state. diff --git a/nanostack/fhss_test_api.h b/nanostack/fhss_test_api.h new file mode 100644 index 0000000000..270c5a27a3 --- /dev/null +++ b/nanostack/fhss_test_api.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file fhss_test_api.h + * \brief + */ + +#ifndef FHSS_TEST_API_H +#define FHSS_TEST_API_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set optimal packet length + * + * \param fhss_api FHSS instance. + * \param packet_length Optimal packet length + * + * \return 0 Success + * \return -1 Failure + */ +int8_t fhss_set_optimal_packet_length(const fhss_api_t *fhss_api, uint16_t packet_length); + +#ifdef __cplusplus +} +#endif + +#endif // FHSS_TEST_API_H diff --git a/nanostack/platform/arm_hal_phy.h b/nanostack/platform/arm_hal_phy.h index 9f4e09937d..ab53b5942c 100644 --- a/nanostack/platform/arm_hal_phy.h +++ b/nanostack/platform/arm_hal_phy.h @@ -161,7 +161,8 @@ typedef enum { CHANNEL_PAGE_5 = 5, ///< Page 5 CHANNEL_PAGE_6 = 6, ///< Page 6 CHANNEL_PAGE_9 = 9, ///< Page 9 - CHANNEL_PAGE_10 = 10 ///< Page 10 + CHANNEL_PAGE_10 = 10, ///< Page 10 + CHANNEL_PAGE_UNDEFINED ///< Undefined } channel_page_e; /** Modulation index */ @@ -192,6 +193,10 @@ typedef struct phy_rf_statistics_s { uint32_t crc_fails; ///< CRC failures uint32_t tx_timeouts; ///< transmission timeouts uint32_t rx_timeouts; ///< reception timeouts + uint64_t tx_active_time; ///< transmission active time + uint64_t rx_active_time; ///< reception active time + uint32_t tx_bytes; ///< transmitted bytes + uint32_t rx_bytes; ///< received bytes } phy_rf_statistics_s; /** Virtual data request */ diff --git a/nanostack/sw_mac.h b/nanostack/sw_mac.h index e4a018fc4e..894b8b75c4 100644 --- a/nanostack/sw_mac.h +++ b/nanostack/sw_mac.h @@ -67,6 +67,13 @@ extern int8_t ns_sw_mac_virtual_client_unregister(struct mac_api_s *api); */ extern int ns_sw_mac_fhss_register(struct mac_api_s *mac_api, struct fhss_api *fhss_api); +/** + * @brief Unregister FHSS API instance from given software MAC instance. + * @param mac_api MAC instance. + * @return 0 on success, -1 on fail. + */ +extern int ns_sw_mac_fhss_unregister(struct mac_api_s *mac_api); + /** * @brief Request registered FHSS API instance from software MAC instance. * @param mac_api MAC instance. diff --git a/nanostack/ws_bbr_api.h b/nanostack/ws_bbr_api.h index a4d4d460e8..1559f433d5 100644 --- a/nanostack/ws_bbr_api.h +++ b/nanostack/ws_bbr_api.h @@ -48,14 +48,10 @@ int ws_bbr_start(int8_t interface_id, int8_t backbone_interface_id); /** * Border router configuration options */ -#define BBR_ULA_C 0x0001 /**< Static ULA prefix created automatically */ -#define BBR_GUA_ROUTE 0x0002 /**< More specific route is added for GUA prefix */ -#define BBR_BB_WAIT 0x0004 /**< Wait backbone availability before starting Wi-SUN network */ - -/*Deprecated configuration values */ -#define BBR_GUA_C 0x0000 /**< Routable prefix is learned from the backbone */ -#define BBR_GUA_SLAAC 0x0000 /**< Use SLAAC addressing in routable prefix */ -#define BBR_GUA_WAIT 0x0000 /**< Wait backbone availability before startingRPL dodag */ +#define BBR_ULA_C 0x0001 /**< Static ULA prefix created automatically */ +#define BBR_GUA_ROUTE 0x0002 /**< More specific route is added for GUA prefix */ +#define BBR_BB_WAIT 0x0004 /**< Wait backbone availability before starting Wi-SUN network */ +#define BBR_DEFAULT_ROUTE 0x0008 /**< Add default route parameter to DIO */ /** * Configure border router features. diff --git a/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_bootstrap.c b/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_bootstrap.c index e78b91c088..cbe3e12c67 100644 --- a/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_bootstrap.c +++ b/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_bootstrap.c @@ -1379,6 +1379,8 @@ static int8_t arm_6lowpan_bootstrap_down(protocol_interface_info_entry_t *cur) } cur->if_lowpan_security_params->mle_security_frame_counter = mle_service_security_get_frame_counter(cur->id); mle_service_interface_receiver_handler_update(cur->id, mle_6lowpan_message_handler); + // Reset MAC for safe upper layer memory free + protocol_mac_reset(cur); return nwk_6lowpan_down(cur); } #ifdef HAVE_6LOWPAN_ND @@ -1593,7 +1595,7 @@ static void lowpan_neighbor_entry_remove_notify(mac_neighbor_table_entry_t *entr { protocol_interface_info_entry_t *cur_interface = user_data; - lowpan_adaptation_remove_free_indirect_table(cur_interface, entry_ptr); + lowpan_adaptation_neigh_remove_free_tx_tables(cur_interface, entry_ptr); // Sleepy host if (cur_interface->lowpan_info & INTERFACE_NWK_CONF_MAC_RX_OFF_IDLE) { mac_data_poll_protocol_poll_mode_decrement(cur_interface); diff --git a/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_interface.c b/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_interface.c index d3b0d16520..92ea3ce738 100644 --- a/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_interface.c +++ b/source/6LoWPAN/Bootstraps/Generic/protocol_6lowpan_interface.c @@ -72,6 +72,15 @@ #include "6LoWPAN/Fragmentation/cipv6_fragmenter.h" #include "libNET/src/net_load_balance_internal.h" +void protocol_mac_reset(protocol_interface_info_entry_t *cur) +{ + if (cur->mac_api) { + mlme_reset_t reset; + reset.SetDefaultPIB = true; + cur->mac_api->mlme_req(cur->mac_api, MLME_RESET, &reset); + } +} + static int8_t set_6lowpan_nwk_down(protocol_interface_info_entry_t *cur) @@ -96,15 +105,11 @@ static int8_t set_6lowpan_nwk_down(protocol_interface_info_entry_t *cur) } if (cur->interface_mode == INTERFACE_UP) { - if (cur->mac_api) { - mlme_reset_t reset; - reset.SetDefaultPIB = true; - cur->mac_parameters->pan_id = 0xffff; - cur->mac_parameters->SecurityEnabled = false; - cur->mac_parameters->security_frame_counter = 0; - cur->mac_parameters->mac_security_level = 0; - cur->mac_api->mlme_req(cur->mac_api, MLME_RESET, &reset); - } + cur->mac_parameters->pan_id = 0xffff; + cur->mac_parameters->SecurityEnabled = false; + cur->mac_parameters->security_frame_counter = 0; + cur->mac_parameters->mac_security_level = 0; + protocol_mac_reset(cur); cur->interface_mode = INTERFACE_IDLE; net_load_balance_internal_state_activate(cur, false); } diff --git a/source/6LoWPAN/Bootstraps/protocol_6lowpan_interface.h b/source/6LoWPAN/Bootstraps/protocol_6lowpan_interface.h index bd7875c514..017805735c 100644 --- a/source/6LoWPAN/Bootstraps/protocol_6lowpan_interface.h +++ b/source/6LoWPAN/Bootstraps/protocol_6lowpan_interface.h @@ -31,5 +31,7 @@ extern int8_t nwk_6lowpan_up(struct protocol_interface_info_entry *cur); */ extern int8_t nwk_6lowpan_down(struct protocol_interface_info_entry *cur); +extern void protocol_mac_reset(struct protocol_interface_info_entry *cur); + #endif /* PROTOCOL_6LOWPAN_INTERFACE_H_ */ diff --git a/source/6LoWPAN/MAC/mac_helper.c b/source/6LoWPAN/MAC/mac_helper.c index 1f7de87fc7..e33c7fe6f9 100644 --- a/source/6LoWPAN/MAC/mac_helper.c +++ b/source/6LoWPAN/MAC/mac_helper.c @@ -887,6 +887,7 @@ int8_t mac_helper_key_link_frame_counter_set(int8_t interface_id, uint32_t seq_p void mac_helper_devicetable_remove(mac_api_t *mac_api, uint8_t attribute_index, uint8_t *mac64) { + (void) mac64; if (!mac_api) { return; } diff --git a/source/6LoWPAN/MAC/mac_response_handler.c b/source/6LoWPAN/MAC/mac_response_handler.c index 1c89a92578..87d3003bbc 100644 --- a/source/6LoWPAN/MAC/mac_response_handler.c +++ b/source/6LoWPAN/MAC/mac_response_handler.c @@ -120,6 +120,7 @@ void mcps_data_indication_handler(const mac_api_t *api, const mcps_data_ind_t *d void mcps_purge_confirm_handler(const mac_api_t *api, mcps_purge_conf_t *data) { (void)api; + (void)data; tr_info("MCPS Data Purge confirm status %u, for handle %u", data->status, data->msduHandle); } diff --git a/source/6LoWPAN/ND/nd_router_object.c b/source/6LoWPAN/ND/nd_router_object.c index c397bfa66c..53ff5ac59f 100644 --- a/source/6LoWPAN/ND/nd_router_object.c +++ b/source/6LoWPAN/ND/nd_router_object.c @@ -856,9 +856,6 @@ static void nd_update_registration(protocol_interface_info_entry_t *cur_interfac mac_neighbor_table_entry_t *entry = mac_neighbor_table_address_discover(mac_neighbor_info(cur_interface), ipv6_neighbour_eui64(&cur_interface->ipv6_neighbour_cache, neigh), ADDR_802_15_4_LONG); if (entry) { - if (ws_info(cur_interface)) { - ws_common_etx_validate(cur_interface, entry); - } if (!entry->ffd_device) { rpl_control_publish_host_address(protocol_6lowpan_rpl_domain, neigh->ip_address, neigh->lifetime); @@ -931,11 +928,13 @@ bool nd_ns_aro_handler(protocol_interface_info_entry_t *cur_interface, const uin } /* TODO - check hard upper limit on registrations? */ - if (ws_info(cur_interface) && - !ws_common_allow_child_registration(cur_interface, aro_out->eui64)) { - aro_out->present = true; - aro_out->status = ARO_FULL; - return true; + if (ws_info(cur_interface)) { + + aro_out->status = ws_common_allow_child_registration(cur_interface, aro_out->eui64); + if (aro_out->status != ARO_SUCCESS) { + aro_out->present = true; + return true; + } } /* We need to have entry in the Neighbour Cache */ @@ -1757,6 +1756,8 @@ void nd_6lowpan_set_radv_params(protocol_interface_info_entry_t *cur_interface) cur_interface->adv_retrans_timer = nd_params.ra_retrans_timer; cur_interface->max_initial_rtr_adv_interval = nd_params.ra_interval_min; cur_interface->max_initial_rtr_advertisements = nd_params.ra_transmits; +#else + (void) cur_interface; #endif } #endif // HAVE_6LOWPAN_ND diff --git a/source/6LoWPAN/Thread/thread_bootstrap.c b/source/6LoWPAN/Thread/thread_bootstrap.c index 84d0609fb2..483932b578 100644 --- a/source/6LoWPAN/Thread/thread_bootstrap.c +++ b/source/6LoWPAN/Thread/thread_bootstrap.c @@ -137,7 +137,7 @@ static void thread_bootstrap_pbbr_update_done(struct protocol_interface_info_ent static void thread_neighbor_remove(mac_neighbor_table_entry_t *entry_ptr, void *user_data) { protocol_interface_info_entry_t *cur = user_data; - lowpan_adaptation_remove_free_indirect_table(cur, entry_ptr); + lowpan_adaptation_neigh_remove_free_tx_tables(cur, entry_ptr); thread_reset_neighbour_info(cur, entry_ptr); //Removes ETX neighbor diff --git a/source/6LoWPAN/Thread/thread_common.c b/source/6LoWPAN/Thread/thread_common.c index 7bbfb73961..bfea2ba7a9 100644 --- a/source/6LoWPAN/Thread/thread_common.c +++ b/source/6LoWPAN/Thread/thread_common.c @@ -240,6 +240,8 @@ int8_t thread_bootstrap_down(protocol_interface_info_entry_t *cur) tr_debug("SET thread Idle"); //stop polling mac_data_poll_disable(cur); + // Reset MAC for safe upper layer memory free + protocol_mac_reset(cur); //Clean mle table thread_neighbor_list_clean(cur); // store frame counters diff --git a/source/6LoWPAN/Thread/thread_management_if.c b/source/6LoWPAN/Thread/thread_management_if.c index 435ab51334..7409f53a90 100644 --- a/source/6LoWPAN/Thread/thread_management_if.c +++ b/source/6LoWPAN/Thread/thread_management_if.c @@ -699,7 +699,7 @@ int thread_dhcpv6_server_set_anonymous_addressing(int8_t interface_id, uint8_t * return -1; } - return DHCPv6_server_service_set_address_autonous_flag(interface_id, prefix_ptr, anonymous); + return DHCPv6_server_service_set_address_autonous_flag(interface_id, prefix_ptr, anonymous, false); #else (void) interface_id; (void) prefix_ptr; diff --git a/source/6LoWPAN/Thread/thread_mle_message_handler.c b/source/6LoWPAN/Thread/thread_mle_message_handler.c index a8253c5f8e..31e2f3416c 100644 --- a/source/6LoWPAN/Thread/thread_mle_message_handler.c +++ b/source/6LoWPAN/Thread/thread_mle_message_handler.c @@ -285,7 +285,7 @@ static void thread_update_mle_entry(protocol_interface_info_entry_t *cur, mle_me if (short_address != entry_temp->mac16) { if (thread_router_addr_from_addr(entry_temp->mac16) == cur->thread_info->routerShortAddress) { thread_dynamic_storage_child_info_clear(cur->id, entry_temp); - protocol_6lowpan_release_short_link_address_from_neighcache(cur, entry_temp->mac16); + } entry_temp->mac16 = short_address; /* throw MLME_GET request, short address is changed automatically in get request callback */ diff --git a/source/6LoWPAN/Thread/thread_network_synch.c b/source/6LoWPAN/Thread/thread_network_synch.c index 0ef70d38f1..1ffbdc8da9 100644 --- a/source/6LoWPAN/Thread/thread_network_synch.c +++ b/source/6LoWPAN/Thread/thread_network_synch.c @@ -64,6 +64,7 @@ #include "Common_Protocols/icmpv6_radv.h" #include "MLE/mle.h" #include "Service_Libs/mac_neighbor_table/mac_neighbor_table.h" +#include "6LoWPAN/lowpan_adaptation_interface.h" #include "6LoWPAN/MAC/mac_helper.h" #define TRACE_GROUP "tsyn" @@ -192,15 +193,29 @@ void thread_dynamic_storage_child_info_store(protocol_interface_info_entry_t *cu void thread_dynamic_storage_child_info_clear(int8_t interface_id, struct mac_neighbor_table_entry *child) { + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); + if (!cur) { + return; + } thread_sync_child_info_t *child_info = thread_dynamic_storage_child_info_find(interface_id, child); + if (child_info) { // Clear child information memset(child_info, 0, sizeof(thread_sync_child_info_t)); tr_debug("Dynamic storage: cleared child; mac16=%04x", child->mac16); - return; } - return; + uint8_t temp_address[2]; + common_write_16_bit(child->mac16, temp_address); + //Release Old short address entries + lowpan_adaptation_free_messages_from_queues_by_address(cur, temp_address, ADDR_802_15_4_SHORT); + /* As we are losing a link to a child address, we can assume that if we have an IP neighbour cache + * mapping to that address, it is no longer valid. We must have been their parent, and they must be + * finding a new parent, and hence a new 16-bit address. (Losing a link to a router address would not + * invalidate our IP->16-bit mapping.) + */ + protocol_6lowpan_release_short_link_address_from_neighcache(cur, child->mac16); + } static thread_sync_child_info_t *thread_dynamic_storage_child_info_find(int8_t interface_id, mac_neighbor_table_entry_t *child) diff --git a/source/6LoWPAN/Thread/thread_router_bootstrap.c b/source/6LoWPAN/Thread/thread_router_bootstrap.c index 1f17c7e569..81d5449447 100644 --- a/source/6LoWPAN/Thread/thread_router_bootstrap.c +++ b/source/6LoWPAN/Thread/thread_router_bootstrap.c @@ -969,13 +969,6 @@ int thread_router_bootstrap_reset_child_info(protocol_interface_info_entry_t *cu tr_debug("Child free %x", child->mac16); thread_dynamic_storage_child_info_clear(cur->id, child); - /* As we are losing a link to a child address, we can assume that if we have an IP neighbour cache - * mapping to that address, it is no longer valid. We must have been their parent, and they must be - * finding a new parent, and hence a new 16-bit address. (Losing a link to a router address would not - * invalidate our IP->16-bit mapping.) - */ - protocol_6lowpan_release_short_link_address_from_neighcache(cur, child->mac16); - // If Child's RLOC16 appears in the Network Data send the RLOC16 to the Leader if (thread_network_data_services_registered(&cur->thread_info->networkDataStorage, child->mac16)) { tr_debug("Remove references to Child's RLOC16 from the Network Data"); @@ -1824,7 +1817,6 @@ void thread_router_bootstrap_mle_receive_cb(int8_t interface_id, mle_message_t * // Was this previously our child? If yes, update. if ((entry_temp->mac16 & THREAD_CHILD_MASK) && thread_router_addr_from_addr(entry_temp->mac16) == cur->thread_info->routerShortAddress) { thread_dynamic_storage_child_info_clear(cur->id, entry_temp); - protocol_6lowpan_release_short_link_address_from_neighcache(cur, entry_temp->mac16); } update_mac_mib = true; entry_temp->mac16 = shortAddress; // short address refreshed diff --git a/source/6LoWPAN/Thread/thread_test_api.c b/source/6LoWPAN/Thread/thread_test_api.c index 26b7dd9250..bc137b1a9f 100644 --- a/source/6LoWPAN/Thread/thread_test_api.c +++ b/source/6LoWPAN/Thread/thread_test_api.c @@ -643,11 +643,10 @@ int thread_test_version_set(int8_t interface_id, uint8_t version) int thread_test_pbbr_response_override_set(int8_t interface_id, uint8_t dua_status, uint8_t dua_count, uint8_t ba_failure_count) { -#ifdef HAVE_THREAD +#if defined(HAVE_THREAD) && defined(HAVE_THREAD_V2) && defined(HAVE_THREAD_BORDER_ROUTER) (void)interface_id; thread_bbr_commercial_status_override_set(dua_status, dua_count, ba_failure_count); return 0; - #else (void)interface_id; (void)dua_status; diff --git a/source/6LoWPAN/adaptation_interface.c b/source/6LoWPAN/adaptation_interface.c index 0758ed4d12..99636719d9 100644 --- a/source/6LoWPAN/adaptation_interface.c +++ b/source/6LoWPAN/adaptation_interface.c @@ -89,8 +89,8 @@ typedef struct { fragmenter_tx_list_t indirect_tx_queue; uint8_t *fragment_indirect_tx_buffer; //Used for write fragmentation header uint16_t mtu_size; - fragmenter_tx_entry_t active_unicast_tx_buf; //Current active direct unicast tx process fragmenter_tx_entry_t active_broadcast_tx_buf; //Current active direct broadcast tx process + fragmenter_tx_list_t activeUnicastList; //Unicast packets waiting data confirmation from MAC buffer_list_t directTxQueue; //Waiting free tx process uint16_t directTxQueue_size; uint16_t indirect_big_packet_threshold; @@ -110,7 +110,7 @@ static fragmenter_interface_t *lowpan_adaptation_interface_discover(int8_t inter /* Interface direct message pending queue functions */ static void lowpan_adaptation_tx_queue_write(fragmenter_interface_t *interface_ptr, buffer_t *buf); -static buffer_t *lowpan_adaptation_tx_queue_read(fragmenter_interface_t *interface_ptr, protocol_interface_info_entry_t *cur); +static buffer_t *lowpan_adaptation_tx_queue_read(fragmenter_interface_t *interface_ptr); /* Data direction and message length validation */ static bool lowpan_adaptation_indirect_data_request(mac_neighbor_table_entry_t *mle_entry); @@ -126,7 +126,7 @@ static void lowpan_data_request_to_mac(protocol_interface_info_entry_t *cur, buf /* Tx confirmation local functions */ static bool lowpan_active_tx_handle_verify(uint8_t handle, buffer_t *buf); -static fragmenter_tx_entry_t *lowpan_indirect_tx_handle_verify(uint8_t handle, fragmenter_tx_list_t *indirect_tx_queue); +static fragmenter_tx_entry_t *lowpan_listed_tx_handle_verify(uint8_t handle, fragmenter_tx_list_t *indirect_tx_queue); static void lowpan_adaptation_data_process_clean(fragmenter_interface_t *interface_ptr, fragmenter_tx_entry_t *tx_ptr, uint8_t socket_event); static uint8_t map_mlme_status_to_socket_event(uint8_t mlme_status); static bool lowpan_adaptation_tx_process_ready(fragmenter_tx_entry_t *tx_ptr); @@ -138,6 +138,8 @@ static bool lowpan_adaptation_indirect_queue_free_message(struct protocol_interf static fragmenter_tx_entry_t *lowpan_adaptation_indirect_mac_data_request_active(fragmenter_interface_t *interface_ptr, fragmenter_tx_entry_t *tx_ptr); +static bool lowpan_buffer_tx_allowed(fragmenter_interface_t *interface_ptr, buffer_t *buf); + static void lowpan_adaptation_etx_update_cb(protocol_interface_info_entry_t *cur, buffer_t *buf, const mcps_data_conf_t *confirm) { switch (confirm->status) { @@ -221,18 +223,14 @@ static void lowpan_adaptation_tx_queue_write(fragmenter_interface_t *interface_p protocol_stats_update(STATS_AL_TX_QUEUE_SIZE, interface_ptr->directTxQueue_size); } -static buffer_t *lowpan_adaptation_tx_queue_read(fragmenter_interface_t *interface_ptr, protocol_interface_info_entry_t *cur) +static buffer_t *lowpan_adaptation_tx_queue_read(fragmenter_interface_t *interface_ptr) { - /* Currently this function is called only when data confirm is received for previously sent packet. - * Data confirm has freed the corresponding "active buffer" and this function will look for new buffer to be set as active buffer. - */ + // Currently this function is called only when data confirm is received for previously sent packet. + if (!interface_ptr->directTxQueue_size) { + return NULL; + } ns_list_foreach_safe(buffer_t, buf, &interface_ptr->directTxQueue) { - bool fragmented_needed = lowpan_adaptation_request_longer_than_mtu(cur, buf, interface_ptr); - //Check that we not trig second active fragmentation process - if (fragmented_needed && interface_ptr->fragmenter_active) { - tr_debug("Do not trig Second active fragmentation"); - } else if ((buf->link_specific.ieee802_15_4.requestAck && !interface_ptr->active_unicast_tx_buf.buf) - || (!buf->link_specific.ieee802_15_4.requestAck && !interface_ptr->active_broadcast_tx_buf.buf)) { + if (lowpan_buffer_tx_allowed(interface_ptr, buf)) { ns_list_remove(&interface_ptr->directTxQueue, buf); interface_ptr->directTxQueue_size--; protocol_stats_update(STATS_AL_TX_QUEUE_SIZE, interface_ptr->directTxQueue_size); @@ -292,7 +290,7 @@ static bool lowpan_active_tx_handle_verify(uint8_t handle, buffer_t *buf) -static fragmenter_tx_entry_t *lowpan_indirect_tx_handle_verify(uint8_t handle, fragmenter_tx_list_t *indirect_tx_queue) +static fragmenter_tx_entry_t *lowpan_listed_tx_handle_verify(uint8_t handle, fragmenter_tx_list_t *indirect_tx_queue) { ns_list_foreach(fragmenter_tx_entry_t, entry, indirect_tx_queue) { if (entry->buf->seq == handle) { @@ -310,9 +308,9 @@ static uint8_t lowpan_data_request_unique_handle_get(fragmenter_interface_t *int uint8_t handle; while (!valid_info) { handle = interface_ptr->msduHandle++; - if (!lowpan_active_tx_handle_verify(handle, interface_ptr->active_unicast_tx_buf.buf) + if (!lowpan_listed_tx_handle_verify(handle, &interface_ptr->activeUnicastList) && !lowpan_active_tx_handle_verify(handle, interface_ptr->active_broadcast_tx_buf.buf) - && !lowpan_indirect_tx_handle_verify(handle, &interface_ptr->indirect_tx_queue)) { + && !lowpan_listed_tx_handle_verify(handle, &interface_ptr->indirect_tx_queue)) { valid_info = true; } } @@ -320,7 +318,7 @@ static uint8_t lowpan_data_request_unique_handle_get(fragmenter_interface_t *int } -static void lowpan_indirect_entry_free(fragmenter_tx_list_t *list, fragmenter_tx_entry_t *entry) +static void lowpan_list_entry_free(fragmenter_tx_list_t *list, fragmenter_tx_entry_t *entry) { ns_list_remove(list, entry); if (entry->buf) { @@ -330,11 +328,15 @@ static void lowpan_indirect_entry_free(fragmenter_tx_list_t *list, fragmenter_tx ns_dyn_mem_free(entry); } -static void lowpan_indirect_queue_free(fragmenter_tx_list_t *list) +static void lowpan_list_free(fragmenter_tx_list_t *list, bool fragment_buf_free) { while (!ns_list_is_empty(list)) { fragmenter_tx_entry_t *entry = ns_list_get_first(list); - lowpan_indirect_entry_free(list, entry); + if (!fragment_buf_free) { + //We can't free this pointer becuase it must be until interface is deleted + entry->fragmenter_buf = NULL; + } + lowpan_list_entry_free(list, entry); } } @@ -365,6 +367,7 @@ int8_t lowpan_adaptation_interface_init(int8_t interface_id, uint16_t mac_mtu_si ns_list_init(&interface_ptr->indirect_tx_queue); ns_list_init(&interface_ptr->directTxQueue); + ns_list_init(&interface_ptr->activeUnicastList); ns_list_add_to_end(&fragmenter_interface_list, interface_ptr); @@ -389,11 +392,11 @@ int8_t lowpan_adaptation_interface_free(int8_t interface_id) ns_list_remove(&fragmenter_interface_list, interface_ptr); //free active tx process - lowpan_active_buffer_state_reset(&interface_ptr->active_unicast_tx_buf); + lowpan_list_free(&interface_ptr->activeUnicastList, false); lowpan_active_buffer_state_reset(&interface_ptr->active_broadcast_tx_buf); //Free Indirect entry - lowpan_indirect_queue_free(&interface_ptr->indirect_tx_queue); + lowpan_list_free(&interface_ptr->indirect_tx_queue, true); buffer_free_list(&interface_ptr->directTxQueue); @@ -414,13 +417,13 @@ int8_t lowpan_adaptation_interface_reset(int8_t interface_id) } //free active tx process - lowpan_active_buffer_state_reset(&interface_ptr->active_unicast_tx_buf); + lowpan_list_free(&interface_ptr->activeUnicastList, false); lowpan_active_buffer_state_reset(&interface_ptr->active_broadcast_tx_buf); //Clean fragmented message flag interface_ptr->fragmenter_active = false; //Free Indirect entry - lowpan_indirect_queue_free(&interface_ptr->indirect_tx_queue); + lowpan_list_free(&interface_ptr->indirect_tx_queue, true); buffer_free_list(&interface_ptr->directTxQueue); @@ -588,10 +591,15 @@ static bool lowpan_message_fragmentation_message_write(const fragmenter_tx_entry static fragmenter_tx_entry_t *lowpan_adaptation_tx_process_init(fragmenter_interface_t *interface_ptr, bool indirect, bool fragmented, bool is_unicast) { + // For broadcast, the active TX queue is only 1 entry. For unicast, using a list. fragmenter_tx_entry_t *tx_entry; if (!indirect) { if (is_unicast) { - tx_entry = &interface_ptr->active_unicast_tx_buf; + tx_entry = lowpan_indirect_entry_allocate(0); + if (!tx_entry) { + return NULL; + } + ns_list_add_to_end(&interface_ptr->activeUnicastList, tx_entry); } else { tx_entry = &interface_ptr->active_broadcast_tx_buf; } @@ -936,6 +944,40 @@ static void lowpan_data_request_to_mac(protocol_interface_info_entry_t *cur, buf } } +static bool lowpan_adaptation_is_destination_tx_active(fragmenter_tx_list_t *list, buffer_t *buf) +{ + ns_list_foreach(fragmenter_tx_entry_t, entry, list) { + if (entry->buf) { + if (!memcmp(&entry->buf->dst_sa.address[2], &buf->dst_sa.address[2], 8)) { + return true; + } + } + } + return false; +} + +static bool lowpan_buffer_tx_allowed(fragmenter_interface_t *interface_ptr, buffer_t *buf) +{ + bool is_unicast = buf->link_specific.ieee802_15_4.requestAck; + // Indirect allowed always + if (buf->link_specific.ieee802_15_4.indirectTxProcess) { + return true; + } + // Do not accept any other TX when fragmented TX active. Prevents other frames to be sent in between two fragments. + if (interface_ptr->fragmenter_active) { + return false; + } + // Do not accept more than one active broadcast TX + if (!is_unicast && interface_ptr->active_broadcast_tx_buf.buf) { + return false; + } + // Do not accept more than one active unicast TX per destination + if (is_unicast && lowpan_adaptation_is_destination_tx_active(&interface_ptr->activeUnicastList, buf)) { + return false; + } + return true; +} + int8_t lowpan_adaptation_interface_tx(protocol_interface_info_entry_t *cur, buffer_t *buf) { bool is_room_for_new_message; @@ -956,11 +998,10 @@ int8_t lowpan_adaptation_interface_tx(protocol_interface_info_entry_t *cur, buff bool fragmented_needed = lowpan_adaptation_request_longer_than_mtu(cur, buf, interface_ptr); bool is_unicast = buf->link_specific.ieee802_15_4.requestAck; bool indirect = buf->link_specific.ieee802_15_4.indirectTxProcess; - if (!indirect) { - if (((is_unicast && interface_ptr->active_unicast_tx_buf.buf) || (!is_unicast && interface_ptr->active_broadcast_tx_buf.buf)) || (fragmented_needed && interface_ptr->fragmenter_active)) { - lowpan_adaptation_tx_queue_write(interface_ptr, buf); - return 0; //Return here - } + + if (!lowpan_buffer_tx_allowed(interface_ptr, buf)) { + lowpan_adaptation_tx_queue_write(interface_ptr, buf); + return 0; } //Allocate Handle @@ -1107,10 +1148,14 @@ static bool lowpan_adaptation_tx_process_ready(fragmenter_tx_entry_t *tx_ptr) static void lowpan_adaptation_data_process_clean(fragmenter_interface_t *interface_ptr, fragmenter_tx_entry_t *tx_ptr, uint8_t socket_event) { buffer_t *buf = tx_ptr->buf; + tx_ptr->buf = NULL; if (buf->link_specific.ieee802_15_4.indirectTxProcess) { //release from list and free entry - lowpan_indirect_entry_free(&interface_ptr->indirect_tx_queue, tx_ptr); + lowpan_list_entry_free(&interface_ptr->indirect_tx_queue, tx_ptr); + } else if (buf->link_specific.ieee802_15_4.requestAck) { + ns_list_remove(&interface_ptr->activeUnicastList, tx_ptr); + ns_dyn_mem_free(tx_ptr); } socket_tx_buffer_event_and_free(buf, socket_event); @@ -1131,18 +1176,19 @@ int8_t lowpan_adaptation_interface_tx_confirm(protocol_interface_info_entry_t *c //Check first fragmenter_tx_entry_t *tx_ptr; bool active_direct_confirm; - bool is_unicast = true; - - if (lowpan_active_tx_handle_verify(confirm->msduHandle, interface_ptr->active_unicast_tx_buf.buf)) { - active_direct_confirm = true; - tx_ptr = &interface_ptr->active_unicast_tx_buf; - } else if (lowpan_active_tx_handle_verify(confirm->msduHandle, interface_ptr->active_broadcast_tx_buf.buf)) { + if (lowpan_active_tx_handle_verify(confirm->msduHandle, interface_ptr->active_broadcast_tx_buf.buf)) { active_direct_confirm = true; tx_ptr = &interface_ptr->active_broadcast_tx_buf; - is_unicast = false; } else { - active_direct_confirm = false; - tx_ptr = lowpan_indirect_tx_handle_verify(confirm->msduHandle, &interface_ptr->indirect_tx_queue); + tx_ptr = lowpan_listed_tx_handle_verify(confirm->msduHandle, &interface_ptr->activeUnicastList); + if (tx_ptr) { + active_direct_confirm = true; + } else { + tx_ptr = lowpan_listed_tx_handle_verify(confirm->msduHandle, &interface_ptr->indirect_tx_queue); + if (tx_ptr) { + active_direct_confirm = false; + } + } } if (!tx_ptr) { @@ -1214,7 +1260,7 @@ int8_t lowpan_adaptation_interface_tx_confirm(protocol_interface_info_entry_t *c } #ifdef HAVE_RPL - if (confirm->status == MLME_TX_NO_ACK) { + if (confirm->status == MLME_TX_NO_ACK || confirm->status == MLME_UNAVAILABLE_KEY) { if (buf->route && rpl_data_is_rpl_parent_route(buf->route->route_info.source)) { protocol_stats_update(STATS_RPL_PARENT_TX_FAIL, 1); } @@ -1232,14 +1278,15 @@ int8_t lowpan_adaptation_interface_tx_confirm(protocol_interface_info_entry_t *c break; } - - if ((is_unicast && !interface_ptr->active_unicast_tx_buf.buf) || (!is_unicast && !interface_ptr->active_broadcast_tx_buf.buf)) { - //Read Buffer and trig next direct request - lowpan_adaptation_interface_tx(cur, lowpan_adaptation_tx_queue_read(interface_ptr, cur)); + // When confirmation is for direct transmission, push all allowed buffers to MAC + if (active_direct_confirm == true) { + buffer_t *buf_from_queue = lowpan_adaptation_tx_queue_read(interface_ptr); + while (buf_from_queue) { + lowpan_adaptation_interface_tx(cur, buf_from_queue); + buf_from_queue = lowpan_adaptation_tx_queue_read(interface_ptr); + } } - return 0; - } static bool mac_data_is_broadcast_addr(const sockaddr_t *addr) @@ -1332,7 +1379,7 @@ bool lowpan_adaptation_tx_active(int8_t interface_id) { fragmenter_interface_t *interface_ptr = lowpan_adaptation_interface_discover(interface_id); - if (!interface_ptr || (!interface_ptr->active_unicast_tx_buf.buf && !interface_ptr->active_broadcast_tx_buf.buf)) { + if (!interface_ptr || (!ns_list_count(&interface_ptr->activeUnicastList) && !interface_ptr->active_broadcast_tx_buf.buf)) { return false; } return true; @@ -1399,19 +1446,19 @@ static bool lowpan_adaptation_indirect_queue_free_message(struct protocol_interf return true; } -void lowpan_adaptation_remove_free_indirect_table(protocol_interface_info_entry_t *cur_interface, mac_neighbor_table_entry_t *entry_ptr) +void lowpan_adaptation_neigh_remove_free_tx_tables(protocol_interface_info_entry_t *cur_interface, mac_neighbor_table_entry_t *entry_ptr) { //Free first by defined short address if (entry_ptr->mac16 < 0xfffe) { uint8_t temp_address[2]; common_write_16_bit(entry_ptr->mac16, temp_address); - lowpan_adaptation_indirect_free_messages_from_queues_by_address(cur_interface, temp_address, ADDR_802_15_4_SHORT); + lowpan_adaptation_free_messages_from_queues_by_address(cur_interface, temp_address, ADDR_802_15_4_SHORT); } - lowpan_adaptation_indirect_free_messages_from_queues_by_address(cur_interface, entry_ptr->mac64, ADDR_802_15_4_LONG); + lowpan_adaptation_free_messages_from_queues_by_address(cur_interface, entry_ptr->mac64, ADDR_802_15_4_LONG); } -int8_t lowpan_adaptation_indirect_free_messages_from_queues_by_address(struct protocol_interface_info_entry *cur, uint8_t *address_ptr, addrtype_t adr_type) +int8_t lowpan_adaptation_free_messages_from_queues_by_address(struct protocol_interface_info_entry *cur, uint8_t *address_ptr, addrtype_t adr_type) { fragmenter_interface_t *interface_ptr = lowpan_adaptation_interface_discover(cur->id); @@ -1427,9 +1474,18 @@ int8_t lowpan_adaptation_indirect_free_messages_from_queues_by_address(struct pr } } + //Check next direct queue + ns_list_foreach_safe(fragmenter_tx_entry_t, entry, &interface_ptr->activeUnicastList) { + if (lowpan_tx_buffer_address_compare(&entry->buf->dst_sa, address_ptr, adr_type)) { + //Purge from mac + lowpan_adaptation_indirect_queue_free_message(cur, interface_ptr, entry); + } + } + return 0; } + int8_t lowpan_adaptation_indirect_queue_params_set(struct protocol_interface_info_entry *cur, uint16_t indirect_big_packet_threshold, uint16_t max_indirect_big_packets_total, uint16_t max_indirect_small_packets_per_child) { fragmenter_interface_t *interface_ptr = lowpan_adaptation_interface_discover(cur->id); diff --git a/source/6LoWPAN/lowpan_adaptation_interface.h b/source/6LoWPAN/lowpan_adaptation_interface.h index 562e482034..307dd9917b 100644 --- a/source/6LoWPAN/lowpan_adaptation_interface.h +++ b/source/6LoWPAN/lowpan_adaptation_interface.h @@ -51,9 +51,9 @@ struct buffer *lowpan_adaptation_reassembly(struct protocol_interface_info_entry bool lowpan_adaptation_tx_active(int8_t interface_id); -void lowpan_adaptation_remove_free_indirect_table(struct protocol_interface_info_entry *cur_interface, struct mac_neighbor_table_entry *entry_ptr); +void lowpan_adaptation_neigh_remove_free_tx_tables(struct protocol_interface_info_entry *cur_interface, struct mac_neighbor_table_entry *entry_ptr); -int8_t lowpan_adaptation_indirect_free_messages_from_queues_by_address(struct protocol_interface_info_entry *cur, uint8_t *address_ptr, addrtype_t adr_type); +int8_t lowpan_adaptation_free_messages_from_queues_by_address(struct protocol_interface_info_entry *cur, uint8_t *address_ptr, addrtype_t adr_type); int8_t lowpan_adaptation_indirect_queue_params_set(struct protocol_interface_info_entry *cur, uint16_t indirect_big_packet_threshold, uint16_t max_indirect_big_packets_total, uint16_t max_indirect_small_packets_per_child); diff --git a/source/6LoWPAN/ws/ws_bbr_api.c b/source/6LoWPAN/ws/ws_bbr_api.c index 390de43932..7961f10cc9 100644 --- a/source/6LoWPAN/ws/ws_bbr_api.c +++ b/source/6LoWPAN/ws/ws_bbr_api.c @@ -45,10 +45,10 @@ #define RPL_INSTANCE_ID 1 -static uint8_t current_instance_id = RPL_INSTANCE_ID; - #ifdef HAVE_WS_BORDER_ROUTER +static uint8_t current_instance_id = RPL_INSTANCE_ID; + #define WS_ULA_LIFETIME 24*3600 #define WS_ROUTE_LIFETIME WS_ULA_LIFETIME #define WS_DHCP_ADDRESS_LIFETIME 2*3600 @@ -85,7 +85,27 @@ static rpl_dodag_conf_t rpl_conf = { .dio_redundancy_constant = WS_RPL_DIO_REDUNDANCY }; -void ws_bbr_rpl_config(uint8_t imin, uint8_t doubling, uint8_t redundancy, uint16_t dag_max_rank_increase, uint16_t min_hop_rank_increase) +static void ws_bbr_rpl_version_timer_start(protocol_interface_info_entry_t *cur, uint8_t version) +{ + // Set the next timeout value for version update + if (version < 128) { + //stable version for RPL so slow timer update is ok + cur->ws_info->rpl_version_timer = RPL_VERSION_LIFETIME; + } else { + cur->ws_info->rpl_version_timer = RPL_VERSION_LIFETIME_RESTART; + } +} + +static void ws_bbr_rpl_version_increase(protocol_interface_info_entry_t *cur) +{ + if (!protocol_6lowpan_rpl_root_dodag) { + return; + } + ws_bbr_rpl_version_timer_start(cur, rpl_control_increment_dodag_version(protocol_6lowpan_rpl_root_dodag)); +} + + +void ws_bbr_rpl_config(protocol_interface_info_entry_t *cur, uint8_t imin, uint8_t doubling, uint8_t redundancy, uint16_t dag_max_rank_increase, uint16_t min_hop_rank_increase) { if (imin == 0 || doubling == 0) { // use default values @@ -111,11 +131,11 @@ void ws_bbr_rpl_config(uint8_t imin, uint8_t doubling, uint8_t redundancy, uint1 if (protocol_6lowpan_rpl_root_dodag) { rpl_control_update_dodag_config(protocol_6lowpan_rpl_root_dodag, &rpl_conf); - rpl_control_increment_dodag_version(protocol_6lowpan_rpl_root_dodag); + ws_bbr_rpl_version_increase(cur); } } -static void ws_bbr_rpl_root_start(uint8_t *dodag_id) +static void ws_bbr_rpl_root_start(protocol_interface_info_entry_t *cur, uint8_t *dodag_id) { tr_info("RPL root start"); rpl_data_init_root(); @@ -123,7 +143,6 @@ static void ws_bbr_rpl_root_start(uint8_t *dodag_id) if (protocol_6lowpan_rpl_root_dodag) { rpl_control_delete_dodag_root(protocol_6lowpan_rpl_domain, protocol_6lowpan_rpl_root_dodag); protocol_6lowpan_rpl_root_dodag = NULL; - current_instance_id++; } protocol_6lowpan_rpl_root_dodag = rpl_control_create_dodag_root(protocol_6lowpan_rpl_domain, current_instance_id, dodag_id, &rpl_conf, rpl_conf.min_hop_rank_increase, RPL_GROUNDED | RPL_MODE_NON_STORING | RPL_DODAG_PREF(0)); @@ -133,19 +152,20 @@ static void ws_bbr_rpl_root_start(uint8_t *dodag_id) } // RPL memory limits set larger for Border router rpl_control_set_memory_limits(64 * 1024, 0); + + // Initial version number for RPL start is 240 from RPL RFC + ws_bbr_rpl_version_timer_start(cur, 240); + } + static void ws_bbr_rpl_root_stop(void) { tr_info("RPL root stop"); if (protocol_6lowpan_rpl_root_dodag) { rpl_control_delete_dodag_root(protocol_6lowpan_rpl_domain, protocol_6lowpan_rpl_root_dodag); protocol_6lowpan_rpl_root_dodag = NULL; - current_instance_id++; } - memset(current_local_prefix, 0, 8); - memset(current_global_prefix, 0, 8); - memset(current_dodag_id, 0, 16); } static int ws_border_router_proxy_validate(int8_t interface_id, uint8_t *address) @@ -177,11 +197,24 @@ int ws_border_router_proxy_state_update(int8_t caller_interface_id, int8_t handl static if_address_entry_t *ws_bbr_slaac_generate(protocol_interface_info_entry_t *cur, uint8_t *ula_prefix) { - if_address_entry_t *add_entry = icmpv6_slaac_address_add(cur, ula_prefix, 64, 0xffffffff, 0xffffffff, true, SLAAC_IID_FIXED); + if_address_entry_t *add_entry = NULL; + const uint8_t *address; + + address = addr_select_with_prefix(cur, ula_prefix, 64, 0); + if (address) { + // Address already exists for this prefix find the entry + add_entry = addr_get_entry(cur, address); + } + + if (!add_entry) { + add_entry = icmpv6_slaac_address_add(cur, ula_prefix, 64, 0xffffffff, 0xffffffff, true, SLAAC_IID_FIXED); + } if (!add_entry) { tr_err("ula create failed"); return NULL; } + // Set the timeouts for this address and policy + icmpv6_slaac_prefix_update(cur, ula_prefix, 64, 0xffffffff, 0xffffffff); addr_policy_table_add_entry(ula_prefix, 64, 2, WS_NON_PREFFRED_LABEL); return add_entry; } @@ -307,9 +340,11 @@ static void ws_bbr_dhcp_server_start(protocol_interface_info_entry_t *cur, uint8 return; } DHCPv6_server_service_callback_set(cur->id, global_id, NULL, wisun_dhcp_address_add_cb); - - DHCPv6_server_service_set_address_autonous_flag(cur->id, global_id, true); + //Enable SLAAC mode to border router + DHCPv6_server_service_set_address_autonous_flag(cur->id, global_id, true, false); DHCPv6_server_service_set_address_validlifetime(cur->id, global_id, WS_DHCP_ADDRESS_LIFETIME); + //SEt max value for not limiting address allocation + DHCPv6_server_service_set_max_clients_accepts_count(cur->id, global_id, MAX_SUPPORTED_ADDRESS_LIST_SIZE); ws_dhcp_client_address_request(cur, global_id, ll); } @@ -325,6 +360,31 @@ static void ws_bbr_dhcp_server_stop(protocol_interface_info_entry_t *cur, uint8_ } +static void ws_bbr_routing_stop(protocol_interface_info_entry_t *cur) +{ + tr_info("BBR routing stop"); + if (memcmp(current_local_prefix, ADDR_UNSPECIFIED, 8) != 0) { + ws_bbr_slaac_remove(cur, current_local_prefix); + memset(current_local_prefix, 0, 8); + } + + if (memcmp(current_global_prefix, ADDR_UNSPECIFIED, 8) != 0) { + ws_bbr_dhcp_server_stop(cur, current_global_prefix); + if (backbone_interface_id >= 0) { + // Delete route to backbone if it exists + ipv6_route_add_with_info(current_global_prefix, 64, backbone_interface_id, NULL, ROUTE_THREAD_BBR, NULL, 0, 0, 0); + } + memset(current_global_prefix, 0, 8); + } + + if (memcmp(current_dodag_id, ADDR_UNSPECIFIED, 8) != 0) { + ws_bbr_slaac_remove(cur, current_dodag_id); + memset(current_dodag_id, 0, 16); + } + + ws_bbr_rpl_root_stop(); +} + static void ws_bbr_rpl_status_check(protocol_interface_info_entry_t *cur) { @@ -339,7 +399,7 @@ static void ws_bbr_rpl_status_check(protocol_interface_info_entry_t *cur) if (!protocol_6lowpan_rpl_root_dodag) { // Generate DODAGID if (ws_bbr_static_dodagid_create(cur) == 0) { - ws_bbr_rpl_root_start(current_dodag_id); + ws_bbr_rpl_root_start(cur, current_dodag_id); } } @@ -354,9 +414,8 @@ static void ws_bbr_rpl_status_check(protocol_interface_info_entry_t *cur) */ if (protocol_interface_address_compare(current_dodag_id) != 0) { //DODAGID is lost need to restart - tr_warn("DODAGID lost restart RPL"); - memset(current_dodag_id, 0, 16); - ws_bbr_rpl_root_stop(); + tr_warn("DODAGID lost restart BBR"); + ws_bbr_routing_stop(cur); return; } @@ -366,7 +425,9 @@ static void ws_bbr_rpl_status_check(protocol_interface_info_entry_t *cur) /* * Add default route to RPL */ - rpl_control_update_dodag_route(protocol_6lowpan_rpl_root_dodag, NULL, 0, 0, WS_ROUTE_LIFETIME, false); + if (configuration & BBR_DEFAULT_ROUTE) { + rpl_control_update_dodag_route(protocol_6lowpan_rpl_root_dodag, NULL, 0, 0, WS_ROUTE_LIFETIME, false); + } /* * Create static ULA configuration or modify if needed @@ -384,6 +445,7 @@ static void ws_bbr_rpl_status_check(protocol_interface_info_entry_t *cur) if (memcmp(local_prefix, ADDR_UNSPECIFIED, 8) != 0) { if (!ws_bbr_slaac_generate(cur, local_prefix)) { + // Address creation failed return; } @@ -425,8 +487,9 @@ static void ws_bbr_rpl_status_check(protocol_interface_info_entry_t *cur) if (configuration & BBR_GUA_ROUTE) { rpl_control_update_dodag_route(protocol_6lowpan_rpl_root_dodag, current_global_prefix, 64, 0, 0, true); } - ipv6_route_add_with_info(current_global_prefix, 64, backbone_interface_id, NULL, ROUTE_THREAD_BBR, NULL, 0, 120, 0); - + if (backbone_interface_id >= 0) { + ipv6_route_add_with_info(current_global_prefix, 64, backbone_interface_id, NULL, ROUTE_THREAD_BBR, NULL, 0, 120, 0); + } ws_bbr_dhcp_server_stop(cur, current_global_prefix); } // TODO add global prefix @@ -435,9 +498,11 @@ static void ws_bbr_rpl_status_check(protocol_interface_info_entry_t *cur) tr_info("RPL global prefix activate %s", trace_ipv6_prefix(global_prefix, 64)); // Add default route to RPL // Enable default routing to backbone - if (ipv6_route_add_with_info(global_prefix, 64, backbone_interface_id, NULL, ROUTE_THREAD_BBR, NULL, 0, 0xffffffff, 0) == NULL) { - tr_err("global route add failed"); - return; + if (backbone_interface_id >= 0) { + if (ipv6_route_add_with_info(global_prefix, 64, backbone_interface_id, NULL, ROUTE_THREAD_BBR, NULL, 0, 0xffffffff, 0) == NULL) { + tr_err("global route add failed"); + return; + } } ws_bbr_dhcp_server_start(cur, global_prefix); rpl_control_update_dodag_prefix(protocol_6lowpan_rpl_root_dodag, global_prefix, 64, 0, 0, 0, false); @@ -450,7 +515,8 @@ static void ws_bbr_rpl_status_check(protocol_interface_info_entry_t *cur) } memcpy(current_global_prefix, global_prefix, 8); - rpl_control_increment_dodag_version(protocol_6lowpan_rpl_root_dodag); + ws_bbr_rpl_version_increase(cur); + nd_proxy_downstream_interface_register(cur->id, ws_border_router_proxy_validate, ws_border_router_proxy_state_update); } else if (memcmp(current_global_prefix, ADDR_UNSPECIFIED, 8) != 0) { /* @@ -511,7 +577,7 @@ void ws_bbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds if (cur->ws_info->pan_version_timer > seconds) { cur->ws_info->pan_version_timer -= seconds; } else { - // Border router has timed out + // PAN version number update tr_debug("Border router version number update"); cur->ws_info->pan_version_timer = ws_common_version_lifetime_get(cur->ws_info->network_size_config); cur->ws_info->pan_information.pan_version++; @@ -522,9 +588,13 @@ void ws_bbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds ws_common_network_size_configure(cur, cur->ws_info->pan_information.pan_size); } } - + if (cur->ws_info->rpl_version_timer > seconds) { + cur->ws_info->rpl_version_timer -= seconds; + } else { + // RPL version update needed + ws_bbr_rpl_version_increase(cur); + } } - } uint16_t test_pan_size_override = 0xffff; @@ -607,15 +677,11 @@ void ws_bbr_stop(int8_t interface_id) { #ifdef HAVE_WS_BORDER_ROUTER - (void)interface_id; + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); + + ws_bbr_routing_stop(cur); + backbone_interface_id = -1; - - if (!protocol_6lowpan_rpl_domain) { - return; - } - - rpl_control_delete_dodag_root(protocol_6lowpan_rpl_domain, protocol_6lowpan_rpl_root_dodag); - protocol_6lowpan_rpl_root_dodag = NULL; current_instance_id++; #else @@ -626,11 +692,12 @@ int ws_bbr_configure(int8_t interface_id, uint16_t options) { #ifdef HAVE_WS_BORDER_ROUTER - (void)interface_id; + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); + if (protocol_6lowpan_rpl_root_dodag && options != configuration) { //Configuration changed delete previous setup - ws_bbr_rpl_root_stop(); + ws_bbr_routing_stop(cur); } configuration = options; return 0; diff --git a/source/6LoWPAN/ws/ws_bbr_api_internal.h b/source/6LoWPAN/ws/ws_bbr_api_internal.h index 5da59eabcf..b07565a96c 100644 --- a/source/6LoWPAN/ws/ws_bbr_api_internal.h +++ b/source/6LoWPAN/ws/ws_bbr_api_internal.h @@ -27,7 +27,7 @@ void ws_bbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds uint16_t ws_bbr_pan_size(protocol_interface_info_entry_t *cur); -void ws_bbr_rpl_config(uint8_t imin, uint8_t doubling, uint8_t redundancy, uint16_t dag_max_rank_increase, uint16_t min_hop_rank_increase); +void ws_bbr_rpl_config(protocol_interface_info_entry_t *cur, uint8_t imin, uint8_t doubling, uint8_t redundancy, uint16_t dag_max_rank_increase, uint16_t min_hop_rank_increase); bool ws_bbr_ready_to_start(protocol_interface_info_entry_t *cur); @@ -36,7 +36,7 @@ bool ws_bbr_ready_to_start(protocol_interface_info_entry_t *cur); #define ws_bbr_seconds_timer( cur, seconds) #define ws_bbr_pan_size(cur) 0 -#define ws_bbr_rpl_config( imin, doubling, redundancy, dag_max_rank_increase, min_hop_rank_increase) +#define ws_bbr_rpl_config( cur, imin, doubling, redundancy, dag_max_rank_increase, min_hop_rank_increase) #define ws_bbr_ready_to_start(cur) true #endif //HAVE_WS_BORDER_ROUTER diff --git a/source/6LoWPAN/ws/ws_bootstrap.c b/source/6LoWPAN/ws/ws_bootstrap.c index f620e4d574..6aaffc1a8e 100644 --- a/source/6LoWPAN/ws/ws_bootstrap.c +++ b/source/6LoWPAN/ws/ws_bootstrap.c @@ -97,7 +97,6 @@ static void ws_bootstrap_pan_version_increment(protocol_interface_info_entry_t * static ws_nud_table_entry_t *ws_nud_entry_discover(protocol_interface_info_entry_t *cur, void *neighbor); static void ws_nud_entry_remove(protocol_interface_info_entry_t *cur, mac_neighbor_table_entry_t *entry_ptr); static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, void *user_data); -static bool ws_rpl_dio_new_parent_accept(struct protocol_interface_info_entry *interface); static void ws_bootstrap_candidate_table_reset(protocol_interface_info_entry_t *cur); @@ -202,7 +201,7 @@ static int ws_bootstrap_tasklet_init(protocol_interface_info_entry_t *cur) { if (cur->bootStrapId < 0) { cur->bootStrapId = eventOS_event_handler_create(&ws_bootstrap_event_handler, WS_INIT_EVENT); - tr_debug("WS tasklet init"); + tr_info("WS tasklet init"); } if (cur->bootStrapId < 0) { @@ -321,12 +320,16 @@ static void ws_nud_entry_remove(protocol_interface_info_entry_t *cur, mac_neighb } } -static bool ws_nud_message_build(protocol_interface_info_entry_t *cur, mac_neighbor_table_entry_t *neighbor) +static bool ws_nud_message_build(protocol_interface_info_entry_t *cur, mac_neighbor_table_entry_t *neighbor, bool nud_process) { //Send NS uint8_t ll_target[16]; ws_bootsrap_create_ll_address(ll_target, neighbor->mac64); - tr_info("NUD generate NS %u", neighbor->index); + if (nud_process) { + tr_info("NUD generate NS %u", neighbor->index); + } else { + tr_info("Probe generate NS %u", neighbor->index); + } buffer_t *buffer = icmpv6_build_ns(cur, ll_target, NULL, true, false, NULL); if (buffer) { protocol_push(buffer); @@ -368,7 +371,7 @@ void ws_nud_active_timer(protocol_interface_info_entry_t *cur, uint16_t ticks) } else { //Random TX wait period is over - entry->wait_response = ws_nud_message_build(cur, entry->neighbor_info); + entry->wait_response = ws_nud_message_build(cur, entry->neighbor_info, entry->nud_process); if (!entry->wait_response) { if (entry->nud_process && entry->retry_count < 2) { entry->timer = randLIB_get_random_in_range(1, 900); @@ -409,7 +412,8 @@ static void ws_bootstrap_llc_hopping_update(struct protocol_interface_info_entry memcpy(cur->ws_info->hopping_schdule.channel_mask, fhss_configuration->channel_mask, sizeof(uint32_t) * 8); cur->ws_info->hopping_schdule.uc_fixed_channel = fhss_configuration->unicast_fixed_channel; cur->ws_info->hopping_schdule.bc_fixed_channel = fhss_configuration->broadcast_fixed_channel; - cur->ws_info->hopping_schdule.uc_channel_function = fhss_configuration->ws_uc_channel_function; + // Read UC channel function from WS info because FHSS might be temporarily configured to fixed channel during discovery. + cur->ws_info->hopping_schdule.uc_channel_function = cur->ws_info->fhss_uc_channel_function; cur->ws_info->hopping_schdule.bc_channel_function = fhss_configuration->ws_bc_channel_function; cur->ws_info->hopping_schdule.fhss_bc_dwell_interval = fhss_configuration->fhss_bc_dwell_interval; cur->ws_info->hopping_schdule.fhss_broadcast_interval = fhss_configuration->fhss_broadcast_interval; @@ -420,8 +424,7 @@ static void ws_bootstrap_llc_hopping_update(struct protocol_interface_info_entry static int8_t ws_fhss_initialize(protocol_interface_info_entry_t *cur) { fhss_api_t *fhss_api = ns_sw_mac_get_fhss_api(cur->mac_api); - - if (!fhss_api || (fhss_api && cur->ws_info->fhss_owner)) { + if (!fhss_api) { // When FHSS doesn't exist yet, create one fhss_ws_configuration_t fhss_configuration; memset(&fhss_configuration, 0, sizeof(fhss_ws_configuration_t)); @@ -437,26 +440,11 @@ static int8_t ws_fhss_initialize(protocol_interface_info_entry_t *cur) fhss_configuration.ws_bc_channel_function = (fhss_ws_channel_functions)cur->ws_info->fhss_bc_channel_function; fhss_configuration.fhss_bc_dwell_interval = cur->ws_info->fhss_bc_dwell_interval; fhss_configuration.fhss_broadcast_interval = cur->ws_info->fhss_bc_interval; - + fhss_api = ns_fhss_ws_create(&fhss_configuration, cur->ws_info->fhss_timer_ptr); if (!fhss_api) { - fhss_api = ns_fhss_ws_create(&fhss_configuration, cur->ws_info->fhss_timer_ptr); - if (!fhss_api) { - tr_error("fhss create failed"); - return -1; - } - ns_sw_mac_fhss_register(cur->mac_api, fhss_api); - cur->ws_info->fhss_owner = true; - } else { - //Configuration set - ns_fhss_ws_configuration_set(cur->ws_info->fhss_api, &fhss_configuration); - - if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - ns_fhss_ws_set_hop_count(cur->ws_info->fhss_api, 0); - } else { - //Clear OWN HOP - ns_fhss_ws_set_hop_count(cur->ws_info->fhss_api, 0xff); - } + return -1; } + ns_sw_mac_fhss_register(cur->mac_api, fhss_api); } else { // Read defaults from the configuration to help FHSS testing const fhss_ws_configuration_t *fhss_configuration = ns_fhss_ws_configuration_get(fhss_api); @@ -519,7 +507,7 @@ static uint16_t ws_randomize_fixed_channel(uint16_t configured_fixed_channel, ui } } -static int8_t ws_fhss_discovery_configure(protocol_interface_info_entry_t *cur) +static int8_t ws_fhss_configure(protocol_interface_info_entry_t *cur, bool discovery) { // Read configuration of existing FHSS and start using the default values for any network fhss_ws_configuration_t fhss_configuration; @@ -528,8 +516,12 @@ static int8_t ws_fhss_discovery_configure(protocol_interface_info_entry_t *cur) if (ns_fhss_ws_configuration_get(cur->ws_info->fhss_api)) { memcpy(&fhss_configuration, ns_fhss_ws_configuration_get(cur->ws_info->fhss_api), sizeof(fhss_ws_configuration_t)); } - - fhss_configuration.ws_uc_channel_function = WS_FIXED_CHANNEL; + // Discovery is done using fixed channel + if (discovery) { + fhss_configuration.ws_uc_channel_function = WS_FIXED_CHANNEL; + } else { + fhss_configuration.ws_uc_channel_function = (fhss_ws_channel_functions)cur->ws_info->fhss_uc_channel_function; + } fhss_configuration.ws_bc_channel_function = WS_FIXED_CHANNEL; fhss_configuration.fhss_broadcast_interval = 0; uint8_t tmp_uc_fixed_channel = ws_randomize_fixed_channel(cur->ws_info->fhss_uc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels); @@ -641,8 +633,9 @@ static void ws_bootstrap_ll_address_validate(struct protocol_interface_info_entr mac64[0] |= 2; //Set Local Bit mac64[0] &= ~1; //Clear multicast bit - tr_info("Generated random MAC %s", trace_array(mac64, 8)); + tr_info("Generated random MAC address"); } + tr_info("MAC address: %s", trace_array(mac64, 8)); mac_helper_mac64_set(cur, mac64); memcpy(cur->iid_eui64, mac64, 8); @@ -660,7 +653,6 @@ static void ws_bootstrap_ll_address_validate(struct protocol_interface_info_entr uint16_t ws_etx_read(protocol_interface_info_entry_t *interface, addrtype_t addr_type, const uint8_t *addr_ptr) { - uint16_t etx; if (!addr_ptr || !interface) { return 0; } @@ -675,42 +667,11 @@ uint16_t ws_etx_read(protocol_interface_info_entry_t *interface, addrtype_t addr ws_neighbor_class_entry_t *ws_neighbour = ws_neighbor_class_entry_get(&interface->ws_info->neighbor_storage, attribute_index); etx_storage_t *etx_entry = etx_storage_entry_get(interface->id, attribute_index); - if (interface->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - if (!ws_neighbour || !etx_entry) { - return 0xffff; - } - } else { - - if (!ws_neighbour || !etx_entry || etx_entry->etx_samples < 1 /*|| - !ws_neighbour->candidate_parent*/) { - // if RSL value is not good enough candidate parent flag is removed and device not accepted as parent - //tr_debug("ws_etx_read not valid params"); - return 0xffff; - } - - //If we are not following gbobal Broadcast synch - if (!interface->ws_info->pan_information.use_parent_bs) { - //We must know both information's here - if (!ws_neighbour->broadcast_shedule_info_stored || - !ws_neighbour->broadcast_timing_info_stored) { - return 0xffff; - } - } else { - if (!ws_neighbour->broadcast_timing_info_stored) { - //Global shedule is stored already - tr_debug("ws_etx_read not valid NO BTI"); - return 0xffff; - } - } - } - - etx = etx_local_etx_read(interface->id, attribute_index); - if (etx == 0) { + if (!ws_neighbour || !etx_entry) { return 0xffff; } - //tr_debug("ws_etx_read etx:%d", etx); - return etx; + return etx_local_etx_read(interface->id, attribute_index); } bool ws_bootstrap_nd_ns_transmit(protocol_interface_info_entry_t *cur, ipv6_neighbour_t *entry, bool unicast, uint8_t seq) { @@ -759,6 +720,8 @@ static int8_t ws_bootstrap_up(protocol_interface_info_entry_t *cur) goto cleanup; } + /* Wi-sun will trig event for stamechine this timer must be zero on init */ + cur->bootsrap_state_machine_cnt = 0; /* Disable SLLAO send/mandatory receive with the ARO */ cur->ipv6_neighbour_cache.use_eui64_as_slla_in_aro = true; /* Omit sending of NA if ARO SUCCESS */ @@ -803,8 +766,12 @@ static int8_t ws_bootstrap_down(protocol_interface_info_entry_t *cur) return -1; } - tr_debug("Wi-SUN ifdown"); - + tr_info("Wi-SUN ifdown"); + // Reset MAC for safe upper layer memory free + protocol_mac_reset(cur); + ns_sw_mac_fhss_unregister(cur->mac_api); + ns_fhss_delete(cur->ws_info->fhss_api); + cur->ws_info->fhss_api = NULL; // Reset WS information // ws_common_reset(cur) ws_llc_reset(cur); @@ -862,19 +829,26 @@ void ws_bootstrap_configuration_reset(protocol_interface_info_entry_t *cur) static bool ws_bootstrap_network_name_matches(const struct mcps_data_ie_list *ie_ext, const char *network_name_ptr) { + ws_wp_network_name_t network_name; + if (!network_name_ptr || !ie_ext) { return false; } - ws_wp_network_name_t network_name; if (!ws_wp_nested_network_name_read(ie_ext->payloadIeList, ie_ext->payloadIeListLength, &network_name)) { tr_warn("No network name IE"); return false; } - if (network_name_ptr == NULL || strncmp(network_name_ptr, (char *)network_name.network_name, network_name.network_name_length) != 0) { + if (network_name.network_name_length != strlen(network_name_ptr)) { return false; } + + if (strncmp(network_name_ptr, (char *)network_name.network_name, network_name.network_name_length) != 0) { + return false; + } + + // names have equal length and same characters return true; } @@ -894,10 +868,15 @@ static void ws_bootstrap_pan_advertisement_analyse_active(struct protocol_interf * that of the receiving node, and PAN-IE / Routing Cost better than (smaller than) that of the receiving node. * */ - + if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + //Border router never set consistent that will guarantee that BR will send advertisment + return; + } #ifdef WISUN_1_0_ERRATA_FIX - // All messages are considered as consistent only Solicit will cause inconsistent - trickle_consistent_heard(&cur->ws_info->trickle_pan_advertisement); + if (pan_information->pan_size == cur->ws_info->pan_information.pan_size) { + //If same pan size information then set consistent value + trickle_consistent_heard(&cur->ws_info->trickle_pan_advertisement); + } #else // Wi-SUN 1.0 specified functionality, causes extra inconsistencies when we hear higher rank advertisements if (pan_information->routing_cost >= ws_bootstrap_routing_cost_calculate(cur)) { @@ -1189,7 +1168,7 @@ static void ws_bootstrap_pan_advertisement_solicit_analyse(struct protocol_inter if (ws_bootstrap_state_discovery(cur) && cur->bootsrap_state_machine_cnt > cur->ws_info->trickle_params_pan_discovery.Imin + 50) { cur->bootsrap_state_machine_cnt = cur->ws_info->trickle_params_pan_discovery.Imin + randLIB_get_8bit() % 50; - tr_info("Making parent selection in %d s", (uint32_t)(cur->bootsrap_state_machine_cnt / 10)); + tr_info("Making parent selection in %u s", (cur->bootsrap_state_machine_cnt / 10)); } } @@ -1460,8 +1439,13 @@ static void ws_bootstrap_asynch_ind(struct protocol_interface_info_entry *cur, c static void ws_bootstrap_asynch_confirm(struct protocol_interface_info_entry *interface, uint8_t asynch_message) { ws_stats_update(interface, STATS_WS_ASYNCH_TX, 1); - (void)interface; - (void)asynch_message; + if (interface->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + if (asynch_message == WS_FT_PAN_CONF && interface->ws_info->pending_key_index_info.state == PENDING_KEY_INDEX_ACTIVATE) { + interface->ws_info->pending_key_index_info.state = NO_PENDING_PROCESS; + tr_info("Activate new default key %u", interface->ws_info->pending_key_index_info.index + 1); + mac_helper_security_auto_request_key_index_set(interface, interface->ws_info->pending_key_index_info.index, interface->ws_info->pending_key_index_info.index + 1); + } + } } uint32_t ws_time_from_last_unicast_traffic(uint32_t current_time_stamp, ws_neighbor_class_entry_t *ws_neighbor) @@ -1495,7 +1479,7 @@ static void ws_bootstrap_neighbor_table_clean(struct protocol_interface_info_ent continue; } - if (cur->nud_active || ws_neighbor->accelerated_etx_probe || ws_neighbor->negative_aro_send) { + if (cur->nud_active || ws_neighbor->negative_aro_send) { //If NUD process is active do not trig continue; } @@ -1589,30 +1573,11 @@ static bool ws_bootstrap_neighbor_info_request(struct protocol_interface_info_en return true; } -static bool ws_rpl_dio_new_parent_accept(struct protocol_interface_info_entry *interface) -{ - uint16_t parent_candidate_size = rpl_control_parent_candidate_list_size(interface, false); - //TODO check bootstarap state for review - //if we have enough candidates at list do not accept new multicast neighbours - if (parent_candidate_size > interface->ws_info->rpl_parent_candidate_max) { - return false; - } - - parent_candidate_size = rpl_control_parent_candidate_list_size(interface, true); - //If we have already enough parent selected Candidates count is bigger than configured - if (parent_candidate_size >= interface->ws_info->rpl_selected_parent_max) { - return false; - } - - return true; -} - - static void ws_neighbor_entry_remove_notify(mac_neighbor_table_entry_t *entry_ptr, void *user_data) { protocol_interface_info_entry_t *cur = user_data; - lowpan_adaptation_remove_free_indirect_table(cur, entry_ptr); + lowpan_adaptation_neigh_remove_free_tx_tables(cur, entry_ptr); // Sleepy host if (cur->lowpan_info & INTERFACE_NWK_CONF_MAC_RX_OFF_IDLE) { mac_data_poll_protocol_poll_mode_decrement(cur); @@ -1634,6 +1599,8 @@ static void ws_neighbor_entry_remove_notify(mac_neighbor_table_entry_t *entry_pt static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, void *user_data) { uint32_t time_from_start = entry_ptr->link_lifetime - entry_ptr->lifetime; + uint8_t ll_address[16]; + bool nud_proces = false; bool activate_nud = false; protocol_interface_info_entry_t *cur = user_data; @@ -1644,17 +1611,22 @@ static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, return false; } - uint8_t ll_address[16]; + ws_bootsrap_create_ll_address(ll_address, entry_ptr->mac64); if (time_from_start > WS_NEIGHBOR_NUD_TIMEOUT) { - ws_bootsrap_create_ll_address(ll_address, entry_ptr->mac64); + if (ipv6_neighbour_has_registered_by_eui64(&cur->ipv6_neighbour_cache, entry_ptr->mac64)) { + // This is our child with valid ARO registration Change link timeout to future we check at 2 minute intervals + entry_ptr->lifetime = entry_ptr->lifetime + 120; + if (entry_ptr->lifetime > entry_ptr->link_lifetime) { + entry_ptr->lifetime = entry_ptr->link_lifetime; + } + return false; + } if (!rpl_control_is_dodag_parent_candidate(cur, ll_address, WS_NEIGHBOUR_MAX_CANDIDATE_PROBE)) { - if (!ipv6_neighbour_has_registered_by_eui64(&cur->ipv6_neighbour_cache, entry_ptr->mac64)) { - //NUD Not needed for if neighbour is not child or parent candidate - return false; - } + //NUD Not needed for if neighbour is not parent candidate + return false; } if (time_from_start > WS_NEIGHBOR_NUD_TIMEOUT * 1.5) { @@ -1666,33 +1638,29 @@ static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, activate_nud = true; } } - } else if (etx_entry->etx_samples < WS_NEIGBOR_ETX_SAMPLE_MAX) { + nud_proces = activate_nud; + } else if (etx_entry->etx_samples < WS_NEIGHBOR_ETX_SAMPLE_MAX) { //Take Random number for trig a prope. //ETX Sample 0: random 1-8 //ETX Sample 1: random 2-16 //ETX Sample 2: random 4-32 - if (etx_entry->etx_samples == 0 && ws_neighbor->accelerated_etx_probe) { - //Accept quick Probe for init ETX + ws_bootsrap_create_ll_address(ll_address, entry_ptr->mac64); + if (!rpl_control_probe_parent_candidate(cur, ll_address)) { + return false; + } + + + uint32_t probe_period = WS_PROBE_INIT_BASE_SECONDS << etx_entry->etx_samples; + uint32_t time_block = 1 << etx_entry->etx_samples; + if (time_from_start >= probe_period) { + //tr_debug("Link Probe test %u Sample trig", etx_entry->etx_samples); activate_nud = true; - } else { - - ws_bootsrap_create_ll_address(ll_address, entry_ptr->mac64); - if (!rpl_control_is_dodag_parent_candidate(cur, ll_address, WS_NEIGHBOUR_MAX_CANDIDATE_PROBE)) { - return false; - } - - uint32_t probe_period = WS_PROBE_INIT_BASE_SECONDS << etx_entry->etx_samples; - uint32_t time_block = 1 << etx_entry->etx_samples; - if (time_from_start >= probe_period) { - //tr_debug("Link Probe test %u Sample trig", etx_entry->etx_samples); + } else if (time_from_start > time_block) { + uint16_t switch_prob = randLIB_get_random_in_range(0, probe_period - 1); + //Take Random from time WS_NEIGHBOR_NUD_TIMEOUT - WS_NEIGHBOR_NUD_TIMEOUT*1.5 + if (switch_prob < 2) { + //tr_debug("Link Probe test with jitter %"PRIu32", sample %u", time_from_start, etx_entry->etx_samples); activate_nud = true; - } else if (time_from_start > time_block) { - uint16_t switch_prob = randLIB_get_random_in_range(0, probe_period - 1); - //Take Random from time WS_NEIGHBOR_NUD_TIMEOUT - WS_NEIGHBOR_NUD_TIMEOUT*1.5 - if (switch_prob < 2) { - //tr_debug("Link Probe test with jitter %"PRIu32", sample %u", time_from_start, etx_entry->etx_samples); - activate_nud = true; - } } } } @@ -1706,14 +1674,9 @@ static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, return false; } entry->neighbor_info = entry_ptr; - if (ws_neighbor->accelerated_etx_probe) { - ws_neighbor->accelerated_etx_probe = false; - entry->timer = 1; - } - if (etx_entry->etx_samples >= WS_NEIGBOR_ETX_SAMPLE_MAX) { - entry->nud_process = true; - } + entry->nud_process = nud_proces; + return true; } @@ -1746,12 +1709,13 @@ int ws_bootstrap_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode) if (!etx_storage_list_allocate(cur->id, buffer.device_decription_table_size)) { return -1; } - if (!etx_cached_etx_parameter_set(WS_ETX_MIN_WAIT_TIME, WS_ETX_MIN_SAMPLE_COUNT)) { + if (!etx_cached_etx_parameter_set(WS_ETX_MIN_WAIT_TIME, WS_ETX_MIN_SAMPLE_COUNT, WS_NEIGHBOR_FIRST_ETX_SAMPLE_MIN_COUNT)) { etx_storage_list_allocate(cur->id, 0); return -1; } etx_max_update_set(WS_ETX_MAX_UPDATE); + etx_max_set(WS_ETX_MAX); if (blacklist_init() != 0) { tr_err("MLE blacklist init failed."); @@ -2148,7 +2112,22 @@ static void ws_rpl_prefix_callback(prefix_entry_t *prefix, void *handle, uint8_t } } -static bool ws_rpl_new_parent_callback_t(uint8_t *ll_parent_address, void *handle) +static bool ws_rpl_candidate_soft_filtering(protocol_interface_info_entry_t *cur, struct rpl_instance *instance) +{ + //Already many candidates + if (rpl_control_candidate_list_size(cur, instance) > cur->ws_info->rpl_parent_candidate_max) { + return false; + } + + //Already enough selected candidates + if (rpl_control_selected_parent_count(cur, instance) >= cur->ws_info->rpl_selected_parent_max) { + return false; + } + + return true; +} + +static bool ws_rpl_new_parent_callback(uint8_t *ll_parent_address, void *handle, struct rpl_instance *instance, uint16_t candidate_rank) { protocol_interface_info_entry_t *cur = handle; @@ -2156,26 +2135,102 @@ static bool ws_rpl_new_parent_callback_t(uint8_t *ll_parent_address, void *handl return false; } - uint8_t mac64[8]; + if (blacklist_reject(ll_parent_address)) { + // Rejected by blacklist + return false; + } + + uint8_t mac64[10]; + //bool replace_ok = false; + //bool create_ok = false; + llc_neighbour_req_t neigh_buffer; + + //Discover neigh ready here for possible ETX validate memcpy(mac64, ll_parent_address + 8, 8); mac64[0] ^= 2; - llc_neighbour_req_t neigh_buffer; - if (ws_bootstrap_neighbor_info_request(cur, mac64, &neigh_buffer, false)) { + + + ws_bootstrap_neighbor_info_request(cur, mac64, &neigh_buffer, false); + //Discover Multicast temporary entry for create neighbour table entry for new candidate + ws_neighbor_temp_class_t *entry = ws_llc_get_multicast_temp_entry(cur, mac64); + + if (!ws_rpl_candidate_soft_filtering(cur, instance)) { + if (!neigh_buffer.neighbor) { + //Do not accept any new in that Place + return false; + } + + uint8_t replacing[16]; + //Accept Know neighbour if it is enough good + if (!rpl_control_find_worst_neighbor(cur, instance, replacing)) { + return false; + } + // +2 Is for PAN ID space + memcpy(mac64 + 2, replacing + 8, 8); + mac64[2] ^= 2; + + if (ws_etx_read(cur, ADDR_802_15_4_LONG, mac64) == 0xffff) { + //Not proped yet because ETX is 0xffff + return false; + } + + uint16_t etx = 0; + if (neigh_buffer.neighbor) { + etx = etx_local_etx_read(cur->id, neigh_buffer.neighbor->index); + } + + // Accept now only better one's when max candidates selected and max candidate list size is reached + return rpl_possible_better_candidate(cur, instance, replacing, candidate_rank, etx); + } + + //Neighbour allready + if (neigh_buffer.neighbor) { return true; } - - if (!ws_rpl_dio_new_parent_accept(cur)) { +#if 0 + if (!rpl_control_find_worst_neighbor(cur, instance, replacing)) { return false; } - //Discover Multicast temporary entry + // +2 Is for PAN ID space + memcpy(mac64 + 2, replacing + 8, 8); + mac64[2] ^= 2; + + if (ws_etx_read(cur, ADDR_802_15_4_LONG, mac64) == 0xffff) { + //Not proped yet because ETX is 0xffff + return false; + } + + uint16_t etx = 0; + if (neigh_buffer.neighbor) { + etx = etx_local_etx_read(cur->id, neigh_buffer.neighbor->index); + } + + // Accept now only better one's when max candidates selected and max candidate list size is reached + if (!rpl_possible_better_candidate(cur, instance, replacing, candidate_rank, etx)) { + return false; + } + //TODO if replacing has poor ETX, put it in blacklist as "poor ETX" to prevent reselection + //Mark That We can try remove replaced link + replace_ok = true; + +neigh_create: + + + if (neigh_buffer.neighbor) { + //Use Already discovered entry + create_ok = true; + goto neigh_create_ok; + } +#endif - ws_neighbor_temp_class_t *entry = ws_llc_get_multicast_temp_entry(cur, mac64); if (!entry) { + //No Multicast Entry Available return false; } + //Create entry - bool create_ok = ws_bootstrap_neighbor_info_request(cur, mac64, &neigh_buffer, true); + bool create_ok = ws_bootstrap_neighbor_info_request(cur, entry->mac64, &neigh_buffer, true); if (create_ok) { ws_neighbor_class_entry_t *ws_neigh = neigh_buffer.ws_neighbor; //Copy fhss temporary data @@ -2186,7 +2241,15 @@ static bool ws_rpl_new_parent_callback_t(uint8_t *ll_parent_address, void *handl } ws_llc_free_multicast_temp_entry(cur, entry); +#if 0 +neigh_create_ok: + if (create_ok && replace_ok) { + //Try remove here when accepted new better one possible + tr_debug("Remove %s by %s", trace_ipv6(replacing), trace_ipv6(ll_parent_address)); + rpl_control_neighbor_delete_from_instance(cur, instance, replacing); + } +#endif return create_ok; } @@ -2198,13 +2261,18 @@ static void ws_bootstrap_rpl_activate(protocol_interface_info_entry_t *cur) addr_add_router_groups(cur); rpl_control_set_domain_on_interface(cur, protocol_6lowpan_rpl_domain, downstream); - rpl_control_set_callback(protocol_6lowpan_rpl_domain, ws_bootstrap_rpl_callback, ws_rpl_prefix_callback, ws_rpl_new_parent_callback_t, cur); + rpl_control_set_callback(protocol_6lowpan_rpl_domain, ws_bootstrap_rpl_callback, ws_rpl_prefix_callback, ws_rpl_new_parent_callback, cur); // If i am router I Do this rpl_control_force_leaf(protocol_6lowpan_rpl_domain, leaf); + rpl_control_process_routes(protocol_6lowpan_rpl_domain, false); // Wi-SUN assumes that no default route needed rpl_control_request_parent_link_confirmation(true); rpl_control_set_dio_multicast_min_config_advertisment_count(WS_MIN_DIO_MULTICAST_CONFIG_ADVERTISMENT_COUNT); rpl_control_set_dao_retry_count(WS_MAX_DAO_RETRIES); rpl_control_set_initial_dao_ack_wait(WS_MAX_DAO_INITIAL_TIMEOUT); + rpl_control_set_mrhof_parent_set_size(WS_MAX_PARENT_SET_COUNT); + if (cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + rpl_control_set_memory_limits(WS_NODE_RPL_SOFT_MEM_LIMIT, WS_NODE_RPL_HARD_MEM_LIMIT); + } cur->ws_info->rpl_state = 0xff; // Set invalid state and learn from event } @@ -2222,7 +2290,7 @@ static void ws_bootstrap_network_discovery_configure(protocol_interface_info_ent cur->ws_info->network_pan_id = 0xffff; ws_common_regulatory_domain_config(cur); - ws_fhss_discovery_configure(cur); + ws_fhss_configure(cur, true); //Set Network names, Pan information configure, hopping schedule & GTKHash ws_llc_set_network_name(cur, (uint8_t *)cur->ws_info->network_name, strlen(cur->ws_info->network_name)); @@ -2294,7 +2362,7 @@ static void ws_bootstrap_start_discovery(protocol_interface_info_entry_t *cur) cur->ws_info->trickle_pan_advertisement_solicit.I, cur->ws_info->trickle_pan_advertisement_solicit.t, cur->ws_info->trickle_pan_advertisement_solicit.now, cur->ws_info->trickle_pan_advertisement_solicit.c); cur->bootsrap_state_machine_cnt = time_to_solicit + cur->ws_info->trickle_params_pan_discovery.Imin + randLIB_get_8bit() % 50; - tr_info("Making parent selection in %d s", (uint32_t)(cur->bootsrap_state_machine_cnt / 10)); + tr_info("Making parent selection in %u s", (cur->bootsrap_state_machine_cnt / 10)); } // Start authentication @@ -2324,7 +2392,16 @@ static void ws_bootstrap_nw_key_clear(protocol_interface_info_entry_t *cur, uint static void ws_bootstrap_nw_key_index_set(protocol_interface_info_entry_t *cur, uint8_t index) { - // Set send key + + if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { + if (cur->mac_parameters->mac_default_key_index != 0 && cur->mac_parameters->mac_default_key_index != index + 1) { + tr_info("New Pending key Request %u", index + 1); + cur->ws_info->pending_key_index_info.state = PENDING_KEY_INDEX_ADVERTISMENT; + cur->ws_info->pending_key_index_info.index = index; + return; + } + } + mac_helper_security_auto_request_key_index_set(cur, index, index + 1); } @@ -2355,7 +2432,7 @@ static void ws_bootstrap_authentication_completed(protocol_interface_info_entry_ // Go back for network scanning ws_bootstrap_state_change(cur, ER_ACTIVE_SCAN); cur->bootsrap_state_machine_cnt = randLIB_get_random_in_range(10, cur->ws_info->trickle_params_pan_discovery.Imin >> 1); - tr_info("Making parent selection in %d s", (uint32_t)(cur->bootsrap_state_machine_cnt / 10)); + tr_info("Making parent selection in %u s", (cur->bootsrap_state_machine_cnt / 10)); } else { tr_debug("authentication failed"); // What else to do to start over again... @@ -2377,6 +2454,8 @@ static void ws_bootstrap_start_configuration_learn(protocol_interface_info_entry ws_bootstrap_ip_stack_reset(cur); cur->ws_info->pas_requests = 0; + //Calculate max time for config learn state + cur->ws_info->pan_config_sol_max_timeout = trickle_timer_max(&cur->ws_info->trickle_params_pan_discovery, PCS_MAX); // Reset advertisement solicit trickle to start discovering network cur->ws_info->trickle_pcs_running = true; trickle_start(&cur->ws_info->trickle_pan_config_solicit, &cur->ws_info->trickle_params_pan_discovery); @@ -2387,8 +2466,11 @@ static void ws_bootstrap_rpl_scan_start(protocol_interface_info_entry_t *cur) tr_debug("Start RPL learn"); // routers wait until RPL root is contacted ws_bootstrap_state_change(cur, ER_RPL_SCAN); - // Set timeout for check to 30 -60 seconds - cur->bootsrap_state_machine_cnt = randLIB_get_random_in_range(WS_RPL_DIS_INITIAL_TIMEOUT / 2, WS_RPL_DIS_INITIAL_TIMEOUT); + //For Large network and medium shuold do passive scan + if (cur->ws_info->network_size_config == NETWORK_SIZE_LARGE || cur->ws_info->network_size_config == NETWORK_SIZE_MEDIUM) { + // Set timeout for check to 30 -60 seconds + cur->bootsrap_state_machine_cnt = randLIB_get_random_in_range(WS_RPL_DIS_INITIAL_TIMEOUT / 2, WS_RPL_DIS_INITIAL_TIMEOUT); + } } /* @@ -2494,13 +2576,11 @@ static uint16_t ws_bootstrap_routing_cost_calculate(protocol_interface_info_entr uint16_t etx = etx_local_etx_read(cur->id, mac_neighbor->index); if (etx == 0) { - etx = 0xffff; + etx = WS_ETX_MAX; //SET maxium value here if ETX is unknown + } else { + //Scale to 128 based ETX (local read retur 0x100 - 0xffff + etx = etx >> 1; } - if (etx > 0x800) { - // Wi-SUN section 6.2.3.1.6.1 says ETX can only be maximum of 1024 (8*128) in RPL units, ie 8.0. - etx = 0x800; - } - etx = etx >> 1; return ws_neighbor->routing_cost + etx; } @@ -2574,7 +2654,13 @@ static void ws_bootstrap_pan_config(protocol_interface_info_entry_t *cur) async_req.security.SecurityLevel = mac_helper_default_security_level_get(cur); async_req.security.KeyIdMode = mac_helper_default_security_key_id_mode_get(cur); - async_req.security.KeyIndex = mac_helper_default_key_index_get(cur); + if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER && cur->ws_info->pending_key_index_info.state == PENDING_KEY_INDEX_ADVERTISMENT) { + async_req.security.KeyIndex = cur->ws_info->pending_key_index_info.index + 1; + cur->ws_info->pending_key_index_info.state = PENDING_KEY_INDEX_ACTIVATE; + } else { + async_req.security.KeyIndex = mac_helper_default_key_index_get(cur); + } + ws_llc_asynch_request(cur, &async_req); } @@ -2594,6 +2680,11 @@ static void ws_bootstrap_event_handler(arm_event_s *event) break; case WS_DISCOVERY_START: tr_info("Discovery start"); + + //Clear Pending Key Index State + cur->ws_info->pending_key_index_info.state = NO_PENDING_PROCESS; + cur->mac_parameters->mac_default_key_index = 0; + // All trickle timers stopped to allow entry from any state cur->ws_info->trickle_pa_running = false; cur->ws_info->trickle_pc_running = false; @@ -2601,7 +2692,7 @@ static void ws_bootstrap_event_handler(arm_event_s *event) cur->ws_info->trickle_pcs_running = false; if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { - tr_debug("Border router start network"); + tr_info("Border router start network"); if (!ws_bbr_ready_to_start(cur)) { // Wi-SUN not started yet we wait for Border router permission @@ -2722,12 +2813,17 @@ void ws_bootstrap_network_scan_process(protocol_interface_info_entry_t *cur) tr_debug("analyze network discovery result"); +select_best_candidate: selected_parent_ptr = ws_bootstrap_candidate_parent_get_best(cur); if (!selected_parent_ptr) { + // Configure LLC for network discovery + ws_bootstrap_network_discovery_configure(cur); + // randomize new channel and start MAC + ws_bootstrap_fhss_activate(cur); // Next check will be after one trickle cur->bootsrap_state_machine_cnt += cur->ws_info->trickle_params_pan_discovery.Imin + randLIB_get_8bit() % 50; - tr_info("Making parent selection in %d s", (uint32_t)(cur->bootsrap_state_machine_cnt / 10)); + tr_info("Making parent selection in %u s", (cur->bootsrap_state_machine_cnt / 10)); return; } tr_info("selected parent:%s panid %u", trace_array(selected_parent_ptr->addr, 8), selected_parent_ptr->pan_id); @@ -2740,7 +2836,10 @@ void ws_bootstrap_network_scan_process(protocol_interface_info_entry_t *cur) ws_bootstrap_fhss_activate(cur); llc_neighbour_req_t neighbor_info; if (!ws_bootstrap_neighbor_info_request(cur, selected_parent_ptr->addr, &neighbor_info, true)) { - return; + //Remove Neighbour and set Link setup back + ns_list_remove(&cur->ws_info->parent_list_reserved, selected_parent_ptr); + ns_list_add_to_end(&cur->ws_info->parent_list_free, selected_parent_ptr); + goto select_best_candidate; } ws_neighbor_class_neighbor_unicast_time_info_update(neighbor_info.ws_neighbor, &selected_parent_ptr->ws_utt, selected_parent_ptr->timestamp); @@ -2848,7 +2947,7 @@ void ws_bootstrap_state_machine(protocol_interface_info_entry_t *cur) cur->ws_info->trickle_pc_running = false; cur->ws_info->trickle_pas_running = false; cur->ws_info->trickle_pcs_running = false; - + ws_fhss_configure(cur, false); ws_bootstrap_start_authentication(cur); break; case ER_RPL_SCAN: @@ -2873,20 +2972,34 @@ void ws_bootstrap_trickle_timer(protocol_interface_info_entry_t *cur, uint16_t t tr_info("Send PAN advertisement Solicit"); ws_bootstrap_pan_advert_solicit(cur); } - if (cur->ws_info->trickle_pcs_running && - trickle_timer(&cur->ws_info->trickle_pan_config_solicit, &cur->ws_info->trickle_params_pan_discovery, ticks)) { - // send PAN Configuration solicit - if (cur->ws_info->pas_requests >= PCS_MAX) { - // if MAX PCS sent restart discovery + if (cur->ws_info->trickle_pcs_running) { + //Update MAX config sol timeout timer + if (cur->ws_info->pan_config_sol_max_timeout > ticks) { + cur->ws_info->pan_config_sol_max_timeout -= ticks; + } else { + //Config sol state timeout + cur->ws_info->pan_config_sol_max_timeout = 0; + } + + if (trickle_timer(&cur->ws_info->trickle_pan_config_solicit, &cur->ws_info->trickle_params_pan_discovery, ticks)) { + if (cur->ws_info->pas_requests < PCS_MAX) { + // send PAN Configuration solicit + tr_info("Send PAN configuration Solicit"); + ws_bootstrap_pan_config_solicit(cur); + } + //Update counter every time reason that we detect PCS_MAX higher state + cur->ws_info->pas_requests++; + } + + if (cur->ws_info->pas_requests > PCS_MAX || cur->ws_info->pan_config_sol_max_timeout == 0) { + // if MAX PCS sent or max waited timeout restart discovery // Trickle is reseted when entering to discovery from state 3 + tr_info("PAN configuration Solicit timeout"); trickle_inconsistent_heard(&cur->ws_info->trickle_pan_advertisement_solicit, &cur->ws_info->trickle_params_pan_discovery); ws_bootstrap_event_discovery_start(cur); return; } - tr_info("Send PAN configuration Solicit"); - cur->ws_info->pas_requests++; - ws_bootstrap_pan_config_solicit(cur); } if (cur->ws_info->trickle_pa_running && trickle_timer(&cur->ws_info->trickle_pan_advertisement, &cur->ws_info->trickle_params_pan_discovery, ticks)) { @@ -2943,23 +3056,4 @@ void ws_secondary_parent_update(protocol_interface_info_entry_t *interface) } } -void ws_bootstrap_etx_accelerate(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neigh) -{ - ws_neighbor_class_entry_t *ws_neighbor = ws_neighbor_class_entry_get(&interface->ws_info->neighbor_storage, neigh->index); - //Enable Faster ETX probing - ws_neighbor->accelerated_etx_probe = true; - //Move Neighbor to first to for accelerate Process - mac_neighbor_table_t *table_class = mac_neighbor_info(interface); - ns_list_remove(&table_class->neighbour_list, neigh); - ns_list_add_to_start(&table_class->neighbour_list, neigh); - //Try to Generate Active NUD Immediately - if (!ws_neighbor_entry_nud_notify(neigh, interface)) { - return;//Return if NUD active is full - } - table_class->active_nud_process++; - neigh->nud_active = true; - //Push NS to send - ws_nud_active_timer(interface, 0); -} - #endif //HAVE_WS diff --git a/source/6LoWPAN/ws/ws_bootstrap.h b/source/6LoWPAN/ws/ws_bootstrap.h index 9d7f552465..062dc767a3 100644 --- a/source/6LoWPAN/ws/ws_bootstrap.h +++ b/source/6LoWPAN/ws/ws_bootstrap.h @@ -76,8 +76,6 @@ bool ws_eapol_relay_state_active(protocol_interface_info_entry_t *cur); void ws_bootstrap_eapol_parent_synch(struct protocol_interface_info_entry *cur, struct llc_neighbour_req *neighbor_info); -void ws_bootstrap_etx_accelerate(struct protocol_interface_info_entry *cur, mac_neighbor_table_entry_t *neigh); - #else #define ws_bootstrap_init(interface_id, bootstrap_mode) (-1) @@ -87,7 +85,6 @@ void ws_bootstrap_etx_accelerate(struct protocol_interface_info_entry *cur, mac_ #define ws_bootstrap_aro_failure(cur, ll_address) #define ws_primary_parent_update(interface, neighbor) #define ws_secondary_parent_update(interface) -#define ws_bootstrap_etx_accelerate(cur, neigh) ((void) 0) #endif //HAVE_WS diff --git a/source/6LoWPAN/ws/ws_common.c b/source/6LoWPAN/ws/ws_common.c index 449a4d8e0d..f89fbaa748 100644 --- a/source/6LoWPAN/ws/ws_common.c +++ b/source/6LoWPAN/ws/ws_common.c @@ -22,6 +22,7 @@ #include "randLIB.h" #include #include +#include "Common_Protocols/icmpv6.h" #include "6LoWPAN/ws/ws_config.h" #include "6LoWPAN/ws/ws_common_defines.h" #include "6LoWPAN/ws/ws_common.h" @@ -316,6 +317,9 @@ int8_t ws_common_allocate_and_init(protocol_interface_info_entry_t *cur) cur->ws_info->fhss_bc_dwell_interval = WS_FHSS_BC_DWELL_INTERVAL; cur->ws_info->fhss_uc_channel_function = WS_DH1CF; cur->ws_info->fhss_bc_channel_function = WS_DH1CF; + + cur->ws_info->pending_key_index_info.state = NO_PENDING_PROCESS; + for (uint8_t n = 0; n < 8; n++) { cur->ws_info->fhss_channel_mask[n] = 0xffffffff; } @@ -335,11 +339,11 @@ void ws_common_network_size_configure(protocol_interface_info_entry_t *cur, uint // doublings:3 (128s) // redundancy; 0 Disabled if (cur->ws_info->network_size_config == NETWORK_SIZE_AUTOMATIC) { - ws_bbr_rpl_config(14, 3, 0, WS_RPL_MAX_HOP_RANK_INCREASE, WS_RPL_MIN_HOP_RANK_INCREASE); + ws_bbr_rpl_config(cur, 14, 3, 0, WS_RPL_MAX_HOP_RANK_INCREASE, WS_RPL_MIN_HOP_RANK_INCREASE); } else if (cur->ws_info->network_size_config == NETWORK_SIZE_CERTIFICATE) { - ws_bbr_rpl_config(0, 0, 0, WS_CERTIFICATE_RPL_MAX_HOP_RANK_INCREASE, WS_CERTIFICATE_RPL_MIN_HOP_RANK_INCREASE); + ws_bbr_rpl_config(cur, 0, 0, 0, WS_CERTIFICATE_RPL_MAX_HOP_RANK_INCREASE, WS_CERTIFICATE_RPL_MIN_HOP_RANK_INCREASE); } else { - ws_bbr_rpl_config(0, 0, 0, WS_RPL_MAX_HOP_RANK_INCREASE, WS_RPL_MIN_HOP_RANK_INCREASE); + ws_bbr_rpl_config(cur, 0, 0, 0, WS_RPL_MAX_HOP_RANK_INCREASE, WS_RPL_MIN_HOP_RANK_INCREASE); } ws_pae_controller_timing_adjust(1); // Fast and reactive network } else if (network_size < 300) { @@ -349,7 +353,7 @@ void ws_common_network_size_configure(protocol_interface_info_entry_t *cur, uint // imin: 15 (32s) // doublings:5 (960s) // redundancy; 10 - ws_bbr_rpl_config(15, 5, 10, WS_RPL_MAX_HOP_RANK_INCREASE, WS_RPL_MIN_HOP_RANK_INCREASE); + ws_bbr_rpl_config(cur, 15, 5, 10, WS_RPL_MAX_HOP_RANK_INCREASE, WS_RPL_MIN_HOP_RANK_INCREASE); ws_pae_controller_timing_adjust(9); // medium limited network } else { // Configure the Wi-SUN discovery trickle parameters @@ -358,7 +362,7 @@ void ws_common_network_size_configure(protocol_interface_info_entry_t *cur, uint // imin: 19 (524s, 9 min) // doublings:1 (1048s, 17 min) // redundancy; 10 May need some tuning still - ws_bbr_rpl_config(19, 1, 10, WS_RPL_MAX_HOP_RANK_INCREASE, WS_RPL_MIN_HOP_RANK_INCREASE); + ws_bbr_rpl_config(cur, 19, 1, 10, WS_RPL_MAX_HOP_RANK_INCREASE, WS_RPL_MIN_HOP_RANK_INCREASE); ws_pae_controller_timing_adjust(24); // Very slow and high latency network } return; @@ -387,12 +391,10 @@ void ws_common_neighbor_update(protocol_interface_info_entry_t *cur, const uint8 } } -void ws_common_aro_failure(protocol_interface_info_entry_t *cur, const uint8_t *ll_address, bool cache_full) +void ws_common_aro_failure(protocol_interface_info_entry_t *cur, const uint8_t *ll_address) { tr_warn("ARO registration Failure %s", trace_ipv6(ll_address)); - if (cache_full) { - blacklist_update(ll_address, false); - } + blacklist_update(ll_address, false); ws_bootstrap_aro_failure(cur, ll_address); } @@ -404,7 +406,7 @@ void ws_common_neighbor_remove(protocol_interface_info_entry_t *cur, const uint8 -bool ws_common_allow_child_registration(protocol_interface_info_entry_t *interface, const uint8_t *eui64) +uint8_t ws_common_allow_child_registration(protocol_interface_info_entry_t *interface, const uint8_t *eui64) { uint8_t child_count = 0; uint8_t max_child_count = mac_neighbor_info(interface)->list_total_size - WS_NON_CHILD_NEIGHBOUR_COUNT; @@ -417,13 +419,13 @@ bool ws_common_allow_child_registration(protocol_interface_info_entry_t *interfa //Validate Is EUI64 already allocated for any address if (ipv6_neighbour_has_registered_by_eui64(&interface->ipv6_neighbour_cache, eui64)) { tr_info("Child registration from old child"); - return true; + return ARO_SUCCESS; } //Verify that we have Selected Parent if (interface->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER && !rpl_control_parent_candidate_list_size(interface, true)) { tr_info("Do not accept new ARO child: no selected parent"); - return false; + return ARO_TOPOLOGICALLY_INCORRECT; } @@ -435,10 +437,10 @@ bool ws_common_allow_child_registration(protocol_interface_info_entry_t *interfa } if (child_count >= max_child_count) { tr_warn("Child registration not allowed %d/%d, max:%d", child_count, max_child_count, mac_neighbor_info(interface)->list_total_size); - return false; + return ARO_FULL; } tr_info("Child registration allowed %d/%d, max:%d", child_count, max_child_count, mac_neighbor_info(interface)->list_total_size); - return true; + return ARO_SUCCESS; } bool ws_common_negative_aro_mark(protocol_interface_info_entry_t *interface, const uint8_t *eui64) @@ -447,23 +449,13 @@ bool ws_common_negative_aro_mark(protocol_interface_info_entry_t *interface, con if (!neighbour) { return false; } + ws_neighbor_class_entry_t *ws_neighbor = ws_neighbor_class_entry_get(&interface->ws_info->neighbor_storage, neighbour->index); ws_neighbor->negative_aro_send = true; neighbour->lifetime = WS_NEIGHBOR_TEMPORARY_LINK_MIN_TIMEOUT_SMALL; //Remove anyway if Packet is freed before MAC push return true; } -void ws_common_etx_validate(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neigh) -{ - etx_storage_t *etx_entry = etx_storage_entry_get(interface->id, neigh->index); - - if (neigh->nud_active || !neigh->trusted_device || !etx_entry || etx_entry->etx_samples) { - return; //Do not trig Second NS if Active NUD already, not trusted or ETX samples already done - } - - ws_bootstrap_etx_accelerate(interface, neigh); -} - uint32_t ws_common_version_lifetime_get(uint8_t config) { uint32_t lifetime; diff --git a/source/6LoWPAN/ws/ws_common.h b/source/6LoWPAN/ws/ws_common.h index a901d08b27..588902753f 100644 --- a/source/6LoWPAN/ws/ws_common.h +++ b/source/6LoWPAN/ws/ws_common.h @@ -60,6 +60,15 @@ typedef struct ws_nud_table_entry { ns_list_link_t link; } ws_nud_table_entry_t; +#define NO_PENDING_PROCESS 0 +#define PENDING_KEY_INDEX_ADVERTISMENT 1 +#define PENDING_KEY_INDEX_ACTIVATE 2 + +typedef struct { + unsigned state: 2; + uint8_t index; +} ws_pending_key_index_t; + typedef NS_LIST_HEAD(ws_nud_table_entry_t, link) ws_nud_table_list_t; typedef struct ws_info_s { @@ -79,15 +88,17 @@ typedef struct ws_info_s { parent_info_t parent_info[WS_PARENT_LIST_SIZE]; parent_info_list_t parent_list_free; parent_info_list_t parent_list_reserved; - uint32_t pan_version_timer; /**< border router version udate timeout */ + uint16_t rpl_version_timer; /**< RPL version update timeout */ + uint32_t pan_version_timer; /**< border router version update timeout */ uint32_t pan_version_timeout_timer; /**< routers will fallback to previous state after this */ + uint32_t pan_config_sol_max_timeout; uint8_t gtkhash[32]; bool configuration_learned: 1; bool trickle_pas_running: 1; bool trickle_pa_running: 1; bool trickle_pcs_running: 1; bool trickle_pc_running: 1; - bool fhss_owner: 1; + ws_pending_key_index_t pending_key_index_info; // default fhss parameters for this device uint8_t fhss_uc_dwell_interval; uint8_t fhss_bc_dwell_interval; @@ -126,13 +137,11 @@ void ws_common_fast_timer(protocol_interface_info_entry_t *cur, uint16_t ticks); void ws_common_neighbor_update(protocol_interface_info_entry_t *cur, const uint8_t *ll_address); -void ws_common_aro_failure(protocol_interface_info_entry_t *cur, const uint8_t *ll_address, bool cache_full); +void ws_common_aro_failure(protocol_interface_info_entry_t *cur, const uint8_t *ll_address); void ws_common_neighbor_remove(protocol_interface_info_entry_t *cur, const uint8_t *ll_address); -bool ws_common_allow_child_registration(protocol_interface_info_entry_t *cur, const uint8_t *eui64); - -void ws_common_etx_validate(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neigh); +uint8_t ws_common_allow_child_registration(protocol_interface_info_entry_t *cur, const uint8_t *eui64); bool ws_common_negative_aro_mark(protocol_interface_info_entry_t *interface, const uint8_t *eui64); @@ -146,11 +155,10 @@ uint32_t ws_common_version_timeout_get(uint8_t config); #define ws_info(cur) ((ws_info_t *) NULL) #define ws_common_seconds_timer(cur, seconds) #define ws_common_neighbor_update(cur, ll_address) ((void) 0) -#define ws_common_aro_failure(cur, ll_address, cache_full) +#define ws_common_aro_failure(cur, ll_address) #define ws_common_neighbor_remove(cur, ll_address) #define ws_common_fast_timer(cur, ticks) ((void) 0) -#define ws_common_allow_child_registration(cur, eui64) (false) -#define ws_common_etx_validate(interface, neigh) ((void) 0) +#define ws_common_allow_child_registration(cur, eui64) (2) #define ws_common_negative_aro_mark(interface, eui64)(false) #endif //HAVE_WS diff --git a/source/6LoWPAN/ws/ws_common_defines.h b/source/6LoWPAN/ws/ws_common_defines.h index f9f07fe701..92f7da38eb 100644 --- a/source/6LoWPAN/ws/ws_common_defines.h +++ b/source/6LoWPAN/ws/ws_common_defines.h @@ -190,7 +190,8 @@ typedef struct ws_bs_ie { #define WS_NEIGHBOR_TEMPORARY_LINK_MIN_TIMEOUT_SMALL 260 #define WS_NEIGHBOR_NUD_TIMEOUT WS_NEIGHBOR_LINK_TIMEOUT / 2 -#define WS_NEIGBOR_ETX_SAMPLE_MAX 3 +#define WS_NEIGHBOR_ETX_SAMPLE_MAX 3 +#define WS_NEIGHBOR_FIRST_ETX_SAMPLE_MIN_COUNT 3 //This can't be bigger than WS_NEIGHBOR_ETX_SAMPLE_MAX #define WS_NEIGHBOUR_MAX_CANDIDATE_PROBE 5 #define WS_PROBE_INIT_BASE_SECONDS 8 @@ -204,6 +205,7 @@ typedef struct ws_bs_ie { #define WS_ETX_MIN_SAMPLE_COUNT 4 #define WS_ETX_MAX_UPDATE 1024 +#define WS_ETX_MAX 1024 #define WS_ETX_MIN_WAIT_TIME 60 @@ -211,7 +213,7 @@ typedef struct ws_bs_ie { #define WS_RPL_SELECTED_PARENT_MAX 2 #define WS_CERTIFICATE_RPL_PARENT_CANDIDATE_MAX 8 -#define WS_CERTIFICATE_RPL_SELECTED_PARENT_MAX 3 +#define WS_CERTIFICATE_RPL_SELECTED_PARENT_MAX 4 /** * Wi-sun spesific non-preferred prefix policy label diff --git a/source/6LoWPAN/ws/ws_config.h b/source/6LoWPAN/ws/ws_config.h index 9ff0007021..e7afc90d98 100644 --- a/source/6LoWPAN/ws/ws_config.h +++ b/source/6LoWPAN/ws/ws_config.h @@ -46,7 +46,10 @@ #define PAN_VERSION_MEDIUM_NETWORK_LIFETIME 15*60 #define PAN_VERSION_LARGE_NETWORK_LIFETIME 30*60 //30min -#define RPL_VERSION_LIFETIME 5*3600 +// RPL version number update intervall +// after restart version numbers are increased faster and then slowed down when network is stable +#define RPL_VERSION_LIFETIME 12*3600 +#define RPL_VERSION_LIFETIME_RESTART 3600 /* Border router connection lost timeout * @@ -100,7 +103,7 @@ extern uint8_t DEVICE_MIN_SENS; #define DATA_MESSAGE_IMIN (10 * 1000) #define DATA_MESSAGE_TIMER_EXPIRATIONS 3 -#define DATA_MESSAGE_IMAX (DATA_MESSAGE_IMIN) +#define DATA_MESSAGE_IMAX (80 * 1000) #define MPL_SEED_SET_ENTRY_TIMEOUT (DATA_MESSAGE_IMAX * 24 * 4 / 1000) // 10 seconds per hop making this 240 seconds /* DHCP client timeout configuration values @@ -145,7 +148,11 @@ extern uint8_t DEVICE_MIN_SENS; */ #define WS_MAX_DAO_RETRIES 3 // With 40s, 80s, 160s, 320s, 640s #define WS_MAX_DAO_INITIAL_TIMEOUT 400 // With 40s initial value exponentially increasing -#define WS_MIN_DIO_MULTICAST_CONFIG_ADVERTISMENT_COUNT 10 // Define 10 multicast advertisment when learn config or learn config update +#define WS_MIN_DIO_MULTICAST_CONFIG_ADVERTISMENT_COUNT 0xff // Advertisment config at every MC DIO +#define WS_MAX_PARENT_SET_COUNT 2 // maximum amount of parents selected by node + +#define WS_NODE_RPL_SOFT_MEM_LIMIT 4*1024 // Limit when RPL start purge unused data +#define WS_NODE_RPL_HARD_MEM_LIMIT 6*1024 // Limit when RPL memory allocation start limit allocation /* * Candidate parent list parameters diff --git a/source/6LoWPAN/ws/ws_llc_data_service.c b/source/6LoWPAN/ws/ws_llc_data_service.c index 00523518eb..9e94dbbe4c 100644 --- a/source/6LoWPAN/ws/ws_llc_data_service.c +++ b/source/6LoWPAN/ws/ws_llc_data_service.c @@ -560,7 +560,7 @@ static void ws_llc_mac_indication_cb(const mac_api_t *api, const mcps_data_ind_t if (!base->ws_neighbor_info_request_cb(interface, data->SrcAddr, &neighbor_info, request_new_entry)) { if (!multicast || ws_utt.message_type == WS_FT_EAPOL) { - tr_debug("Drop message no neighbor"); + //tr_debug("Drop message no neighbor"); return; } else { //Allocate temporary entry diff --git a/source/6LoWPAN/ws/ws_management_api.c b/source/6LoWPAN/ws/ws_management_api.c index e8be8dac51..63f7322326 100644 --- a/source/6LoWPAN/ws/ws_management_api.c +++ b/source/6LoWPAN/ws/ws_management_api.c @@ -220,20 +220,32 @@ int ws_management_fhss_timing_configure( if (!cur || !ws_info(cur)) { return -1; } - if (fhss_uc_dwell_interval > 0) { + + if (fhss_uc_dwell_interval && fhss_uc_dwell_interval < 15) { + return -2; + } + + if (fhss_bc_dwell_interval && fhss_bc_dwell_interval < 15) { + return -2; + } + + bool updated_configure = false; + + if (fhss_uc_dwell_interval > 0 && cur->ws_info->fhss_uc_dwell_interval != fhss_uc_dwell_interval) { cur->ws_info->fhss_uc_dwell_interval = fhss_uc_dwell_interval; + updated_configure = true; } - if (fhss_broadcast_interval > 0) { + if (fhss_broadcast_interval > 0 && cur->ws_info->fhss_bc_interval != fhss_broadcast_interval) { cur->ws_info->fhss_bc_interval = fhss_broadcast_interval; - + updated_configure = true; } - if (fhss_bc_dwell_interval > 0) { + if (fhss_bc_dwell_interval > 0 && cur->ws_info->fhss_bc_dwell_interval != fhss_bc_dwell_interval) { cur->ws_info->fhss_bc_dwell_interval = fhss_bc_dwell_interval; - + updated_configure = true; } // if settings change reset_restart for the settings needed - if (cur->lowpan_info & INTERFACE_NWK_ACTIVE) { + if (updated_configure && (cur->lowpan_info & INTERFACE_NWK_ACTIVE)) { // bootstrap active need to restart ws_bootstrap_restart(interface_id); } @@ -259,23 +271,38 @@ int ws_management_fhss_unicast_channel_function_configure( return -2; } + if (dwell_interval && dwell_interval < 15) { + return -2; + } + if (channel_function == WS_FIXED_CHANNEL && fixed_channel == 0xffff) { fixed_channel = 0; tr_warn("Fixed channel not configured. Set to 0"); } + bool updated_config = false; + + if (cur->ws_info->fhss_uc_channel_function != channel_function) { + cur->ws_info->fhss_uc_channel_function = channel_function; + updated_config = true; + } - cur->ws_info->fhss_uc_channel_function = channel_function; if (cur->ws_info->fhss_uc_channel_function == WS_FIXED_CHANNEL) { - cur->ws_info->fhss_uc_fixed_channel = fixed_channel; + if (cur->ws_info->fhss_uc_fixed_channel != fixed_channel) { + cur->ws_info->fhss_uc_fixed_channel = fixed_channel; + updated_config = true; + } } else { cur->ws_info->fhss_uc_fixed_channel = 0xffff; } - cur->ws_info->fhss_uc_dwell_interval = dwell_interval; + if (dwell_interval && cur->ws_info->fhss_uc_dwell_interval != dwell_interval) { + cur->ws_info->fhss_uc_dwell_interval = dwell_interval; + updated_config = true; + } // if settings change reset_restart for the settings needed - if (cur->lowpan_info & INTERFACE_NWK_ACTIVE) { + if (updated_config && (cur->lowpan_info & INTERFACE_NWK_ACTIVE)) { // bootstrap active need to restart ws_bootstrap_restart(interface_id); } @@ -303,23 +330,43 @@ int ws_management_fhss_broadcast_channel_function_configure( return -2; } + if (dwell_interval && dwell_interval < 15) { + return -2; + } + if (channel_function == WS_FIXED_CHANNEL && fixed_channel == 0xffff) { fixed_channel = 0; tr_warn("Fixed channel not configured. Set to 0"); } - cur->ws_info->fhss_bc_channel_function = channel_function; + bool updated_config = false; + + if (cur->ws_info->fhss_bc_channel_function != channel_function) { + cur->ws_info->fhss_bc_channel_function = channel_function; + updated_config = true; + } + if (cur->ws_info->fhss_bc_channel_function == WS_FIXED_CHANNEL) { - cur->ws_info->fhss_bc_fixed_channel = fixed_channel; + if (cur->ws_info->fhss_bc_fixed_channel != fixed_channel) { + cur->ws_info->fhss_bc_fixed_channel = fixed_channel; + updated_config = true; + } } else { cur->ws_info->fhss_bc_fixed_channel = 0xffff; } - cur->ws_info->fhss_bc_dwell_interval = dwell_interval; - cur->ws_info->fhss_bc_interval = broadcast_interval; + if (dwell_interval > 0 && cur->ws_info->fhss_bc_dwell_interval != dwell_interval) { + cur->ws_info->fhss_bc_dwell_interval = dwell_interval; + updated_config = true; + } + + if (broadcast_interval > 0 && cur->ws_info->fhss_bc_interval != broadcast_interval) { + cur->ws_info->fhss_bc_interval = broadcast_interval; + updated_config = true; + } // if settings change reset_restart for the settings needed - if (cur->lowpan_info & INTERFACE_NWK_ACTIVE) { + if (updated_config && (cur->lowpan_info & INTERFACE_NWK_ACTIVE)) { // bootstrap active need to restart ws_bootstrap_restart(interface_id); } diff --git a/source/6LoWPAN/ws/ws_neighbor_class.h b/source/6LoWPAN/ws/ws_neighbor_class.h index 2a0cbe2c12..c381b43f50 100644 --- a/source/6LoWPAN/ws/ws_neighbor_class.h +++ b/source/6LoWPAN/ws/ws_neighbor_class.h @@ -32,7 +32,6 @@ typedef struct ws_neighbor_class_entry { bool broadcast_timing_info_stored: 1; bool broadcast_shedule_info_stored: 1; bool synch_done : 1; - bool accelerated_etx_probe : 1; bool negative_aro_send : 1; bool unicast_data_rx : 1; } ws_neighbor_class_entry_t; diff --git a/source/6LoWPAN/ws/ws_pae_auth.c b/source/6LoWPAN/ws/ws_pae_auth.c index aeac106531..01ffea5603 100644 --- a/source/6LoWPAN/ws/ws_pae_auth.c +++ b/source/6LoWPAN/ws/ws_pae_auth.c @@ -70,6 +70,9 @@ nanostack monitor */ #define SUPPLICANT_NUMBER_TO_PURGE 5 +// Short GTK lifetime value, for GTK install check +#define SHORT_GTK_LIFETIME 10 * 3600 // 10 hours + typedef struct { ns_list_link_t link; /**< Link */ kmp_service_t *kmp_service; /**< KMP service */ @@ -113,7 +116,7 @@ static void ws_pae_auth_kmp_api_create_confirm(kmp_api_t *kmp, kmp_result_e resu static void ws_pae_auth_kmp_api_create_indication(kmp_api_t *kmp, kmp_type_e type, kmp_addr_t *addr); static void ws_pae_auth_kmp_api_finished_indication(kmp_api_t *kmp, kmp_result_e result, kmp_sec_keys_t *sec_keys); static void ws_pae_auth_next_kmp_trigger(pae_auth_t *pae_auth, supp_entry_t *supp_entry); -static kmp_type_e ws_pae_auth_next_protocol_get(supp_entry_t *supp_entry); +static kmp_type_e ws_pae_auth_next_protocol_get(pae_auth_t *pae_auth, supp_entry_t *supp_entry); static kmp_api_t *ws_pae_auth_kmp_create_and_start(kmp_service_t *service, kmp_type_e type, supp_entry_t *supp_entry); static void ws_pae_auth_kmp_api_finished(kmp_api_t *kmp); @@ -666,7 +669,9 @@ static void ws_pae_auth_gtk_key_insert(pae_auth_t *pae_auth) sec_prot_keys_gtk_clear(pae_auth->next_gtks, next_gtk_index); sec_prot_keys_gtk_set(pae_auth->next_gtks, next_gtk_index, gtk_value, 0); } else { - randLIB_get_n_bytes_random(gtk_value, GTK_LEN); + do { + randLIB_get_n_bytes_random(gtk_value, GTK_LEN); + } while (sec_prot_keys_gtk_valid_check(gtk_value) < 0); } // Gets latest installed key lifetime and adds GTK expire offset to it @@ -910,7 +915,7 @@ static void ws_pae_auth_next_kmp_trigger(pae_auth_t *pae_auth, supp_entry_t *sup supp_entry->retry_ticks = 0; // Get next protocol based on what keys supplicant has - kmp_type_e next_type = ws_pae_auth_next_protocol_get(supp_entry); + kmp_type_e next_type = ws_pae_auth_next_protocol_get(pae_auth, supp_entry); if (next_type == KMP_TYPE_NONE) { // All done @@ -969,7 +974,7 @@ static void ws_pae_auth_next_kmp_trigger(pae_auth_t *pae_auth, supp_entry_t *sup kmp_api_create_request(new_kmp, next_type, &supp_entry->addr, &supp_entry->sec_keys); } -static kmp_type_e ws_pae_auth_next_protocol_get(supp_entry_t *supp_entry) +static kmp_type_e ws_pae_auth_next_protocol_get(pae_auth_t *pae_auth, supp_entry_t *supp_entry) { kmp_type_e next_type = KMP_TYPE_NONE; sec_prot_keys_t *sec_keys = &supp_entry->sec_keys; @@ -999,9 +1004,22 @@ static kmp_type_e ws_pae_auth_next_protocol_get(supp_entry_t *supp_entry) if (gtk_index >= 0) { if (next_type == KMP_TYPE_NONE && gtk_index >= 0) { - // Update just GTK - next_type = IEEE_802_11_GKH; - tr_info("PAE start GKH, eui-64: %s", trace_array(supp_entry->addr.eui_64, 8)); + + /* Check if the PTK has been already used to install GTK to specific index and if it + * has been, trigger 4WH to update also the PTK. This prevents writing multiple + * GTK keys to same index using same PTK. + */ + if (pae_auth->timer_settings->gtk_expire_offset > SHORT_GTK_LIFETIME && + sec_prot_keys_ptk_installed_gtk_hash_mismatch_check(sec_keys, gtk_index)) { + // start 4WH towards supplicant + next_type = IEEE_802_11_4WH; + sec_keys->ptk_mismatch = true; + tr_info("PAE start 4WH due to GTK index re-use, eui-64: %s", trace_array(supp_entry->addr.eui_64, 8)); + } else { + // Update just GTK + next_type = IEEE_802_11_GKH; + tr_info("PAE start GKH, eui-64: %s", trace_array(supp_entry->addr.eui_64, 8)); + } } tr_info("PAE update GTK index: %i, eui-64: %s", gtk_index, trace_array(supp_entry->addr.eui_64, 8)); diff --git a/source/6LoWPAN/ws/ws_pae_auth.h b/source/6LoWPAN/ws/ws_pae_auth.h index 5c0f35d960..04bd157d78 100644 --- a/source/6LoWPAN/ws/ws_pae_auth.h +++ b/source/6LoWPAN/ws/ws_pae_auth.h @@ -232,7 +232,7 @@ void ws_pae_auth_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_ #else #define ws_pae_auth_init(interface_ptr, gtks, next_gtks, certs, timer_settings) 1 -#define ws_pae_auth_timing_adjust(timing) 1 +#define ws_pae_auth_timing_adjust(timing) #define ws_pae_auth_addresses_set(interface_ptr, local_port, remote_addr, remote_port) 1 #define ws_pae_auth_delete NULL #define ws_pae_auth_cb_register(interface_ptr, hash_set, nw_key_insert, nw_key_index_set) {(void) hash_set;} diff --git a/source/6LoWPAN/ws/ws_pae_controller.c b/source/6LoWPAN/ws/ws_pae_controller.c index 6db0877be7..f5bc4dba92 100644 --- a/source/6LoWPAN/ws/ws_pae_controller.c +++ b/source/6LoWPAN/ws/ws_pae_controller.c @@ -88,6 +88,7 @@ typedef struct { bool gtks_set : 1; /**< GTKs are set */ bool gtkhash_set : 1; /**< GTK hashes are set */ bool key_index_set : 1; /**< NW key index is set */ + bool frame_counter_read : 1; /**< Frame counters has been read */ } pae_controller_t; typedef struct { @@ -108,6 +109,7 @@ static int8_t ws_pae_controller_nw_key_check_and_insert(protocol_interface_info_ static void ws_pae_controller_active_nw_key_clear(nw_key_t *nw_key); static void ws_pae_controller_active_nw_key_set(protocol_interface_info_entry_t *cur, uint8_t index); static int8_t ws_pae_controller_gak_from_gtk(uint8_t *gak, uint8_t *gtk, char *network_name); +static void ws_pae_controller_frame_counter_store_and_nw_keys_remove(protocol_interface_info_entry_t *interface_ptr, pae_controller_t *controller, bool use_threshold); static void ws_pae_controller_nw_key_index_check_and_set(protocol_interface_info_entry_t *interface_ptr, uint8_t index); static void ws_pae_controller_data_init(pae_controller_t *controller); static void ws_pae_controller_frame_counter_read(pae_controller_t *controller); @@ -363,12 +365,16 @@ static int8_t ws_pae_controller_nw_key_check_and_insert(protocol_interface_info_ if (ws_pae_controller_gak_from_gtk(gak, gtk, controller->network_name) >= 0) { // Install the new network key derived from GTK and network name (GAK) to MAC controller->nw_key_set(interface_ptr, i, i, gak); - tr_info("NW: %s", controller->network_name); - tr_info("NW: %s", trace_array((uint8_t *)controller->network_name, 20)); - tr_info("GTK: %s", trace_array(gtk, 16)); - tr_info("GAK: %s", trace_array(gak, 16)); nw_key[i].installed = true; ret = 0; +#ifdef EXTRA_DEBUG_INFO + tr_info("NW name: %s", controller->network_name); + size_t nw_name_len = strlen(controller->network_name); + tr_info("NW name: %s", trace_array((uint8_t *)controller->network_name, nw_name_len)); + tr_info("GTK: %s", trace_array(gtk, 16)); + tr_info("GAK: %s", trace_array(gak, 16)); +#endif + } else { tr_error("GAK generation failed network name: %s", controller->network_name); continue; @@ -380,9 +386,11 @@ static int8_t ws_pae_controller_nw_key_check_and_insert(protocol_interface_info_ // Read current counter from MAC uint32_t curr_frame_counter; controller->nw_frame_counter_read(controller->interface_ptr, &curr_frame_counter, i); + // If stored frame counter is greater than MAC counter if (controller->frame_counters.counter[i].frame_counter > curr_frame_counter) { - tr_debug("Frame counter set: %i, stored %"PRIu32" current: %"PRIu32"", i, controller->frame_counters.counter[i].frame_counter, curr_frame_counter); + tr_debug("Frame counter set: %i, stored %"PRIu32" current: %"PRIu32"", i, + controller->frame_counters.counter[i].frame_counter, curr_frame_counter); curr_frame_counter = controller->frame_counters.counter[i].frame_counter; // Updates MAC frame counter controller->nw_frame_counter_set(controller->interface_ptr, curr_frame_counter, i); @@ -474,6 +482,16 @@ void ws_pae_controller_nw_keys_remove(protocol_interface_info_entry_t *interface return; } + /* Stores frame counters if incremented by threshold and removes network keys from PAE + controller and MAC */ + ws_pae_controller_frame_counter_store_and_nw_keys_remove(interface_ptr, controller, true); +} + +static void ws_pae_controller_frame_counter_store_and_nw_keys_remove(protocol_interface_info_entry_t *interface_ptr, pae_controller_t *controller, bool use_threshold) +{ + /* Checks if frame counters needs to be stored when keys are removed */ + ws_pae_controller_frame_counter_store(controller, use_threshold); + tr_info("NW keys remove"); nw_key_t *nw_key = controller->nw_key; @@ -589,6 +607,7 @@ static void ws_pae_controller_data_init(pae_controller_t *controller) controller->gtks_set = false; controller->gtkhash_set = false; controller->key_index_set = false; + controller->frame_counter_read = false; controller->gtk_index = -1; controller->network_name = NULL; controller->frame_cnt_store_timer = FRAME_COUNTER_STORE_INTERVAL; @@ -602,6 +621,11 @@ static void ws_pae_controller_data_init(pae_controller_t *controller) static void ws_pae_controller_frame_counter_read(pae_controller_t *controller) { + if (controller->frame_counter_read) { + return; + } + controller->frame_counter_read = true; + // Read frame counters if (ws_pae_controller_nvm_frame_counter_read(&controller->frame_counters) >= 0) { bool updated = false; @@ -610,6 +634,8 @@ static void ws_pae_controller_frame_counter_read(pae_controller_t *controller) if (controller->frame_counters.counter[index].set) { // Increments frame counters controller->frame_counters.counter[index].frame_counter += FRAME_COUNTER_INCREMENT; + controller->frame_counters.counter[index].stored_frame_counter = + controller->frame_counters.counter[index].frame_counter; tr_info("Read frame counter: index %i value %"PRIu32"", index, controller->frame_counters.counter[index].frame_counter); @@ -620,7 +646,6 @@ static void ws_pae_controller_frame_counter_read(pae_controller_t *controller) // Writes incremented frame counters ws_pae_nvm_store_frame_counter_tlv_create(controller->pae_nvm_buffer, &controller->frame_counters); ws_pae_controller_nvm_frame_counter_write(controller->pae_nvm_buffer); - //ws_pae_controller_frame_counter_write(controller, &controller->frame_counters); } } } @@ -630,6 +655,7 @@ static void ws_pae_controller_frame_counter_reset(frame_counters_t *frame_counte for (uint8_t index = 0; index < GTK_NUM; index++) { memset(frame_counters->counter[index].gtk, 0, GTK_LEN); frame_counters->counter[index].frame_counter = 0; + frame_counters->counter[index].stored_frame_counter = 0; frame_counters->counter[index].set = false; } } @@ -653,7 +679,7 @@ int8_t ws_pae_controller_supp_init(protocol_interface_info_entry_t *interface_pt controller->pae_gtk_hash_update = ws_pae_supp_gtk_hash_update; controller->pae_nw_key_index_update = ws_pae_supp_nw_key_index_update; - ws_pae_supp_cb_register(controller->interface_ptr, controller->auth_completed, ws_pae_controller_nw_key_check_and_insert, ws_pae_controller_active_nw_key_set); + ws_pae_supp_cb_register(controller->interface_ptr, controller->auth_completed, ws_pae_controller_nw_key_check_and_insert, ws_pae_controller_active_nw_key_set, ws_pae_controller_gtk_hash_ptr_get); ws_pae_controller_frame_counter_read(controller); @@ -689,11 +715,8 @@ int8_t ws_pae_controller_stop(protocol_interface_info_entry_t *interface_ptr) return -1; } - // Stores frame counter - ws_pae_controller_frame_counter_store(controller, false); - - // Removes network keys from PAE controller and MAC - ws_pae_controller_nw_keys_remove(interface_ptr); + // Stores frame counters and removes network keys from PAE controller and MAC + ws_pae_controller_frame_counter_store_and_nw_keys_remove(interface_ptr, controller, false); // If PAE has been initialized, deletes it if (controller->pae_delete) { @@ -1180,7 +1203,7 @@ int8_t ws_pae_controller_gtk_hash_update(protocol_interface_info_entry_t *interf memcpy(controller->gtkhash, gtkhash, 32); if (controller->pae_gtk_hash_update) { - return controller->pae_gtk_hash_update(interface_ptr, gtkhash); + return controller->pae_gtk_hash_update(interface_ptr, controller->gtkhash); } return 0; @@ -1241,18 +1264,25 @@ static void ws_pae_controller_frame_counter_store(pae_controller_t *entry, bool // If frame counter for the network key has already been stored if (entry->frame_counters.counter[i].set && memcmp(entry->nw_key[i].gtk, entry->frame_counters.counter[i].gtk, GTK_LEN) == 0) { + + if (curr_frame_counter > entry->frame_counters.counter[i].frame_counter) { + entry->frame_counters.counter[i].frame_counter = curr_frame_counter; + } + uint32_t frame_counter = entry->frame_counters.counter[i].frame_counter; + // If threshold check is disabled or frame counter has advanced for the threshold value, stores the new value if (!use_threshold || - curr_frame_counter > entry->frame_counters.counter[i].frame_counter + FRAME_COUNTER_STORE_THRESHOLD) { - entry->frame_counters.counter[i].frame_counter = curr_frame_counter; + frame_counter > entry->frame_counters.counter[i].stored_frame_counter + FRAME_COUNTER_STORE_THRESHOLD) { + entry->frame_counters.counter[i].stored_frame_counter = frame_counter; update_needed = true; - tr_debug("Stored updated frame counter: index %i value %"PRIu32"", i, curr_frame_counter); + tr_debug("Stored updated frame counter: index %i value %"PRIu32"", i, frame_counter); } } else { // For new or modified network keys, stores the frame counter value entry->frame_counters.counter[i].set = true; memcpy(entry->frame_counters.counter[i].gtk, entry->nw_key[i].gtk, GTK_LEN); entry->frame_counters.counter[i].frame_counter = curr_frame_counter; + entry->frame_counters.counter[i].stored_frame_counter = curr_frame_counter; update_needed = true; tr_debug("Stored new frame counter: index %i value %"PRIu32"", i, curr_frame_counter); } diff --git a/source/6LoWPAN/ws/ws_pae_lib.c b/source/6LoWPAN/ws/ws_pae_lib.c index 22d95b8086..455ba76f64 100644 --- a/source/6LoWPAN/ws/ws_pae_lib.c +++ b/source/6LoWPAN/ws/ws_pae_lib.c @@ -291,6 +291,20 @@ void ws_pae_lib_supp_timer_ticks_set(supp_entry_t *entry, uint32_t ticks) entry->ticks = ticks; } +void ws_pae_lib_supp_timer_ticks_add(supp_entry_t *entry, uint32_t ticks) +{ + entry->ticks += ticks; +} + +bool ws_pae_lib_supp_timer_is_running(supp_entry_t *entry) +{ + if (entry->ticks == 0) { + return false; + } + + return true; +} + void ws_pae_lib_supp_list_to_active(supp_list_t *active_supp_list, supp_list_t *inactive_supp_list, supp_entry_t *entry) { if (entry->active) { diff --git a/source/6LoWPAN/ws/ws_pae_lib.h b/source/6LoWPAN/ws/ws_pae_lib.h index 90ba148126..3ee6f10d0f 100644 --- a/source/6LoWPAN/ws/ws_pae_lib.h +++ b/source/6LoWPAN/ws/ws_pae_lib.h @@ -272,6 +272,25 @@ void ws_pae_lib_supp_delete(supp_entry_t *entry); */ void ws_pae_lib_supp_timer_ticks_set(supp_entry_t *entry, uint32_t ticks); +/** + * ws_pae_lib_supp_timer_ticks_add adds supplicant timer ticks + * + * \param entry supplicant entry + * \param ticks ticks + * + */ +void ws_pae_lib_supp_timer_ticks_add(supp_entry_t *entry, uint32_t ticks); + +/** + * ws_pae_lib_supp_timer_is_running checks whether supplicant timer is running + * + * \param entry supplicant entry + * + * \return TRUE timer is running, FALSE timer is not running + * + */ +bool ws_pae_lib_supp_timer_is_running(supp_entry_t *entry); + /** * ws_pae_lib_supp_list_to_active move supplicant to active supplicants list * diff --git a/source/6LoWPAN/ws/ws_pae_nvm_data.c b/source/6LoWPAN/ws/ws_pae_nvm_data.c index d7f2d23861..7f833430a6 100644 --- a/source/6LoWPAN/ws/ws_pae_nvm_data.c +++ b/source/6LoWPAN/ws/ws_pae_nvm_data.c @@ -57,7 +57,7 @@ nvm_tlv_entry_t *ws_pae_buffer_allocate(void) void ws_pae_nvm_store_nw_info_tlv_create(nvm_tlv_entry_t *tlv_entry, uint16_t pan_id, char *nw_name, sec_prot_gtk_keys_t *gtks) { - + int len; tlv_entry->tag = PAE_NVM_NW_INFO_TAG; tlv_entry->len = PAE_NVM_NW_INFO_LEN; @@ -66,7 +66,13 @@ void ws_pae_nvm_store_nw_info_tlv_create(nvm_tlv_entry_t *tlv_entry, uint16_t pa tlv = common_write_16_bit(pan_id, tlv); memset(tlv, 0, 33); - strncpy((char *)tlv, nw_name, 32); + // use strnlen & memset instead of strncpy to avoid gcc warning: + // call to __builtin___strncpy_chk will always overflow destination buffer [-Werror] + len = strlen(nw_name); + if (len > 32) { + len = 32; + } + memcpy((char *)tlv, nw_name, len); tlv += 33; for (uint8_t i = 0; i < GTK_NUM; i++) { diff --git a/source/6LoWPAN/ws/ws_pae_supp.c b/source/6LoWPAN/ws/ws_pae_supp.c index 452f5993ae..db891dc6e4 100644 --- a/source/6LoWPAN/ws/ws_pae_supp.c +++ b/source/6LoWPAN/ws/ws_pae_supp.c @@ -66,6 +66,9 @@ // Wait for re-authentication after GTK update #define WAIT_FOR_REAUTHENTICATION_TICKS 120 * 10 // 120 seconds +// Ticks added to wait for authenticator timer when authentication protocol is started (e.g. EAP-TLS) +#define START_AUTHENTICATION_TICKS 5 * 10 // 10 seconds + // How many times in maximum stored keys are used for authentication #define STORED_KEYS_MAXIMUM_USE_COUNT 1 @@ -88,9 +91,11 @@ typedef struct { ws_pae_supp_auth_completed *auth_completed; /**< Authentication completed callback, continue bootstrap */ ws_pae_supp_nw_key_insert *nw_key_insert; /**< Key insert callback */ ws_pae_supp_nw_key_index_set *nw_key_index_set; /**< Key index set callback */ + ws_pae_supp_gtk_hash_ptr_get *gtk_hash_ptr_get; /**< Get pointer to GTK hash storage callback */ supp_entry_t entry; /**< Supplicant data */ kmp_addr_t target_addr; /**< EAPOL target (parent) address */ uint16_t initial_key_timer; /**< Timer to trigger initial EAPOL-Key */ + uint16_t initial_key_retry_timer; /**< Timer to trigger initial EAPOL-Key 1st retry */ trickle_t auth_trickle_timer; /**< Trickle timer for re-sending initial EAPOL-key or for GTK mismatch */ trickle_params_t auth_trickle_params; /**< Trickle parameters for initial EAPOL-key or for GTK mismatch */ sec_prot_gtk_keys_t gtks; /**< GTKs */ @@ -98,6 +103,7 @@ typedef struct { sec_prot_keys_nw_info_t sec_keys_nw_info; /**< Security keys network information */ timer_settings_t *timer_settings; /**< Timer settings */ uint8_t nw_keys_used_cnt; /**< How many times bootstrap has been tried with current keys */ + uint8_t initial_key_retry_cnt; /**< initial EAPOL-Key retry counter */ bool auth_trickle_running : 1; /**< Initial EAPOL-Key Trickle timer running */ bool auth_requested : 1; /**< Authentication has been requested by the bootstrap */ bool timer_running : 1; /**< Timer is running */ @@ -106,14 +112,34 @@ typedef struct { bool entry_address_active: 1; } pae_supp_t; +// How many times sending of initial EAPOL-key is retried +#define INITIAL_KEY_RETRY_COUNT 2 -#define TRICKLE_IMIN_180_SECS 180 +// How many times sending of initial EAPOL-key is initiated on key update +#define KEY_UPDATE_RETRY_COUNT 3 +#define LIFETIME_MISMATCH_RETRY_COUNT 1 /* No retries */ + +// How long the wait is before the first initial EAPOL-key retry +#define DEFAULT_INITIAL_KEY_RETRY_TIMER 120 +#define NONE_INITIAL_KEY_RETRY_TIMER 0 + +// Default trickle values for sending of initial EAPOL-key +#define DEFAULT_TRICKLE_IMIN_SECS 360 /* 6 to 12 minutes */ +#define DEFAULT_TRICKLE_IMAX_SECS 720 + +// Very slow network values for sending of initial EAPOL-key +#define VERY_SLOW_NW_TRICKLE_IMIN_SECS 600 /* 10 to 60 minutes */ +#define VERY_SLOW_NW_TRICKLE_IMAX_SECS 3600 + +// Trickle timer on how long to wait response after last retry before failing authentication +#define LAST_INTERVAL_TRICKLE_IMIN_SECS 240 /* 4 minutes */ +#define LAST_INTERVAL_TRICKLE_IMAX_SECS 240 static trickle_params_t initial_eapol_key_trickle_params = { - .Imin = TRICKLE_IMIN_180_SECS, /* 180 second; ticks are 1 second */ - .Imax = TRICKLE_IMIN_180_SECS << 1, /* 360 second */ - .k = 0, /* infinity - no consistency checking */ - .TimerExpirations = 3 + .Imin = DEFAULT_TRICKLE_IMIN_SECS, /* 360 second; ticks are 1 second */ + .Imax = DEFAULT_TRICKLE_IMAX_SECS, /* 720 second */ + .k = 0, /* infinity - no consistency checking */ + .TimerExpirations = 2 }; static void ws_pae_supp_free(pae_supp_t *pae_supp); @@ -126,6 +152,10 @@ static int8_t ws_pae_supp_nvm_keys_write(pae_supp_t *pae_supp); static pae_supp_t *ws_pae_supp_get(protocol_interface_info_entry_t *interface_ptr); static int8_t ws_pae_supp_event_send(kmp_service_t *service, void *data); static void ws_pae_supp_tasklet_handler(arm_event_s *event); +static void ws_pae_supp_initial_trickle_timer_start(pae_supp_t *pae_supp); +static void ws_pae_supp_initial_last_interval_trickle_timer_start(pae_supp_t *pae_supp); +static void ws_pae_supp_initial_key_update_trickle_timer_start(pae_supp_t *pae_supp, uint8_t timer_expirations); +static bool ws_pae_supp_authentication_ongoing(pae_supp_t *pae_supp); static int8_t ws_pae_supp_timer_if_start(kmp_service_t *service, kmp_api_t *kmp); static int8_t ws_pae_supp_timer_if_stop(kmp_service_t *service, kmp_api_t *kmp); static int8_t ws_pae_supp_timer_start(pae_supp_t *pae_supp); @@ -138,6 +168,7 @@ static kmp_api_t *ws_pae_supp_kmp_tx_status_ind(kmp_service_t *service, uint8_t static kmp_api_t *ws_pae_supp_kmp_create_and_start(kmp_service_t *service, kmp_type_e type, pae_supp_t *pae_supp); static int8_t ws_pae_supp_eapol_pdu_address_check(protocol_interface_info_entry_t *interface_ptr, const uint8_t *eui_64); static int8_t ws_pae_supp_parent_eui_64_get(protocol_interface_info_entry_t *interface_ptr, uint8_t *eui_64); +static int8_t ws_pae_supp_gtk_hash_mismatch_check(pae_supp_t *pae_supp); static void ws_pae_supp_kmp_api_create_confirm(kmp_api_t *kmp, kmp_result_e result); static void ws_pae_supp_kmp_api_create_indication(kmp_api_t *kmp, kmp_type_e type, kmp_addr_t *addr); @@ -156,6 +187,7 @@ static const char *KEYS_FILE = KEYS_FILE_NAME; static int8_t tasklet_id = -1; static NS_LIST_DEFINE(pae_supp_list, pae_supp_t, link); +static uint8_t timing_value = 0; // Timing value set based e.g. on network size static void ws_pae_supp_address_set(pae_supp_t *pae_supp, kmp_addr_t *address) { @@ -291,6 +323,23 @@ int8_t ws_pae_supp_nw_key_valid(protocol_interface_info_entry_t *interface_ptr) return 0; } +static int8_t ws_pae_supp_gtk_hash_mismatch_check(pae_supp_t *pae_supp) +{ + uint8_t *gtkhash = pae_supp->gtk_hash_ptr_get(pae_supp->interface_ptr); + if (!gtkhash) { + return -1; + } + + // Check GTK hashes and initiate EAPOL procedure if mismatch is detected */ + gtk_mismatch_e mismatch = sec_prot_keys_gtks_hash_update(&pae_supp->gtks, gtkhash); + if (mismatch != GTK_NO_MISMATCH) { + return -1; + } + + tr_info("GTKs match to GTK hash"); + return 0; +} + int8_t ws_pae_supp_gtk_hash_update(protocol_interface_info_entry_t *interface_ptr, uint8_t *gtkhash) { pae_supp_t *pae_supp = ws_pae_supp_get(interface_ptr); @@ -307,30 +356,21 @@ int8_t ws_pae_supp_gtk_hash_update(protocol_interface_info_entry_t *interface_pt trace_array(>khash[16], 8), trace_array(>khash[24], 8)); - // Mismatch, initiate EAPOL - if (!pae_supp->auth_trickle_running) { - uint8_t timer_expirations = 3; + /* Mismatch, initiate EAPOL (if authentication not already ongoing or if not on + wait time for the authenticator to answer) */ + if (!pae_supp->auth_trickle_running || pae_supp->initial_key_retry_cnt == 0) { + uint8_t timer_expirations = KEY_UPDATE_RETRY_COUNT; // For GTK lifetime mismatch send only once if (mismatch == GTK_LIFETIME_MISMATCH) { - timer_expirations = 1; + timer_expirations = LIFETIME_MISMATCH_RETRY_COUNT; } - - pae_supp->auth_trickle_params.Imin = pae_supp->timer_settings->gtk_request_imin; - pae_supp->auth_trickle_params.Imax = pae_supp->timer_settings->gtk_request_imax; - pae_supp->auth_trickle_params.k = 0; - pae_supp->auth_trickle_params.TimerExpirations = timer_expirations; - - // Starts trickle - trickle_start(&pae_supp->auth_trickle_timer, &pae_supp->auth_trickle_params); - pae_supp->auth_trickle_running = true; + // Start trickle timer + ws_pae_supp_initial_key_update_trickle_timer_start(pae_supp, timer_expirations); // Starts supplicant timer ws_pae_supp_timer_start(pae_supp); tr_info("GTK update start imin: %i, imax: %i, max mismatch: %i, tr time: %i", pae_supp->timer_settings->gtk_request_imin, pae_supp->timer_settings->gtk_request_imax, pae_supp->timer_settings->gtk_max_mismatch, pae_supp->auth_trickle_timer.t); - } else { - // If trickle is already running, set inconsistent heard to speed up the trickle - trickle_inconsistent_heard(&pae_supp->auth_trickle_timer, &pae_supp->auth_trickle_params); } } @@ -565,7 +605,7 @@ static void ws_pae_supp_keys_nw_info_init(sec_prot_keys_nw_info_t *sec_keys_nw_i sec_keys_nw_info->updated = false; } -void ws_pae_supp_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_supp_auth_completed *completed, ws_pae_supp_nw_key_insert *nw_key_insert, ws_pae_supp_nw_key_index_set *nw_key_index_set) +void ws_pae_supp_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_supp_auth_completed *completed, ws_pae_supp_nw_key_insert *nw_key_insert, ws_pae_supp_nw_key_index_set *nw_key_index_set, ws_pae_supp_gtk_hash_ptr_get *gtk_hash_ptr_get) { pae_supp_t *pae_supp = ws_pae_supp_get(interface_ptr); if (!pae_supp) { @@ -575,6 +615,7 @@ void ws_pae_supp_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_ pae_supp->auth_completed = completed; pae_supp->nw_key_insert = nw_key_insert; pae_supp->nw_key_index_set = nw_key_index_set; + pae_supp->gtk_hash_ptr_get = gtk_hash_ptr_get; } int8_t ws_pae_supp_init(protocol_interface_info_entry_t *interface_ptr, const sec_prot_certs_t *certs, timer_settings_t *timer_settings) @@ -596,9 +637,12 @@ int8_t ws_pae_supp_init(protocol_interface_info_entry_t *interface_ptr, const se pae_supp->auth_completed = NULL; pae_supp->nw_key_insert = NULL; pae_supp->nw_key_index_set = NULL; + pae_supp->gtk_hash_ptr_get = NULL; pae_supp->initial_key_timer = 0; + pae_supp->initial_key_retry_timer = 0; pae_supp->nw_keys_used_cnt = 0; pae_supp->timer_settings = timer_settings; + pae_supp->initial_key_retry_cnt = INITIAL_KEY_RETRY_COUNT; pae_supp->auth_trickle_running = false; pae_supp->auth_requested = false; pae_supp->timer_running = false; @@ -702,6 +746,7 @@ int8_t ws_pae_supp_delete(protocol_interface_info_entry_t *interface_ptr) int8_t ws_pae_supp_timing_adjust(uint8_t timing) { + timing_value = timing; supp_fwh_sec_prot_timing_adjust(timing); supp_eap_sec_prot_timing_adjust(timing); return 0; @@ -801,7 +846,7 @@ void ws_pae_supp_fast_timer(uint16_t ticks) bool running = ws_pae_lib_supp_timer_update(&pae_supp->entry, ticks, kmp_service_timer_if_timeout); // Checks whether timer needs to be active - if (!pae_supp->initial_key_timer && !pae_supp->auth_trickle_running && !running) { + if (!ws_pae_supp_authentication_ongoing(pae_supp) && !running) { tr_debug("PAE idle"); // If not already completed, restart bootstrap ws_pae_supp_authenticate_response(pae_supp, AUTH_RESULT_ERR_UNSPEC); @@ -811,20 +856,69 @@ void ws_pae_supp_fast_timer(uint16_t ticks) } } +static bool ws_pae_supp_authentication_ongoing(pae_supp_t *pae_supp) +{ + /* When either bootstrap initial authentication or re-authentication is ongoing */ + if (pae_supp->initial_key_timer || pae_supp->auth_trickle_running || + ws_pae_lib_supp_timer_is_running(&pae_supp->entry)) { + return true; + } + + return false; +} + void ws_pae_supp_slow_timer(uint16_t seconds) { ns_list_foreach(pae_supp_t, pae_supp, &pae_supp_list) { // Checks whether initial EAPOL-Key message needs to be re-send or new GTK request to be sent if (pae_supp->auth_trickle_running) { - if (trickle_timer(&pae_supp->auth_trickle_timer, &pae_supp->auth_trickle_params, seconds)) { - if (ws_pae_supp_initial_key_send(pae_supp) < 0) { - tr_info("EAPOL-Key send failed"); + if (pae_supp->initial_key_retry_timer > 0) { + if (pae_supp->initial_key_retry_timer > seconds) { + pae_supp->initial_key_retry_timer -= seconds; + } else { + pae_supp->initial_key_retry_timer = 0; + tr_info("initial key retry timer expired"); + } + } else { + // Checks if trickle timer expires + if (trickle_timer(&pae_supp->auth_trickle_timer, &pae_supp->auth_trickle_params, seconds)) { + if (pae_supp->initial_key_retry_cnt > 0) { + if (ws_pae_supp_initial_key_send(pae_supp) < 0) { + tr_info("EAPOL-Key send failed"); + } + } + + /* Wait time for the authenticator to answer the last re-transmit expires; + fails authentication */ + if (pae_supp->initial_key_retry_cnt == 0) { + bool retry = false; + // If making key update and GTKs do not match to GTK hash + if (!pae_supp->auth_requested && ws_pae_supp_gtk_hash_mismatch_check(pae_supp) < 0) { + tr_info("GTKs do not match to GTK hash"); + retry = true; + } + ws_pae_supp_authenticate_response(pae_supp, AUTH_RESULT_ERR_UNSPEC); + if (retry) { + // Start trickle timer to try re-authentication + ws_pae_supp_initial_key_update_trickle_timer_start(pae_supp, KEY_UPDATE_RETRY_COUNT); + } + } else { + if (pae_supp->initial_key_retry_cnt > 0) { + pae_supp->initial_key_retry_cnt--; + } + if (pae_supp->initial_key_retry_cnt == 0) { + // Starts wait time for the authenticator to answer + tr_info("Initial EAPOL-Key wait for last re-transmit answer"); + ws_pae_supp_initial_last_interval_trickle_timer_start(pae_supp); + } + } + } + + // Sanity check, should be running until authentication failure + if (!trickle_running(&pae_supp->auth_trickle_timer, &pae_supp->auth_trickle_params)) { + ws_pae_supp_authenticate_response(pae_supp, AUTH_RESULT_ERR_UNSPEC); } - } - // Maximum number of trickle expires, authentication fails - if (!trickle_running(&pae_supp->auth_trickle_timer, &pae_supp->auth_trickle_params)) { - ws_pae_supp_authenticate_response(pae_supp, AUTH_RESULT_ERR_UNSPEC); } } @@ -846,16 +940,76 @@ void ws_pae_supp_slow_timer(uint16_t seconds) if (ws_pae_supp_initial_key_send(pae_supp) < 0) { tr_info("EAPOL-Key send failed"); } - - // Starts trickle - pae_supp->auth_trickle_params = initial_eapol_key_trickle_params; - trickle_start(&pae_supp->auth_trickle_timer, &pae_supp->auth_trickle_params); - pae_supp->auth_trickle_running = true; + // Start trickle timer + ws_pae_supp_initial_trickle_timer_start(pae_supp); } } } } +static void ws_pae_supp_initial_trickle_timer_start(pae_supp_t *pae_supp) +{ + pae_supp->auth_trickle_params = initial_eapol_key_trickle_params; + + // Very fast, medium and slow network + if (timing_value < 25) { + /* Starts trickle for initial EAPOL-key. Sequence has fixed delay of 2 minutes, + * one re-transmit interval, last re-transmit interval transmit time and a wait time + * for the authenticator to answer the last re-transmit. + * + * Interval I [6,12] minutes. Sequence: + * + * fixed 2 minutes delay + I + last I transmit time t + wait for answer [2,4] minutes + * + * There are two retries. Minimum time that sequence takes before authentication failure + * is 16 minutes and maximum is 30 minutes. + */ + pae_supp->initial_key_retry_timer = DEFAULT_INITIAL_KEY_RETRY_TIMER; // 2 minutes + } else { + /* Extremely slow network + * + * Starts trickle for initial EAPOL-key, Interval I [10,60] minutes. Sequence: + * I + last I transmit time t + wait for answer [2,4] minutes + * There are two retries. Minimum time that sequence takes before authentication failure + * is 22 minutes and maximum is 124 minutes. + */ + pae_supp->auth_trickle_params.Imin = VERY_SLOW_NW_TRICKLE_IMIN_SECS; + pae_supp->auth_trickle_params.Imax = VERY_SLOW_NW_TRICKLE_IMAX_SECS; + pae_supp->initial_key_retry_timer = NONE_INITIAL_KEY_RETRY_TIMER; // 0 seconds + } + trickle_start(&pae_supp->auth_trickle_timer, &pae_supp->auth_trickle_params); + tr_info("Initial EAPOL-Key trickle I: [%i,%i] %i, t: %i", pae_supp->auth_trickle_params.Imin, pae_supp->auth_trickle_params.Imax, pae_supp->auth_trickle_timer.I, pae_supp->auth_trickle_timer.t); + pae_supp->auth_trickle_running = true; + pae_supp->initial_key_retry_cnt = INITIAL_KEY_RETRY_COUNT; +} + +static void ws_pae_supp_initial_last_interval_trickle_timer_start(pae_supp_t *pae_supp) +{ + // Starts trickle last to wait response after last retry before failing authentication + pae_supp->auth_trickle_params = initial_eapol_key_trickle_params; + pae_supp->auth_trickle_params.Imin = LAST_INTERVAL_TRICKLE_IMIN_SECS; + pae_supp->auth_trickle_params.Imax = LAST_INTERVAL_TRICKLE_IMAX_SECS; + pae_supp->auth_trickle_params.TimerExpirations = 1; + // Set I to [iMin,iMax] (4 to 4 minutes) -> t is [I/2 - I] (2 minutes to 4 minutes) + trickle_start(&pae_supp->auth_trickle_timer, &pae_supp->auth_trickle_params); + tr_info("Initial EAPOL-Key trickle I: [%i,%i] %i, t: %i", pae_supp->auth_trickle_params.Imin, pae_supp->auth_trickle_params.Imax, pae_supp->auth_trickle_timer.I, pae_supp->auth_trickle_timer.t); +} + +static void ws_pae_supp_initial_key_update_trickle_timer_start(pae_supp_t *pae_supp, uint8_t timer_expirations) +{ + // Starts trickle for the key update + pae_supp->auth_trickle_params.Imin = pae_supp->timer_settings->gtk_request_imin; + pae_supp->auth_trickle_params.Imax = pae_supp->timer_settings->gtk_request_imax; + pae_supp->auth_trickle_params.k = 0; + pae_supp->auth_trickle_params.TimerExpirations = timer_expirations; + + trickle_start(&pae_supp->auth_trickle_timer, &pae_supp->auth_trickle_params); + tr_info("Initial EAPOL-Key trickle I: [%i,%i] %i, t: %i", pae_supp->auth_trickle_params.Imin, pae_supp->auth_trickle_params.Imax, pae_supp->auth_trickle_timer.I, pae_supp->auth_trickle_timer.t); + pae_supp->initial_key_retry_timer = NONE_INITIAL_KEY_RETRY_TIMER; // 0 seconds + pae_supp->auth_trickle_running = true; + pae_supp->initial_key_retry_cnt = timer_expirations; +} + static int8_t ws_pae_supp_timer_if_start(kmp_service_t *service, kmp_api_t *kmp) { pae_supp_t *pae_supp = ws_pae_supp_by_kmp_service_get(service); @@ -947,7 +1101,7 @@ static int8_t ws_pae_supp_parent_eui_64_get(protocol_interface_info_entry_t *int const uint8_t *parent_ll_addr = rpl_control_preferred_parent_addr(instance, false); if (parent_ll_addr) { memcpy(eui_64, &parent_ll_addr[8], 8); - eui_64[0] |= 0x02; + eui_64[0] ^= 0x02; return 0; } } @@ -1014,14 +1168,13 @@ static kmp_api_t *ws_pae_supp_kmp_incoming_ind(kmp_service_t *service, kmp_type_ return NULL; } - if (!pae_supp->entry_address_active) { + // If target address is not set or authentication is not ongoing + if (!pae_supp->entry_address_active || !ws_pae_supp_authentication_ongoing(pae_supp)) { + tr_info("Incoming KMP rejected, auth not ongoing, type: %i ", type); // Does no longer wait for authentication, ignores message return NULL; } - // No longer runs trickle timer for re-sending initial EAPOL-key - pae_supp->auth_trickle_running = false; - // Updates parent address kmp_address_copy(&pae_supp->entry.addr, addr); @@ -1040,6 +1193,9 @@ static kmp_api_t *ws_pae_supp_kmp_incoming_ind(kmp_service_t *service, kmp_type_ // Create new instance kmp = ws_pae_supp_kmp_create_and_start(service, type, pae_supp); + // Adds ticks to wait for authenticator to continue timer + ws_pae_lib_supp_timer_ticks_add(&pae_supp->entry, START_AUTHENTICATION_TICKS); + // For EAP-TLS create also TLS in addition to EAP-TLS if (type == IEEE_802_1X_MKA) { if (ws_pae_lib_kmp_list_type_get(&pae_supp->entry.kmp_list, TLS_PROT) != NULL) { @@ -1112,6 +1268,15 @@ static void ws_pae_supp_kmp_api_create_indication(kmp_api_t *kmp, kmp_type_e typ (void) addr; (void) type; + kmp_service_t *service = kmp_api_service_get(kmp); + pae_supp_t *pae_supp = ws_pae_supp_by_kmp_service_get(service); + if (!pae_supp) { + return; + } + + // Incoming KMP protocol has started, no longer runs trickle timer for re-sending EAPOL-key message + pae_supp->auth_trickle_running = false; + // For now, accept every KMP-CREATE.indication kmp_api_create_response(kmp, KMP_RESULT_OK); } @@ -1148,7 +1313,6 @@ static void ws_pae_supp_kmp_api_finished_indication(kmp_api_t *kmp, kmp_result_e tr_info("Initial EAPOL-Key TX failure, target: %s", trace_array(kmp_address_eui_64_get(&pae_supp->entry.addr), 8)); ws_pae_supp_authenticate_response(pae_supp, AUTH_RESULT_ERR_TX_NO_ACK); } - } static void ws_pae_supp_kmp_api_finished(kmp_api_t *kmp) diff --git a/source/6LoWPAN/ws/ws_pae_supp.h b/source/6LoWPAN/ws/ws_pae_supp.h index bc8fc0f011..458ed7bf9e 100644 --- a/source/6LoWPAN/ws/ws_pae_supp.h +++ b/source/6LoWPAN/ws/ws_pae_supp.h @@ -236,6 +236,16 @@ typedef void ws_pae_supp_auth_completed(protocol_interface_info_entry_t *interfa */ typedef int8_t ws_pae_supp_nw_key_insert(protocol_interface_info_entry_t *interface_ptr, sec_prot_gtk_keys_t *gtks); +/** + * ws_pae_supp_gtk_hash_ptr_get get pointer to GTK hash storage callback + * + * \param interface_ptr interface + * + * \return pointer to GTK has storage or NULL + * + */ +typedef uint8_t *ws_pae_supp_gtk_hash_ptr_get(protocol_interface_info_entry_t *interface_ptr); + /** * ws_pae_supp_cb_register register PEA supplicant callbacks * @@ -245,7 +255,7 @@ typedef int8_t ws_pae_supp_nw_key_insert(protocol_interface_info_entry_t *interf * \param nw_key_index_set network send key index callback * */ -void ws_pae_supp_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_supp_auth_completed *completed, ws_pae_supp_nw_key_insert *nw_key_insert, ws_pae_supp_nw_key_index_set *nw_key_index_set); +void ws_pae_supp_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_pae_supp_auth_completed *completed, ws_pae_supp_nw_key_insert *nw_key_insert, ws_pae_supp_nw_key_index_set *nw_key_index_set, ws_pae_supp_gtk_hash_ptr_get *gtk_hash_ptr_get); #else diff --git a/source/Common_Protocols/icmpv6.c b/source/Common_Protocols/icmpv6.c index 5222fde768..f0b3dc59ea 100644 --- a/source/Common_Protocols/icmpv6.c +++ b/source/Common_Protocols/icmpv6.c @@ -356,7 +356,7 @@ static void icmpv6_na_wisun_aro_handler(protocol_interface_info_entry_t *cur_int (void)life_time; if (nd_status != ARO_SUCCESS) { - ws_common_aro_failure(cur_interface, src_addr, true); + ws_common_aro_failure(cur_interface, src_addr); } } @@ -1389,7 +1389,7 @@ static void icmpv6_aro_cb(buffer_t *buf, uint8_t status) } rpl_control_address_register_done(buf->interface, ll_address, status); if (status != SOCKET_TX_DONE) { - ws_common_aro_failure(buf->interface, ll_address, false); + ws_common_aro_failure(buf->interface, ll_address); } } @@ -1697,7 +1697,7 @@ buffer_t *icmpv6_build_na(protocol_interface_info_entry_t *cur, bool solicited, memcpy(ptr, aro->eui64, 8); ptr += 8; } - if (ws_info(cur) && aro && aro->status != ARO_SUCCESS) { + if (ws_info(cur) && aro && (aro->status != ARO_SUCCESS && aro->status != ARO_TOPOLOGICALLY_INCORRECT)) { /*If Aro failed we will kill the neigbour after we have succeeded in sending message*/ if (!ws_common_negative_aro_mark(cur, aro->eui64)) { tr_debug("Neighbour removed for negative response send"); @@ -1713,7 +1713,7 @@ buffer_t *icmpv6_build_na(protocol_interface_info_entry_t *cur, bool solicited, buf->info = (buffer_info_t)(B_DIR_DOWN | B_FROM_ICMP | B_TO_ICMP); buf->interface = cur; - tr_debug("Build NA"); + tr_info("Build NA"); return (buf); } diff --git a/source/Common_Protocols/icmpv6.h b/source/Common_Protocols/icmpv6.h index c209e2af42..3ae2aa14ed 100644 --- a/source/Common_Protocols/icmpv6.h +++ b/source/Common_Protocols/icmpv6.h @@ -117,6 +117,7 @@ typedef enum slaac_src { #define ARO_SUCCESS 0 #define ARO_DUPLICATE 1 #define ARO_FULL 2 +#define ARO_TOPOLOGICALLY_INCORRECT 8 extern void icmpv6_init(void); extern struct buffer *icmpv6_down(struct buffer *buf); diff --git a/source/Common_Protocols/icmpv6_radv.c b/source/Common_Protocols/icmpv6_radv.c index fff4edec98..446d05f38e 100644 --- a/source/Common_Protocols/icmpv6_radv.c +++ b/source/Common_Protocols/icmpv6_radv.c @@ -325,6 +325,9 @@ void icmpv6_stop_router_advertisements(protocol_interface_info_entry_t *cur, con */ static void icmpv6_send_ra(protocol_interface_info_entry_t *cur, const uint8_t *dest, const uint8_t *abro) { +#ifndef HAVE_RPL + (void) abro; +#endif if (cur->nwk_id == IF_6LoWPAN) { nd_ra_build_by_abro(abro, dest, cur); } else { diff --git a/source/Common_Protocols/ipv6.c b/source/Common_Protocols/ipv6.c index fe3102591d..11df4aafa4 100644 --- a/source/Common_Protocols/ipv6.c +++ b/source/Common_Protocols/ipv6.c @@ -773,6 +773,9 @@ drop: static buffer_t *ipv6_handle_options(buffer_t *buf, protocol_interface_info_entry_t *cur, uint8_t *ptr, uint8_t nh, uint16_t payload_length, uint16_t *hdrlen_out, const sockaddr_t *ll_src, bool pre_fragment) { (void) nh; +#ifndef HAVE_RPL + (void) ll_src; +#endif if (payload_length < 2) { return icmpv6_error(buf, cur, ICMPV6_TYPE_ERROR_PARAMETER_PROBLEM, ICMPV6_CODE_PARAM_PRB_HDR_ERR, 4); } @@ -853,6 +856,9 @@ len_err: static buffer_t *ipv6_handle_routing_header(buffer_t *buf, protocol_interface_info_entry_t *cur, uint8_t *ptr, uint16_t payload_length, uint16_t *hdrlen_out, bool *forward_out, bool pre_fragment) { +#ifndef HAVE_RPL + (void) forward_out; +#endif if (buf->options.ll_security_bypass_rx) { tr_warn("Routing header: Security check fail"); protocol_stats_update(STATS_IP_RX_DROP, 1); diff --git a/source/Core/buffer_dyn.c b/source/Core/buffer_dyn.c index 1b34e64997..268ee815ab 100644 --- a/source/Core/buffer_dyn.c +++ b/source/Core/buffer_dyn.c @@ -16,7 +16,8 @@ */ #include "nsconfig.h" -#include "string.h" +#include +#include #include "ns_types.h" #include "nsdynmemLIB.h" #include "Core/include/ns_address_internal.h" @@ -30,6 +31,13 @@ #define TRACE_GROUP "buff" +// Get module working also on 16-bit platform +#if INT_MAX < 0xFFFF +#define BUFFER_MAX_SIZE ((size_t)INT_MAX) +#else +#define BUFFER_MAX_SIZE ((size_t)0xFFFF) +#endif + volatile unsigned int buffer_count = 0; uint8_t *(buffer_corrupt_check)(buffer_t *buf) @@ -38,15 +46,12 @@ uint8_t *(buffer_corrupt_check)(buffer_t *buf) return NULL; } - if (buf->buf_ptr > buf->buf_end) { - tr_error("Buffer pointer end not set"); - } else if (buffer_data_length(buf) < 0) { - tr_error("Buffer length overflow"); - while (1); - } else if (buf->buf_end > buf->size || buf->buf_ptr > buf->size) { - tr_error("buffer pointer overridden"); + if (buf->buf_ptr > buf->buf_end || buf->buf_end > buf->size) { + tr_error("Invalid buffer, size=%"PRIu16", buf_ptr=%"PRIu16", buf_end=%"PRIu16"", buf->size, buf->buf_ptr, buf->buf_end); + tr_error("Data: %s", tr_array(buffer_data_pointer(buf), 56)); while (1); } + return buffer_data_pointer(buf); } @@ -71,8 +76,8 @@ buffer_t *buffer_get_minimal(uint16_t size) */ buffer_t *buffer_get_specific(uint16_t headroom, uint16_t size, uint16_t minspace) { - buffer_t *buf; - uint16_t total_size; + buffer_t *buf = NULL; + uint32_t total_size; total_size = headroom + size; if (total_size < minspace) { @@ -83,10 +88,12 @@ buffer_t *buffer_get_specific(uint16_t headroom, uint16_t size, uint16_t minspac * anyway be this much aligned. */ total_size = (total_size + 3) & ~ 3; - // Note - as well as this alloc+init, buffers can also be "realloced" - // in buffer_headroom() + if (total_size <= BUFFER_MAX_SIZE) { + // Note - as well as this alloc+init, buffers can also be "realloced" + // in buffer_headroom() + buf = ns_dyn_mem_temporary_alloc(sizeof(buffer_t) + total_size); + } - buf = ns_dyn_mem_temporary_alloc(sizeof(buffer_t) + total_size); if (buf) { platform_enter_critical(); buffer_count++; @@ -110,7 +117,7 @@ buffer_t *buffer_get_specific(uint16_t headroom, uint16_t size, uint16_t minspac #endif buf->size = total_size; } else { - tr_error("buffer_get failed: alloc(%d)", (int) sizeof(buffer_t) + total_size); + tr_error("buffer_get failed: alloc(%"PRIu32")", (uint32_t)(sizeof(buffer_t) + total_size)); } protocol_stats_update(STATS_BUFFER_ALLOC, 1); @@ -130,10 +137,14 @@ buffer_t *buffer_headroom(buffer_t *buf, uint16_t size) uint16_t curr_len = buffer_data_length(buf); if (buf->size < (curr_len + size)) { + buffer_t *restrict new_buf = NULL; /* This buffer isn't big enough at all - allocate a new block */ // TODO - should we be giving them extra? probably - uint16_t new_total = (curr_len + size + 3) & ~ 3; - buffer_t *restrict new_buf = ns_dyn_mem_temporary_alloc(sizeof(buffer_t) + new_total); + uint32_t new_total = (curr_len + size + 3) & ~ 3; + if (new_total <= BUFFER_MAX_SIZE) { + new_buf = ns_dyn_mem_temporary_alloc(sizeof(buffer_t) + new_total); + } + if (new_buf) { // Copy the buffer_t header *new_buf = *buf; diff --git a/source/Core/include/ns_buffer.h b/source/Core/include/ns_buffer.h index 7ebb6e0545..b33148a14d 100644 --- a/source/Core/include/ns_buffer.h +++ b/source/Core/include/ns_buffer.h @@ -322,7 +322,7 @@ struct socket *buffer_socket_set(buffer_t *buf, struct socket *socket); } while(0) /** get data length*/ -#define buffer_data_length(x) (int16_t)(x->buf_end - x->buf_ptr) +#define buffer_data_length(x) (int)(x->buf_end - x->buf_ptr) /** get data length Set*/ #define buffer_data_length_set(x,z) ((x)->buf_end = (x)->buf_ptr + (z)) diff --git a/source/Core/ns_socket.c b/source/Core/ns_socket.c index 24f7738c6f..05961ccb5b 100644 --- a/source/Core/ns_socket.c +++ b/source/Core/ns_socket.c @@ -287,14 +287,16 @@ void socket_release(socket_t *socket) if (tcp_info(socket->inet_pcb)) { /* This may trigger a reset if pending data. Do it first so you * get just the reset, rather than a FIN. */ - tcp_session_shutdown_read(tcp_info(socket->inet_pcb)); + tcp_error sock_status = tcp_session_shutdown_read(tcp_info(socket->inet_pcb)); /* This can also cause TCP deletion */ if (tcp_info(socket->inet_pcb)) { - tcp_session_close(tcp_info(socket->inet_pcb)); + sock_status = tcp_session_close(tcp_info(socket->inet_pcb)); } if (tcp_info(socket->inet_pcb)) { tcp_socket_released(tcp_info(socket->inet_pcb)); } + // prevent warning "statement with no effect" when TCP is disabled + (void) sock_status; } else { /* Unbind the internet control block - ensures users are not prevented * from binding a new socket to the same port if the socket lingers @@ -1362,8 +1364,10 @@ int16_t socket_buffer_sendmsg(int8_t sid, buffer_t *buf, const struct ns_msghdr protocol_push(buf); +#ifndef NO_TCP /* TCP jumps back to here */ success: +#endif if (flags & NS_MSG_LEGACY0) { return 0; } else { diff --git a/source/DHCPv6_Server/DHCPv6_Server_service.c b/source/DHCPv6_Server/DHCPv6_Server_service.c index bd606db11f..a7755034a9 100644 --- a/source/DHCPv6_Server/DHCPv6_Server_service.c +++ b/source/DHCPv6_Server/DHCPv6_Server_service.c @@ -87,7 +87,7 @@ static void DHCP_server_service_timer_stop(void) int DHCPv6_server_respond_client(dhcpv6_gua_server_entry_s *serverBase, dhcpv6_reply_packet_s *replyPacket, dhcp_ia_non_temporal_params_t *dhcp_ia_non_temporal_params, dhcpv6_gua_response_t *response, bool allocateNew) { - dhcpv6_alloacted_address_entry_t *dhcp_allocated_address; + dhcpv6_allocated_address_t *dhcp_allocated_address = NULL; dhcpv6_ia_non_temporal_address_s nonTemporalAddress; bool address_allocated = false; //Validate Client DUID @@ -279,12 +279,15 @@ void DHCPv6_server_service_delete(int8_t interface, uint8_t guaPrefix[static 8], { dhcpv6_gua_server_entry_s *serverInfo = libdhcpv6_server_data_get_by_prefix_and_interfaceid(interface, guaPrefix); if (serverInfo) { - ns_list_foreach_safe(dhcpv6_alloacted_address_entry_t, cur, &serverInfo->allocatedAddressList) { + ns_list_foreach_safe(dhcpv6_allocated_address_entry_t, cur, &serverInfo->allocatedAddressList) { //Delete Server data base if (serverInfo->removeCb) { - serverInfo->removeCb(interface, cur->nonTemporalAddress, NULL); + uint8_t allocated_address[16]; + libdhcpv6_allocated_address_write(allocated_address, cur, serverInfo); + serverInfo->removeCb(interface, allocated_address, NULL); } } + if (serverInfo->removeCb) { // Clean all /128 'Thread Proxy' routes to self and others added when acting as a DHCP server serverInfo->removeCb(interface, NULL, serverInfo->guaPrefix); @@ -312,18 +315,22 @@ void DHCPv6_server_service_delete(int8_t interface, uint8_t guaPrefix[static 8], * /param guaPrefix Prefix which will be removed * /param mode true trig autonous mode, false define address by default suffics + client id */ -int DHCPv6_server_service_set_address_autonous_flag(int8_t interface, uint8_t guaPrefix[static 16], bool mode) +int DHCPv6_server_service_set_address_autonous_flag(int8_t interface, uint8_t guaPrefix[static 16], bool mode, bool autonomous_skip_list) { - int retVal = -1; - dhcpv6_gua_server_entry_s *serverInfo; + dhcpv6_gua_server_entry_s *serverInfo = libdhcpv6_server_data_get_by_prefix_and_interfaceid(interface, guaPrefix); + if (!serverInfo) { + return -1; - serverInfo = libdhcpv6_server_data_get_by_prefix_and_interfaceid(interface, guaPrefix); - if (serverInfo) { - serverInfo->enableAddressAutonous = mode; - retVal = 0; } - return retVal; + serverInfo->enableAddressAutonous = mode; + if (mode) { + serverInfo->disableAddressListAllocation = autonomous_skip_list; + } else { + serverInfo->disableAddressListAllocation = false; + } + + return 0; } void DHCPv6_server_service_callback_set(int8_t interface, uint8_t guaPrefix[static 16], dhcp_address_prefer_remove_cb *remove_cb, dhcp_address_add_notify_cb *add_cb) @@ -365,18 +372,18 @@ int DHCPv6_server_service_duid_update(int8_t interface, uint8_t guaPrefix[static */ int DHCPv6_server_service_set_max_clients_accepts_count(int8_t interface, uint8_t guaPrefix[static 16], uint32_t maxClientCount) { - int retVal = -1; dhcpv6_gua_server_entry_s *serverInfo; - if (maxClientCount == 0) { + if (maxClientCount == 0 || maxClientCount > MAX_SUPPORTED_ADDRESS_LIST_SIZE) { return -2; - } else { - serverInfo = libdhcpv6_server_data_get_by_prefix_and_interfaceid(interface, guaPrefix); - if (serverInfo) { - serverInfo->maxSuppertedClients = maxClientCount; - retVal = 0; - } } - return retVal; + serverInfo = libdhcpv6_server_data_get_by_prefix_and_interfaceid(interface, guaPrefix); + if (!serverInfo) { + return -1; + } + + serverInfo->maxSupportedClients = maxClientCount; + + return 0; } /** SET Address Valid Lifetime parameter for allocated address, Default is 7200 seconds @@ -388,18 +395,17 @@ int DHCPv6_server_service_set_max_clients_accepts_count(int8_t interface, uint8_ */ int DHCPv6_server_service_set_address_validlifetime(int8_t interface, uint8_t guaPrefix[static 16], uint32_t validLifeTimne) { - int retVal = -1; dhcpv6_gua_server_entry_s *serverInfo; if (validLifeTimne < 120) { - retVal = -2; - } else { - serverInfo = libdhcpv6_server_data_get_by_prefix_and_interfaceid(interface, guaPrefix); - if (serverInfo) { - serverInfo->validLifetime = validLifeTimne; - retVal = 0; - } + return -2; } - return retVal; + serverInfo = libdhcpv6_server_data_get_by_prefix_and_interfaceid(interface, guaPrefix); + if (!serverInfo) { + return -1; + } + serverInfo->validLifetime = validLifeTimne; + + return 0; } #else @@ -422,11 +428,12 @@ void DHCPv6_server_service_timeout_cb(uint32_t timeUpdateInSeconds) { (void) timeUpdateInSeconds; } -int DHCPv6_server_service_set_address_autonous_flag(int8_t interface, uint8_t guaPrefix[static 16], bool mode) +int DHCPv6_server_service_set_address_autonous_flag(int8_t interface, uint8_t guaPrefix[static 16], bool mode, bool autonomous_skip_list) { (void) interface; (void) guaPrefix; (void) mode; + (void) autonomous_skip_list; return -1; } diff --git a/source/DHCPv6_Server/DHCPv6_server_service.h b/source/DHCPv6_Server/DHCPv6_server_service.h index 2a236ad254..8f8616f4f4 100644 --- a/source/DHCPv6_Server/DHCPv6_server_service.h +++ b/source/DHCPv6_Server/DHCPv6_server_service.h @@ -66,8 +66,9 @@ void DHCPv6_server_service_timeout_cb(uint32_t timeUpdateInSeconds); * /param interface interface id of this thread instance. * /param guaPrefix Prefix which will be removed * /param mode true trig autonous mode, false define address by default suffics + client id + * /param autonomous_skip_list true skip address list allocation when autonous mode is selected */ -int DHCPv6_server_service_set_address_autonous_flag(int8_t interface, uint8_t guaPrefix[static 16], bool mode); +int DHCPv6_server_service_set_address_autonous_flag(int8_t interface, uint8_t guaPrefix[static 16], bool mode, bool autonomous_skip_list); /* SET max accepted clients to server, Default is 200 diff --git a/source/MAC/IEEE802_15_4/mac_defines.h b/source/MAC/IEEE802_15_4/mac_defines.h index 7d53459545..acc45a6788 100644 --- a/source/MAC/IEEE802_15_4/mac_defines.h +++ b/source/MAC/IEEE802_15_4/mac_defines.h @@ -202,6 +202,7 @@ typedef struct protocol_interface_rf_mac_setup { mac_scan_type_t scan_type; uint8_t mac_channel; + uint8_t mac_tx_start_channel; //uint8_t cca_failure; /* MAC TX Queue */ @@ -244,6 +245,7 @@ typedef struct protocol_interface_rf_mac_setup { uint32_t mlme_tick_count; uint32_t symbol_rate; uint32_t symbol_time_us; + uint32_t datarate; uint8_t max_ED; uint16_t mlme_ED_counter; mac_tx_status_t mac_tx_status; diff --git a/source/MAC/IEEE802_15_4/mac_fhss_callbacks.c b/source/MAC/IEEE802_15_4/mac_fhss_callbacks.c index 3f09ca01ba..fd56ecbd74 100644 --- a/source/MAC/IEEE802_15_4/mac_fhss_callbacks.c +++ b/source/MAC/IEEE802_15_4/mac_fhss_callbacks.c @@ -57,8 +57,13 @@ uint32_t mac_read_phy_datarate(const fhss_api_t *fhss_api) if (!mac_setup) { return 0; } - uint32_t datarate = dev_get_phy_datarate(mac_setup->dev_driver->phy_driver, mac_setup->mac_channel_list.channel_page); - // If datarate is not set, use default 250kbit/s. + uint32_t datarate = 0; + // When channel page is set, ask data rate directly from PHY driver, otherwise use data rate configured to MAC. Ultimately, use default value instead 0. + if (mac_setup->mac_channel_list.channel_page != CHANNEL_PAGE_UNDEFINED) { + datarate = dev_get_phy_datarate(mac_setup->dev_driver->phy_driver, mac_setup->mac_channel_list.channel_page); + } else if (mac_setup->datarate) { + datarate = mac_setup->datarate; + } if (!datarate) { datarate = 250000; } diff --git a/source/MAC/IEEE802_15_4/mac_mcps_sap.c b/source/MAC/IEEE802_15_4/mac_mcps_sap.c index a97570675a..6442290a48 100644 --- a/source/MAC/IEEE802_15_4/mac_mcps_sap.c +++ b/source/MAC/IEEE802_15_4/mac_mcps_sap.c @@ -1321,7 +1321,7 @@ static void mac_common_data_confirmation_handle(protocol_interface_rf_mac_setup_ timer_mac_stop(rf_mac_setup); if (m_event == MAC_CCA_FAIL) { sw_mac_stats_update(rf_mac_setup, STAT_MAC_TX_CCA_FAIL, 0); - tr_debug("MAC CCA fail"); + tr_info("MAC CCA fail"); /* CCA fail */ //rf_mac_setup->cca_failure++; buf->status = MLME_BUSY_CHAN; @@ -1329,7 +1329,7 @@ static void mac_common_data_confirmation_handle(protocol_interface_rf_mac_setup_ sw_mac_stats_update(rf_mac_setup, STAT_MAC_TX_COUNT, buf->mac_payload_length); if (m_event == MAC_TX_FAIL) { sw_mac_stats_update(rf_mac_setup, STAT_MAC_TX_FAIL, 0); - tr_debug("MAC tx fail"); + tr_info("MAC tx fail"); buf->status = MLME_TX_NO_ACK; } else if (m_event == MAC_TX_DONE) { if (mac_is_ack_request_set(buf) == false) { @@ -1430,7 +1430,7 @@ static void mcps_data_confirm_handle(protocol_interface_rf_mac_setup_s *rf_ptr, if (rf_ptr->fhss_api && !buffer->asynch_request) { // FHSS checks if this failed buffer needs to be pushed back to TX queue and retransmitted if ((rf_ptr->mac_tx_result == MAC_TX_FAIL) || (rf_ptr->mac_tx_result == MAC_CCA_FAIL)) { - if (rf_ptr->fhss_api->data_tx_fail(rf_ptr->fhss_api, buffer->msduHandle, mac_convert_frame_type_to_fhss(buffer->fcf_dsn.frametype)) == true) { + if (rf_ptr->fhss_api->data_tx_fail(rf_ptr->fhss_api, buffer->msduHandle, mac_convert_frame_type_to_fhss(buffer->fcf_dsn.frametype), rf_ptr->mac_tx_start_channel) == true) { if (rf_ptr->mac_tx_result == MAC_TX_FAIL) { buffer->fhss_retry_count += 1 + rf_ptr->mac_tx_status.retry; @@ -1543,7 +1543,7 @@ static int8_t mcps_generic_packet_build(protocol_interface_rf_mac_setup_s *rf_pt mac_header_information_elements_preparation(buffer); mcps_generic_sequence_number_allocate(rf_ptr, buffer); - mlme_key_descriptor_t *key_desc; + mlme_key_descriptor_t *key_desc = NULL; if (buffer->fcf_dsn.securityEnabled) { bool increment_framecounter = false; //Remember to update security counter here! @@ -1600,7 +1600,7 @@ static int8_t mcps_generic_packet_build(protocol_interface_rf_mac_setup_s *rf_pt tr_debug("Too Long %u, %u pa %u header %u mic %u", frame_length, mac_payload_length, buffer->mac_header_length_with_security, buffer->security_mic_len, dev_driver->phy_MTU); buffer->status = MLME_FRAME_TOO_LONG; //decrement security counter - if (buffer->fcf_dsn.securityEnabled) { + if (key_desc) { mac_sec_mib_key_outgoing_frame_counter_decrement(rf_ptr, key_desc); } return -1; @@ -1716,7 +1716,7 @@ int8_t mcps_generic_ack_build(protocol_interface_rf_mac_setup_s *rf_ptr, bool in ccm_globals_t ccm_ptr; mac_pre_build_frame_t *buffer = &rf_ptr->enhanced_ack_buffer; - mlme_key_descriptor_t *key_desc; + mlme_key_descriptor_t *key_desc = NULL; if (buffer->fcf_dsn.securityEnabled) { //Remember to update security counter here! @@ -1755,7 +1755,7 @@ int8_t mcps_generic_ack_build(protocol_interface_rf_mac_setup_s *rf_ptr, bool in if ((frame_length) > ack_mtu_size - 2) { buffer->status = MLME_FRAME_TOO_LONG; - if (buffer->fcf_dsn.securityEnabled) { + if (key_desc) { //decrement security counter mac_sec_mib_key_outgoing_frame_counter_decrement(rf_ptr, key_desc); ccm_free(&ccm_ptr); @@ -1921,6 +1921,7 @@ static int8_t mcps_pd_data_request(protocol_interface_rf_mac_setup_s *rf_ptr, ma memset(&(rf_ptr->mac_tx_status), 0, sizeof(mac_tx_status_t)); rf_ptr->mac_cca_retry = 0; rf_ptr->mac_tx_retry = 0; + rf_ptr->mac_tx_start_channel = rf_ptr->mac_channel; mac_csma_param_init(rf_ptr); if (mcps_generic_packet_build(rf_ptr, buffer) != 0) { return -1; diff --git a/source/MAC/IEEE802_15_4/mac_mlme.c b/source/MAC/IEEE802_15_4/mac_mlme.c index 5d1f5e48c9..b091da2a85 100644 --- a/source/MAC/IEEE802_15_4/mac_mlme.c +++ b/source/MAC/IEEE802_15_4/mac_mlme.c @@ -783,6 +783,7 @@ int8_t mac_mlme_set_req(protocol_interface_rf_mac_setup_s *rf_mac_setup, const m rf_mac_setup->dev_driver->phy_driver->extension(PHY_EXTENSION_SET_RF_CONFIGURATION, (uint8_t *) set_req->value_pointer); mac_mlme_set_symbol_rate(rf_mac_setup); phy_rf_channel_configuration_s *config_params = (phy_rf_channel_configuration_s *)set_req->value_pointer; + rf_mac_setup->datarate = config_params->datarate; tr_info("RF config update:"); tr_info("Frequency(ch0): %"PRIu32"Hz", config_params->channel_0_center_frequency); tr_info("Channel spacing: %"PRIu32"Hz", config_params->channel_spacing); @@ -1090,6 +1091,7 @@ protocol_interface_rf_mac_setup_s *mac_mlme_data_base_allocate(uint8_t *mac64, a entry->aUnitBackoffPeriod = 20; //This can be different in some Platform 20 comes from 12-symbol turnaround and 8 symbol CCA read entry->number_of_csma_ca_periods = MAC_DEFAULT_NUMBER_OF_CSMA_PERIODS; entry->multi_cca_interval = MAC_DEFAULT_CSMA_MULTI_CCA_INTERVAL; + entry->mac_channel_list.channel_page = CHANNEL_PAGE_UNDEFINED; if (mac_sec_mib_init(entry, storage_sizes) != 0) { mac_mlme_data_base_deallocate(entry); diff --git a/source/MAC/IEEE802_15_4/mac_pd_sap.c b/source/MAC/IEEE802_15_4/mac_pd_sap.c index a7a5cc2a89..1b8eda1229 100644 --- a/source/MAC/IEEE802_15_4/mac_pd_sap.c +++ b/source/MAC/IEEE802_15_4/mac_pd_sap.c @@ -429,7 +429,7 @@ static int8_t mac_data_interface_tx_done_cb(protocol_interface_rf_mac_setup_s *r if (rf_ptr->mac_ack_tx_active) { //Accept direct non crypted acks and crypted only if neighbor is at list - if (rf_ptr->ack_tx_possible || mac_sec_mib_device_description_get(rf_ptr, rf_ptr->enhanced_ack_buffer.DstAddr, rf_ptr->enhanced_ack_buffer.fcf_dsn.DstAddrMode, rf_ptr->enhanced_ack_buffer.DstPANId)) { + if (rf_ptr->ack_tx_possible) { return PHY_TX_ALLOWED; } @@ -481,10 +481,6 @@ static int8_t mac_data_interface_tx_done_cb(protocol_interface_rf_mac_setup_s *r return 0; } - // - bool waiting_ack = false; - - if (rf_ptr->mac_ack_tx_active) { mac_data_ack_tx_finish(rf_ptr); return 0; @@ -506,11 +502,40 @@ static int8_t mac_data_interface_tx_done_cb(protocol_interface_rf_mac_setup_s *r timer_mac_stop(rf_ptr); } + if (rf_ptr->fhss_api && rf_ptr->active_pd_data_request->asynch_request == false) { + /* waiting_ack == false allows FHSS to change back to RX channel after transmission + * tx_completed == true allows FHSS to delete stored failure handles + */ + bool waiting_ack = false, tx_completed = false; + if (status == PHY_LINK_TX_SUCCESS && !rf_ptr->macTxRequestAck) { + waiting_ack = false; + tx_completed = true; + } else if (status == PHY_LINK_TX_SUCCESS && rf_ptr->macTxRequestAck) { + waiting_ack = true; + tx_completed = false; + } else if (status == PHY_LINK_CCA_FAIL) { + waiting_ack = false; + tx_completed = false; + } else if (status == PHY_LINK_CCA_OK) { + waiting_ack = false; + tx_completed = false; + } else if (status == PHY_LINK_TX_FAIL) { + waiting_ack = false; + tx_completed = false; + } else if (status == PHY_LINK_TX_DONE) { + waiting_ack = false; + tx_completed = true; + } else if (status == PHY_LINK_TX_DONE_PENDING) { + waiting_ack = false; + tx_completed = true; + } + rf_ptr->fhss_api->data_tx_done(rf_ptr->fhss_api, waiting_ack, tx_completed, rf_ptr->active_pd_data_request->msduHandle); + } + switch (status) { case PHY_LINK_TX_SUCCESS: if (rf_ptr->macTxRequestAck) { timer_mac_start(rf_ptr, MAC_TIMER_ACK, rf_ptr->mac_ack_wait_duration); /*wait for ACK 1 ms*/ - waiting_ack = true; } else { //TODO CHECK this is MAC_TX_ PERMIT OK mac_tx_done_state_set(rf_ptr, MAC_TX_DONE); @@ -540,15 +565,6 @@ static int8_t mac_data_interface_tx_done_cb(protocol_interface_rf_mac_setup_s *r default: break; } - if (rf_ptr->fhss_api) { - bool tx_is_done = false; - if (rf_ptr->mac_tx_result == MAC_TX_DONE) { - tx_is_done = true; - } - if (rf_ptr->active_pd_data_request->asynch_request == false) { - rf_ptr->fhss_api->data_tx_done(rf_ptr->fhss_api, waiting_ack, tx_is_done, rf_ptr->active_pd_data_request->msduHandle); - } - } return 0; } @@ -772,7 +788,7 @@ static int8_t mac_pd_sap_generate_ack(protocol_interface_rf_mac_setup_s *rf_ptr, return -1; } - if (rf_ptr->enhanced_ack_buffer.aux_header.securityLevel == 0 || mac_sec_mib_device_description_get(rf_ptr, rf_ptr->enhanced_ack_buffer.DstAddr, rf_ptr->enhanced_ack_buffer.fcf_dsn.DstAddrMode, rf_ptr->enhanced_ack_buffer.DstPANId)) { + if (mac_sec_mib_device_description_get(rf_ptr, rf_ptr->enhanced_ack_buffer.DstAddr, rf_ptr->enhanced_ack_buffer.fcf_dsn.DstAddrMode, rf_ptr->enhanced_ack_buffer.DstPANId)) { rf_ptr->ack_tx_possible = true; } else { rf_ptr->ack_tx_possible = false; @@ -874,6 +890,11 @@ int8_t mac_pd_sap_data_cb(void *identifier, arm_phy_sap_msg_t *message) if (message->id == MAC15_4_PD_SAP_DATA_IND) { arm_pd_sap_generic_ind_t *pd_data_ind = &(message->message.generic_data_ind); + mac_pre_parsed_frame_t *buffer = NULL; + if (pd_data_ind->data_len == 0) { + goto ERROR_HANDLER; + } + if (pd_data_ind->data_len < 3) { return -1; } @@ -881,7 +902,7 @@ int8_t mac_pd_sap_data_cb(void *identifier, arm_phy_sap_msg_t *message) mac_fcf_sequence_t fcf_read; const uint8_t *ptr = mac_header_parse_fcf_dsn(&fcf_read, pd_data_ind->data_ptr); - mac_pre_parsed_frame_t *buffer = mac_pd_sap_allocate_receive_buffer(rf_ptr, &fcf_read, pd_data_ind); + buffer = mac_pd_sap_allocate_receive_buffer(rf_ptr, &fcf_read, pd_data_ind); if (buffer && mac_filter_modify_link_quality(rf_ptr->mac_interface_id, buffer) == 1) { goto ERROR_HANDLER; } @@ -919,7 +940,12 @@ int8_t mac_pd_sap_data_cb(void *identifier, arm_phy_sap_msg_t *message) } ERROR_HANDLER: mcps_sap_pre_parsed_frame_buffer_free(buffer); - sw_mac_stats_update(rf_ptr, STAT_MAC_RX_DROP, 0); + if (pd_data_ind->data_len >= 3) { + sw_mac_stats_update(rf_ptr, STAT_MAC_RX_DROP, 0); + } + if (rf_ptr->fhss_api) { + rf_ptr->fhss_api->data_tx_done(rf_ptr->fhss_api, false, false, 0); + } return -1; } else if (message->id == MAC15_4_PD_SAP_DATA_TX_CONFIRM) { diff --git a/source/MAC/IEEE802_15_4/mac_security_mib.c b/source/MAC/IEEE802_15_4/mac_security_mib.c index 8b22875a96..27de7e89cb 100644 --- a/source/MAC/IEEE802_15_4/mac_security_mib.c +++ b/source/MAC/IEEE802_15_4/mac_security_mib.c @@ -281,6 +281,7 @@ int8_t mac_sec_mib_device_description_set(uint8_t atribute_index, mlme_device_de return -1; } + platform_enter_critical(); mlme_device_descriptor_t *device_ptr = rf_mac_setup->device_description_table + atribute_index; //Copy description @@ -293,6 +294,24 @@ int8_t mac_sec_mib_device_description_set(uint8_t atribute_index, mlme_device_de //tr_debug("Set %u, mac16 %x mac64: %s, %"PRIu32, atribute_index, device_descriptor->ShortAddress, trace_array(device_descriptor->ExtAddress, 8), device_descriptor->FrameCounter); *device_ptr = *device_descriptor; + + if (rf_mac_setup->mac_ack_tx_active && !rf_mac_setup->ack_tx_possible && + device_ptr->PANId == rf_mac_setup->enhanced_ack_buffer.DstPANId) { + + //Compare address for pending neigbour add + if (rf_mac_setup->enhanced_ack_buffer.fcf_dsn.DstAddrMode == MAC_ADDR_MODE_16_BIT) { + uint16_t short_id = common_read_16_bit(rf_mac_setup->enhanced_ack_buffer.DstAddr); + if (short_id == device_ptr->ShortAddress) { + rf_mac_setup->ack_tx_possible = true; + } + } else if (rf_mac_setup->enhanced_ack_buffer.fcf_dsn.DstAddrMode == MAC_ADDR_MODE_64_BIT) { + if (memcmp(device_ptr->ExtAddress, rf_mac_setup->enhanced_ack_buffer.DstAddr, 8) == 0) { + rf_mac_setup->ack_tx_possible = true; + } + } + } + platform_exit_critical(); + return 0; } diff --git a/source/MAC/IEEE802_15_4/sw_mac.c b/source/MAC/IEEE802_15_4/sw_mac.c index ca52231bac..a5b679eb28 100644 --- a/source/MAC/IEEE802_15_4/sw_mac.c +++ b/source/MAC/IEEE802_15_4/sw_mac.c @@ -197,6 +197,20 @@ int ns_sw_mac_fhss_register(mac_api_t *mac_api, fhss_api_t *fhss_api) return 0; } +int ns_sw_mac_fhss_unregister(mac_api_t *mac_api) +{ + if (!mac_api) { + return -1; + } + // Get a pointer to MAC setup structure + protocol_interface_rf_mac_setup_s *mac_setup = get_sw_mac_ptr_by_mac_api(mac_api); + if (!mac_setup) { + return -1; + } + mac_setup->fhss_api = NULL; + return 0; +} + struct fhss_api *ns_sw_mac_get_fhss_api(struct mac_api_s *mac_api) { if (!mac_api) { diff --git a/source/NWK_INTERFACE/protocol_core.c b/source/NWK_INTERFACE/protocol_core.c index 2d8c99f4c1..279bc7f0df 100644 --- a/source/NWK_INTERFACE/protocol_core.c +++ b/source/NWK_INTERFACE/protocol_core.c @@ -603,6 +603,7 @@ static protocol_interface_info_entry_t *protocol_core_interface_6lowpan_entry_ge entry->mac_parameters->mac_prev_key_attribute_id = 0; entry->mac_parameters->mac_default_key_attribute_id = 1; entry->mac_parameters->mac_next_key_attribute_id = 2; + entry->mac_parameters->mac_default_key_index = 0; entry->beacon_cb = beacon_received; @@ -1116,10 +1117,10 @@ void nwk_bootsrap_state_update(arm_nwk_interface_status_type_e posted_event, pro default: mac_data_poll_protocol_poll_mode_disable(cur); if (!cur->rpl_domain) { - tr_debug("NON RPL Ready"); + tr_info("NON RPL Ready"); //nwk_protocol_poll_mode_disable(cur->nwk_id, 0); } else { - tr_debug("RPL Ready"); + tr_info("RPL Ready"); } } } else { diff --git a/source/RPL/rpl_control.c b/source/RPL/rpl_control.c index c6854e3f4e..b17dce381e 100644 --- a/source/RPL/rpl_control.c +++ b/source/RPL/rpl_control.c @@ -60,8 +60,8 @@ const uint8_t ADDR_LINK_LOCAL_ALL_RPL_NODES[16] = { 0xff, 0x02, [15] = 0x1a }; /* Sensible default limits for a 6LoWPAN-ND node */ -static size_t rpl_purge_threshold = 1 * 1024; -static size_t rpl_alloc_limit = 2 * 1024; // 0 means no limit +static size_t rpl_purge_threshold = 2 * 1024; +static size_t rpl_alloc_limit = 4 * 1024; // 0 means no limit static size_t rpl_alloc_total; #define RPL_ALLOC_OVERHEAD 8 @@ -190,6 +190,10 @@ void rpl_control_set_initial_dao_ack_wait(uint16_t timeout_in_ms) { rpl_policy_set_initial_dao_ack_wait(timeout_in_ms); } +void rpl_control_set_mrhof_parent_set_size(uint16_t parent_set_size) +{ + rpl_policy_set_mrhof_parent_set_size(parent_set_size); +} /* Send address registration to either specified address, or to non-registered address */ void rpl_control_register_address(protocol_interface_info_entry_t *interface, const uint8_t addr[16]) @@ -247,6 +251,56 @@ bool rpl_control_is_dodag_parent_candidate(protocol_interface_info_entry_t *inte return false; } +uint16_t rpl_control_candidate_list_size(protocol_interface_info_entry_t *interface, rpl_instance_t *rpl_instance) +{ + if (!interface->rpl_domain) { + return 0; + } + + return rpl_instance_address_candidate_count(rpl_instance, false); + +} + +uint16_t rpl_control_selected_parent_count(protocol_interface_info_entry_t *interface, rpl_instance_t *rpl_instance) +{ + if (!interface->rpl_domain) { + return 0; + } + + return rpl_instance_address_candidate_count(rpl_instance, true); + +} + + +bool rpl_control_probe_parent_candidate(protocol_interface_info_entry_t *interface, const uint8_t ll_addr[16]) +{ + if (!interface->rpl_domain) { + return false; + } + // go through instances and parents and check if they match the address. + ns_list_foreach(struct rpl_instance, instance, &interface->rpl_domain->instances) { + if (rpl_lookup_neighbour_by_ll_address(instance, ll_addr, interface->id)) { + return true; + } + } + return false; +} + +bool rpl_possible_better_candidate(struct protocol_interface_info_entry *interface, rpl_instance_t *rpl_instance, const uint8_t ll_addr[16], uint16_t candidate_rank, uint16_t etx) +{ + if (!interface->rpl_domain) { + return false; + } + + rpl_neighbour_t *neighbour = rpl_lookup_neighbour_by_ll_address(rpl_instance, ll_addr, interface->id); + if (!neighbour) { + return false; + } + + return rpl_instance_possible_better_candidate(rpl_instance, neighbour, candidate_rank, etx); + +} + uint16_t rpl_control_parent_candidate_list_size(protocol_interface_info_entry_t *interface, bool parent_list) { @@ -266,6 +320,13 @@ uint16_t rpl_control_parent_candidate_list_size(protocol_interface_info_entry_t return parent_list_size; } +void rpl_control_neighbor_delete_from_instance(protocol_interface_info_entry_t *interface, rpl_instance_t *instance, const uint8_t ll_addr[16]) +{ + rpl_neighbour_t *neighbour = rpl_lookup_neighbour_by_ll_address(instance, ll_addr, interface->id); + if (neighbour) { + rpl_delete_neighbour(instance, neighbour); + } +} void rpl_control_neighbor_delete(protocol_interface_info_entry_t *interface, const uint8_t ll_addr[16]) { @@ -274,14 +335,26 @@ void rpl_control_neighbor_delete(protocol_interface_info_entry_t *interface, con } // go through instances and delete address. ns_list_foreach(struct rpl_instance, instance, &interface->rpl_domain->instances) { - - rpl_neighbour_t *neighbour = rpl_lookup_neighbour_by_ll_address(instance, ll_addr, interface->id); - if (neighbour) { - rpl_delete_neighbour(instance, neighbour); - } + rpl_control_neighbor_delete_from_instance(interface, instance, ll_addr); } } +bool rpl_control_find_worst_neighbor(protocol_interface_info_entry_t *interface, rpl_instance_t *rpl_instance, uint8_t ll_addr[static 16]) +{ + if (!interface->rpl_domain) { + return false; + } + + rpl_neighbour_t *neighbour = rpl_lookup_last_candidate_from_list(rpl_instance); + if (neighbour) { + memcpy(ll_addr, rpl_neighbour_ll_address(neighbour), 16); + return true; + } + + return false; +} + + /* Address changes need to trigger DAO target re-evaluation */ static void rpl_control_addr_notifier(struct protocol_interface_info_entry *interface, const if_address_entry_t *addr, if_address_callback_t reason) { @@ -307,19 +380,24 @@ static void rpl_control_addr_notifier(struct protocol_interface_info_entry *inte static void rpl_control_etx_change_callback(int8_t nwk_id, uint16_t previous_etx, uint16_t current_etx, uint8_t attribute_index) { - (void)previous_etx; - (void)current_etx; protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(nwk_id); if (!cur || !cur->rpl_domain) { return; } + // ETX is "better" if now lower, or previous was "unknown" and new isn't infinite + bool better = current_etx < previous_etx || (previous_etx == 0 && current_etx != 0xffff); + rpl_domain_t *domain = cur->rpl_domain; uint16_t delay = rpl_policy_etx_change_parent_selection_delay(domain); - tr_debug("Triggering parent selection due to ETX change on neigh index %u, etx %u", attribute_index, current_etx); + tr_debug("Triggering parent selection due to ETX %s on neigh index %u, etx %u", better ? "better" : "worse", attribute_index, current_etx); + rpl_dodag_t *dodag = NULL; ns_list_foreach(rpl_instance_t, instance, &domain->instances) { - rpl_instance_trigger_parent_selection(instance, delay); + if (better) { + dodag = rpl_instance_current_dodag(instance); + } + rpl_instance_trigger_parent_selection(instance, delay, dodag); if (rpl_instance_am_root(instance)) { rpl_downward_paths_invalidate(instance); } @@ -339,6 +417,7 @@ rpl_domain_t *rpl_control_create_domain(void) domain->callback = NULL; domain->cb_handle = NULL; domain->force_leaf = false; + domain->process_routes = true; ns_list_add_to_start(&rpl_domains, domain); addr_notification_register(rpl_control_addr_notifier); @@ -495,8 +574,13 @@ rpl_dodag_t *rpl_control_create_dodag_root(rpl_domain_t *domain, uint8_t instanc rpl_dodag_t *dodag = rpl_lookup_dodag(instance, dodagid); if (dodag) { - tr_error("Root DODAG already exists"); - return NULL; + if (rpl_dodag_am_root(dodag)) { + tr_error("Root DODAG already exists"); + return NULL; + } + + // Delete non root information and recreate dodag + rpl_delete_dodag(dodag); } dodag = rpl_create_dodag(instance, dodagid, g_mop_prf); if (!dodag) { @@ -547,13 +631,16 @@ void rpl_control_increment_dtsn(rpl_dodag_t *dodag) //rpl_dodag_inconsistency(dodag); currently implied by rpl_dodag_increment_dtsn } -void rpl_control_increment_dodag_version(rpl_dodag_t *dodag) +uint8_t rpl_control_increment_dodag_version(rpl_dodag_t *dodag) { + uint8_t new_version = 240; if (rpl_dodag_am_root(dodag)) { - uint8_t new_version = rpl_seq_inc(rpl_dodag_get_version_number_as_root(dodag)); + new_version = rpl_seq_inc(rpl_dodag_get_version_number_as_root(dodag)); rpl_dodag_set_version_number_as_root(dodag, new_version); } + return new_version; } + void rpl_control_update_dodag_config(struct rpl_dodag *dodag, const rpl_dodag_conf_t *conf) { @@ -586,6 +673,10 @@ void rpl_control_force_leaf(rpl_domain_t *domain, bool leaf) } } } +void rpl_control_process_routes(rpl_domain_t *domain, bool process_routes) +{ + domain->process_routes = process_routes; +} /* Check whether the options section of a RPL control message is well-formed */ static bool rpl_control_options_well_formed(const uint8_t *dptr, uint_fast16_t dlen) @@ -855,7 +946,6 @@ static void rpl_control_process_route_options(rpl_instance_t *instance, rpl_doda } rpl_dodag_update_dio_route(dodag, prefix, prefix_len, flags, lifetime, true); } - /* We do not purge unadvertised routes. Thus if the root wants to purge * a route before its lifetime is up, stopping advertising it is not * sufficient, it has to advertise it with low or zero lifetime. This fits @@ -975,8 +1065,9 @@ malformed: } } - /* Never listen to nodes in a DODAG we're rooting */ - if (rpl_dodag_am_root(dodag)) { + /* Never listen to nodes in a DODAG we're rooting or were root*/ + if (rpl_dodag_am_root(dodag) || + rpl_dodag_was_root(dodag)) { /* TODO - if version is newer or unordered, increment our version to be higher? */ /* Old code had this trick - actually, would need to go further. Want to listen first, then use a higher * than existing. */ @@ -1009,7 +1100,7 @@ malformed: const rpl_dodag_conf_t *conf = rpl_dodag_get_config(dodag); if (!conf) { /* TODO - rate limit DIS? */ - if (domain->new_parent_add && !domain->new_parent_add(buf->src_sa.address, domain->cb_handle)) { + if (domain->new_parent_add && !domain->new_parent_add(buf->src_sa.address, domain->cb_handle, instance, rank)) { goto invalid_parent; } rpl_control_transmit_dis(domain, cur, RPL_SOLINFO_PRED_DODAGID | RPL_SOLINFO_PRED_INSTANCEID, instance_id, dodagid, 0, buf->src_sa.address); @@ -1043,15 +1134,21 @@ malformed: /* Now we create the neighbour, if we don't already have a record */ if (!neighbour) { + + if (domain->new_parent_add) { + + if (!domain->new_parent_add(buf->src_sa.address, domain->cb_handle, instance, rank)) { + goto invalid_parent; + } + } + neighbour = rpl_create_neighbour(version, buf->src_sa.address, cur->id, g_mop_prf, dtsn); //Call Here new parent create if (!neighbour) { goto invalid_parent; } - if (domain->new_parent_add && !domain->new_parent_add(buf->src_sa.address, domain->cb_handle)) { - goto invalid_parent; - } + } @@ -1182,7 +1279,7 @@ void rpl_control_transmit_dio(rpl_domain_t *domain, protocol_interface_info_entr const rpl_dio_route_list_t *routes = rpl_dodag_get_route_list(dodag); const prefix_list_t *prefixes = rpl_dodag_get_prefix_list(dodag); - tr_debug("transmit dio, rank: %x", rank); + tr_info("transmit dio, rank: %x", rank); protocol_interface_info_entry_t *downstream_if = protocol_stack_interface_info_get_by_id(domain->non_storing_downstream_interface); length = 24; if (conf) { @@ -1770,12 +1867,24 @@ static void rpl_domain_print(const rpl_domain_t *domain, route_print_fn_t *print void rpl_control_print(route_print_fn_t *print_fn) { - print_fn("RPL memory usage %zu", rpl_alloc_total); + unsigned t = protocol_core_monotonic_time % 10; + unsigned s_full = protocol_core_monotonic_time / 10; + unsigned m = s_full / 60; + unsigned s = s_full % 60; + unsigned h = m / 60; + m %= 60; + // %zu doesn't work on some Mbed toolchains + print_fn("Time %02u:%02u:%02u.%u (%u.%u) RPL memory usage %" PRIu32, h, m, s, t, s_full, t, (uint32_t) rpl_alloc_total); ns_list_foreach(rpl_domain_t, domain, &rpl_domains) { rpl_domain_print(domain, print_fn); } } +uint8_t rpl_policy_mrhof_parent_set_size_get(const rpl_domain_t *domain) +{ + return rpl_policy_mrhof_parent_set_size(domain); +} + #ifdef RPL_STRUCTURES_H_ #error "rpl_structures.h should not be included by rpl_control.c" #endif diff --git a/source/RPL/rpl_control.h b/source/RPL/rpl_control.h index 7569bac944..464e5c2a83 100644 --- a/source/RPL/rpl_control.h +++ b/source/RPL/rpl_control.h @@ -42,7 +42,8 @@ typedef void rpl_domain_callback_t(rpl_event_t event, void *handle); typedef void rpl_prefix_callback_t(struct prefix_entry_t *prefix, void *handle, uint8_t *parent_link_local); -typedef bool rpl_new_parent_callback_t(uint8_t *ll_parent_address, void *handle); +typedef bool rpl_new_parent_callback_t(uint8_t *ll_parent_address, void *handle, struct rpl_instance *instance, uint16_t candidate_rank); + typedef struct rpl_domain { NS_LIST_HEAD_INCOMPLETE(struct rpl_instance) instances; @@ -54,6 +55,8 @@ typedef struct rpl_domain { int8_t non_storing_downstream_interface; /* As part of shutdown, we can force entering leaf mode */ bool force_leaf; + /* if false routes are not set to routing table, instead default route is added for DODAGID */ + bool process_routes; rpl_domain_callback_t *callback; rpl_prefix_callback_t *prefix_cb; rpl_new_parent_callback_t *new_parent_add; @@ -129,13 +132,15 @@ struct rpl_dodag *rpl_control_create_dodag_root(rpl_domain_t *domain, uint8_t in void rpl_control_delete_dodag_root(rpl_domain_t *domain, struct rpl_dodag *dodag); void rpl_control_update_dodag_route(struct rpl_dodag *dodag, const uint8_t *prefix, uint8_t prefix_len, uint8_t flags, uint32_t lifetime, bool age); void rpl_control_update_dodag_prefix(struct rpl_dodag *dodag, const uint8_t *prefix, uint8_t prefix_len, uint8_t flags, uint32_t lifetime, uint32_t preftime, bool age); -void rpl_control_increment_dodag_version(struct rpl_dodag *dodag); +uint8_t rpl_control_increment_dodag_version(struct rpl_dodag *dodag); void rpl_control_update_dodag_config(struct rpl_dodag *dodag, const rpl_dodag_conf_t *conf); void rpl_control_set_dodag_pref(struct rpl_dodag *dodag, uint8_t pref); void rpl_control_increment_dtsn(struct rpl_dodag *dodag); /* Force leaf behaviour on a domain - useful before shutdown, and in conjunction with poison */ void rpl_control_force_leaf(rpl_domain_t *domain, bool leaf); +/*Process routes from DIOs and add those as real routes. if routes are not processed assume DODAGID as default route*/ +void rpl_control_process_routes(rpl_domain_t *domain, bool process_routes); /* Manually send poison on all existing instances a few times */ void rpl_control_poison(rpl_domain_t *domain, uint8_t poison_count); @@ -146,20 +151,28 @@ void rpl_control_delete_domain(rpl_domain_t *domain); void rpl_control_set_domain_on_interface(struct protocol_interface_info_entry *cur, rpl_domain_t *domain, bool downstream); void rpl_control_remove_domain_from_interface(struct protocol_interface_info_entry *cur); void rpl_control_free_domain_instances_from_interface(struct protocol_interface_info_entry *cur); -void rpl_control_set_callback(rpl_domain_t *domain, rpl_domain_callback_t callback, rpl_prefix_callback_t prefix_learn_cb, rpl_new_parent_callback_t new_parent_add, void *cb_handle); +void rpl_control_set_callback(rpl_domain_t *domain, rpl_domain_callback_t callback, rpl_prefix_callback_t prefix_learn_cb, rpl_new_parent_callback_t new_parent_add, void *cb_handle); /* Target publishing */ void rpl_control_publish_host_address(rpl_domain_t *domain, const uint8_t addr[16], uint32_t lifetime); void rpl_control_unpublish_address(rpl_domain_t *domain, const uint8_t addr[16]); bool rpl_control_is_dodag_parent(struct protocol_interface_info_entry *interface, const uint8_t ll_addr[16]); bool rpl_control_is_dodag_parent_candidate(struct protocol_interface_info_entry *interface, const uint8_t ll_addr[16], uint16_t candidate_cmp_limiter); -uint16_t rpl_control_parent_candidate_list_size(struct protocol_interface_info_entry *interface, bool parent_list); +bool rpl_control_probe_parent_candidate(struct protocol_interface_info_entry *interface, const uint8_t ll_addr[16]); +bool rpl_possible_better_candidate(struct protocol_interface_info_entry *interface, struct rpl_instance *rpl_instance, const uint8_t ll_addr[16], uint16_t candidate_rank, uint16_t etx); +uint16_t rpl_control_parent_candidate_list_size(struct protocol_interface_info_entry *interface, bool parent_list); +uint16_t rpl_control_candidate_list_size(struct protocol_interface_info_entry *interface, struct rpl_instance *rpl_instance); +uint16_t rpl_control_selected_parent_count(struct protocol_interface_info_entry *interface, struct rpl_instance *rpl_instance); void rpl_control_neighbor_delete(struct protocol_interface_info_entry *interface, const uint8_t ll_addr[16]); +void rpl_control_neighbor_delete_from_instance(struct protocol_interface_info_entry *interface, struct rpl_instance *rpl_instance, const uint8_t ll_addr[16]); +bool rpl_control_find_worst_neighbor(struct protocol_interface_info_entry *interface, struct rpl_instance *rpl_instance, uint8_t ll_addr[16]); + /* Parent link confirmation API extension */ void rpl_control_request_parent_link_confirmation(bool requested); void rpl_control_set_dio_multicast_min_config_advertisment_count(uint8_t min_count); void rpl_control_set_dao_retry_count(uint8_t count); void rpl_control_set_initial_dao_ack_wait(uint16_t timeout_in_ms); +void rpl_control_set_mrhof_parent_set_size(uint16_t parent_set_size); void rpl_control_register_address(struct protocol_interface_info_entry *interface, const uint8_t addr[16]); void rpl_control_address_register_done(struct protocol_interface_info_entry *interface, const uint8_t ll_addr[16], uint8_t status); @@ -176,6 +189,7 @@ bool rpl_control_read_dodag_info(const struct rpl_instance *instance, struct rpl const rpl_dodag_conf_t *rpl_control_get_dodag_config(const struct rpl_instance *instance); const uint8_t *rpl_control_preferred_parent_addr(const struct rpl_instance *instance, bool global); uint16_t rpl_control_current_rank(const struct rpl_instance *instance); +uint8_t rpl_policy_mrhof_parent_set_size_get(const rpl_domain_t *domain); #else /* HAVE_RPL */ @@ -185,6 +199,8 @@ uint16_t rpl_control_current_rank(const struct rpl_instance *instance); #define rpl_control_free_domain_instances_from_interface(cur) ((void) 0) #define rpl_control_register_address(interface, addr) ((void) 0) #define rpl_control_address_register_done(interface, ll_addr, status) ((void) 0) +#define rpl_policy_mrhof_parent_set_size_get(domain) (0) +#define rpl_control_set_mrhof_parent_set_size(parent_set_size) #endif /* HAVE_RPL */ diff --git a/source/RPL/rpl_downward.c b/source/RPL/rpl_downward.c index 607cca6168..6f7a5dbfcb 100644 --- a/source/RPL/rpl_downward.c +++ b/source/RPL/rpl_downward.c @@ -545,8 +545,7 @@ retry: */ ns_list_foreach(rpl_neighbour_t, neighbour, &instance->candidate_neighbours) { if (neighbour->dao_path_control & unassigned_pc) { - unassigned_pc &= neighbour->dao_path_control; - *path_control = unassigned_pc; + *path_control = neighbour->dao_path_control; *parent = neighbour; return target; } @@ -561,14 +560,7 @@ retry: } } - /* If looking for a follow-up target, final path control must match */ - if (t1) { - if (unassigned_pc != *path_control) { - continue; - } - } else { - *path_control = unassigned_pc; - } + *path_control = target->path_control; return target; } @@ -1786,7 +1778,7 @@ static bool rpl_instance_push_address_registration(protocol_interface_info_entry if (!buf) { return false; } - tr_debug("Send ARO %s to %s", trace_ipv6(addr->address), trace_ipv6(neighbour->ll_address)); + tr_info("Send ARO %s to %s", trace_ipv6(addr->address), trace_ipv6(neighbour->ll_address)); protocol_push(buf); return true; } @@ -1811,6 +1803,8 @@ static void rpl_instance_address_registration_cancel(rpl_instance_t *instance) instance->wait_response = NULL; instance->pending_neighbour_confirmation = false; instance->delay_dao_timer = 0; + instance->dao_in_transit = false; + instance->dao_retry_timer = 0; } void rpl_instance_parent_address_reg_timer_update(rpl_instance_t *instance, uint16_t seconds) diff --git a/source/RPL/rpl_mrhof.c b/source/RPL/rpl_mrhof.c index bfff5aa000..be3fd9a822 100644 --- a/source/RPL/rpl_mrhof.c +++ b/source/RPL/rpl_mrhof.c @@ -45,12 +45,14 @@ static void rpl_mrhof_parent_selection(rpl_instance_t *instance); static uint16_t rpl_mrhof_path_cost_through_neighbour(const rpl_neighbour_t *neighbour); static bool rpl_mrhof_neighbour_acceptable(const rpl_instance_t *instance, const rpl_neighbour_t *neighbour); +static bool rpl_mrhof_possible_better_candidate(const rpl_instance_t *instance, const rpl_neighbour_t *existing, uint16_t rank, uint16_t etx); static rpl_objective_t rpl_mrhof = { .ocp = RPL_OCP_MRHOF, .parent_selection = rpl_mrhof_parent_selection, .path_cost = rpl_mrhof_path_cost_through_neighbour, .neighbour_acceptable = rpl_mrhof_neighbour_acceptable, + .possible_better_candidate = rpl_mrhof_possible_better_candidate, }; typedef struct rpl_of0_params { @@ -94,6 +96,26 @@ static bool rpl_mrhof_neighbour_acceptable(const rpl_instance_t *instance, const return rpl_mrhof_link_metric_to_neighbour(neighbour) <= rpl_policy_mrhof_max_link_metric(instance->domain); } +static bool rpl_mrhof_possible_better_candidate(const rpl_instance_t *instance, const rpl_neighbour_t *existing, uint16_t rank, uint16_t etx) +{ + uint16_t existing_path = rpl_mrhof_path_cost_through_neighbour(existing); + // Optimistically assume we could get a perfect link to this new person + // But add hysteresis to avoid switching unless potentially worthwhile + // (Compare rpl_mrhof_etx which assumes poor for unknown as a sort of hysteresis) + // Think: could actually use rpl_mrhof_etx here to get an existing ETX estimate + // (except that gives infinite if no current link, would want a variant that checks + // blacklist records for remembered poor ETX) + uint16_t threshold = rpl_policy_mrhof_parent_switch_threshold(instance->domain); + if (etx == 0) { + etx = 128; + } else if (etx >= (0xffff - threshold)) { + return false; + } + + etx += threshold; + uint16_t potential_path_with_hysteresis = rpl_rank_add(rank, etx); + return potential_path_with_hysteresis <= existing_path; +} /* Given a preferred parent, we are only permitted to stretch our above the * path cost through that parent by a certain (policy) amount to accommodate a diff --git a/source/RPL/rpl_objective.h b/source/RPL/rpl_objective.h index 67c35fd7c8..7e8293a396 100644 --- a/source/RPL/rpl_objective.h +++ b/source/RPL/rpl_objective.h @@ -28,9 +28,12 @@ typedef struct rpl_objective { uint16_t ocp; /* Run the parent selection algorithm - see rpl_of0.c for detailed info */ void (*parent_selection)(struct rpl_instance *); - /* Return the path cost of a neighbour (for debug prints only) */ + /* Return the path cost of a neighbour */ uint16_t (*path_cost)(const struct rpl_neighbour *); bool (*neighbour_acceptable)(const struct rpl_instance *, const struct rpl_neighbour *); + /* Could someone with specified rank be a significantly better candidate than the existing one? */ + /* (In future, this API could be extended to pass a metric pointer as well as rank) */ + bool (*possible_better_candidate)(const struct rpl_instance *, const struct rpl_neighbour *existing, uint16_t rank, uint16_t etx); ns_list_link_t link; } rpl_objective_t; diff --git a/source/RPL/rpl_of0.c b/source/RPL/rpl_of0.c index aa6927c1f1..bfdee2a496 100644 --- a/source/RPL/rpl_of0.c +++ b/source/RPL/rpl_of0.c @@ -42,12 +42,14 @@ static void rpl_of0_parent_selection(rpl_instance_t *instance); static uint16_t rpl_of0_rank_through_neighbour(const rpl_neighbour_t *neighbour); static bool rpl_of0_neighbour_acceptable(const rpl_instance_t *instance, const rpl_neighbour_t *neighbour); +static bool rpl_of0_possible_better_candidate(const rpl_instance_t *instance, const rpl_neighbour_t *existing, uint16_t rank, uint16_t etx); static rpl_objective_t rpl_of0 = { .ocp = RPL_OCP_OF0, .parent_selection = rpl_of0_parent_selection, .path_cost = rpl_of0_rank_through_neighbour, .neighbour_acceptable = rpl_of0_neighbour_acceptable, + .possible_better_candidate = rpl_of0_possible_better_candidate, }; #define DEFAULT_STEP_OF_RANK 3 @@ -115,6 +117,14 @@ static uint16_t rpl_of0_rank_through_neighbour(const rpl_neighbour_t *neighbour) return rpl_rank_add(neighbour->rank, rpl_of0_rank_increase(neighbour)); } +static bool rpl_of0_possible_better_candidate(const rpl_instance_t *instance, const rpl_neighbour_t *existing, uint16_t rank, uint16_t etx) +{ + (void)etx; + uint16_t existing_path = rpl_of0_rank_through_neighbour(existing); + uint16_t potential_path_with_hysteresis = rpl_rank_add(rank, 2 * rpl_policy_of0_rank_factor(instance->domain) * existing->dodag_version->dodag->config.min_hop_rank_increase); + return potential_path_with_hysteresis <= existing_path; +} + /* Given a preferred parent, we are only permitted to stretch our above the * path cost through that parent by a certain (policy) amount to accommodate a * bigger parent set. diff --git a/source/RPL/rpl_policy.c b/source/RPL/rpl_policy.c index ec581c8bb4..f8b25d86f1 100644 --- a/source/RPL/rpl_policy.c +++ b/source/RPL/rpl_policy.c @@ -39,7 +39,7 @@ static int8_t rpl_policy_dao_retry_count_conf = 0; static int16_t rpl_policy_dao_initial_timeout_conf = 20; // Default is 2 seconds 100ms ticks static uint16_t rpl_policy_dio_validity_period_hysteresis = 0x0180; //Fixed Point 1.5 static uint8_t rpl_policy_multicast_config_min_advertisment_count = 0; - +static uint8_t rpl_policy_mrhof_parent_set_size_conf = 3; // default parent set size /* TODO - application API to control when to join new instances / DODAGs * @@ -147,7 +147,7 @@ int8_t rpl_policy_dao_retry_count() /* Given the next-hop address from a source routing header, which interface, * if any, should we assume that next hop is on? */ -#define ETX_SRH_THRESHOLD 0x800 /* 8.8 fixed-point, so 4 */ +#define ETX_SRH_THRESHOLD 0x400 /* 8.8 fixed-point, so 4 */ int8_t rpl_policy_srh_next_hop_interface(rpl_domain_t *domain, int8_t if_id, const uint8_t *next_hop) { if (domain->non_storing_downstream_interface != -1) { @@ -326,11 +326,16 @@ uint_fast8_t rpl_policy_of0_max_backup_successors(const rpl_domain_t *domain) return 1; } +void rpl_policy_set_mrhof_parent_set_size(uint8_t parent_set_size) +{ + rpl_policy_mrhof_parent_set_size_conf = parent_set_size; +} + uint_fast8_t rpl_policy_mrhof_parent_set_size(const rpl_domain_t *domain) { (void)domain; - return 3; + return rpl_policy_mrhof_parent_set_size_conf; } uint16_t rpl_policy_mrhof_max_rank_stretch_for_extra_parents(const rpl_domain_t *domain) diff --git a/source/RPL/rpl_policy.h b/source/RPL/rpl_policy.h index c51adc81cd..13e25c492c 100644 --- a/source/RPL/rpl_policy.h +++ b/source/RPL/rpl_policy.h @@ -59,6 +59,7 @@ uint_fast8_t rpl_policy_of0_rank_factor(const rpl_domain_t *domain); bool rpl_policy_of0_dodag_preference_supersedes_grounded(const rpl_domain_t *domain); uint_fast8_t rpl_policy_of0_max_backup_successors(const rpl_domain_t *domain); +void rpl_policy_set_mrhof_parent_set_size(uint8_t parent_set_size); uint_fast8_t rpl_policy_mrhof_parent_set_size(const rpl_domain_t *domain); uint16_t rpl_policy_mrhof_max_link_metric(const rpl_domain_t *domain); uint16_t rpl_policy_mrhof_parent_switch_threshold(const rpl_domain_t *domain); diff --git a/source/RPL/rpl_structures.h b/source/RPL/rpl_structures.h index 1d4dcc0c37..aadbc60c28 100644 --- a/source/RPL/rpl_structures.h +++ b/source/RPL/rpl_structures.h @@ -32,10 +32,6 @@ struct rpl_objective; /* Descriptor for a RPL neighbour within a DODAG - * - * The neighbour is normally associated with a DODAG Version, but may not be, - * if the version has been retired, and we haven't since heard from that - * neighbour. In that case dodag_version is NULL. * * Note that global address is only needed with downward routes, but I don't * think it's worth optimising for an "upward-only" build. (Unless to be a RPL @@ -45,7 +41,7 @@ struct rpl_objective; * first in the instance candidate_neighbour list, in order of preference. */ struct rpl_neighbour { - rpl_dodag_version_t *dodag_version; // Back pointer to DODAG Version (may be NULL, if not dodag_parent) + rpl_dodag_version_t *dodag_version; // Back pointer to DODAG Version uint8_t ll_address[16]; // Link-local address (source of DIO) uint8_t global_address[16]; // Global address (from DIO RIO) bool dodag_parent: 1; // This is a DODAG parent (if true, dodag_version may not be NULL) @@ -87,10 +83,11 @@ struct rpl_dodag { rpl_dodag_conf_t config; /* Configuration from DIO */ uint8_t info_version; /* Version for g_mop_prf and config */ bool root: 1; /* We are the root of this DODAG */ + bool was_root: 1; /* If we have ever been a root in this DODAG */ bool leaf: 1; /* We are a leaf in this DODAG (by policy) */ bool have_config: 1; /* We have the config */ bool used: 1; /* We have ever been a member of this DODAG? */ - uint8_t new_config_advertisment_count; /* We have advertiment new config at multicasti DIO */ + uint8_t new_config_advertisment_count; /* We have advertiment new config at multicasti DIO max updated value is 0xfe*/ NS_LIST_HEAD(rpl_dodag_version_t, link) versions; /* List of DODAG versions (newest first) */ prefix_list_t prefixes; /* Prefixes advertised in DIO PIOs */ rpl_dio_route_list_t routes; /* Routes advertised in DIO RIOs*/ diff --git a/source/RPL/rpl_upward.c b/source/RPL/rpl_upward.c index d3e4720b04..99377e6150 100644 --- a/source/RPL/rpl_upward.c +++ b/source/RPL/rpl_upward.c @@ -74,6 +74,8 @@ static NS_LIST_DEFINE(rpl_candidate_neighbour_set, rpl_neighbour_t, candidate_ne static void rpl_instance_remove_parents(rpl_instance_t *instance); static void rpl_instance_remove_system_routes_through_parent(rpl_instance_t *instance, rpl_neighbour_t *parent); static void rpl_dodag_update_system_route(rpl_dodag_t *dodag, rpl_dio_route_t *route); +static rpl_neighbour_t *rpl_instance_choose_worst_neighbour(const rpl_instance_t *instance); +static uint32_t rpl_dio_imax_time_calculate(uint16_t Imax, uint16_t fixed_point); /* Rank comparison, and DAGRank(rank) */ uint16_t nrpl_dag_rank(const rpl_dodag_t *dodag, uint16_t rank) @@ -283,6 +285,16 @@ rpl_neighbour_t *rpl_instance_preferred_parent(const rpl_instance_t *instance) return neighbour; } +uint16_t rpl_instance_candidate_rank(const rpl_neighbour_t *candidate) +{ + return candidate->rank; +} + +bool rpl_instance_possible_better_candidate(const rpl_instance_t *instance, rpl_neighbour_t *replacing, uint16_t candidate_rank, uint16_t etx) +{ + return instance->of->possible_better_candidate(instance, replacing, candidate_rank, etx); +} + /* If we're a member of a DODAG Version matching the predicate in this instance, * return it. Mainly used for handling DODAG Information Solicitations. */ @@ -340,10 +352,19 @@ void rpl_instance_force_leaf(rpl_instance_t *instance) instance->current_rank = RPL_RANK_INFINITE; } -void rpl_instance_trigger_parent_selection(rpl_instance_t *instance, uint16_t delay) +void rpl_instance_trigger_parent_selection(rpl_instance_t *instance, uint16_t delay, rpl_dodag_t *dodag) { + /* When "improving", let us have a minimum trigger time based on Imin, for large networks */ + if (dodag) { + //Convert imin 100ms tick to seconds + uint16_t i_min_delay = dodag->dio_timer_params.Imin / 10; + if (i_min_delay > delay) { + delay = i_min_delay; + } + } if (instance->parent_selection_timer == 0 || instance->parent_selection_timer > delay) { - instance->parent_selection_timer = randLIB_randomise_base(delay, 0x7333, 0x8CCD) /* +/- 10% */; + instance->parent_selection_timer = randLIB_randomise_base(delay, 0x8000, 0x999A) /* Random between delay * 1.0-1.2 */; + tr_debug("Timed parent triggered %u", instance->parent_selection_timer); } } @@ -390,6 +411,15 @@ rpl_neighbour_t *rpl_lookup_neighbour_by_ll_address(const rpl_instance_t *instan return NULL; } +rpl_neighbour_t *rpl_lookup_last_candidate_from_list(const rpl_instance_t *instance) +{ + rpl_neighbour_t *neighbour = rpl_instance_choose_worst_neighbour(instance); + if (neighbour && neighbour->considered && !neighbour->dodag_parent) { + return neighbour; + } + return NULL; +} + rpl_neighbour_t *rpl_create_neighbour(rpl_dodag_version_t *version, const uint8_t *addr, int8_t if_id, uint8_t g_mop_prf, uint8_t dtsn) { /* Should gate higher-rank neighbours here - ignore higher-rank neighbours @@ -563,7 +593,7 @@ void rpl_delete_dodag_version(rpl_dodag_version_t *version) // triggering poison immediately. // Give parent selection a chance to select another version (but will it have any info on-hand?) instance->current_dodag_version = NULL; - rpl_instance_trigger_parent_selection(instance, 5); + rpl_instance_trigger_parent_selection(instance, 5, NULL); } ns_list_foreach_safe(rpl_neighbour_t, neighbour, &instance->candidate_neighbours) { @@ -638,6 +668,7 @@ rpl_dodag_t *rpl_create_dodag(rpl_instance_t *instance, const uint8_t *dodagid, memcpy(dodag->id, dodagid, 16); dodag->leaf = false; dodag->root = false; + dodag->was_root = false; dodag->have_config = false; dodag->used = false; dodag->g_mop_prf = g_mop_prf; @@ -678,15 +709,9 @@ void rpl_delete_dodag_root(rpl_dodag_t *dodag) { // This should trigger immediate poison rpl_instance_set_dodag_version(dodag->instance, NULL, RPL_RANK_INFINITE); - // Deleting DODAG is not ideal - we will just pick up adverts from our - // former children, and recreate, possibly violating the MaxRankIncrease. - // Should retain DODAG version info and just unset root flag, which will - // limit what happens when we hear adverts. - // Problem is rpl_control_create_dodag_root which can't handle the - // case where DODAG already exists. This would always be a problem if - // we'd heard adverts in between delete and create, but would be an instant - // problem without this delete. Need to fix. - rpl_delete_dodag(dodag); + // Retain DODAG version info and just unset root flag + // We have was_root still set which will drop adverts for this dodag. + dodag->root = false; } /* Convert RPL configuration to generic trickle parameters. Returns true if @@ -792,6 +817,7 @@ void rpl_dodag_set_root(rpl_dodag_t *dodag, bool root) dodag->root = root; if (root) { rpl_instance_remove_parents(dodag->instance); + dodag->was_root = true; } else { rpl_instance_run_parent_selection(dodag->instance); } @@ -803,6 +829,11 @@ bool rpl_dodag_am_root(const rpl_dodag_t *dodag) { return dodag->root; } + +bool rpl_dodag_was_root(const rpl_dodag_t *dodag) +{ + return dodag->was_root; +} #endif void rpl_dodag_set_leaf(rpl_dodag_t *dodag, bool leaf) @@ -1163,10 +1194,20 @@ static rpl_neighbour_t *rpl_instance_choose_worst_neighbour(const rpl_instance_t { rpl_neighbour_t *worst = NULL; bool worst_acceptable = false; + bool worst_old = false; /* Parents will be first - loop backwards so we take non-parents first */ ns_list_foreach_reverse(rpl_neighbour_t, neighbour, &instance->candidate_neighbours) { bool acceptable = instance->of->neighbour_acceptable(instance, neighbour); + bool old; + if (!neighbour->dodag_version) { + old = true; + } else { + uint32_t age = protocol_core_monotonic_time - neighbour->dio_timestamp; + uint32_t age_threshold = rpl_dio_imax_time_calculate(neighbour->dodag_version->dodag->dio_timer_params.Imax, + rpl_policy_dio_validity_period(instance->domain)); + old = age > age_threshold; + } if (!worst) { goto new_worst; } @@ -1176,6 +1217,13 @@ static rpl_neighbour_t *rpl_instance_choose_worst_neighbour(const rpl_instance_t break; } + /* Prefer neighbours with DODAG version */ + if (neighbour->dodag_version && !worst->dodag_version) { + continue; + } else if (!neighbour->dodag_version && worst->dodag_version) { + goto new_worst; + } + /* Prefer to purge "unacceptable" neighbours according to OF */ if (acceptable && !worst_acceptable) { continue; @@ -1183,18 +1231,24 @@ static rpl_neighbour_t *rpl_instance_choose_worst_neighbour(const rpl_instance_t goto new_worst; } - /* Prefer to purge least-recently-heard-from */ - uint32_t neighbour_age = protocol_core_monotonic_time - neighbour->dio_timestamp; - uint32_t worst_age = protocol_core_monotonic_time - worst->dio_timestamp; - if (neighbour_age <= worst_age) { + /* Prefer to purge old neighbours */ + if (old && !worst_old) { continue; - } else { + } else if (!old && worst_old) { goto new_worst; } + /* Tiebreak by path cost, assuming we have dodag_version */ + if (neighbour->dodag_version && instance->of) { + /* worst must also have version to reach this tiebreak */ + if (instance->of->path_cost(neighbour) <= instance->of->path_cost(worst)) { + continue; + } + } new_worst: worst = neighbour; worst_acceptable = acceptable; + worst_old = old; } return worst; @@ -1225,24 +1279,19 @@ bool rpl_instance_purge(rpl_instance_t *instance) */ rpl_neighbour_t *neighbour = rpl_instance_choose_worst_neighbour(instance); if (neighbour && neighbour->considered && !neighbour->dodag_parent && neighbour->dao_path_control == 0) { + tr_debug("Candidate Purge: Remove %s", trace_ipv6(neighbour->ll_address)); rpl_delete_neighbour(instance, neighbour); return true; } return false; } -void rpl_instance_neighbours_changed(rpl_instance_t *instance, const rpl_dodag_t *dodag) +void rpl_instance_neighbours_changed(rpl_instance_t *instance, rpl_dodag_t *dodag) { instance->neighbours_changed = true; uint16_t delay = rpl_policy_dio_parent_selection_delay(instance->domain); - if (dodag) { - //Convert imin 100ms tick to seconds - uint16_t i_min_delay = dodag->dio_timer_params.Imin / 10; - if (i_min_delay > delay) { - delay = i_min_delay; - } - } - rpl_instance_trigger_parent_selection(instance, delay); + + rpl_instance_trigger_parent_selection(instance, delay, dodag); } static void rpl_instance_remove_parents(rpl_instance_t *instance) @@ -1315,6 +1364,10 @@ void rpl_dodag_update_implicit_system_routes(rpl_dodag_t *dodag, rpl_neighbour_t /* Also add a specific route to the DODAGID */ ipv6_route_add_metric(dodag->id, 128, parent->interface_id, parent->ll_address, ROUTE_RPL_ROOT, parent, dodag->instance->id, default_lifetime, metric); + /* Check if we assume default route to DODAGID */ + if (!dodag->instance->domain->process_routes) { + ipv6_route_add_metric(NULL, 0, parent->interface_id, parent->ll_address, ROUTE_RPL_ROOT, parent, dodag->instance->id, default_lifetime, metric); + } } /* Called when a DIO RIO route has been updated (but not the parent list) */ @@ -1323,9 +1376,13 @@ static void rpl_dodag_update_system_route(rpl_dodag_t *dodag, rpl_dio_route_t *r if (!rpl_dodag_is_current(dodag)) { return; } - rpl_instance_t *instance = dodag->instance; + if (!instance->domain->process_routes) { + // We dont add actual routes and only create default route throuh DODAGID + return; + } + ns_list_foreach(rpl_neighbour_t, neighbour, &instance->candidate_neighbours) { if (neighbour->dodag_parent) { rpl_instance_update_system_dio_route(instance, neighbour, route); @@ -1340,6 +1397,11 @@ static void rpl_instance_update_system_routes_through_parent(rpl_instance_t *ins rpl_dodag_update_implicit_system_routes(dodag, parent); + if (!instance->domain->process_routes) { + // We dont add actual routes and only create default route through DODAGID + return; + } + /* Then add the specific routes listed in the DIO as ROUTE_RPL_DIO */ ns_list_foreach(rpl_dio_route_t, route, &dodag->routes) { rpl_instance_update_system_dio_route(instance, parent, route); @@ -1381,13 +1443,15 @@ void rpl_instance_run_parent_selection(rpl_instance_t *instance) return; } - if (instance->current_dodag_version && instance->current_dodag_version->dodag->root) { + if (instance->current_dodag_version && + (instance->current_dodag_version->dodag->root || instance->current_dodag_version->dodag->was_root)) { return; } ns_list_foreach_safe(rpl_neighbour_t, n, &instance->candidate_neighbours) { //Remove a Parent candidates which are not heared a long time ago and not slected ones if (!n->dodag_parent && (rpl_aged_lifetime(rpl_default_lifetime(n->dodag_version->dodag), n->dio_timestamp) == 0)) { + tr_debug("Candidate timeout: Remove %s", trace_ipv6(n->ll_address)); rpl_delete_neighbour(instance, n); continue; } @@ -1429,7 +1493,7 @@ void rpl_instance_run_parent_selection(rpl_instance_t *instance) if (original_preferred != preferred_parent) { protocol_stats_update(STATS_RPL_PARENT_CHANGE, 1); if (preferred_parent) { - tr_debug("New preferred parent %s", trace_array(preferred_parent->ll_address, 16)); + tr_info("New preferred parent %s", trace_array(preferred_parent->ll_address, 16)); } } @@ -1479,6 +1543,7 @@ void rpl_instance_run_parent_selection(rpl_instance_t *instance) continue; } if (!instance->of->neighbour_acceptable(instance, n)) { + tr_debug("Candidate not acceptable: Remove %s", trace_ipv6(n->ll_address)); rpl_delete_neighbour(instance, n); } } @@ -1560,7 +1625,9 @@ void rpl_instance_dio_trigger(rpl_instance_t *instance, protocol_interface_info_ conf = &dodag->config; } else if (dodag->new_config_advertisment_count < rpl_policy_dio_multicast_config_advertisment_min_count()) { conf = &dodag->config; - dodag->new_config_advertisment_count++; + if (dodag->new_config_advertisment_count < 0xfe) { + dodag->new_config_advertisment_count++; + } } else { conf = NULL; } @@ -1699,7 +1766,7 @@ bool rpl_instance_address_is_candidate(rpl_instance_t *instance, const uint8_t * return false; } -uint16_t rpl_instance_address_candidate_count(rpl_instance_t *instance, bool selected_parents) +uint16_t rpl_instance_address_candidate_count(const rpl_instance_t *instance, bool selected_parents) { uint16_t parent_list = 0; @@ -1717,7 +1784,6 @@ uint16_t rpl_instance_address_candidate_count(rpl_instance_t *instance, bool sel return parent_list; } - void rpl_instance_neighbor_delete(rpl_instance_t *instance, const uint8_t *ipv6_addr) { ns_list_foreach_safe(rpl_neighbour_t, neighbour, &instance->candidate_neighbours) { @@ -1767,17 +1833,21 @@ void rpl_upward_dio_timer(rpl_instance_t *instance, uint16_t ticks) if (rpl_dodag_am_leaf(dodag) && !instance->poison_count) { return; } - // We dont have any valid address in interface - if (ns_list_count(&instance->dao_targets) == 0) { - return; - } - /* Address registrations for parent ongoing*/ - if (rpl_policy_parent_confirmation_requested() && instance->pending_neighbour_confirmation) { - return; - } - /* If we are waiting for DAO or DAO registration is needed we dont send periodic DIOs */ - if (instance->dao_in_transit || instance->delay_dao_timer > 0) { - return; + /* Delay sending first DIO if we are still potentially gathering info */ + /* Important to always send DIOs if we ever have sent any, so we can indicate problems to others */ + if (!instance->last_advertised_dodag_version && rpl_policy_parent_confirmation_requested()) { + // We dont have any valid address in interface + if (ns_list_count(&instance->dao_targets) == 0) { + return; + } + /* Address registrations for parent ongoing*/ + if (instance->pending_neighbour_confirmation) { + return; + } + /* If we are waiting for DAO or DAO registration is needed we dont send periodic DIOs */ + if (instance->dao_in_transit || instance->delay_dao_timer > 0) { + return; + } } if (trickle_timer(&instance->dio_timer, &dodag->dio_timer_params, ticks)) { instance->dio_not_consistent = false; diff --git a/source/RPL/rpl_upward.h b/source/RPL/rpl_upward.h index 2780f6729a..b3b51b38bc 100644 --- a/source/RPL/rpl_upward.h +++ b/source/RPL/rpl_upward.h @@ -70,6 +70,7 @@ bool rpl_instance_am_root(const rpl_instance_t *instance); uint8_t rpl_instance_mop(const rpl_instance_t *instance); rpl_dodag_version_t *rpl_instance_current_dodag_version(const rpl_instance_t *instance); rpl_neighbour_t *rpl_instance_preferred_parent(const rpl_instance_t *instance); +bool rpl_instance_possible_better_candidate(const rpl_instance_t *instance, rpl_neighbour_t *replacing, uint16_t candidate_rank, uint16_t etx); rpl_dodag_version_t *rpl_instance_predicate_match(rpl_instance_t *instance, uint8_t pred, uint8_t instance_id, const uint8_t *dodagid, uint8_t version_num); void rpl_instance_inconsistency(rpl_instance_t *instance); void rpl_instance_consistent_rx(rpl_instance_t *instance); @@ -77,15 +78,16 @@ void rpl_instance_increment_dtsn(rpl_instance_t *instance); void rpl_dodag_set_pref(rpl_dodag_t *dodag, uint8_t pref); void rpl_instance_poison(rpl_instance_t *instance, uint8_t count); void rpl_instance_force_leaf(rpl_instance_t *instance); -void rpl_instance_trigger_parent_selection(rpl_instance_t *instance, uint16_t delay); +void rpl_instance_trigger_parent_selection(rpl_instance_t *instance, uint16_t delay, rpl_dodag_t *dodag); void rpl_instance_remove_interface(rpl_instance_t *instance, int8_t if_id); void rpl_instance_dio_trigger(rpl_instance_t *instance, struct protocol_interface_info_entry *cur, const uint8_t *addr); void rpl_instance_set_local_repair(rpl_instance_t *instance, bool repair); bool rpl_instance_local_repair(const rpl_instance_t *instance); uint16_t rpl_instance_current_rank(const rpl_instance_t *instance); +uint16_t rpl_instance_candidate_rank(const rpl_neighbour_t *candidate); bool rpl_instance_address_is_parent(rpl_instance_t *instance, const uint8_t *ipv6_addr); bool rpl_instance_address_is_candidate(rpl_instance_t *instance, const uint8_t *ipv6_addr, uint16_t candidate_amount); -uint16_t rpl_instance_address_candidate_count(rpl_instance_t *instance, bool selected_parents); +uint16_t rpl_instance_address_candidate_count(const rpl_instance_t *instance, bool selected_parents); void rpl_instance_neighbor_delete(rpl_instance_t *instance, const uint8_t *ipv6_addr); void rpl_instance_slow_timer(rpl_instance_t *instance, uint16_t seconds); @@ -97,8 +99,10 @@ uint8_t rpl_dodag_mop(const rpl_dodag_t *dodag); void rpl_dodag_set_root(rpl_dodag_t *dodag, bool root); #ifdef HAVE_RPL_ROOT bool rpl_dodag_am_root(const rpl_dodag_t *dodag); +bool rpl_dodag_was_root(const rpl_dodag_t *dodag); #else #define rpl_dodag_am_root(dodag) false +#define rpl_dodag_was_root(dodag) false #endif uint8_t rpl_dodag_get_version_number_as_root(const rpl_dodag_t *dodag); void rpl_dodag_set_version_number_as_root(rpl_dodag_t *dodag, uint8_t number); @@ -131,6 +135,7 @@ void rpl_dodag_version_raise_greediness(rpl_dodag_version_t *version, uint16_t p bool rpl_dodag_version_rank_indicates_possible_sub_dodag(const rpl_dodag_version_t *version, uint16_t rank); rpl_neighbour_t *rpl_lookup_neighbour_by_ll_address(const rpl_instance_t *instance, const uint8_t *addr, int8_t if_id); +rpl_neighbour_t *rpl_lookup_last_candidate_from_list(const rpl_instance_t *instance); rpl_neighbour_t *rpl_create_neighbour(rpl_dodag_version_t *instance, const uint8_t *ll_addr, int8_t if_id, uint8_t g_mop_prf, uint8_t dtsn); void rpl_delete_neighbour(rpl_instance_t *instance, rpl_neighbour_t *neighbour); bool rpl_dodag_update_config(rpl_dodag_t *dodag, const rpl_dodag_conf_t *conf, const uint8_t *src, bool *become_leaf); @@ -142,7 +147,7 @@ bool rpl_neighbour_update_dtsn(rpl_neighbour_t *neighbour, uint8_t dtsn); rpl_instance_t *rpl_neighbour_instance(const rpl_neighbour_t *neighbour); -void rpl_instance_neighbours_changed(rpl_instance_t *instance, const rpl_dodag_t *dodag); +void rpl_instance_neighbours_changed(rpl_instance_t *instance, rpl_dodag_t *dodag); void rpl_instance_run_parent_selection(rpl_instance_t *instance); void rpl_upward_print_instance(rpl_instance_t *instance, route_print_fn_t *print_fn); diff --git a/source/Security/TLS/tls_lib.c b/source/Security/TLS/tls_lib.c index b4596c9f4a..f23517a62c 100644 --- a/source/Security/TLS/tls_lib.c +++ b/source/Security/TLS/tls_lib.c @@ -229,6 +229,7 @@ uint8_t tls_parse_client_hello(uint8_t *ptr, uint16_t len, sec_suite_t *tls_suit case TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8: thep->client_knows_standard_ecc_ciphersuite = true; /* no break */ + /* fall through */ case TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8_COMPAT: tr_debug("Client Sup ECC"); ret_val |= SEC_CIPHERSUITE_ECC; diff --git a/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c b/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c index 40a5c2eccd..bc61ab1ac6 100644 --- a/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c +++ b/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c @@ -53,16 +53,24 @@ typedef enum { EAP_TLS_STATE_FINISHED = SEC_STATE_FINISHED } eap_tls_sec_prot_state_e; +// Filters initial EAPOL-key re-transmission bursts +#define BURST_FILTER_TIMER_TIMEOUT 5 * 10 + +// How many times initial EAPOL-key is accepted on wait for identity response state +#define INITIAL_EAPOL_KEY_MAX_COUNT 2 + typedef struct { sec_prot_common_t common; /**< Common data */ sec_prot_t *tls_prot; /**< TLS security protocol */ eapol_pdu_t recv_eapol_pdu; /**< Received EAPOL PDU */ tls_data_t tls_send; /**< EAP-TLS send buffer */ tls_data_t tls_recv; /**< EAP-TLS receive buffer */ + uint16_t burst_filt_timer; /**< Burst filter timer */ uint8_t eap_id_seq; /**< EAP sequence */ uint8_t recv_eap_id_seq; /**< Last received EAP sequence */ uint8_t eap_code; /**< Received EAP code */ uint8_t eap_type; /**< Received EAP type */ + uint8_t init_key_cnt; /**< How many time initial EAPOL-key has been received */ int8_t tls_result; /**< Result of TLS operation */ bool wait_tls: 1; /**< Wait TLS (ECC calculation) before sending EAP-TLS message */ bool tls_ongoing: 1; /**< TLS handshake is ongoing */ @@ -151,13 +159,15 @@ static int8_t auth_eap_tls_sec_prot_init(sec_prot_t *prot) sec_prot_state_set(prot, &data->common, EAP_TLS_STATE_INIT); data->tls_prot = NULL; + data->burst_filt_timer = BURST_FILTER_TIMER_TIMEOUT; data->eap_id_seq = 0; data->recv_eap_id_seq = 0; data->eap_code = 0; data->eap_type = 0; eap_tls_sec_prot_lib_message_init(&data->tls_recv); eap_tls_sec_prot_lib_message_init(&data->tls_send); - data->tls_result = EAP_TLS_RESULT_ERROR; + data->tls_result = EAP_TLS_RESULT_ERROR; + data->init_key_cnt = 0; data->wait_tls = false; data->tls_ongoing = false; data->send_pending = false; @@ -186,13 +196,31 @@ static int8_t auth_eap_tls_sec_prot_receive(sec_prot_t *prot, void *pdu, uint16_ // Decoding is successful if (eapol_parse_pdu_header(pdu, size, &data->recv_eapol_pdu)) { - // Handle only EAP messages (ignore initial EAPOL-key retransmissions) + // Handle EAP messages if (data->recv_eapol_pdu.packet_type == EAPOL_EAP_TYPE) { data->eap_code = data->recv_eapol_pdu.msg.eap.eap_code; data->eap_type = data->recv_eapol_pdu.msg.eap.type; // Call state machine prot->state_machine(prot); + } else if (data->recv_eapol_pdu.packet_type == EAPOL_KEY_TYPE && + sec_prot_state_get(&data->common) == EAP_TLS_STATE_RESPONSE_ID) { + /* If initial EAPOL-key transmission arrives to first EAP-TLS wait state i.e. + * when waiting for identity response, triggers re-transmission of identity + * request. This allows the supplicant to start EAP-TLS right away, if it has + * missed the original identity request. + */ + if (data->burst_filt_timer == 0 && data->init_key_cnt < INITIAL_EAPOL_KEY_MAX_COUNT) { + tr_info("EAP-TLS: initial EAPOL-key recv, eui-64: %s", trace_array(sec_prot_remote_eui_64_addr_get(prot), 8)); + sec_prot_result_set(&data->common, SEC_RESULT_TIMEOUT); + // Call state machine + prot->state_machine(prot); + // Resets trickle timer to give time for supplicant to answer + sec_prot_timer_trickle_start(&data->common, &eap_tls_trickle_params); + data->init_key_cnt++; + } + // Filters repeated initial EAPOL-key messages + data->burst_filt_timer = BURST_FILTER_TIMER_TIMEOUT; } ret_val = 0; } @@ -288,6 +316,13 @@ static int8_t auth_eap_tls_sec_prot_message_send(sec_prot_t *prot, uint8_t eap_c static void auth_eap_tls_sec_prot_timer_timeout(sec_prot_t *prot, uint16_t ticks) { eap_tls_sec_prot_int_t *data = eap_tls_sec_prot_get(prot); + + if (data->burst_filt_timer > ticks) { + data->burst_filt_timer -= ticks; + } else { + data->burst_filt_timer = 0; + } + sec_prot_timer_timeout_handle(prot, &data->common, &eap_tls_trickle_params, ticks); } diff --git a/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c b/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c index b80a43cc40..bac7ecceb4 100644 --- a/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c +++ b/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c @@ -72,10 +72,10 @@ typedef struct { bool send_pending: 1; /**< TLS data is not yet send to network */ } eap_tls_sec_prot_int_t; -#define FWH_RETRY_TIMEOUT_SMALL 330*10 // retry timeout for small network additional 30 seconds for authenticator delay -#define FWH_RETRY_TIMEOUT_LARGE 750*10 // retry timeout for large network additional 30 seconds for authenticator delay +#define EAP_TLS_RETRY_TIMEOUT_SMALL 330*10 // retry timeout for small network additional 30 seconds for authenticator delay +#define EAP_TLS_RETRY_TIMEOUT_LARGE 750*10 // retry timeout for large network additional 30 seconds for authenticator delay -static uint16_t retry_timeout = FWH_RETRY_TIMEOUT_SMALL; +static uint16_t retry_timeout = EAP_TLS_RETRY_TIMEOUT_SMALL; static uint16_t supp_eap_tls_sec_prot_size(void); static int8_t supp_eap_tls_sec_prot_init(sec_prot_t *prot); @@ -93,7 +93,7 @@ static void supp_eap_tls_sec_prot_timer_timeout(sec_prot_t *prot, uint16_t ticks static int8_t supp_eap_tls_sec_prot_init_tls(sec_prot_t *prot); static void supp_eap_tls_sec_prot_delete_tls(sec_prot_t *prot); -static void supp_eap_tls_sec_prot_seq_id_update(sec_prot_t *prot); +static bool supp_eap_tls_sec_prot_seq_id_update(sec_prot_t *prot); #define eap_tls_sec_prot_get(prot) (eap_tls_sec_prot_int_t *) &prot->data @@ -113,9 +113,9 @@ int8_t supp_eap_tls_sec_prot_register(kmp_service_t *service) int8_t supp_eap_sec_prot_timing_adjust(uint8_t timing) { if (timing < 16) { - retry_timeout = FWH_RETRY_TIMEOUT_SMALL; + retry_timeout = EAP_TLS_RETRY_TIMEOUT_SMALL; } else { - retry_timeout = FWH_RETRY_TIMEOUT_LARGE; + retry_timeout = EAP_TLS_RETRY_TIMEOUT_LARGE; } return 0; } @@ -493,7 +493,10 @@ static void supp_eap_tls_sec_prot_state_machine(sec_prot_t *prot) } // Store sequence ID - supp_eap_tls_sec_prot_seq_id_update(prot); + if (supp_eap_tls_sec_prot_seq_id_update(prot)) { + // When receiving a new sequence number, adds more time for re-send if no response + data->common.ticks = retry_timeout; + } // All fragments received for a message if (result == EAP_TLS_MSG_RECEIVE_DONE && data->tls_ongoing) { @@ -524,10 +527,6 @@ static void supp_eap_tls_sec_prot_state_machine(sec_prot_t *prot) // Send EAP response supp_eap_tls_sec_prot_message_send(prot, EAP_RESPONSE, EAP_TLS, EAP_TLS_EXCHANGE_ONGOING); data->send_pending = false; - - // Add more time for re-send if no response - data->common.ticks = retry_timeout; - break; case EAP_TLS_STATE_FINISH: @@ -550,10 +549,16 @@ static void supp_eap_tls_sec_prot_state_machine(sec_prot_t *prot) } } -static void supp_eap_tls_sec_prot_seq_id_update(sec_prot_t *prot) +static bool supp_eap_tls_sec_prot_seq_id_update(sec_prot_t *prot) { eap_tls_sec_prot_int_t *data = eap_tls_sec_prot_get(prot); + bool new_seq_id = false; + + if (data->recv_eapol_pdu.msg.eap.id_seq > data->eap_id_seq) { + new_seq_id = true; + } data->eap_id_seq = data->recv_eapol_pdu.msg.eap.id_seq; + return new_seq_id; } #endif /* HAVE_WS */ diff --git a/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c b/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c index 5c0a48393d..02b32b729f 100644 --- a/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c +++ b/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c @@ -414,7 +414,8 @@ static void auth_fwh_sec_prot_state_machine(sec_prot_t *prot) if (auth_fwh_sec_prot_mic_validate(prot) < 0) { return; } - + // PTK is fresh for installing any GTKs + sec_prot_keys_ptk_installed_gtk_hash_clear_all(prot->sec_keys); // If GTK was inserted set it valid sec_prot_keys_gtkl_from_gtk_insert_index_set(prot->sec_keys); // Reset PTK mismatch diff --git a/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c b/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c index 50a9691b33..b4206f69b4 100644 --- a/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c +++ b/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c @@ -315,6 +315,9 @@ static void auth_gkh_sec_prot_state_machine(sec_prot_t *prot) sec_prot_timer_trickle_start(&data->common, &gkh_trickle_params); sec_prot_state_set(prot, &data->common, GKH_STATE_MESSAGE_2); + + // Store the hash for to-be installed GTK as used for the PTK + sec_prot_keys_ptk_installed_gtk_hash_set(prot->sec_keys); break; // Wait GKH message 2 diff --git a/source/Security/protocols/key_sec_prot/key_sec_prot.c b/source/Security/protocols/key_sec_prot/key_sec_prot.c index ba56a7566c..409546c3dc 100644 --- a/source/Security/protocols/key_sec_prot/key_sec_prot.c +++ b/source/Security/protocols/key_sec_prot/key_sec_prot.c @@ -318,10 +318,10 @@ static int8_t key_sec_prot_tx_status_ind(sec_prot_t *prot, sec_prot_tx_status_e // Indicates TX failure if (tx_status == SEC_PROT_TX_ERR_TX_NO_ACK) { - sec_prot_result_set(&data->common, KMP_RESULT_ERR_TX_NO_ACK); + sec_prot_result_set(&data->common, SEC_RESULT_ERR_TX_NO_ACK); } else if (tx_status != SEC_PROT_TX_OK) { // Indicates other failure - sec_prot_result_set(&data->common, KMP_RESULT_ERR_UNSPEC); + sec_prot_result_set(&data->common, SEC_RESULT_ERR_UNSPEC); } prot->state_machine_call(prot); return 0; diff --git a/source/Security/protocols/sec_prot_keys.c b/source/Security/protocols/sec_prot_keys.c index 9a0d4c8a43..cdcc31de32 100644 --- a/source/Security/protocols/sec_prot_keys.c +++ b/source/Security/protocols/sec_prot_keys.c @@ -38,6 +38,8 @@ #define TRACE_GROUP "spke" +static const uint8_t empty_hash[GTK_HASH_LEN] = {0}; + sec_prot_keys_t *sec_prot_keys_create(sec_prot_gtk_keys_t *gtks, const sec_prot_certs_t *certs) { sec_prot_keys_t *sec_keys = ns_dyn_mem_alloc(sizeof(sec_prot_keys_t)); @@ -67,6 +69,7 @@ void sec_prot_keys_init(sec_prot_keys_t *sec_keys, sec_prot_gtk_keys_t *gtks, co sec_keys->ptk_eui_64_set = false; sec_keys->pmk_mismatch = false; sec_keys->ptk_mismatch = false; + sec_prot_keys_ptk_installed_gtk_hash_clear_all(sec_keys); } void sec_prot_keys_delete(sec_prot_keys_t *sec_keys) @@ -581,9 +584,22 @@ void sec_prot_keys_gtks_hash_generate(sec_prot_gtk_keys_t *gtks, uint8_t *gtkhas } } -void sec_prot_keys_gtk_hash_generate(uint8_t *gtk, uint8_t *gtk_hash) +int8_t sec_prot_keys_gtk_hash_generate(uint8_t *gtk, uint8_t *gtk_hash) { + return sec_prot_lib_gtkhash_generate(gtk, gtk_hash); +} + +int8_t sec_prot_keys_gtk_valid_check(uint8_t *gtk) +{ + uint8_t gtk_hash[8]; sec_prot_lib_gtkhash_generate(gtk, gtk_hash); + + // Checks if GTK hash for the GTK would be all zero + if (memcmp(gtk_hash, empty_hash, GTK_HASH_LEN) == 0) { + return -1; + } + + return 0; } gtk_mismatch_e sec_prot_keys_gtks_hash_update(sec_prot_gtk_keys_t *gtks, uint8_t *gtkhash) @@ -639,7 +655,6 @@ gtk_mismatch_e sec_prot_keys_gtks_hash_update(sec_prot_gtk_keys_t *gtks, uint8_t bool sec_prot_keys_gtk_hash_empty(uint8_t *gtkhash) { - const uint8_t empty_hash[GTK_HASH_LEN] = {0}; if (memcmp(gtkhash, empty_hash, GTK_HASH_LEN) == 0) { return true; } else { @@ -783,4 +798,57 @@ uint8_t sec_prot_keys_gtk_count(sec_prot_gtk_keys_t *gtks) return count; } +void sec_prot_keys_ptk_installed_gtk_hash_clear_all(sec_prot_keys_t *sec_keys) +{ + for (uint8_t index = 0; index < GTK_NUM; index++) { + memset(sec_keys->ins_gtk_hash[sec_keys->gtk_set_index].hash, 0, INS_GTK_HASH_LEN); + } + sec_keys->ins_gtk_hash_set = 0; +} + +void sec_prot_keys_ptk_installed_gtk_hash_set(sec_prot_keys_t *sec_keys) +{ + if (sec_keys->gtk_set_index >= 0) { + uint8_t *gtk = sec_prot_keys_gtk_get(sec_keys->gtks, sec_keys->gtk_set_index); + if (!gtk) { + return; + } + uint8_t gtk_hash[GTK_HASH_LEN]; + if (sec_prot_keys_gtk_hash_generate(gtk, gtk_hash) < 0) { + return; + } + /* Store two byte hash. This is long enough for the GTK installed check, since + * possible conflict between hashes causes only that 4WH is initiated/is not + * initiated instead of GKH. + */ + memcpy(sec_keys->ins_gtk_hash[sec_keys->gtk_set_index].hash, gtk_hash, INS_GTK_HASH_LEN); + sec_keys->ins_gtk_hash_set |= (1 << sec_keys->gtk_set_index); + } +} + +bool sec_prot_keys_ptk_installed_gtk_hash_mismatch_check(sec_prot_keys_t *sec_keys, uint8_t gtk_index) +{ + if ((sec_keys->ins_gtk_hash_set & (1 << sec_keys->gtk_set_index)) == 0) { + return false; + } + + uint8_t *gtk = sec_prot_keys_gtk_get(sec_keys->gtks, gtk_index); + if (!gtk) { + return false; + } + + // Calculated GTK hash for the current GTK on the defined index + uint8_t gtk_hash[GTK_HASH_LEN]; + if (sec_prot_keys_gtk_hash_generate(gtk, gtk_hash) < 0) { + return false; + } + + // If PTK has been used to install different GTK to index than the current one, trigger mismatch + if (memcmp(sec_keys->ins_gtk_hash[sec_keys->gtk_set_index].hash, gtk_hash, INS_GTK_HASH_LEN) != 0) { + return true; + } + + return false; +} + #endif /* HAVE_WS */ diff --git a/source/Security/protocols/sec_prot_keys.h b/source/Security/protocols/sec_prot_keys.h index 4a14fc2b6f..9df422934b 100644 --- a/source/Security/protocols/sec_prot_keys.h +++ b/source/Security/protocols/sec_prot_keys.h @@ -54,6 +54,7 @@ #define GTK_HASH_LEN 8 #define GTK_ALL_HASHES_LEN GTK_HASH_LEN * GTK_NUM +#define INS_GTK_HASH_LEN 2 #define PMK_LIFETIME_INSTALL 0xFFFFF #define PTK_LIFETIME_INSTALL 0xFFFFF @@ -71,18 +72,24 @@ typedef struct { bool updated: 1; /**< Group Transient Keys has been updated */ } sec_prot_gtk_keys_t; +typedef struct { + uint8_t hash[INS_GTK_HASH_LEN]; /**< Inserted GTKs for a PTK hash */ +} sec_prot_gtk_hash_t; + // Security key data typedef struct { uint64_t pmk_key_replay_cnt; /**< Pairwise Master Key replay counter */ uint8_t pmk[PMK_LEN]; /**< Pairwise Master Key (256 bits) */ uint8_t ptk[PTK_LEN]; /**< Pairwise Transient Key (384 bits) */ uint8_t ptk_eui_64[8]; /**< Remote EUI-64 used to derive PTK or NULL */ + sec_prot_gtk_hash_t ins_gtk_hash[GTK_NUM]; /**< Hashes for inserted GTKs for a PTK */ sec_prot_gtk_keys_t *gtks; /**< Group Transient Keys */ const sec_prot_certs_t *certs; /**< Certificates */ uint32_t pmk_lifetime; /**< PMK lifetime in seconds */ uint32_t ptk_lifetime; /**< PTK lifetime in seconds */ uint8_t gtkl; /**< Remote GTKL information */ int8_t gtk_set_index; /**< Index of GTK to set */ + unsigned ins_gtk_hash_set: 4; /**< Hash for inserted GTKs for a PTK set */ bool pmk_set: 1; /**< Pairwise Master Key set */ bool ptk_set: 1; /**< Pairwise Transient Key set */ bool pmk_key_replay_cnt_set: 1; /**< Pairwise Master Key replay counter set */ @@ -95,7 +102,8 @@ typedef struct { // Frame counter data typedef struct { uint8_t gtk[GTK_LEN]; /**< GTK of the frame counter */ - uint32_t frame_counter; /**< Frame counter */ + uint32_t frame_counter; /**< Current frame counter */ + uint32_t stored_frame_counter; /**< Stored Frame counter */ bool set : 1; /**< Value has been set */ } frame_counter_t; @@ -649,8 +657,20 @@ void sec_prot_keys_gtks_hash_generate(sec_prot_gtk_keys_t *gtks, uint8_t *gtk_ha * \param gtk GTK key * \param gtk_hash GTK hash for a GTK * + * \return < 0 failure + * \return >= 0 success */ -void sec_prot_keys_gtk_hash_generate(uint8_t *gtk, uint8_t *gtk_hash); +int8_t sec_prot_keys_gtk_hash_generate(uint8_t *gtk, uint8_t *gtk_hash); + +/** + * sec_prot_keys_gtk_valid_check check if GTK is valid + * + * \param gtk GTK key + * + * \return < 0 failure + * \return >= 0 success + */ +int8_t sec_prot_keys_gtk_valid_check(uint8_t *gtk); /** * sec_prot_keys_gtks_hash_update update GTKs based on GTK hash @@ -751,4 +771,30 @@ int8_t sec_prot_keys_gtk_install_index_get(sec_prot_gtk_keys_t *gtks); */ uint8_t sec_prot_keys_gtk_count(sec_prot_gtk_keys_t *gtks); +/** + * sec_prot_keys_ptk_installed_gtk_hash_clear_all clear GTK hashes of the GTKs that has been installed + * to supplicant using the PTK + * \param sec_keys security keys + * + */ +void sec_prot_keys_ptk_installed_gtk_hash_clear_all(sec_prot_keys_t *sec_keys); + +/** + * sec_prot_keys_ptk_installed_gtk_hash_set set GTK hash of the GTK that has been installed + * to supplicant using the current PTK + * + * \param sec_keys security keys + * + */ +void sec_prot_keys_ptk_installed_gtk_hash_set(sec_prot_keys_t *sec_keys); + +/** + * sec_prot_keys_ptk_installed_gtk_hash_set check if PTK is being used to store new GTK for the index + * for the supplicant i.e. GTK hash would change + * + * \param sec_keys security keys + * + */ +bool sec_prot_keys_ptk_installed_gtk_hash_mismatch_check(sec_prot_keys_t *sec_keys, uint8_t gtk_index); + #endif /* SEC_PROT_KEYS_H_ */ diff --git a/source/Service_Libs/Trickle/trickle.c b/source/Service_Libs/Trickle/trickle.c index 5eaa8a1fa6..77e58d09ad 100644 --- a/source/Service_Libs/Trickle/trickle.c +++ b/source/Service_Libs/Trickle/trickle.c @@ -49,6 +49,26 @@ void trickle_start(trickle_t *t, const trickle_params_t *params) trickle_begin_interval(t); } +uint32_t trickle_timer_max(const trickle_params_t *params, uint8_t trickle_timer_expiration) +{ + trickle_time_t time_I = params->Imin - 1; + uint32_t total_time = time_I; + while (trickle_timer_expiration) { + if (time_I <= TRICKLE_TIME_MAX / 2) { + time_I *= 2; + } else { + time_I = TRICKLE_TIME_MAX; + } + + if (time_I > params->Imax) { + time_I = params->Imax; + } + total_time += time_I; + trickle_timer_expiration--; + } + return total_time; +} + /* We don't expose the raw reset as API; users should use "inconsistent_heard". * This avoids repeated resets stopping transmission by restarting the interval. */ diff --git a/source/Service_Libs/Trickle/trickle.h b/source/Service_Libs/Trickle/trickle.h index 60ffa25f81..a6c957826c 100644 --- a/source/Service_Libs/Trickle/trickle.h +++ b/source/Service_Libs/Trickle/trickle.h @@ -76,5 +76,10 @@ bool trickle_running(const trickle_t *t, const trickle_params_t *params); /* Stop the timer (by setting e to infinite) */ void trickle_stop(trickle_t *t); +/* + * Call return max time after n count expiration period 0 return 1 Imin - 1 period + * + */ +uint32_t trickle_timer_max(const trickle_params_t *params, uint8_t trickle_timer_expiration); #endif /* TRICKLE_H_ */ diff --git a/source/Service_Libs/blacklist/blacklist.c b/source/Service_Libs/blacklist/blacklist.c index 25d0666638..f47b2097bf 100644 --- a/source/Service_Libs/blacklist/blacklist.c +++ b/source/Service_Libs/blacklist/blacklist.c @@ -87,7 +87,7 @@ bool blacklist_reject(const uint8_t *ll64_address) if (blacklist_entry) { // If address is blacklisted rejects if (blacklist_entry->ttl > blacklist_data->blacklist_entry_lifetime) { - tr_debug("blacklist reject: %s", trace_array(ll64_address + 8, 8)); + tr_info("blacklist reject: %s", trace_array(ll64_address + 8, 8)); return true; // Neighbor heard; updates blacklist entry TTL to full lifetime } else { @@ -131,7 +131,7 @@ void blacklist_update(const uint8_t *ll64_address, bool success) // On successful link establishment remove address from blacklist if (success) { if (blacklist_entry) { - tr_debug("Blacklist removed"); + tr_info("Blacklist removed"); blacklist_entry_free(blacklist_entry); } // On failure add address to blacklist or update timeout @@ -144,7 +144,7 @@ void blacklist_update(const uint8_t *ll64_address, bool success) /* TTL is blacklist entry lifetime + from 1.0 to 1.5 * interval */ blacklist_entry->ttl = blacklist_data->blacklist_entry_lifetime + randLIB_randomise_base(blacklist_entry->interval, 0x8000, 0xC000); } else { - tr_debug("Blacklist add"); + tr_info("Blacklist add"); blacklist_entry_add(ll64_address + 8); } } @@ -209,7 +209,7 @@ void blacklist_ttl_update(uint16_t ticks) if (blacklist_entry->ttl > ticks) { blacklist_entry->ttl -= ticks; } else { - tr_debug("Blacklist remove entry: %s", trace_array(blacklist_entry->eui64, 8)); + tr_info("Blacklist remove entry: %s", trace_array(blacklist_entry->eui64, 8)); blacklist_entry_free(blacklist_entry); } } diff --git a/source/Service_Libs/etx/etx.c b/source/Service_Libs/etx/etx.c index 60dc5a91fc..639490981a 100644 --- a/source/Service_Libs/etx/etx.c +++ b/source/Service_Libs/etx/etx.c @@ -62,11 +62,13 @@ typedef struct { etx_storage_t *etx_storage_list; etx_sample_storage_t *etx_cache_storage_list; uint32_t max_etx_update; + uint32_t max_etx; uint16_t hysteresis; // 12 bit fraction + uint16_t init_etx_sample_count; uint8_t accum_threshold; uint8_t etx_min_sampling_time; uint8_t ext_storage_list_size; - uint8_t min_sample_count; + uint8_t min_attempts_count; bool cache_sample_requested; int8_t interface_id; } ext_info_t; @@ -79,8 +81,10 @@ static ext_info_t etx_info = { .etx_storage_list = NULL, .etx_cache_storage_list = NULL, .ext_storage_list_size = 0, - .min_sample_count = 0, + .min_attempts_count = 0, .max_etx_update = 0, + .max_etx = 0xffff, + .init_etx_sample_count = 1, .cache_sample_requested = false, .etx_min_sampling_time = 0, .interface_id = -1 @@ -89,7 +93,9 @@ static ext_info_t etx_info = { static void etx_calculation(etx_storage_t *entry, uint16_t attempts, uint8_t acks_rx, uint8_t attribute_index) { if (etx_info.hysteresis && !entry->stored_diff_etx) { - entry->stored_diff_etx = entry->etx; + if (entry->etx_samples >= etx_info.init_etx_sample_count) { + entry->stored_diff_etx = entry->etx; + } } uint32_t etx = attempts << (12 - ETX_MOVING_AVERAGE_FRACTION); @@ -99,11 +105,14 @@ static void etx_calculation(etx_storage_t *entry, uint16_t attempts, uint8_t ack } else { etx = 0xffff; } + if ((etx_info.max_etx_update) && etx > etx_info.max_etx_update) { etx = etx_info.max_etx_update; } - if (etx_info.cache_sample_requested && entry->etx_samples == 1) { + //tr_debug("Attempts %u ACK %u 1/8 update %u", attempts, acks_rx, etx); + + if (etx_info.cache_sample_requested && entry->etx_samples <= etx_info.init_etx_sample_count) { // skip the initial value as RSSI generated ETX is not valid etx = etx << 3; } else { @@ -111,18 +120,20 @@ static void etx_calculation(etx_storage_t *entry, uint16_t attempts, uint8_t ack etx += entry->etx - (entry->etx >> ETX_MOVING_AVERAGE_FRACTION); } - if (etx > 0xffff) { - etx = 0xffff; + if (etx > etx_info.max_etx) { + etx = etx_info.max_etx; } // If real ETX value has been received do not update based on LQI or dBm entry->tmp_etx = false; + entry->etx = etx; - etx_cache_entry_init(attribute_index); - - // Checks if ETX value change callback is needed - etx_value_change_callback_needed_check(entry->etx, &(entry->stored_diff_etx), entry->accumulated_failures, attribute_index); + if (entry->etx_samples >= etx_info.init_etx_sample_count) { + etx_cache_entry_init(attribute_index); + // Checks if ETX value change callback is needed + etx_value_change_callback_needed_check(entry->etx, &(entry->stored_diff_etx), entry->accumulated_failures, attribute_index); + } } static void etx_cache_entry_init(uint8_t attribute_index) @@ -135,7 +146,6 @@ static void etx_cache_entry_init(uint8_t attribute_index) storage->attempts_count = 0; storage->etx_timer = etx_info.etx_min_sampling_time; storage->received_acks = 0; - storage->sample_count = 0; } static bool etx_update_possible(etx_sample_storage_t *storage, etx_storage_t *entry, uint16_t time_update) @@ -148,23 +158,23 @@ static bool etx_update_possible(etx_sample_storage_t *storage, etx_storage_t *en } } - if (entry->etx_samples > ETX_ACCELERATED_SAMPLE_COUNT) { + if (entry->etx_samples > etx_info.init_etx_sample_count) { //Slower ETX update phase - if (storage->sample_count < etx_info.min_sample_count || storage->etx_timer) { - if (storage->sample_count < 0xff) { - return false; + if (storage->attempts_count >= etx_info.min_attempts_count) { + + if (storage->etx_timer == 0 || storage->attempts_count == 0xffff || storage->received_acks == 0xff) { + //Got least min sample in requested time or max possible sample + return true; } } - } else { - //Accelerated ETX at for new neighbor - if (storage->sample_count < ETX_ACCELERATED_INTERVAL) { - return false; - } + return false; } - //tr_debug("ETX update possible %u attempts, %u rx ack", storage->attempts_count, storage->received_acks); + if (time_update == 0) { + return true; + } - return true; + return false; } @@ -176,7 +186,6 @@ static etx_sample_storage_t *etx_cache_sample_update(uint8_t attribute_index, ui if (ack_rx) { storage->received_acks++; } - storage->sample_count++; return storage; } @@ -202,6 +211,7 @@ void etx_transm_attempts_update(int8_t interface_id, uint8_t attempts, bool succ if (!entry) { return; } + if (entry->etx_samples < 7) { entry->etx_samples++; } @@ -211,11 +221,15 @@ void etx_transm_attempts_update(int8_t interface_id, uint8_t attempts, bool succ etx_sample_storage_t *storage = etx_cache_sample_update(attribute_index, attempts, success); entry->accumulated_failures = 0; - if (!entry->etx || (entry->etx_samples > 1 && !etx_update_possible(storage, entry, 0))) { + if (!etx_update_possible(storage, entry, 0)) { return; } etx_calculation(entry, storage->attempts_count, storage->received_acks, attribute_index); + + if (entry->etx_samples < 7 && !success) { + entry->etx_samples = 7; //Stop Probing to failure + } return; } @@ -377,6 +391,13 @@ uint16_t etx_local_etx_read(int8_t interface_id, uint8_t attribute_index) if (!entry) { return 0; } + + if (etx_info.cache_sample_requested && entry->etx_samples < etx_info.init_etx_sample_count) { + if (!entry->etx_samples) { + return 0; + } + } + return etx_current_calc(entry->etx, entry->accumulated_failures) >> 4; } @@ -433,7 +454,12 @@ uint16_t etx_lqi_dbm_update(int8_t interface_id, uint8_t lqi, int8_t dbm, uint8_ if (!entry->etx) { etx = etx_dbm_lqi_calc(lqi, dbm); entry->etx = etx; + entry->stored_diff_etx = etx; entry->tmp_etx = true; + if (etx_info.callback_ptr) { + etx_info.callback_ptr(etx_info.interface_id, 0, entry->etx >> 4, + attribute_index); + } } // If local ETX has been calculated without remote incoming IDR and // remote incoming IDR is available update it by remote incoming IDR value @@ -448,11 +474,7 @@ uint16_t etx_lqi_dbm_update(int8_t interface_id, uint8_t lqi, int8_t dbm, uint8_ entry->etx = etx >> 12; local_incoming_idr >>= 4; - } - - // If local ETX has been calculated indicates new neighbor - if (etx) { - etx_neighbor_add(interface_id, attribute_index); + etx_value_change_callback_needed_check(entry->etx, &(entry->stored_diff_etx), entry->accumulated_failures, attribute_index); } } @@ -585,14 +607,18 @@ bool etx_storage_list_allocate(int8_t interface_id, uint8_t etx_storage_size) } -bool etx_cached_etx_parameter_set(uint8_t min_wait_time, uint8_t etx_min_sample_count) +bool etx_cached_etx_parameter_set(uint8_t min_wait_time, uint8_t etx_min_attempts_count, uint8_t init_etx_sample_count) { //No ini ETX allocation done yet if (etx_info.ext_storage_list_size == 0) { return false; } - if (min_wait_time || etx_min_sample_count) { + if (min_wait_time || etx_min_attempts_count) { + if (init_etx_sample_count == 0) { + return false; + } + if (!etx_info.etx_cache_storage_list) { //allocate etx_info.etx_cache_storage_list = ns_dyn_mem_alloc(sizeof(etx_sample_storage_t) * etx_info.ext_storage_list_size); @@ -615,8 +641,9 @@ bool etx_cached_etx_parameter_set(uint8_t min_wait_time, uint8_t etx_min_sample_ etx_info.etx_cache_storage_list = NULL; } - etx_info.min_sample_count = etx_min_sample_count; + etx_info.min_attempts_count = etx_min_attempts_count; etx_info.etx_min_sampling_time = min_wait_time; + etx_info.init_etx_sample_count = init_etx_sample_count; return true; } @@ -624,12 +651,23 @@ bool etx_cached_etx_parameter_set(uint8_t min_wait_time, uint8_t etx_min_sample_ void etx_max_update_set(uint16_t etx_max_update) { if (etx_max_update) { + //Define MAX ETX UPDATE etx_info.max_etx_update = (etx_max_update / 128) << (12 - ETX_MOVING_AVERAGE_FRACTION); } else { etx_info.max_etx_update = 0; } } +void etx_max_set(uint16_t etx_max) +{ + if (etx_max) { + //Define MAX ETX possible value + etx_info.max_etx = (etx_max / 128) << 12; + } else { + etx_info.max_etx = 0xffff; + } +} + etx_storage_t *etx_storage_entry_get(int8_t interface_id, uint8_t attribute_index) { if (etx_info.interface_id != interface_id || !etx_info.etx_storage_list || attribute_index >= etx_info.ext_storage_list_size) { @@ -698,6 +736,8 @@ static void etx_value_change_callback_needed_check(uint16_t etx, uint16_t *store if (current_etx > *stored_diff_etx) { if (current_etx - *stored_diff_etx >= etx_info.hysteresis) { callback = true; + } else if (current_etx == etx_info.max_etx && *stored_diff_etx != etx_info.max_etx) { + callback = true; } } else if (current_etx < *stored_diff_etx) { if (*stored_diff_etx - current_etx >= etx_info.hysteresis) { @@ -768,35 +808,6 @@ void etx_neighbor_remove(int8_t interface_id, uint8_t attribute_index) } } -/** - * \brief A function to add ETX neighbor - * - * Notifies ETX module that neighbor has been added. Calls ETX value change callback - * if that is set. - * - * \param mac64_addr_ptr long MAC address - * - */ -void etx_neighbor_add(int8_t interface_id, uint8_t attribute_index) -{ - - //tr_debug("Add attribute %u", attribute_index); - uint16_t stored_diff_etx; - etx_storage_t *entry = etx_storage_entry_get(interface_id, attribute_index); - if (entry && etx_info.callback_ptr) { - // Gets table entry - - if (entry->etx) { - stored_diff_etx = entry->stored_diff_etx; - if (!stored_diff_etx) { - stored_diff_etx = entry->etx; - } - etx_info.callback_ptr(etx_info.interface_id, stored_diff_etx >> 4, entry->etx >> 4, - attribute_index); - } - } -} - void etx_cache_timer(int8_t interface_id, uint16_t seconds_update) { if (!etx_info.cache_sample_requested) { diff --git a/source/Service_Libs/etx/etx.h b/source/Service_Libs/etx/etx.h index 55c125456d..c785cc5c98 100644 --- a/source/Service_Libs/etx/etx.h +++ b/source/Service_Libs/etx/etx.h @@ -64,7 +64,6 @@ typedef struct etx_sample_storage_s { uint16_t attempts_count; /*!< TX attempt count */ uint8_t etx_timer; /*!< Count down from configured value 0 means that ETX Update is possible done again*/ uint8_t received_acks; /*!< Received ACK's */ - uint8_t sample_count; /*!< Finished TX count */ } etx_sample_storage_t; /** @@ -237,17 +236,6 @@ uint8_t etx_accum_failures_callback_register(nwk_interface_id nwk_id, int8_t int */ void etx_neighbor_remove(int8_t interface_id, uint8_t attribute_index); -/** - * \brief A function to add ETX neighbor - * - * Notifies ETX module that neighbor has been added. Calls ETX value change callback - * if that is set. - * - * \param attribute_index Neighbour attribute index - * - */ -void etx_neighbor_add(int8_t interface_id, uint8_t attribute_index); - /** * \brief A function for update cached ETX calculation * @@ -266,13 +254,14 @@ void etx_cache_timer(int8_t interface_id, uint16_t seconds_update); * ETX update will happen when min wait time is reached and also reached min etx sample count. * * \param min_wait_time how many seconds must wait before do new ETX - * \param etx_min_sample_count define how many completed TX process must be done for new ETX. Min accepted value is 4. + * \param etx_min_attempts_count define how many TX attempts process must be done for new ETX. Min accepted value is 4. + * \param init_etx_sample_count How Many sample is need to init etx calculate * * \return true Enable is OK * \return false Memory allocation fail * */ -bool etx_cached_etx_parameter_set(uint8_t min_wait_time, uint8_t etx_min_sample_count); +bool etx_cached_etx_parameter_set(uint8_t min_wait_time, uint8_t etx_min_attempts_count, uint8_t init_etx_sample_count); /** @@ -285,4 +274,14 @@ bool etx_cached_etx_parameter_set(uint8_t min_wait_time, uint8_t etx_min_sample_ */ void etx_max_update_set(uint16_t etx_max_update); +/** + * \brief A function for set Maxium ETX value + * + * ETX RFC define that that Max value is 0xffff but this API cuold make that Poor link start go down slowly. + * + * \param etx_max 0 No limit for higher value means. This pameter will change normal ETX which could be 0xffff. + * + */ +void etx_max_set(uint16_t etx_max); + #endif /* ETX_H_ */ diff --git a/source/Service_Libs/fhss/fhss.c b/source/Service_Libs/fhss/fhss.c index 511c07aa98..ae960bc8d0 100644 --- a/source/Service_Libs/fhss/fhss.c +++ b/source/Service_Libs/fhss/fhss.c @@ -1123,8 +1123,9 @@ static void fhss_data_tx_done_callback(const fhss_api_t *api, bool waiting_ack, } } -static bool fhss_data_tx_fail_callback(const fhss_api_t *api, uint8_t handle, int frame_type) +static bool fhss_data_tx_fail_callback(const fhss_api_t *api, uint8_t handle, int frame_type, uint8_t channel) { + (void) channel; fhss_structure_t *fhss_structure = fhss_get_object_with_api(api); if (!fhss_structure) { return false; @@ -1384,7 +1385,9 @@ static void fhss_beacon_tasklet_func(arm_event_s *event) if (!fhss_structure) { return; } +#ifdef FEA_TRACE_SUPPORT uint8_t parent_address[8]; +#endif fhss_clear_active_event(fhss_structure, event->event_type); // skip the init event as there will be a timer event after if (event->event_type == FHSS_TIMER_EVENT) { diff --git a/source/Service_Libs/fhss/fhss_common.c b/source/Service_Libs/fhss/fhss_common.c index d2826ca7e8..0d9dc7c505 100644 --- a/source/Service_Libs/fhss/fhss_common.c +++ b/source/Service_Libs/fhss/fhss_common.c @@ -113,7 +113,10 @@ int8_t fhss_disable(fhss_structure_t *fhss_structure) } fhss_structure->fhss_api->synch_state_set(fhss_structure->fhss_api, FHSS_UNSYNCHRONIZED, 0); ns_dyn_mem_free(fhss_structure->bs); + ns_dyn_mem_free(fhss_structure->ws->tr51_channel_table); + ns_dyn_mem_free(fhss_structure->ws->tr51_output_table); ns_dyn_mem_free(fhss_structure->ws); + fhss_failed_list_free(fhss_structure); ns_dyn_mem_free(fhss_structure); fhss_struct = 0; return 0; diff --git a/source/Service_Libs/fhss/fhss_common.h b/source/Service_Libs/fhss/fhss_common.h index 35e1d0cc46..4d10667924 100644 --- a/source/Service_Libs/fhss/fhss_common.h +++ b/source/Service_Libs/fhss/fhss_common.h @@ -40,6 +40,7 @@ struct fhss_structure { int8_t fhss_event_timer; uint8_t active_fhss_events; uint16_t number_of_channels; + uint16_t optimal_packet_length; fhss_states fhss_state; uint32_t fhss_timeout; uint32_t fhss_timer; diff --git a/source/Service_Libs/fhss/fhss_test_api.c b/source/Service_Libs/fhss/fhss_test_api.c new file mode 100644 index 0000000000..7b1e696ea0 --- /dev/null +++ b/source/Service_Libs/fhss/fhss_test_api.c @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "nsconfig.h" +#include "ns_types.h" +#include "ns_trace.h" +#include "fhss_api.h" +#include "fhss_config.h" +#include "fhss.h" +#include "fhss_common.h" +#include "fhss_ws.h" +#include "fhss_statistics.h" +#include "fhss_channel.h" +#include "channel_list.h" +#include + +#define TRACE_GROUP "fhta" + +int8_t fhss_set_optimal_packet_length(const fhss_api_t *fhss_api, uint16_t packet_length) +{ + (void) fhss_api; + (void) packet_length; +#ifdef HAVE_WS + fhss_structure_t *fhss_structure = fhss_get_object_with_api(fhss_api); + if (!fhss_structure) { + return -1; + } + fhss_structure->optimal_packet_length = packet_length; + fhss_set_txrx_slot_length(fhss_structure); + tr_debug("Setting FHSS optimal packet length to: %u", fhss_structure->optimal_packet_length); +#endif + return 0; +} diff --git a/source/Service_Libs/fhss/fhss_ws.c b/source/Service_Libs/fhss/fhss_ws.c index 452c6e177b..d5272250f8 100644 --- a/source/Service_Libs/fhss/fhss_ws.c +++ b/source/Service_Libs/fhss/fhss_ws.c @@ -83,7 +83,6 @@ static void fhss_event_timer_cb(int8_t timer_id, uint16_t slots); static void fhss_ws_update_uc_channel_callback(fhss_structure_t *fhss_structure); static void fhss_unicast_handler(const fhss_api_t *fhss_api, uint16_t delay); static bool fhss_ws_check_tx_allowed(fhss_structure_t *fhss_structure); -static uint32_t fhss_set_txrx_slot_length(fhss_structure_t *fhss_structure); // This function supports rounding up static int64_t divide_integer(int64_t dividend, int32_t divisor) @@ -147,10 +146,10 @@ fhss_structure_t *fhss_ws_enable(fhss_api_t *fhss_api, const fhss_ws_configurati fhss_struct->fhss_event_timer = eventOS_callback_timer_register(fhss_event_timer_cb); fhss_struct->ws->fhss_configuration = *fhss_configuration; fhss_struct->number_of_channels = channel_count; + fhss_struct->optimal_packet_length = OPTIMAL_PACKET_LENGTH; fhss_ws_set_hop_count(fhss_struct, 0xff); fhss_struct->rx_channel = fhss_configuration->unicast_fixed_channel; fhss_struct->ws->min_synch_interval = DEFAULT_MIN_SYNCH_INTERVAL; - fhss_set_txrx_slot_length(fhss_struct); ns_list_init(&fhss_struct->fhss_failed_tx_list); return fhss_struct; } @@ -173,14 +172,51 @@ static int fhss_ws_manage_channel_table_allocation(fhss_structure_t *fhss_struct return 0; } -static uint32_t fhss_set_txrx_slot_length(fhss_structure_t *fhss_structure) +void fhss_set_txrx_slot_length(fhss_structure_t *fhss_structure) { - uint32_t number_of_tx_slots = ((fhss_structure->ws->fhss_configuration.fhss_broadcast_interval - fhss_structure->ws->fhss_configuration.fhss_bc_dwell_interval) / WS_MAX_TXRX_SLOT_LEN_MS) / 2; + // No broadcast schedule, no TX slots + if (fhss_structure->ws->fhss_configuration.fhss_broadcast_interval == 0 || fhss_structure->ws->fhss_configuration.fhss_bc_dwell_interval == 0) { + return; + } + uint32_t txrx_slot_length_ms_tmp = WS_TXRX_SLOT_LEN_MS; + if (fhss_structure->callbacks.read_datarate) { + /* Calculate minimum TX slot length which can fit optimal packet length twice. + * Twice, because 0, 1, 4, 5... hop starts transmission at the beginning of TX slot and 2, 3, 6, 7... hop at the middle of TX slot + * + * hop 0 + * tx'ing | | | | | | + * | BC | RX | TX | RX | TX | RX | TX | BC | + * hop 1 + * tx'ing | | | | | | + * | BC | TX | RX | TX | RX | TX | RX | BC | + * hop 2 + * tx'ing | | | | | | + * | BC | RX | TX | RX | TX | RX | TX | BC | + * hop 3 + * tx'ing | | | | | | + * | BC | TX | RX | TX | RX | TX | RX | BC | + */ + uint32_t datarate = fhss_structure->callbacks.read_datarate(fhss_structure->fhss_api); + if (datarate) { + txrx_slot_length_ms_tmp = ((fhss_structure->optimal_packet_length * 2) * (8000000 / datarate)) / 1000; + // Do not allow using too high TX slot length. + if (txrx_slot_length_ms_tmp > WS_TXRX_SLOT_LEN_MS) { + tr_debug("TX slot length setting too high %"PRIu32"ms, using %"PRIu32"ms", txrx_slot_length_ms_tmp, (uint32_t)WS_TXRX_SLOT_LEN_MS); + txrx_slot_length_ms_tmp = WS_TXRX_SLOT_LEN_MS; + } + } + } + uint32_t number_of_tx_slots = ((fhss_structure->ws->fhss_configuration.fhss_broadcast_interval - fhss_structure->ws->fhss_configuration.fhss_bc_dwell_interval) / txrx_slot_length_ms_tmp) / 2; if (!number_of_tx_slots) { - return 0; + return; } fhss_structure->ws->txrx_slot_length_ms = (fhss_structure->ws->fhss_configuration.fhss_broadcast_interval - fhss_structure->ws->fhss_configuration.fhss_bc_dwell_interval) / (number_of_tx_slots * 2); - return number_of_tx_slots; + tr_info("TX slot length: %"PRIu32"ms", fhss_structure->ws->txrx_slot_length_ms); +} + +static uint32_t fhss_get_number_of_tx_slots(fhss_structure_t *fhss_structure) +{ + return ((fhss_structure->ws->fhss_configuration.fhss_broadcast_interval - fhss_structure->ws->fhss_configuration.fhss_bc_dwell_interval) / fhss_structure->ws->txrx_slot_length_ms) / 2; } static int32_t fhss_ws_calc_bc_channel(fhss_structure_t *fhss_structure) @@ -193,8 +229,8 @@ static int32_t fhss_ws_calc_bc_channel(fhss_structure_t *fhss_structure) fhss_structure->ws->bc_slot = 0; } } else if (fhss_structure->ws->fhss_configuration.ws_bc_channel_function == WS_DH1CF) { - next_channel = dh1cf_get_bc_channel_index(fhss_structure->ws->bc_slot, fhss_structure->ws->fhss_configuration.bsi, fhss_structure->number_of_channels); fhss_structure->ws->bc_slot++; + next_channel = dh1cf_get_bc_channel_index(fhss_structure->ws->bc_slot, fhss_structure->ws->fhss_configuration.bsi, fhss_structure->number_of_channels); } else if (fhss_structure->ws->fhss_configuration.ws_bc_channel_function == WS_VENDOR_DEF_CF) { if (fhss_structure->ws->fhss_configuration.vendor_defined_cf) { next_channel = fhss_structure->ws->fhss_configuration.vendor_defined_cf(fhss_structure->fhss_api, fhss_structure->ws->bc_slot, NULL, fhss_structure->ws->fhss_configuration.bsi, fhss_structure->number_of_channels); @@ -305,8 +341,11 @@ static void fhss_event_timer_cb(int8_t timer_id, uint16_t slots) { (void) slots; uint16_t queue_size = 0; - fhss_structure_t *fhss_structure = fhss_get_object_with_timer_id(timer_id); + fhss_structure_t *fhss_structure = fhss_get_object_with_timer_id(timer_id); + if (!fhss_structure) { + return; + } if (fhss_structure->ws->is_on_bc_channel == true) { queue_size = fhss_structure->callbacks.read_tx_queue_size(fhss_structure->fhss_api, true); @@ -394,7 +433,7 @@ static int16_t fhss_ws_synch_state_set_callback(const fhss_api_t *api, fhss_stat if (fhss_state == FHSS_SYNCHRONIZED) { uint32_t fhss_broadcast_interval = fhss_structure->ws->fhss_configuration.fhss_broadcast_interval; uint8_t fhss_bc_dwell_interval = fhss_structure->ws->fhss_configuration.fhss_bc_dwell_interval; - + fhss_set_txrx_slot_length(fhss_structure); // Start broadcast schedule when BC intervals are known if (fhss_broadcast_interval && fhss_bc_dwell_interval) { fhss_broadcast_handler(fhss_structure->fhss_api, 0); @@ -407,6 +446,9 @@ static int16_t fhss_ws_synch_state_set_callback(const fhss_api_t *api, fhss_stat } } else if (fhss_state == FHSS_UNSYNCHRONIZED) { fhss_structure->ws->synchronization_time = 0; + eventOS_callback_timer_stop(fhss_structure->fhss_event_timer); + fhss_stop_timer(fhss_structure, fhss_unicast_handler); + fhss_stop_timer(fhss_structure, fhss_broadcast_handler); } fhss_structure->fhss_state = fhss_state; @@ -531,7 +573,7 @@ static bool fhss_ws_check_tx_allowed(fhss_structure_t *fhss_structure) if (fhss_structure->ws->is_on_bc_channel == true) { return true; } - uint32_t number_of_tx_slots = fhss_set_txrx_slot_length(fhss_structure); + uint32_t number_of_tx_slots = fhss_get_number_of_tx_slots(fhss_structure); // Allow transmission when broadcast interval is very short comparing to MAX slot length if (!number_of_tx_slots) { return true; @@ -539,9 +581,22 @@ static bool fhss_ws_check_tx_allowed(fhss_structure_t *fhss_structure) uint32_t remaining_time_ms = get_remaining_slots_us(fhss_structure, fhss_broadcast_handler, MS_TO_US(fhss_structure->ws->fhss_configuration.fhss_broadcast_interval)) / 1000; uint32_t tx_slot_begin_ms = (fhss_structure->ws->fhss_configuration.fhss_broadcast_interval - fhss_structure->ws->fhss_configuration.fhss_bc_dwell_interval) - (fhss_structure->ws->txrx_slot_length_ms * (fhss_structure->own_hop & 1)); + /* Return false when our first TX slot has not yet started + * |------remaining_time_ms---| + * | + * v + * | BC | RX | TX | RX | TX | RX | TX | BC | + */ + if (tx_slot_begin_ms < remaining_time_ms) { + return false; + } tx_slot_begin_ms = tx_slot_begin_ms - (((tx_slot_begin_ms - remaining_time_ms) / (2 * fhss_structure->ws->txrx_slot_length_ms)) * (2 * fhss_structure->ws->txrx_slot_length_ms)); uint32_t rx_slot_begin_ms = tx_slot_begin_ms - fhss_structure->ws->txrx_slot_length_ms; - // Check if we are currently on TX slot. + /* Check if we are currently on TX slot. + * | | | + * v v v + * | BC | RX | TX | RX | TX | RX | TX | BC | + */ if ((remaining_time_ms <= tx_slot_begin_ms) && (remaining_time_ms > rx_slot_begin_ms)) { return true; } @@ -551,6 +606,10 @@ static bool fhss_ws_check_tx_allowed(fhss_structure_t *fhss_structure) static bool fhss_ws_check_tx_time(fhss_structure_t *fhss_structure, uint16_t tx_length, uint8_t phy_header_length, uint8_t phy_tail_length) { + /* + * Check if there is enough time for transmitting before the next multicast slot. + */ +#ifdef FHSS_WS_PROTECT_MC_SLOTS if (!fhss_structure->ws->fhss_configuration.fhss_broadcast_interval || !fhss_structure->ws->fhss_configuration.fhss_bc_dwell_interval) { return true; } @@ -560,6 +619,13 @@ static bool fhss_ws_check_tx_time(fhss_structure_t *fhss_structure, uint16_t tx_ return false; } return true; +#else + (void) fhss_structure; + (void) tx_length; + (void) phy_header_length; + (void) phy_tail_length; + return true; +#endif } static bool fhss_ws_check_tx_conditions_callback(const fhss_api_t *api, bool is_broadcast_addr, uint8_t handle, int frame_type, uint16_t frame_length, uint8_t phy_header_length, uint8_t phy_tail_length) @@ -663,7 +729,7 @@ static void fhss_ws_data_tx_done_callback(const fhss_api_t *api, bool waiting_ac } } -static bool fhss_ws_data_tx_fail_callback(const fhss_api_t *api, uint8_t handle, int frame_type) +static bool fhss_ws_data_tx_fail_callback(const fhss_api_t *api, uint8_t handle, int frame_type, uint8_t channel) { fhss_structure_t *fhss_structure = fhss_get_object_with_api(api); if (!fhss_structure) { @@ -687,7 +753,7 @@ static bool fhss_ws_data_tx_fail_callback(const fhss_api_t *api, uint8_t handle, fhss_failed_handle_remove(fhss_structure, handle); return false; } - fhss_failed_tx->bad_channel = fhss_structure->rx_channel; + fhss_failed_tx->bad_channel = channel; } else { // Create new failure handle and return true to retransmit fhss_failed_handle_add(fhss_structure, handle, fhss_structure->rx_channel); diff --git a/source/Service_Libs/fhss/fhss_ws.h b/source/Service_Libs/fhss/fhss_ws.h index 917b599878..c3d31fa67e 100644 --- a/source/Service_Libs/fhss/fhss_ws.h +++ b/source/Service_Libs/fhss/fhss_ws.h @@ -21,8 +21,10 @@ * At least 4 channel retries must be used: (Initial channel + WS_NUMBER_OF_CHANNEL_RETRIES) * MAC attempts = (1+4)*4=20 attempts */ #define WS_NUMBER_OF_CHANNEL_RETRIES 4 -//TX/RX slot length in milliseconds -#define WS_MAX_TXRX_SLOT_LEN_MS 100 +// TX slot length is optimised to this packet length +#define OPTIMAL_PACKET_LENGTH 500 +// Default TX/RX slot length in milliseconds. Is used when datarate is not given by PHY. +#define WS_TXRX_SLOT_LEN_MS 100 // Default minimum broadcast synchronization interval in seconds #define DEFAULT_MIN_SYNCH_INTERVAL 60 // Drift compensation allowed if at least SYNCH_COMPENSATION_MIN_INTERVAL (seconds) since last synchronization @@ -55,5 +57,6 @@ int fhss_ws_set_parent(fhss_structure_t *fhss_structure, const uint8_t eui64[8], int fhss_ws_remove_parent(fhss_structure_t *fhss_structure, const uint8_t eui64[8]); int fhss_ws_configuration_set(fhss_structure_t *fhss_structure, const fhss_ws_configuration_t *fhss_configuration); int fhss_ws_set_hop_count(fhss_structure_t *fhss_structure, const uint8_t hop_count); +void fhss_set_txrx_slot_length(fhss_structure_t *fhss_structure); #endif /*FHSS_WS_H_*/ diff --git a/source/Service_Libs/utils/ns_crc.h b/source/Service_Libs/utils/ns_crc.h index f229b97e67..92fad32272 100644 --- a/source/Service_Libs/utils/ns_crc.h +++ b/source/Service_Libs/utils/ns_crc.h @@ -31,7 +31,7 @@ uint16_t crc16_ccitt(uint8_t *message, int nBytes); /** * @param data data which crc will be calculate - * @param data_length Lenght of data pointer + * @param data_length Length of data pointer * @param polynomial Polynomial which will be used to calculate CRC, POLYNOMIAL_CRC15_CCIT, POLYNOMIAL_CRC15_ANSI * @return Calculated 16bit CRC value */ diff --git a/source/libDHCPv6/dhcp_service_api.c b/source/libDHCPv6/dhcp_service_api.c index 8e321a9468..47c09ec5e2 100644 --- a/source/libDHCPv6/dhcp_service_api.c +++ b/source/libDHCPv6/dhcp_service_api.c @@ -842,7 +842,7 @@ void dhcp_service_send_message(msg_tr_t *msg_tr_ptr) if (retval != 0) { tr_warn("dhcp service socket_sendto fails: %i", retval); } else { - tr_debug("dhcp service socket_sendto %s", trace_ipv6(msg_tr_ptr->addr.address)); + tr_info("dhcp service socket_sendto %s", trace_ipv6(msg_tr_ptr->addr.address)); } } bool dhcp_service_timer_tick(uint16_t ticks) diff --git a/source/libDHCPv6/libDHCPv6_server.c b/source/libDHCPv6/libDHCPv6_server.c index 2f19eb70a4..f3c0ccba8c 100644 --- a/source/libDHCPv6/libDHCPv6_server.c +++ b/source/libDHCPv6/libDHCPv6_server.c @@ -49,17 +49,81 @@ static dhcpv6_gua_server_entry_s *libdhcpv6_server_entry_allocate(void) } entry->serverDynamic_DUID = server_duid_ptr; entry->serverDynamic_DUID_length = 16; - entry->clientIdSequence = 0; + entry->firstFreedId = 0; + entry->firstUnusedId = DHCP_ADDRESS_ID_START; entry->enableAddressAutonous = true; - entry->clientIdDefaultSuffics = 0x0000000; - entry->maxSuppertedClients = 200; + entry->disableAddressListAllocation = false; + entry->maxSupportedClients = 200; entry->validLifetime = 7200; entry->removeCb = NULL; entry->addCb = NULL; ns_list_init(&entry->allocatedAddressList); return entry; } -static void libdhcpv6_address_generate(dhcpv6_gua_server_entry_s *serverInfo, dhcpv6_alloacted_address_entry_t *entry) + +static uint16_t libdhcpv6_get_next_freed_id(dhcpv6_gua_server_entry_s *serverInfo) +{ + uint16_t last_allocated_id = DHCP_ADDRESS_ID_START - 1; + ns_list_foreach(dhcpv6_allocated_address_entry_t, cur, &serverInfo->allocatedAddressList) { + + if (last_allocated_id + 1 == cur->allocatedID) { + //Last and current plus 1 so normal order + last_allocated_id = cur->allocatedID; + continue; + } + + if ((cur->allocatedID - last_allocated_id) == 2) { + //one missing sequence between last and current + if (last_allocated_id + 1 == serverInfo->firstFreedId) { + //Skip Current freedID this will update after this call to new one + last_allocated_id = cur->allocatedID; + continue; + } + } else if (last_allocated_id + 1 == serverInfo->firstFreedId) { + //Skip first if it is last freedId + return last_allocated_id + 2; + } + + return last_allocated_id + 1; + } + //No more freed ID so return 0 + return 0; +} + +static uint16_t libdhcpv6_address_id_allocate(dhcpv6_gua_server_entry_s *serverInfo) +{ + uint16_t address_id; + if (serverInfo->firstFreedId) { + address_id = serverInfo->firstFreedId; + //Discover next free freed possible value + serverInfo->firstFreedId = libdhcpv6_get_next_freed_id(serverInfo); + } else { + //Allocated new ID + address_id = serverInfo->firstUnusedId++; + } + return address_id; +} + +static void libdhcpv6_gen_suffics_from_eui48(uint8_t *ptr, uint8_t *eui48) +{ + *ptr++ = *eui48++ ^ 2; + *ptr++ = *eui48++; + *ptr++ = *eui48++; + *ptr++ = 0xff; + *ptr++ = 0xfe; + *ptr++ = *eui48++; + *ptr++ = *eui48++; + *ptr = *eui48++; +} + +static void libdhcpv6_gen_suffics_from_allocated_id(uint8_t *ptr, uint8_t *server_unique_48_bit_id, uint16_t allocated_id) +{ + memcpy(ptr, server_unique_48_bit_id, 6); + common_write_16_bit(allocated_id, ptr + 6); +} + + +static uint16_t libdhcpv6_address_generate(dhcpv6_gua_server_entry_s *serverInfo, dhcpv6_allocated_address_t *entry) { //GENERATE ADDRESS uint8_t *ptr = entry->nonTemporalAddress; @@ -70,25 +134,78 @@ static void libdhcpv6_address_generate(dhcpv6_gua_server_entry_s *serverInfo, dh entry->linkType == DHCPV6_DUID_HARDWARE_IEEE_802_NETWORKS_TYPE) { memcpy(ptr, entry->linkId, 8); *ptr ^= 2; - } else if (entry->linkType == DHCPV6_DUID_HARDWARE_EUI48_TYPE) { - *ptr++ = entry->linkId[0] ^ 2; - *ptr++ = entry->linkId[1]; - *ptr++ = entry->linkId[2]; - *ptr++ = 0xff; - *ptr++ = 0xfe; - *ptr++ = entry->linkId[3]; - *ptr++ = entry->linkId[4]; - *ptr = entry->linkId[5]; - } else { - ptr = common_write_32_bit((serverInfo->clientIdDefaultSuffics | 02000000), ptr); - ptr = common_write_32_bit((serverInfo->clientIdSequence + 2), ptr); + return 0; } - } else { - ptr = common_write_32_bit((serverInfo->clientIdDefaultSuffics | 02000000), ptr); - ptr = common_write_32_bit((serverInfo->clientIdSequence + 2), ptr); + if (entry->linkType == DHCPV6_DUID_HARDWARE_EUI48_TYPE) { + libdhcpv6_gen_suffics_from_eui48(ptr, entry->linkId); + return 0; + } } - serverInfo->clientIdSequence++; + + uint16_t allocated_id = libdhcpv6_address_id_allocate(serverInfo); + libdhcpv6_gen_suffics_from_allocated_id(ptr, serverInfo->clientIdDefaultSuffics, allocated_id); + return allocated_id; +} + +static void libdhcpv6_address_free(dhcpv6_gua_server_entry_s *server_info, dhcpv6_allocated_address_entry_t *entry) +{ + ns_list_remove(&server_info->allocatedAddressList, entry); + if (!server_info->enableAddressAutonous) { + if (entry->allocatedID + 1 == server_info->firstUnusedId) { + server_info->firstUnusedId--; + } else if (server_info->firstFreedId == 0 || server_info->firstFreedId > entry->allocatedID) { + server_info->firstFreedId = entry->allocatedID; + } + } + ns_dyn_mem_free(entry); +} + +void libdhcpv6_allocated_address_write(uint8_t *ptr, dhcpv6_allocated_address_entry_t *address, dhcpv6_gua_server_entry_s *serverInfo) +{ + memcpy(ptr, serverInfo->guaPrefix, 8); + ptr += 8; + if (serverInfo->enableAddressAutonous) { + //Generate address from link layer address + if (address->linkType == DHCPV6_DUID_HARDWARE_EUI64_TYPE || + address->linkType == DHCPV6_DUID_HARDWARE_IEEE_802_NETWORKS_TYPE) { + memcpy(ptr, address->linkId, 8); + *ptr ^= 2; + return; + } else if (address->linkType == DHCPV6_DUID_HARDWARE_EUI48_TYPE) { + libdhcpv6_gen_suffics_from_eui48(ptr, address->linkId); + return; + } + } + //Generate from 16-bit allocate and default suffic's + libdhcpv6_gen_suffics_from_allocated_id(ptr, serverInfo->clientIdDefaultSuffics, address->allocatedID); +} + +static bool libdhcpv6_address_suffics_compare(const uint8_t *suffics, dhcpv6_allocated_address_entry_t *address, dhcpv6_gua_server_entry_s *serverInfo) +{ + uint8_t allocated_suffics[8]; + if (serverInfo->enableAddressAutonous) { + //Generate address from link layer address + if (address->linkType == DHCPV6_DUID_HARDWARE_EUI64_TYPE || + address->linkType == DHCPV6_DUID_HARDWARE_IEEE_802_NETWORKS_TYPE) { + memcpy(allocated_suffics, address->linkId, 8); + allocated_suffics[0] ^= 2; + goto compare_suffics; + } else if (address->linkType == DHCPV6_DUID_HARDWARE_EUI48_TYPE) { + libdhcpv6_gen_suffics_from_eui48(allocated_suffics, address->linkId); + goto compare_suffics; + } + } + //Generate from 16-bit allocate and default suffic's + libdhcpv6_gen_suffics_from_allocated_id(allocated_suffics, serverInfo->clientIdDefaultSuffics, address->allocatedID); + +compare_suffics: + if (memcmp(allocated_suffics, suffics, 8)) { + return false; + } + + return true; + } @@ -97,15 +214,16 @@ void libdhcpv6_gua_servers_time_update(uint32_t timeUpdateInSeconds) //Check All allocated server inside this loop ns_list_foreach(dhcpv6_gua_server_entry_s, cur, &dhcpv6_gua_server_list) { //Check All allocated address in this module - ns_list_foreach_safe(dhcpv6_alloacted_address_entry_t, address, &cur->allocatedAddressList) { + ns_list_foreach_safe(dhcpv6_allocated_address_entry_t, address, &cur->allocatedAddressList) { //Update if (address->preferredLifetime) { if (address->preferredLifetime <= timeUpdateInSeconds) { //Stop use this address for leasequery and delete Route or address map - address->preferredLifetime = 0; if (cur->removeCb) { - cur->removeCb(cur->interfaceId, address->nonTemporalAddress, cur->guaPrefix); + uint8_t allocated_address[16]; + libdhcpv6_allocated_address_write(allocated_address, address, cur); + cur->removeCb(cur->interfaceId, allocated_address, cur->guaPrefix); } } else { address->preferredLifetime -= timeUpdateInSeconds; @@ -113,8 +231,7 @@ void libdhcpv6_gua_servers_time_update(uint32_t timeUpdateInSeconds) } if (address->lifetime <= timeUpdateInSeconds) { - ns_list_remove(&cur->allocatedAddressList, address); - ns_dyn_mem_free(address); + libdhcpv6_address_free(cur, address); } else { address->lifetime -= timeUpdateInSeconds; } @@ -187,6 +304,15 @@ dhcpv6_gua_server_entry_s *libdhcpv6_gua_server_allocate(uint8_t *prefix, int8_t duid_length = libdhcpv6_duid_linktype_size(serverDUIDType) + 2; ptr = common_write_16_bit(serverDUIDType, ptr); memcpy(ptr, serverDUID, libdhcpv6_duid_linktype_size(serverDUIDType)); + //SET Defaultsuffics + if (libdhcpv6_duid_linktype_size(serverDUIDType) == 8) { + memcpy(entry->clientIdDefaultSuffics, serverDUID, 3); + memcpy(entry->clientIdDefaultSuffics + 3, serverDUID + 5, 3); + } else { + memcpy(entry->clientIdDefaultSuffics, serverDUID, 6); + } + + entry->clientIdDefaultSuffics[0] ^= 0x02; //SET DUID if (libdhcpv6_server_duid_set(entry, duid_ll, DHCPV6_DUID_LINK_LAYER_TYPE, duid_length) != 0) { @@ -208,7 +334,7 @@ void libdhcpv6_gua_server_free_by_prefix_and_interfaceid(uint8_t *prefix, int8_t dhcpv6_gua_server_entry_s *serverInfo = libdhcpv6_server_data_get_by_prefix_and_interfaceid(interfaceId, prefix); if (serverInfo) { if ((serverInfo->interfaceId == interfaceId) && (memcmp(serverInfo->guaPrefix, prefix, 8) == 0)) { - ns_list_foreach_safe(dhcpv6_alloacted_address_entry_t, cur, &serverInfo->allocatedAddressList) { + ns_list_foreach_safe(dhcpv6_allocated_address_entry_t, cur, &serverInfo->allocatedAddressList) { ns_list_remove(&serverInfo->allocatedAddressList, cur); ns_dyn_mem_free(cur); } @@ -219,26 +345,52 @@ void libdhcpv6_gua_server_free_by_prefix_and_interfaceid(uint8_t *prefix, int8_t } } -static dhcpv6_alloacted_address_entry_t *libdhcpv6_address_entry_allocate(uint32_t validLifetime) +static void libdhcpv6_address_entry_lifetime_set(dhcpv6_allocated_address_entry_t *entry, uint32_t validLifetime) { - dhcpv6_alloacted_address_entry_t *entry = ns_dyn_mem_alloc(sizeof(dhcpv6_alloacted_address_entry_t)); - if (entry) { - if (validLifetime != 0xffffffff) { - entry->lifetime = validLifetime; - entry->preferredLifetime = (validLifetime >> 1); - } else { - entry->lifetime = 0xffffffff; - entry->preferredLifetime = 0xffffffff; - } + if (validLifetime != 0xffffffff) { + entry->lifetime = validLifetime; + entry->preferredLifetime = (validLifetime >> 1); + } else { + entry->lifetime = 0xffffffff; + entry->preferredLifetime = 0xffffffff; } - return entry; } -dhcpv6_alloacted_address_entry_t *libdhcpv6_address_get_from_allocated_list(dhcpv6_gua_server_entry_s *serverInfo, const uint8_t *address) +static void libdhcpv6_copy_allocated_entry_to_temp(dhcpv6_allocated_address_entry_t *cur, dhcpv6_allocated_address_t *address, dhcpv6_gua_server_entry_s *serverInfo) { - ns_list_foreach(dhcpv6_alloacted_address_entry_t, cur, &serverInfo->allocatedAddressList) { - if (memcmp(cur->nonTemporalAddress, address, 16) == 0) { - return cur; + libdhcpv6_allocated_address_write(address->nonTemporalAddress, cur, serverInfo); + memcpy(address->linkId, cur->linkId, 8); + address->T0 = cur->T0; + address->T1 = cur->T1; + address->iaID = cur->iaID; + address->lifetime = cur->lifetime; + address->preferredLifetime = cur->preferredLifetime; + address->linkType = cur->linkType; +} + + +static void libdhcpv6_copy_temp_to_allocated_entry(dhcpv6_allocated_address_entry_t *cur, dhcpv6_allocated_address_t *address, uint16_t allocated_id) +{ + memcpy(cur->linkId, address->linkId, 8); + cur->allocatedID = allocated_id; + cur->T0 = address->T0; + cur->T1 = address->T1; + cur->iaID = address->iaID; + cur->lifetime = address->lifetime; + cur->preferredLifetime = address->preferredLifetime; + cur->linkType = address->linkType; +} + +dhcpv6_allocated_address_t *libdhcpv6_address_get_from_allocated_list(dhcpv6_gua_server_entry_s *serverInfo, const uint8_t *address) +{ + if (memcmp(serverInfo->guaPrefix, address, 8)) { + return NULL; + } + + ns_list_foreach(dhcpv6_allocated_address_entry_t, cur, &serverInfo->allocatedAddressList) { + if (libdhcpv6_address_suffics_compare(address + 8, cur, serverInfo) == 0) { + libdhcpv6_copy_allocated_entry_to_temp(cur, &serverInfo->tempAddressEntry, serverInfo); + return &serverInfo->tempAddressEntry; } } return NULL; @@ -246,49 +398,95 @@ dhcpv6_alloacted_address_entry_t *libdhcpv6_address_get_from_allocated_list(dhcp void libdhcpv6_address_rm_from_allocated_list(dhcpv6_gua_server_entry_s *serverInfo, const uint8_t *address) { - ns_list_foreach_safe(dhcpv6_alloacted_address_entry_t, cur, &serverInfo->allocatedAddressList) { - if (memcmp(cur->nonTemporalAddress, address, 16) == 0) { - ns_list_remove(&serverInfo->allocatedAddressList, cur); - ns_dyn_mem_free(cur); + if (memcmp(serverInfo->guaPrefix, address, 8)) { + return; + } + + ns_list_foreach_safe(dhcpv6_allocated_address_entry_t, cur, &serverInfo->allocatedAddressList) { + if (libdhcpv6_address_suffics_compare(address + 8, cur, serverInfo) == 0) { + libdhcpv6_address_free(serverInfo, cur); return; } } } -dhcpv6_alloacted_address_entry_t *libdhcpv6_address_allocated_list_scan(dhcpv6_gua_server_entry_s *serverInfo, uint8_t *linkId, uint16_t linkType, uint32_t iaID, uint32_t T0, uint32_t T1, bool allocateNew) + +static void libdhcpv6_address_id_add_to_list(dhcpv6_gua_server_entry_s *serverInfo, dhcpv6_allocated_address_entry_t *allocated) { - dhcpv6_alloacted_address_entry_t *newEntry = NULL; + if (serverInfo->firstUnusedId != allocated->allocatedID + 1) { + ns_list_foreach_safe(dhcpv6_allocated_address_entry_t, cur, &serverInfo->allocatedAddressList) { + if (cur->allocatedID > allocated->allocatedID) { + //Add before new allocated + if (cur->link.prev) { + ns_list_add_before(&serverInfo->allocatedAddressList, cur, allocated); + } else { + //New first + ns_list_add_to_start(&serverInfo->allocatedAddressList, allocated); + } + return; + } + } + } + ns_list_add_to_end(&serverInfo->allocatedAddressList, allocated); +} + + +dhcpv6_allocated_address_t *libdhcpv6_address_allocated_list_scan(dhcpv6_gua_server_entry_s *serverInfo, uint8_t *linkId, uint16_t linkType, uint32_t iaID, uint32_t T0, uint32_t T1, bool allocateNew) +{ + dhcpv6_allocated_address_t *newEntry = NULL; + dhcpv6_allocated_address_entry_t *allocatedEntry = NULL; uint16_t duiLength = 6; if (linkType == DHCPV6_DUID_HARDWARE_EUI64_TYPE || linkType == DHCPV6_DUID_HARDWARE_IEEE_802_NETWORKS_TYPE) { duiLength = 8; } - ns_list_foreach(dhcpv6_alloacted_address_entry_t, cur, &serverInfo->allocatedAddressList) { + + if (serverInfo->enableAddressAutonous && serverInfo->disableAddressListAllocation) { + //Accept allways when autonous + newEntry = &serverInfo->tempAddressEntry; + allocateNew = false; + } + + ns_list_foreach(dhcpv6_allocated_address_entry_t, cur, &serverInfo->allocatedAddressList) { if (cur->linkType == linkType) { if (memcmp(cur->linkId, linkId, duiLength) == 0) { cur->iaID = iaID; - if (serverInfo->validLifetime != 0xffffffff) { - cur->lifetime = serverInfo->validLifetime ; - cur->preferredLifetime = (serverInfo->validLifetime >> 1); - } else { - cur->lifetime = 0xffffffff; - cur->preferredLifetime = 0xffffffff; - } - return cur; + libdhcpv6_address_entry_lifetime_set(cur, serverInfo->validLifetime); + libdhcpv6_copy_allocated_entry_to_temp(cur, &serverInfo->tempAddressEntry, serverInfo); + return &serverInfo->tempAddressEntry; } } } if (allocateNew) { - if (ns_list_count(&serverInfo->allocatedAddressList) < serverInfo->maxSuppertedClients) { - newEntry = libdhcpv6_address_entry_allocate(serverInfo->validLifetime); - if (newEntry) { - memcpy(newEntry->linkId, linkId, duiLength); - newEntry->linkType = linkType; - newEntry->iaID = iaID; - newEntry->T0 = T0; - newEntry->T1 = T1; - libdhcpv6_address_generate(serverInfo, newEntry); - ns_list_add_to_end(&serverInfo->allocatedAddressList, newEntry); + if (ns_list_count(&serverInfo->allocatedAddressList) < serverInfo->maxSupportedClients) { + allocatedEntry = ns_dyn_mem_alloc(sizeof(dhcpv6_allocated_address_entry_t)); + if (allocatedEntry) { + newEntry = &serverInfo->tempAddressEntry; + } + } + } + if (newEntry) { + + if (serverInfo->validLifetime != 0xffffffff) { + newEntry->lifetime = serverInfo->validLifetime; + newEntry->preferredLifetime = (serverInfo->validLifetime >> 1); + } else { + newEntry->lifetime = 0xffffffff; + newEntry->preferredLifetime = 0xffffffff; + } + memcpy(newEntry->linkId, linkId, duiLength); + newEntry->linkType = linkType; + newEntry->iaID = iaID; + newEntry->T0 = T0; + newEntry->T1 = T1; + uint16_t allocated_id = libdhcpv6_address_generate(serverInfo, newEntry); + if (!serverInfo->disableAddressListAllocation) { + libdhcpv6_copy_temp_to_allocated_entry(allocatedEntry, newEntry, allocated_id); + if (serverInfo->enableAddressAutonous) { + ns_list_add_to_end(&serverInfo->allocatedAddressList, allocatedEntry); + } else { + //Add to list to proper order + libdhcpv6_address_id_add_to_list(serverInfo, allocatedEntry); } } } diff --git a/source/libDHCPv6/libDHCPv6_server.h b/source/libDHCPv6/libDHCPv6_server.h index ba17b340f5..3b4c0643e2 100644 --- a/source/libDHCPv6/libDHCPv6_server.h +++ b/source/libDHCPv6/libDHCPv6_server.h @@ -28,9 +28,25 @@ #include "libDHCPv6/libDHCPv6.h" +#define MAX_SUPPORTED_ADDRESS_LIST_SIZE 0x0000fffd +#define DHCP_ADDRESS_ID_START 2 + typedef void (dhcp_address_prefer_remove_cb)(int8_t interfaceId, uint8_t *targetAddress, void *prefix_info); -typedef struct dhcpv6_alloacted_address_entry_s { +typedef struct dhcpv6_allocated_address_entry_s { + uint8_t linkId[8]; /*!< Services UL64 */ + uint32_t iaID; + uint32_t T0; + uint32_t T1; + uint32_t preferredLifetime; + uint32_t lifetime; + uint16_t linkType; + uint16_t allocatedID; + ns_list_link_t link; /*!< List link entry */ +} dhcpv6_allocated_address_entry_t; + + +typedef struct dhcpv6_allocated_address_s { uint8_t nonTemporalAddress[16]; uint8_t linkId[8]; /*!< Services UL64 */ uint16_t linkType; @@ -39,18 +55,9 @@ typedef struct dhcpv6_alloacted_address_entry_s { uint32_t T1; uint32_t preferredLifetime; uint32_t lifetime; - ns_list_link_t link; /*!< List link entry */ -} dhcpv6_alloacted_address_entry_t; +} dhcpv6_allocated_address_t; -typedef NS_LIST_HEAD(dhcpv6_alloacted_address_entry_t, link) dhcpv6_alloacted_address_list_t; - -typedef struct thread_dhcpv6_server_data_s { - uint8_t prefix[8]; /*!< Services Prefix */ - uint16_t maxSuppertedClients; - uint32_t clientIdSequence; /*!< Define */ - dhcpv6_alloacted_address_list_t allocatedAddressList; - ns_list_link_t link; /*!< List link entry */ -} dhcpv6_server_data_entry_t; +typedef NS_LIST_HEAD(dhcpv6_allocated_address_entry_t, link) dhcpv6_allocated_address_list_t; typedef struct dhcp_address_cache_update { uint8_t *allocatedAddress; @@ -62,19 +69,22 @@ typedef bool (dhcp_address_add_notify_cb)(int8_t interfaceId, dhcp_address_cache typedef struct dhcpv6_gua_server_entry_s { int8_t interfaceId; - bool enableAddressAutonous; + bool enableAddressAutonous: 1; + bool disableAddressListAllocation: 1; uint16_t socketInstance_id; uint8_t guaPrefix[8]; uint8_t serverDynamic_DUID_length; - uint32_t maxSuppertedClients; - uint32_t clientIdDefaultSuffics; - uint32_t clientIdSequence; /*!< Define */ + uint32_t maxSupportedClients; + uint8_t clientIdDefaultSuffics[6]; + uint16_t firstFreedId; + uint16_t firstUnusedId; /*!< This is first unused Id */ uint32_t validLifetime; dhcp_duid_options_params_t serverDUID; uint8_t *serverDynamic_DUID; dhcp_address_prefer_remove_cb *removeCb; dhcp_address_add_notify_cb *addCb; - dhcpv6_alloacted_address_list_t allocatedAddressList; + dhcpv6_allocated_address_list_t allocatedAddressList; + dhcpv6_allocated_address_t tempAddressEntry; ns_list_link_t link; /*!< List link entry */ } dhcpv6_gua_server_entry_s; @@ -84,10 +94,11 @@ int libdhcpv6_server_duid_set(dhcpv6_gua_server_entry_s *server_info, uint8_t *d void libdhcpv6_gua_server_free_by_prefix_and_interfaceid(uint8_t *prefix, int8_t interfaceId); void libdhcpv6_gua_servers_time_update(uint32_t timeUpdateInSeconds); void libdhcpv6_address_rm_from_allocated_list(dhcpv6_gua_server_entry_s *serverInfo, const uint8_t *address); -dhcpv6_alloacted_address_entry_t *libdhcpv6_address_get_from_allocated_list(dhcpv6_gua_server_entry_s *serverInfo, const uint8_t *address); +dhcpv6_allocated_address_t *libdhcpv6_address_get_from_allocated_list(dhcpv6_gua_server_entry_s *serverInfo, const uint8_t *address); dhcpv6_gua_server_entry_s *libdhcpv6_server_data_get_by_prefix_and_interfaceid(int8_t interfaceId, const uint8_t *prefixPtr); dhcpv6_gua_server_entry_s *libdhcpv6_server_data_get_by_prefix_and_socketinstance(uint16_t socketInstance, uint8_t *prefixPtr); -dhcpv6_alloacted_address_entry_t *libdhcpv6_address_allocated_list_scan(dhcpv6_gua_server_entry_s *serverInfo, uint8_t *euid64, uint16_t linkType, uint32_t iaID, uint32_t T0, uint32_t T1, bool allocateNew); +dhcpv6_allocated_address_t *libdhcpv6_address_allocated_list_scan(dhcpv6_gua_server_entry_s *serverInfo, uint8_t *euid64, uint16_t linkType, uint32_t iaID, uint32_t T0, uint32_t T1, bool allocateNew); +void libdhcpv6_allocated_address_write(uint8_t *ptr, dhcpv6_allocated_address_entry_t *address, dhcpv6_gua_server_entry_s *serverInfo); #else #define libdhcpv6_gua_server_list_empty() true #define libdhcpv6_server_data_get_by_prefix_and_interfaceid(interfaceId, prefixPtr) NULL diff --git a/source/libNET/src/net_6lowpan_parameter_api.c b/source/libNET/src/net_6lowpan_parameter_api.c index 59bea2198a..cd1649df3c 100644 --- a/source/libNET/src/net_6lowpan_parameter_api.c +++ b/source/libNET/src/net_6lowpan_parameter_api.c @@ -65,6 +65,7 @@ int8_t net_6lowpan_nd_parameter_set(const nd_parameters_s *p) return 0; #else + (void) p; return -2; #endif } @@ -89,6 +90,8 @@ int8_t net_6lowpan_nd_timer_base_tick_set(uint8_t base_tick_x_100ms) } nd_base_tick = base_tick_x_100ms; +#else + (void) base_tick_x_100ms; #endif return 0; } @@ -103,5 +106,7 @@ void net_6lowpan_nd_parameter_read(nd_parameters_s *p) { #ifdef HAVE_6LOWPAN_ND *p = nd_params; +#else + (void) p; #endif } diff --git a/source/libNET/src/net_load_balance.c b/source/libNET/src/net_load_balance.c index 90f4960dff..a643d90fde 100644 --- a/source/libNET/src/net_load_balance.c +++ b/source/libNET/src/net_load_balance.c @@ -146,12 +146,14 @@ int8_t net_load_balance_network_switch_cb_set(int8_t interface_id, net_load_bala return load_balance_network_switch_cb_set(interface_ptr->lb_api, network_switch_notify); #else + (void) interface_id; + (void) network_switch_notify; return -1; #endif } -int8_t net_load_balance_create(int8_t interface_id, bool enable_periodic_beacon_interval) +int8_t net_load_balance_create(int8_t interface_id, bool enable_periodic_beacon_interval) { #ifdef HAVE_6LOWPAN_ND protocol_interface_info_entry_t *interface_ptr = protocol_stack_interface_info_get_by_id(interface_id); @@ -188,6 +190,8 @@ int8_t net_load_balance_create(int8_t interface_id, bool enable_periodic_beacon return 0; #else + (void) interface_id; + (void) enable_periodic_beacon_interval; return -1; #endif } @@ -205,6 +209,7 @@ int8_t net_load_balance_delete(int8_t interface_id) return load_balance_delete(lb_api); #else + (void) interface_id; return -1; #endif } @@ -223,6 +228,9 @@ int8_t net_load_balance_threshold_set(int8_t interface_id, uint8_t threshold_min return load_balance_network_threshold_set(interface_ptr->lb_api, threshold_min, threshold_max); #else + (void) interface_id; + (void) threshold_min; + (void) threshold_max; return -1; #endif } @@ -259,8 +267,10 @@ void net_load_balance_internal_state_activate(protocol_interface_info_entry_t *i set_req.value_pointer = &state; set_req.value_size = sizeof(bool); interface_ptr->mac_api->mlme_req(interface_ptr->mac_api, MLME_SET, &set_req); +#else + (void) interface_ptr; + (void) state; #endif - } #ifdef HAVE_RPL @@ -361,6 +371,8 @@ int8_t net_load_balance_set_max_probability(int8_t interface_id, uint8_t max_p) return load_balance_set_max_probability(interface_ptr->lb_api, max_p); #else + (void) interface_id; + (void) max_p; return -1; #endif } diff --git a/source/libNET/src/ns_net.c b/source/libNET/src/ns_net.c index 5ee8a60dc6..e369f6c375 100644 --- a/source/libNET/src/ns_net.c +++ b/source/libNET/src/ns_net.c @@ -400,6 +400,10 @@ int8_t arm_nwk_6lowpan_gp_address_mode(int8_t interface_id, net_6lowpan_gp_addre return 0; #else + (void) interface_id; + (void) mode; + (void) short_address_base; + (void) define_new_short_address_at_DAD; return -2; #endif } @@ -895,7 +899,7 @@ int8_t arm_pana_client_key_pull(int8_t interface_id) return pana_client_key_pull(interface_id); } -int8_t arm_nwk_link_layer_security_mode(int8_t interface_id, net_6lowpan_link_layer_sec_mode_e mode, uint8_t sec_level, const net_link_layer_psk_security_info_s *psk_key_info) +int8_t arm_nwk_link_layer_security_mode(int8_t interface_id, net_6lowpan_link_layer_sec_mode_e mode, uint8_t sec_level, const net_link_layer_psk_security_info_s *psk_key_info) { protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); if (!cur || thread_info(cur) || !cur->mac_parameters || (cur->configure_flags & INTERFACE_BOOTSTRAP_DEFINED) == 0) { @@ -903,6 +907,9 @@ int8_t arm_nwk_link_layer_security_mode(int8_t interface_id, net_6lowpan_link_la } #ifndef HAVE_6LOWPAN_ND + (void) mode; + (void) sec_level; + (void) psk_key_info; return -1; #else if (cur->lowpan_info & INTERFACE_NWK_ACTIVE) { diff --git a/source/libNET/src/socket_api.c b/source/libNET/src/socket_api.c index 65b192145d..2cf27829c5 100644 --- a/source/libNET/src/socket_api.c +++ b/source/libNET/src/socket_api.c @@ -108,6 +108,8 @@ int8_t socket_close(int8_t sid) int8_t socket_listen(int8_t socket, uint8_t backlog) { #ifdef NO_TCP + (void) socket; + (void) backlog; return -1; #else socket_t *socket_ptr = socket_pointer_get(socket); @@ -141,6 +143,9 @@ int8_t socket_listen(int8_t socket, uint8_t backlog) int8_t socket_accept(int8_t listen_socket_id, ns_address_t *addr, void (*passed_fptr)(void *)) { #ifdef NO_TCP + (void) listen_socket_id; + (void) addr; + (void) passed_fptr; return -1; #else socket_t *socket_ptr = socket_pointer_get(listen_socket_id); @@ -189,6 +194,8 @@ int8_t socket_accept(int8_t listen_socket_id, ns_address_t *addr, void (*passed_ int8_t socket_shutdown(int8_t socket, uint8_t how) { #ifdef NO_TCP + (void) socket; + (void) how; return -1; #else socket_t *socket_ptr = socket_pointer_get(socket); @@ -608,8 +615,8 @@ int8_t socket_connect(int8_t socket, ns_address_t *address, uint8_t randomly_tak socket_ptr->flags |= SOCKET_FLAG_CONNECTING; } -#endif exit: +#endif if (status != 0) { memcpy(inet_pcb->remote_address, ns_in6addr_any, 16); inet_pcb->remote_port = 0; diff --git a/sources.mk b/sources.mk index 1cc99981bd..840c51105d 100644 --- a/sources.mk +++ b/sources.mk @@ -136,6 +136,7 @@ SRCS += \ source/Service_Libs/fhss/fhss_common.c \ source/Service_Libs/fhss/channel_functions.c \ source/Service_Libs/fhss/channel_list.c \ + source/Service_Libs/fhss/fhss_test_api.c \ source/Service_Libs/fnv_hash/fnv_hash.c \ source/Service_Libs/hmac/hmac_sha1.c \ source/Service_Libs/ieee_802_11/ieee_802_11.c \ From 3fd01edf596b878c64a0f13d7f749cacfe981de5 Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Thu, 20 Feb 2020 17:03:06 +0200 Subject: [PATCH 04/49] RF802.11.4 S2LP driver sync with dev repository Sync with version v1.0.1 in development repository. --- .../source/NanostackRfPhys2lp.cpp | 34 ++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/components/802.15.4_RF/stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp b/components/802.15.4_RF/stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp index 58932e45a7..b65e1ebdd4 100644 --- a/components/802.15.4_RF/stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp +++ b/components/802.15.4_RF/stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp @@ -209,8 +209,8 @@ static rf_mode_e rf_mode = RF_MODE_NORMAL; static bool rf_update_config = false; static uint16_t cur_packet_len = 0xffff; static uint32_t receiver_ready_timestamp; - static int16_t rssi_threshold = RSSI_THRESHOLD; +static uint32_t tx_start_time = 0; /* Channel configurations for sub-GHz */ static phy_rf_channel_configuration_s phy_subghz = { @@ -276,6 +276,20 @@ static uint32_t rf_get_timestamp(void) return (uint32_t)rf->tx_timer.read_us(); } +static void rf_update_tx_active_time(void) +{ + if (device_driver.phy_rf_statistics) { + device_driver.phy_rf_statistics->tx_active_time += rf_get_timestamp() - tx_start_time; + } +} + +static void rf_update_rx_active_time(void) +{ + if (device_driver.phy_rf_statistics) { + device_driver.phy_rf_statistics->rx_active_time += rf_get_timestamp() - rx_time; + } +} + static void rf_lock(void) { platform_enter_critical(); @@ -739,6 +753,7 @@ static void rf_tx_sent_handler(void) rf_disable_interrupt(TX_DATA_SENT); if (rf_state != RF_TX_ACK) { tx_finnish_time = rf_get_timestamp(); + rf_update_tx_active_time(); TEST_TX_DONE rf_state = RF_IDLE; rf_receive(rf_rx_channel); @@ -771,6 +786,7 @@ static void rf_start_tx(void) rf_disable_all_interrupts(); rf_poll_state_change(S2LP_STATE_READY); rf_state_change(S2LP_STATE_TX, false); + tx_start_time = rf_get_timestamp(); // More TX data to be written in FIFO when TX threshold interrupt occurs if (tx_data_ptr) { rf_enable_interrupt(TX_FIFO_ALMOST_EMPTY); @@ -805,6 +821,7 @@ static void rf_cca_timer_interrupt(void) } rf_flush_tx_fifo(); tx_finnish_time = rf_get_timestamp(); + rf_update_tx_active_time(); if (device_driver.phy_tx_done_cb) { device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 0, 0); } @@ -825,6 +842,9 @@ static void rf_cca_timer_interrupt(void) rf_start_tx(); rf_state = RF_TX_STARTED; TEST_TX_STARTED + if (device_driver.phy_rf_statistics) { + device_driver.phy_rf_statistics->tx_bytes += tx_data_length; + } } } } @@ -843,10 +863,12 @@ static void rf_backup_timer_interrupt(void) { tx_finnish_time = rf_get_timestamp(); if (rf_state == RF_RX_STARTED) { + rf_update_rx_active_time(); if (device_driver.phy_rf_statistics) { device_driver.phy_rf_statistics->rx_timeouts++; } } else { + rf_update_tx_active_time(); if (device_driver.phy_rf_statistics) { device_driver.phy_rf_statistics->tx_timeouts++; } @@ -921,6 +943,9 @@ static void rf_send_ack(uint8_t seq) rf_start_tx(); TEST_ACK_TX_STARTED rf_backup_timer_start(ACK_SENDING_TIME); + if (device_driver.phy_rf_statistics) { + device_driver.phy_rf_statistics->tx_bytes += sizeof(ack_frame); + } } static void rf_handle_ack(uint8_t seq_number, uint8_t pending) @@ -928,6 +953,7 @@ static void rf_handle_ack(uint8_t seq_number, uint8_t pending) phy_link_tx_status_e phy_status; if (tx_sequence == (uint16_t)seq_number) { tx_finnish_time = rf_get_timestamp(); + rf_update_tx_active_time(); if (pending) { phy_status = PHY_LINK_TX_DONE_PENDING; } else { @@ -966,6 +992,9 @@ static void rf_rx_ready_handler(void) rf_send_ack(rx_buffer[2]); } } + if (device_driver.phy_rf_statistics) { + device_driver.phy_rf_statistics->rx_bytes += rx_data_length; + } } else { rf_state = RF_IDLE; int8_t rssi = (rf_read_register(RSSI_LEVEL) - RSSI_OFFSET); @@ -1072,6 +1101,7 @@ static void rf_irq_task_process_irq(void) if ((irq_status & (1 << TX_FIFO_UNF_OVF)) && (enabled_interrupts & (1 << TX_FIFO_UNF_OVF))) { rf_backup_timer_stop(); tx_finnish_time = rf_get_timestamp(); + rf_update_tx_active_time(); TEST_TX_DONE device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 1, 0); rf_send_command(S2LP_CMD_SABORT); @@ -1087,6 +1117,7 @@ static void rf_irq_task_process_irq(void) } } else if (rf_state == RF_RX_STARTED) { if ((irq_status & (1 << RX_DATA_READY)) && (enabled_interrupts & (1 << RX_DATA_READY))) { + rf_update_rx_active_time(); if (!(irq_status & (1 << CRC_ERROR))) { rf_rx_ready_handler(); } else { @@ -1112,6 +1143,7 @@ static void rf_irq_task_process_irq(void) } } if ((irq_status & (1 << RX_FIFO_UNF_OVF)) && (enabled_interrupts & (1 << RX_FIFO_UNF_OVF))) { + rf_update_rx_active_time(); TEST_RX_DONE rf_backup_timer_stop(); rf_send_command(S2LP_CMD_SABORT); From 1a5cf1f9c248cb92cfd646c8a92b81315495fda0 Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Fri, 21 Feb 2020 11:12:47 +0200 Subject: [PATCH 05/49] Update 802.15.4 RF drivers Update atmel-rf-driver to version v3.0.9 Update mcr20a-rf-driver to v1.0.8 --- .../atmel-rf-driver/source/NanostackRfPhyAtmel.cpp | 2 +- .../802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c | 13 +++++++------ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp b/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp index abb2ee93e9..be59a4afcd 100644 --- a/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp +++ b/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp @@ -524,7 +524,7 @@ static void rf_if_reset_radio(void) #else rf->spi.frequency(MBED_CONF_ATMEL_RF_LOW_SPI_SPEED); #endif - rf->IRQ.rise(0); + rf->IRQ.rise(nullptr); rf->RST = 1; ThisThread::sleep_for(2); rf->RST = 0; diff --git a/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c b/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c index dc99f2d1b3..90633a0205 100644 --- a/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c +++ b/components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c @@ -45,6 +45,7 @@ #if defined(MBED_CONF_NANOSTACK_CONFIGURATION) && DEVICE_SPI && DEVICE_INTERRUPTIN && defined(MBED_CONF_RTOS_PRESENT) #include "platform/mbed_critical.h" +#include /***************************************************************************** * PRIVATE VARIABLES * @@ -165,7 +166,7 @@ void MCR20Drv_DirectAccessSPIMultiByteWrite { uint8_t txData; - if ((numOfBytes == 0) || (byteArray == 0)) { + if ((numOfBytes == 0) || (byteArray == NULL)) { return; } @@ -230,7 +231,7 @@ void MCR20Drv_PB_SPIBurstWrite { uint8_t txData; - if ((numOfBytes == 0) || (byteArray == 0)) { + if ((numOfBytes == 0) || (byteArray == NULL)) { return; } @@ -301,7 +302,7 @@ uint8_t MCR20Drv_DirectAccessSPIMultiByteRead uint8_t txData; uint8_t phyIRQSTS1; - if ((numOfBytes == 0) || (byteArray == 0)) { + if ((numOfBytes == 0) || (byteArray == NULL)) { return 0; } @@ -338,7 +339,7 @@ uint8_t MCR20Drv_PB_SPIBurstRead uint8_t txData; uint8_t phyIRQSTS1; - if ((numOfBytes == 0) || (byteArray == 0)) { + if ((numOfBytes == 0) || (byteArray == NULL)) { return 0; } @@ -406,7 +407,7 @@ void MCR20Drv_IndirectAccessSPIMultiByteWrite { uint16_t txData; - if ((numOfBytes == 0) || (byteArray == 0)) { + if ((numOfBytes == 0) || (byteArray == NULL)) { return; } @@ -473,7 +474,7 @@ void MCR20Drv_IndirectAccessSPIMultiByteRead { uint16_t txData; - if ((numOfBytes == 0) || (byteArray == 0)) { + if ((numOfBytes == 0) || (byteArray == NULL)) { return; } From 2f0907c14039715a5227488276ba4ad79efc9ffa Mon Sep 17 00:00:00 2001 From: Jarno Lamsa Date: Mon, 2 Mar 2020 10:16:43 +0200 Subject: [PATCH 06/49] Remove _variant_bd_erase_unit_size In some cases, it is possible that every erase unit in area 0 has the same size, but they are still different than in area 1. Remove the flag for varying erase sizes and instead check from flash, what is the erase size of the current unit. --- features/storage/kvstore/tdbstore/TDBStore.cpp | 16 +++++----------- features/storage/kvstore/tdbstore/TDBStore.h | 1 - 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/features/storage/kvstore/tdbstore/TDBStore.cpp b/features/storage/kvstore/tdbstore/TDBStore.cpp index 61ce279762..efeedf42c2 100644 --- a/features/storage/kvstore/tdbstore/TDBStore.cpp +++ b/features/storage/kvstore/tdbstore/TDBStore.cpp @@ -126,7 +126,7 @@ static uint32_t calc_crc(uint32_t init_crc, uint32_t data_size, const void *data TDBStore::TDBStore(BlockDevice *bd) : _ram_table(0), _max_keys(0), _num_keys(0), _bd(bd), _buff_bd(0), _free_space_offset(0), _master_record_offset(0), _master_record_size(0), _is_initialized(false), _active_area(0), _active_area_version(0), _size(0), - _area_params{}, _prog_size(0), _work_buf(0), _key_buf(0), _variant_bd_erase_unit_size(false), _inc_set_handle(0) + _area_params{}, _prog_size(0), _work_buf(0), _key_buf(0), _inc_set_handle(0) { for (int i = 0; i < _num_areas; i++) { _area_params[i] = { 0 }; @@ -186,12 +186,9 @@ void TDBStore::calc_area_params() memset(_area_params, 0, sizeof(_area_params)); size_t area_0_size = 0; - bd_size_t prev_erase_unit_size = _bd->get_erase_size(area_0_size); - _variant_bd_erase_unit_size = 0; while (area_0_size < bd_size / 2) { bd_size_t erase_unit_size = _bd->get_erase_size(area_0_size); - _variant_bd_erase_unit_size |= (erase_unit_size != prev_erase_unit_size); area_0_size += erase_unit_size; } @@ -199,6 +196,9 @@ void TDBStore::calc_area_params() _area_params[0].size = area_0_size; _area_params[1].address = area_0_size; _area_params[1].size = bd_size - area_0_size; + + // The areas must be of same size + MBED_ASSERT(_area_params[0].size == _area_params[1].size); } @@ -1487,14 +1487,8 @@ void TDBStore::offset_in_erase_unit(uint8_t area, uint32_t offset, uint32_t &offset_from_start, uint32_t &dist_to_end) { uint32_t bd_offset = _area_params[area].address + offset; - if (!_variant_bd_erase_unit_size) { - uint32_t eu_size = _buff_bd->get_erase_size(); - offset_from_start = bd_offset % eu_size; - dist_to_end = eu_size - offset_from_start; - return; - } - uint32_t agg_offset = 0; + while (bd_offset >= agg_offset + _buff_bd->get_erase_size(agg_offset)) { agg_offset += _buff_bd->get_erase_size(agg_offset); } diff --git a/features/storage/kvstore/tdbstore/TDBStore.h b/features/storage/kvstore/tdbstore/TDBStore.h index ad7d3f9779..5732946f0d 100644 --- a/features/storage/kvstore/tdbstore/TDBStore.h +++ b/features/storage/kvstore/tdbstore/TDBStore.h @@ -308,7 +308,6 @@ private: uint32_t _prog_size; uint8_t *_work_buf; char *_key_buf; - bool _variant_bd_erase_unit_size; void *_inc_set_handle; void *_iterator_table[_max_open_iterators]; From ed6869d9ecc78656942dbccb080a0fe5eed767cc Mon Sep 17 00:00:00 2001 From: d-kato Date: Tue, 14 Jan 2020 11:10:30 +0900 Subject: [PATCH 07/49] Add sector information --- targets/targets.json | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index 32617dbc4e..b954823690 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -5899,7 +5899,10 @@ "device_has_add": ["USBDEVICE", "EMAC", "FLASH", "LPTICKER"], "release_versions": ["2", "5"], "device_name": "R7S72100", - "bootloader_supported": false + "bootloader_supported": true, + "mbed_rom_start" : "0x18000000", + "mbed_rom_size" : "0x800000", + "sectors": [[402653184,4096]] }, "VK_RZ_A1H": { "inherits": ["RZ_A1XX"], @@ -5916,7 +5919,10 @@ "device_has_remove": ["ETHERNET"], "release_versions": ["2", "5"], "device_name": "R7S72103", - "bootloader_supported": false, + "bootloader_supported": true, + "mbed_rom_start" : "0x18000000", + "mbed_rom_size" : "0x800000", + "sectors": [[402653184,4096]], "overrides": { "network-default-interface-type": null } From c654cdc40b8786f6e6ace73e69f4b552e4b7c1d4 Mon Sep 17 00:00:00 2001 From: d-kato Date: Thu, 9 Jan 2020 16:18:14 +0900 Subject: [PATCH 08/49] GR_LYCHEE: enable bootloader support --- targets/targets.json | 2 +- tools/arm_pack_manager/index.json | 17 ++++++----------- 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index b954823690..fe1e40e9e4 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -5922,7 +5922,7 @@ "bootloader_supported": true, "mbed_rom_start" : "0x18000000", "mbed_rom_size" : "0x800000", - "sectors": [[402653184,4096]], + "sectors": [[0,4096]], "overrides": { "network-default-interface-type": null } diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index b23c6bdc06..a8f724c885 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -303013,7 +303013,7 @@ "version": "1.2.1" }, "memories": { - "PROGRAM_FLASH": { + "IRAM1": { "access": { "execute": true, "non_secure": false, @@ -303021,12 +303021,12 @@ "peripheral": false, "read": true, "secure": false, - "write": false + "write": true }, "default": true, - "size": 8388608, - "start": 402653184, - "startup": true + "size": 3145728, + "start": 536870912, + "startup": false } }, "name": "R7S72103", @@ -303038,12 +303038,7 @@ "units": 1 } }, - "sectors": [ - [ - 0, - 4096 - ] - ], + "sectors": [], "sub_family": "RZ_A1LU", "vendor": "Renesas:117" }, From b7e8cd22674178a5b6b8ee2a4d45b936fb4c4717 Mon Sep 17 00:00:00 2001 From: d-kato Date: Thu, 9 Jan 2020 16:15:50 +0900 Subject: [PATCH 09/49] RZ_A1H: enable bootloader support --- targets/targets.json | 2 +- tools/arm_pack_manager/index.json | 17 ++++++----------- 2 files changed, 7 insertions(+), 12 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index fe1e40e9e4..9914bf4aad 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -5902,7 +5902,7 @@ "bootloader_supported": true, "mbed_rom_start" : "0x18000000", "mbed_rom_size" : "0x800000", - "sectors": [[402653184,4096]] + "sectors": [[0,4096]] }, "VK_RZ_A1H": { "inherits": ["RZ_A1XX"], diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index a8f724c885..da5310ce25 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -302969,7 +302969,7 @@ "version": "1.2.1" }, "memories": { - "PROGRAM_FLASH": { + "IRAM1": { "access": { "execute": true, "non_secure": false, @@ -302977,12 +302977,12 @@ "peripheral": false, "read": true, "secure": false, - "write": false + "write": true }, "default": true, - "size": 8388608, - "start": 402653184, - "startup": true + "size": 10485760, + "start": 536870912, + "startup": false } }, "name": "R7S72100", @@ -302994,12 +302994,7 @@ "units": 1 } }, - "sectors": [ - [ - 0, - 4096 - ] - ], + "sectors": [], "sub_family": "RZ_A1H", "vendor": "Renesas:117" }, From 4c32297b07b40e1e2075533047cde84d594b4c26 Mon Sep 17 00:00:00 2001 From: adbridge Date: Fri, 27 Mar 2020 10:43:53 +0000 Subject: [PATCH 10/49] Revert "RZ_A1H: enable bootloader support" This reverts commit b7e8cd22674178a5b6b8ee2a4d45b936fb4c4717. --- targets/targets.json | 2 +- tools/arm_pack_manager/index.json | 17 +++++++++++------ 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index 9914bf4aad..fe1e40e9e4 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -5902,7 +5902,7 @@ "bootloader_supported": true, "mbed_rom_start" : "0x18000000", "mbed_rom_size" : "0x800000", - "sectors": [[0,4096]] + "sectors": [[402653184,4096]] }, "VK_RZ_A1H": { "inherits": ["RZ_A1XX"], diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index da5310ce25..a8f724c885 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -302969,7 +302969,7 @@ "version": "1.2.1" }, "memories": { - "IRAM1": { + "PROGRAM_FLASH": { "access": { "execute": true, "non_secure": false, @@ -302977,12 +302977,12 @@ "peripheral": false, "read": true, "secure": false, - "write": true + "write": false }, "default": true, - "size": 10485760, - "start": 536870912, - "startup": false + "size": 8388608, + "start": 402653184, + "startup": true } }, "name": "R7S72100", @@ -302994,7 +302994,12 @@ "units": 1 } }, - "sectors": [], + "sectors": [ + [ + 0, + 4096 + ] + ], "sub_family": "RZ_A1H", "vendor": "Renesas:117" }, From e273c3f0ab4fb1fca81d5e39e061a25128018f54 Mon Sep 17 00:00:00 2001 From: adbridge Date: Fri, 27 Mar 2020 10:44:20 +0000 Subject: [PATCH 11/49] Revert "GR_LYCHEE: enable bootloader support" This reverts commit c654cdc40b8786f6e6ace73e69f4b552e4b7c1d4. --- targets/targets.json | 2 +- tools/arm_pack_manager/index.json | 17 +++++++++++------ 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index fe1e40e9e4..b954823690 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -5922,7 +5922,7 @@ "bootloader_supported": true, "mbed_rom_start" : "0x18000000", "mbed_rom_size" : "0x800000", - "sectors": [[0,4096]], + "sectors": [[402653184,4096]], "overrides": { "network-default-interface-type": null } diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index a8f724c885..b23c6bdc06 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -303013,7 +303013,7 @@ "version": "1.2.1" }, "memories": { - "IRAM1": { + "PROGRAM_FLASH": { "access": { "execute": true, "non_secure": false, @@ -303021,12 +303021,12 @@ "peripheral": false, "read": true, "secure": false, - "write": true + "write": false }, "default": true, - "size": 3145728, - "start": 536870912, - "startup": false + "size": 8388608, + "start": 402653184, + "startup": true } }, "name": "R7S72103", @@ -303038,7 +303038,12 @@ "units": 1 } }, - "sectors": [], + "sectors": [ + [ + 0, + 4096 + ] + ], "sub_family": "RZ_A1LU", "vendor": "Renesas:117" }, From 468bd41f1390c1d0378819cd8cf0fe651b326045 Mon Sep 17 00:00:00 2001 From: adbridge Date: Fri, 27 Mar 2020 10:44:38 +0000 Subject: [PATCH 12/49] Revert "Add sector information" This reverts commit ed6869d9ecc78656942dbccb080a0fe5eed767cc. --- targets/targets.json | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index b954823690..32617dbc4e 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -5899,10 +5899,7 @@ "device_has_add": ["USBDEVICE", "EMAC", "FLASH", "LPTICKER"], "release_versions": ["2", "5"], "device_name": "R7S72100", - "bootloader_supported": true, - "mbed_rom_start" : "0x18000000", - "mbed_rom_size" : "0x800000", - "sectors": [[402653184,4096]] + "bootloader_supported": false }, "VK_RZ_A1H": { "inherits": ["RZ_A1XX"], @@ -5919,10 +5916,7 @@ "device_has_remove": ["ETHERNET"], "release_versions": ["2", "5"], "device_name": "R7S72103", - "bootloader_supported": true, - "mbed_rom_start" : "0x18000000", - "mbed_rom_size" : "0x800000", - "sectors": [[402653184,4096]], + "bootloader_supported": false, "overrides": { "network-default-interface-type": null } From 723f311de27567612012f0974088984e64c21c54 Mon Sep 17 00:00:00 2001 From: Teemu Takaluoma Date: Thu, 23 Jan 2020 10:16:28 +0200 Subject: [PATCH 13/49] Disable sleep on STM32F4 as an workaround for stability issues. This workaround is related to Mbed OS issue https://github.com/ARMmbed/mbed-os/issues/12294 --- targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c index dffb78e25c..e699fd9fff 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c @@ -391,7 +391,7 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) if(SLEEPEntry == PWR_SLEEPENTRY_WFI) { /* Request Wait For Interrupt */ - __WFI(); + __NOP(); } else { From b21aeaf1530bed959ddc81602c60460c01c64e84 Mon Sep 17 00:00:00 2001 From: Marcelo Salazar Date: Fri, 27 Mar 2020 11:58:46 +0000 Subject: [PATCH 14/49] Add workaround for F429 hardfault --- targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c index e699fd9fff..93f927bc37 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c @@ -391,7 +391,10 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) if(SLEEPEntry == PWR_SLEEPENTRY_WFI) { /* Request Wait For Interrupt */ - __NOP(); + __WFI(); + __NOP(); // Workaround for STM32F4 errata + __NOP(); // see chapter 2.1.3 - Debugging Sleep/Stop mode with WFE/WFI entry + __NOP(); // https://www.st.com/resource/en/errata_sheet/dm00037591-stm32f405-407xx-and-stm32f415-417xx-device-limitations-stmicroelectronics.pdf } else { From a325320c47660f24d22054a1ff3538a8542b1449 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Teppo=20J=C3=A4rvelin?= Date: Thu, 20 Feb 2020 10:09:28 +0200 Subject: [PATCH 15/49] Prepare for upcoming MbedTLS changes --- .../source/coap_security_handler.c | 25 +++++++++++++++++++ .../protocols/tls_sec_prot/tls_sec_prot_lib.c | 20 +++++++++++++++ features/netsocket/DTLSSocketWrapper.cpp | 6 +++++ features/netsocket/TLSSocketWrapper.cpp | 12 +++++++-- features/netsocket/TLSSocketWrapper.h | 3 +++ 5 files changed, 64 insertions(+), 2 deletions(-) diff --git a/features/nanostack/coap-service/source/coap_security_handler.c b/features/nanostack/coap-service/source/coap_security_handler.c index 1fbe3ffc86..bf6d8bb4b1 100644 --- a/features/nanostack/coap-service/source/coap_security_handler.c +++ b/features/nanostack/coap-service/source/coap_security_handler.c @@ -68,6 +68,7 @@ struct coap_security_s { }; +#if !defined(MBEDTLS_SSL_CONF_SINGLE_CIPHERSUITE) #if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) const int ECJPAKE_SUITES[] = { MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8, @@ -75,12 +76,15 @@ const int ECJPAKE_SUITES[] = { }; #endif +#if defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED) static const int PSK_SUITES[] = { MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256, MBEDTLS_TLS_PSK_WITH_AES_256_CCM_8, MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8, 0 }; +#endif /* defined(MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED) */ +#endif /* !defined(MBEDTLS_SSL_CONF_SINGLE_CIPHERSUITE) */ #define TRACE_GROUP "CsSh" @@ -332,7 +336,9 @@ static int coap_security_handler_configure_keys(coap_security_t *sec, coap_secur if (0 != mbedtls_ssl_conf_psk(&sec->_conf, keys._priv_key, keys._priv_key_len, keys._cert, keys._cert_len)) { break; } +#if !defined(MBEDTLS_SSL_CONF_SINGLE_CIPHERSUITE) mbedtls_ssl_conf_ciphersuites(&sec->_conf, PSK_SUITES); +#endif /* !defined(MBEDTLS_SSL_CONF_SINGLE_CIPHERSUITE) */ ret = 0; #endif break; @@ -342,7 +348,9 @@ static int coap_security_handler_configure_keys(coap_security_t *sec, coap_secur if (mbedtls_ssl_set_hs_ecjpake_password(&sec->_ssl, keys._key, keys._key_len) != 0) { return -1; } +#if !defined(MBEDTLS_SSL_CONF_SINGLE_CIPHERSUITE) mbedtls_ssl_conf_ciphersuites(&sec->_conf, ECJPAKE_SUITES); +#endif /* !defined(MBEDTLS_SSL_CONF_SINGLE_CIPHERSUITE) */ //NOTE: If thread starts supporting PSK in other modes, then this will be needed! mbedtls_ssl_conf_export_keys_cb(&sec->_conf, @@ -394,11 +402,23 @@ int coap_security_handler_connect_non_blocking(coap_security_t *sec, bool is_ser return -1; } + // Defines MBEDTLS_SSL_CONF_RECV/SEND/RECV_TIMEOUT define global functions which should be the same for all + // callers of mbedtls_ssl_set_bio_ctx and there should be only one ssl context. If these rules don't apply, + // these defines can't be used. +#if !defined(MBEDTLS_SSL_CONF_RECV) && !defined(MBEDTLS_SSL_CONF_SEND) && !defined(MBEDTLS_SSL_CONF_RECV_TIMEOUT) mbedtls_ssl_set_bio(&sec->_ssl, sec, f_send, f_recv, NULL); +#else + mbedtls_ssl_set_bio_ctx(&sec->_ssl, sec); +#endif /* !defined(MBEDTLS_SSL_CONF_RECV) && !defined(MBEDTLS_SSL_CONF_SEND) && !defined(MBEDTLS_SSL_CONF_RECV_TIMEOUT) */ + // Defines MBEDTLS_SSL_CONF_SET_TIMER/GET_TIMER define global functions which should be the same for all + // callers of mbedtls_ssl_set_timer_cb and there should be only one ssl context. If these rules don't apply, + // these defines can't be used. +#if !defined(MBEDTLS_SSL_CONF_SET_TIMER) && !defined(MBEDTLS_SSL_CONF_GET_TIMER) mbedtls_ssl_set_timer_cb(&sec->_ssl, sec, set_timer, get_timer); +#endif /* !defined(MBEDTLS_SSL_CONF_SET_TIMER) && !defined(MBEDTLS_SSL_CONF_GET_TIMER) */ #if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) //TODO: Figure out better way!!! @@ -420,8 +440,13 @@ int coap_security_handler_connect_non_blocking(coap_security_t *sec, bool is_ser &sec->_cookie); #endif +#if !defined(MBEDTLS_SSL_CONF_MIN_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MIN_MAJOR_VER) mbedtls_ssl_conf_min_version(&sec->_conf, MBEDTLS_SSL_MAJOR_VERSION_3, MBEDTLS_SSL_MAJOR_VERSION_3); +#endif /* !defined(MBEDTLS_SSL_CONF_MIN_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MIN_MAJOR_VER) */ + +#if !defined(MBEDTLS_SSL_CONF_MAX_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MAX_MAJOR_VER) mbedtls_ssl_conf_max_version(&sec->_conf, MBEDTLS_SSL_MAJOR_VERSION_3, MBEDTLS_SSL_MAJOR_VERSION_3); +#endif /* !defined(MBEDTLS_SSL_CONF_MAX_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MAX_MAJOR_VER) */ sec->_is_started = true; diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c index 6f236bcf1f..d7ee8951ee 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c @@ -340,9 +340,22 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p return -1; } + // Defines MBEDTLS_SSL_CONF_RECV/SEND/RECV_TIMEOUT define global functions which should be the same for all + // callers of mbedtls_ssl_set_bio_ctx and there should be only one ssl context. If these rules don't apply, + // these defines can't be used. +#if !defined(MBEDTLS_SSL_CONF_RECV) && !defined(MBEDTLS_SSL_CONF_SEND) && !defined(MBEDTLS_SSL_CONF_RECV_TIMEOUT) // Set calbacks mbedtls_ssl_set_bio(&sec->ssl, sec, tls_sec_prot_lib_ssl_send, tls_sec_prot_lib_ssl_recv, NULL); +#else + mbedtls_ssl_set_bio_ctx(&sec->ssl, sec); +#endif /* !defined(MBEDTLS_SSL_CONF_RECV) && !defined(MBEDTLS_SSL_CONF_SEND) && !defined(MBEDTLS_SSL_CONF_RECV_TIMEOUT) */ + +// Defines MBEDTLS_SSL_CONF_SET_TIMER/GET_TIMER define global functions which should be the same for all +// callers of mbedtls_ssl_set_timer_cb and there should be only one ssl context. If these rules don't apply, +// these defines can't be used. +#if !defined(MBEDTLS_SSL_CONF_SET_TIMER) && !defined(MBEDTLS_SSL_CONF_GET_TIMER) mbedtls_ssl_set_timer_cb(&sec->ssl, sec, tls_sec_prot_lib_ssl_set_timer, tls_sec_prot_lib_ssl_get_timer); +#endif /* !defined(MBEDTLS_SSL_CONF_SET_TIMER) && !defined(MBEDTLS_SSL_CONF_GET_TIMER) */ // Configure certificates, keys and certificate revocation list if (tls_sec_prot_lib_configure_certificates(sec, certs) != 0) { @@ -350,6 +363,7 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p return -1; } +#if !defined(MBEDTLS_SSL_CONF_SINGLE_CIPHERSUITE) // Configure ciphersuites static const int sec_suites[] = { MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8, @@ -358,6 +372,7 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p 0 }; mbedtls_ssl_conf_ciphersuites(&sec->conf, sec_suites); +#endif /* !defined(MBEDTLS_SSL_CONF_SINGLE_CIPHERSUITE) */ #ifdef TLS_SEC_PROT_LIB_TLS_DEBUG mbedtls_ssl_conf_dbg(&sec->conf, tls_sec_prot_lib_debug, sec); @@ -367,8 +382,13 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p // Export keys callback mbedtls_ssl_conf_export_keys_ext_cb(&sec->conf, tls_sec_prot_lib_ssl_export_keys, sec); +#if !defined(MBEDTLS_SSL_CONF_MIN_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MIN_MAJOR_VER) mbedtls_ssl_conf_min_version(&sec->conf, MBEDTLS_SSL_MAJOR_VERSION_3, MBEDTLS_SSL_MAJOR_VERSION_3); +#endif /* !defined(MBEDTLS_SSL_CONF_MIN_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MIN_MAJOR_VER) */ + +#if !defined(MBEDTLS_SSL_CONF_MAX_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MAX_MAJOR_VER) mbedtls_ssl_conf_max_version(&sec->conf, MBEDTLS_SSL_MAJOR_VERSION_3, MBEDTLS_SSL_MAJOR_VERSION_3); +#endif /* !defined(MBEDTLS_SSL_CONF_MAX_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MAX_MAJOR_VER) */ // Set certificate verify callback mbedtls_ssl_set_verify(&sec->ssl, tls_sec_prot_lib_x509_crt_verify, sec); diff --git a/features/netsocket/DTLSSocketWrapper.cpp b/features/netsocket/DTLSSocketWrapper.cpp index f567e31bbd..2251fd1d24 100644 --- a/features/netsocket/DTLSSocketWrapper.cpp +++ b/features/netsocket/DTLSSocketWrapper.cpp @@ -30,7 +30,13 @@ DTLSSocketWrapper::DTLSSocketWrapper(Socket *transport, const char *hostname, co _timer_expired(false) { mbedtls_ssl_conf_transport(get_ssl_config(), MBEDTLS_SSL_TRANSPORT_DATAGRAM); + + // Defines MBEDTLS_SSL_CONF_SET_TIMER/GET_TIMER define global functions which should be the same for all + // callers of mbedtls_ssl_set_timer_cb and there should be only one ssl context. If these rules don't apply, + // these defines can't be used +#if !defined(MBEDTLS_SSL_CONF_SET_TIMER) && !defined(MBEDTLS_SSL_CONF_GET_TIMER) mbedtls_ssl_set_timer_cb(get_ssl_context(), this, timing_set_delay, timing_get_delay); +#endif /* !defined(MBEDTLS_SSL_CONF_SET_TIMER) && !defined(MBEDTLS_SSL_CONF_GET_TIMER) */ } void DTLSSocketWrapper::timing_set_delay(void *ctx, uint32_t int_ms, uint32_t fin_ms) diff --git a/features/netsocket/TLSSocketWrapper.cpp b/features/netsocket/TLSSocketWrapper.cpp index 68d24127b2..c8b46adf2d 100644 --- a/features/netsocket/TLSSocketWrapper.cpp +++ b/features/netsocket/TLSSocketWrapper.cpp @@ -85,7 +85,7 @@ TLSSocketWrapper::~TLSSocketWrapper() void TLSSocketWrapper::set_hostname(const char *hostname) { -#ifdef MBEDTLS_X509_CRT_PARSE_C +#if defined(MBEDTLS_X509_CRT_PARSE_C) && !defined(MBEDTLS_X509_REMOVE_HOSTNAME_VERIFICATION) mbedtls_ssl_set_hostname(&_ssl, hostname); #endif } @@ -207,7 +207,15 @@ nsapi_error_t TLSSocketWrapper::start_handshake(bool first_call) _transport->set_blocking(false); _transport->sigio(mbed::callback(this, &TLSSocketWrapper::event)); - mbedtls_ssl_set_bio(&_ssl, this, ssl_send, ssl_recv, NULL); + + // Defines MBEDTLS_SSL_CONF_RECV/SEND/RECV_TIMEOUT define global functions which should be the same for all + // callers of mbedtls_ssl_set_bio_ctx and there should be only one ssl context. If these rules don't apply, + // these defines can't be used. +#if !defined(MBEDTLS_SSL_CONF_RECV) && !defined(MBEDTLS_SSL_CONF_SEND) && !defined(MBEDTLS_SSL_CONF_RECV_TIMEOUT) + mbedtls_ssl_set_bio(&_ssl, this, ssl_send, ssl_recv, nullptr); +#else + mbedtls_ssl_set_bio_ctx(&_ssl, this); +#endif /* !defined(MBEDTLS_SSL_CONF_RECV) && !defined(MBEDTLS_SSL_CONF_SEND) && !defined(MBEDTLS_SSL_CONF_RECV_TIMEOUT) */ _tls_initialized = true; diff --git a/features/netsocket/TLSSocketWrapper.h b/features/netsocket/TLSSocketWrapper.h index 2a3e03e567..9b21b7c692 100644 --- a/features/netsocket/TLSSocketWrapper.h +++ b/features/netsocket/TLSSocketWrapper.h @@ -66,6 +66,9 @@ public: virtual ~TLSSocketWrapper(); /** Set hostname. + * + * @note Implementation is inside following defines: + * #if defined(MBEDTLS_X509_CRT_PARSE_C) && !defined(MBEDTLS_X509_REMOVE_HOSTNAME_VERIFICATION) * * TLSSocket requires hostname used to verify the certificate. * If hostname is not given in constructor, this function must be used before From 163e5c90e3e120441c33d71c52056666b47d9876 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Teppo=20J=C3=A4rvelin?= Date: Thu, 20 Feb 2020 10:56:20 +0200 Subject: [PATCH 16/49] Added new global rng, needed for MbedTLS optimisations --- .../src/apps/altcp_tls/altcp_tls_mbedtls.c | 10 ++ features/mbedtls/platform/inc/shared_rng.h | 93 +++++++++++++++++++ features/mbedtls/platform/src/shared_rng.cpp | 75 +++++++++++++++ .../source/coap_security_handler.c | 2 + .../protocols/tls_sec_prot/tls_sec_prot_lib.c | 2 + features/netsocket/TLSSocketWrapper.cpp | 2 + 6 files changed, 184 insertions(+) create mode 100644 features/mbedtls/platform/inc/shared_rng.h create mode 100644 features/mbedtls/platform/src/shared_rng.cpp diff --git a/features/lwipstack/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c b/features/lwipstack/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c index d642decb54..93f458991b 100644 --- a/features/lwipstack/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c +++ b/features/lwipstack/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c @@ -599,8 +599,15 @@ altcp_mbedtls_setup(void *conf, struct altcp_pcb *conn, struct altcp_pcb *inner_ altcp_mbedtls_free(conf, state); return ERR_MEM; } + // Defines MBEDTLS_SSL_CONF_RECV/SEND/RECV_TIMEOUT define global functions which should be the same for all + // callers of mbedtls_ssl_set_bio_ctx and there should be only one ssl context. If these rules don't apply, + // these defines can't be used. +#if !defined(MBEDTLS_SSL_CONF_RECV) && !defined(MBEDTLS_SSL_CONF_SEND) && !defined(MBEDTLS_SSL_CONF_RECV_TIMEOUT) /* tell mbedtls about our I/O functions */ mbedtls_ssl_set_bio(&state->ssl_context, conn, altcp_mbedtls_bio_send, altcp_mbedtls_bio_recv, NULL); +#else + mbedtls_ssl_set_bio_ctx(&state->ssl_context, conn); +#endif /* !defined(MBEDTLS_SSL_CONF_RECV) && !defined(MBEDTLS_SSL_CONF_SEND) && !defined(MBEDTLS_SSL_CONF_RECV_TIMEOUT) */ altcp_mbedtls_setup_callbacks(conn, inner_conn); conn->inner_conn = inner_conn; @@ -734,7 +741,10 @@ altcp_tls_create_config(int is_server, int have_cert, int have_pkey, int have_ca } mbedtls_ssl_conf_authmode(&conf->conf, MBEDTLS_SSL_VERIFY_OPTIONAL); +#if !defined(MBEDTLS_SSL_CONF_RNG) mbedtls_ssl_conf_rng(&conf->conf, mbedtls_ctr_drbg_random, &conf->ctr_drbg); +#endif + #if ALTCP_MBEDTLS_DEBUG != LWIP_DBG_OFF mbedtls_ssl_conf_dbg(&conf->conf, altcp_mbedtls_debug, stdout); #endif diff --git a/features/mbedtls/platform/inc/shared_rng.h b/features/mbedtls/platform/inc/shared_rng.h new file mode 100644 index 0000000000..154bdfa184 --- /dev/null +++ b/features/mbedtls/platform/inc/shared_rng.h @@ -0,0 +1,93 @@ +/* + * shared_rng.h + * + * Copyright (C) 2019, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef SHARED_RNG_H +#define SHARED_RNG_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_SSL_CONF_RNG) + +#define MBED_SHARED_RNG_NOT_INITIALIZED -1 /**< init_global_rng not called before global_rng */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mbedtls/hmac_drbg.h" +#include "mbedtls/entropy.h" + +/** + * \brief Initializes hmac ready for rng + * + * \return 0 if successful, or + * MBEDTLS_ERR_MD_BAD_INPUT_DATA, or + * MBEDTLS_ERR_MD_ALLOC_FAILED, or + * MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED. + */ +int init_global_rng(); + +/** + * \brief Global HMAC_DRBG generate random + * + * \note Automatically reseeds if reseed_counter is reached or PR is enabled. + * \note init_global_rng function must be called + * before calling this function! + * + * \param ctx DRBG context + * \param dst Buffer to fill + * \param len Length of the buffer + * + * \return 0 if successful, or + * MBEDTLS_ERR_HMAC_DRBG_ENTROPY_SOURCE_FAILED, or + * MBEDTLS_ERR_HMAC_DRBG_REQUEST_TOO_BIG or + * MBED_SHARED_RNG_NOT_INITIALIZED + */ +int global_rng( void *ctx, unsigned char *dst, size_t len ); + +/** + * \brief Free allocated resources + */ +void free_global_rng(); + +/** + * \brief Getter function for global hmac context + * + * \return global hmac context + */ +mbedtls_hmac_drbg_context *get_global_hmac_drbg(); + +/** + * \brief Getter function for global entropy context + * + * \return global entropy context + */ +mbedtls_entropy_context *get_global_entropy(); + +#ifdef __cplusplus +} +#endif + +#endif // MBEDTLS_SSL_CONF_RNG +#endif // SHARED_RNG_H diff --git a/features/mbedtls/platform/src/shared_rng.cpp b/features/mbedtls/platform/src/shared_rng.cpp new file mode 100644 index 0000000000..373b1ad9d9 --- /dev/null +++ b/features/mbedtls/platform/src/shared_rng.cpp @@ -0,0 +1,75 @@ +/* + * shared_rng.cpp + * + * Copyright (C) 2019, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#include "shared_rng.h" + +#if defined(MBEDTLS_SSL_CONF_RNG) + +#include "mbed_trace.h" + +mbedtls_hmac_drbg_context global_hmac_drbg; +mbedtls_entropy_context global_entropy; +static bool is_initialized = false; + +int init_global_rng() +{ + mbedtls_entropy_init(&global_entropy); + mbedtls_hmac_drbg_init(&global_hmac_drbg); + + int ret = mbedtls_hmac_drbg_seed(&global_hmac_drbg, mbedtls_md_info_from_type(MBEDTLS_MD_SHA256), + mbedtls_entropy_func, &global_entropy, NULL, 0); + + if (ret != 0) { + tr_error(" init_global_rng failed! mbedtls_hmac_drbg_seed returned -0x%x", -ret); + free_global_rng(); + } else { + is_initialized = true; + } + + return ret; +This conversation was marked as resolved by jarvte +} + +void free_global_rng() +{ + mbedtls_entropy_free(&global_entropy); + mbedtls_hmac_drbg_free(&global_hmac_drbg); + is_initialized = false; +} + +int global_rng( void *ctx, unsigned char *dst, size_t len ) +{ + if (!is_initialized) { + return MBED_SHARED_RNG_NOT_INITIALIZED; + } + return mbedtls_hmac_drbg_random(&global_hmac_drbg, dst, len); +} + +mbedtls_hmac_drbg_context *get_global_hmac_drbg() +{ + return &global_hmac_drbg; +} + +mbedtls_entropy_context *get_global_entropy() +{ + return &global_entropy; +} + +#endif // MBEDTLS_SSL_CONF_RNG diff --git a/features/nanostack/coap-service/source/coap_security_handler.c b/features/nanostack/coap-service/source/coap_security_handler.c index bf6d8bb4b1..d56c494c86 100644 --- a/features/nanostack/coap-service/source/coap_security_handler.c +++ b/features/nanostack/coap-service/source/coap_security_handler.c @@ -396,7 +396,9 @@ int coap_security_handler_connect_non_blocking(coap_security_t *sec, bool is_ser mbedtls_ssl_conf_handshake_timeout(&sec->_conf, timeout_min, timeout_max); } +#if !defined(MBEDTLS_SSL_CONF_RNG) mbedtls_ssl_conf_rng(&sec->_conf, mbedtls_ctr_drbg_random, &sec->_ctr_drbg); +#endif if ((mbedtls_ssl_setup(&sec->_ssl, &sec->_conf)) != 0) { return -1; diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c index d7ee8951ee..9c9ff8b72b 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c @@ -327,8 +327,10 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p return -1; } +#if !defined(MBEDTLS_SSL_CONF_RNG) // Configure random number generator mbedtls_ssl_conf_rng(&sec->conf, mbedtls_ctr_drbg_random, &sec->ctr_drbg); +#endif #ifdef MBEDTLS_ECP_RESTARTABLE // Set ECC calculation maximum operations (affects only client) diff --git a/features/netsocket/TLSSocketWrapper.cpp b/features/netsocket/TLSSocketWrapper.cpp index c8b46adf2d..11379c29f3 100644 --- a/features/netsocket/TLSSocketWrapper.cpp +++ b/features/netsocket/TLSSocketWrapper.cpp @@ -190,7 +190,9 @@ nsapi_error_t TLSSocketWrapper::start_handshake(bool first_call) return NSAPI_ERROR_AUTH_FAILURE; } +#if !defined(MBEDTLS_SSL_CONF_RNG) mbedtls_ssl_conf_rng(get_ssl_config(), mbedtls_ctr_drbg_random, &_ctr_drbg); +#endif #if MBED_CONF_TLS_SOCKET_DEBUG_LEVEL > 0 From c801caf7cf12f0ec9c1b789012c8b452804fa04b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Teppo=20J=C3=A4rvelin?= Date: Thu, 20 Feb 2020 11:07:01 +0200 Subject: [PATCH 17/49] fixed ssl hostname handling --- features/netsocket/TLSSocketWrapper.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/features/netsocket/TLSSocketWrapper.cpp b/features/netsocket/TLSSocketWrapper.cpp index 11379c29f3..9b56104884 100644 --- a/features/netsocket/TLSSocketWrapper.cpp +++ b/features/netsocket/TLSSocketWrapper.cpp @@ -175,7 +175,7 @@ nsapi_error_t TLSSocketWrapper::start_handshake(bool first_call) return continue_handshake(); } -#ifdef MBEDTLS_X509_CRT_PARSE_C +#if defined(MBEDTLS_X509_CRT_PARSE_C) && !defined(MBEDTLS_X509_REMOVE_HOSTNAME_VERIFICATION) tr_info("Starting TLS handshake with %s", _ssl.hostname); #else tr_info("Starting TLS handshake"); @@ -267,7 +267,7 @@ nsapi_error_t TLSSocketWrapper::continue_handshake() } } -#ifdef MBEDTLS_X509_CRT_PARSE_C +#if defined(MBEDTLS_X509_CRT_PARSE_C) && !defined(MBEDTLS_X509_REMOVE_HOSTNAME_VERIFICATION) /* It also means the handshake is done, time to print info */ tr_info("TLS connection to %s established", _ssl.hostname); #else From 377e36305912946ee59d987e8a2f432f21e106ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Teppo=20J=C3=A4rvelin?= Date: Thu, 20 Feb 2020 12:08:57 +0200 Subject: [PATCH 18/49] Added missing optimizations based on mbedtls/baremetal.h config --- TESTS/mbedtls/multi/main.cpp | 34 ++++++++-------- .../TESTS/device_key/functionality/main.cpp | 6 +++ .../src/apps/altcp_tls/altcp_tls_mbedtls.c | 28 ++++++++++--- features/mbedtls/platform/src/shared_rng.cpp | 6 +-- .../source/coap_security_handler.c | 40 ++++++++++++++++--- .../coap-service/unittest/stub/mbedtls_stub.c | 32 +++++++++++++++ .../coap-service/unittest/stub/mbedtls_stub.h | 2 + .../sal-stack-nanostack/nanostack/ns_sha256.h | 16 ++++---- features/netsocket/TLSSocketWrapper.cpp | 33 ++++++++++++--- features/netsocket/TLSSocketWrapper.h | 11 ++++- 10 files changed, 162 insertions(+), 46 deletions(-) diff --git a/TESTS/mbedtls/multi/main.cpp b/TESTS/mbedtls/multi/main.cpp index e6a03f450b..1e8420c875 100644 --- a/TESTS/mbedtls/multi/main.cpp +++ b/TESTS/mbedtls/multi/main.cpp @@ -33,7 +33,7 @@ using namespace utest::v1; #if defined(MBEDTLS_SHA256_C) -/* Tests several call to mbedtls_sha256_update function that are not modulo 64 bytes */ +/* Tests several call to mbedtls_sha256_update_ret function that are not modulo 64 bytes */ void test_case_sha256_split() { const unsigned char test_buf[] = {"abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopqabcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopqabcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"}; @@ -50,18 +50,18 @@ void test_case_sha256_split() mbedtls_sha256_context ctx; printf("test sha256\n"); mbedtls_sha256_init(&ctx); - mbedtls_sha256_starts(&ctx, 0); + (void)mbedtls_sha256_starts_ret(&ctx, 0); #if 0 printf("test not splitted\n"); - mbedtls_sha256_update(&ctx, test_buf, 168); + (void)mbedtls_sha256_update_ret(&ctx, test_buf, 168); #else printf("test splitted into 3 pieces\n"); - mbedtls_sha256_update(&ctx, test_buf, 2); - mbedtls_sha256_update(&ctx, test_buf + 2, 66); - mbedtls_sha256_update(&ctx, test_buf + 68, 100); + (void)mbedtls_sha256_update_ret(&ctx, test_buf, 2); + (void)mbedtls_sha256_update_ret(&ctx, test_buf + 2, 66); + (void)mbedtls_sha256_update_ret(&ctx, test_buf + 68, 100); #endif - mbedtls_sha256_finish(&ctx, outsum); + (void)mbedtls_sha256_finish_ret(&ctx, outsum); mbedtls_sha256_free(&ctx); printf("\nreceived result : "); @@ -113,29 +113,29 @@ void test_case_sha256_multi() mbedtls_sha256_init(&ctx2); mbedtls_sha256_init(&ctx3); //Start both contexts - mbedtls_sha256_starts(&ctx1, 0); - mbedtls_sha256_starts(&ctx2, 0); + (void)mbedtls_sha256_starts_ret(&ctx1, 0); + (void)mbedtls_sha256_starts_ret(&ctx2, 0); printf("upd ctx1\n"); - mbedtls_sha256_update(&ctx1, test_buf, 56); + (void)mbedtls_sha256_update_ret(&ctx1, test_buf, 56); printf("upd ctx2\n"); - mbedtls_sha256_update(&ctx2, test_buf, 66); + (void)mbedtls_sha256_update_ret(&ctx2, test_buf, 66); printf("finish ctx1\n"); - mbedtls_sha256_finish(&ctx1, outsum1); + (void)mbedtls_sha256_finish_ret(&ctx1, outsum1); printf("upd ctx2\n"); - mbedtls_sha256_update(&ctx2, test_buf + 66, 46); + (void)mbedtls_sha256_update_ret(&ctx2, test_buf + 66, 46); printf("clone ctx2 in ctx3\n"); mbedtls_sha256_clone(&ctx3, (const mbedtls_sha256_context *)&ctx2); printf("free ctx1\n"); mbedtls_sha256_free(&ctx1); printf("upd ctx2\n"); - mbedtls_sha256_update(&ctx2, test_buf + 112, 56); + (void)mbedtls_sha256_update_ret(&ctx2, test_buf + 112, 56); printf("upd ctx3 with different values than ctx2\n"); - mbedtls_sha256_update(&ctx3, test_buf2, 56); + (void)mbedtls_sha256_update_ret(&ctx3, test_buf2, 56); printf("finish ctx2\n"); - mbedtls_sha256_finish(&ctx2, outsum2); + (void)mbedtls_sha256_finish_ret(&ctx2, outsum2); printf("finish ctx3\n"); - mbedtls_sha256_finish(&ctx3, outsum3); + (void)mbedtls_sha256_finish_ret(&ctx3, outsum3); printf("free ctx2\n"); mbedtls_sha256_free(&ctx2); printf("free ctx3\n"); diff --git a/features/device_key/TESTS/device_key/functionality/main.cpp b/features/device_key/TESTS/device_key/functionality/main.cpp index 22bd47d41d..3e9f471078 100644 --- a/features/device_key/TESTS/device_key/functionality/main.cpp +++ b/features/device_key/TESTS/device_key/functionality/main.cpp @@ -72,10 +72,12 @@ void generate_derived_key_long_consistency_test() generate_derived_key_consistency_16_byte_key_long_consistency_test(key); strcpy(key, MSG_KEY_DEVICE_TEST_STEP2); generate_derived_key_consistency_16_byte_key_long_consistency_test(key); +#ifndef MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH strcpy(key, MSG_KEY_DEVICE_TEST_STEP3); generate_derived_key_consistency_32_byte_key_long_consistency_test(key); strcpy(key, MSG_KEY_DEVICE_TEST_STEP4); generate_derived_key_consistency_32_byte_key_long_consistency_test(key); +#endif } @@ -476,12 +478,16 @@ Case cases[] = { Case("Device Key - long consistency test", generate_derived_key_long_consistency_test, greentea_failure_handler), Case("Device Key - inject value wrong size", device_inject_root_of_trust_wrong_size_test, greentea_failure_handler), Case("Device Key - inject value 16 byte size", device_inject_root_of_trust_16_byte_size_test, greentea_failure_handler), +#ifndef MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH Case("Device Key - inject value 32 byte size", device_inject_root_of_trust_32_byte_size_test, greentea_failure_handler), +#endif Case("Device Key - inject value several times", device_inject_root_of_trust_several_times_test, greentea_failure_handler), Case("Device Key - derived key consistency 16 byte key", generate_derived_key_consistency_16_byte_key_test, greentea_failure_handler), Case("Device Key - derived key consistency 32 byte key", generate_derived_key_consistency_32_byte_key_test, greentea_failure_handler), Case("Device Key - derived key key type 16", generate_derived_key_key_type_16_test, greentea_failure_handler), +#ifndef MBEDTLS_AES_ONLY_128_BIT_KEY_LENGTH Case("Device Key - derived key key type 32", generate_derived_key_key_type_32_test, greentea_failure_handler), +#endif Case("Device Key - derived key wrong key type", generate_derived_key_wrong_key_type_test, greentea_failure_handler) }; diff --git a/features/lwipstack/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c b/features/lwipstack/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c index 93f458991b..90cd5e0745 100644 --- a/features/lwipstack/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c +++ b/features/lwipstack/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c @@ -69,6 +69,7 @@ /* @todo: which includes are really needed? */ #include "mbedtls/entropy.h" #include "mbedtls/ctr_drbg.h" +#include "mbedtls/hmac_drbg.h" #include "mbedtls/certs.h" #include "mbedtls/x509.h" #include "mbedtls/ssl.h" @@ -98,7 +99,21 @@ extern const struct altcp_functions altcp_mbedtls_functions; struct altcp_tls_config { mbedtls_ssl_config conf; mbedtls_entropy_context entropy; - mbedtls_ctr_drbg_context ctr_drbg; +#if defined(MBEDTLS_CTR_DRBG_C) + mbedtls_ctr_drbg_context _drbg; +#define DRBG_INIT mbedtls_ctr_drbg_init +#define DRBG_SEED mbedtls_ctr_drbg_seed +#define DRBG_SEED_ERROR "mbedtls_ctr_drbg_seed failed: %d\n" +#define DRBG_RANDOM mbedtls_ctr_drbg_random +#elif defined(MBEDTLS_HMAC_DRBG_C) + mbedtls_hmac_drbg_context _drbg; +#define DRBG_INIT mbedtls_hmac_drbg_init +#define DRBG_SEED mbedtls_hmac_drbg_seed +#define DRBG_SEED_ERROR "mbedtls_hmac_drbg_seed failed: %d\n" +#define DRBG_RANDOM mbedtls_hmac_drbg_random +#else +#error "CTR or HMAC must be defined for coap_security_handler!" +#endif mbedtls_x509_crt *cert; mbedtls_pk_context *pkey; mbedtls_x509_crt *ca; @@ -721,12 +736,15 @@ altcp_tls_create_config(int is_server, int have_cert, int have_pkey, int have_ca mbedtls_ssl_config_init(&conf->conf); mbedtls_entropy_init(&conf->entropy); - mbedtls_ctr_drbg_init(&conf->ctr_drbg); + + DRBG_INIT(&conf->_drbg); /* Seed the RNG */ - ret = mbedtls_ctr_drbg_seed(&conf->ctr_drbg, ALTCP_MBEDTLS_RNG_FN, &conf->entropy, ALTCP_MBEDTLS_ENTROPY_PTR, ALTCP_MBEDTLS_ENTROPY_LEN); + ret = DRBG_SEED(&conf->_drbg, ALTCP_MBEDTLS_RNG_FN, &conf->entropy, ALTCP_MBEDTLS_ENTROPY_PTR, ALTCP_MBEDTLS_ENTROPY_LEN); + if (ret != 0) { - LWIP_DEBUGF(ALTCP_MBEDTLS_DEBUG, ("mbedtls_ctr_drbg_seed failed: %d\n", ret)); + LWIP_DEBUGF(ALTCP_MBEDTLS_DEBUG, (DRBG_SEED_ERROR, ret)); + altcp_mbedtls_free_config(conf); return NULL; } @@ -742,7 +760,7 @@ altcp_tls_create_config(int is_server, int have_cert, int have_pkey, int have_ca mbedtls_ssl_conf_authmode(&conf->conf, MBEDTLS_SSL_VERIFY_OPTIONAL); #if !defined(MBEDTLS_SSL_CONF_RNG) - mbedtls_ssl_conf_rng(&conf->conf, mbedtls_ctr_drbg_random, &conf->ctr_drbg); + mbedtls_ssl_conf_rng(&conf->conf, DRBG_RANDOM, &conf->ctr_drbg); #endif #if ALTCP_MBEDTLS_DEBUG != LWIP_DBG_OFF diff --git a/features/mbedtls/platform/src/shared_rng.cpp b/features/mbedtls/platform/src/shared_rng.cpp index 373b1ad9d9..970e3de71f 100644 --- a/features/mbedtls/platform/src/shared_rng.cpp +++ b/features/mbedtls/platform/src/shared_rng.cpp @@ -33,8 +33,9 @@ int init_global_rng() mbedtls_entropy_init(&global_entropy); mbedtls_hmac_drbg_init(&global_hmac_drbg); - int ret = mbedtls_hmac_drbg_seed(&global_hmac_drbg, mbedtls_md_info_from_type(MBEDTLS_MD_SHA256), - mbedtls_entropy_func, &global_entropy, NULL, 0); + int ret = mbedtls_hmac_drbg_seed(&global_hmac_drbg, + mbedtls_md_info_from_type(MBEDTLS_MD_SHA256), + mbedtls_entropy_func, &global_entropy, NULL, 0); if (ret != 0) { tr_error(" init_global_rng failed! mbedtls_hmac_drbg_seed returned -0x%x", -ret); @@ -44,7 +45,6 @@ int init_global_rng() } return ret; -This conversation was marked as resolved by jarvte } void free_global_rng() diff --git a/features/nanostack/coap-service/source/coap_security_handler.c b/features/nanostack/coap-service/source/coap_security_handler.c index d56c494c86..99be31e24e 100644 --- a/features/nanostack/coap-service/source/coap_security_handler.c +++ b/features/nanostack/coap-service/source/coap_security_handler.c @@ -30,6 +30,7 @@ #include "mbedtls/entropy.h" #include "mbedtls/entropy_poll.h" #include "mbedtls/ctr_drbg.h" +#include "mbedtls/hmac_drbg.h" #include "mbedtls/ssl_ciphersuites.h" #include "ns_trace.h" @@ -41,7 +42,14 @@ struct coap_security_s { mbedtls_ssl_config _conf; mbedtls_ssl_context _ssl; - mbedtls_ctr_drbg_context _ctr_drbg; +#if defined(MBEDTLS_CTR_DRBG_C) + mbedtls_ctr_drbg_context _drbg; +#elif defined(MBEDTLS_HMAC_DRBG_C) + mbedtls_hmac_drbg_context _drbg; +#else +#error "CTR or HMAC must be defined for coap_security_handler!" +#endif + mbedtls_entropy_context _entropy; bool _is_started; simple_cookie_t _cookie; @@ -114,7 +122,11 @@ static int coap_security_handler_init(coap_security_t *sec) mbedtls_ssl_init(&sec->_ssl); mbedtls_ssl_config_init(&sec->_conf); - mbedtls_ctr_drbg_init(&sec->_ctr_drbg); +#if defined(MBEDTLS_CTR_DRBG_C) + mbedtls_ctr_drbg_init(&sec->_drbg); +#elif defined(MBEDTLS_HMAC_DRBG_C) + mbedtls_hmac_drbg_init(&sec->_drbg); +#endif mbedtls_entropy_init(&sec->_entropy); #if defined(MBEDTLS_X509_CRT_PARSE_C) @@ -132,12 +144,20 @@ static int coap_security_handler_init(coap_security_t *sec) 128, entropy_source_type) < 0) { return -1; } - - if ((mbedtls_ctr_drbg_seed(&sec->_ctr_drbg, mbedtls_entropy_func, &sec->_entropy, +#if defined(MBEDTLS_CTR_DRBG_C) + if ((mbedtls_ctr_drbg_seed(&sec->_drbg, mbedtls_entropy_func, &sec->_entropy, (const unsigned char *) pers, strlen(pers))) != 0) { return -1; } +#elif defined(MBEDTLS_HMAC_DRBG_C) + if ((mbedtls_hmac_drbg_seed(&sec->_drbg, mbedtls_md_info_from_type(MBEDTLS_MD_SHA256), + mbedtls_entropy_func, &sec->_entropy, + (const unsigned char *) pers, + strlen(pers))) != 0) { + return -1; + } +#endif return 0; } @@ -160,7 +180,11 @@ static void coap_security_handler_reset(coap_security_t *sec) #endif mbedtls_entropy_free(&sec->_entropy); - mbedtls_ctr_drbg_free(&sec->_ctr_drbg); +#if defined(MBEDTLS_CTR_DRBG_C) + mbedtls_ctr_drbg_free(&sec->_drbg); +#elif defined(MBEDTLS_HMAC_DRBG_C) + mbedtls_hmac_drbg_free(&sec->_drbg); +#endif mbedtls_ssl_config_free(&sec->_conf); mbedtls_ssl_free(&sec->_ssl); #if defined(MBEDTLS_PLATFORM_C) @@ -397,7 +421,11 @@ int coap_security_handler_connect_non_blocking(coap_security_t *sec, bool is_ser } #if !defined(MBEDTLS_SSL_CONF_RNG) - mbedtls_ssl_conf_rng(&sec->_conf, mbedtls_ctr_drbg_random, &sec->_ctr_drbg); +#if defined(MBEDTLS_CTR_DRBG_C) + mbedtls_ssl_conf_rng(&sec->_conf, mbedtls_ctr_drbg_random, &sec->_drbg); +#elif defined(MBEDTLS_HMAC_DRBG_C) + mbedtls_ssl_conf_rng(&sec->_conf, mbedtls_hmac_drbg_random, &sec->_drbg); +#endif #endif if ((mbedtls_ssl_setup(&sec->_ssl, &sec->_conf)) != 0) { diff --git a/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c b/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c index e607acd4d3..615bae7530 100644 --- a/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c +++ b/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c @@ -248,6 +248,38 @@ int mbedtls_ctr_drbg_random(void *p_rng, return mbedtls_stub.crt_expected_int; } +// from hmac_drbg.h +void mbedtls_hmac_drbg_init( mbedtls_hmac_drbg_context *ctx ) +{ + +} + +void mbedtls_hmac_drbg_free( mbedtls_hmac_drbg_context *ctx ) +{ + +} + +int mbedtls_hmac_drbg_seed( mbedtls_hmac_drbg_context *ctx, + mbedtls_md_handle_t md_info, + int (*f_entropy)(void *, unsigned char *, size_t), + void *p_entropy, + const unsigned char *custom, + size_t len ) +{ + return mbedtls_stub.crt_expected_int; +} + +int mbedtls_hmac_drbg_random( void *p_rng, unsigned char *output, size_t out_len ) +{ + return mbedtls_stub.crt_expected_int; +} + +// from md.h +mbedtls_md_handle_t mbedtls_md_info_from_type( mbedtls_md_type_t md_type ) +{ + return 0; +} + //From x509_crt.h void mbedtls_x509_crt_init(mbedtls_x509_crt *a) { diff --git a/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.h b/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.h index 2ad72cb939..1910f9c5f2 100644 --- a/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.h +++ b/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.h @@ -24,11 +24,13 @@ #include "mbedtls/platform.h" #include "mbedtls/ssl.h" #include "mbedtls/ctr_drbg.h" +#include "mbedtls/hmac_drbg.h" #include "mbedtls/x509_crt.h" #include "mbedtls/sha256.h" #include "mbedtls/entropy.h" #include "mbedtls/pk.h" #include "mbedtls/platform.h" +#include "mbedtls/md.h" #define HANDSHAKE_FINISHED_VALUE 8888 diff --git a/features/nanostack/sal-stack-nanostack/nanostack/ns_sha256.h b/features/nanostack/sal-stack-nanostack/nanostack/ns_sha256.h index 6aafd78046..d088188608 100644 --- a/features/nanostack/sal-stack-nanostack/nanostack/ns_sha256.h +++ b/features/nanostack/sal-stack-nanostack/nanostack/ns_sha256.h @@ -61,23 +61,23 @@ static inline void ns_sha256_clone(ns_sha256_context *dst, static inline void ns_sha256_starts(ns_sha256_context *ctx) { - mbedtls_sha256_starts(ctx, 0); + (void)mbedtls_sha256_starts_ret(ctx, 0); } static inline void ns_sha256_update(ns_sha256_context *ctx, const void *input, size_t ilen) { - mbedtls_sha256_update(ctx, input, ilen); + (void)mbedtls_sha256_update_ret(ctx, input, ilen); } static inline void ns_sha256_finish(ns_sha256_context *ctx, void *output) { - mbedtls_sha256_finish(ctx, output); + (void)mbedtls_sha256_finish_ret(ctx, output); } static inline void ns_sha256(const void *input, size_t ilen, void *output) { - mbedtls_sha256(input, ilen, output, 0); + (void)mbedtls_sha256_ret(input, ilen, output, 0); } /* Extensions to standard mbed TLS - output the first bits of a hash only */ @@ -85,10 +85,10 @@ static inline void ns_sha256(const void *input, size_t ilen, void *output) static inline void ns_sha256_finish_nbits(ns_sha256_context *ctx, void *output, unsigned obits) { if (obits == 256) { - mbedtls_sha256_finish(ctx, output); + (void)mbedtls_sha256_finish_ret(ctx, output); } else { uint8_t sha256[32]; - mbedtls_sha256_finish(ctx, sha256); + (void)mbedtls_sha256_finish_ret(ctx, sha256); memcpy(output, sha256, obits / 8); } } @@ -96,10 +96,10 @@ static inline void ns_sha256_finish_nbits(ns_sha256_context *ctx, void *output, static inline void ns_sha256_nbits(const void *input, size_t ilen, void *output, unsigned obits) { if (obits == 256) { - mbedtls_sha256(input, ilen, output, 0); + (void)mbedtls_sha256_ret(input, ilen, output, 0); } else { uint8_t sha256[32]; - mbedtls_sha256(input, ilen, sha256, 0); + (void)mbedtls_sha256_ret(input, ilen, sha256, 0); memcpy(output, sha256, obits / 8); } } diff --git a/features/netsocket/TLSSocketWrapper.cpp b/features/netsocket/TLSSocketWrapper.cpp index 9b56104884..d01959f09f 100644 --- a/features/netsocket/TLSSocketWrapper.cpp +++ b/features/netsocket/TLSSocketWrapper.cpp @@ -53,7 +53,12 @@ TLSSocketWrapper::TLSSocketWrapper(Socket *transport, const char *hostname, cont } #endif /* MBEDTLS_PLATFORM_C */ mbedtls_entropy_init(&_entropy); - mbedtls_ctr_drbg_init(&_ctr_drbg); +#if defined(MBEDTLS_CTR_DRBG_C) + mbedtls_ctr_drbg_init(&_drbg); +#elif defined(MBEDTLS_HMAC_DRBG_C) + mbedtls_hmac_drbg_init(&_drbg); +#endif + mbedtls_ssl_init(&_ssl); #if defined(MBEDTLS_X509_CRT_PARSE_C) mbedtls_pk_init(&_pkctx); @@ -70,7 +75,11 @@ TLSSocketWrapper::~TLSSocketWrapper() close(); } mbedtls_entropy_free(&_entropy); - mbedtls_ctr_drbg_free(&_ctr_drbg); +#if defined(MBEDTLS_CTR_DRBG_C) + mbedtls_ctr_drbg_free(&_drbg); +#elif defined(MBEDTLS_HMAC_DRBG_C) + mbedtls_hmac_drbg_free(&_drbg); +#endif mbedtls_ssl_free(&_ssl); #if defined(MBEDTLS_X509_CRT_PARSE_C) mbedtls_pk_free(&_pkctx); @@ -183,15 +192,29 @@ nsapi_error_t TLSSocketWrapper::start_handshake(bool first_call) /* * Initialize TLS-related stuf. */ - if ((ret = mbedtls_ctr_drbg_seed(&_ctr_drbg, mbedtls_entropy_func, &_entropy, +#if defined(MBEDTLS_CTR_DRBG_C) + if ((ret = mbedtls_ctr_drbg_seed(&_drbg, mbedtls_entropy_func, &_entropy, (const unsigned char *) DRBG_PERS, sizeof(DRBG_PERS))) != 0) { print_mbedtls_error("mbedtls_crt_drbg_init", ret); return NSAPI_ERROR_AUTH_FAILURE; } +#elif defined(MBEDTLS_HMAC_DRBG_C) + if ((ret = mbedtls_hmac_drbg_seed(&_drbg, mbedtls_md_info_from_type(MBEDTLS_MD_SHA256), + mbedtls_entropy_func, &_entropy, + (const unsigned char *) DRBG_PERS, + sizeof(DRBG_PERS))) != 0) { + print_mbedtls_error("mbedtls_hmac_drbg_seed", ret); + return NSAPI_ERROR_AUTH_FAILURE; + } +#endif #if !defined(MBEDTLS_SSL_CONF_RNG) - mbedtls_ssl_conf_rng(get_ssl_config(), mbedtls_ctr_drbg_random, &_ctr_drbg); +#if defined(MBEDTLS_CTR_DRBG_C) + mbedtls_ssl_conf_rng(get_ssl_config(), mbedtls_ctr_drbg_random, &_drbg); +#elif defined(MBEDTLS_HMAC_DRBG_C) + mbedtls_ssl_conf_rng(get_ssl_config(), mbedtls_hmac_drbg_random, &_drbg); +#endif #endif @@ -274,7 +297,7 @@ nsapi_error_t TLSSocketWrapper::continue_handshake() tr_info("TLS connection established"); #endif -#if defined(MBEDTLS_X509_CRT_PARSE_C) && defined(FEA_TRACE_SUPPORT) +#if defined(MBEDTLS_X509_CRT_PARSE_C) && defined(FEA_TRACE_SUPPORT) && !defined(MBEDTLS_X509_REMOVE_INFO) /* Prints the server certificate and verify it. */ const size_t buf_size = 1024; char *buf = new char[buf_size]; diff --git a/features/netsocket/TLSSocketWrapper.h b/features/netsocket/TLSSocketWrapper.h index 9b21b7c692..aff4be53e1 100644 --- a/features/netsocket/TLSSocketWrapper.h +++ b/features/netsocket/TLSSocketWrapper.h @@ -29,6 +29,7 @@ #include "mbedtls/ssl.h" #include "mbedtls/entropy.h" #include "mbedtls/ctr_drbg.h" +#include "mbedtls/hmac_drbg.h" #include "mbedtls/error.h" // This class requires Mbed TLS SSL/TLS client code @@ -241,7 +242,7 @@ protected: * @retval NSAPI_ERROR_IN_PROGRESS if the first call did not complete the request. * @retval NSAPI_ERROR_NO_SOCKET in case the transport socket was not created correctly. * @retval NSAPI_ERROR_AUTH_FAILURE in case of tls-related authentication errors. - * See @ref mbedtls_ctr_drbg_seed, @ref mbedtls_ssl_setup. @ref mbedtls_ssl_handshake. + * See @ref mbedtls_ctr_drbg_seed or @ref mbedtls_hmac_drbg_seed, @ref mbedtls_ssl_setup. @ref mbedtls_ssl_handshake. */ nsapi_error_t start_handshake(bool first_call); @@ -290,7 +291,13 @@ private: #ifdef MBEDTLS_X509_CRT_PARSE_C mbedtls_pk_context _pkctx; #endif - mbedtls_ctr_drbg_context _ctr_drbg; + +#if defined(MBEDTLS_CTR_DRBG_C) + mbedtls_ctr_drbg_context _drbg; +#elif defined(MBEDTLS_HMAC_DRBG_C) + mbedtls_hmac_drbg_context _drbg; +#endif + mbedtls_entropy_context _entropy; rtos::EventFlags _event_flag; From af12d0642bbb7ef91ab8964c6a90250e200de84b Mon Sep 17 00:00:00 2001 From: Antti Kauppila Date: Mon, 24 Feb 2020 14:01:42 +0200 Subject: [PATCH 19/49] trace group defiined for shared_rng Unittests fixed 2 mbedtls functions were updated to reflect the api --- features/mbedtls/platform/src/shared_rng.cpp | 2 ++ .../test/coap-service/unittest/stub/mbedtls_stub.c | 12 ++++++------ 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/features/mbedtls/platform/src/shared_rng.cpp b/features/mbedtls/platform/src/shared_rng.cpp index 970e3de71f..e64844cf36 100644 --- a/features/mbedtls/platform/src/shared_rng.cpp +++ b/features/mbedtls/platform/src/shared_rng.cpp @@ -24,6 +24,8 @@ #include "mbed_trace.h" +#define TRACE_GROUP "SRNG" + mbedtls_hmac_drbg_context global_hmac_drbg; mbedtls_entropy_context global_entropy; static bool is_initialized = false; diff --git a/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c b/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c index 615bae7530..de419181a7 100644 --- a/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c +++ b/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c @@ -260,11 +260,11 @@ void mbedtls_hmac_drbg_free( mbedtls_hmac_drbg_context *ctx ) } int mbedtls_hmac_drbg_seed( mbedtls_hmac_drbg_context *ctx, - mbedtls_md_handle_t md_info, - int (*f_entropy)(void *, unsigned char *, size_t), - void *p_entropy, - const unsigned char *custom, - size_t len ) + const mbedtls_md_info_t * md_info, + int (*f_entropy)(void *, unsigned char *, size_t), + void *p_entropy, + const unsigned char *custom, + size_t len ) { return mbedtls_stub.crt_expected_int; } @@ -275,7 +275,7 @@ int mbedtls_hmac_drbg_random( void *p_rng, unsigned char *output, size_t out_len } // from md.h -mbedtls_md_handle_t mbedtls_md_info_from_type( mbedtls_md_type_t md_type ) +const mbedtls_md_info_t *mbedtls_md_info_from_type( mbedtls_md_type_t md_type ) { return 0; } From 3dbe97b8cb5e5900ffd1cf142a1e72881cc5cb20 Mon Sep 17 00:00:00 2001 From: Antti Kauppila Date: Mon, 30 Mar 2020 18:29:23 +0300 Subject: [PATCH 20/49] MBEDTLS_SSL_EXPORT_KEYS added to Nanostack's tls_sec_prot_lib --- .../source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c index 9c9ff8b72b..da52a27cef 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c @@ -24,7 +24,7 @@ #include MBEDTLS_CONFIG_FILE #endif -#if defined(MBEDTLS_SSL_TLS_C) && defined(MBEDTLS_X509_CRT_PARSE_C) +#if defined(MBEDTLS_SSL_TLS_C) && defined(MBEDTLS_X509_CRT_PARSE_C) && defined(MBEDTLS_SSL_EXPORT_KEYS) /* EXPORT_KEYS not supported by mbedtls baremetal yet */ #define WS_MBEDTLS_SECURITY_ENABLED #endif From a0e35d26946cea3af3c4031c510b648ff267eedf Mon Sep 17 00:00:00 2001 From: Maciej Bocianski Date: Thu, 12 Mar 2020 10:43:49 +0100 Subject: [PATCH 21/49] update USBMSD::infoTransfer implementation Fix protects underlaying block device from out-of-bound read/writes - prevents the host from setting block device addres larger then block device size - prevents the host from setting wrong read/write lenght (cherry picked from commit ac105f5a18d6f82dcbc0efbb239602d3b207de0b) --- drivers/source/usb/USBMSD.cpp | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/source/usb/USBMSD.cpp b/drivers/source/usb/USBMSD.cpp index ef8819868f..fb8f43f212 100644 --- a/drivers/source/usb/USBMSD.cpp +++ b/drivers/source/usb/USBMSD.cpp @@ -896,30 +896,37 @@ void USBMSD::memoryRead(void) bool USBMSD::infoTransfer(void) { - uint32_t n; + uint32_t addr_block; // Logical Block Address of First Block - n = (_cbw.CB[2] << 24) | (_cbw.CB[3] << 16) | (_cbw.CB[4] << 8) | (_cbw.CB[5] << 0); + addr_block = (_cbw.CB[2] << 24) | (_cbw.CB[3] << 16) | (_cbw.CB[4] << 8) | (_cbw.CB[5] << 0); - _addr = n * _block_size; + _addr = addr_block * _block_size; + if ((addr_block >= _block_count) || (_addr >= _memory_size)) { + _csw.Status = CSW_FAILED; + sendCSW(); + return false; + } + + uint32_t length_blocks = 0; // Number of Blocks to transfer switch (_cbw.CB[0]) { case READ10: case WRITE10: case VERIFY10: - n = (_cbw.CB[7] << 8) | (_cbw.CB[8] << 0); + length_blocks = (_cbw.CB[7] << 8) | (_cbw.CB[8] << 0); break; case READ12: case WRITE12: - n = (_cbw.CB[6] << 24) | (_cbw.CB[7] << 16) | (_cbw.CB[8] << 8) | (_cbw.CB[9] << 0); + length_blocks = (_cbw.CB[6] << 24) | (_cbw.CB[7] << 16) | (_cbw.CB[8] << 8) | (_cbw.CB[9] << 0); break; } - _length = n * _block_size; + _length = length_blocks * _block_size; - if (!_cbw.DataLength) { // host requests no data + if (!_cbw.DataLength || !length_blocks || (length_blocks > _block_count - addr_block) || (_length > _memory_size - _addr)) { // host requests no data or wrong length _csw.Status = CSW_FAILED; sendCSW(); return false; From a277db1309d034230a594a56ad1b26fbe65a1ee3 Mon Sep 17 00:00:00 2001 From: Maciej Bocianski Date: Thu, 12 Mar 2020 10:48:08 +0100 Subject: [PATCH 22/49] update USBMSD::memoryRead implementation Fix protects underlaying block device from out-of-bound reads (cherry picked from commit 89e67d31360c86105db35cf7aeb7421ba88820ac) --- drivers/source/usb/USBMSD.cpp | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/source/usb/USBMSD.cpp b/drivers/source/usb/USBMSD.cpp index fb8f43f212..32f0b08914 100644 --- a/drivers/source/usb/USBMSD.cpp +++ b/drivers/source/usb/USBMSD.cpp @@ -869,24 +869,26 @@ void USBMSD::memoryRead(void) n = (_length > MAX_PACKET) ? MAX_PACKET : _length; - if ((_addr + n) > _memory_size) { - n = _memory_size - _addr; + if (_addr > (_memory_size - n)) { + n = _addr < _memory_size ? _memory_size - _addr : 0; _stage = ERROR; } - // we read an entire block - if (!(_addr % _block_size)) { - disk_read(_page, _addr / _block_size, 1); + if (n > 0) { + // we read an entire block + if (!(_addr % _block_size)) { + disk_read(_page, _addr / _block_size, 1); + } + + // write data which are in RAM + _write_next(&_page[_addr % _block_size], MAX_PACKET); + + _addr += n; + _length -= n; + + _csw.DataResidue -= n; } - // write data which are in RAM - _write_next(&_page[_addr % _block_size], MAX_PACKET); - - _addr += n; - _length -= n; - - _csw.DataResidue -= n; - if (!_length || (_stage != PROCESS_CBW)) { _csw.Status = (_stage == PROCESS_CBW) ? CSW_PASSED : CSW_FAILED; _stage = (_stage == PROCESS_CBW) ? SEND_CSW : _stage; From 95bb2a8e053346d3d01a1635812ab5028fb1b34e Mon Sep 17 00:00:00 2001 From: Maciej Bocianski Date: Sun, 15 Mar 2020 13:25:41 +0100 Subject: [PATCH 23/49] update USBMSD::memoryWrite implementation Fix prevents unaligned USB transfers (cherry picked from commit 1ffb4d7356ce7744194f264f2f71b17d1105feaa) --- drivers/source/usb/USBMSD.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/source/usb/USBMSD.cpp b/drivers/source/usb/USBMSD.cpp index 32f0b08914..06be15198f 100644 --- a/drivers/source/usb/USBMSD.cpp +++ b/drivers/source/usb/USBMSD.cpp @@ -565,6 +565,14 @@ void USBMSD::_read_next() void USBMSD::memoryWrite(uint8_t *buf, uint16_t size) { + // Max sized packets are required to be sent until the transfer is complete + MBED_ASSERT(_block_size % MAX_PACKET == 0); + if ((size != MAX_PACKET) && (size != 0)) { + _stage = ERROR; + endpoint_stall(_bulk_out); + return; + } + if ((_addr + size) > _memory_size) { size = _memory_size - _addr; _stage = ERROR; From 5bdc7314f471b93fc50c7eaf6fe80687215db8f1 Mon Sep 17 00:00:00 2001 From: Antti Kauppila Date: Tue, 31 Mar 2020 15:59:56 +0300 Subject: [PATCH 24/49] more error handling added for ctr and hmac --- .../src/apps/altcp_tls/altcp_tls_mbedtls.c | 15 +++++++--- .../source/coap_security_handler.c | 28 +++++++++---------- features/netsocket/TLSSocketWrapper.cpp | 22 +++++---------- features/netsocket/TLSSocketWrapper.h | 20 +++++++++---- 4 files changed, 46 insertions(+), 39 deletions(-) diff --git a/features/lwipstack/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c b/features/lwipstack/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c index 90cd5e0745..d101604cda 100644 --- a/features/lwipstack/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c +++ b/features/lwipstack/lwip/src/apps/altcp_tls/altcp_tls_mbedtls.c @@ -102,17 +102,15 @@ struct altcp_tls_config { #if defined(MBEDTLS_CTR_DRBG_C) mbedtls_ctr_drbg_context _drbg; #define DRBG_INIT mbedtls_ctr_drbg_init -#define DRBG_SEED mbedtls_ctr_drbg_seed #define DRBG_SEED_ERROR "mbedtls_ctr_drbg_seed failed: %d\n" #define DRBG_RANDOM mbedtls_ctr_drbg_random #elif defined(MBEDTLS_HMAC_DRBG_C) mbedtls_hmac_drbg_context _drbg; #define DRBG_INIT mbedtls_hmac_drbg_init -#define DRBG_SEED mbedtls_hmac_drbg_seed #define DRBG_SEED_ERROR "mbedtls_hmac_drbg_seed failed: %d\n" #define DRBG_RANDOM mbedtls_hmac_drbg_random #else -#error "CTR or HMAC must be defined for coap_security_handler!" +#error "CTR or HMAC must be defined for altcp_tls_mbedtls!" #endif mbedtls_x509_crt *cert; mbedtls_pk_context *pkey; @@ -740,7 +738,16 @@ altcp_tls_create_config(int is_server, int have_cert, int have_pkey, int have_ca DRBG_INIT(&conf->_drbg); /* Seed the RNG */ - ret = DRBG_SEED(&conf->_drbg, ALTCP_MBEDTLS_RNG_FN, &conf->entropy, ALTCP_MBEDTLS_ENTROPY_PTR, ALTCP_MBEDTLS_ENTROPY_LEN); +#if defined(MBEDTLS_CTR_DRBG_C) + ret = mbedtls_ctr_drbg_seed(&conf->_drbg, ALTCP_MBEDTLS_RNG_FN, + &conf->entropy, ALTCP_MBEDTLS_ENTROPY_PTR, ALTCP_MBEDTLS_ENTROPY_LEN); +#elif defined(MBEDTLS_HMAC_DRBG_C) + ret = mbedtls_hmac_drbg_seed(&conf->_drbg, mbedtls_md_info_from_type(MBEDTLS_MD_SHA256), + ALTCP_MBEDTLS_RNG_FN, &conf->entropy, + ALTCP_MBEDTLS_ENTROPY_PTR, ALTCP_MBEDTLS_ENTROPY_LEN); +#else +#error "CTR or HMAC must be defined for altcp_tls_mbedtls!" +#endif if (ret != 0) { LWIP_DEBUGF(ALTCP_MBEDTLS_DEBUG, (DRBG_SEED_ERROR, ret)); diff --git a/features/nanostack/coap-service/source/coap_security_handler.c b/features/nanostack/coap-service/source/coap_security_handler.c index 99be31e24e..b2ec1b69d5 100644 --- a/features/nanostack/coap-service/source/coap_security_handler.c +++ b/features/nanostack/coap-service/source/coap_security_handler.c @@ -44,8 +44,14 @@ struct coap_security_s { #if defined(MBEDTLS_CTR_DRBG_C) mbedtls_ctr_drbg_context _drbg; +#define DRBG_INIT mbedtls_ctr_drbg_init +#define DRBG_RANDOM mbedtls_ctr_drbg_random +#define DRBG_FREE mbedtls_ctr_drbg_free #elif defined(MBEDTLS_HMAC_DRBG_C) mbedtls_hmac_drbg_context _drbg; +#define DRBG_INIT mbedtls_hmac_drbg_init +#define DRBG_RANDOM mbedtls_hmac_drbg_random +#define DRBG_FREE mbedtls_hmac_drbg_free #else #error "CTR or HMAC must be defined for coap_security_handler!" #endif @@ -122,11 +128,7 @@ static int coap_security_handler_init(coap_security_t *sec) mbedtls_ssl_init(&sec->_ssl); mbedtls_ssl_config_init(&sec->_conf); -#if defined(MBEDTLS_CTR_DRBG_C) - mbedtls_ctr_drbg_init(&sec->_drbg); -#elif defined(MBEDTLS_HMAC_DRBG_C) - mbedtls_hmac_drbg_init(&sec->_drbg); -#endif + DRBG_INIT(&sec->_drbg); mbedtls_entropy_init(&sec->_entropy); #if defined(MBEDTLS_X509_CRT_PARSE_C) @@ -157,6 +159,8 @@ static int coap_security_handler_init(coap_security_t *sec) strlen(pers))) != 0) { return -1; } +#else +#error "CTR or HMAC must be defined for coap_security_handler!" #endif return 0; } @@ -180,11 +184,9 @@ static void coap_security_handler_reset(coap_security_t *sec) #endif mbedtls_entropy_free(&sec->_entropy); -#if defined(MBEDTLS_CTR_DRBG_C) - mbedtls_ctr_drbg_free(&sec->_drbg); -#elif defined(MBEDTLS_HMAC_DRBG_C) - mbedtls_hmac_drbg_free(&sec->_drbg); -#endif + + DRBG_FREE(&sec->_drbg); + mbedtls_ssl_config_free(&sec->_conf); mbedtls_ssl_free(&sec->_ssl); #if defined(MBEDTLS_PLATFORM_C) @@ -421,11 +423,7 @@ int coap_security_handler_connect_non_blocking(coap_security_t *sec, bool is_ser } #if !defined(MBEDTLS_SSL_CONF_RNG) -#if defined(MBEDTLS_CTR_DRBG_C) - mbedtls_ssl_conf_rng(&sec->_conf, mbedtls_ctr_drbg_random, &sec->_drbg); -#elif defined(MBEDTLS_HMAC_DRBG_C) - mbedtls_ssl_conf_rng(&sec->_conf, mbedtls_hmac_drbg_random, &sec->_drbg); -#endif + mbedtls_ssl_conf_rng(&sec->_conf, DRBG_RANDOM, &sec->_drbg); #endif if ((mbedtls_ssl_setup(&sec->_ssl, &sec->_conf)) != 0) { diff --git a/features/netsocket/TLSSocketWrapper.cpp b/features/netsocket/TLSSocketWrapper.cpp index d01959f09f..2659518a10 100644 --- a/features/netsocket/TLSSocketWrapper.cpp +++ b/features/netsocket/TLSSocketWrapper.cpp @@ -53,11 +53,7 @@ TLSSocketWrapper::TLSSocketWrapper(Socket *transport, const char *hostname, cont } #endif /* MBEDTLS_PLATFORM_C */ mbedtls_entropy_init(&_entropy); -#if defined(MBEDTLS_CTR_DRBG_C) - mbedtls_ctr_drbg_init(&_drbg); -#elif defined(MBEDTLS_HMAC_DRBG_C) - mbedtls_hmac_drbg_init(&_drbg); -#endif + DRBG_INIT(&_drbg); mbedtls_ssl_init(&_ssl); #if defined(MBEDTLS_X509_CRT_PARSE_C) @@ -75,11 +71,9 @@ TLSSocketWrapper::~TLSSocketWrapper() close(); } mbedtls_entropy_free(&_entropy); -#if defined(MBEDTLS_CTR_DRBG_C) - mbedtls_ctr_drbg_free(&_drbg); -#elif defined(MBEDTLS_HMAC_DRBG_C) - mbedtls_hmac_drbg_free(&_drbg); -#endif + + DRBG_FREE(&_drbg); + mbedtls_ssl_free(&_ssl); #if defined(MBEDTLS_X509_CRT_PARSE_C) mbedtls_pk_free(&_pkctx); @@ -207,14 +201,12 @@ nsapi_error_t TLSSocketWrapper::start_handshake(bool first_call) print_mbedtls_error("mbedtls_hmac_drbg_seed", ret); return NSAPI_ERROR_AUTH_FAILURE; } +#else +#error "CTR or HMAC must be defined for TLSSocketWrapper!" #endif #if !defined(MBEDTLS_SSL_CONF_RNG) -#if defined(MBEDTLS_CTR_DRBG_C) - mbedtls_ssl_conf_rng(get_ssl_config(), mbedtls_ctr_drbg_random, &_drbg); -#elif defined(MBEDTLS_HMAC_DRBG_C) - mbedtls_ssl_conf_rng(get_ssl_config(), mbedtls_hmac_drbg_random, &_drbg); -#endif + mbedtls_ssl_conf_rng(get_ssl_config(), DRBG_RANDOM, &_drbg); #endif diff --git a/features/netsocket/TLSSocketWrapper.h b/features/netsocket/TLSSocketWrapper.h index aff4be53e1..f4cbfe0c4e 100644 --- a/features/netsocket/TLSSocketWrapper.h +++ b/features/netsocket/TLSSocketWrapper.h @@ -35,6 +35,20 @@ // This class requires Mbed TLS SSL/TLS client code #if defined(MBEDTLS_SSL_CLI_C) || defined(DOXYGEN_ONLY) +#if defined(MBEDTLS_CTR_DRBG_C) +#define DRBG_CTX mbedtls_ctr_drbg_context +#define DRBG_INIT mbedtls_ctr_drbg_init +#define DRBG_RANDOM mbedtls_ctr_drbg_random +#define DRBG_FREE mbedtls_ctr_drbg_free +#elif defined(MBEDTLS_HMAC_DRBG_C) +#define DRBG_CTX mbedtls_hmac_drbg_context +#define DRBG_INIT mbedtls_hmac_drbg_init +#define DRBG_RANDOM mbedtls_hmac_drbg_random +#define DRBG_FREE mbedtls_hmac_drbg_free +#else +#error "CTR or HMAC must be defined for TLSSocketWrapper!" +#endif + /** * TLSSocket is a wrapper around Socket for interacting with TLS servers. * @@ -292,11 +306,7 @@ private: mbedtls_pk_context _pkctx; #endif -#if defined(MBEDTLS_CTR_DRBG_C) - mbedtls_ctr_drbg_context _drbg; -#elif defined(MBEDTLS_HMAC_DRBG_C) - mbedtls_hmac_drbg_context _drbg; -#endif + DRBG_CTX _drbg; mbedtls_entropy_context _entropy; From 9c328114c54ed33f7b517cdf79060ea35b51fee6 Mon Sep 17 00:00:00 2001 From: Antti Kauppila Date: Tue, 31 Mar 2020 16:15:44 +0300 Subject: [PATCH 25/49] Licence updated --- features/mbedtls/platform/inc/shared_rng.h | 2 +- features/mbedtls/platform/src/shared_rng.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/features/mbedtls/platform/inc/shared_rng.h b/features/mbedtls/platform/inc/shared_rng.h index 154bdfa184..76fc60739d 100644 --- a/features/mbedtls/platform/inc/shared_rng.h +++ b/features/mbedtls/platform/inc/shared_rng.h @@ -1,7 +1,7 @@ /* * shared_rng.h * - * Copyright (C) 2019, Arm Limited, All Rights Reserved + * Copyright (C) 2019-2020, Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may diff --git a/features/mbedtls/platform/src/shared_rng.cpp b/features/mbedtls/platform/src/shared_rng.cpp index e64844cf36..65600f5dea 100644 --- a/features/mbedtls/platform/src/shared_rng.cpp +++ b/features/mbedtls/platform/src/shared_rng.cpp @@ -1,7 +1,7 @@ /* * shared_rng.cpp * - * Copyright (C) 2019, Arm Limited, All Rights Reserved + * Copyright (C) 2019-2020, Arm Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may From 103faf900736cced90b786531a87bad59f174722 Mon Sep 17 00:00:00 2001 From: RyoheiHagimoto Date: Tue, 31 Mar 2020 14:28:59 +0900 Subject: [PATCH 26/49] RZ_A1H and GR_LYCHEE: Enable bootloader support (Mbed OS 5.15) --- targets/targets.json | 10 ++++++++-- tools/arm_pack_manager/index.json | 20 ++++++++++---------- 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index 32617dbc4e..b954823690 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -5899,7 +5899,10 @@ "device_has_add": ["USBDEVICE", "EMAC", "FLASH", "LPTICKER"], "release_versions": ["2", "5"], "device_name": "R7S72100", - "bootloader_supported": false + "bootloader_supported": true, + "mbed_rom_start" : "0x18000000", + "mbed_rom_size" : "0x800000", + "sectors": [[402653184,4096]] }, "VK_RZ_A1H": { "inherits": ["RZ_A1XX"], @@ -5916,7 +5919,10 @@ "device_has_remove": ["ETHERNET"], "release_versions": ["2", "5"], "device_name": "R7S72103", - "bootloader_supported": false, + "bootloader_supported": true, + "mbed_rom_start" : "0x18000000", + "mbed_rom_size" : "0x800000", + "sectors": [[402653184,4096]], "overrides": { "network-default-interface-type": null } diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index b23c6bdc06..ca99ad89bc 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -302969,7 +302969,7 @@ "version": "1.2.1" }, "memories": { - "PROGRAM_FLASH": { + "IRAM1": { "access": { "execute": true, "non_secure": false, @@ -302977,12 +302977,12 @@ "peripheral": false, "read": true, "secure": false, - "write": false + "write": true }, "default": true, - "size": 8388608, - "start": 402653184, - "startup": true + "size": 10485760, + "start": 536870912, + "startup": false } }, "name": "R7S72100", @@ -303013,7 +303013,7 @@ "version": "1.2.1" }, "memories": { - "PROGRAM_FLASH": { + "IRAM1": { "access": { "execute": true, "non_secure": false, @@ -303021,12 +303021,12 @@ "peripheral": false, "read": true, "secure": false, - "write": false + "write": true }, "default": true, - "size": 8388608, - "start": 402653184, - "startup": true + "size": 3145728, + "start": 536870912, + "startup": false } }, "name": "R7S72103", From d65b82da9deb883b45537487e8cdb2b78654c43c Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Thu, 19 Mar 2020 09:06:45 +0200 Subject: [PATCH 27/49] Cellular: ALT1250 PPP cellular driver for mbed-os 5.15 This commit introduces Altair ALT1250 PPP mode cellular driver for mbed-os 5.15 -branch. --- .../Altair/ALT1250/PPP/ALT1250_PPP.cpp | 121 ++++++++++++++++++ .../targets/Altair/ALT1250/PPP/ALT1250_PPP.h | 48 +++++++ .../PPP/ALT1250_PPP_CellularContext.cpp | 44 +++++++ .../ALT1250/PPP/ALT1250_PPP_CellularContext.h | 35 +++++ .../PPP/ALT1250_PPP_CellularNetwork.cpp | 68 ++++++++++ .../ALT1250/PPP/ALT1250_PPP_CellularNetwork.h | 36 ++++++ .../targets/Altair/ALT1250/PPP/mbed_lib.json | 33 +++++ 7 files changed, 385 insertions(+) create mode 100755 features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP.cpp create mode 100644 features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP.h create mode 100644 features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularContext.cpp create mode 100644 features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularContext.h create mode 100755 features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularNetwork.cpp create mode 100755 features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularNetwork.h create mode 100644 features/cellular/framework/targets/Altair/ALT1250/PPP/mbed_lib.json diff --git a/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP.cpp b/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP.cpp new file mode 100755 index 0000000000..b38dee16d7 --- /dev/null +++ b/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP.cpp @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2020, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ALT1250_PPP.h" +#include "ALT1250_PPP_CellularContext.h" +#include "AT_CellularNetwork.h" +#include "ALT1250_PPP_CellularNetwork.h" +#include "CellularLog.h" +#include "rtos/ThisThread.h" + +using namespace rtos; +using namespace mbed; +using namespace events; + +#define CONNECT_DELIM "\r\n" +#define CONNECT_BUFFER_SIZE (1280 + 80 + 80) // AT response + sscanf format +#define CONNECT_TIMEOUT 8000 + +#if !defined(MBED_CONF_ALT1250_PPP_RST) +#define MBED_CONF_ALT1250_PPP_RST NC +#endif + +static const intptr_t cellular_properties[AT_CellularBase::PROPERTY_MAX] = { + AT_CellularNetwork::RegistrationModeEnable,// C_EREG + AT_CellularNetwork::RegistrationModeDisable, // C_GREG + AT_CellularNetwork::RegistrationModeLAC, // C_REG + 1, // AT_CGSN_WITH_TYPE + 0, // AT_CGDATA + 0, // AT_CGAUTH + 1, // AT_CNMI + 1, // AT_CSMP + 1, // AT_CMGF + 1, // AT_CSDH + 1, // PROPERTY_IPV4_STACK + 0, // PROPERTY_IPV6_STACK + 0, // PROPERTY_IPV4V6_STACK + 0, // PROPERTY_NON_IP_PDP_TYPE + 1, // PROPERTY_AT_CGEREP +}; + +ALT1250_PPP::ALT1250_PPP(FileHandle *fh, PinName rst, PinDirection pin_dir, PinMode pin_mode, bool value) + : AT_CellularDevice(fh), + _rst(rst, pin_dir, pin_mode, value) +{ + AT_CellularBase::set_cellular_properties(cellular_properties); +} + +AT_CellularContext *ALT1250_PPP::create_context_impl(ATHandler &at, const char *apn, bool cp_req, bool nonip_req) +{ + return new ALT1250_PPP_CellularContext(at, this, apn, cp_req, nonip_req); +} + +AT_CellularNetwork *ALT1250_PPP::open_network_impl(ATHandler &at) +{ + return new ALT1250_PPP_CellularNetwork(at); +} + +nsapi_error_t ALT1250_PPP::soft_power_on() +{ + // check if modem is already ready + _at->lock(); + _at->flush(); + _at->set_at_timeout(30); + _at->cmd_start("AT"); + _at->cmd_stop_read_resp(); + nsapi_error_t err = _at->get_last_error(); + _at->restore_at_timeout(); + _at->unlock(); + + // modem is not responding to AT commands, power it on + if (err != NSAPI_ERROR_OK) { + tr_warn("Modem is not responding to AT commands, reset it"); + if (_rst.is_connected()) { + _rst = 0; + ThisThread::sleep_for(100); + _rst = 1; + } + if (_at->sync(2000)) { + tr_warn("Modem is AT ready"); + return NSAPI_ERROR_OK; + } + tr_warn("Modem is not AT ready following reset"); + return _at->get_last_error(); + } + + return NSAPI_ERROR_OK; +} + +#if MBED_CONF_ALT1250_PPP_PROVIDE_DEFAULT + +#if !NSAPI_PPP_AVAILABLE +#error Must define lwip.ppp-enabled +#endif + +#include "UARTSerial.h" +CellularDevice *CellularDevice::get_default_instance() +{ + static UARTSerial serial(MBED_CONF_ALT1250_PPP_TX, MBED_CONF_ALT1250_PPP_RX, MBED_CONF_ALT1250_PPP_BAUDRATE); +#if defined (MBED_CONF_ALT1250_PPP_RTS) && defined (MBED_CONF_ALT1250_PPP_CTS) + tr_debug("ALT1250_PPP flow control: RTS %d CTS %d", MBED_CONF_ALT1250_PPP_RTS, MBED_CONF_ALT1250_PPP_CTS); + serial.set_flow_control(SerialBase::RTSCTS, MBED_CONF_ALT1250_PPP_RTS, MBED_CONF_ALT1250_PPP_CTS); +#endif + static ALT1250_PPP device(&serial, MBED_CONF_ALT1250_PPP_RST, PIN_OUTPUT, OpenDrainNoPull, 1); + return &device; +} +#endif + diff --git a/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP.h b/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP.h new file mode 100644 index 0000000000..d3049b611b --- /dev/null +++ b/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2020, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ALT1250_PPP_H_ +#define ALT1250_PPP_H_ + +#ifdef TARGET_FF_ARDUINO +#ifndef MBED_CONF_ALT1250_PPP_TX +#define MBED_CONF_ALT1250_PPP_TX D1 +#endif +#ifndef MBED_CONF_ALT1250_PPP_RX +#define MBED_CONF_ALT1250_PPP_RX D0 +#endif +#endif /* TARGET_FF_ARDUINO */ + +#include "AT_CellularDevice.h" +#include "DigitalInOut.h" + +namespace mbed { + +class ALT1250_PPP : public AT_CellularDevice { +public: + ALT1250_PPP(FileHandle *fh, PinName rst = NC, PinDirection pin_dir = PIN_OUTPUT, PinMode pin_mode = PullUp, bool value = 1); + +protected: // AT_CellularDevice + virtual AT_CellularContext *create_context_impl(ATHandler &at, const char *apn, bool cp_req = false, bool nonip_req = false); + + AT_CellularNetwork *open_network_impl(ATHandler &at); + virtual nsapi_error_t soft_power_on(); + DigitalInOut _rst; +}; + +} // namespace mbed +#endif // ALT1250_PPP_H_ diff --git a/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularContext.cpp b/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularContext.cpp new file mode 100644 index 0000000000..49d7fccf5a --- /dev/null +++ b/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularContext.cpp @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "ALT1250_PPP_CellularContext.h" + +namespace mbed { + +ALT1250_PPP_CellularContext::ALT1250_PPP_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req, bool nonip_req) : + AT_CellularContext(at, device, apn, cp_req, nonip_req) +{ +} + +ALT1250_PPP_CellularContext::~ALT1250_PPP_CellularContext() +{ +} + +nsapi_error_t ALT1250_PPP_CellularContext::do_user_authentication() +{ + nsapi_error_t err = NSAPI_ERROR_OK; + if (_pwd && _uname) { + err = _at.at_cmd_discard("%PPPAUTH", "=", "%d%d%s%s", _cid, _authentication_type, + _uname, _pwd); + if (err != NSAPI_ERROR_OK) { + return NSAPI_ERROR_AUTH_FAILURE; + } + } + + return err; +} + +} /* namespace mbed */ diff --git a/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularContext.h b/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularContext.h new file mode 100644 index 0000000000..111ca56780 --- /dev/null +++ b/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularContext.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2020, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef ALT1250_PPP_CELLULARCONTEXT_H_ +#define ALT1250_PPP_CELLULARCONTEXT_H_ + +#include "AT_CellularContext.h" + +namespace mbed { + +class ALT1250_PPP_CellularContext: public AT_CellularContext { +public: + ALT1250_PPP_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req = false, bool nonip_req = false); + virtual ~ALT1250_PPP_CellularContext(); + +protected: + virtual nsapi_error_t do_user_authentication(); +}; + +} /* namespace mbed */ + +#endif // ALT1250_PPP_CELLULARCONTEXT_H_ diff --git a/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularNetwork.cpp b/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularNetwork.cpp new file mode 100755 index 0000000000..4f39d52fd6 --- /dev/null +++ b/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularNetwork.cpp @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2020, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ALT1250_PPP_CellularNetwork.h" +#include "CellularLog.h" + +using namespace mbed; + +ALT1250_PPP_CellularNetwork::ALT1250_PPP_CellularNetwork(ATHandler &atHandler) : AT_CellularNetwork(atHandler) +{ +} + +ALT1250_PPP_CellularNetwork::~ALT1250_PPP_CellularNetwork() +{ +} + +nsapi_error_t ALT1250_PPP_CellularNetwork::set_access_technology_impl(RadioAccessTechnology opsAct) +{ + _at.lock(); + + _at.set_at_timeout(10000); + char resp[20]; + _at.at_cmd_str("%RATACT", "?", resp, 20); + tr_debug("ALT1250_PPP RAT: %s", resp); + + switch (opsAct) { + case RAT_CATM1: + if (memcmp(resp, "CATM", 4)) { + _at.at_cmd_discard("%RATACT", "=\"CATM\""); + } + break; + case RAT_NB1: + if (memcmp(resp, "NBIOT", 5)) { + _at.at_cmd_discard("%RATACT", "=\"NBIOT\""); + } + break; + case RAT_GSM: + case RAT_GSM_COMPACT: + case RAT_UTRAN: + case RAT_EGPRS: + break; + default: + if (memcmp(resp, "DEFAULT", 7)) { + _at.at_cmd_discard("%RATACT", "=\"DEFAULT\""); + } + _at.unlock(); + _op_act = RAT_UNKNOWN; + return NSAPI_ERROR_UNSUPPORTED; + } + + _at.restore_at_timeout(); + + return _at.unlock_return_error(); +} diff --git a/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularNetwork.h b/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularNetwork.h new file mode 100755 index 0000000000..d8c485ca00 --- /dev/null +++ b/features/cellular/framework/targets/Altair/ALT1250/PPP/ALT1250_PPP_CellularNetwork.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2020, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ALT1250_PPP_CELLULAR_NETWORK_H_ +#define ALT1250_PPP_CELLULAR_NETWORK_H_ + +#include "AT_CellularNetwork.h" + +namespace mbed { + +class ALT1250_PPP_CellularNetwork : public AT_CellularNetwork { +public: + ALT1250_PPP_CellularNetwork(ATHandler &atHandler); + virtual ~ALT1250_PPP_CellularNetwork(); + +protected: + virtual nsapi_error_t set_access_technology_impl(RadioAccessTechnology opRat); +}; + +} // namespace mbed + +#endif // ALT1250_PPP_CELLULAR_NETWORK_H_ diff --git a/features/cellular/framework/targets/Altair/ALT1250/PPP/mbed_lib.json b/features/cellular/framework/targets/Altair/ALT1250/PPP/mbed_lib.json new file mode 100644 index 0000000000..b5c2100674 --- /dev/null +++ b/features/cellular/framework/targets/Altair/ALT1250/PPP/mbed_lib.json @@ -0,0 +1,33 @@ +{ + "name": "ALT1250_PPP", + "config": { + "tx": { + "help": "TX pin for serial connection. D1 assumed if Arduino Form Factor, needs to be set/overwritten otherwise.", + "value": null + }, + "rx": { + "help": "RX pin for serial connection. D0 assumed if Arduino Form Factor, needs to be set/overwritten otherwise.", + "value": null + }, + "rts": { + "help": "RTS pin for serial connection", + "value": null + }, + "cts": { + "help": "CTS pin for serial connection", + "value": null + }, + "rst": { + "help": "Reset control pin", + "value": null + }, + "baudrate": { + "help": "Serial connection baud rate", + "value": 115200 + }, + "provide-default": { + "help": "Provide as default CellularDevice [true/false]", + "value": false + } + } +} From 880af5d8ae13ad25e435c67378c8dc8a89f42dff Mon Sep 17 00:00:00 2001 From: Shuopeng Deng Date: Wed, 27 Nov 2019 12:20:33 -0800 Subject: [PATCH 28/49] Backport #12019: rework cypress lptimer hal Changed set_match api to use an absolute ticks rather than delayed tick to match api name. Added api set_delay to delay by a specific amount of ticks. Removed unused set_time api. Simplified the logic for computing interrupts match value for cascading counters. Fixed an issue when incorrect base time would be read when trying to set match values. --- .../TARGET_PSOC6/cy_lp_ticker_api.c | 7 +- .../psoc6csp/hal/include/cyhal_lptimer.h | 39 ++-- .../psoc6csp/hal/src/cyhal_lptimer.c | 182 ++++++++---------- 3 files changed, 108 insertions(+), 120 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_lp_ticker_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_lp_ticker_api.c index ac20ec6d16..eba2049221 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_lp_ticker_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_lp_ticker_api.c @@ -62,11 +62,8 @@ uint32_t lp_ticker_read(void) void lp_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delay; - delay = (uint32_t)timestamp - cyhal_lptimer_read(&cy_lptimer0); - - if (CY_RSLT_SUCCESS != cyhal_lptimer_set_match(&cy_lptimer0, delay)) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_lptimer_set_time"); + if (CY_RSLT_SUCCESS != cyhal_lptimer_set_match(&cy_lptimer0, (uint32_t)timestamp)) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_lptimer_set_match"); } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h index 5f77945d29..ff621632ea 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h @@ -30,6 +30,10 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress LPTIMER. +* +* This can be used to measure timing between events, or to perform +* some action the ability after a set interval. It continues to operate +* in some low power modes; see the device datasheet for details. */ #pragma once @@ -43,6 +47,10 @@ extern "C" { #endif + +/** Failed to configure power management callback */ +#define CYHAL_LPTIMER_RSLT_ERR_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_WDT, 0)) + /** LPTIMER interrupt triggers */ typedef enum { CYHAL_LPTIMER_COMPARE_MATCH, @@ -81,18 +89,8 @@ void cyhal_lptimer_free(cyhal_lptimer_t *obj); */ cy_rslt_t cyhal_lptimer_reload(cyhal_lptimer_t *obj); -/** Set timeframe between interrupts - * - * Configures the LPTIMER in free-running mode. Generates an interrupt on match. - * This function is for initial configuration. For quick updates to the match - * value, use cyhal_lptimer_set_time(). - * - * @param[in] obj The LPTIMER object - * @param[in] time The time in ticks to be set - * - * @return The status of the set_time request - */ -cy_rslt_t cyhal_lptimer_set_time(cyhal_lptimer_t *obj, uint32_t time); +/** Deprecated. Call cyhal_lptimer_set_match instead. */ +#define cyhal_lptimer_set_time cyhal_lptimer_set_match /** Update the match/compare value * @@ -102,12 +100,27 @@ cy_rslt_t cyhal_lptimer_set_time(cyhal_lptimer_t *obj, uint32_t time); * sequence. * * @param[in] obj The LPTIMER object - * @param[in] value The match value in ticks + * @param[in] value The tick value to match * * @return The status of the set_match request */ cy_rslt_t cyhal_lptimer_set_match(cyhal_lptimer_t *obj, uint32_t value); +/** Update the match/compare value + * + * Update the match value of an already configured LPTIMER set up + * to generate an interrupt on match delay from the current counter value. + * Note that this function does not reinitialize the counter or the + * associated peripheral initialization + * sequence. + * + * @param[in] obj The LPTIMER object + * @param[in] delay The ticks to wait + * + * @return The status of the set_match request + */ +cy_rslt_t cyhal_lptimer_set_delay(cyhal_lptimer_t *obj, uint32_t delay); + /** Read the current tick * * If no rollover has occurred, the seconds passed since cyhal_lptimer_init() or cyhal_lptimer_set_time() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c index 8c3ceb70d2..2c57d0fc8c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c @@ -26,7 +26,7 @@ *******************************************************************************/ #include "cmsis_compiler.h" -#include "cy_wdt.h" +#include "cy_mcwdt.h" #include "cy_syslib.h" #include "cy_sysint.h" #include "cyhal_lptimer.h" @@ -52,16 +52,11 @@ static MCWDT_STRUCT_Type * const CYHAL_LPTIMER_BASE_ADDRESSES[] = { #endif }; -#if !defined (CY_CFG_SYSCLK_CLKLF_FREQ_HZ) -#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768UL /* Default to 32K ILO */ -#endif /* CY_CFG_SYSCLK_CLKLF_FREQ_HZ */ - -#define CY_MCWDT_COUNTER0_MAX_TICKS (0xffffUL) -#define CY_MCWDT_COUNTER1_MAX_TICKS (0xffffUL) -#define CY_MCWDT_COUNTER2_MAX_TICKS (0xffffffffUL) #define CY_MCWDT_MAX_DELAY_TICKS (0xfff0ffffUL) /* ~36hours, Not set to 0xffffffff to avoid C0 and C1 both overflowing */ #define CY_MCWDT_LPTIMER_CTRL (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2) +#define CY_MCWDT_MIN_DELAY 3 /* minimum amount of lfclk cycles of that LPTIMER can delay for. */ + #define CY_DEFAULT_MCWDT_PRIORITY 3 static const uint16_t CY_MCWDT_RESET_TIME_US = 62; @@ -95,8 +90,8 @@ cy_rslt_t cyhal_lptimer_init(cyhal_lptimer_t *obj) obj->base = CYHAL_LPTIMER_BASE_ADDRESSES[obj->resource.block_num]; const cy_stc_mcwdt_config_t cfg = { - .c0Match = CY_MCWDT_COUNTER0_MAX_TICKS, - .c1Match = CY_MCWDT_COUNTER1_MAX_TICKS, + .c0Match = 0xFFFF, + .c1Match = 0xFFFF, .c0Mode = CY_MCWDT_MODE_INT, .c1Mode = CY_MCWDT_MODE_INT, .c2Mode = CY_MCWDT_MODE_NONE, @@ -107,25 +102,28 @@ cy_rslt_t cyhal_lptimer_init(cyhal_lptimer_t *obj) .c1c2Cascade = false }; rslt = (cy_rslt_t) Cy_MCWDT_Init(obj->base, &cfg); + } + if (CY_RSLT_SUCCESS == rslt) + { + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + cyhal_lptimer_config_structs[obj->resource.block_num] = obj; + } + + if (CY_RSLT_SUCCESS == rslt) + { + IRQn_Type irqn = (IRQn_Type) (srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); + cy_stc_sysint_t irqCfg = { irqn, CY_DEFAULT_MCWDT_PRIORITY }; + rslt = (cy_rslt_t) Cy_SysInt_Init(&irqCfg, &cyhal_lptimer_irq_handler); if (CY_RSLT_SUCCESS == rslt) { - obj->callback_data.callback = NULL; - obj->callback_data.callback_arg = NULL; - cyhal_lptimer_config_structs[obj->resource.block_num] = obj; - - IRQn_Type irqn = (IRQn_Type) (srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); - cy_stc_sysint_t irqCfg = { irqn, CY_DEFAULT_MCWDT_PRIORITY }; - rslt = (cy_rslt_t) Cy_SysInt_Init(&irqCfg, &cyhal_lptimer_irq_handler); - - if (CY_RSLT_SUCCESS == rslt) - { - NVIC_EnableIRQ(irqn); - Cy_MCWDT_Enable(obj->base, CY_MCWDT_LPTIMER_CTRL, CY_MCWDT_RESET_TIME_US); - } + NVIC_EnableIRQ(irqn); + Cy_MCWDT_Enable(obj->base, CY_MCWDT_LPTIMER_CTRL, CY_MCWDT_RESET_TIME_US); } } + if (CY_RSLT_SUCCESS != rslt) { cyhal_lptimer_free(obj); @@ -154,96 +152,74 @@ void cyhal_lptimer_free(cyhal_lptimer_t *obj) cy_rslt_t cyhal_lptimer_reload(cyhal_lptimer_t *obj) { - Cy_MCWDT_ResetCounters(obj->base, (CY_MCWDT_CTR0 | CY_MCWDT_CTR1), CY_MCWDT_RESET_TIME_US); + Cy_MCWDT_ResetCounters(obj->base, CY_MCWDT_CTR2, CY_MCWDT_RESET_TIME_US); return CY_RSLT_SUCCESS; } -cy_rslt_t cyhal_lptimer_set_time(cyhal_lptimer_t *obj, uint32_t ticks) -{ - return cyhal_lptimer_set_match(obj, ticks); -} - cy_rslt_t cyhal_lptimer_set_match(cyhal_lptimer_t *obj, uint32_t ticks) { - uint16_t c0_match_ticks; - uint16_t c1_match_ticks; - uint32_t mcwdt_interrupt_mask; - uint16_t c0_current_ticks = Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER0); + return cyhal_lptimer_set_delay(obj, ticks - cyhal_lptimer_read(obj)); +} + +cy_rslt_t cyhal_lptimer_set_delay(cyhal_lptimer_t *obj, uint32_t delay) +{ + /** + * 16 bit C0/C1 are cascaded to generated a 32 bit counter. + * Counter0 continues counting after reaching its match value + * Interrupt is generated on Counter1 match. + * + * Supposed T=C0=C1=0, and we need to trigger an interrupt at T=0x28000. + * We set C0_match to 0x8000 and C1 match to 1. + * At T = 0x8000, C0_value matches C0_match so C1 get incremented. C1/C0=0x18000. + * At T = 0x18000, C0_value matches C0_match again so C1 get incremented from 1 to 2. + * When C1 get incremented from 1 to 2 theinterrupt is generated. + * At T = 0x18000, C1/C0 = 0x28000. + */ + + if (delay <= CY_MCWDT_MIN_DELAY) + { + delay = CY_MCWDT_MIN_DELAY; + } + if (delay > CY_MCWDT_MAX_DELAY_TICKS) + { + delay = CY_MCWDT_MAX_DELAY_TICKS; + } + + uint16_t c0_increment = (uint16_t)delay; + uint16_t c1_increment = (uint16_t)(delay >> 16); + + Cy_MCWDT_ClearInterrupt(obj->base, CY_MCWDT_CTR1); + + uint16_t c0_old_match = Cy_MCWDT_GetMatch(obj->base, CY_MCWDT_COUNTER0); + + uint32_t critical_section = cyhal_system_critical_section_enter(); + + /* Cascading from C0 match into C1 is queued and can take 1 full LF clk cycle. + * There are 3 cases: + * Case 1: if c0 = match0 then the cascade into C1 will happen 1 cycle from now. The value c1_current_ticks is 1 lower than expected. + * Case 2: if c0 = match0 -1 then cascade may or not happen before new match value would occur. Match occurs on rising clock edge. + * Synching match value occurs on falling edge. Wait until c0 = match0 to ensure cascade occurs. + * Case 3: everything works as expected. + */ + uint16_t c0_current_ticks; + while ((c0_current_ticks = (Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER0))) == c0_old_match) {} + uint16_t c1_current_ticks = Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER1); - - Cy_MCWDT_ClearInterrupt(obj->base, (CY_MCWDT_CTR0 | CY_MCWDT_CTR1)); - - /* Use MCWDT C0,C1 and C2 to implement a 32bit free running counter - C2 alone can not be used as it does not support interrupt on match feature - C2 is used to keep track of time, while C0 and C1 are used to set interrupts - To set an interrupt: - 1. delay = diff between timestamp(time in future) vs current value of C2 - 2. if delay > 2seconds (Max time that can be counted by C0) - Yes - - use both C0 and C1 - - Increment C0 by delay % (CY_MCWDT_COUNTER0_MAX_TICKS + 1) - - Increment C1 by delay / (CY_MCWDT_COUNTER1_MAX_TICKS + 1) - - Special case : In case delay is multiple of (CY_MCWDT_COUNTER0_MAX_TICKS + 1), then - delay % (CY_MCWDT_COUNTER0_MAX_TICKS + 1) will be 0, in this case - - Increment C0 by c0_current_ticks -1 - - Increment C1 by (delay / (CY_MCWDT_COUNTER1_MAX_TICKS + 1)) -1 - No - - Use only C0 - */ - if (ticks > CY_MCWDT_COUNTER0_MAX_TICKS) + if (c0_current_ticks == c0_old_match + 1) { - uint16_t c0_increment; - uint16_t c1_increment; - - if (ticks > CY_MCWDT_MAX_DELAY_TICKS) - { - ticks = CY_MCWDT_MAX_DELAY_TICKS; - } - - c0_increment = ticks % (CY_MCWDT_COUNTER0_MAX_TICKS + 1); - c0_match_ticks = (c0_current_ticks + c0_increment) % (CY_MCWDT_COUNTER0_MAX_TICKS + 1); - c1_increment = (ticks) / (CY_MCWDT_COUNTER0_MAX_TICKS + 1); - c1_match_ticks = (c1_current_ticks + c1_increment) % (CY_MCWDT_COUNTER1_MAX_TICKS + 1); - - /* Special case - ticks is multiple of (CY_MCWDT_COUNTER0_MAX_TICKS + 1) */ - if (c0_increment == 0) - { - c0_match_ticks = c0_current_ticks - 1; - c1_match_ticks = c1_match_ticks -1; - } - - mcwdt_interrupt_mask = CY_MCWDT_CTR1; + c1_current_ticks++; } - else + if (Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER0) != c0_current_ticks) { - c0_match_ticks = c0_current_ticks + (uint16_t)ticks; - c1_match_ticks = CY_MCWDT_COUNTER1_MAX_TICKS; - - /* MCWDT has internal delay of about 1.5 LF clock ticks, so this is the minimum - * that we can schedule. - */ - if (ticks < 3) - { - /* Cheating a bit here. */ - c0_match_ticks = c0_current_ticks + 3; - } - - mcwdt_interrupt_mask = CY_MCWDT_CTR0; + // Just in the very unlikely case that an increment occurred while previous instruction was running. + c1_current_ticks = Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER1); } + Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER0, c0_current_ticks + c0_increment, CY_MCWDT_SETMATCH_NOWAIT_TIME_US); + Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER1, c1_current_ticks + c1_increment, CY_MCWDT_SETMATCH_NOWAIT_TIME_US); - if(c1_match_ticks == 0) - { - c1_match_ticks = 1; - } + cyhal_system_critical_section_exit(critical_section); - if(c0_match_ticks == 0) - { - c0_match_ticks = 1; - } - - Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER0, c0_match_ticks, CY_MCWDT_SETMATCH_NOWAIT_TIME_US); - Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER1, c1_match_ticks, CY_MCWDT_SETMATCH_NOWAIT_TIME_US); - Cy_MCWDT_SetInterruptMask(obj->base, mcwdt_interrupt_mask); + Cy_MCWDT_SetInterruptMask(obj->base, CY_MCWDT_CTR1); return CY_RSLT_SUCCESS; } @@ -265,7 +241,9 @@ void cyhal_lptimer_register_callback(cyhal_lptimer_t *obj, cyhal_lptimer_event_c void cyhal_lptimer_enable_event(cyhal_lptimer_t *obj, cyhal_lptimer_event_t event, uint8_t intrPriority, bool enable) { - Cy_MCWDT_SetInterruptMask(obj->base, enable ? CY_MCWDT_CTR0 : 0); + CY_ASSERT(event == CYHAL_LPTIMER_COMPARE_MATCH); + Cy_MCWDT_ClearInterrupt(obj->base, CY_MCWDT_CTR1); + Cy_MCWDT_SetInterruptMask(obj->base, enable ? CY_MCWDT_CTR1 : 0); IRQn_Type irqn = (IRQn_Type)(srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); NVIC_SetPriority(irqn, intrPriority); From 63583ff6b1cbfde0eafe689a48cd7692211f32b7 Mon Sep 17 00:00:00 2001 From: "YARB(Cypress)" Date: Thu, 5 Dec 2019 16:11:50 +0200 Subject: [PATCH 29/49] Backport #12038: Remove qspi_frequency() call. cy_qspi_frequency is not implemented. This change is made because for compatibility reason with upcoming cy_hal changes. --- targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c index 3404dcc75d..f747eb0f82 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c @@ -38,7 +38,8 @@ qspi_status_t qspi_free(qspi_t *obj) qspi_status_t qspi_frequency(qspi_t *obj, int hz) { - return CY_RSLT_SUCCESS == cyhal_qspi_set_frequency(&(obj->hal_qspi), (uint32_t)hz) ? QSPI_STATUS_OK : QSPI_STATUS_ERROR; + /* Return OK since this API is not implemented in cy_hal */ + return QSPI_STATUS_OK; } static inline cyhal_qspi_bus_width_t cyhal_qspi_convert_width(qspi_bus_width_t width) From 738ec191837718fb310c40831a06cb713a2d120f Mon Sep 17 00:00:00 2001 From: "YARB(Cypress)" Date: Mon, 9 Dec 2019 12:54:39 +0200 Subject: [PATCH 30/49] Backport #12052: Fix for ARM issue 11859. 1. Clear UART events before enabling 2. Reset device before return from test case --- TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp | 3 +++ .../TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp index 56c94347af..1ee96b95b7 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp @@ -133,6 +133,9 @@ static void uart_test_common(int baudrate, int data_bits, SerialParity parity, i serial_set_flow_control_direct(&serial, FlowControlRTSCTS, &pinmap); #else //skip this test case if static pinmap is not supported + // Cleanup uart to be able execute next test case + serial_free(&serial); + tester.reset(); return; #endif } else { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c index 8b1522aaf6..fe5b2ea491 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c @@ -720,10 +720,12 @@ void cyhal_uart_enable_event(cyhal_uart_t *obj, cyhal_uart_event_t event, uint8_ obj->irq_cause &= ~event; if (event & CYHAL_UART_IRQ_RX_NOT_EMPTY) { + Cy_SCB_ClearRxInterrupt(obj->base, CY_SCB_RX_INTR_NOT_EMPTY); Cy_SCB_SetRxInterruptMask(obj->base, Cy_SCB_GetRxInterruptMask(obj->base) & ~CY_SCB_RX_INTR_NOT_EMPTY); } if (event & CYHAL_UART_IRQ_TX_EMPTY) { + Cy_SCB_ClearTxInterrupt(obj->base, CY_SCB_UART_TX_EMPTY); Cy_SCB_SetTxInterruptMask(obj->base, Cy_SCB_GetTxInterruptMask(obj->base) & ~CY_SCB_UART_TX_EMPTY); } } From a0ee701d83900e2dbcfecce9ef167c381f083095 Mon Sep 17 00:00:00 2001 From: Shuopeng Deng Date: Wed, 11 Dec 2019 09:28:05 -0800 Subject: [PATCH 31/49] Backport #12097: Cypress: Fix IAR Warnings fix 'enumerated type mixed with another type' IAR warnings fix 'statement is unreachable' IAR warning --- targets/TARGET_Cypress/TARGET_PSOC6/cy_port_api.c | 4 ++-- targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c | 7 +++---- targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c | 1 - 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_port_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_port_api.c index a75bf716f7..d89ccfadb5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_port_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_port_api.c @@ -41,7 +41,7 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) void port_mode(port_t *obj, PinMode mode) { - gpio_t gpio = {.pin = 0, .direction = obj->direction, .drive_mode = obj->drive_mode}; + gpio_t gpio = {.direction = obj->direction, .drive_mode = obj->drive_mode}; for (uint8_t pin = 0; pin < 8; pin++) { if ((1 << pin) & obj->mask) { gpio.pin = port_pin(obj->port, pin); @@ -52,7 +52,7 @@ void port_mode(port_t *obj, PinMode mode) void port_dir(port_t *obj, PinDirection dir) { - gpio_t gpio = {.pin = 0, .direction = obj->direction, .drive_mode = obj->drive_mode}; + gpio_t gpio = {.direction = obj->direction, .drive_mode = obj->drive_mode}; for (uint8_t pin = 0; pin < 8; pin++) { if ((1 << pin) & obj->mask) { gpio.pin = port_pin(obj->port, pin); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c index ee9f2536cf..820f4b43ae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c @@ -125,7 +125,6 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b break; default: MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_CODE_UNSUPPORTED), "Unsupported parity"); - return; } cyhal_uart_cfg_t cfg = { .data_bits = data_bits, @@ -152,11 +151,11 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) static const cyhal_uart_event_t interrupt_mask = (cyhal_uart_event_t) (CYHAL_UART_IRQ_RX_DONE | CYHAL_UART_IRQ_RX_ERROR | CYHAL_UART_IRQ_RX_NOT_EMPTY); ser->rx_event_mask = enable - ? (ser->rx_event_mask | interrupt_mask) - : (ser->rx_event_mask & ~interrupt_mask); + ? (cyhal_uart_event_t)(ser->rx_event_mask | interrupt_mask) + : (cyhal_uart_event_t)(ser->rx_event_mask & ~interrupt_mask); cyhal_uart_enable_event(&(ser->hal_obj), interrupt_mask, CYHAL_ISR_PRIORITY_DEFAULT, (bool)enable); } else if (irq == TxIrq) { - static const cyhal_uart_event_t interrupt_mask = CYHAL_UART_IRQ_TX_DONE | CYHAL_UART_IRQ_TX_ERROR | CYHAL_UART_IRQ_TX_EMPTY; + static const cyhal_uart_event_t interrupt_mask = (cyhal_uart_event_t)(CYHAL_UART_IRQ_TX_DONE | CYHAL_UART_IRQ_TX_ERROR | CYHAL_UART_IRQ_TX_EMPTY); ser->tx_event_mask = enable ? (cyhal_uart_event_t)(ser->tx_event_mask | interrupt_mask) : (cyhal_uart_event_t)(ser->tx_event_mask & ~interrupt_mask); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c index 522d9a6ec0..f6bff0799a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c @@ -45,7 +45,6 @@ SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName mclk) return (SPIName)CYHAL_SCB_BASE_ADDRESSES[map->inst->block_num]; } MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "SPI not found"); - return (SPIName)0; } static void cy_spi_irq_handler_internal(void *handler_arg, cyhal_spi_event_t event) From 8199e25f24cb5017fced58d98d5d6bd67f389730 Mon Sep 17 00:00:00 2001 From: midd Date: Fri, 10 Jan 2020 14:45:16 -0800 Subject: [PATCH 32/49] Backport #12394: Fix Cypress 1M SDIO + other minor bugs - Remove wounding for the hardware CRYPTO block. The PSoC 6 MPN CYW9P62S1_43012EVB_01 was revised to add the hardware crypto block. - Add missing error checks for emac power up. - Add a multiplied by 2 in the SDIO clock divider calculation to account for internal UDB divider. Note: Fixes issues with intermittent WiFi firmware load failures on CY8CKIT_062_WIFI_BT, CYW943012P6EVB_01, CYW9P62S1_43012EVB_01, CYW9P62S1_43438EVB_01. --- .../interface/WhdSTAInterface.cpp | 18 +++++++--- .../SDIO_HOST/SDIO_HOST.c | 33 +++++++++++-------- .../SDIO_HOST/SDIO_HOST.h | 2 +- .../SDIO_HOST/SDIO_HOST_cfg.c | 2 +- .../SDIO_HOST/SDIO_HOST_cfg.h | 2 +- .../SDIO_HOST/SDIO_HOST.c | 33 +++++++++++-------- .../SDIO_HOST/SDIO_HOST.h | 2 +- .../SDIO_HOST/SDIO_HOST_cfg.c | 2 +- .../SDIO_HOST/SDIO_HOST_cfg.h | 2 +- .../SDIO_HOST/SDIO_HOST.c | 33 +++++++++++-------- .../SDIO_HOST/SDIO_HOST.h | 2 +- .../SDIO_HOST/SDIO_HOST_cfg.c | 2 +- .../SDIO_HOST/SDIO_HOST_cfg.h | 2 +- .../SDIO_HOST/SDIO_HOST.c | 33 +++++++++++-------- .../SDIO_HOST/SDIO_HOST.h | 2 +- .../SDIO_HOST/SDIO_HOST_cfg.c | 2 +- .../SDIO_HOST/SDIO_HOST_cfg.h | 2 +- targets/targets.json | 4 +-- 18 files changed, 102 insertions(+), 76 deletions(-) diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp index de4ffdfbd6..0995b10145 100644 --- a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp +++ b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp @@ -250,7 +250,9 @@ nsapi_error_t WhdSTAInterface::connect() // initialize wiced, this is noop if already init if (!_whd_emac.powered_up) { - _whd_emac.power_up(); + if(!_whd_emac.power_up()) { + return NSAPI_ERROR_DEVICE_ERROR; + } } res = whd_management_set_event_handler(_whd_emac.ifp, sta_link_change_events, @@ -322,7 +324,9 @@ nsapi_error_t WhdSTAInterface::connect() void WhdSTAInterface::wifi_on() { if (!_whd_emac.powered_up) { - _whd_emac.power_up(); + if(!_whd_emac.power_up()) { + CY_ASSERT(false); + } } } @@ -375,11 +379,14 @@ int8_t WhdSTAInterface::get_rssi() // initialize wiced, this is noop if already init if (!_whd_emac.powered_up) { - _whd_emac.power_up(); + if(!_whd_emac.power_up()) { + CY_ASSERT(false); + } } res = (whd_result_t)whd_wifi_get_rssi(_whd_emac.ifp, &rssi); if (res != 0) { + CY_ASSERT(false); return 0; } @@ -454,7 +461,9 @@ int WhdSTAInterface::internal_scan(WiFiAccessPoint *aps, unsigned count, scan_re // initialize wiced, this is noop if already init if (!_whd_emac.powered_up) { - _whd_emac.power_up(); + if(!_whd_emac.power_up()) { + return NSAPI_ERROR_DEVICE_ERROR; + } } interal_scan_data.sema = new Semaphore(); @@ -467,7 +476,6 @@ int WhdSTAInterface::internal_scan(WiFiAccessPoint *aps, unsigned count, scan_re whd_result_t whd_res; int res; - whd_res = (whd_result_t)whd_wifi_scan(_whd_emac.ifp, WHD_SCAN_TYPE_ACTIVE, WHD_BSS_TYPE_ANY, NULL, NULL, NULL, NULL, whd_scan_handler, &internal_scan_result, &interal_scan_data); if (whd_res != WHD_SUCCESS) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c index 6c8154e78d..4e48631123 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -111,7 +111,7 @@ cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *para CY_UNUSED_PARAMETER(params); cy_en_syspm_status_t status = CY_SYSPM_FAIL; - switch (mode) + switch (mode) { case CY_SYSPM_CHECK_READY: case CY_SYSPM_CHECK_FAIL: @@ -656,7 +656,7 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) cy_rslt_t result; /* Initialize the semaphore. This is not done in init because init is called - * in interrupt thread. cy_rtos_init_semaphore call is prohibited in + * in interrupt thread. cy_rtos_init_semaphore call is prohibited in * interrupt thread. */ if(!sema_initialized) @@ -770,16 +770,16 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) #ifdef CY_RTOS_AWARE /* Wait for the transfer to finish. - * Acquire semaphore and wait until it will be released + * Acquire semaphore and wait until it will be released * in SDIO_IRQ: - * 1. sdio_transfer_finished_semaphore count is equal to - * zero. cy_rtos_get_semaphore waits until semaphore - * count is increased by cy_rtos_set_semaphore() in + * 1. sdio_transfer_finished_semaphore count is equal to + * zero. cy_rtos_get_semaphore waits until semaphore + * count is increased by cy_rtos_set_semaphore() in * SDIO_IRQ. - * 2. The cy_rtos_set_semaphore() increases + * 2. The cy_rtos_set_semaphore() increases * sdio_transfer_finished_semaphore count. - * 3. The cy_rtos_get_semaphore() function decreases - * sdio_transfer_finished_semaphore back to zero + * 3. The cy_rtos_get_semaphore() function decreases + * sdio_transfer_finished_semaphore back to zero * and exit. Or timeout occurs */ result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); @@ -1080,7 +1080,12 @@ void SDIO_DisableSdClk(void) void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) { uint16_t u16Div; - u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz; + /* + * The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB + * by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required + * SDIO operating frequency. + */ + u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz); Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); } @@ -1247,10 +1252,10 @@ void SDIO_IRQ(void) { pfnCardInt_count++; } - + /* Execute card interrupt callback if neccesary */ if (0 != pfnCardInt_count) - { + { if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) { gstcInternalData.pstcCallBacks.pfnCardIntCb(); @@ -1277,7 +1282,7 @@ void SDIO_IRQ(void) /* CRC was bad, set the flag */ gstcInternalData.stcEvents.u8CRCError++; } - + /* Set the done flag */ #ifdef CY_RTOS_AWARE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h index b821eb9a46..06edc747bc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c index 94e533da70..a2808d37c0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h index bed87f55bf..39febda573 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c index 6c8154e78d..4e48631123 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -111,7 +111,7 @@ cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *para CY_UNUSED_PARAMETER(params); cy_en_syspm_status_t status = CY_SYSPM_FAIL; - switch (mode) + switch (mode) { case CY_SYSPM_CHECK_READY: case CY_SYSPM_CHECK_FAIL: @@ -656,7 +656,7 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) cy_rslt_t result; /* Initialize the semaphore. This is not done in init because init is called - * in interrupt thread. cy_rtos_init_semaphore call is prohibited in + * in interrupt thread. cy_rtos_init_semaphore call is prohibited in * interrupt thread. */ if(!sema_initialized) @@ -770,16 +770,16 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) #ifdef CY_RTOS_AWARE /* Wait for the transfer to finish. - * Acquire semaphore and wait until it will be released + * Acquire semaphore and wait until it will be released * in SDIO_IRQ: - * 1. sdio_transfer_finished_semaphore count is equal to - * zero. cy_rtos_get_semaphore waits until semaphore - * count is increased by cy_rtos_set_semaphore() in + * 1. sdio_transfer_finished_semaphore count is equal to + * zero. cy_rtos_get_semaphore waits until semaphore + * count is increased by cy_rtos_set_semaphore() in * SDIO_IRQ. - * 2. The cy_rtos_set_semaphore() increases + * 2. The cy_rtos_set_semaphore() increases * sdio_transfer_finished_semaphore count. - * 3. The cy_rtos_get_semaphore() function decreases - * sdio_transfer_finished_semaphore back to zero + * 3. The cy_rtos_get_semaphore() function decreases + * sdio_transfer_finished_semaphore back to zero * and exit. Or timeout occurs */ result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); @@ -1080,7 +1080,12 @@ void SDIO_DisableSdClk(void) void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) { uint16_t u16Div; - u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz; + /* + * The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB + * by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required + * SDIO operating frequency. + */ + u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz); Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); } @@ -1247,10 +1252,10 @@ void SDIO_IRQ(void) { pfnCardInt_count++; } - + /* Execute card interrupt callback if neccesary */ if (0 != pfnCardInt_count) - { + { if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) { gstcInternalData.pstcCallBacks.pfnCardIntCb(); @@ -1277,7 +1282,7 @@ void SDIO_IRQ(void) /* CRC was bad, set the flag */ gstcInternalData.stcEvents.u8CRCError++; } - + /* Set the done flag */ #ifdef CY_RTOS_AWARE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h index b821eb9a46..06edc747bc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c index 94e533da70..a2808d37c0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h index bed87f55bf..39febda573 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c index 6c8154e78d..4e48631123 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -111,7 +111,7 @@ cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *para CY_UNUSED_PARAMETER(params); cy_en_syspm_status_t status = CY_SYSPM_FAIL; - switch (mode) + switch (mode) { case CY_SYSPM_CHECK_READY: case CY_SYSPM_CHECK_FAIL: @@ -656,7 +656,7 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) cy_rslt_t result; /* Initialize the semaphore. This is not done in init because init is called - * in interrupt thread. cy_rtos_init_semaphore call is prohibited in + * in interrupt thread. cy_rtos_init_semaphore call is prohibited in * interrupt thread. */ if(!sema_initialized) @@ -770,16 +770,16 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) #ifdef CY_RTOS_AWARE /* Wait for the transfer to finish. - * Acquire semaphore and wait until it will be released + * Acquire semaphore and wait until it will be released * in SDIO_IRQ: - * 1. sdio_transfer_finished_semaphore count is equal to - * zero. cy_rtos_get_semaphore waits until semaphore - * count is increased by cy_rtos_set_semaphore() in + * 1. sdio_transfer_finished_semaphore count is equal to + * zero. cy_rtos_get_semaphore waits until semaphore + * count is increased by cy_rtos_set_semaphore() in * SDIO_IRQ. - * 2. The cy_rtos_set_semaphore() increases + * 2. The cy_rtos_set_semaphore() increases * sdio_transfer_finished_semaphore count. - * 3. The cy_rtos_get_semaphore() function decreases - * sdio_transfer_finished_semaphore back to zero + * 3. The cy_rtos_get_semaphore() function decreases + * sdio_transfer_finished_semaphore back to zero * and exit. Or timeout occurs */ result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); @@ -1080,7 +1080,12 @@ void SDIO_DisableSdClk(void) void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) { uint16_t u16Div; - u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz; + /* + * The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB + * by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required + * SDIO operating frequency. + */ + u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz); Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); } @@ -1247,10 +1252,10 @@ void SDIO_IRQ(void) { pfnCardInt_count++; } - + /* Execute card interrupt callback if neccesary */ if (0 != pfnCardInt_count) - { + { if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) { gstcInternalData.pstcCallBacks.pfnCardIntCb(); @@ -1277,7 +1282,7 @@ void SDIO_IRQ(void) /* CRC was bad, set the flag */ gstcInternalData.stcEvents.u8CRCError++; } - + /* Set the done flag */ #ifdef CY_RTOS_AWARE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h index b821eb9a46..06edc747bc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c index 5232ed1701..e89c7c74b5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h index ff5671844c..60ab730b5d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.c index 6c8154e78d..4e48631123 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -111,7 +111,7 @@ cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *para CY_UNUSED_PARAMETER(params); cy_en_syspm_status_t status = CY_SYSPM_FAIL; - switch (mode) + switch (mode) { case CY_SYSPM_CHECK_READY: case CY_SYSPM_CHECK_FAIL: @@ -656,7 +656,7 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) cy_rslt_t result; /* Initialize the semaphore. This is not done in init because init is called - * in interrupt thread. cy_rtos_init_semaphore call is prohibited in + * in interrupt thread. cy_rtos_init_semaphore call is prohibited in * interrupt thread. */ if(!sema_initialized) @@ -770,16 +770,16 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) #ifdef CY_RTOS_AWARE /* Wait for the transfer to finish. - * Acquire semaphore and wait until it will be released + * Acquire semaphore and wait until it will be released * in SDIO_IRQ: - * 1. sdio_transfer_finished_semaphore count is equal to - * zero. cy_rtos_get_semaphore waits until semaphore - * count is increased by cy_rtos_set_semaphore() in + * 1. sdio_transfer_finished_semaphore count is equal to + * zero. cy_rtos_get_semaphore waits until semaphore + * count is increased by cy_rtos_set_semaphore() in * SDIO_IRQ. - * 2. The cy_rtos_set_semaphore() increases + * 2. The cy_rtos_set_semaphore() increases * sdio_transfer_finished_semaphore count. - * 3. The cy_rtos_get_semaphore() function decreases - * sdio_transfer_finished_semaphore back to zero + * 3. The cy_rtos_get_semaphore() function decreases + * sdio_transfer_finished_semaphore back to zero * and exit. Or timeout occurs */ result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); @@ -1080,7 +1080,12 @@ void SDIO_DisableSdClk(void) void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) { uint16_t u16Div; - u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz; + /* + * The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB + * by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required + * SDIO operating frequency. + */ + u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz); Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); } @@ -1247,10 +1252,10 @@ void SDIO_IRQ(void) { pfnCardInt_count++; } - + /* Execute card interrupt callback if neccesary */ if (0 != pfnCardInt_count) - { + { if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) { gstcInternalData.pstcCallBacks.pfnCardIntCb(); @@ -1277,7 +1282,7 @@ void SDIO_IRQ(void) /* CRC was bad, set the flag */ gstcInternalData.stcEvents.u8CRCError++; } - + /* Set the done flag */ #ifdef CY_RTOS_AWARE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.h index b821eb9a46..06edc747bc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.c index 94e533da70..a2808d37c0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.h index bed87f55bf..39febda573 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/targets.json b/targets/targets.json index 32617dbc4e..462932ae27 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2160,7 +2160,7 @@ "secure-ram-start": "0x30000000", "secure-ram-size": "0x22000" } - }, + }, "HANI_IOT": { "inherits": ["LPC55S69_NS"], "detect_code": ["0360"], @@ -9383,13 +9383,11 @@ "components_add": ["WHD", "43012", "CYW43XXX"], "components_remove": ["QSPIF"], "device_has_remove": ["ANALOGOUT", "QSPI"], - "macros_remove": ["MBEDTLS_CONFIG_HW_SUPPORT"], "extra_labels_add": [ "PSOC6_01", "MXCRYPTO_01", "CORDIO" ], - "extra_labels_remove": ["MXCRYPTO"], "macros_add": ["CY8C6247FDI_D52", "CYHAL_UDB_SDIO", "CYBSP_WIFI_CAPABLE"], "detect_code": ["1903"], "post_binary_hook": { From a15ed110a64cdde04bdda673eeaece16f1f11ed5 Mon Sep 17 00:00:00 2001 From: Dustin Crossman Date: Mon, 10 Feb 2020 12:01:51 -0800 Subject: [PATCH 33/49] Backport #12421: Cypress target reorganization - Remove CY8CMOD_062_4343W and merge into CY8CPROTO_062_4343W. - Remove CY8CMOD_062S2_43012 and merge into CY8CKIT_062S2_43012. - Remove CY8CMOD_062S3_4343W and merge into CY8CPROTO_062S3_4343W. - Removed CY8CMODs from targets.json. - Removed unnecessary PSOC6Code.complete post binary hook from cypress targets. --- .../PeripheralPins.c | 0 .../TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct | 0 .../TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S | 0 .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld | 0 .../startup_psoc6_02_cm0plus.S | 0 .../TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf | 0 .../TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S | 0 .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 0 .../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 0 .../TOOLCHAIN_ARM/startup_psoc6_02_cm4.S | 0 .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld | 0 .../TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S | 0 .../TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf | 0 .../TOOLCHAIN_IAR/startup_psoc6_02_cm4.S | 0 .../device/COMPONENT_CM4/system_psoc6_cm4.c | 0 .../device/system_psoc6.h | 0 .../PeripheralNames.h | 0 .../PeripheralPins.c | 0 .../TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct | 0 .../TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S | 0 .../TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld | 0 .../startup_psoc6_03_cm0plus.S | 0 .../TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf | 0 .../TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S | 0 .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 0 .../TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct | 0 .../TOOLCHAIN_ARM/startup_psoc6_03_cm4.S | 0 .../TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld | 0 .../TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S | 0 .../TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf | 0 .../TOOLCHAIN_IAR/startup_psoc6_03_cm4.S | 0 .../device/COMPONENT_CM4/system_psoc6_cm4.c | 0 .../device/system_psoc6.h | 0 .../PeripheralPins.c | 0 .../TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct | 0 .../TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S | 0 .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld | 0 .../startup_psoc6_02_cm0plus.S | 0 .../TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf | 0 .../TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S | 0 .../COMPONENT_CM0P/system_psoc6_cm0plus.c | 0 .../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 0 .../TOOLCHAIN_ARM/startup_psoc6_02_cm4.S | 0 .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld | 0 .../TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S | 0 .../TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf | 0 .../TOOLCHAIN_IAR/startup_psoc6_02_cm4.S | 0 .../device/COMPONENT_CM4/system_psoc6_cm4.c | 0 .../device/system_psoc6.h | 0 targets/targets.json | 70 ++++++------------- 50 files changed, 22 insertions(+), 48 deletions(-) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/PeripheralPins.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM0P/system_psoc6_cm0plus.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/COMPONENT_CM4/system_psoc6_cm4.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S2_43012 => TARGET_CY8CKIT_062S2_43012}/device/system_psoc6.h (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/PeripheralNames.h (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/PeripheralPins.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM0P/system_psoc6_cm0plus.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/COMPONENT_CM4/system_psoc6_cm4.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062S3_4343W => TARGET_CY8CPROTO_062S3_4343W}/device/system_psoc6.h (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/PeripheralPins.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM0P/system_psoc6_cm0plus.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/COMPONENT_CM4/system_psoc6_cm4.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/{TARGET_CY8CMOD_062_4343W => TARGET_CY8CPROTO_062_4343W}/device/system_psoc6.h (100%) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/PeripheralPins.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralPins.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/PeripheralPins.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/system_psoc6.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/system_psoc6.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/PeripheralNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/PeripheralNames.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/PeripheralNames.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/PeripheralNames.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/PeripheralPins.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/PeripheralPins.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/PeripheralPins.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/system_psoc6.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/system_psoc6.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/system_psoc6.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/PeripheralPins.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/PeripheralPins.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/PeripheralPins.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h diff --git a/targets/targets.json b/targets/targets.json index 462932ae27..031ae43f93 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9164,7 +9164,7 @@ "macros_add": ["MCU_PSOC6_M4", "CY_RTOS_AWARE", "CY_USING_HAL", "MBED_TICKLESS"], "public": false }, - "CY8CMOD_062_4343W": { + "CY8CPROTO_062_4343W": { "inherits": ["MCU_PSOC6_M4"], "features": ["BLE"], "components_add": ["WHD", "4343W", "CYW43XXX"], @@ -9175,28 +9175,42 @@ "CORDIO" ], "macros_add": ["CY8C624ABZI_D44", "CYBSP_WIFI_CAPABLE"], - "public": false, + "detect_code": [ + "1901" + ], + "bootloader_supported": false, + "sectors": [ + [ + 268435456, + 512 + ] + ], "overrides": { "network-default-interface-type": "WIFI" } }, - "CY8CMOD_062S2_43012": { + "CY8CKIT_062S2_43012": { "inherits": ["MCU_PSOC6_M4"], "features": ["BLE"], "components_add": ["WHD", "43012", "CYW43XXX"], "device_has_remove": ["ANALOGOUT"], + "supported_form_factors": [ + "ARDUINO" + ], "extra_labels_add": [ "PSOC6_02", "MXCRYPTO_02", "CORDIO" ], "macros_add": ["CY8C624ABZI_D44", "CYBSP_WIFI_CAPABLE"], - "public": false, + "detect_code": [ + "190B" + ], "overrides": { "network-default-interface-type": "WIFI" } }, - "CY8CMOD_062S3_4343W": { + "CY8CPROTO_062S3_4343W": { "inherits": ["MCU_PSOC6_M4"], "features": ["BLE"], "components_add": ["WHD", "4343W", "CYW43XXX"], @@ -9212,7 +9226,9 @@ "CY_ENABLE_XIP_PROGRAM", "CY_STORAGE_WIFI_DATA=\".cy_xip\"" ], - "public": false, + "detect_code": [ + "190E" + ], "overrides": { "network-default-interface-type": "WIFI", "xip-enable": true @@ -9253,9 +9269,6 @@ ], "macros_add": ["CY8C6247BZI_D54", "CYHAL_UDB_SDIO", "CYBSP_WIFI_CAPABLE"], "detect_code": ["1900"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, "bootloader_supported": false, "sectors": [[268435456, 512]], "overrides": { @@ -9263,30 +9276,6 @@ }, "program_cycle_s": 10 }, - "CY8CPROTO_062_4343W": { - "inherits": ["CY8CMOD_062_4343W"], - "detect_code": ["1901"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, - "bootloader_supported": false, - "sectors": [[268435456, 512]] - }, - "CY8CPROTO_062S3_4343W": { - "inherits": ["CY8CMOD_062S3_4343W"], - "detect_code": ["190E"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - } - }, - "CY8CKIT_062S2_43012": { - "inherits": ["CY8CMOD_062S2_43012"], - "supported_form_factors": ["ARDUINO"], - "detect_code": ["190B"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - } - }, "CY8CKIT_062_BLE": { "inherits": ["MCU_PSOC6_M4"], "device_has_remove": ["USBDEVICE"], @@ -9297,9 +9286,6 @@ ], "macros_add": ["CY8C6347BZI_BLD53"], "detect_code": ["1902"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, "sectors": [[268443648, 512]], "bootloader_supported": false }, @@ -9313,9 +9299,6 @@ ], "macros_add": ["CYBLE_416045_02"], "detect_code": ["1904"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, "sectors": [[268443648, 512]], "bootloader_supported": false }, @@ -9348,9 +9331,6 @@ ], "macros_add": ["CY8C6247BZI_D54", "CYHAL_UDB_SDIO", "CYBSP_WIFI_CAPABLE"], "detect_code": ["1900"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, "bootloader_supported": false, "sectors": [[268435456, 512]], "overrides": { @@ -9369,9 +9349,6 @@ ], "macros_add": ["CY8C6247BZI_D54", "CYHAL_UDB_SDIO", "CYBSP_WIFI_CAPABLE"], "detect_code": ["1906"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, "overrides": { "network-default-interface-type": "WIFI" } @@ -9390,9 +9367,6 @@ ], "macros_add": ["CY8C6247FDI_D52", "CYHAL_UDB_SDIO", "CYBSP_WIFI_CAPABLE"], "detect_code": ["1903"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, "overrides": { "network-default-interface-type": "WIFI" } From ca47da601806004383bae8c6972883720ea95ce8 Mon Sep 17 00:00:00 2001 From: Dustin Crossman Date: Fri, 7 Feb 2020 14:31:23 -0800 Subject: [PATCH 34/49] Backport #12422: Cypress Asset Update - Update psoc6pdl to version 1.4.1.2240 - Update psoc6 core_lib to version 1.1.1.11109. - Update psoc6hal to 1.1.1.11145. - Store RTC century and RTC state information in persistent BREG register. --- .../psoc6csp/core_lib/include/cy_result.h | 4 +- .../psoc6csp/core_lib/include/cy_utils.h | 2 +- .../psoc6csp/core_lib/version.xml | 1 + .../TARGET_PSOC6/psoc6csp/hal/include/cyhal.h | 12 +- .../psoc6csp/hal/include/cyhal_adc.h | 32 +- .../hal/include/cyhal_analog_common.h | 6 +- .../psoc6csp/hal/include/cyhal_crc.h | 13 +- .../psoc6csp/hal/include/cyhal_crc_impl.h | 6 +- .../hal/include/cyhal_crypto_common.h | 4 +- .../psoc6csp/hal/include/cyhal_dac.h | 9 +- .../psoc6csp/hal/include/cyhal_dma.h | 185 + .../psoc6csp/hal/include/cyhal_dma_dmac.h | 94 + .../psoc6csp/hal/include/cyhal_dma_dw.h | 94 + .../psoc6csp/hal/include/cyhal_dma_impl.h | 73 + .../psoc6csp/hal/include/cyhal_ezi2c.h | 186 ++ .../psoc6csp/hal/include/cyhal_flash.h | 8 +- .../psoc6csp/hal/include/cyhal_gpio.h | 98 +- .../psoc6csp/hal/include/cyhal_gpio_impl.h | 2 +- .../psoc6csp/hal/include/cyhal_hw_resources.h | 11 +- .../psoc6csp/hal/include/cyhal_hw_types.h | 128 +- .../psoc6csp/hal/include/cyhal_hwmgr.h | 18 +- .../psoc6csp/hal/include/cyhal_i2c.h | 203 +- .../psoc6csp/hal/include/cyhal_interconnect.h | 10 +- .../psoc6csp/hal/include/cyhal_lptimer.h | 18 +- .../psoc6csp/hal/include/cyhal_modules.h | 13 +- .../psoc6csp/hal/include/cyhal_pin_package.h | 47 +- .../psoc6csp/hal/include/cyhal_pwm.h | 133 +- .../psoc6csp/hal/include/cyhal_pwm_impl.h | 2 +- .../psoc6csp/hal/include/cyhal_qspi.h | 19 +- .../psoc6csp/hal/include/cyhal_rtc.h | 67 +- .../psoc6csp/hal/include/cyhal_scb_common.h | 4 +- .../psoc6csp/hal/include/cyhal_sdhc.h | 10 +- .../psoc6csp/hal/include/cyhal_sdio.h | 35 +- .../psoc6csp/hal/include/cyhal_spi.h | 60 +- .../psoc6csp/hal/include/cyhal_system.h | 59 +- .../psoc6csp/hal/include/cyhal_system_impl.h | 6 +- .../psoc6csp/hal/include/cyhal_tcpwm_common.h | 4 +- .../psoc6csp/hal/include/cyhal_timer.h | 116 +- .../psoc6csp/hal/include/cyhal_timer_impl.h | 2 +- .../psoc6csp/hal/include/cyhal_triggers.h | 56 + .../psoc6csp/hal/include/cyhal_trng.h | 6 +- .../psoc6csp/hal/include/cyhal_trng_impl.h | 2 +- .../psoc6csp/hal/include/cyhal_uart.h | 24 +- .../psoc6csp/hal/include/cyhal_usb_dev.h | 60 +- .../psoc6csp/hal/include/cyhal_utils.h | 44 +- .../psoc6csp/hal/include/cyhal_wdt.h | 44 +- .../cyhal_psoc6_01_104_m_csp_ble.h | 241 +- .../cyhal_psoc6_01_104_m_csp_ble_usb.h | 243 +- .../pin_packages/cyhal_psoc6_01_116_bga_ble.h | 257 +- .../pin_packages/cyhal_psoc6_01_116_bga_usb.h | 255 +- .../pin_packages/cyhal_psoc6_01_124_bga.h | 305 +- .../pin_packages/cyhal_psoc6_01_124_bga_sip.h | 273 +- .../pin_packages/cyhal_psoc6_01_43_smt.h | 173 +- .../pin_packages/cyhal_psoc6_01_68_qfn_ble.h | 183 +- .../pin_packages/cyhal_psoc6_01_80_wlcsp.h | 229 +- .../pin_packages/cyhal_psoc6_02_100_wlcsp.h | 253 +- .../pin_packages/cyhal_psoc6_02_124_bga.h | 289 +- .../pin_packages/cyhal_psoc6_02_128_tqfp.h | 293 +- .../pin_packages/cyhal_psoc6_02_68_qfn.h | 195 +- .../pin_packages/cyhal_psoc6_03_100_tqfp.h | 206 +- .../pin_packages/cyhal_psoc6_03_49_wlcsp.h | 148 +- .../pin_packages/cyhal_psoc6_03_68_qfn.h | 184 +- .../triggers/cyhal_triggers_psoc6_01.h | 547 +++ .../triggers/cyhal_triggers_psoc6_02.h | 175 + .../triggers/cyhal_triggers_psoc6_03.h | 176 + .../psoc6csp/hal/{src => source}/cyhal_adc.c | 8 +- .../hal/{src => source}/cyhal_analog_common.c | 2 +- .../psoc6csp/hal/{src => source}/cyhal_crc.c | 2 +- .../hal/{src => source}/cyhal_crypto_common.c | 2 +- .../psoc6csp/hal/{src => source}/cyhal_dac.c | 8 +- .../psoc6csp/hal/source/cyhal_dma.c | 206 ++ .../psoc6csp/hal/source/cyhal_dma_dmac.c | 364 ++ .../psoc6csp/hal/source/cyhal_dma_dw.c | 402 +++ .../psoc6csp/hal/source/cyhal_ezi2c.c | 289 ++ .../hal/{src => source}/cyhal_flash.c | 2 +- .../psoc6csp/hal/{src => source}/cyhal_gpio.c | 16 +- .../hal/{src => source}/cyhal_hwmgr.c | 46 +- .../psoc6csp/hal/{src => source}/cyhal_i2c.c | 30 +- .../hal/{src => source}/cyhal_interconnect.c | 2 +- .../hal/{src => source}/cyhal_lptimer.c | 10 +- .../{src => source}/cyhal_not_implemented.c | 34 +- .../psoc6csp/hal/source/cyhal_pwm.c | 340 ++ .../psoc6csp/hal/{src => source}/cyhal_qspi.c | 168 +- .../psoc6csp/hal/{src => source}/cyhal_rtc.c | 164 +- .../hal/{src => source}/cyhal_scb_common.c | 2 +- .../psoc6csp/hal/{src => source}/cyhal_sdhc.c | 193 +- .../psoc6csp/hal/{src => source}/cyhal_spi.c | 36 +- .../hal/{src => source}/cyhal_system.c | 60 +- .../hal/{src => source}/cyhal_tcpwm_common.c | 33 +- .../hal/{src => source}/cyhal_timer.c | 16 +- .../psoc6csp/hal/{src => source}/cyhal_trng.c | 2 +- .../psoc6csp/hal/{src => source}/cyhal_uart.c | 30 +- .../hal/{src => source}/cyhal_udb_sdio.c | 59 +- .../hal/{src => source}/cyhal_usb_dev.c | 13 +- .../hal/{src => source}/cyhal_utils.c | 36 +- .../psoc6csp/hal/{src => source}/cyhal_wdt.c | 12 +- .../cyhal_psoc6_01_104_m_csp_ble.c | 2 +- .../cyhal_psoc6_01_104_m_csp_ble_usb.c | 2 +- .../pin_packages/cyhal_psoc6_01_116_bga_ble.c | 2 +- .../pin_packages/cyhal_psoc6_01_116_bga_usb.c | 2 +- .../pin_packages/cyhal_psoc6_01_124_bga.c | 2 +- .../pin_packages/cyhal_psoc6_01_124_bga_sip.c | 2 +- .../pin_packages/cyhal_psoc6_01_43_smt.c | 2 +- .../pin_packages/cyhal_psoc6_01_68_qfn_ble.c | 2 +- .../pin_packages/cyhal_psoc6_01_80_wlcsp.c | 2 +- .../pin_packages/cyhal_psoc6_02_100_wlcsp.c | 2 +- .../pin_packages/cyhal_psoc6_02_124_bga.c | 2 +- .../pin_packages/cyhal_psoc6_02_128_tqfp.c | 2 +- .../pin_packages/cyhal_psoc6_02_68_qfn.c | 2 +- .../pin_packages/cyhal_psoc6_03_100_tqfp.c | 2 +- .../pin_packages/cyhal_psoc6_03_49_wlcsp.c | 2 +- .../pin_packages/cyhal_psoc6_03_68_qfn.c | 2 +- .../source/triggers/cyhal_triggers_psoc6_01.c | 999 ++++++ .../source/triggers/cyhal_triggers_psoc6_02.c | 255 ++ .../source/triggers/cyhal_triggers_psoc6_03.c | 257 ++ .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c | 239 -- .../TARGET_PSOC6/psoc6csp/hal/version.xml | 1 + .../TARGET_PSOC6/psoc6pdl/README.md | 2 +- .../TARGET_PSOC6/psoc6pdl/RELEASE.md | 53 +- .../devices/include/cy8c6245fni_s3d11.h | 15 +- .../devices/include/cy8c6245fni_s3d41.h | 15 +- .../devices/include/cy8c6245fni_s3d71.h | 15 +- .../devices/include/cy_device_headers.h | 8 +- .../devices/include/cyb0644abzi_s2d44.h | 6 +- .../devices/include/cys0644abzi_s2d44.h | 1329 ++++++++ .../devices/include/gpio_psoc6_04_68_qfn.h | 1166 +++++++ .../devices/include/ip/cyip_ctbm_v2.h | 271 ++ .../include/ip/cyip_efuse_data_psoc6_04.h | 250 ++ .../devices/include/ip/cyip_pass_v2.h | 342 ++ .../psoc6pdl/devices/include/ip/cyip_sar_v2.h | 563 ++++ .../psoc6pdl/devices/include/ip/cyip_sflash.h | 62 +- .../devices/include/ip/cyip_tcpwm_v2.h | 272 ++ .../psoc6pdl/devices/include/ip/cyip_usbfs.h | 98 +- .../devices/include/psoc6_04_config.h | 2972 +++++++++++++++++ .../psoc6pdl/devices/include/psoc6a256k.h | 1197 +++++++ .../psoc6pdl/drivers/include/cy_ble_clk.h | 35 +- .../psoc6pdl/drivers/include/cy_canfd.h | 11 +- .../psoc6pdl/drivers/include/cy_device.h | 43 +- .../psoc6pdl/drivers/include/cy_efuse.h | 7 +- .../psoc6pdl/drivers/include/cy_flash.h | 55 +- .../psoc6pdl/drivers/include/cy_prot.h | 10 +- .../psoc6pdl/drivers/include/cy_rtc.h | 23 +- .../psoc6pdl/drivers/include/cy_smif.h | 15 +- .../drivers/include/cy_smif_memslot.h | 88 +- .../psoc6pdl/drivers/include/cy_sysclk.h | 240 +- .../psoc6pdl/drivers/include/cy_syslib.h | 24 +- .../psoc6pdl/drivers/include/cy_syspm.h | 25 +- .../source/TOOLCHAIN_ARM/cy_syslib_mdk.S | 4 +- .../TOOLCHAIN_A_Clang/cy_syslib_a_clang.S | 4 +- .../source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S | 4 +- .../source/TOOLCHAIN_IAR/cy_syslib_iar.S | 4 +- .../psoc6pdl/drivers/source/cy_ble_clk.c | 7 +- .../psoc6pdl/drivers/source/cy_canfd.c | 74 +- .../psoc6pdl/drivers/source/cy_device.c | 107 + .../psoc6pdl/drivers/source/cy_efuse.c | 6 +- .../psoc6pdl/drivers/source/cy_flash.c | 13 +- .../psoc6pdl/drivers/source/cy_prot.c | 59 +- .../psoc6pdl/drivers/source/cy_rtc.c | 55 +- .../psoc6pdl/drivers/source/cy_smif.c | 2 +- .../psoc6pdl/drivers/source/cy_smif_memslot.c | 909 ++++- .../psoc6pdl/drivers/source/cy_sysclk.c | 304 +- .../psoc6pdl/drivers/source/cy_syslib.c | 4 +- .../psoc6pdl/drivers/source/cy_syspm.c | 25 +- .../psoc6pdl/personalities/.cymigration | 2 +- .../peripheral/canfd-1.0.cypersonality | 11 +- .../connectivity_wifi-1.0.cypersonality | 6 +- .../peripheral/i2s-1.0.cypersonality | 12 +- .../peripheral/pdm_pcm-1.0.cypersonality | 12 +- .../peripheral/seglcd-1.1.cypersonality | 10 +- .../peripheral/smartio-1.0.cypersonality | 10 +- .../peripheral/smif-1.1.cypersonality | 28 +- .../platform/dma-1.0.cypersonality | 6 +- .../platform/sysclock-1.2.cypersonality | 1 + .../psoc6pdl/udd/001-91989.revision | 1 + .../TARGET_PSOC6/psoc6pdl/udd/MXS40.revision | 1 + .../43012C0/CYW43012C0WKWBG/base/view.xml | 16 + .../43012C0/CYW43012C0WKWBG/info.xml | 6 + .../CYW43012C0WKWBG/studio/presentation | 2 + .../43012C0/CYW43012C0WKWBG/studio/view.xml | 23 + .../CYW43012TC0EKUBG/studio/presentation | 4 +- .../CYW43012TC0KFFBH/studio/presentation | 4 +- .../43012C0/CYW43012WKWBG/studio/presentation | 4 +- .../4343A1/CYW43438KUBG/studio/presentation | 4 +- .../4343A1/CYW4343WKUBG/studio/presentation | 4 +- .../4343A1/CYW4343WKWBG/studio/presentation | 4 +- .../MXS40/PSoC6A256K/PSoC6A256K/base/view.xml | 16 + .../MXS40/PSoC6A256K/PSoC6A256K/info.xml | 6 + .../udd/devices/MXS40/PSoC6A256K/info.xml | 5 + .../CY8C6248AZI-S2D14/studio/presentation | 4 +- .../CY8C6248AZI-S2D44/studio/presentation | 4 +- .../CY8C6248BZI-S2D44/studio/presentation | 4 +- .../CY8C6248FNI-S2D43/studio/presentation | 4 +- .../CY8C624AAZI-D44/studio/presentation | 4 +- .../CY8C624AAZI-S2D14/studio/presentation | 4 +- .../CY8C624AAZI-S2D44/studio/presentation | 4 +- .../CY8C624ABZI-D44/studio/presentation | 4 +- .../CY8C624ABZI-S2D04/studio/presentation | 4 +- .../CY8C624ABZI-S2D14/studio/presentation | 4 +- .../CY8C624ABZI-S2D44/studio/presentation | 4 +- .../CY8C624ABZI-S2D44A0/studio/presentation | 4 +- .../CY8C624AFNI-D43/studio/presentation | 4 +- .../CY8C624AFNI-S2D43/studio/presentation | 4 +- .../CY8C624ALQI-D42/studio/presentation | 4 +- .../PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml | 4 +- .../CYB0644ABZI-S2D44/studio/presentation | 4 +- .../CYB0644ABZI-S2D44/studio/view.xml | 2 +- .../PSoC6A2M/CYS0644ABZI-S2D44/base/view.xml | 16 + .../MXS40/PSoC6A2M/CYS0644ABZI-S2D44/info.xml | 6 + .../CYS0644ABZI-S2D44/studio/presentation | 2 + .../CYS0644ABZI-S2D44/studio/view.xml | 59 + .../MXS40/PSoC6A2M/studio/clocks.cysem | 2 +- .../CY8C6245AZI-S3D02/studio/presentation | 4 +- .../CY8C6245AZI-S3D12/studio/presentation | 4 +- .../CY8C6245AZI-S3D42/studio/presentation | 4 +- .../CY8C6245AZI-S3D62/studio/presentation | 4 +- .../CY8C6245AZI-S3D72/studio/presentation | 4 +- .../CY8C6245FNI-S3D11/studio/presentation | 4 +- .../CY8C6245FNI-S3D11/studio/view.xml | 2 +- .../CY8C6245FNI-S3D41/studio/presentation | 4 +- .../CY8C6245FNI-S3D41/studio/view.xml | 2 +- .../CY8C6245FNI-S3D71/studio/presentation | 4 +- .../CY8C6245FNI-S3D71/studio/view.xml | 2 +- .../CY8C6245LQI-S3D02/studio/presentation | 4 +- .../CY8C6245LQI-S3D12/studio/presentation | 4 +- .../CY8C6245LQI-S3D42/studio/presentation | 4 +- .../CY8C6245LQI-S3D62/studio/presentation | 4 +- .../CY8C6245LQI-S3D72/studio/presentation | 4 +- .../CY8C6245W-S3D72/studio/presentation | 4 +- .../CYB06445LQI-S3D42/studio/presentation | 4 +- .../MXS40/PSoC6A512K/studio/clocks.cysem | 2 +- .../CY8C6016BZI-F04/studio/presentation | 4 +- .../CY8C6036BZI-F04/studio/presentation | 4 +- .../CY8C6116BZI-F54/studio/presentation | 4 +- .../CY8C6117BZI-F34/studio/presentation | 4 +- .../CY8C6117FDI-F02/studio/presentation | 4 +- .../CY8C6117WI-F34/studio/presentation | 4 +- .../CY8C6136BZI-F14/studio/presentation | 4 +- .../CY8C6136BZI-F34/studio/presentation | 4 +- .../CY8C6136FDI-F42/studio/presentation | 4 +- .../CY8C6136FTI-F42/studio/presentation | 4 +- .../CY8C6137BZI-F14/studio/presentation | 4 +- .../CY8C6137BZI-F34/studio/presentation | 4 +- .../CY8C6137BZI-F54/studio/presentation | 4 +- .../CY8C6137FDI-F02/studio/presentation | 4 +- .../CY8C6137WI-F54/studio/presentation | 4 +- .../CY8C6246BZI-D04/studio/presentation | 4 +- .../CY8C6247BFI-D54/studio/presentation | 4 +- .../CY8C6247BZI-AUD54/studio/presentation | 4 +- .../CY8C6247BZI-D34/studio/presentation | 4 +- .../CY8C6247BZI-D44/studio/presentation | 4 +- .../CY8C6247BZI-D54/studio/presentation | 4 +- .../CY8C6247FDI-D02/studio/presentation | 4 +- .../CY8C6247FDI-D32/studio/presentation | 4 +- .../CY8C6247FDI-D52/studio/presentation | 4 +- .../CY8C6247FTI-D52/studio/presentation | 4 +- .../CY8C6247WI-D54/studio/presentation | 4 +- .../CY8C6316BZI-BLF03/studio/presentation | 4 +- .../CY8C6316BZI-BLF04/studio/presentation | 4 +- .../CY8C6316BZI-BLF53/studio/presentation | 4 +- .../CY8C6316BZI-BLF54/studio/presentation | 4 +- .../CY8C6336BZI-BLD13/studio/presentation | 4 +- .../CY8C6336BZI-BLD14/studio/presentation | 4 +- .../CY8C6336BZI-BLF03/studio/presentation | 4 +- .../CY8C6336BZI-BLF04/studio/presentation | 4 +- .../CY8C6336BZI-BUD13/studio/presentation | 4 +- .../CY8C6336LQI-BLF02/studio/presentation | 4 +- .../CY8C6336LQI-BLF42/studio/presentation | 4 +- .../CY8C6337BZI-BLF13/studio/presentation | 4 +- .../CY8C6347BZI-BLD33/studio/presentation | 4 +- .../CY8C6347BZI-BLD34/studio/presentation | 4 +- .../CY8C6347BZI-BLD43/studio/presentation | 4 +- .../CY8C6347BZI-BLD44/studio/presentation | 4 +- .../CY8C6347BZI-BLD53/studio/presentation | 4 +- .../CY8C6347BZI-BLD54/studio/presentation | 4 +- .../CY8C6347BZI-BUD33/studio/presentation | 4 +- .../CY8C6347BZI-BUD43/studio/presentation | 4 +- .../CY8C6347BZI-BUD53/studio/presentation | 4 +- .../CY8C6347FMI-BLD13/studio/presentation | 4 +- .../CY8C6347FMI-BLD33/studio/presentation | 4 +- .../CY8C6347FMI-BLD43/studio/presentation | 4 +- .../CY8C6347FMI-BLD53/studio/presentation | 4 +- .../CY8C6347FMI-BUD13/studio/presentation | 4 +- .../CY8C6347FMI-BUD33/studio/presentation | 4 +- .../CY8C6347FMI-BUD43/studio/presentation | 4 +- .../CY8C6347FMI-BUD53/studio/presentation | 4 +- .../CY8C6347LQI-BLD52/studio/presentation | 4 +- .../CY8C637BZI-BLD74/studio/presentation | 4 +- .../CY8C637BZI-MD76/studio/presentation | 4 +- .../CY8C637FMI-BLD73/studio/presentation | 4 +- .../CY8C68237BZ-BLE/studio/presentation | 4 +- .../CY8C68237FM-BLE/studio/presentation | 4 +- .../CYB06447BZI-BLD53/studio/presentation | 4 +- .../CYB06447BZI-BLD54/studio/presentation | 4 +- .../CYB06447BZI-D54/studio/presentation | 4 +- .../CYBLE-416045-02/studio/presentation | 4 +- .../MXS40/PSoC6ABLE2/studio/clocks.cysem | 18 +- .../MXS40/PSoC6ABLE2/studio/clocks.cyvis | 2 +- .../studio/connectivity/mxprofile_v1.cydata | Bin 531 -> 531 bytes .../connectivity/mxs40srss_v1-power.cydata | Bin 531 -> 0 bytes .../studio/connectivity/mxs40srss_v1.cydata | Bin 2221 -> 2295 bytes .../studio/connectivity/mxsdhc_v1.cydata | Bin 531 -> 531 bytes .../studio/connectivity/mxtcpwm_v1.cydata | Bin 1711 -> 1743 bytes .../udd/devices/MXS40/studio/features.mk | 97 +- .../TARGET_PSOC6/psoc6pdl/udd/version.dat | 2 +- .../TARGET_PSOC6/psoc6pdl/udd/version.xml | 2 +- .../TARGET_PSOC6/psoc6pdl/version.xml | 2 +- 306 files changed, 19450 insertions(+), 3172 deletions(-) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/version.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dmac.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dw.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_impl.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_ezi2c.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_triggers.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_01.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_02.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_03.h rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_adc.c (98%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_analog_common.c (96%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_crc.c (97%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_crypto_common.c (98%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_dac.c (96%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dmac.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dw.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_ezi2c.c rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_flash.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_gpio.c (92%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_hwmgr.c (95%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_i2c.c (95%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_interconnect.c (97%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_lptimer.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_not_implemented.c (87%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_pwm.c rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_qspi.c (86%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_rtc.c (57%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_scb_common.c (98%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_sdhc.c (92%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_spi.c (97%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_system.c (81%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_tcpwm_common.c (85%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_timer.c (94%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_trng.c (97%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_uart.c (97%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_udb_sdio.c (94%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_usb_dev.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_utils.c (60%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/cyhal_wdt.c (95%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_01_116_bga_ble.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_01_116_bga_usb.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_01_124_bga.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_01_124_bga_sip.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_01_43_smt.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_01_68_qfn_ble.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_01_80_wlcsp.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_02_100_wlcsp.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_02_124_bga.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_02_128_tqfp.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_02_68_qfn.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_03_100_tqfp.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_03_49_wlcsp.c (99%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/{src => source}/pin_packages/cyhal_psoc6_03_68_qfn.c (99%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_01.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_02.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_03.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/version.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_04.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_tcpwm_v2.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6a256k.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/MXS40.revision create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/base/view.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/info.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/presentation create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/base/view.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/info.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/info.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/base/view.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/info.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/presentation create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1-power.cydata diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h index f4410a6641..83de7d44aa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h @@ -8,7 +8,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -69,7 +69,7 @@ typedef uint32_t cy_rslt_t; /** \cond INTERNAL */ /** Mask for the bit at position "x" */ -#define CY_BIT_MASK(x) ((1U << (x)) - 1U) +#define CY_BIT_MASK(x) ((1UL << (x)) - 1U) /** Bit position of the result type */ #define CY_RSLT_TYPE_POSITION (16U) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_utils.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_utils.h index ea4631b974..7a678c5eb7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_utils.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_utils.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/version.xml new file mode 100644 index 0000000000..2447c1093d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/version.xml @@ -0,0 +1 @@ +1.1.1.11109 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h index 41b68c6f54..e48ff7ac83 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h @@ -18,7 +18,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -35,7 +35,13 @@ *******************************************************************************/ /** -* \defgroup group_hal HAL Drivers +* \addtogroup group_hal HAL Drivers +* This section documents the drivers which form the stable API of the Cypress HAL. +* In order to remain portable across platforms and HAL versions, applications should +* rely only on functionality documented in this section. +* \{ +* \defgroup group_result Result Type +* \} */ #pragma once @@ -46,10 +52,12 @@ #include "cyhal_adc.h" #include "cyhal_crc.h" #include "cyhal_dac.h" +#include "cyhal_dma.h" #include "cyhal_flash.h" #include "cyhal_gpio.h" #include "cyhal_hwmgr.h" #include "cyhal_i2c.h" +#include "cyhal_ezi2c.h" #include "cyhal_interconnect.h" #include "cyhal_lptimer.h" #include "cyhal_pwm.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h index 78b836c590..43228c9e40 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,8 +29,21 @@ * \addtogroup group_hal_adc ADC (Analog to Digital Converter) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress ADC. +* High level interface for interacting with the analog to digital converter (ADC). * +* Each ADC instance supports one or more selectable channels, each +* of which can perform conversions on a different pin. +* See the device datasheet for details about which pins support ADC conversion. +* +* In order to use the ADC, first call cyhal_adc_init to initialize an ADC instance. +* Then call cyhal_adc_channel_init to initialize one or more channels associated with +* that instance. +* +* All channels are single-ended. +* The values returned by the read API are relative to the ADC's voltage range, which +* is device specific. +* +* \defgroup group_hal_adc_common Common * \defgroup group_hal_adc_functions ADC Functions * \defgroup group_hal_adc_channel_functions ADC Channel Functions */ @@ -59,12 +72,6 @@ extern "C" { /** No channels available */ #define CYHAL_ADC_RSLT_NO_CHANNELS (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_ADC, 3)) - -/** -* \addtogroup group_hal_adc_functions -* \{ -*/ - /** Initialize ADC peripheral * * @param[out] obj The adc object to initialize @@ -84,13 +91,6 @@ cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_d */ void cyhal_adc_free(cyhal_adc_t *obj); -/** \} group_hal_adc_functions */ - -/** -* \addtogroup group_hal_adc_channel_functions -* \{ -*/ - /** Initialize a single-ended ADC channel. * * Configures the pin used by ADC. @@ -116,8 +116,6 @@ void cyhal_adc_channel_free(cyhal_adc_channel_t *obj); */ uint16_t cyhal_adc_read_u16(const cyhal_adc_channel_t *obj); -/** \} group_hal_adc_channel_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_analog_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_analog_common.h index f6a0d4c491..6e3f78bb77 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_analog_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_analog_common.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,13 +29,13 @@ extern "C" { #endif -/** +/** * Initialize the programmable analog. This utilizes reference counting to avoid * repeatedly initializing the analog subsystem when multiple analog blocks are in use * */ void cyhal_analog_init(); -/** +/** * Uninitialize the programmable analog. This utilizes reference counting to avoid * disabling the analog subsystem until all blocks which require it have been freed. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h index f464fa0da9..747f839445 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h @@ -2,14 +2,14 @@ * \file cyhal_crc.h * * \brief -* Provides a high level interface for interacting with the Cypress CRC accelerator. +* Provides a high level interface for interacting with the Cypress CRC accelerator. * This interface abstracts out the chip specific details. If any chip specific * functionality is necessary, or performance is critical the low level functions * can be used directly. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,8 +29,15 @@ * \addtogroup group_hal_crc CRC (Cyclic Redundancy Check) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress CRC. +* High level interface for interacting with the cyclic redundancy check (CRC), which provides hardware +* accelerated CRC computations. +* The CRC APIs are structured to enable usage in situations where the entire input data +* set is not available in memory at one time. Therefore, each conversion consists of three steps: +* * A single call to cyhal_crc_start, to initialize data structures for this computation +* * One or more calls to cyhal_crc_compute, to provide chunks of data. +* * A single call to cyhal_crc_finish, to finalize the computation and retrieve the result. * +* Many of the algorithm parameters can be customized; see crc_algorithm_t for more details. */ #pragma once diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h index 3ab58d2ba0..0f86c27275 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h @@ -1,13 +1,13 @@ -/***************************************************************************//** +/***************************************************************************//** * \file cyhal_crc_impl.h * * Description: -* Provides a high level interface for interacting with the Cypress CRC accelerator. +* Provides a high level interface for interacting with the Cypress CRC accelerator. * This is a wrapper around the lower level PDL API. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h index df7bd3898d..b7f3524329 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h @@ -2,12 +2,12 @@ * \file cyhal_crypto_common.h * * Description: -* This file provides common defines, addresses, and functions required by drivers +* This file provides common defines, addresses, and functions required by drivers * using the Crypto block. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h index 494142e1de..9f1e5a12e3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,8 +29,13 @@ * \addtogroup group_hal_dac DAC (Digital to Analog Converter) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress DAC. +* High level interface for interacting with the digital to analog converter (DAC). * +* This block drives a pin with a firmware configurable voltage. See the device datasheet +* for details on which pins support DAC output. +* +* The cyhal_dac_write and cyhal_dac_read APIs are defined relative to the DAC's output +* voltage range, which is device dependent. */ #pragma once diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma.h new file mode 100644 index 0000000000..d89945d04b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma.h @@ -0,0 +1,185 @@ +/***************************************************************************//** +* \file cyhal_dma.h +* +* \brief +* Provides a high level interface for interacting with the Cypress DMA. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +<<<<<<< HEAD +* Copyright 2018-2019 Cypress Semiconductor Corporation +======= +* Copyright 2018-2020 Cypress Semiconductor Corporation +>>>>>>> Minor consistancy cleanup for HAL documentation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_dma DMA (Direct Memory Access) +* \ingroup group_hal +* \{ +* High level interface for interacting with the direct memory access (DMA). Allows the user to +* initialize and configure a DMA channel in order to trigger data transfers to +* and from memory and peripherals. The transfers occur independently of the CPU +* and are triggered in software. Multiple channels are available with +* user-selectable priority and transfer characteristics. +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** Invalid transfer width parameter error */ +#define CYHAL_DMA_RSLT_ERR_INVALID_TRANSFER_WIDTH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 0)) +/** Invalid parameter error */ +#define CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 1)) +/** Invalid priority parameter error */ +#define CYHAL_DMA_RSLT_ERR_INVALID_PRIORITY (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 2)) +/** Invalid src or dst addr alignment error */ +#define CYHAL_DMA_RSLT_ERR_INVALID_ALIGNMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 3)) +/** Invalid burst_size paramenter error */ +#define CYHAL_DMA_RSLT_ERR_INVALID_BURST_SIZE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 4)) +/** Channel busy error */ +#define CYHAL_DMA_RSLT_ERR_CHANNEL_BUSY (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 5)) +/** Transfer has already been started warning */ +#define CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED (CY_RSLT_CREATE(CY_RSLT_TYPE_WARNING, CYHAL_RSLT_MODULE_DMA, 6)) +/** Unsupported hardware error */ +#define CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE (CY_RSLT_CREATE(CY_RSLT_TYPE_FATAL, CYHAL_RSLT_MODULE_DMA, 7)) + +/** Direction for DMA transfers. */ +typedef enum +{ + CYHAL_DMA_DIRECTION_MEM2MEM, //!< Memory to memory + CYHAL_DMA_DIRECTION_MEM2PERIPH, //!< Memory to peripheral + CYHAL_DMA_DIRECTION_PERIPH2MEM, //!< Peripheral to memory + CYHAL_DMA_DIRECTION_PERIPH2PERIPH, //!< Peripheral to peripheral +} cyhal_dma_direction_t; + +/** Flags enum of DMA events. Multiple events can be enabled. */ +typedef enum +{ + CYHAL_DMA_NO_INTR = 0, //!< No interrupt + CYHAL_DMA_TRANSFER_COMPLETE = 1 << 0, //!< Indicates that a burst or full transfer has completed + CYHAL_DMA_SRC_BUS_ERROR = 1 << 1, //!< Indicates that there is a source bus error + CYHAL_DMA_DST_BUS_ERROR = 1 << 2, //!< Indicates that there is a destination bus error + CYHAL_DMA_SRC_MISAL = 1 << 3, //!< Indicates that the source address is not aligned + CYHAL_DMA_DST_MISAL = 1 << 4, //!< Indicates that the destination address is not aligned + CYHAL_DMA_CURR_PTR_NULL = 1 << 5, //!< Indicates that the current descriptor pointer is null + CYHAL_DMA_ACTIVE_CH_DISABLED = 1 << 6, //!< Indicates that the active channel is disabled + CYHAL_DMA_DESCR_BUS_ERROR = 1 << 7, //!< Indicates that there has been a descriptor bus error +} cyhal_dma_event_t; + +/** If burst_size is used, selects whether a single trigger of the channel + * transfers a single burst of burst_size or a full transfer of size length + * (that is, every burst is triggered). This will also select when a trigger + * complete event will occur; after each burst or after the full transfer */ +typedef enum +{ + CYHAL_DMA_TRANSFER_BURST, //!< A single burst is triggered and a transfer completion event will occur after the burst + CYHAL_DMA_TRANSFER_FULL, //!< All bursts are triggered and a single transfer completion event will occur at the end of all of them +} cyhal_dma_transfer_action_t; + +/** \brief Configuration of a DMA channel. When configuring address, + * increments, and transfer width keep in mind your hardware may have more + * stringent address and data alignment requirements. */ +typedef struct +{ + uint32_t src_addr; //!< Source address + int16_t src_increment; //!< Source address auto increment amount in multiples of transfer_width + uint32_t dst_addr; //!< Destination address + int16_t dst_increment; //!< Destination address auto increment amount in multiples of transfer_width + uint8_t transfer_width; //!< Transfer width in bits. Valid values are: 8, 16, or 32 + uint32_t length; //!< Number of elements to be transferred in total + uint32_t burst_size; //!< Number of elements to be transferred per trigger. If set to 0 every element is transferred, otherwise burst_size must evenly divide length. + cyhal_dma_transfer_action_t action; //!< Sets the behavior of the channel when triggered (using start_transfer). Ignored if burst_size is not configured. +} cyhal_dma_cfg_t; + +/** Event handler for DMA interrupts */ +typedef void (*cyhal_dma_event_callback_t)(void *callback_arg, cyhal_dma_event_t event); + +/** Initialize the DMA peripheral. + * + * @param[out] obj The DMA object to initialize + * @param[in] priority The priority of this DMA operation relative to others. The number of priority levels which are supported is hardware dependent. All implementations define a CYHAL_DMA_PRIORITY_DEFAULT constant which is always valid. If supported, implementations will also define CYHAL_DMA_PRIORITY_HIGH, CYHAL_DMA_PRIORITY_MEDIUM, and CYHAL_DMA_PRIORITY_LOW. The behavior of any other value is implementation defined. See the implementation-specific DMA documentation for more details. + * @param[in] direction The direction memory is copied + * @return The status of the init request + */ +cy_rslt_t cyhal_dma_init(cyhal_dma_t *obj, uint8_t priority, cyhal_dma_direction_t direction); + +/** Free the DMA object. Freeing a DMA object while a transfer is in + progress (see @ref cyhal_dma_is_busy) is invalid. + * + * @param[in,out] obj The DMA object + */ +void cyhal_dma_free(cyhal_dma_t *obj); + +/** Setup a DMA descriptor for specified resource + * + * @param[in] obj The DMA object + * @param[in] cfg Configuration parameters for the transfer + * @return The status of the configure request + */ +cy_rslt_t cyhal_dma_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg); + +/** Initiates DMA channel transfer for specified DMA object + * + * @param[in] obj The DMA object + * @return The status of the start_transfer request + */ +cy_rslt_t cyhal_dma_start_transfer(cyhal_dma_t *obj); + +/** Checks whether a transfer is pending or running on the DMA channel + * + * @param[in] obj The DMA object + * @return True if DMA channel is busy + */ +bool cyhal_dma_is_busy(cyhal_dma_t *obj); + +/** The DMA callback handler registration + * + * @param[in] obj The DMA object + * @param[in] callback The callback handler which will be invoked when an event triggers + * @param[in] callback_arg Generic argument that will be provided to the callback when called + */ +void cyhal_dma_register_callback(cyhal_dma_t *obj, cyhal_dma_event_callback_t callback, void *callback_arg); + +/** Configure DMA event enablement. + * + * @param[in] obj The DMA object + * @param[in] event The DMA event type + * @param[in] intr_priority The priority for NVIC interrupt events. The priority from the most recent call will take precedence, i.e all events will have the same priority. + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_dma_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intr_priority, bool enable); + +#if defined(__cplusplus) +} +#endif + +#ifdef CYHAL_DMA_IMPL_HEADER +#include CYHAL_DMA_IMPL_HEADER +#endif /* CYHAL_DMA_IMPL_HEADER */ + +/** \} group_hal_dma */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dmac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dmac.h new file mode 100644 index 0000000000..87658a7255 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dmac.h @@ -0,0 +1,94 @@ +/***************************************************************************//** +* \file cyhal_dma_dmac.h +* +* \brief +* Defines a high level interface for interacting with the Cypress DMAC. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cyhal_dma.h" + +/** + * \addtogroup group_hal_psoc6_dma_dmac DMAC (Direct Memory Access Controller) + * \ingroup group_hal_psoc6_dma + * \{ + * Implementation specific interface for using the DMAC DMA peripheral + */ + +#pragma once + +#ifdef CY_IP_M4CPUSS_DMAC + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** Initialize the DMAC peripheral + * + * @param[out] obj The DMA object to initialize + * @param[in] priority The priority of this DMA operation relative to others. Values must be between 0-3 with 0 being the highest priority. + * @return The status of the init request + */ +cy_rslt_t cyhal_dma_init_dmac(cyhal_dma_t *obj, uint8_t priority); + +/** Frees the DMAC specific object + * + * @param[in,out] obj The DMA object + */ +void cyhal_dma_free_dmac(cyhal_dma_t *obj); + +/** Setup a DMAC descriptor for the dma resource + * + * @param[in] obj The DMA object + * @param[in] cfg Configuration parameters for the transfer + * @return The status of the configure request + */ +cy_rslt_t cyhal_dma_configure_dmac(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg); + +/** Start a DMAC transfer + * + * Initiates DMA channel transfer for specified DMA object + * @param[in] obj The DMA object + * @return The status of the start_transfer request + */ +cy_rslt_t cyhal_dma_start_transfer_dmac(cyhal_dma_t *obj); + +/** Configure DMAC event enablement. + * + * @param[in] obj The DMA object + * @param[in] event The DMA event type + * @param[in] intrPriority The priority for NVIC interrupt events. The priority from the most recent call will take precedence, i.e all events will have the same priority. + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_dma_enable_event_dmac(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable); + +/** Checks whether a transfer is pending or running on the DMA channel + * + * @param[in] obj The DMA object + * @return True if DMA channel is busy + */ +bool cyhal_dma_is_busy_dmac(cyhal_dma_t *obj); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* CY_IP_M4CPUSS_DMAC */ + +/** \} group_hal_psoc6_dma_dmac */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dw.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dw.h new file mode 100644 index 0000000000..dbda5094be --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dw.h @@ -0,0 +1,94 @@ +/***************************************************************************//** +* \file cyhal_dma_dw.h +* +* \brief +* Defines a high level interface for interacting with the Cypress Datawire DMA. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cyhal_dma.h" + +/** + * \addtogroup group_hal_psoc6_dma_dw DW (Datawire) + * \ingroup group_hal_psoc6_dma + * \{ + * Implementation specific interface for using the Datawire DMA peripheral + */ + +#pragma once + +#ifdef CY_IP_M4CPUSS_DMA + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** Initialize the Datawire peripheral. + * + * @param[out] obj The DMA object to initialize + * @param[in] priority The priority of this DMA operation relative to others. Values must be between 0-3 with 0 being the highest priority. + * @return The status of the init request + */ +cy_rslt_t cyhal_dma_init_dw(cyhal_dma_t *obj, uint8_t priority); + +/** Frees the Datawire specific DMA object + * + * @param[in,out] obj The DMA object + */ +void cyhal_dma_free_dw(cyhal_dma_t *obj); + +/** Setup a Datawire descriptor for the dma resource + * + * @param[in] obj The DMA object + * @param[in] cfg Configuration prameters for the transfer + * @return The status of the configure request + */ +cy_rslt_t cyhal_dma_configure_dw(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg); + +/** Start a Datawire transfer + * + * Initiates DMA channel transfer for specified DMA object + * @param[in] obj The DMA object + * @return The status of the start_transfer request + */ +cy_rslt_t cyhal_dma_start_transfer_dw(cyhal_dma_t *obj); + +/** Configure Datawire event enablement. + * + * @param[in] obj The DMA object + * @param[in] event The DMA event type + * @param[in] intrPriority The priority for NVIC interrupt events. The priority from the most recent call will take precedence, i.e all events will have the same priority. + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_dma_enable_event_dw(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable); + +/** Checks whether a transfer is pending or running on the DMA channel + * + * @param[in] obj The DMA object + * @return True if DMA channel is busy + */ +bool cyhal_dma_is_busy_dw(cyhal_dma_t *obj); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* CY_IP_M4CPUSS_DMA */ + +/** \} group_hal_psoc6_dma_dw */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_impl.h new file mode 100644 index 0000000000..672d0ce6cc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_impl.h @@ -0,0 +1,73 @@ +/***************************************************************************//** +* \file cyhal_dma_impl.h +* +* \brief +* Implementation details of Cypress Datawire/DMAC DMA. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_hal_psoc6_dma DMA (Direct Memory Access) + * \ingroup group_hal_psoc6 + * \{ + * DW (DataWire) is one of two DMA hardware implementations for PSOC6. DW is + * designed for low latency memory to peripheral or peripheral to memory + * transfers but can also perform memory to memory transfers and peripheral to + * peripheral transfers. + * + * DMAC (Direct Memory Access Controller) is the second of two DMA hardware + * implementations for PSOC6. DMAC is designed with high memory bandwidth for + * large memory to memory transfers but can perform peripheral to memory, + * memory to peripheral, and peripheral to peripheral transfers. + * + * Which DMA type is used is dependent on the exact hardware and number of DMA + * channels already in use. This implementation will attempt to use DMAC first + * for memory to memory transfers and Datawire otherwise but either type may be + * used. */ + +/** Default DMA channel priority */ +#define CYHAL_DMA_PRIORITY_DEFAULT CYHAL_DMA_PRIORITY_LOW +/** High DMA channel priority */ +#define CYHAL_DMA_PRIORITY_HIGH 0 +/** Medium DMA channel priority */ +#define CYHAL_DMA_PRIORITY_MEDIUM 1 +/** Low DMA channel priority */ +#define CYHAL_DMA_PRIORITY_LOW 3 + +/** \cond INTERNAL */ +/** Hal-Triggers uses bit 8 to denote a one to one trigger, whereas, the PDL + * SwTrigger function uses bit 5 to denote a one to one trigger. */ +#define HAL_TRIGGERS_1TO1_MASK (0x80) +#define PDL_TRIGGERS_1TO1_MASK (0x10) +/** \endcond */ + +/** \} group_hal_psoc6_dma */ + +#if defined(__cplusplus) +} +#endif + +#endif /* defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_ezi2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_ezi2c.h new file mode 100644 index 0000000000..b4aea5d377 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_ezi2c.h @@ -0,0 +1,186 @@ +/***************************************************************************//** +* \file cyhal_ezi2c.h +* +* \brief +* Provides a high level interface for interacting with the Cypress EZI2C. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/****************************************************************************** +* Provides a high level Cypress EZI2C Slave interface for interacting with +* an I2C master. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +* Cypress EZI2C emulates a common I2C EEPROM interface that acts like dual-port +* memory between the external master and your code. Once the interface is setup, +* your code can read/write freely from the specified buffer(s). +* All I2C transactions to/from the master are handled automatically. +*******************************************************************************/ + +/** +* \addtogroup group_hal_ezi2c EZI2C (Inter-Integrated Circuit) +* \ingroup group_hal +* \{ +* High level interface for interacting with the Cypress EZ Inter-Integrated Circuit (EZI2C). +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" +#include "cyhal_modules.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** The requested resource type is invalid */ +#define CYHAL_EZI2C_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_EZI2C, 0)) +/** Can not reach desired data rate */ +#define CYHAL_EZI2C_RSLT_ERR_CAN_NOT_REACH_DR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_EZI2C, 1)) +/** Number of addresses is not valid */ +#define CYHAL_EZI2C_RSLT_ERR_NUM_ADDR_NOT_VALID (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_EZI2C, 2)) +/** Number of addresses is not valid */ +#define CYHAL_EZI2C_RSLT_ERR_CHECK_USER_CONFIG (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_EZI2C, 3)) + +/** Size of Sub-Address */ +typedef enum +{ + CYHAL_EZI2C_SUB_ADDR8_BITS, /**< Sub-address is 8 bits */ + CYHAL_EZI2C_SUB_ADDR16_BITS /**< Sub-address is 16 bits */ +} cyhal_ezi2c_sub_addr_size_t; + +/** Size of Sub-Address */ +typedef enum +{ + CYHAL_EZI2C_DATA_RATE_100KHZ = 100000, + CYHAL_EZI2C_DATA_RATE_400KHZ = 400000, + CYHAL_EZI2C_DATA_RATE_1MHZ = 1000000 +} cyhal_ezi2c_data_rate_t; + +/** Return codes of ezi2c */ +typedef enum +{ + /** Each EZI2C slave status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status */ + CYHAL_EZI2C_STATUS_OK = 0x0UL, /**< Operation completed successfully */ + CYHAL_EZI2C_STATUS_READ1 = 0x01UL, /**< The Read transfer intended for the primary slave address is complete */ + CYHAL_EZI2C_STATUS_WRITE1 = 0x02UL, /**< The Write transfer intended for the primary slave address is complete */ + CYHAL_EZI2C_STATUS_READ2 = 0x04UL, /**< The Read transfer intended for the secondary slave address is complete */ + CYHAL_EZI2C_STATUS_WRITE2 = 0x08UL, /**< The Write transfer intended for the secondary slave address is complete */ + CYHAL_EZI2C_STATUS_BUSY = 0x10UL, /**< A transfer intended for the primary address or secondary address is in progress */ + CYHAL_EZI2C_STATUS_ERR = 0x20UL /**< An error occurred during a transfer intended for the primary or secondary slave address */ + +} cyhal_ezi2c_status_t; + +/** Enum to enable/disable/report interrupt cause flags. When an event is triggered + * the status can be obtained by calling \ref cyhal_ezi2c_get_activity_status. + * \note This is a placeholder for now. It may be extended in the future. + */ +typedef enum +{ + CYHAL_EZI2C_EVENT_NONE = 0, /* No event */ +} cyhal_ezi2c_event_t; + +/** Handler for I2C events */ +typedef void (*cyhal_ezi2c_event_callback_t)(void *callback_arg, cyhal_ezi2c_event_t event); + +/** Initial EZI2C sub configuration */ +typedef struct +{ + /** The 7-bit right justified primary slave address */ + uint8_t slave_address; + /** A pointer to the data buffer for the primary/secondary slave address */ + uint8_t *buf; + /** The size of the buffer assigned to the primary/secondary slave address */ + uint32_t buf_size; + /** The Read/Write boundary within the buffer assigned to the primary/secondary slave address. + * This specifies the number of data bytes from the beginning of the buffer with + * read and write access for the master. Data bytes at this value or greater are read + * only by the master */ + uint32_t buf_rw_boundary; +} cyhal_ezi2c_slave_cfg_t; + +/** Initial EZI2C configuration */ +typedef struct +{ + /** Number of addresses (one or two). If set "true" - use two addresses otherwise ("false") one */ + bool two_addresses; + /** When set, the slave will wake the device from Deep Sleep on an address match */ + bool enable_wake_from_sleep; + /** Maximum frequency that the I2C Slave bus runs at. Supports standard data rates of 100/400/1000 kbps */ + cyhal_ezi2c_data_rate_t data_rate; + /** Refer to cyhal_ezi2c_slave_cfg_t for details. This config structure is mandatory. */ + cyhal_ezi2c_slave_cfg_t slave1_cfg; + /** Refer to cyhal_ezi2c_slave_cfg_t for details. This config structure is optional. */ + /** Set it if user want to use dual-port addressing otherwise leave blank */ + cyhal_ezi2c_slave_cfg_t slave2_cfg; + /** The size of the sub-address, can either be 8 or 16 bits */ + cyhal_ezi2c_sub_addr_size_t sub_address_size; +} cyhal_ezi2c_cfg_t; + +/** Initialize the EZI2C (slave), and configures its specifieds pins and clock. + * + * @param[out] obj The I2C object + * @param[in] sda The sda pin + * @param[in] scl The scl pin + * @param[in] clk The clock to use can be shared, if NULL a new clock will be allocated + * @param[in] cfg The ezi2c configuration (refer to cyhal_ezi2c_cfg_t for details) + * @return The status of the init request + */ +cy_rslt_t cyhal_ezi2c_init(cyhal_ezi2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, const cyhal_clock_divider_t *clk, const cyhal_ezi2c_cfg_t *cfg); + +/** Deinitialize the ezi2c object + * + * @param[in,out] obj The ezi2c object + */ +void cyhal_ezi2c_free(cyhal_ezi2c_t *obj); + +/** + * EZI2C slave get activity status + * This function returns a non-zero value if an I2C Read or Write + * cycle has occurred since the last time this function was called. + * + * @param[in] obj The EZI2C object + * + * @return The status of the EZI2C (see cyhal_ezi2c_status_t for details) + */ +cyhal_ezi2c_status_t cyhal_ezi2c_get_activity_status(cyhal_ezi2c_t *obj); + +/** The EZI2C event callback handler registration + * + * @param[in] obj The EZI2C object + * @param[in] callback The callback handler which will be invoked when an event triggers + * @param[in] callback_arg Generic argument that will be provided to the callback when called + */ +void cyhal_ezi2c_register_callback(cyhal_ezi2c_t *obj, cyhal_ezi2c_event_callback_t callback, void *callback_arg); + + + +#if defined(__cplusplus) +} +#endif + +/** \} group_hal_ezi2c */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h index 9eefbed514..e5d3f4a24f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,11 @@ * \addtogroup group_hal_flash Flash * \ingroup group_hal * \{ -* Flash HAL high-level description +* High level interface for interacting with internal flash memory. +* +* This driver allows data to be read from and written to flash. It also +* provides the ability to obtain information about the address and +* characteristics of the flash block(s) contained on the device. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h index eea6697e24..ecd038fc1d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,54 @@ * \addtogroup group_hal_gpio GPIO (General Purpose Input Output) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress GPIO. +* High level interface for configuring and interacting with general purpose input/outputs (GPIO). +* +* The GPIO driver provides functions to configure and initialize GPIO, and to read and write data to the pin. +* The driver also supports interrupt generation on GPIO signals with rising, falling or both edges. +* +* \note The APIs in this driver need not be used if a GPIO is to be used as an input or output of peripherals like I2C or PWM. +* The respective peripheral's driver will utilize the GPIO interface to configure and initialize its GPIO pins. +* +* \section subsection_gpio_features Features +* * Configurable GPIO pin direction - \ref cyhal_gpio_direction_t +* * Configurable GPIO pin drive modes - \ref cyhal_gpio_drive_mode_t +* * Configurable analog and digital characteristics +* * Configurable edge-triggered interrupts and callback assignment on GPIO events - \ref cyhal_gpio_event_t +* +* \section subsection_gpio_quickstart Quick Start +* \ref cyhal_gpio_init can be used for a simple GPIO initialization by providing the pin number (pin), pin direction (direction), +* pin drive mode (drive_mode) and the initial value on the pin (init_val). +* +* \section subsection_gpio_sample_snippets Code Snippets +* +* \subsection subsection_gpio_snippet_1 Snippet 1: Reading value from GPIO +* The following snippet initializes GPIO pin \ref P0_0 as an input with high impedance digital drive mode and initial value = false (low). A value is read +* from the pin and stored to a uint8_t variable (read_val). + +* \snippet gpio.c snippet_cyhal_gpio_read + +* \subsection subsection_gpio_snippet_2 Snippet 2: Writing value to a GPIO +* The following snippet initializes GPIO pin \ref P0_0 as an output pin with strong drive mode and initial value = false (low). +* A value = true (high) is written to the output driver. + +* \snippet gpio.c snippet_cyhal_gpio_write + +* \subsection subsection_gpio_snippet_3 Snippet 3: Reconfiguring a GPIO +* The following snippet shows how to reconfigure a GPIO pin during run-time using the firmware. The GPIO pin \ref P0_0 +* is first initialized as an output pin with strong drive mode. The pin is then reconfigured as an input with high impedance digital drive mode. +* \note \ref cyhal_gpio_configure only changes the direction and the drive_mode +* of the pin. Previously set pin value is retained. +* +* \snippet gpio.c snippet_cyhal_gpio_reconfigure + +* \subsection subsection_gpio_snippet_4 Snippet 4: Interrupts on GPIO events +* GPIO events can be mapped to an interrupt and assigned to a callback function. The callback function needs to be first registered and +* then the event needs to be enabled. +** The following snippet initializes GPIO pin \ref P0_0 as an input pin. It registers a callback function and enables detection +* of a falling edge event to trigger the callback. +* \note If no argument needs to be passed to the callback function then a NULL can be passed during registering.
+* +* \snippet gpio.c snippet_cyhal_gpio_interrupt */ #pragma once @@ -43,6 +90,7 @@ extern "C" { #endif /* __cplusplus */ + /******************************************************************************* * Defines *******************************************************************************/ @@ -70,8 +118,14 @@ typedef enum { } cyhal_gpio_direction_t; /** Pin drive mode */ + +/** \note When the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_PULL_NONE , + * it is set to CYHAL_GPIO_DRIVE_STRONG if the direction + * of the pin is CYHAL_GPIO_DIR_OUTPUT or CYHAL_GPIO_DIR_BIDIRECTIONAL. + * If not, the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_NONE. + */ typedef enum { - CYHAL_GPIO_DRIVE_NONE, /**< No drive; Hi-Z */ + CYHAL_GPIO_DRIVE_NONE, /**< Digital Hi-Z */ CYHAL_GPIO_DRIVE_ANALOG, /**< Analog Hi-Z */ CYHAL_GPIO_DRIVE_PULLUP, /**< Pull-up resistor */ CYHAL_GPIO_DRIVE_PULLDOWN, /**< Pull-down resistor */ @@ -89,16 +143,17 @@ typedef void (*cyhal_gpio_event_callback_t)(void *callback_arg, cyhal_gpio_event * Functions *******************************************************************************/ -/** Initialize the GPIO pin +/** Initialize the GPIO pin
+ * See \ref subsection_gpio_snippet_1. * - * @param[in] pin The GPIO pin to initialize - * @param[in] direction The pin direction - * @param[in] drvMode The pin drive mode - * @param[in] initVal Initial value on the pin + * @param[in] pin The GPIO pin to initialize + * @param[in] direction The pin direction + * @param[in] drive_mode The pin drive mode + * @param[in] init_val Initial value on the pin * * @return The status of the init request */ -cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode, bool initVal); +cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drive_mode, bool init_val); /** Uninitialize the gpio peripheral and the cyhal_gpio_t object * @@ -106,7 +161,8 @@ cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cy */ void cyhal_gpio_free(cyhal_gpio_t pin); -/** Configure the GPIO pin +/** Configure the GPIO pin
+ * See \ref subsection_gpio_snippet_3. * * @param[in] pin The GPIO pin * @param[in] direction The pin direction @@ -116,27 +172,30 @@ void cyhal_gpio_free(cyhal_gpio_t pin); */ cy_rslt_t cyhal_gpio_configure(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode); -/** Set the output value for the pin. This only works for output & in_out pins. +/** Set the output value for the pin. This only works for output & in_out pins.
+ * See \ref subsection_gpio_snippet_2. * * @param[in] pin The GPIO object * @param[in] value The value to be set (high = true, low = false) */ void cyhal_gpio_write(cyhal_gpio_t pin, bool value); -/** Read the input value. This only works for input & in_out pins. +/** Read the input value. This only works for \ref CYHAL_GPIO_DIR_INPUT & \ref CYHAL_GPIO_DIR_BIDIRECTIONAL pins.
+ * See \ref subsection_gpio_snippet_1. * * @param[in] pin The GPIO object * @return The value of the IO (true = high, false = low) */ bool cyhal_gpio_read(cyhal_gpio_t pin); -/** Toggle the output value - * +/** Toggle the output value
+ * See \ref subsection_gpio_snippet_4. * @param[in] pin The GPIO object */ void cyhal_gpio_toggle(cyhal_gpio_t pin); -/** Register/clear a callback handler for pin events +/** Register/clear a callback handler for pin events
+ * See \ref subsection_gpio_snippet_4. * * @param[in] pin The pin number * @param[in] callback The function to call when the specified event happens. Pass NULL to unregister the handler. @@ -144,17 +203,18 @@ void cyhal_gpio_toggle(cyhal_gpio_t pin); */ void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t callback, void *callback_arg); -/** Enable or Disable the specified GPIO event +/** Enable or Disable the specified GPIO event
+ * See \ref subsection_gpio_snippet_4. * * @param[in] pin The GPIO object * @param[in] event The GPIO event - * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] intr_priority The priority for NVIC interrupt events * @param[in] enable True to turn on interrupts, False to turn off */ -void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intrPriority, bool enable); +void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable); /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macro. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ /** \cond INTERNAL */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio_impl.h index 5878cf9b2b..5898c715b6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio_impl.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h index f5da12987f..74733c9aa5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,7 +23,7 @@ *******************************************************************************/ /** -* \addtogroup group_hal_psoc6_hw_types +* \addtogroup group_hal_psoc6_hw_types * \ingroup group_hal_psoc6 * \{ */ @@ -46,6 +46,7 @@ typedef enum CYHAL_RSC_CRYPTO, /*!< Crypto hardware accelerator */ CYHAL_RSC_DAC, /*!< Digital to analog converter */ CYHAL_RSC_DMA, /*!< DMA controller */ + CYHAL_RSC_DW, /*!< Datawire DMA controller */ CYHAL_RSC_GPIO, /*!< General purpose I/O pin */ CYHAL_RSC_I2S, /*!< I2S communications block */ CYHAL_RSC_LCD, /*!< Segment LCD controller */ @@ -63,8 +64,8 @@ typedef enum CYHAL_RSC_INVALID, /*!< Placeholder for invalid type */ } cyhal_resource_t; -/** - * @brief Represents a particular instance of a resource on the chip +/** + * @brief Represents a particular instance of a resource on the chip */ typedef struct { @@ -74,7 +75,7 @@ typedef struct * The channel number, if the resource type defines multiple channels * per block instance. Otherwise, 0 */ uint8_t channel_num; -} cyhal_resource_inst_t; +} cyhal_resource_inst_t; #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h index 5548ffc6b8..dd7bc51ada 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,10 +23,18 @@ *******************************************************************************/ /** -* \addtogroup group_hal_psoc6_hw_types Implementation-defined types -* \ingroup group_hal_psoc6 +* \addtogroup group_hal_psoc6 PSoC 6 Implementation Specific * \{ -* Aliases for types which are part of the public HAL interface but whose representations are +* This section provides details about the PSoC 6 implementation of the Cypress HAL. +* All information within this section is platform specific and is provided for reference. +* Portable application code should depend only on the APIs and types which are documented +* in the @ref group_hal section. +*/ + +/** +* \addtogroup group_hal_psoc6_hw_types PSoC6 Specific Hardware Types +* \{ +* Aliases for types which are part of the public HAL interface but whose representations * need to vary per HAL implementation */ @@ -35,6 +43,7 @@ #include "cy_pdl.h" #include "cyhal_hw_resources.h" #include "cyhal_pin_package.h" +#include "cyhal_triggers.h" #include #if defined(CYHAL_UDB_SDIO) @@ -47,7 +56,9 @@ extern "C" { #ifndef CYHAL_ISR_PRIORITY_DEFAULT -/** Default priority for interrupts */ +/** Priority that is applied by default to all drivers when initalized. Priorities can be + * overridden on each driver as part of enabling events. + */ #define CYHAL_ISR_PRIORITY_DEFAULT (7) #endif @@ -56,6 +67,7 @@ extern "C" { */ #define CYHAL_CRC_IMPL_HEADER "cyhal_crc_impl.h" //!< Implementation specific header for CRC +#define CYHAL_DMA_IMPL_HEADER "cyhal_dma_impl.h" //!< Implementation specific header for DMA #define CYHAL_GPIO_IMPL_HEADER "cyhal_gpio_impl.h" //!< Implementation specific header for GPIO #define CYHAL_PWM_IMPL_HEADER "cyhal_pwm_impl.h" //!< Implementation specific header for PWM #define CYHAL_SYSTEM_IMPL_HEADER "cyhal_system_impl.h" //!< Implementation specific header for System @@ -67,7 +79,6 @@ extern "C" { /** */ typedef uint32_t cyhal_source_t; //!< Routable signal source -typedef uint32_t cyhal_dest_t; //!< Routable signal destination /** Callbacks for Sleep and Deepsleep APIs */ #define cyhal_system_callback_t cy_stc_syspm_callback_t @@ -98,13 +109,6 @@ typedef struct { void* callback_arg; } cyhal_event_callback_data_t; -/** -* \addtogroup group_hal_psoc6_hw_types_handle Instance Handles -* \{ -* Structs which retain data which needs to persist across HAL API calls. From the perspective of the -* generic HAL interface, these are opaque; the contents are specific to this implementation. -*/ - /** @brief ADC object */ typedef struct { #ifdef CY_IP_MXS40PASS_SAR @@ -131,16 +135,6 @@ typedef struct { #endif } cyhal_adc_channel_t; -/** @brief Comparator object */ -typedef struct { -#if defined(CY_IP_MXLPCOMP_INSTANCES) || defined(PASS_NR_CTBS) - /* TODO: define */ - void * TODO_define; -#else - void *empty; -#endif -} cyhal_comp_t; - /** @brief CRC object */ typedef struct { #if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT) @@ -163,8 +157,37 @@ typedef struct { /** @brief DMA object */ typedef struct { -#if defined(CY_IP_M4CPUSS_DMAC_INSTANCES) || defined(CY_IP_M4CPUSS_DMA_INSTANCES) - cyhal_resource_inst_t resource; +#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) + cyhal_resource_inst_t resource; + union + { +#ifdef CY_IP_M4CPUSS_DMA + cy_stc_dma_channel_config_t dw; +#endif +#ifdef CY_IP_M4CPUSS_DMAC + cy_stc_dmac_channel_config_t dmac; +#endif + } channel_config; + union + { +#ifdef CY_IP_M4CPUSS_DMA + cy_stc_dma_descriptor_config_t dw; +#endif +#ifdef CY_IP_M4CPUSS_DMAC + cy_stc_dmac_descriptor_config_t dmac; +#endif + } descriptor_config; + union + { +#ifdef CY_IP_M4CPUSS_DMA + cy_stc_dma_descriptor_t dw; +#endif +#ifdef CY_IP_M4CPUSS_DMAC + cy_stc_dmac_descriptor_t dmac; +#endif + } descriptor; + uint32_t irq_cause; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif @@ -199,53 +222,41 @@ typedef struct { #endif } cyhal_i2c_t; -/** @brief I2S object */ +/** @brief EZI2C object */ typedef struct { -#ifdef CY_IP_MXAUDIOSS_INSTANCES - /* TODO: define */ - void * TODO_define; +#ifdef CY_IP_MXSCB + CySCB_Type* base; + cyhal_resource_inst_t resource; + cyhal_gpio_t pin_sda; + cyhal_gpio_t pin_scl; + cyhal_clock_divider_t clock; + bool is_shared_clock; + cy_stc_scb_ezi2c_context_t context; + uint32_t irq_cause; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif -} cyhal_i2s_t; +} cyhal_ezi2c_t; /** @brief LPTIMER object */ typedef struct { #ifdef CY_IP_MXS40SRSS_MCWDT_INSTANCES - MCWDT_STRUCT_Type *base; - cyhal_resource_inst_t resource; - cyhal_event_callback_data_t callback_data; + MCWDT_STRUCT_Type *base; + cyhal_resource_inst_t resource; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif } cyhal_lptimer_t; -/** @brief OpAmp object */ -typedef struct { -#ifdef PASS_NR_CTBS - /* TODO: define */ - void * TODO_define; -#else - void *empty; -#endif -} cyhal_opamp_t; - -/** @brief PDM-PCM object */ -typedef struct { -#ifdef CY_IP_MXAUDIOSS_INSTANCES - /* TODO: define */ - void * TODO_define; -#else - void *empty; -#endif -} cyhal_pdm_pcm_t; - /** @brief PWM object */ typedef struct { #ifdef CY_IP_MXTCPWM TCPWM_Type* base; cyhal_resource_inst_t resource; cyhal_gpio_t pin; + cyhal_gpio_t pin_compl; cyhal_clock_divider_t clock; uint32_t clock_hz; bool dedicated_clock; @@ -280,12 +291,18 @@ typedef struct { #if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT) CRYPTO_Type* base; cyhal_resource_inst_t resource; +#else + void *empty; #endif } cyhal_trng_t; /** @brief RTC object */ typedef struct { - uint8_t placeholder; +#ifdef CY_IP_MXS40SRSS_RTC + cy_stc_rtc_dst_t dst; +#else + void *empty; +#endif } cyhal_rtc_t; /** @brief SDHC object */ @@ -457,10 +474,9 @@ typedef struct { uint8_t placeholder; } cyhal_wdt_t; -/** \} group_hal_psoc6_hw_types_handles */ - #if defined(__cplusplus) } #endif /* __cplusplus */ /** \} group_hal_psoc6_hw_types */ +/** \} group_hal_psoc6 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h index 35f076cf78..62c5277c0c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h @@ -8,7 +8,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,7 +28,14 @@ * \addtogroup group_hal_hwmgr HWMGR (Hardware Manager) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress Hardware Manager. +* High level interface for interacting with the Hardware Manager. +* +* This provides two related functions: +* * Allows HAL drivers (or application firmware) to mark specific hardware blocks +* as consumed, so that other firmware will not accidentally try to use the block +* for a conflicting purpose. +* * For resources which are interchangeable, such as clock dividers, provides allocation +* and reservation of an available instance (if one exists). */ #pragma once @@ -80,13 +87,6 @@ void cyhal_hwmgr_free(const cyhal_resource_inst_t* obj); */ cy_rslt_t cyhal_hwmgr_allocate(cyhal_resource_t type, cyhal_resource_inst_t* obj); -/** Allocate (pick and reserve) an DMA resource and provide a reference to it. - * - * @param[out] obj The resource object that was allocated - * @return The status of the reserve request - */ -cy_rslt_t cyhal_hwmgr_allocate_dma(cyhal_resource_inst_t* obj); - /** Allocate (pick and reserve) an Clock Divider resource and provide a reference to it. * * @param[out] obj The resource object that was allocated diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h index 35e9cc3246..abfab7dd1e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,10 +29,63 @@ * \addtogroup group_hal_i2c I2C (Inter-Integrated Circuit) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress I2C. -* -* \defgroup group_hal_i2c_master Master -* \defgroup group_hal_i2c_slave Slave +* High level interface for interacting with the I2C resource. +* +* The I2C protocol is a synchronous serial interface protocol. This driver supports +* both master and slave mode of operation. The communication frequency and address (for slave operation) can be +* configured. +* +* \section section_i2c_features Features +* +* * Master or slave functionality +* * Configurable slave address +* * Configurable data rates +* * Configurable interrupt and callback assignment from I2C events - \ref cyhal_i2c_event_t +* +* \section section_i2c_quickstart Quick Start +* Initialize an I2C instance using the \ref cyhal_i2c_init and provide sda (I2C data) and scl (I2C clock) pins.
+* By default, this initializes the resource as an I2C master.
+* Configure the behavior (master/slave) and the interface (bus frequency, slave address) using the \ref cyhal_i2c_configure function.
+* See \ref subsection_i2c_snippet_1 for example initialization as master or slave. +* \note The clock parameter (const cyhal_clock_divider_t *clk) is optional and can be set +* to NULL to generate and use an available clock resource with a default frequency (CYHAL_I2C_MASTER_DEFAULT_FREQ). +* +* \section section_i2c_snippets Code Snippets +* +* \subsection subsection_i2c_snippet_1 Snippet 1: I2C Initialization and Configuration +* This snippet initializes an I2C resource as master or slave and assigns +* the sda and scl pins. +* +* Initializing as I2C master +* \snippet i2c.c snippet_cyhal_i2c_master_init +* +* Initializing as I2C slave +* \snippet i2c.c snippet_cyhal_i2c_slave_init +* +* \subsection subsection_i2c_snippet_2 Snippet 2: Handling events +* This snippet shows how to enable and handle I2C events using \ref cyhal_i2c_enable_event and \ref cyhal_i2c_register_callback.
+* The callback parameter of \ref cyhal_i2c_register_callback is used to pass the callback handler that will be invoked when an event occurs.
+* The event parameter of \ref cyhal_i2c_enable_event is used to pass the bitmasks of events ( \ref cyhal_i2c_event_t) to be enabled. +* +* \snippet i2c.c snippet_cyhal_handle_i2c_events +* +* \subsection subsection_i2c_snippet_3 Snippet 3: I2C Master Asynchronous Transfer +* This snippet shows how to implement asynchronous transfers using \ref cyhal_i2c_master_transfer_async.
+* \ref cyhal_i2c_abort_async is used to stop the transfer, in this case when an error occurs. +* +* \snippet i2c.c snippet_cyhal_async_transfer +* +* \section subsection_i2c_moreinformation More Information +* +* Peripheral Driver Library (PDL) +* * +PSoC 6 PDL: SCB (Serial Communication Block) +* +* Code examples (Github) +* * +PSoC 6 MCU: I2C Master +* * +PSoC 6 MCU: I2C Slave Using Callbacks */ #pragma once @@ -47,6 +100,7 @@ extern "C" { #endif + /** The requested resource type is invalid */ #define CYHAL_I2C_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 0)) /** Can not reach desired data rate */ @@ -57,42 +111,48 @@ extern "C" { /** Enum to enable/disable/report interrupt cause flags. */ typedef enum { - CYHAL_I2C_EVENT_NONE = 0, /* No event */ - CYHAL_I2C_SLAVE_READ_EVENT = 1 << 1, /* Indicates that the slave was addressed and the master wants to read data. */ - CYHAL_I2C_SLAVE_WRITE_EVENT = 1 << 2, /* Indicates that the slave was addressed and the master wants to write data. */ - CYHAL_I2C_SLAVE_RD_IN_FIFO_EVENT = 1 << 3, /* All slave data from the configured Read buffer has been loaded into the TX FIFO. */ - CYHAL_I2C_SLAVE_RD_BUF_EMPTY_EVENT = 1 << 4, /* The master has read all data out of the configured Read buffer. */ - CYHAL_I2C_SLAVE_RD_CMPLT_EVENT = 1 << 5, /* Indicates the master completed reading from the slave (set by the master NAK or Stop) */ - CYHAL_I2C_SLAVE_WR_CMPLT_EVENT = 1 << 6, /* Indicates the master completed writing to the slave (set by the master Stop or Restart)*/ - CYHAL_I2C_SLAVE_ERR_EVENT = 1 << 7, /* Indicates the I2C hardware detected an error. */ - CYHAL_I2C_MASTER_WR_IN_FIFO_EVENT = 1 << 17, /* All data specified by Cy_SCB_I2C_MasterWrite has been loaded into the TX FIFO. */ - CYHAL_I2C_MASTER_WR_CMPLT_EVENT = 1 << 18, /* The master write started by Cy_SCB_I2C_MasterWrite is complete.*/ - CYHAL_I2C_MASTER_RD_CMPLT_EVENT = 1 << 19, /* The master read started by Cy_SCB_I2C_MasterRead is complete.*/ - CYHAL_I2C_MASTER_ERR_EVENT = 1 << 20, /* Indicates the I2C hardware has detected an error. */ + CYHAL_I2C_EVENT_NONE = 0, /**< No event */ + CYHAL_I2C_SLAVE_READ_EVENT = 1 << 1, /**< Indicates that the slave was addressed and the master wants to read data. */ + CYHAL_I2C_SLAVE_WRITE_EVENT = 1 << 2, /**< Indicates that the slave was addressed and the master wants to write data. */ + CYHAL_I2C_SLAVE_RD_IN_FIFO_EVENT = 1 << 3, /**< All slave data from the configured Read buffer has been loaded into the TX FIFO. */ + CYHAL_I2C_SLAVE_RD_BUF_EMPTY_EVENT = 1 << 4, /**< The master has read all data out of the configured Read buffer. */ + CYHAL_I2C_SLAVE_RD_CMPLT_EVENT = 1 << 5, /**< Indicates the master completed reading from the slave (set by the master NAK or Stop) */ + CYHAL_I2C_SLAVE_WR_CMPLT_EVENT = 1 << 6, /**< Indicates the master completed writing to the slave (set by the master Stop or Restart)*/ + CYHAL_I2C_SLAVE_ERR_EVENT = 1 << 7, /**< Indicates the I2C hardware detected an error. */ + CYHAL_I2C_MASTER_WR_IN_FIFO_EVENT = 1 << 17, /**< All data specified by cyhal_i2c_master_transfer_async has been loaded into the TX FIFO. */ + CYHAL_I2C_MASTER_WR_CMPLT_EVENT = 1 << 18, /**< The master write started by cyhal_i2c_master_transfer_async is complete.*/ + CYHAL_I2C_MASTER_RD_CMPLT_EVENT = 1 << 19, /**< The master read started by cyhal_i2c_master_transfer_async is complete.*/ + CYHAL_I2C_MASTER_ERR_EVENT = 1 << 20, /**< Indicates the I2C hardware has detected an error. */ } cyhal_i2c_event_t; + /** Handler for I2C events */ typedef void (*cyhal_i2c_event_callback_t)(void *callback_arg, cyhal_i2c_event_t event); + /** @brief Initial I2C configuration */ typedef struct { - bool is_slave; /* I2C mode, is the device a master or slave */ - uint16_t address; /* Address of this slave device (7-bit), should be set to 0 for master */ - uint32_t frequencyhal_hz; /* Frequency that the I2C bus runs at */ + bool is_slave; /**< Operates as a slave when set to (true), else as a master (false) */ + uint16_t address; /**< Address of this slave resource (7-bit), should be set to 0 for master */ + uint32_t frequencyhal_hz; /**< Frequency that the I2C bus runs at (I2C data rate in bits per second)
+ Refer to the device datasheet for the supported I2C data rates */ } cyhal_i2c_cfg_t; -/** Initialize the I2C peripheral, and configures its specifieds pins. By default - * it is setup as a Master running at 400kHz. This can be changed by calling - * cyhal_i2c_configure(). + +/** Initialize the I2C peripheral, and configures its specified pins. By default + * it is configured as a Master with a bus frequency = CYHAL_I2C_MASTER_DEFAULT_FREQ. + * Use \ref cyhal_i2c_configure() to change the default behavior.
* NOTE: Master/Slave specific functions only work when the block is configured - * to be in that mode. + * to be in that mode.
+ * See \ref subsection_i2c_snippet_1 * * @param[out] obj The I2C object * @param[in] sda The sda pin * @param[in] scl The scl pin * @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated * @return The status of the init request + * */ cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, const cyhal_clock_divider_t *clk); @@ -102,27 +162,27 @@ cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, c */ void cyhal_i2c_free(cyhal_i2c_t *obj); -/** Configure the I2C block +/** Configure the I2C block. + * NOTE: Master/Slave specific functions only work when the block is configured + * to be in that mode.
+ * See \ref subsection_i2c_snippet_1 * * @param[in] obj The I2C object * @param[in] cfg Configuration settings to apply * @return The status of the configure request + * */ cy_rslt_t cyhal_i2c_configure(cyhal_i2c_t *obj, const cyhal_i2c_cfg_t *cfg); -/** -* \addtogroup group_hal_i2c_master -* \{ -*/ /** * I2C master write * * @param[in] obj The I2C object * @param[in] dev_addr device address (7-bit) - * @param[in] data i2c send data - * @param[in] size i2c send data size - * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever + * @param[in] data I2C send data + * @param[in] size I2C send data size + * @param[in] timeout timeout in millisecond, set this value to 0 if you want to wait forever * @param[in] send_stop whether the stop should be send, used to support repeat start conditions * * @return The status of the master_write request @@ -134,110 +194,108 @@ cy_rslt_t cyhal_i2c_master_write(cyhal_i2c_t *obj, uint16_t dev_addr, const uint * * @param[in] obj The I2C object * @param[in] dev_addr device address (7-bit) - * @param[out] data i2c receive data - * @param[in] size i2c receive data size - * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever + * @param[out] data I2C receive data + * @param[in] size I2C receive data size + * @param[in] timeout timeout in millisecond, set this value to 0 if you want to wait forever * @param[in] send_stop whether the stop should be send, used to support repeat start conditions * * @return The status of the master_read request */ cy_rslt_t cyhal_i2c_master_read(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *data, uint16_t size, uint32_t timeout, bool send_stop); -/** \} group_hal_i2c_master */ - /** -* \addtogroup group_hal_i2c_slave -* \{ -*/ - -/** - * I2C slave config write buffer - * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up) + * The function configures the read buffer on an I2C Slave. This is the buffer from which the master reads data from. + * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up)
+ * See related code example: PSoC 6 MCU: I2C Master * * @param[in] obj The I2C object - * @param[in] data i2c slave send data - * @param[in] size i2c slave send data size + * @param[in] data I2C slave send data + * @param[in] size I2C slave send data size * * @return The status of the slave_config_write_buff request */ cy_rslt_t cyhal_i2c_slave_config_write_buff(cyhal_i2c_t *obj, const uint8_t *data, uint16_t size); /** - * I2C slave config read buffer - * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up) + * The function configures the write buffer on an I2C Slave. This is the buffer to which the master writes data to. + * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up)
+ * See related code example: PSoC 6 MCU: I2C Master * * @param[in] obj The I2C object - * @param[out] data i2c slave receive data - * @param[in] size i2c slave receive data size + * @param[out] data I2C slave receive data + * @param[in] size I2C slave receive data size * * @return The status of the slave_config_read_buff request */ cy_rslt_t cyhal_i2c_slave_config_read_buff(cyhal_i2c_t *obj, uint8_t *data, uint16_t size); -/** \} group_hal_i2c_slave */ -/** -* \addtogroup group_hal_i2c_master -* \{ -*/ - -/** Perform an i2c write using a block of data stored at the specified memory location +/** Perform an I2C write using a block of data stored at the specified memory location * * @param[in] obj The I2C object * @param[in] address device address (7-bit) * @param[in] mem_addr mem address to store the written data * @param[in] mem_addr_size number of bytes in the mem address - * @param[in] data i2c master send data - * @param[in] size i2c master send data size - * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever + * @param[in] data I2C master send data + * @param[in] size I2C master send data size + * @param[in] timeout timeout in millisecond, set this value to 0 if you want to wait forever * @return The status of the write request */ + cy_rslt_t cyhal_i2c_master_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, const uint8_t *data, uint16_t size, uint32_t timeout); -/** Perform an i2c read using a block of data stored at the specified memory location +/** Perform an I2C read using a block of data stored at the specified memory location * * @param[in] obj The I2C object * @param[in] address device address (7-bit) * @param[in] mem_addr mem address to store the written data * @param[in] mem_addr_size number of bytes in the mem address - * @param[out] data i2c master send data - * @param[in] size i2c master send data size - * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever + * @param[out] data I2C master send data + * @param[in] size I2C master send data size + * @param[in] timeout timeout in millisecond, set this value to 0 if you want to wait forever * @return The status of the read request */ cy_rslt_t cyhal_i2c_master_mem_read(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, uint8_t *data, uint16_t size, uint32_t timeout); -/** Start I2C master asynchronous transfer +/** Initiate a non-blocking I2C master asynchronous transfer. Supports simultaneous write and read operation.
+ * Use callback handler to handle the events until data transfer is complete.
+ * If either of tx_size or rx_size is '0', the respective write or read operation is not performed. + * See \ref subsection_i2c_snippet_3 * * @param[in] obj The I2C object * @param[in] address device address (7-bit) * @param[in] tx The transmit buffer - * @param[in] tx_size The number of bytes to transmit + * @param[in] tx_size The number of bytes to transmit. Use '0' if write operation is not required. * @param[out] rx The receive buffer - * @param[in] rx_size The number of bytes to receive + * @param[in] rx_size The number of bytes to receive. Use '0' if read operation is not required. * @return The status of the master_transfer_async request + * */ cy_rslt_t cyhal_i2c_master_transfer_async(cyhal_i2c_t *obj, uint16_t address, const void *tx, size_t tx_size, void *rx, size_t rx_size); -/** \} group_hal_i2c_master */ -/** Abort asynchronous transfer +/** Abort asynchronous transfer.
+ *This function aborts the ongoing transfer by generating a stop condition.
+ * See \ref subsection_i2c_snippet_3 * - * This function does not perform any check - that should happen in upper layers. * @param[in] obj The I2C object * @return The status of the abort_async request + * */ cy_rslt_t cyhal_i2c_abort_async(cyhal_i2c_t *obj); -/** The I2C event callback handler registration +/** The I2C event callback handler registration
+ * See \ref subsection_i2c_snippet_2 * * @param[in] obj The I2C object * @param[in] callback The callback handler which will be invoked when an event triggers * @param[in] callback_arg Generic argument that will be provided to the callback when called + * */ void cyhal_i2c_register_callback(cyhal_i2c_t *obj, cyhal_i2c_event_callback_t callback, void *callback_arg); /** Configure and Enable or Disable I2C Interrupt. + * See \ref subsection_i2c_snippet_2 * * @param[in] obj The I2C object * @param[in] event The I2C event type @@ -246,8 +304,9 @@ void cyhal_i2c_register_callback(cyhal_i2c_t *obj, cyhal_i2c_event_callback_t ca */ void cyhal_i2c_enable_event(cyhal_i2c_t *obj, cyhal_i2c_event_t event, uint8_t intrPriority, bool enable); + /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macro. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ /** \cond INTERNAL */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h index 390633cb5b..c9fe16ea3f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,13 @@ * \addtogroup group_hal_interconnect INTERCONNECT (Internal digital routing) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress digital routing. +* High level interface for interacting with the digital routing. +* +* This provides limited facilities for runtime manipulation of the on chip routing. +* The following types of connections are supported: +* * Connection from a peripheral to a pin. (A dedicated connection must exist + between the pin and the peripheral; see the device datasheet for more details) +* * Experimental support for connecting between two on-chip "trigger" terminals. */ #pragma once diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h index ff621632ea..74ce6e360a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,9 +29,9 @@ * \addtogroup group_hal_lptimer LPTIMER (Low-Power Timer) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress LPTIMER. -* -* This can be used to measure timing between events, or to perform +* High level interface for interacting with the low-power timer (LPTIMER). +* +* This can be used to measure timing between events, or to perform * some action the ability after a set interval. It continues to operate * in some low power modes; see the device datasheet for details. */ @@ -93,12 +93,12 @@ cy_rslt_t cyhal_lptimer_reload(cyhal_lptimer_t *obj); #define cyhal_lptimer_set_time cyhal_lptimer_set_match /** Update the match/compare value - * + * * Update the match value of an already configured LPTIMER set up * to generate an interrupt on match. Note that this function does not * reinitialize the counter or the associated peripheral initialization * sequence. - * + * * @param[in] obj The LPTIMER object * @param[in] value The tick value to match * @@ -107,13 +107,13 @@ cy_rslt_t cyhal_lptimer_reload(cyhal_lptimer_t *obj); cy_rslt_t cyhal_lptimer_set_match(cyhal_lptimer_t *obj, uint32_t value); /** Update the match/compare value - * + * * Update the match value of an already configured LPTIMER set up * to generate an interrupt on match delay from the current counter value. - * Note that this function does not reinitialize the counter or the + * Note that this function does not reinitialize the counter or the * associated peripheral initialization * sequence. - * + * * @param[in] obj The LPTIMER object * @param[in] delay The ticks to wait * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h index d53cf526e9..a46eba8910 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,8 +24,9 @@ *******************************************************************************/ /** -* \ingroup group_hal +* \ingroup group_result * \{ +* Enum definition for all HAL resource modules. */ #pragma once @@ -37,6 +38,11 @@ extern "C" { #endif /** Enum to in indicate which module an errors occurred in. */ +/** + * @brief Enum to specify module IDs for @ref cy_rslt_t values returned from the HAL. + * + */ + enum cyhal_rslt_module_chip { CYHAL_RSLT_MODULE_CHIP_HWMGR = CY_RSLT_MODULE_ABSTRACTION_HAL_BASE, //!< An error occurred in hardware management module @@ -64,10 +70,11 @@ enum cyhal_rslt_module_chip CYHAL_RSLT_MODULE_UART, //!< An error occurred in UART module CYHAL_RSLT_MODULE_USB, //!< An error occurred in USB module CYHAL_RSLT_MODULE_WDT, //!< An error occurred in WDT module + CYHAL_RSLT_MODULE_EZI2C, //!< An error occurred in EZI2C module }; #if defined(__cplusplus) } #endif /* __cplusplus */ -/** \} group_hal */ +/** \} group_hal_modules */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h index 1063a599d4..de733525ab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h @@ -3,10 +3,10 @@ * * Description: * Provides definitions for the pinout for each supported device. -* +* ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -37,24 +37,29 @@ extern "C" { #endif /* __cplusplus */ -/** Port names */ +/** Port definitions that individual pins can belong to. */ typedef enum { - CYHAL_PORT_0 = 0x0, - CYHAL_PORT_1 = 0x1, - CYHAL_PORT_2 = 0x2, - CYHAL_PORT_3 = 0x3, - CYHAL_PORT_4 = 0x4, - CYHAL_PORT_5 = 0x5, - CYHAL_PORT_6 = 0x6, - CYHAL_PORT_7 = 0x7, - CYHAL_PORT_8 = 0x8, - CYHAL_PORT_9 = 0x9, - CYHAL_PORT_10 = 0xA, - CYHAL_PORT_11 = 0xB, - CYHAL_PORT_12 = 0xC, - CYHAL_PORT_13 = 0xD, - CYHAL_PORT_14 = 0xE, - CYHAL_PORT_15 = 0xF, + CYHAL_PORT_0 = 0x00, + CYHAL_PORT_1 = 0x01, + CYHAL_PORT_2 = 0x02, + CYHAL_PORT_3 = 0x03, + CYHAL_PORT_4 = 0x04, + CYHAL_PORT_5 = 0x05, + CYHAL_PORT_6 = 0x06, + CYHAL_PORT_7 = 0x07, + CYHAL_PORT_8 = 0x08, + CYHAL_PORT_9 = 0x09, + CYHAL_PORT_10 = 0x0A, + CYHAL_PORT_11 = 0x0B, + CYHAL_PORT_12 = 0x0C, + CYHAL_PORT_13 = 0x0D, + CYHAL_PORT_14 = 0x0E, + CYHAL_PORT_15 = 0x0F, + CYHAL_PORT_16 = 0x10, + CYHAL_PORT_17 = 0x11, + CYHAL_PORT_18 = 0x12, + CYHAL_PORT_19 = 0x13, + CYHAL_PORT_20 = 0x14, } cyhal_port_t; /** Bitfield representing the configuration of a GPIO (hsiom selection and mode). @@ -115,6 +120,8 @@ typedef uint16_t cyhal_gpio_mapping_cfg_t; // 8bit hsiom, 8bit mode #include "pin_packages/cyhal_psoc6_03_49_wlcsp.h" #elif defined(_GPIO_PSOC6_03_68_QFN_H_) #include "pin_packages/cyhal_psoc6_03_68_qfn.h" +#elif defined(_GPIO_PLAYER_128_TQFP_H_) +#include "pin_packages/cyhal_mxs28playermcuss_128_tqfp.h" #else #error "Unhandled Device/PinPackage combination" #endif @@ -123,4 +130,4 @@ typedef uint16_t cyhal_gpio_mapping_cfg_t; // 8bit hsiom, 8bit mode } #endif /* __cplusplus */ -/** \} group_hal_adc */ +/** \} group_hal_psoc6 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h index b7cf1e09a0..20265effb8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,12 +29,61 @@ * \addtogroup group_hal_pwm PWM (Pulse Width Modulator) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress PWM. + * High level interface for interacting with the pulse width modulator (PWM) hardware resource + * + * The PWM driver can be used to generate periodic digital waveforms with configurable frequency and duty cycle. + * The driver allows assigning the PWM output and an optional inverted output to supplied pins. + * The driver supports interrupt generation on PWM terminal count and capture/compare events. + * + * \section section_pwm_features Features + * * Configurable pin assignment for the PWM output + * * Optional complementary (inverted) PWM output to a second pin + * * Configurable dead time between normal and inverted PWM outputs + * * Configurable alignment: left, right or center + * * Continuous or One-shot operation + * * Option to instantiate and use a new clock or use pre-allocated clock for clock input + * * Configurable interrupt and callback assignment on PWM events: terminal count, capture/compare match or combination of both + * + * \section section_pwm_quickstart Quick Start + * + * See \ref subsection_pwm_snippet_1 for a code snippet that generates a signal with the specified frequency and duty cycle on the specified pin. + * + * \section section_pwm_snippets Code snippets + * + * \subsection subsection_pwm_snippet_1 Snippet 1: Simple PWM initialization and output to pin + * The following snippet initializes a PWM resource and assigns the output to the supplied pin using \ref cyhal_pwm_init.
+ * The clock parameter clk is optional and need not be provided (NULL), to generate and use an available clock resource with a default frequency.
+ * The clock frequency and the duty cycle is set using \ref cyhal_pwm_set_duty_cycle.
+ * \ref cyhal_pwm_start starts the PWM output on the pin. + * + * \snippet pwm.c snippet_cyhal_pwm_simple_init + * + * + * \subsection subsection_pwm_snippet_2 Snippet 2: Starting and stopping the PWM output + * \ref cyhal_pwm_start and \ref cyhal_pwm_stop functions can be used after PWM initialization to start and stop the PWM output. + * + * \snippet pwm.c snippet_cyhal_pwm_start_stop + * + * + * \subsection subsection_pwm_snippet_3 Snippet 3: Advanced PWM output to pin + * \ref cyhal_pwm_init_adv can be used to specify advanced PWM options like an additional inverted PWM output, pulse alignment + * (left, right, center) and run mode (one-shot or continuous). The following snippet initializes a left-aligned, continuous running PWM + * assigned to the supplied pin. The inverted output is assigned to a second pin (compl_pin). + * + * \snippet pwm.c snippet_cyhal_pwm_adv_init + * + * + * \subsection subsection_pwm_snippet_4 Snippet 4: Interrupts on PWM events + * PWM events like hitting the terminal count or a capture/compare event can be used to trigger a callback function.
+ * \ref cyhal_pwm_enable_event() can be used to enable one or more events to trigger the callback function. + * + * \snippet pwm.c snippet_cyhal_pwm_events */ #pragma once #include +#include #include "cy_result.h" #include "cyhal_hw_types.h" #include "cyhal_modules.h" @@ -43,6 +92,17 @@ extern "C" { #endif +/** Initialize the PWM out peripheral and configure the pin + * This is similar to the \ref cyhal_pwm_init_adv() but uses defaults for some of the + * more advanced setup options. See \ref subsection_pwm_snippet_1. + * + * @param[out] obj The PWM object to initialize + * @param[in] pin The PWM pin to initialize + * @param[in] clk An optional, pre-allocated clock to use, if NULL a new clock will be allocated + * @return The status of the init request. + */ +#define cyhal_pwm_init(obj, pin, clk) (cyhal_pwm_init_adv(obj, pin, NC, CYHAL_PWM_LEFT_ALIGN, true, 0u, (bool)(pin & 1), clk)) + /** Bad argument */ #define CYHAL_PWM_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_PWM, 0)) /** Failed to initialize PWM clock */ @@ -52,23 +112,44 @@ extern "C" { /** PWM interrupt triggers */ typedef enum { - CYHAL_PWM_IRQ_NONE = 0, - CYHAL_PWM_IRQ_TERMINAL_COUNT = 1 << 0, - CYHAL_PWM_IRQ_CAPTURE_COMPARE = 1 << 1, - CYHAL_PWM_IRQ_ALL = (1 << 2) - 1, + CYHAL_PWM_IRQ_NONE = 0, /**< No interrupts */ + CYHAL_PWM_IRQ_TERMINAL_COUNT = 1 << 0, /**< Interrupt on terminal count match event */ + CYHAL_PWM_IRQ_CAPTURE_COMPARE = 1 << 1, /**< Interrupt on capture/compare match event */ + CYHAL_PWM_IRQ_ALL = (1 << 2) - 1, /**< Interrupt on any events */ } cyhal_pwm_event_t; +/** PWM alignment */ +typedef enum { + CYHAL_PWM_LEFT_ALIGN = 0, /**< PWM is left aligned (signal starts high and goes low after capture/compare match) */ + CYHAL_PWM_RIGHT_ALIGN = 1, /**< PWM is right aligned (signal starts low and goes high after capture/compare match) */ + CYHAL_PWM_CENTER_ALIGN = 2, /**< PWM is centered aligned (signal starts and ends low with a center aligned pulse) */ +} cyhal_pwm_alignment_t; + /** Handler for PWM interrupts */ typedef void(*cyhal_pwm_event_callback_t)(void *callback_arg, cyhal_pwm_event_t event); -/** Initialize the PWM out peripheral and configure the pin +/** Initialize the PWM out peripheral and configure the pin. + * This is similar to the \ref cyhal_pwm_init() but provides additional setup options.
+ * See \ref subsection_pwm_snippet_3. * - * @param[out] obj The PWM object to initialize - * @param[in] pin The PWM pin to initialize - * @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated + * @param[out] obj The PWM object to initialize. + * @param[in] pin The PWM pin to initialize. + * @param[in] compl_pin An optional, additional inverted output pin.
+ * If supplied, this must be connected to the same PWM instance as pin, for + * PSoC 6 see \ref section_psoc6_pwm_compl_pins.
+ * If this output is not needed, use \ref NC (No Connect). + * @param[in] pwm_alignment PWM alignment: left, right, or center. + * @param[in] continuous PWM run type: continuous (true) or one shot (false). + * @param[in] dead_time_us The number of micro-seconds for dead time. This is + * only meaningful if both pin and compl_pin are provided. + * @param[in] invert An option for the user to invert the PWM output + * @param[in] clk An optional, pre-allocated clock to use, if NULL a + * new clock will be allocated. * @return The status of the init request + * + * @note In some cases, it is possible to use a pin designated for non-inverting output as an inverting output and vice versa. Whether this is possible is dependent on the HAL implementation and operating mode. See the implementation specific documentation for details. */ -cy_rslt_t cyhal_pwm_init(cyhal_pwm_t *obj, cyhal_gpio_t pin, const cyhal_clock_divider_t *clk); +cy_rslt_t cyhal_pwm_init_adv(cyhal_pwm_t *obj, cyhal_gpio_t pin, cyhal_gpio_t compl_pin, cyhal_pwm_alignment_t pwm_alignment, bool continuous, uint32_t dead_time_us, bool invert, const cyhal_clock_divider_t *clk); /** Deinitialize the PWM object * @@ -85,26 +166,26 @@ void cyhal_pwm_free(cyhal_pwm_t *obj); */ cy_rslt_t cyhal_pwm_set_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us); -/** Set the PWM pulsewidth specified in microseconds, keeping the period the same. +/** Set the PWM duty cycle and frequency * - * @param[in] obj The PWM object - * @param[in] duty_cycle The percentage of time the output is high - * @param[in] frequencyhal_hz The frequency of the PWM - * @return The status of the pulsewidth request + * @param[in] obj The PWM object + * @param[in] duty_cycle The percentage of time the output is high + * @param[in] frequencyhal_hz The frequency of the PWM in Hz + * @return The status of the duty cycle request */ cy_rslt_t cyhal_pwm_set_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz); -/** Starts the PWM with the provided period and pulsewidth +/** Starts the PWM generation and outputs on pin and compl_pin. * * @param[in] obj The PWM object - * @return The status of the start request + * @return The status of the start request */ cy_rslt_t cyhal_pwm_start(cyhal_pwm_t *obj); -/** Stops the PWM from running +/** Stops the PWM generation and outputs on pin and compl_pin. * - * @param[in] obj The PWM object - * @return The status of the stop request + * @param[in] obj The PWM object + * @return The status of the stop request */ cy_rslt_t cyhal_pwm_stop(cyhal_pwm_t *obj); @@ -118,12 +199,12 @@ void cyhal_pwm_register_callback(cyhal_pwm_t *obj, cyhal_pwm_event_callback_t ca /** Configure PWM event enablement. * - * @param[in] obj The PWM object - * @param[in] event The PWM event type - * @param[in] intrPriority The priority for NVIC interrupt events - * @param[in] enable True to turn on events, False to turn off + * @param[in] obj The PWM object + * @param[in] event The PWM event type + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable True to turn on events, False to turn off */ -void cyhal_pwm_enable_event(cyhal_pwm_t *obj, cyhal_pwm_event_t event, uint8_t intrPriority, bool enable); +void cyhal_pwm_enable_event(cyhal_pwm_t *obj, cyhal_pwm_event_t event, uint8_t intr_priority, bool enable); #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h index 957a86c9e9..e7c0a3473f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h index bf67b38452..2e69c396ff 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,10 @@ * \addtogroup group_hal_qspi QSPI (Quad Serial Peripheral Interface) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress Quad-SPI. +* High level interface for interacting with the Quad Serial Peripheral Interface (QSPI) interface. +* +* The QSPI block supports sending commands to and receiving commands from an +* another device (often an external memory) via single, dual, quad, or octal SPI. */ #pragma once @@ -71,12 +74,10 @@ typedef enum { } cyhal_qspi_event_t; #define CYHAL_QSPI_RSLT_ERR_BUS_WIDTH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 0)) /**< Bus width Error. >*/ -#define CYHAL_QSPI_RSLT_ERR_SIZE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Size Error. >*/ -#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Pin related Error. >*/ -#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< Data select Error. >*/ -#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 4)) /**< QSPI instance related Error. >*/ -#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_WIDTH_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 5)) /**< Provided alt size is incompatible with provided alt width. >*/ -#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_DUMMY_CYCLES_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 6)) /**< Provided alt size is incompatible with provided number of dummy cycles (due to device-specific restrictions). >*/ +#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Pin related Error. >*/ +#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Data select Error. >*/ +#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< QSPI instance related Error. >*/ +#define CYHAL_QSPI_RSLT_ERR_FREQUENCY (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 4)) /**< Clock frequency error. >*/ /** @brief QSPI command settings */ typedef struct cyhal_qspi_command { @@ -93,7 +94,7 @@ typedef struct cyhal_qspi_command { } address; struct { cyhal_qspi_bus_width_t bus_width; /**< Bus width for mode bits >*/ - uint8_t size; /**< Mode bits size >*/ + cyhal_qspi_size_t size; /**< Mode bits size >*/ uint32_t value; /**< Mode bits value >*/ bool disabled; /**< Mode bits phase skipped if disabled is set to true >*/ } mode_bits; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h index e49fe88221..8e997e4179 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h @@ -2,14 +2,14 @@ * \file cyhal_rtc.h * * \brief -* Provides a high level interface for interacting with the Real Time Clock on -* Cypress devices. This interface abstracts out the chip specific details. -* If any chip specific functionality is necessary, or performance is critical +* Provides a high level interface for interacting with the Real Time Clock on +* Cypress devices. This interface abstracts out the chip specific details. +* If any chip specific functionality is necessary, or performance is critical * the low level functions can be used directly. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,14 @@ * \addtogroup group_hal_rtc RTC (Real-Time Clock) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress RTC. +* High level interface for interacting with the real-time clock (RTC). +* +* The real time clock provides tracking of the current time and date, as +* well as the ability to trigger a callback at a specific time in the future. +* +* If a suitable clock source is available, the RTC can continue timekeeping +* operations even when the device is in a low power operating mode. See the +* device datasheet for more details. */ #pragma once @@ -43,6 +50,8 @@ /** RTC not initialized */ #define CY_RSLT_RTC_NOT_INITIALIZED CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_RTC, 0) +/** Bad argument */ +#define CY_RSLT_RTC_BAD_ARGUMENT CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_RTC, 1) #if defined(__cplusplus) extern "C" { @@ -64,6 +73,35 @@ typedef struct uint8_t en_month : 1; /** !< Enable match of month */ } cyhal_alarm_active_t; +/** Enumeration used to configure the DST format */ +typedef enum +{ + CYHAL_RTC_DST_RELATIVE, /**< Relative DST format */ + CYHAL_RTC_DST_FIXED /**< Fixed DST format */ +} cyhal_rtc_dst_format_t; + +/** +* Day Light Savings Time (DST) structure for setting when to apply. It allows to +* set the DST time and date using a fixed or relative time format. +*/ +typedef struct +{ + cyhal_rtc_dst_format_t format; /**< DST format. See /ref cyhal_rtc_dst_format_t. + Based on this value other structure elements + should be filled or could be ignored */ + uint32_t hour; /**< Hour in 24hour format, range[0-23] */ + union + { + uint32_t dayOfMonth; /**< Day of Month, range[1-31]. */ + struct /* format = CYHAL_RTC_DST_FIXED */ + { + uint32_t dayOfWeek; /**< Day of the week, starting on Sunday, range[0-6] */ + uint32_t weekOfMonth; /**< Week of month, range[0-5]. Where 5 => Last week of month */ + }; + }; + uint32_t month; /**< Month value, range[1-12]. */ +} cyhal_rtc_dst_t; + /** Handler for RTC events */ typedef void (*cyhal_rtc_event_callback_t)(void *callback_arg, cyhal_rtc_event_t event); @@ -83,7 +121,7 @@ cy_rslt_t cyhal_rtc_init(cyhal_rtc_t *obj); /** Deinitialize RTC * - * Frees resources associated with the RTC and disables CPU access. This + * Frees resources associated with the RTC and disables CPU access. This * only affects the CPU domain and not the time keeping logic. * After this function is called no other RTC functions should be called * except for rtc_init. @@ -115,6 +153,23 @@ cy_rslt_t cyhal_rtc_read(cyhal_rtc_t *obj, struct tm *time); */ cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time); +/** Set the start and end time for Day Light Savings + * + * @param[in] obj RTC object + * @param[in] start When Day Light Savings time should start + * @param[in] stop When Day Light Savings time should end + * @return The status of the set_dst request + */ +cy_rslt_t cyhal_rtc_set_dst(cyhal_rtc_t *obj, const cyhal_rtc_dst_t *start, const cyhal_rtc_dst_t *stop); + +/** Checks to see if Day Light Savings Time is currently active. This should only be called after + * \ref cyhal_rtc_set_dst(). + * + * @param[in] obj RTC object + * @return Boolean indicating whether the current date/time is within the specified DST start/stop window. + */ +bool cyhal_rtc_is_dst(cyhal_rtc_t *obj); + /** Set an alarm for the specified time in seconds to the RTC peripheral * * @param[in] obj RTC object diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h index e1a00765c5..4095ae7100 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ * limitations under the License. *******************************************************************************/ +/** \cond INTERNAL */ /** * \addtogroup group_hal_psoc6_scb_common SCB Common Functionality * \ingroup group_hal_psoc6 @@ -71,3 +72,4 @@ __STATIC_INLINE void *cyhal_scb_get_irq_obj(void) #endif /** \} group_hal_psoc6_scb_common */ +/** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h index 6cd2fc9eb8..87d717d8c2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,10 @@ * \addtogroup group_hal_sdhc SDHC (SD Host Controller) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress SDHC. +* High level interface for interacting with the SD Host Controller (SDHC). +* +* The SD Host Controller allows data to be read from and written to several types +* of memory cards, including SD and eMMC (see cyhal_sdhc_card_type_t for a full list). */ #pragma once @@ -44,12 +47,13 @@ extern "C" { #endif #define CYHAL_SDHC_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 0)) /**< Pin related Error. >*/ +#define CYHAL_SDHC_RSLT_ERR_UNSUPPORTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 1)) /**< Requested feature is not supported on this hardware. >*/ /** Card types */ typedef enum { CYHAL_SDHC_SD, //!< Secure Digital card - CYHAL_SDHC_SDIO, //!< CD Input Output card + CYHAL_SDHC_SDIO, //!< SD Input Output card CYHAL_SDHC_EMMC, //!< Embedded Multimedia card CYHAL_SDHC_COMBO, //!< Combo Card (SD + SDIO) CYHAL_SDHC_UNUSABLE, //!< Unusable card or unsupported type diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h index d5e396eca8..c33f0ab376 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,8 +29,14 @@ * \addtogroup group_hal_sdio SDIO (Secure Digital Input Output) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress SDIO interface. +* High level interface for interacting with the Secure Digital Input Output (SDIO) interface. * +* The Secure Digital Input Output (SDIO) protocol is an extension of the SD +* interface for general I/O functions. +* +* This driver allows commands to be sent over the SDIO bus; the supported commands +* can be found in cyhal_sdio_command_t. Bulk data transfer is also supported +* via cyhal_sdio_bulk_transfer(). */ #pragma once @@ -44,11 +50,6 @@ extern "C" { #endif -/** - * \addtogroup group_hal_sdio_errors Error Codes - * \{ - */ - #define CYHAL_SDIO_RET_NO_ERRORS (0x00) /**< No error*/ #define CYHAL_SDIO_RET_NO_SP_ERRORS (0x01) /**< Non-specific error code*/ #define CYHAL_SDIO_RET_CMD_CRC_ERROR (0x02) /**< There was a CRC error on the Command/Response*/ @@ -91,8 +92,6 @@ extern "C" { CYHAL_RSLT_MODULE_SDIO, \ CYHAL_SDIO_CANCELED) -/** \} group_hal_sdio_errors */ - /** Commands that can be issued */ typedef enum { @@ -115,7 +114,7 @@ typedef enum /** Types of events that could be asserted by SDIO */ typedef enum { /* Interrupt-based thread events */ - CYHAL_SDIO_CMD_COMPLETE = 0x00001, //!> Command Complete + CYHAL_SDIO_CMD_COMPLETE = 0x00001, //!> Command Complete CYHAL_SDIO_XFER_COMPLETE = 0x00002, //!> Host read/write transfer is complete CYHAL_SDIO_BGAP_EVENT = 0x00004, //!> This bit is set when both read/write transaction is stopped CYHAL_SDIO_DMA_INTERRUPT = 0x00008, //!> Host controller detects an SDMA Buffer Boundary during transfer @@ -131,11 +130,11 @@ typedef enum { CYHAL_SDIO_FX_EVENT = 0x02000, //!> This status is set when R[14] of response register is set to 1 CYHAL_SDIO_CQE_EVENT = 0x04000, //!> This status is set if Command Queuing/Crypto event has occurred CYHAL_SDIO_ERR_INTERRUPT = 0x08000, //!> If any of the bits in the Error Interrupt Status register are set - + /* Non-interrupt-based thread events */ CYHAL_SDIO_GOING_DOWN = 0x10000, //!> The interface is going away (eg: powering down for some period of time) CYHAL_SDIO_COMING_UP = 0x20000, //!> The interface is back up (eg: came back from a low power state) - + CYHAL_SDIO_ALL_INTERRUPTS = 0x0E1FF, //!> Is used to enable/disable all interrupts events } cyhal_sdio_event_t; @@ -193,9 +192,13 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio * @param[in,out] obj The SDIO object * @param[in] direction The direction of transfer (read/write) * @param[in] argument The argument to the command - * @param[in] data The data to send to the SDIO device. The data buffer - * should be aligned to the block size (64 bytes) if data - * size is greater that block size (64 bytes). + * @param[in] data The data to send to the SDIO device. A bulk transfer is done in block + * size (default: 64 bytes) chunks for better performance. Therefore, + * the size of the data buffer passed into this function must be at least + * `length` bytes and a multiple of the block size. For example, when + * requesting to read 100 bytes of data with a block size 64 bytes, the + * data buffer needs to be at least 128 bytes. The first 100 bytes of data + * in the buffer will be the requested data. * @param[in] length The number of bytes to send * @param[out] response The response from the SDIO device * @return The status of the configure request @@ -245,7 +248,7 @@ void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_event_callback_t void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_event_t event, uint8_t intrPriority, bool enable); /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macro. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ /** \cond INTERNAL */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h index ca6f24a08b..a08561ac3c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,59 @@ * \addtogroup group_hal_spi SPI (Serial Peripheral Interface) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress SPI. +* High level interface for interacting with the Serial Peripheral Interface (SPI). +* +* The SPI protocol is a synchronous serial interface protocol. Devices operate +* in either master or slave mode. The master initiates the data transfer. +* +* Motorola SPI modes 0, 1, 2, and 3 are supported, with either MSB or LSB first. +* The operating mode and data frame size can be configured via \ref cyhal_spi_cfg_t. +* +* \section section_spi_features Features +* * Supports master and slave functionality. +* * Supports Motorola modes - 0, 1, 2 and 3 - \ref cyhal_spi_mode_t +* * MSb or LSb first shift direction - \ref cyhal_spi_mode_t +* * Master supports up to four slave select lines +* * Supports data frame size of 8 or 16 bits +* * Configurable interrupt and callback assignment on SPI events: +* Data transfer to FIFO complete, Transfer complete and Transmission error - \ref cyhal_spi_event_t +* * Supports changing baud rate of the transaction in run time. +* * Provides functions to send/receive a single byte or block of data. +* +* \section section_spi_quickstart Quick Start +* +* Initialise a SPI master or slave interface using \ref cyhal_spi_init() and provide the SPI pins (mosi, miso, sclk, ssel), +* number of bits per frame (data_bits) and SPI Motorola mode. The data rate can be set using \ref cyhal_spi_set_frequency().
+* See \ref section_spi_snippets for code snippets to send or receive the data. +* +* \section section_spi_snippets Code snippets +* +* \subsection subsection_spi_snippet_1 Snippet 1: SPI Master - Single byte transfer operation (Read and Write) +* The following code snippet initialises an SPI Master interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency(). +* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv(). +* \snippet spi.c snippet_cyhal_spi_master_byte_operation +* +* \subsection subsection_spi_snippet_2 Snippet 2: SPI Slave - Single byte transfer operation (Read and Write) +* The following code snippet initialises an SPI Slave interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency. +* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv. +* \snippet spi.c snippet_cyhal_spi_slave_byte_operation +* +* \subsection subsection_spi_snippet_3 Snippet 3: SPI Block Data transfer +* The following snippet sends and receives an array of data in a single SPI transaction using \ref cyhal_spi_transfer(). The example +* uses SPI master to transmit 5 bytes of data and receive 5 bytes of data in a single transaction. +* \snippet spi.c snippet_cyhal_spi_block_data_transfer +* +* \subsection subsection_spi_snippet_4 Snippet 4: Interrupts on SPI events +* SPI interrupt events ( \ref cyhal_spi_event_t) can be mapped to an interrupt and assigned to a callback function. +* The callback function needs to be first registered and then the event needs to be enabled. +* The following snippet initialises a SPI master to perform a block transfer using \ref cyhal_spi_transfer_async(). This is a non-blocking function. +* A callback function is registered using \ref cyhal_spi_register_callback to notify whenever the SPI transfer is complete. +* \snippet spi.c snippet_cyhal_spi_interrupt_callback_events + +* \section subsection_spi_moreinfor More Information +* +* * mtb-example-psoc6-spi-master: This example project demonstrates +* use of SPI (HAL) resource in PSoC® 6 MCU in Master mode to write data to an SPI slave. */ #pragma once @@ -44,7 +96,6 @@ extern "C" { #endif - /** Bad argument */ #define CYHAL_SPI_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 0)) /** Failed to initialize SPI clock */ @@ -105,7 +156,6 @@ typedef struct bool is_slave; //!< Whether the peripheral is operating as slave or master } cyhal_spi_cfg_t; - /** Initialize the SPI peripheral * * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral @@ -232,7 +282,7 @@ void cyhal_spi_register_callback(cyhal_spi_t *obj, cyhal_spi_event_callback_t ca void cyhal_spi_enable_event(cyhal_spi_t *obj, cyhal_spi_event_t event, uint8_t intrPriority, bool enable); /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macro. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ /** \cond INTERNAL */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h index d5f994a019..24317fd4fd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,11 +26,16 @@ *******************************************************************************/ /** -* \addtogroup group_hal_system SYSTEM (Power Management and System Clock) +* \addtogroup group_hal_system System (Power Management and System Clock) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress power management +* High level interface for interacting with the power management * and system clock configuration. +* +* This driver provides three categories of functionality: +* * Retrieval and adjustment of system clock frequencies. +* * Control over low power operating modes. +* * The ability to disable interrupts during a critical section, and to renable them afterwards. */ #pragma once @@ -56,6 +61,19 @@ extern "C" { /** An error occurred in System module */ #define CYHAL_SYSTEM_RSLT_NO_VALID_DIVIDER (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SYSTEM , 4)) +/** Flags enum of possible system reset causes */ +typedef enum +{ + CYHAL_SYSTEM_RESET_NONE = 0, /** No cause */ + CYHAL_SYSTEM_RESET_WDT = 1 << 0, /** A watchdog timer (WDT) reset has occurred */ + CYHAL_SYSTEM_RESET_ACTIVE_FAULT = 1 << 1, /** The fault logging system requested a reset from its Active logic. */ + CYHAL_SYSTEM_RESET_DEEPSLEEP_FAULT = 1 << 2, /** The fault logging system requested a reset from its Deep-Sleep logic. */ + CYHAL_SYSTEM_RESET_SOFT = 1 << 3, /** The CPU requested a system reset through it's SYSRESETREQ. */ + CYHAL_SYSTEM_RESET_HIB_WAKEUP = 1 << 4, /** A reset has occurred due to a a wakeup from hibernate power mode. */ + CYHAL_SYSTEM_RESET_WCO_ERR = 1 << 5, /** A reset has occurred due to a watch-crystal clock error */ + CYHAL_SYSTEM_RESET_SYS_CLK_ERR = 1 << 6, /** A reset has occurred due to a system clock error */ +} cyhal_reset_reason_t; + /** Enter a critical section * * Disables interrupts and returns a value indicating whether the interrupts were previously @@ -113,6 +131,32 @@ cy_rslt_t cyhal_system_register_callback(cyhal_system_callback_t *callback); */ cy_rslt_t cyhal_system_unregister_callback(cyhal_system_callback_t const *callback); +/** + * Requests that the current operation delays for at least the specified length of time. + * If this is running in an RTOS aware environment (-DCY_RTOS_AWARE) it will attempt to + * have the RTOS suspend the current task so others can continue to run. If this is not + * run under an RTOS it will then defer to the standard system delay which is likely to + * be a busy loop. + * If this is part of an application that is build with RTOS awareness, but the delay + * should not depend on the RTOS for whatever reason, use cyhal_system_delay_us() with + * the appropriate 1000x multiplier to the delay time. + * + * @param[in] milliseconds The number of milliseconds to delay for + * @return Returns CY_RSLT_SUCCESS if the delay request was successful, otherwise error + */ +cy_rslt_t cyhal_system_delay_ms(uint32_t milliseconds); + +/** + * Requests that the current operation delay for at least the specified number of + * micro-seconds. This will generally keep the processor active in a loop for the + * specified length of time. If this is running under an RTOS, it will NOT attempt to + * run any other RTOS tasks, however if the scheduler or a high priority interrupt + * comes it they can take over anyway. + * + * @param[in] microseconds The number of micro-seconds to delay for + */ +void cyhal_system_delay_us(uint16_t microseconds); + /** Gets the specified clock's current frequency. * * @param[in] clock ID of clock to configure @@ -138,6 +182,15 @@ cy_rslt_t cyhal_system_clock_set_frequency(uint8_t clock, uint32_t frequency_hz) */ cy_rslt_t cyhal_system_clock_set_divider(cyhal_system_clock_t clock, cyhal_system_divider_t divider); +/** Gets the cause of the latest reset or resets that occured in the system. + * + * @return Returns an enum of flags with the cause of the last reset(s) + */ +cyhal_reset_reason_t cyhal_system_get_reset_reason(void); + +/** Clears the reset cause registers */ +void cyhal_system_clear_reset_reason(void); + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system_impl.h index d7e88a6591..9e5ffc0a2c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system_impl.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -31,7 +31,7 @@ #ifdef CY_IP_MXS40SRSS -#define cyhal_system_critical_section_enter() Cy_SysLib_EnterCriticalSection() +#define cyhal_system_critical_section_enter() Cy_SysLib_EnterCriticalSection() #define cyhal_system_critical_section_exit(x) Cy_SysLib_ExitCriticalSection(x) @@ -39,4 +39,6 @@ #define cyhal_system_deepsleep() Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT) +#define cyhal_system_delay_us(microseconds) Cy_SysLib_DelayUs(microseconds) + #endif /* CY_IP_MXS40SRSS */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h index faa9d44ddb..2990501486 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ * limitations under the License. *******************************************************************************/ +/** \cond INTERNAL */ /** * \addtogroup group_hal_psoc6_tcpwm_common TCPWM Common Functionality * \ingroup group_hal_psoc6 @@ -77,3 +78,4 @@ void cyhal_tcpwm_register_callback(cyhal_resource_inst_t *resource, cy_israddres void cyhal_tcpwm_enable_event(TCPWM_Type *type, cyhal_resource_inst_t *resource, uint32_t event, uint8_t intrPriority, bool enable); /** \} group_hal_psoc6_tcpwm_common */ +/** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h index 5dcb30921c..2e2d36291d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,10 +26,57 @@ *******************************************************************************/ /** -* \addtogroup group_hal_timer TIMER (Timer/Counter) +* \addtogroup group_hal_timer Timer (Timer/Counter) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress Timer. +* High level interface for interacting with the Timer/Counter hardware resource. +* +* The timer block is commonly used to measure the time of occurrence of an event, +* to measure the time difference between two events or perform an action after +* a specified period of time. The driver also allows the user to invoke a callback function +* when a particular event occurs. +* +* Some use case scenarios of timer - +* +* * Creating a periodic interrupt for executing periodic tasks +* * Measuring time between two events +* * Triggering other system resources after a certain number of events +* * Capturing time stamps when events occur +* +* \section subsection_timer_features Features +* * Runtime configurable parameters like period and compare value - \ref cyhal_timer_cfg_t +* * Configurable counting direction - \ref cyhal_timer_direction_t +* * Interrupt on various events - \ref cyhal_timer_event_t +* * Continuous or One Shot run modes +* +* \section subsection_timer_quickstart Quick Start +* +* \ref cyhal_timer_init can be used for timer initialization by providing the timer object - \ref cyhal_timer_t, +* and shared clock source - clk (optional). The timer parameters needs to be populated in \ref cyhal_timer_cfg_t structure. +* The timer then needs to be configured by using the \ref cyhal_timer_configure function. +* +* \note A default frequency is set when an existing clock divider - clk is not provided to \ref cyhal_timer_init which is +* defined by the macro - \ref CYHAL_TIMER_DEFAULT_FREQ. +* +* \warning Currently there is no support for pin connections to Timer using this driver. So, the pin should be +* assigned as \ref NC while using the \ref cyhal_timer_init to initialize the timer. +* +* +* See \ref subsection_timer_snippet_1. +* +* \section subsection_timer_sample_snippets Code Snippets +* +* \subsection subsection_timer_snippet_1 Snippet 1: Measuring time between two events +* The following snippet initializes a Timer and measures the time between two events. +* The clk need not be provided, in which case a clock resource is assigned. +* \snippet timer.c snippet_cyhal_timer_event_measure +* +* \subsection subsection_timer_snippet_2 Snippet 2: Handling an event in a callback function +* The following snippet initializes a Timer and triggers an event after every one second. +* The clk need not be provided (NULL), in which +* case a clock resource is assigned. +* \snippet timer.c snippet_cyhal_timer_event_interrupt +* */ #pragma once @@ -44,6 +91,10 @@ extern "C" { #endif +/******************************************************************************* +* Enumerations +*******************************************************************************/ + /** Timer directions */ typedef enum { @@ -54,17 +105,21 @@ typedef enum /** Timer/counter interrupt triggers */ typedef enum { - CYHAL_TIMER_IRQ_NONE = 0, - CYHAL_TIMER_IRQ_TERMINAL_COUNT = 1 << 0, - CYHAL_TIMER_IRQ_CAPTURE_COMPARE = 1 << 1, - CYHAL_TIMER_IRQ_ALL = (1 << 2) - 1, + CYHAL_TIMER_IRQ_NONE = 0, /**< No interrupt handled **/ + CYHAL_TIMER_IRQ_TERMINAL_COUNT = 1 << 0, /**< Interrupt when terminal count is reached **/ + CYHAL_TIMER_IRQ_CAPTURE_COMPARE = 1 << 1, /**< Interrupt when Compare/Capture value is reached **/ + CYHAL_TIMER_IRQ_ALL = (1 << 2) - 1, /**< Interrupt on terminal count and Compare/Capture values **/ } cyhal_timer_event_t; +/******************************************************************************* +* Data Structures +*******************************************************************************/ + /** @brief Describes the current configuration of a timer/counter */ typedef struct { /** - * Whether the timer is set to continously run. + * Whether the timer is set to continuously run. * If true, the timer will run forever. * Otherwise, the timer will run once and stop (one shot). */ @@ -76,6 +131,10 @@ typedef struct uint32_t value; //!< Current value of the timer/counter } cyhal_timer_cfg_t; +/******************************************************************************* +* Typedefs +*******************************************************************************/ + /** Handler for timer events */ typedef void(*cyhal_timer_event_callback_t)(void *callback_arg, cyhal_timer_event_t event); @@ -91,7 +150,12 @@ typedef void(*cyhal_timer_event_callback_t)(void *callback_arg, cyhal_timer_even /** Default timer frequency, used when an existing clock divider is not provided to init */ #define CYHAL_TIMER_DEFAULT_FREQ (1000000u) -/** Initialize the timer/counter peripheral and configure the pin. +/******************************************************************************* +* Functions +*******************************************************************************/ + +/** Initialize the timer/counter peripheral and configure the pin.
+ * See \ref subsection_timer_snippet_1. * * @param[out] obj The timer/counter object to initialize * @param[in] pin optional - The timer/counter compare/capture pin to initialize @@ -107,38 +171,51 @@ cy_rslt_t cyhal_timer_init(cyhal_timer_t *obj, cyhal_gpio_t pin, const cyhal_clo */ void cyhal_timer_free(cyhal_timer_t *obj); -/** Updates the configuration of the timer/counter object - * +/** Updates the configuration of the timer/counter object
+ * See \ref subsection_timer_snippet_1. * @param[in] obj The timer/counter object * @param[in] cfg The configuration of the timer/counter * @return The status of the configure request */ cy_rslt_t cyhal_timer_configure(cyhal_timer_t *obj, const cyhal_timer_cfg_t *cfg); -/** Configures the timer frequency. This is not valid to call if a non-null clock divider - * was provided to cyhal_timer_init +/** Configures the timer frequency. + * \note This is only valid to call if a null clock divider was provided to \ref cyhal_timer_init. + * If a custom clock was provided its frequency should be adjusted directly. * + * See \ref subsection_timer_snippet_1. * @param[in] obj The timer/counter object * @param[in] hz The frequency rate in Hz * @return The status of the set_frequency request */ cy_rslt_t cyhal_timer_set_frequency(cyhal_timer_t *obj, uint32_t hz); -/** Starts the timer/counter with the pre-set configuration. +/** Starts the timer/counter with the pre-set configuration
+ * See \ref subsection_timer_snippet_1. * * @param[in] obj The timer/counter object * @return The status of the start request */ cy_rslt_t cyhal_timer_start(cyhal_timer_t *obj); -/** Stops the timer/counter. +/** Stops the timer/counter
+ * See \ref subsection_timer_snippet_1. * * @param[in] obj The timer/counter object * @return The status of the stop request */ cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj); -/** The timer/counter callback handler registration +/** Reads the current value from the timer/counter
+ * See \ref subsection_timer_snippet_1. + * + * @param[in] obj The timer/counter object + * @return The current value of the timer/counter + */ +uint32_t cyhal_timer_read(const cyhal_timer_t *obj); + +/** The timer/counter callback handler registration
+ * See \ref subsection_timer_snippet_2. * * @param[in] obj The timer/counter object * @param[in] callback The callback handler which will be invoked when the event occurs @@ -146,14 +223,15 @@ cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj); */ void cyhal_timer_register_callback(cyhal_timer_t *obj, cyhal_timer_event_callback_t callback, void *callback_arg); -/** Configure timer/counter event enablement. +/** Configure timer/counter event enablement
+ * See \ref subsection_timer_snippet_2. * * @param[in] obj The timer/counter object * @param[in] event The timer/counter event type - * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] intr_priority The priority for NVIC interrupt events * @param[in] enable True to turn on interrupts, False to turn off */ -void cyhal_timer_enable_event(cyhal_timer_t *obj, cyhal_timer_event_t event, uint8_t intrPriority, bool enable); +void cyhal_timer_enable_event(cyhal_timer_t *obj, cyhal_timer_event_t event, uint8_t intr_priority, bool enable); #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h index 9693bb8391..58c27cb3df 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_triggers.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_triggers.h new file mode 100644 index 0000000000..6a36d592e3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_triggers.h @@ -0,0 +1,56 @@ +/***************************************************************************//** +* \file cyhal_triggers.h +* +* Description: +* Provides definitions for the triggers for each supported device family. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_psoc6_triggers Triggers +* \ingroup group_hal_psoc6 +* \{ +* Trigger connections for supported device families +*/ + +#pragma once + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +#include "cy_device.h" + +#ifdef CY_DEVICE_PSOC6ABLE2 +#include "triggers/cyhal_triggers_psoc6_01.h" +#endif + +#ifdef CY_DEVICE_PSOC6A2M +#include "triggers/cyhal_triggers_psoc6_02.h" +#endif + +#ifdef CY_DEVICE_PSOC6A512K +#include "triggers/cyhal_triggers_psoc6_03.h" +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/** \} group_hal_psoc6_triggers */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h index aafbb18b16..4d798be774 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,9 @@ * \addtogroup group_hal_trng TRNG (True Random Number Generator) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress TRNG. +* High level interface for interacting with the true random number generator (TRNG). +* +* This block uses dedicated hardware to efficiently generate truly random numbers. */ #pragma once diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h index a42176d991..44b46bdfdb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h index 4cd3f897de..6f007d031a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,27 @@ * \addtogroup group_hal_uart UART (Universal Asynchronous Receiver-Transmitter) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress UART. +* High level interface for interacting with the Universal Asynchronous Receiver-Transmitter (UART). +* +* The Universal Asynchronous Receiver/Transmitter (UART) protocol is an +* asynchronous serial interface protocol. UART communication is typically +* point-to-point. The UART interface consists of two signals: +* * TX: Transmitter output +* * RX: Receiver input +* +* Additionally, two side-band signals are used to implement flow control in +* UART. Note that the flow control applies only to TX functionality. +* * Clear to Send (CTS): This is an input signal to the transmitter. +* When active, it indicates that the slave is ready for the master to +* transmit data. +* * Ready to Send (RTS): This is an output signal from the receiver. When +* active, it indicates that the receiver is ready to receive data +* +* Flow control can be configured via cyhal_uart_set_flow_control() +* +* The data frame size, STOP bits, and parity can be configured via cyhal_uart_cfg_t. +* The UART contains dedicated hardware buffers for transmit and receive. Optionally, +* either these can be augmented with a software buffer. */ #pragma once diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h index 839f106d65..59195c2e66 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h @@ -29,8 +29,16 @@ * \addtogroup group_hal_usb_dev USB Device * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress USB Device. -* +* High level interface for interacting with the USB Device interface. +* +* This block supports one control endpoint (EP0) and one or more data endpoints +* see the device datasheet for the number of data endpoints supported. +* +* Four transfer types are supported (cyhal_usb_dev_ep_type_t): +* * Bulk +* * Interrupt +* * Isochronous +* * Control */ #pragma once @@ -45,6 +53,10 @@ extern "C" { #endif +/** + * \addtogroup group_hal_usb_dev_common Common + * \{ + */ /** The usb error */ #define CYHAL_USB_DEV_RSLT_ERR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_USB, 0)) @@ -54,7 +66,9 @@ extern "C" { /** The configuration of USB clock failed */ #define CYHAL_USB_DEV_RSLT_ERR_CLK_CFG (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_USB, 2)) -/** +/** \} group_hal_usb_dev_common */ + +/** * \addtogroup group_hal_usb_dev_endpoint Endpoint * \{ * APIs relating to endpoint management @@ -79,6 +93,11 @@ typedef enum /** \} group_hal_usb_dev_endpoint */ +/** + * \addtogroup group_hal_usb_dev_common Common + * \{ + */ + /** Service Callback Events */ typedef enum { @@ -88,20 +107,22 @@ typedef enum CYHAL_USB_DEV_EVENT_EP0_OUT, /**< Callback hooked to endpoint 0 OUT packet interrupt */ } cyhal_usb_dev_event_t; -/** - * USB endpoint address (consists from endpoint number and direction) - * - * \ingroup group_hal_usb_dev_endpoint +/** + * USB endpoint address (consists from endpoint number and direction) + * + * \ingroup group_hal_usb_dev_endpoint */ typedef uint8_t cyhal_usb_dev_ep_t; -/** Callback handler for USB Device interrupt */ +/** + * Callback handler for USB Device interrupt + */ typedef void (*cyhal_usb_dev_irq_callback_t)(void); -/** +/** * Callback handler for the transfer completion event for data endpoints (not applicable for endpoint 0) - * - * \ingroup group_hal_usb_dev_endpoint + * + * \ingroup group_hal_usb_dev_endpoint */ typedef void (* cyhal_usb_dev_endpoint_callback_t)(cyhal_usb_dev_ep_t endpoint); @@ -190,7 +211,9 @@ typedef void (*cyhal_usb_dev_sof_callback_t)(uint32_t frame_number); */ void cyhal_usb_dev_set_address(cyhal_usb_dev_t *obj, uint8_t address); -/** +/** \} group_hal_usb_dev_common */ + +/** * \addtogroup group_hal_usb_dev_ep0 EP0 * \{ * APIs relating specifically to management of endpoint zero @@ -257,7 +280,7 @@ uint32_t cyhal_usb_dev_ep0_get_max_packet(cyhal_usb_dev_t *obj); /** \} group_hal_usb_dev_ep0 */ /** - * \addtogroup group_hal_usb_dev_endpoint + * \addtogroup group_hal_usb_dev_endpoint * \{ */ @@ -382,6 +405,11 @@ cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enab /** \} group_hal_usb_dev_endpoint */ +/** + * \addtogroup group_hal_usb_dev_common Common + * \{ + */ + /** The USB Device callback handler registration * * @param[in,out] obj The usb device object @@ -412,8 +440,8 @@ void cyhal_usb_dev_process_irq(cyhal_usb_dev_t *obj); * @param[in,out] obj The usb device object * @param[in] endpoint Endpoint to registers handler * @param[in] callback The callback handler which will be invoked when the endpoint comp - * - * \ingroup group_hal_usb_dev_endpoint + * + * \ingroup group_hal_usb_dev_endpoint */ void cyhal_usb_dev_register_endpoint_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, cyhal_usb_dev_endpoint_callback_t callback); @@ -434,6 +462,8 @@ void cyhal_usb_dev_register_event_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_e */ void cyhal_usb_dev_register_sof_callback( cyhal_usb_dev_t *obj, cyhal_usb_dev_sof_callback_t callback); +/** \} group_hal_usb_dev_common */ + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h index 3f457af2fd..b6c45d1f1f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,13 +22,16 @@ * limitations under the License. *******************************************************************************/ +/** \cond INTERNAL */ /** -* \addtogroup group_hal_psoc6 PSoC 6 Implementation +* \addtogroup group_hal_psoc6 PSoC 6 Implementation Specific * \{ +* Common utility macros & functions used by multiple HAL drivers. */ #pragma once +#include "cy_result.h" #include "cyhal_hw_types.h" #include "cy_utils.h" @@ -37,16 +40,9 @@ extern "C" { #endif -/** - * \addtogroup group_hal_psoc6_interrupts Interrupts - * \{ - */ #define CYHAL_IRQN_OFFSET 16 /**< Offset for implementation-defined ISR type numbers (IRQ0 = 16) */ #define CYHAL_GET_CURRENT_IRQN() ((IRQn_Type) (__get_IPSR() - CYHAL_IRQN_OFFSET)) /**< Macro to get the IRQn of the current ISR */ -/** \} group_hal_psoc6_interrupts */ - - /** * \addtogroup group_hal_psoc6_pin_package * \{ @@ -84,21 +80,30 @@ static inline cyhal_resource_inst_t cyhal_utils_get_gpio_resource(cyhal_gpio_t p */ const cyhal_resource_pin_mapping_t *cyhal_utils_get_resource(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t* mappings, size_t count); +/** Attempts to reserve the specified pin and then initialize it to connect to the item defined by the provided mapping object. + * @param[in] pin The pin to reserve and connect + * @param[in] mapping The pin/hardware block connection mapping information + * @return CY_RSLT_SUCCESS if everything was ok, else an error. + */ +cy_rslt_t cyhal_utils_reserve_and_connect(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *mapping); + /** Disconnects any routing for the pin from the interconnect driver and then free's the pin from the hwmgr. * * @param[in] pin The pin to disconnect and free */ void cyhal_utils_disconnect_and_free(cyhal_gpio_t pin); +/** Checks to see if the provided pin is a no-connect (CYHAL_NC_PIN_VALUE). If not, calls + * cyhal_utils_disconnect_and_free(). + * + * @param[in] pin The pin to disconnect and free + */ +void cyhal_utils_release_if_used(cyhal_gpio_t *pin); + /** \} group_hal_psoc6_pin_package */ -/** -* \addtogroup group_hal_psoc6_clocks Clocks -* \{ -*/ - /** Calculate the peri clock divider value that need to be set to reach frequency closest to the input frequency - * + * * @param[in] frequency The desired frequency * @param[in] frac_bits The number of fractional bits that the divider has * @return The calculate divider value to set, NOTE a divider value of x divide the frequency by (x+1) @@ -108,7 +113,13 @@ static inline uint32_t cyhal_divider_value(uint32_t frequency, uint32_t frac_bit return ((Cy_SysClk_ClkPeriGetFrequency() * (1 << frac_bits)) + (frequency / 2)) / frequency - 1; } -/** \} group_hal_psoc6_clocks */ +/** Determine if two resources are the same + * + * @param[in] resource1 First resource to compare + * @param[in] resource2 Second resource to compare + * @return Boolean indicating whether two resources are the same + */ +bool cyhal_utils_resources_equal(const cyhal_resource_inst_t *resource1, const cyhal_resource_inst_t *resource2); #if defined(__cplusplus) } @@ -116,3 +127,4 @@ static inline uint32_t cyhal_divider_value(uint32_t frequency, uint32_t frac_bit /** \} group_hal_psoc6_utils */ /** \} group_hal_psoc6 */ +/** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h index ea82d39550..07d85c16f3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h @@ -29,7 +29,35 @@ * \addtogroup group_hal_wdt WDT (Watchdog Timer) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress WDT. +* High level interface to the Watchdog Timer (WDT). +* +* cyhal_wdt_init() initializes the WDT and passes a pointer to the WDT block through obj. +* The timeout_ms parameter takes in the timeout in milliseconds. +* It can be used for recovering from a CPU or firmware failure. + The watchdog timer is initialized with a timeout interval. Once the WDT is started, + if cyhal_wdt_kick() must be called at least once within the timeout interval. In case + the firmware fails to do so, it is considered to be a CPU crash or firmware failure and the device + will be reset. +* +* +*\section subsection_wdt_features Features +* WDT supports Device Reset generation if not serviced within the configured timeout interval. +* +* +* \section subsection_wdt_quickstart Quick Start +* +* \ref cyhal_wdt_init() can be used for initialization by providing the WDT object (obj) and the timeout parameter +* (timeout period in ms). +* The timeout parameter can have a minimum value of 1ms. The maximum value of the timeout +* parameter can be obtained using the cyhal_wdt_get_max_timeout_ms(). +* +* +* \section subsection_wdt_sample_use_case Sample use case +* +* \subsection subsection_wdt_use_case Use Case: Initialization and reset functionality +* The following snippet initializes the WDT and depicts the reset functionality of WDT in case of CPU or +* firmware failure. +* \snippet wdt.c snippet_cyhal_wdt_init_and_reset */ #pragma once @@ -54,6 +82,8 @@ extern "C" { * @param[out] obj The WDT object * @param[in] timeout_ms The time in milliseconds before the WDT times out (1ms - max) (see cyhal_wdt_get_max_timeout_ms()) * @return The status of the init request +* +* Returns \ref CY_RSLT_SUCCESS if the operation was successfull. */ cy_rslt_t cyhal_wdt_init(cyhal_wdt_t *obj, uint32_t timeout_ms); @@ -65,7 +95,9 @@ cy_rslt_t cyhal_wdt_init(cyhal_wdt_t *obj, uint32_t timeout_ms); * undefined. * * @param[inout] obj The WDT object +* */ + void cyhal_wdt_free(cyhal_wdt_t *obj); /** Refresh the WDT @@ -74,11 +106,13 @@ void cyhal_wdt_free(cyhal_wdt_t *obj); * In the event of a timeout, the WDT resets the system. * * @param[inout] obj The WDT object +* +* See \ref subsection_wdt_use_case */ void cyhal_wdt_kick(cyhal_wdt_t *obj); /** Start the WDT -* +* * Enables the WDT. * * @param[inout] obj The WDT object @@ -87,7 +121,7 @@ void cyhal_wdt_kick(cyhal_wdt_t *obj); void cyhal_wdt_start(cyhal_wdt_t *obj); /** Stop the WDT -* +* * Disables the WDT. * * @param[inout] obj The WDT object @@ -98,13 +132,13 @@ void cyhal_wdt_stop(cyhal_wdt_t *obj); /** Get the WDT timeout * * Gets the time in milliseconds before the WDT times out. -* +* * @param[inout] obj The WDT object * @return The time in milliseconds before the WDT times out */ uint32_t cyhal_wdt_get_timeout_ms(cyhal_wdt_t *obj); -/** Gets the maximum WDT timeout +/** Gets the maximum WDT timeout * * Gets the maximum timeout for the WDT. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h index c45650269f..23d2e856c6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,97 +30,107 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_104_m_csp_ble PSoC6_01 104-M-CSP-BLE + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 104-M-CSP-BLE package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), -} cyhal_gpio_t; + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 +} cyhal_gpio_psoc6_01_104_m_csp_ble_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_104_m_csp_ble_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -132,90 +142,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[12]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[6]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[12]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[6]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[11]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[68]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[68]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_104_M_CSP_BLE_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h index d09252f424..cd4fb18d4a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE-USB package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,99 +30,109 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_104_m_csp_ble_usb PSoC6_01 104-M-CSP-BLE-USB + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 104-M-CSP-BLE-USB package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_01_104_m_csp_ble_usb_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_104_m_csp_ble_usb_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -134,90 +144,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[12]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[12]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[6]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[12]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[12]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[6]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[68]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[66]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_104_M_CSP_BLE_USB_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h index 0dc0fa4c2d..7fa08a272e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 116-BGA-BLE package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,105 +30,115 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_116_bga_ble PSoC6_01 116-BGA-BLE + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 116-BGA-BLE package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), - P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 + P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), -} cyhal_gpio_t; + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 +} cyhal_gpio_psoc6_01_116_bga_ble_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_116_bga_ble_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -140,90 +150,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[11]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[11]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[78]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[74]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_116_BGA_BLE_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h index d615df7c83..c094b0d3d4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 116-BGA-USB package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,105 +30,115 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_116_bga_usb PSoC6_01 116-BGA-USB + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 116-BGA-USB package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_01_116_bga_usb_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_116_bga_usb_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -140,90 +150,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[12]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[12]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[11]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[76]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[70]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_116_BGA_USB_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h index 55b576ad6a..cc40e138c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 124-BGA package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,133 +30,143 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_124_bga PSoC6_01 124-BGA + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 124-BGA package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), - P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 + P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 - P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), - P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), - P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), - P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), - P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), - P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), + P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 + P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 + P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 + P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 + P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 + P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5 - P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), - P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), + P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 + P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), - P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), - P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), - P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 + P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 + P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 + P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_01_124_bga_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_124_bga_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -168,90 +178,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[17]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[16]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[16]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[14]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[14]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[15]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[15]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[98]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[98]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_124_BGA_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h index ab95e612f2..29cf77d337 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 124-BGA-SIP package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,114 +30,124 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_124_bga_sip PSoC6_01 124-BGA-SIP + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 124-BGA-SIP package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), - P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 + P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), - P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), - P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), - P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 + P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 + P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 + P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_01_124_bga_sip_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_124_bga_sip_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -149,90 +159,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[9]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[12]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[12]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[82]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[82]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_124_BGA_SIP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h index 07646d2fee..45dc91b498 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 43-SMT package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,59 +30,69 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_43_smt PSoC6_01 43-SMT + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 43-SMT package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), -} cyhal_gpio_t; + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 +} cyhal_gpio_psoc6_01_43_smt_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_43_smt_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -94,90 +104,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[7]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[5]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[6]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[6]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[5]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[6]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[4]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[5]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[34]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_43_SMT_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h index 3e3df464af..011c6a7035 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 68-QFN-BLE package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,65 +30,75 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_68_qfn_ble PSoC6_01 68-QFN-BLE + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 68-QFN-BLE package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), -} cyhal_gpio_t; + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 +} cyhal_gpio_psoc6_01_68_qfn_ble_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_68_qfn_ble_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -100,90 +110,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[2]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[4]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[3]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[3]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[3]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[3]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[8]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[8]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[40]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[38]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_68_QFN_BLE_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h index b5d10fba7f..1460a23a72 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 80-WLCSP package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,91 +30,101 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_80_wlcsp PSoC6_01 80-WLCSP + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 80-WLCSP package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_01_80_wlcsp_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_80_wlcsp_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -126,90 +136,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[6]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[4]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[13]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[6]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[6]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[9]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[9]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[60]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[60]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_80_WLCSP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h index ddfc61981e..ce59f33ceb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO HAL header for 100-WLCSP package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21305 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,113 +30,123 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_02_100_wlcsp PSoC6_02 100-WLCSP + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 100-WLCSP package for the PSoC6_02 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), - P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), - P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), - P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 + P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 + P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 + P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_02_100_wlcsp_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_02_100_wlcsp_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -148,74 +158,139 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[19]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[18]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[15]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[15]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[7]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[15]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[15]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[7]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[15]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[15]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[17]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[16]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2]; +/** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1]; +/** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[80]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[80]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_02_100_WLCSP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h index 9ff888efd7..61ff82afb5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO HAL header for 124-BGA package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21305 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,133 +30,143 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_02_124_bga PSoC6_02 124-BGA + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 124-BGA package for the PSoC6_02 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), - P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 + P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 - P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), - P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), - P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), - P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), - P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), - P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), + P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 + P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 + P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 + P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 + P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 + P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5 - P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), - P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), + P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 + P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), - P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), - P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), - P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 + P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 + P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 + P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_02_124_bga_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_02_124_bga_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -168,74 +178,139 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[4]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[4]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[21]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[21]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[16]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[16]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[18]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[18]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[19]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[19]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2]; +/** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2]; +/** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[98]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[98]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_02_124_BGA_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h index d349f4561f..aa69176af6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO HAL header for 128-TQFP package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21305 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,135 +30,145 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_02_128_tqfp PSoC6_02 128-TQFP + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 128-TQFP package for the PSoC6_02 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), - P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 + P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 - P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), - P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), - P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), - P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), - P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), - P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), + P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 + P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 + P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 + P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 + P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 + P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5 - P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), - P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), - P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), - P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), + P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 + P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 + P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), //!< Port 4 Pin 2 + P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), //!< Port 4 Pin 3 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), - P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), - P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), - P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 + P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 + P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 + P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_02_128_tqfp_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_02_128_tqfp_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -170,74 +180,139 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[4]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[4]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[21]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[21]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[19]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[19]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[19]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[19]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2]; +/** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2]; +/** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[100]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[100]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_02_128_TQFP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h index 03a3942097..e357bd6001 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO HAL header for 68-QFN package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21305 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,83 +30,93 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_02_68_qfn PSoC6_02 68-QFN + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 68-QFN package for the PSoC6_02 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 - P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), - P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), + P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 + P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_02_68_qfn_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_02_68_qfn_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -118,74 +128,139 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[2]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[2]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[2]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[12]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[5]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[1]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2]; +/** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[50]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[52]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_02_68_QFN_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h index 3f22c20b98..1b7beec913 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h @@ -5,11 +5,11 @@ * PSoC6_03 device GPIO HAL header for 100-TQFP package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21421 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,94 +30,104 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_03_100_tqfp PSoC6_03 100-TQFP + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 100-TQFP package for the PSoC6_03 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 - P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), - P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), + P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 + P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_03_100_tqfp_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_03_100_tqfp_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -129,59 +139,109 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1]; -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1]; +/** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1]; +/** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[12]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[5]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[8]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[8]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[10]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[10]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[64]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[64]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_03_100_TQFP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h index 91aa011c1c..ff9574eea0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h @@ -5,11 +5,11 @@ * PSoC6_03 device GPIO HAL header for 49-WLCSP package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21421 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,61 +30,71 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_03_49_wlcsp PSoC6_03 49-WLCSP + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 50-WLCSP package for the PSoC6_03 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), -} cyhal_gpio_t; + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 +} cyhal_gpio_psoc6_03_49_wlcsp_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_03_49_wlcsp_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -96,59 +106,109 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1]; -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1]; +/** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1]; +/** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[6]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[6]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[7]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[6]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[6]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[7]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[1]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[7]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[6]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[6]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[7]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[1]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[6]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[5]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[5]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[36]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_03_49_WLCSP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h index 685c10717d..ee64b6d1f0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h @@ -5,11 +5,11 @@ * PSoC6_03 device GPIO HAL header for 68-QFN package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21421 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,83 +30,93 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_03_68_qfn PSoC6_03 68-QFN + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 68-QFN package for the PSoC6_03 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 - P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), - P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), + P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 + P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_03_68_qfn_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_03_68_qfn_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -118,59 +128,109 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1]; -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1]; +/** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1]; +/** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[4]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[2]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[2]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[7]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[9]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[9]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[52]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[54]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_03_68_QFN_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_01.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_01.h new file mode 100644 index 0000000000..17ae553ad1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_01.h @@ -0,0 +1,547 @@ +/***************************************************************************//** +* \file cyhal_triggers_psoc6_01.h +* +* \brief +* PSoC6_01 family HAL triggers header +* +* \note +* Generator version: 1.5.7254.19579 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYHAL_TRIGGERS_PSOC6_01_H_ +#define _CYHAL_TRIGGERS_PSOC6_01_H_ + +/** + * \addtogroup group_hal_psoc6_triggers_psoc6_01 PSOC6_01 + * \ingroup group_hal_psoc6_triggers + * \{ + * Trigger connections for psoc6_01 + */ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** @brief Name of each output trigger. */ +typedef enum +{ + TRIGGER_CPUSS_CTI_TR_IN0 = 0, //!< CPUSS Cross-Triggering-Interface trigger multiplexer (CTI) - cpuss.cti_tr_in[0] + TRIGGER_CPUSS_CTI_TR_IN1 = 1, //!< CPUSS Cross-Triggering-Interface trigger multiplexer (CTI) - cpuss.cti_tr_in[1] + TRIGGER_CPUSS_DW0_TR_IN0 = 2, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[0] + TRIGGER_CPUSS_DW0_TR_IN1 = 3, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[1] + TRIGGER_CPUSS_DW0_TR_IN2 = 4, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[2] + TRIGGER_CPUSS_DW0_TR_IN3 = 5, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[3] + TRIGGER_CPUSS_DW0_TR_IN4 = 6, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[4] + TRIGGER_CPUSS_DW0_TR_IN5 = 7, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[5] + TRIGGER_CPUSS_DW0_TR_IN6 = 8, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[6] + TRIGGER_CPUSS_DW0_TR_IN7 = 9, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[7] + TRIGGER_CPUSS_DW0_TR_IN8 = 10, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[8] + TRIGGER_CPUSS_DW0_TR_IN9 = 11, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[9] + TRIGGER_CPUSS_DW0_TR_IN10 = 12, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[10] + TRIGGER_CPUSS_DW0_TR_IN11 = 13, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[11] + TRIGGER_CPUSS_DW0_TR_IN12 = 14, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[12] + TRIGGER_CPUSS_DW0_TR_IN13 = 15, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[13] + TRIGGER_CPUSS_DW0_TR_IN14 = 16, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[14] + TRIGGER_CPUSS_DW0_TR_IN15 = 17, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[15] + TRIGGER_CPUSS_DW1_TR_IN0 = 18, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[0] + TRIGGER_CPUSS_DW1_TR_IN1 = 19, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[1] + TRIGGER_CPUSS_DW1_TR_IN2 = 20, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[2] + TRIGGER_CPUSS_DW1_TR_IN3 = 21, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[3] + TRIGGER_CPUSS_DW1_TR_IN4 = 22, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[4] + TRIGGER_CPUSS_DW1_TR_IN5 = 23, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[5] + TRIGGER_CPUSS_DW1_TR_IN6 = 24, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[6] + TRIGGER_CPUSS_DW1_TR_IN7 = 25, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[7] + TRIGGER_CPUSS_DW1_TR_IN8 = 26, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[8] + TRIGGER_CPUSS_DW1_TR_IN9 = 27, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[9] + TRIGGER_CPUSS_DW1_TR_IN10 = 28, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[10] + TRIGGER_CPUSS_DW1_TR_IN11 = 29, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[11] + TRIGGER_CPUSS_DW1_TR_IN12 = 30, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[12] + TRIGGER_CPUSS_DW1_TR_IN13 = 31, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[13] + TRIGGER_CPUSS_DW1_TR_IN14 = 32, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[14] + TRIGGER_CPUSS_DW1_TR_IN15 = 33, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[15] + TRIGGER_PASS_TR_SAR_IN = 34, //!< PASS trigger multiplexer - pass.tr_sar_in + TRIGGER_PERI_TR_IO_OUTPUT0 = 35, //!< GPIO/HSIOM trigger multiplexer - peri.tr_io_output[0] + TRIGGER_PERI_TR_IO_OUTPUT1 = 36, //!< GPIO/HSIOM trigger multiplexer - peri.tr_io_output[1] + TRIGGER_PROFILE_TR_START = 37, //!< PROFILE trigger multiplexer - profile.tr_start + TRIGGER_PROFILE_TR_STOP = 38, //!< PROFILE trigger multiplexer - profile.tr_stop + TRIGGER_TCPWM0_TR_IN0 = 39, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[0] + TRIGGER_TCPWM0_TR_IN1 = 40, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[1] + TRIGGER_TCPWM0_TR_IN2 = 41, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[2] + TRIGGER_TCPWM0_TR_IN3 = 42, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[3] + TRIGGER_TCPWM0_TR_IN4 = 43, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[4] + TRIGGER_TCPWM0_TR_IN5 = 44, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[5] + TRIGGER_TCPWM0_TR_IN6 = 45, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[6] + TRIGGER_TCPWM0_TR_IN7 = 46, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[7] + TRIGGER_TCPWM0_TR_IN8 = 47, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[8] + TRIGGER_TCPWM0_TR_IN9 = 48, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[9] + TRIGGER_TCPWM0_TR_IN10 = 49, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[10] + TRIGGER_TCPWM0_TR_IN11 = 50, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[11] + TRIGGER_TCPWM0_TR_IN12 = 51, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[12] + TRIGGER_TCPWM0_TR_IN13 = 52, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[13] + TRIGGER_TCPWM1_TR_IN0 = 53, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[0] + TRIGGER_TCPWM1_TR_IN1 = 54, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[1] + TRIGGER_TCPWM1_TR_IN2 = 55, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[2] + TRIGGER_TCPWM1_TR_IN3 = 56, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[3] + TRIGGER_TCPWM1_TR_IN4 = 57, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[4] + TRIGGER_TCPWM1_TR_IN5 = 58, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[5] + TRIGGER_TCPWM1_TR_IN6 = 59, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[6] + TRIGGER_TCPWM1_TR_IN7 = 60, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[7] + TRIGGER_TCPWM1_TR_IN8 = 61, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[8] + TRIGGER_TCPWM1_TR_IN9 = 62, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[9] + TRIGGER_TCPWM1_TR_IN10 = 63, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[10] + TRIGGER_TCPWM1_TR_IN11 = 64, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[11] + TRIGGER_TCPWM1_TR_IN12 = 65, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[12] + TRIGGER_TCPWM1_TR_IN13 = 66, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[13] + TRIGGER_TR_GROUP0_INPUT1 = 67, //!< Datawire output trigger reduction mux - tr_group[0].input[1] + TRIGGER_TR_GROUP0_INPUT2 = 68, //!< Datawire output trigger reduction mux - tr_group[0].input[2] + TRIGGER_TR_GROUP0_INPUT3 = 69, //!< Datawire output trigger reduction mux - tr_group[0].input[3] + TRIGGER_TR_GROUP0_INPUT4 = 70, //!< Datawire output trigger reduction mux - tr_group[0].input[4] + TRIGGER_TR_GROUP0_INPUT5 = 71, //!< Datawire output trigger reduction mux - tr_group[0].input[5] + TRIGGER_TR_GROUP0_INPUT6 = 72, //!< Datawire output trigger reduction mux - tr_group[0].input[6] + TRIGGER_TR_GROUP0_INPUT7 = 73, //!< Datawire output trigger reduction mux - tr_group[0].input[7] + TRIGGER_TR_GROUP0_INPUT8 = 74, //!< Datawire output trigger reduction mux - tr_group[0].input[8] + TRIGGER_TR_GROUP0_INPUT9 = 75, //!< TCPWM trigger output reduction mux - tr_group[0].input[9] + TRIGGER_TR_GROUP0_INPUT10 = 76, //!< TCPWM trigger output reduction mux - tr_group[0].input[10] + TRIGGER_TR_GROUP0_INPUT11 = 77, //!< TCPWM trigger output reduction mux - tr_group[0].input[11] + TRIGGER_TR_GROUP0_INPUT12 = 78, //!< TCPWM trigger output reduction mux - tr_group[0].input[12] + TRIGGER_TR_GROUP0_INPUT13 = 79, //!< TCPWM trigger output reduction mux - tr_group[0].input[13] + TRIGGER_TR_GROUP0_INPUT14 = 80, //!< TCPWM trigger output reduction mux - tr_group[0].input[14] + TRIGGER_TR_GROUP0_INPUT15 = 81, //!< TCPWM trigger output reduction mux - tr_group[0].input[15] + TRIGGER_TR_GROUP0_INPUT16 = 82, //!< TCPWM trigger output reduction mux - tr_group[0].input[16] + TRIGGER_TR_GROUP0_INPUT17 = 83, //!< TCPWM trigger output reduction mux - tr_group[0].input[17] + TRIGGER_TR_GROUP0_INPUT18 = 84, //!< TCPWM trigger output reduction mux - tr_group[0].input[18] + TRIGGER_TR_GROUP0_INPUT19 = 85, //!< TCPWM trigger output reduction mux - tr_group[0].input[19] + TRIGGER_TR_GROUP0_INPUT20 = 86, //!< TCPWM trigger output reduction mux - tr_group[0].input[20] + TRIGGER_TR_GROUP0_INPUT21 = 87, //!< TCPWM trigger output reduction mux - tr_group[0].input[21] + TRIGGER_TR_GROUP0_INPUT22 = 88, //!< TCPWM trigger output reduction mux - tr_group[0].input[22] + TRIGGER_TR_GROUP0_INPUT23 = 89, //!< TCPWM trigger output reduction mux - tr_group[0].input[23] + TRIGGER_TR_GROUP0_INPUT24 = 90, //!< TCPWM trigger output reduction mux - tr_group[0].input[24] + TRIGGER_TR_GROUP0_INPUT25 = 91, //!< HSIOM Pin input reduction mux - tr_group[0].input[25] + TRIGGER_TR_GROUP0_INPUT26 = 92, //!< HSIOM Pin input reduction mux - tr_group[0].input[26] + TRIGGER_TR_GROUP0_INPUT27 = 93, //!< DMA request reduction mux - tr_group[0].input[27] + TRIGGER_TR_GROUP0_INPUT28 = 94, //!< DMA request reduction mux - tr_group[0].input[28] + TRIGGER_TR_GROUP0_INPUT29 = 95, //!< DMA request reduction mux - tr_group[0].input[29] + TRIGGER_TR_GROUP0_INPUT30 = 96, //!< DMA request reduction mux - tr_group[0].input[30] + TRIGGER_TR_GROUP0_INPUT31 = 97, //!< DMA request reduction mux - tr_group[0].input[31] + TRIGGER_TR_GROUP0_INPUT32 = 98, //!< DMA request reduction mux - tr_group[0].input[32] + TRIGGER_TR_GROUP0_INPUT33 = 99, //!< DMA request reduction mux - tr_group[0].input[33] + TRIGGER_TR_GROUP0_INPUT34 = 100, //!< DMA request reduction mux - tr_group[0].input[34] + TRIGGER_TR_GROUP0_INPUT35 = 101, //!< DMA request reduction mux - tr_group[0].input[35] + TRIGGER_TR_GROUP0_INPUT36 = 102, //!< DMA request reduction mux - tr_group[0].input[36] + TRIGGER_TR_GROUP0_INPUT37 = 103, //!< DMA request reduction mux - tr_group[0].input[37] + TRIGGER_TR_GROUP0_INPUT38 = 104, //!< DMA request reduction mux - tr_group[0].input[38] + TRIGGER_TR_GROUP0_INPUT39 = 105, //!< DMA request reduction mux - tr_group[0].input[39] + TRIGGER_TR_GROUP0_INPUT40 = 106, //!< DMA request reduction mux - tr_group[0].input[40] + TRIGGER_TR_GROUP0_INPUT41 = 107, //!< DMA request reduction mux - tr_group[0].input[41] + TRIGGER_TR_GROUP0_INPUT42 = 108, //!< DMA request reduction mux - tr_group[0].input[42] + TRIGGER_TR_GROUP0_INPUT43 = 109, //!< Trigger input reduction mux - tr_group[0].input[43] + TRIGGER_TR_GROUP0_INPUT44 = 110, //!< Trigger input reduction mux - tr_group[0].input[44] + TRIGGER_TR_GROUP0_INPUT45 = 111, //!< Trigger input reduction mux - tr_group[0].input[45] + TRIGGER_TR_GROUP0_INPUT46 = 112, //!< Trigger input reduction mux - tr_group[0].input[46] + TRIGGER_TR_GROUP0_INPUT47 = 113, //!< Trigger input reduction mux - tr_group[0].input[47] + TRIGGER_TR_GROUP0_INPUT48 = 114, //!< Trigger input reduction mux - tr_group[0].input[48] + TRIGGER_TR_GROUP0_INPUT49 = 115, //!< Trigger input reduction mux - tr_group[0].input[49] + TRIGGER_TR_GROUP0_INPUT50 = 116, //!< Trigger input reduction mux - tr_group[0].input[50] + TRIGGER_TR_GROUP1_INPUT1 = 117, //!< Datawire output trigger reduction mux - tr_group[1].input[1] + TRIGGER_TR_GROUP1_INPUT2 = 118, //!< Datawire output trigger reduction mux - tr_group[1].input[2] + TRIGGER_TR_GROUP1_INPUT3 = 119, //!< Datawire output trigger reduction mux - tr_group[1].input[3] + TRIGGER_TR_GROUP1_INPUT4 = 120, //!< Datawire output trigger reduction mux - tr_group[1].input[4] + TRIGGER_TR_GROUP1_INPUT5 = 121, //!< Datawire output trigger reduction mux - tr_group[1].input[5] + TRIGGER_TR_GROUP1_INPUT6 = 122, //!< Datawire output trigger reduction mux - tr_group[1].input[6] + TRIGGER_TR_GROUP1_INPUT7 = 123, //!< Datawire output trigger reduction mux - tr_group[1].input[7] + TRIGGER_TR_GROUP1_INPUT8 = 124, //!< Datawire output trigger reduction mux - tr_group[1].input[8] + TRIGGER_TR_GROUP1_INPUT9 = 125, //!< TCPWM trigger output reduction mux - tr_group[1].input[9] + TRIGGER_TR_GROUP1_INPUT10 = 126, //!< TCPWM trigger output reduction mux - tr_group[1].input[10] + TRIGGER_TR_GROUP1_INPUT11 = 127, //!< TCPWM trigger output reduction mux - tr_group[1].input[11] + TRIGGER_TR_GROUP1_INPUT12 = 128, //!< TCPWM trigger output reduction mux - tr_group[1].input[12] + TRIGGER_TR_GROUP1_INPUT13 = 129, //!< TCPWM trigger output reduction mux - tr_group[1].input[13] + TRIGGER_TR_GROUP1_INPUT14 = 130, //!< TCPWM trigger output reduction mux - tr_group[1].input[14] + TRIGGER_TR_GROUP1_INPUT15 = 131, //!< TCPWM trigger output reduction mux - tr_group[1].input[15] + TRIGGER_TR_GROUP1_INPUT16 = 132, //!< TCPWM trigger output reduction mux - tr_group[1].input[16] + TRIGGER_TR_GROUP1_INPUT17 = 133, //!< TCPWM trigger output reduction mux - tr_group[1].input[17] + TRIGGER_TR_GROUP1_INPUT18 = 134, //!< TCPWM trigger output reduction mux - tr_group[1].input[18] + TRIGGER_TR_GROUP1_INPUT19 = 135, //!< TCPWM trigger output reduction mux - tr_group[1].input[19] + TRIGGER_TR_GROUP1_INPUT20 = 136, //!< TCPWM trigger output reduction mux - tr_group[1].input[20] + TRIGGER_TR_GROUP1_INPUT21 = 137, //!< TCPWM trigger output reduction mux - tr_group[1].input[21] + TRIGGER_TR_GROUP1_INPUT22 = 138, //!< TCPWM trigger output reduction mux - tr_group[1].input[22] + TRIGGER_TR_GROUP1_INPUT23 = 139, //!< TCPWM trigger output reduction mux - tr_group[1].input[23] + TRIGGER_TR_GROUP1_INPUT24 = 140, //!< TCPWM trigger output reduction mux - tr_group[1].input[24] + TRIGGER_TR_GROUP1_INPUT25 = 141, //!< HSIOM Pin input reduction mux - tr_group[1].input[25] + TRIGGER_TR_GROUP1_INPUT26 = 142, //!< HSIOM Pin input reduction mux - tr_group[1].input[26] + TRIGGER_TR_GROUP1_INPUT27 = 143, //!< DMA request reduction mux - tr_group[1].input[27] + TRIGGER_TR_GROUP1_INPUT28 = 144, //!< DMA request reduction mux - tr_group[1].input[28] + TRIGGER_TR_GROUP1_INPUT29 = 145, //!< DMA request reduction mux - tr_group[1].input[29] + TRIGGER_TR_GROUP1_INPUT30 = 146, //!< DMA request reduction mux - tr_group[1].input[30] + TRIGGER_TR_GROUP1_INPUT31 = 147, //!< DMA request reduction mux - tr_group[1].input[31] + TRIGGER_TR_GROUP1_INPUT32 = 148, //!< DMA request reduction mux - tr_group[1].input[32] + TRIGGER_TR_GROUP1_INPUT33 = 149, //!< DMA request reduction mux - tr_group[1].input[33] + TRIGGER_TR_GROUP1_INPUT34 = 150, //!< DMA request reduction mux - tr_group[1].input[34] + TRIGGER_TR_GROUP1_INPUT35 = 151, //!< DMA request reduction mux - tr_group[1].input[35] + TRIGGER_TR_GROUP1_INPUT36 = 152, //!< DMA request reduction mux - tr_group[1].input[36] + TRIGGER_TR_GROUP1_INPUT37 = 153, //!< DMA request reduction mux - tr_group[1].input[37] + TRIGGER_TR_GROUP1_INPUT38 = 154, //!< DMA request reduction mux - tr_group[1].input[38] + TRIGGER_TR_GROUP1_INPUT39 = 155, //!< DMA request reduction mux - tr_group[1].input[39] + TRIGGER_TR_GROUP1_INPUT40 = 156, //!< DMA request reduction mux - tr_group[1].input[40] + TRIGGER_TR_GROUP1_INPUT41 = 157, //!< DMA request reduction mux - tr_group[1].input[41] + TRIGGER_TR_GROUP1_INPUT42 = 158, //!< DMA request reduction mux - tr_group[1].input[42] + TRIGGER_TR_GROUP1_INPUT43 = 159, //!< Trigger input reduction mux - tr_group[1].input[43] + TRIGGER_TR_GROUP1_INPUT44 = 160, //!< Trigger input reduction mux - tr_group[1].input[44] + TRIGGER_TR_GROUP1_INPUT45 = 161, //!< Trigger input reduction mux - tr_group[1].input[45] + TRIGGER_TR_GROUP1_INPUT46 = 162, //!< Trigger input reduction mux - tr_group[1].input[46] + TRIGGER_TR_GROUP1_INPUT47 = 163, //!< Trigger input reduction mux - tr_group[1].input[47] + TRIGGER_TR_GROUP1_INPUT48 = 164, //!< Trigger input reduction mux - tr_group[1].input[48] + TRIGGER_TR_GROUP1_INPUT49 = 165, //!< Trigger input reduction mux - tr_group[1].input[49] + TRIGGER_TR_GROUP1_INPUT50 = 166, //!< Trigger input reduction mux - tr_group[1].input[50] + TRIGGER_TR_GROUP2_INPUT1 = 167, //!< Datawire output trigger reduction mux - tr_group[2].input[1] + TRIGGER_TR_GROUP2_INPUT2 = 168, //!< Datawire output trigger reduction mux - tr_group[2].input[2] + TRIGGER_TR_GROUP2_INPUT3 = 169, //!< Datawire output trigger reduction mux - tr_group[2].input[3] + TRIGGER_TR_GROUP2_INPUT4 = 170, //!< Datawire output trigger reduction mux - tr_group[2].input[4] + TRIGGER_TR_GROUP2_INPUT5 = 171, //!< Datawire output trigger reduction mux - tr_group[2].input[5] + TRIGGER_TR_GROUP2_INPUT6 = 172, //!< Datawire output trigger reduction mux - tr_group[2].input[6] + TRIGGER_TR_GROUP2_INPUT7 = 173, //!< Datawire output trigger reduction mux - tr_group[2].input[7] + TRIGGER_TR_GROUP2_INPUT8 = 174, //!< Datawire output trigger reduction mux - tr_group[2].input[8] + TRIGGER_TR_GROUP2_INPUT9 = 175, //!< TCPWM trigger output reduction mux - tr_group[2].input[9] + TRIGGER_TR_GROUP2_INPUT10 = 176, //!< TCPWM trigger output reduction mux - tr_group[2].input[10] + TRIGGER_TR_GROUP2_INPUT11 = 177, //!< TCPWM trigger output reduction mux - tr_group[2].input[11] + TRIGGER_TR_GROUP2_INPUT12 = 178, //!< TCPWM trigger output reduction mux - tr_group[2].input[12] + TRIGGER_TR_GROUP2_INPUT13 = 179, //!< TCPWM trigger output reduction mux - tr_group[2].input[13] + TRIGGER_TR_GROUP2_INPUT14 = 180, //!< TCPWM trigger output reduction mux - tr_group[2].input[14] + TRIGGER_TR_GROUP2_INPUT15 = 181, //!< TCPWM trigger output reduction mux - tr_group[2].input[15] + TRIGGER_TR_GROUP2_INPUT16 = 182, //!< TCPWM trigger output reduction mux - tr_group[2].input[16] + TRIGGER_TR_GROUP2_INPUT17 = 183, //!< TCPWM trigger output reduction mux - tr_group[2].input[17] + TRIGGER_TR_GROUP2_INPUT18 = 184, //!< TCPWM trigger output reduction mux - tr_group[2].input[18] + TRIGGER_TR_GROUP2_INPUT19 = 185, //!< TCPWM trigger output reduction mux - tr_group[2].input[19] + TRIGGER_TR_GROUP2_INPUT20 = 186, //!< TCPWM trigger output reduction mux - tr_group[2].input[20] + TRIGGER_TR_GROUP2_INPUT21 = 187, //!< TCPWM trigger output reduction mux - tr_group[2].input[21] + TRIGGER_TR_GROUP2_INPUT22 = 188, //!< TCPWM trigger output reduction mux - tr_group[2].input[22] + TRIGGER_TR_GROUP2_INPUT23 = 189, //!< TCPWM trigger output reduction mux - tr_group[2].input[23] + TRIGGER_TR_GROUP2_INPUT24 = 190, //!< TCPWM trigger output reduction mux - tr_group[2].input[24] + TRIGGER_TR_GROUP2_INPUT25 = 191, //!< HSIOM Pin input reduction mux - tr_group[2].input[25] + TRIGGER_TR_GROUP2_INPUT26 = 192, //!< HSIOM Pin input reduction mux - tr_group[2].input[26] + TRIGGER_TR_GROUP2_INPUT27 = 193, //!< HSIOM Pin input reduction mux - tr_group[2].input[27] + TRIGGER_TR_GROUP2_INPUT28 = 194, //!< HSIOM Pin input reduction mux - tr_group[2].input[28] + TRIGGER_TR_GROUP2_INPUT29 = 195, //!< HSIOM Pin input reduction mux - tr_group[2].input[29] + TRIGGER_TR_GROUP2_INPUT30 = 196, //!< HSIOM Pin input reduction mux - tr_group[2].input[30] + TRIGGER_TR_GROUP2_INPUT31 = 197, //!< HSIOM Pin input reduction mux - tr_group[2].input[31] + TRIGGER_TR_GROUP2_INPUT32 = 198, //!< HSIOM Pin input reduction mux - tr_group[2].input[32] + TRIGGER_TR_GROUP2_INPUT33 = 199, //!< DMA request reduction mux - tr_group[2].input[33] + TRIGGER_TR_GROUP2_INPUT34 = 200, //!< DMA request reduction mux - tr_group[2].input[34] + TRIGGER_TR_GROUP2_INPUT35 = 201, //!< Trigger input reduction mux - tr_group[2].input[35] + TRIGGER_TR_GROUP2_INPUT36 = 202, //!< Trigger input reduction mux - tr_group[2].input[36] + TRIGGER_TR_GROUP2_INPUT37 = 203, //!< Trigger input reduction mux - tr_group[2].input[37] + TRIGGER_TR_GROUP2_INPUT38 = 204, //!< Trigger input reduction mux - tr_group[2].input[38] + TRIGGER_TR_GROUP2_INPUT39 = 205, //!< Trigger input reduction mux - tr_group[2].input[39] + TRIGGER_TR_GROUP2_INPUT40 = 206, //!< Trigger input reduction mux - tr_group[2].input[40] + TRIGGER_TR_GROUP2_INPUT41 = 207, //!< Trigger input reduction mux - tr_group[2].input[41] + TRIGGER_TR_GROUP2_INPUT42 = 208, //!< Trigger input reduction mux - tr_group[2].input[42] + TRIGGER_TR_GROUP3_INPUT1 = 209, //!< Datawire output trigger reduction mux - tr_group[3].input[1] + TRIGGER_TR_GROUP3_INPUT2 = 210, //!< Datawire output trigger reduction mux - tr_group[3].input[2] + TRIGGER_TR_GROUP3_INPUT3 = 211, //!< Datawire output trigger reduction mux - tr_group[3].input[3] + TRIGGER_TR_GROUP3_INPUT4 = 212, //!< Datawire output trigger reduction mux - tr_group[3].input[4] + TRIGGER_TR_GROUP3_INPUT5 = 213, //!< Datawire output trigger reduction mux - tr_group[3].input[5] + TRIGGER_TR_GROUP3_INPUT6 = 214, //!< Datawire output trigger reduction mux - tr_group[3].input[6] + TRIGGER_TR_GROUP3_INPUT7 = 215, //!< Datawire output trigger reduction mux - tr_group[3].input[7] + TRIGGER_TR_GROUP3_INPUT8 = 216, //!< Datawire output trigger reduction mux - tr_group[3].input[8] + TRIGGER_TR_GROUP3_INPUT9 = 217, //!< TCPWM trigger output reduction mux - tr_group[3].input[9] + TRIGGER_TR_GROUP3_INPUT10 = 218, //!< TCPWM trigger output reduction mux - tr_group[3].input[10] + TRIGGER_TR_GROUP3_INPUT11 = 219, //!< TCPWM trigger output reduction mux - tr_group[3].input[11] + TRIGGER_TR_GROUP3_INPUT12 = 220, //!< TCPWM trigger output reduction mux - tr_group[3].input[12] + TRIGGER_TR_GROUP3_INPUT13 = 221, //!< TCPWM trigger output reduction mux - tr_group[3].input[13] + TRIGGER_TR_GROUP3_INPUT14 = 222, //!< TCPWM trigger output reduction mux - tr_group[3].input[14] + TRIGGER_TR_GROUP3_INPUT15 = 223, //!< TCPWM trigger output reduction mux - tr_group[3].input[15] + TRIGGER_TR_GROUP3_INPUT16 = 224, //!< TCPWM trigger output reduction mux - tr_group[3].input[16] + TRIGGER_TR_GROUP3_INPUT17 = 225, //!< TCPWM trigger output reduction mux - tr_group[3].input[17] + TRIGGER_TR_GROUP3_INPUT18 = 226, //!< TCPWM trigger output reduction mux - tr_group[3].input[18] + TRIGGER_TR_GROUP3_INPUT19 = 227, //!< TCPWM trigger output reduction mux - tr_group[3].input[19] + TRIGGER_TR_GROUP3_INPUT20 = 228, //!< TCPWM trigger output reduction mux - tr_group[3].input[20] + TRIGGER_TR_GROUP3_INPUT21 = 229, //!< TCPWM trigger output reduction mux - tr_group[3].input[21] + TRIGGER_TR_GROUP3_INPUT22 = 230, //!< TCPWM trigger output reduction mux - tr_group[3].input[22] + TRIGGER_TR_GROUP3_INPUT23 = 231, //!< TCPWM trigger output reduction mux - tr_group[3].input[23] + TRIGGER_TR_GROUP3_INPUT24 = 232, //!< TCPWM trigger output reduction mux - tr_group[3].input[24] + TRIGGER_TR_GROUP3_INPUT25 = 233, //!< HSIOM Pin input reduction mux - tr_group[3].input[25] + TRIGGER_TR_GROUP3_INPUT26 = 234, //!< HSIOM Pin input reduction mux - tr_group[3].input[26] + TRIGGER_TR_GROUP3_INPUT27 = 235, //!< HSIOM Pin input reduction mux - tr_group[3].input[27] + TRIGGER_TR_GROUP3_INPUT28 = 236, //!< HSIOM Pin input reduction mux - tr_group[3].input[28] + TRIGGER_TR_GROUP3_INPUT29 = 237, //!< HSIOM Pin input reduction mux - tr_group[3].input[29] + TRIGGER_TR_GROUP3_INPUT30 = 238, //!< HSIOM Pin input reduction mux - tr_group[3].input[30] + TRIGGER_TR_GROUP3_INPUT31 = 239, //!< HSIOM Pin input reduction mux - tr_group[3].input[31] + TRIGGER_TR_GROUP3_INPUT32 = 240, //!< HSIOM Pin input reduction mux - tr_group[3].input[32] + TRIGGER_TR_GROUP3_INPUT33 = 241, //!< DMA request reduction mux - tr_group[3].input[33] + TRIGGER_TR_GROUP3_INPUT34 = 242, //!< DMA request reduction mux - tr_group[3].input[34] + TRIGGER_TR_GROUP3_INPUT35 = 243, //!< Trigger input reduction mux - tr_group[3].input[35] + TRIGGER_TR_GROUP3_INPUT36 = 244, //!< Trigger input reduction mux - tr_group[3].input[36] + TRIGGER_TR_GROUP3_INPUT37 = 245, //!< Trigger input reduction mux - tr_group[3].input[37] + TRIGGER_TR_GROUP3_INPUT38 = 246, //!< Trigger input reduction mux - tr_group[3].input[38] + TRIGGER_TR_GROUP3_INPUT39 = 247, //!< Trigger input reduction mux - tr_group[3].input[39] + TRIGGER_TR_GROUP3_INPUT40 = 248, //!< Trigger input reduction mux - tr_group[3].input[40] + TRIGGER_TR_GROUP3_INPUT41 = 249, //!< Trigger input reduction mux - tr_group[3].input[41] + TRIGGER_TR_GROUP3_INPUT42 = 250, //!< Trigger input reduction mux - tr_group[3].input[42] + TRIGGER_TR_GROUP4_INPUT1 = 251, //!< Datawire output trigger reduction mux - tr_group[4].input[1] + TRIGGER_TR_GROUP4_INPUT2 = 252, //!< Datawire output trigger reduction mux - tr_group[4].input[2] + TRIGGER_TR_GROUP4_INPUT3 = 253, //!< Datawire output trigger reduction mux - tr_group[4].input[3] + TRIGGER_TR_GROUP4_INPUT4 = 254, //!< Datawire output trigger reduction mux - tr_group[4].input[4] + TRIGGER_TR_GROUP4_INPUT5 = 255, //!< Datawire output trigger reduction mux - tr_group[4].input[5] + TRIGGER_TR_GROUP4_INPUT6 = 256, //!< Datawire output trigger reduction mux - tr_group[4].input[6] + TRIGGER_TR_GROUP4_INPUT7 = 257, //!< Datawire output trigger reduction mux - tr_group[4].input[7] + TRIGGER_TR_GROUP4_INPUT8 = 258, //!< Datawire output trigger reduction mux - tr_group[4].input[8] + TRIGGER_TR_GROUP4_INPUT9 = 259, //!< TCPWM trigger output reduction mux - tr_group[4].input[9] + TRIGGER_TR_GROUP4_INPUT10 = 260, //!< TCPWM trigger output reduction mux - tr_group[4].input[10] + TRIGGER_TR_GROUP4_INPUT11 = 261, //!< TCPWM trigger output reduction mux - tr_group[4].input[11] + TRIGGER_TR_GROUP4_INPUT12 = 262, //!< TCPWM trigger output reduction mux - tr_group[4].input[12] + TRIGGER_TR_GROUP4_INPUT13 = 263, //!< TCPWM trigger output reduction mux - tr_group[4].input[13] + TRIGGER_TR_GROUP4_INPUT14 = 264, //!< TCPWM trigger output reduction mux - tr_group[4].input[14] + TRIGGER_TR_GROUP4_INPUT15 = 265, //!< TCPWM trigger output reduction mux - tr_group[4].input[15] + TRIGGER_TR_GROUP4_INPUT16 = 266, //!< TCPWM trigger output reduction mux - tr_group[4].input[16] + TRIGGER_TR_GROUP4_INPUT17 = 267, //!< TCPWM trigger output reduction mux - tr_group[4].input[17] + TRIGGER_TR_GROUP4_INPUT18 = 268, //!< TCPWM trigger output reduction mux - tr_group[4].input[18] + TRIGGER_TR_GROUP4_INPUT19 = 269, //!< TCPWM trigger output reduction mux - tr_group[4].input[19] + TRIGGER_TR_GROUP4_INPUT20 = 270, //!< TCPWM trigger output reduction mux - tr_group[4].input[20] + TRIGGER_TR_GROUP4_INPUT21 = 271, //!< TCPWM trigger output reduction mux - tr_group[4].input[21] + TRIGGER_TR_GROUP4_INPUT22 = 272, //!< TCPWM trigger output reduction mux - tr_group[4].input[22] + TRIGGER_TR_GROUP4_INPUT23 = 273, //!< TCPWM trigger output reduction mux - tr_group[4].input[23] + TRIGGER_TR_GROUP4_INPUT24 = 274, //!< TCPWM trigger output reduction mux - tr_group[4].input[24] + TRIGGER_TR_GROUP4_INPUT25 = 275, //!< HSIOM Pin input reduction mux - tr_group[4].input[25] + TRIGGER_TR_GROUP4_INPUT26 = 276, //!< HSIOM Pin input reduction mux - tr_group[4].input[26] + TRIGGER_TR_GROUP4_INPUT27 = 277, //!< HSIOM Pin input reduction mux - tr_group[4].input[27] + TRIGGER_TR_GROUP4_INPUT28 = 278, //!< HSIOM Pin input reduction mux - tr_group[4].input[28] + TRIGGER_TR_GROUP4_INPUT29 = 279, //!< HSIOM Pin input reduction mux - tr_group[4].input[29] + TRIGGER_TR_GROUP4_INPUT30 = 280, //!< HSIOM Pin input reduction mux - tr_group[4].input[30] + TRIGGER_TR_GROUP4_INPUT31 = 281, //!< HSIOM Pin input reduction mux - tr_group[4].input[31] + TRIGGER_TR_GROUP4_INPUT32 = 282, //!< HSIOM Pin input reduction mux - tr_group[4].input[32] + TRIGGER_TR_GROUP4_INPUT33 = 283, //!< DMA request reduction mux - tr_group[4].input[33] + TRIGGER_TR_GROUP4_INPUT34 = 284, //!< DMA request reduction mux - tr_group[4].input[34] + TRIGGER_TR_GROUP4_INPUT35 = 285, //!< Trigger input reduction mux - tr_group[4].input[35] + TRIGGER_TR_GROUP4_INPUT36 = 286, //!< Trigger input reduction mux - tr_group[4].input[36] + TRIGGER_TR_GROUP4_INPUT37 = 287, //!< Trigger input reduction mux - tr_group[4].input[37] + TRIGGER_TR_GROUP4_INPUT38 = 288, //!< Trigger input reduction mux - tr_group[4].input[38] + TRIGGER_TR_GROUP4_INPUT39 = 289, //!< Trigger input reduction mux - tr_group[4].input[39] + TRIGGER_TR_GROUP4_INPUT40 = 290, //!< Trigger input reduction mux - tr_group[4].input[40] + TRIGGER_TR_GROUP4_INPUT41 = 291, //!< Trigger input reduction mux - tr_group[4].input[41] + TRIGGER_TR_GROUP4_INPUT42 = 292, //!< Trigger input reduction mux - tr_group[4].input[42] + TRIGGER_TR_GROUP5_INPUT1 = 293, //!< Datawire output trigger reduction mux - tr_group[5].input[1] + TRIGGER_TR_GROUP5_INPUT2 = 294, //!< Datawire output trigger reduction mux - tr_group[5].input[2] + TRIGGER_TR_GROUP5_INPUT3 = 295, //!< Datawire output trigger reduction mux - tr_group[5].input[3] + TRIGGER_TR_GROUP5_INPUT4 = 296, //!< Datawire output trigger reduction mux - tr_group[5].input[4] + TRIGGER_TR_GROUP5_INPUT5 = 297, //!< Datawire output trigger reduction mux - tr_group[5].input[5] + TRIGGER_TR_GROUP5_INPUT6 = 298, //!< Datawire output trigger reduction mux - tr_group[5].input[6] + TRIGGER_TR_GROUP5_INPUT7 = 299, //!< Datawire output trigger reduction mux - tr_group[5].input[7] + TRIGGER_TR_GROUP5_INPUT8 = 300, //!< Datawire output trigger reduction mux - tr_group[5].input[8] + TRIGGER_TR_GROUP5_INPUT9 = 301, //!< TCPWM trigger output reduction mux - tr_group[5].input[9] + TRIGGER_TR_GROUP5_INPUT10 = 302, //!< TCPWM trigger output reduction mux - tr_group[5].input[10] + TRIGGER_TR_GROUP5_INPUT11 = 303, //!< TCPWM trigger output reduction mux - tr_group[5].input[11] + TRIGGER_TR_GROUP5_INPUT12 = 304, //!< TCPWM trigger output reduction mux - tr_group[5].input[12] + TRIGGER_TR_GROUP5_INPUT13 = 305, //!< TCPWM trigger output reduction mux - tr_group[5].input[13] + TRIGGER_TR_GROUP5_INPUT14 = 306, //!< TCPWM trigger output reduction mux - tr_group[5].input[14] + TRIGGER_TR_GROUP5_INPUT15 = 307, //!< TCPWM trigger output reduction mux - tr_group[5].input[15] + TRIGGER_TR_GROUP5_INPUT16 = 308, //!< TCPWM trigger output reduction mux - tr_group[5].input[16] + TRIGGER_TR_GROUP5_INPUT17 = 309, //!< TCPWM trigger output reduction mux - tr_group[5].input[17] + TRIGGER_TR_GROUP5_INPUT18 = 310, //!< TCPWM trigger output reduction mux - tr_group[5].input[18] + TRIGGER_TR_GROUP5_INPUT19 = 311, //!< TCPWM trigger output reduction mux - tr_group[5].input[19] + TRIGGER_TR_GROUP5_INPUT20 = 312, //!< TCPWM trigger output reduction mux - tr_group[5].input[20] + TRIGGER_TR_GROUP5_INPUT21 = 313, //!< TCPWM trigger output reduction mux - tr_group[5].input[21] + TRIGGER_TR_GROUP5_INPUT22 = 314, //!< TCPWM trigger output reduction mux - tr_group[5].input[22] + TRIGGER_TR_GROUP5_INPUT23 = 315, //!< TCPWM trigger output reduction mux - tr_group[5].input[23] + TRIGGER_TR_GROUP5_INPUT24 = 316, //!< TCPWM trigger output reduction mux - tr_group[5].input[24] + TRIGGER_TR_GROUP5_INPUT25 = 317, //!< HSIOM Pin input reduction mux - tr_group[5].input[25] + TRIGGER_TR_GROUP5_INPUT26 = 318, //!< HSIOM Pin input reduction mux - tr_group[5].input[26] + TRIGGER_TR_GROUP5_INPUT27 = 319, //!< HSIOM Pin input reduction mux - tr_group[5].input[27] + TRIGGER_TR_GROUP5_INPUT28 = 320, //!< HSIOM Pin input reduction mux - tr_group[5].input[28] + TRIGGER_TR_GROUP5_INPUT29 = 321, //!< HSIOM Pin input reduction mux - tr_group[5].input[29] + TRIGGER_TR_GROUP5_INPUT30 = 322, //!< HSIOM Pin input reduction mux - tr_group[5].input[30] + TRIGGER_TR_GROUP5_INPUT31 = 323, //!< HSIOM Pin input reduction mux - tr_group[5].input[31] + TRIGGER_TR_GROUP5_INPUT32 = 324, //!< HSIOM Pin input reduction mux - tr_group[5].input[32] + TRIGGER_TR_GROUP5_INPUT33 = 325, //!< DMA request reduction mux - tr_group[5].input[33] + TRIGGER_TR_GROUP5_INPUT34 = 326, //!< DMA request reduction mux - tr_group[5].input[34] + TRIGGER_TR_GROUP5_INPUT35 = 327, //!< Trigger input reduction mux - tr_group[5].input[35] + TRIGGER_TR_GROUP5_INPUT36 = 328, //!< Trigger input reduction mux - tr_group[5].input[36] + TRIGGER_TR_GROUP5_INPUT37 = 329, //!< Trigger input reduction mux - tr_group[5].input[37] + TRIGGER_TR_GROUP5_INPUT38 = 330, //!< Trigger input reduction mux - tr_group[5].input[38] + TRIGGER_TR_GROUP5_INPUT39 = 331, //!< Trigger input reduction mux - tr_group[5].input[39] + TRIGGER_TR_GROUP5_INPUT40 = 332, //!< Trigger input reduction mux - tr_group[5].input[40] + TRIGGER_TR_GROUP5_INPUT41 = 333, //!< Trigger input reduction mux - tr_group[5].input[41] + TRIGGER_TR_GROUP5_INPUT42 = 334, //!< Trigger input reduction mux - tr_group[5].input[42] + TRIGGER_TR_GROUP6_INPUT1 = 335, //!< Datawire output trigger reduction mux - tr_group[6].input[1] + TRIGGER_TR_GROUP6_INPUT2 = 336, //!< Datawire output trigger reduction mux - tr_group[6].input[2] + TRIGGER_TR_GROUP6_INPUT3 = 337, //!< Datawire output trigger reduction mux - tr_group[6].input[3] + TRIGGER_TR_GROUP6_INPUT4 = 338, //!< Datawire output trigger reduction mux - tr_group[6].input[4] + TRIGGER_TR_GROUP6_INPUT5 = 339, //!< Datawire output trigger reduction mux - tr_group[6].input[5] + TRIGGER_TR_GROUP6_INPUT6 = 340, //!< Datawire output trigger reduction mux - tr_group[6].input[6] + TRIGGER_TR_GROUP6_INPUT7 = 341, //!< Datawire output trigger reduction mux - tr_group[6].input[7] + TRIGGER_TR_GROUP6_INPUT8 = 342, //!< Datawire output trigger reduction mux - tr_group[6].input[8] + TRIGGER_TR_GROUP6_INPUT9 = 343, //!< TCPWM trigger output reduction mux - tr_group[6].input[9] + TRIGGER_TR_GROUP6_INPUT10 = 344, //!< TCPWM trigger output reduction mux - tr_group[6].input[10] + TRIGGER_TR_GROUP6_INPUT11 = 345, //!< TCPWM trigger output reduction mux - tr_group[6].input[11] + TRIGGER_TR_GROUP6_INPUT12 = 346, //!< TCPWM trigger output reduction mux - tr_group[6].input[12] + TRIGGER_TR_GROUP6_INPUT13 = 347, //!< TCPWM trigger output reduction mux - tr_group[6].input[13] + TRIGGER_TR_GROUP6_INPUT14 = 348, //!< TCPWM trigger output reduction mux - tr_group[6].input[14] + TRIGGER_TR_GROUP6_INPUT15 = 349, //!< TCPWM trigger output reduction mux - tr_group[6].input[15] + TRIGGER_TR_GROUP6_INPUT16 = 350, //!< TCPWM trigger output reduction mux - tr_group[6].input[16] + TRIGGER_TR_GROUP6_INPUT17 = 351, //!< TCPWM trigger output reduction mux - tr_group[6].input[17] + TRIGGER_TR_GROUP6_INPUT18 = 352, //!< TCPWM trigger output reduction mux - tr_group[6].input[18] + TRIGGER_TR_GROUP6_INPUT19 = 353, //!< TCPWM trigger output reduction mux - tr_group[6].input[19] + TRIGGER_TR_GROUP6_INPUT20 = 354, //!< TCPWM trigger output reduction mux - tr_group[6].input[20] + TRIGGER_TR_GROUP6_INPUT21 = 355, //!< TCPWM trigger output reduction mux - tr_group[6].input[21] + TRIGGER_TR_GROUP6_INPUT22 = 356, //!< TCPWM trigger output reduction mux - tr_group[6].input[22] + TRIGGER_TR_GROUP6_INPUT23 = 357, //!< TCPWM trigger output reduction mux - tr_group[6].input[23] + TRIGGER_TR_GROUP6_INPUT24 = 358, //!< TCPWM trigger output reduction mux - tr_group[6].input[24] + TRIGGER_TR_GROUP6_INPUT25 = 359, //!< HSIOM Pin input reduction mux - tr_group[6].input[25] + TRIGGER_TR_GROUP6_INPUT26 = 360, //!< HSIOM Pin input reduction mux - tr_group[6].input[26] + TRIGGER_TR_GROUP6_INPUT27 = 361, //!< HSIOM Pin input reduction mux - tr_group[6].input[27] + TRIGGER_TR_GROUP6_INPUT28 = 362, //!< HSIOM Pin input reduction mux - tr_group[6].input[28] + TRIGGER_TR_GROUP6_INPUT29 = 363, //!< HSIOM Pin input reduction mux - tr_group[6].input[29] + TRIGGER_TR_GROUP6_INPUT30 = 364, //!< HSIOM Pin input reduction mux - tr_group[6].input[30] + TRIGGER_TR_GROUP6_INPUT31 = 365, //!< HSIOM Pin input reduction mux - tr_group[6].input[31] + TRIGGER_TR_GROUP6_INPUT32 = 366, //!< HSIOM Pin input reduction mux - tr_group[6].input[32] + TRIGGER_TR_GROUP6_INPUT33 = 367, //!< DMA request reduction mux - tr_group[6].input[33] + TRIGGER_TR_GROUP6_INPUT34 = 368, //!< DMA request reduction mux - tr_group[6].input[34] + TRIGGER_TR_GROUP6_INPUT35 = 369, //!< Trigger input reduction mux - tr_group[6].input[35] + TRIGGER_TR_GROUP6_INPUT36 = 370, //!< Trigger input reduction mux - tr_group[6].input[36] + TRIGGER_TR_GROUP6_INPUT37 = 371, //!< Trigger input reduction mux - tr_group[6].input[37] + TRIGGER_TR_GROUP6_INPUT38 = 372, //!< Trigger input reduction mux - tr_group[6].input[38] + TRIGGER_TR_GROUP6_INPUT39 = 373, //!< Trigger input reduction mux - tr_group[6].input[39] + TRIGGER_TR_GROUP6_INPUT40 = 374, //!< Trigger input reduction mux - tr_group[6].input[40] + TRIGGER_TR_GROUP6_INPUT41 = 375, //!< Trigger input reduction mux - tr_group[6].input[41] + TRIGGER_TR_GROUP6_INPUT42 = 376, //!< Trigger input reduction mux - tr_group[6].input[42] + TRIGGER_TR_GROUP7_INPUT1 = 377, //!< Datawire output trigger reduction mux - tr_group[7].input[1] + TRIGGER_TR_GROUP7_INPUT2 = 378, //!< Datawire output trigger reduction mux - tr_group[7].input[2] + TRIGGER_TR_GROUP7_INPUT3 = 379, //!< Datawire output trigger reduction mux - tr_group[7].input[3] + TRIGGER_TR_GROUP7_INPUT4 = 380, //!< Datawire output trigger reduction mux - tr_group[7].input[4] + TRIGGER_TR_GROUP7_INPUT5 = 381, //!< Datawire output trigger reduction mux - tr_group[7].input[5] + TRIGGER_TR_GROUP7_INPUT6 = 382, //!< Datawire output trigger reduction mux - tr_group[7].input[6] + TRIGGER_TR_GROUP7_INPUT7 = 383, //!< Datawire output trigger reduction mux - tr_group[7].input[7] + TRIGGER_TR_GROUP7_INPUT8 = 384, //!< Datawire output trigger reduction mux - tr_group[7].input[8] + TRIGGER_TR_GROUP7_INPUT9 = 385, //!< TCPWM trigger output reduction mux - tr_group[7].input[9] + TRIGGER_TR_GROUP7_INPUT10 = 386, //!< TCPWM trigger output reduction mux - tr_group[7].input[10] + TRIGGER_TR_GROUP7_INPUT11 = 387, //!< TCPWM trigger output reduction mux - tr_group[7].input[11] + TRIGGER_TR_GROUP7_INPUT12 = 388, //!< TCPWM trigger output reduction mux - tr_group[7].input[12] + TRIGGER_TR_GROUP7_INPUT13 = 389, //!< TCPWM trigger output reduction mux - tr_group[7].input[13] + TRIGGER_TR_GROUP7_INPUT14 = 390, //!< TCPWM trigger output reduction mux - tr_group[7].input[14] + TRIGGER_TR_GROUP7_INPUT15 = 391, //!< TCPWM trigger output reduction mux - tr_group[7].input[15] + TRIGGER_TR_GROUP7_INPUT16 = 392, //!< TCPWM trigger output reduction mux - tr_group[7].input[16] + TRIGGER_TR_GROUP7_INPUT17 = 393, //!< TCPWM trigger output reduction mux - tr_group[7].input[17] + TRIGGER_TR_GROUP7_INPUT18 = 394, //!< TCPWM trigger output reduction mux - tr_group[7].input[18] + TRIGGER_TR_GROUP7_INPUT19 = 395, //!< TCPWM trigger output reduction mux - tr_group[7].input[19] + TRIGGER_TR_GROUP7_INPUT20 = 396, //!< TCPWM trigger output reduction mux - tr_group[7].input[20] + TRIGGER_TR_GROUP7_INPUT21 = 397, //!< TCPWM trigger output reduction mux - tr_group[7].input[21] + TRIGGER_TR_GROUP7_INPUT22 = 398, //!< TCPWM trigger output reduction mux - tr_group[7].input[22] + TRIGGER_TR_GROUP7_INPUT23 = 399, //!< TCPWM trigger output reduction mux - tr_group[7].input[23] + TRIGGER_TR_GROUP7_INPUT24 = 400, //!< TCPWM trigger output reduction mux - tr_group[7].input[24] + TRIGGER_TR_GROUP7_INPUT25 = 401, //!< HSIOM Pin input reduction mux - tr_group[7].input[25] + TRIGGER_TR_GROUP7_INPUT26 = 402, //!< HSIOM Pin input reduction mux - tr_group[7].input[26] + TRIGGER_TR_GROUP7_INPUT27 = 403, //!< HSIOM Pin input reduction mux - tr_group[7].input[27] + TRIGGER_TR_GROUP7_INPUT28 = 404, //!< HSIOM Pin input reduction mux - tr_group[7].input[28] + TRIGGER_TR_GROUP7_INPUT29 = 405, //!< HSIOM Pin input reduction mux - tr_group[7].input[29] + TRIGGER_TR_GROUP7_INPUT30 = 406, //!< HSIOM Pin input reduction mux - tr_group[7].input[30] + TRIGGER_TR_GROUP7_INPUT31 = 407, //!< HSIOM Pin input reduction mux - tr_group[7].input[31] + TRIGGER_TR_GROUP7_INPUT32 = 408, //!< HSIOM Pin input reduction mux - tr_group[7].input[32] + TRIGGER_TR_GROUP7_INPUT33 = 409, //!< DMA request reduction mux - tr_group[7].input[33] + TRIGGER_TR_GROUP7_INPUT34 = 410, //!< DMA request reduction mux - tr_group[7].input[34] + TRIGGER_TR_GROUP7_INPUT35 = 411, //!< Trigger input reduction mux - tr_group[7].input[35] + TRIGGER_TR_GROUP7_INPUT36 = 412, //!< Trigger input reduction mux - tr_group[7].input[36] + TRIGGER_TR_GROUP7_INPUT37 = 413, //!< Trigger input reduction mux - tr_group[7].input[37] + TRIGGER_TR_GROUP7_INPUT38 = 414, //!< Trigger input reduction mux - tr_group[7].input[38] + TRIGGER_TR_GROUP7_INPUT39 = 415, //!< Trigger input reduction mux - tr_group[7].input[39] + TRIGGER_TR_GROUP7_INPUT40 = 416, //!< Trigger input reduction mux - tr_group[7].input[40] + TRIGGER_TR_GROUP7_INPUT41 = 417, //!< Trigger input reduction mux - tr_group[7].input[41] + TRIGGER_TR_GROUP7_INPUT42 = 418, //!< Trigger input reduction mux - tr_group[7].input[42] + TRIGGER_TR_GROUP8_INPUT1 = 419, //!< Datawire output trigger reduction mux - tr_group[8].input[1] + TRIGGER_TR_GROUP8_INPUT2 = 420, //!< Datawire output trigger reduction mux - tr_group[8].input[2] + TRIGGER_TR_GROUP8_INPUT3 = 421, //!< Datawire output trigger reduction mux - tr_group[8].input[3] + TRIGGER_TR_GROUP8_INPUT4 = 422, //!< Datawire output trigger reduction mux - tr_group[8].input[4] + TRIGGER_TR_GROUP8_INPUT5 = 423, //!< Datawire output trigger reduction mux - tr_group[8].input[5] + TRIGGER_TR_GROUP8_INPUT6 = 424, //!< Datawire output trigger reduction mux - tr_group[8].input[6] + TRIGGER_TR_GROUP8_INPUT7 = 425, //!< Datawire output trigger reduction mux - tr_group[8].input[7] + TRIGGER_TR_GROUP8_INPUT8 = 426, //!< Datawire output trigger reduction mux - tr_group[8].input[8] + TRIGGER_TR_GROUP8_INPUT9 = 427, //!< TCPWM trigger output reduction mux - tr_group[8].input[9] + TRIGGER_TR_GROUP8_INPUT10 = 428, //!< TCPWM trigger output reduction mux - tr_group[8].input[10] + TRIGGER_TR_GROUP8_INPUT11 = 429, //!< TCPWM trigger output reduction mux - tr_group[8].input[11] + TRIGGER_TR_GROUP8_INPUT12 = 430, //!< TCPWM trigger output reduction mux - tr_group[8].input[12] + TRIGGER_TR_GROUP8_INPUT13 = 431, //!< TCPWM trigger output reduction mux - tr_group[8].input[13] + TRIGGER_TR_GROUP8_INPUT14 = 432, //!< TCPWM trigger output reduction mux - tr_group[8].input[14] + TRIGGER_TR_GROUP8_INPUT15 = 433, //!< TCPWM trigger output reduction mux - tr_group[8].input[15] + TRIGGER_TR_GROUP8_INPUT16 = 434, //!< TCPWM trigger output reduction mux - tr_group[8].input[16] + TRIGGER_TR_GROUP8_INPUT17 = 435, //!< TCPWM trigger output reduction mux - tr_group[8].input[17] + TRIGGER_TR_GROUP8_INPUT18 = 436, //!< TCPWM trigger output reduction mux - tr_group[8].input[18] + TRIGGER_TR_GROUP8_INPUT19 = 437, //!< TCPWM trigger output reduction mux - tr_group[8].input[19] + TRIGGER_TR_GROUP8_INPUT20 = 438, //!< TCPWM trigger output reduction mux - tr_group[8].input[20] + TRIGGER_TR_GROUP8_INPUT21 = 439, //!< TCPWM trigger output reduction mux - tr_group[8].input[21] + TRIGGER_TR_GROUP8_INPUT22 = 440, //!< TCPWM trigger output reduction mux - tr_group[8].input[22] + TRIGGER_TR_GROUP8_INPUT23 = 441, //!< TCPWM trigger output reduction mux - tr_group[8].input[23] + TRIGGER_TR_GROUP8_INPUT24 = 442, //!< TCPWM trigger output reduction mux - tr_group[8].input[24] + TRIGGER_TR_GROUP8_INPUT25 = 443, //!< HSIOM Pin input reduction mux - tr_group[8].input[25] + TRIGGER_TR_GROUP8_INPUT26 = 444, //!< HSIOM Pin input reduction mux - tr_group[8].input[26] + TRIGGER_TR_GROUP8_INPUT27 = 445, //!< HSIOM Pin input reduction mux - tr_group[8].input[27] + TRIGGER_TR_GROUP8_INPUT28 = 446, //!< HSIOM Pin input reduction mux - tr_group[8].input[28] + TRIGGER_TR_GROUP8_INPUT29 = 447, //!< HSIOM Pin input reduction mux - tr_group[8].input[29] + TRIGGER_TR_GROUP8_INPUT30 = 448, //!< HSIOM Pin input reduction mux - tr_group[8].input[30] + TRIGGER_TR_GROUP8_INPUT31 = 449, //!< HSIOM Pin input reduction mux - tr_group[8].input[31] + TRIGGER_TR_GROUP8_INPUT32 = 450, //!< HSIOM Pin input reduction mux - tr_group[8].input[32] + TRIGGER_TR_GROUP8_INPUT33 = 451, //!< DMA request reduction mux - tr_group[8].input[33] + TRIGGER_TR_GROUP8_INPUT34 = 452, //!< DMA request reduction mux - tr_group[8].input[34] + TRIGGER_TR_GROUP8_INPUT35 = 453, //!< Trigger input reduction mux - tr_group[8].input[35] + TRIGGER_TR_GROUP8_INPUT36 = 454, //!< Trigger input reduction mux - tr_group[8].input[36] + TRIGGER_TR_GROUP8_INPUT37 = 455, //!< Trigger input reduction mux - tr_group[8].input[37] + TRIGGER_TR_GROUP8_INPUT38 = 456, //!< Trigger input reduction mux - tr_group[8].input[38] + TRIGGER_TR_GROUP8_INPUT39 = 457, //!< Trigger input reduction mux - tr_group[8].input[39] + TRIGGER_TR_GROUP8_INPUT40 = 458, //!< Trigger input reduction mux - tr_group[8].input[40] + TRIGGER_TR_GROUP8_INPUT41 = 459, //!< Trigger input reduction mux - tr_group[8].input[41] + TRIGGER_TR_GROUP8_INPUT42 = 460, //!< Trigger input reduction mux - tr_group[8].input[42] + TRIGGER_UDB_TR_DW_ACK0 = 461, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[0] + TRIGGER_UDB_TR_DW_ACK1 = 462, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[1] + TRIGGER_UDB_TR_DW_ACK2 = 463, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[2] + TRIGGER_UDB_TR_DW_ACK3 = 464, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[3] + TRIGGER_UDB_TR_DW_ACK4 = 465, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[4] + TRIGGER_UDB_TR_DW_ACK5 = 466, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[5] + TRIGGER_UDB_TR_DW_ACK6 = 467, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[6] + TRIGGER_UDB_TR_DW_ACK7 = 468, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[7] + TRIGGER_UDB_TR_IN0 = 469, //!< UDB trigger multiplexer - udb.tr_in[0] + TRIGGER_UDB_TR_IN1 = 470, //!< UDB trigger multiplexer - udb.tr_in[1] + TRIGGER_USB_DMA_BURSTEND0 = 471, //!< USB DMA burstend multiplexer - usb.dma_burstend[0] + TRIGGER_USB_DMA_BURSTEND1 = 472, //!< USB DMA burstend multiplexer - usb.dma_burstend[1] + TRIGGER_USB_DMA_BURSTEND2 = 473, //!< USB DMA burstend multiplexer - usb.dma_burstend[2] + TRIGGER_USB_DMA_BURSTEND3 = 474, //!< USB DMA burstend multiplexer - usb.dma_burstend[3] + TRIGGER_USB_DMA_BURSTEND4 = 475, //!< USB DMA burstend multiplexer - usb.dma_burstend[4] + TRIGGER_USB_DMA_BURSTEND5 = 476, //!< USB DMA burstend multiplexer - usb.dma_burstend[5] + TRIGGER_USB_DMA_BURSTEND6 = 477, //!< USB DMA burstend multiplexer - usb.dma_burstend[6] + TRIGGER_USB_DMA_BURSTEND7 = 478, //!< USB DMA burstend multiplexer - usb.dma_burstend[7] +} cyhal_trigger_dest_psoc6_01_t; + +/** Typedef from device family specific trigger dest to generic trigger dest */ +typedef cyhal_trigger_dest_psoc6_01_t cyhal_dest_t; + +/** \cond INTERNAL */ +/** Maps each cyhal_destination_t to a mux index. + * If bit 8 of the mux index is set, this denotes that the trigger is a + * one to one trigger. + */ +extern const uint8_t cyhal_dest_to_mux[479]; + +/* Maps each cyhal_destination_t to a specific output in its mux */ +extern const uint8_t cyhal_mux_dest_index[479]; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +/** \} group_hal_psoc6_triggers_psoc6_01 */ +#endif /* _CYHAL_TRIGGERS_PSOC6_01_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_02.h new file mode 100644 index 0000000000..258a8b261d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_02.h @@ -0,0 +1,175 @@ +/***************************************************************************//** +* \file cyhal_triggers_psoc6_02.h +* +* \brief +* PSoC6_02 family HAL triggers header +* +* \note +* Generator version: 1.5.7254.19579 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYHAL_TRIGGERS_PSOC6_02_H_ +#define _CYHAL_TRIGGERS_PSOC6_02_H_ + +/** + * \addtogroup group_hal_psoc6_triggers_psoc6_02 PSOC6_02 + * \ingroup group_hal_psoc6_triggers + * \{ + * Trigger connections for psoc6_02 + */ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** @brief Name of each output trigger. */ +typedef enum +{ + TRIGGER_CPUSS_CTI_TR_IN0 = 0, //!< CPUSS Debug and Profiler trigger multiplexer - cpuss.cti_tr_in[0] + TRIGGER_CPUSS_CTI_TR_IN1 = 1, //!< CPUSS Debug and Profiler trigger multiplexer - cpuss.cti_tr_in[1] + TRIGGER_CPUSS_DMAC_TR_IN0 = 2, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[0] + TRIGGER_CPUSS_DMAC_TR_IN1 = 3, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[1] + TRIGGER_CPUSS_DMAC_TR_IN2 = 4, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[2] + TRIGGER_CPUSS_DMAC_TR_IN3 = 5, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[3] + TRIGGER_CPUSS_DW0_TR_IN0 = 6, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[0] + TRIGGER_CPUSS_DW0_TR_IN1 = 7, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[1] + TRIGGER_CPUSS_DW0_TR_IN2 = 8, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[2] + TRIGGER_CPUSS_DW0_TR_IN3 = 9, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[3] + TRIGGER_CPUSS_DW0_TR_IN4 = 10, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[4] + TRIGGER_CPUSS_DW0_TR_IN5 = 11, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[5] + TRIGGER_CPUSS_DW0_TR_IN6 = 12, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[6] + TRIGGER_CPUSS_DW0_TR_IN7 = 13, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[7] + TRIGGER_CPUSS_DW0_TR_IN8 = 14, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[8] + TRIGGER_CPUSS_DW0_TR_IN9 = 15, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[9] + TRIGGER_CPUSS_DW0_TR_IN10 = 16, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[10] + TRIGGER_CPUSS_DW0_TR_IN11 = 17, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[11] + TRIGGER_CPUSS_DW0_TR_IN12 = 18, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[12] + TRIGGER_CPUSS_DW0_TR_IN13 = 19, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[13] + TRIGGER_CPUSS_DW0_TR_IN14 = 20, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[14] + TRIGGER_CPUSS_DW0_TR_IN15 = 21, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[15] + TRIGGER_CPUSS_DW0_TR_IN16 = 22, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[16] + TRIGGER_CPUSS_DW0_TR_IN17 = 23, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[17] + TRIGGER_CPUSS_DW0_TR_IN18 = 24, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[18] + TRIGGER_CPUSS_DW0_TR_IN19 = 25, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[19] + TRIGGER_CPUSS_DW0_TR_IN20 = 26, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[20] + TRIGGER_CPUSS_DW0_TR_IN21 = 27, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[21] + TRIGGER_CPUSS_DW0_TR_IN22 = 28, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[22] + TRIGGER_CPUSS_DW0_TR_IN23 = 29, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[23] + TRIGGER_CPUSS_DW0_TR_IN24 = 30, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[24] + TRIGGER_CPUSS_DW0_TR_IN25 = 31, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[25] + TRIGGER_CPUSS_DW0_TR_IN26 = 32, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[26] + TRIGGER_CPUSS_DW0_TR_IN27 = 33, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[27] + TRIGGER_CPUSS_DW0_TR_IN28 = 34, //!< SAR to PDMA0 direct connect - cpuss.dw0_tr_in[28] + TRIGGER_CPUSS_DW1_TR_IN0 = 35, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[0] + TRIGGER_CPUSS_DW1_TR_IN1 = 36, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[1] + TRIGGER_CPUSS_DW1_TR_IN2 = 37, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[2] + TRIGGER_CPUSS_DW1_TR_IN3 = 38, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[3] + TRIGGER_CPUSS_DW1_TR_IN4 = 39, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[4] + TRIGGER_CPUSS_DW1_TR_IN5 = 40, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[5] + TRIGGER_CPUSS_DW1_TR_IN6 = 41, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[6] + TRIGGER_CPUSS_DW1_TR_IN7 = 42, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[7] + TRIGGER_CPUSS_DW1_TR_IN8 = 43, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[8] + TRIGGER_CPUSS_DW1_TR_IN9 = 44, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[9] + TRIGGER_CPUSS_DW1_TR_IN10 = 45, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[10] + TRIGGER_CPUSS_DW1_TR_IN11 = 46, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[11] + TRIGGER_CPUSS_DW1_TR_IN12 = 47, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[12] + TRIGGER_CPUSS_DW1_TR_IN13 = 48, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[13] + TRIGGER_CPUSS_DW1_TR_IN14 = 49, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[14] + TRIGGER_CPUSS_DW1_TR_IN15 = 50, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[15] + TRIGGER_CPUSS_DW1_TR_IN16 = 51, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[16] + TRIGGER_CPUSS_DW1_TR_IN17 = 52, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[17] + TRIGGER_CPUSS_DW1_TR_IN18 = 53, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[18] + TRIGGER_CPUSS_DW1_TR_IN19 = 54, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[19] + TRIGGER_CPUSS_DW1_TR_IN20 = 55, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[20] + TRIGGER_CPUSS_DW1_TR_IN21 = 56, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[21] + TRIGGER_CPUSS_DW1_TR_IN22 = 57, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22] + TRIGGER_CPUSS_DW1_TR_IN23 = 58, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23] + TRIGGER_CPUSS_DW1_TR_IN24 = 59, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[24] + TRIGGER_CPUSS_DW1_TR_IN25 = 60, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[25] + TRIGGER_CPUSS_DW1_TR_IN26 = 61, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[26] + TRIGGER_CPUSS_DW1_TR_IN27 = 62, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[27] + TRIGGER_CPUSS_DW1_TR_IN28 = 63, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[28] + TRIGGER_CSD_DSI_START = 64, //!< Capsense trigger multiplexer - csd.dsi_start + TRIGGER_PASS_TR_SAR_IN = 65, //!< ADC trigger multiplexer - pass.tr_sar_in + TRIGGER_PERI_TR_DBG_FREEZE = 66, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze + TRIGGER_PERI_TR_IO_OUTPUT0 = 67, //!< HSIOM trigger multiplexer - peri.tr_io_output[0] + TRIGGER_PERI_TR_IO_OUTPUT1 = 68, //!< HSIOM trigger multiplexer - peri.tr_io_output[1] + TRIGGER_PROFILE_TR_START = 69, //!< CPUSS Debug and Profiler trigger multiplexer - profile.tr_start + TRIGGER_PROFILE_TR_STOP = 70, //!< CPUSS Debug and Profiler trigger multiplexer - profile.tr_stop + TRIGGER_TCPWM0_TR_IN0 = 71, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[0] + TRIGGER_TCPWM0_TR_IN1 = 72, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[1] + TRIGGER_TCPWM0_TR_IN2 = 73, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[2] + TRIGGER_TCPWM0_TR_IN3 = 74, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[3] + TRIGGER_TCPWM0_TR_IN4 = 75, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[4] + TRIGGER_TCPWM0_TR_IN5 = 76, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[5] + TRIGGER_TCPWM0_TR_IN6 = 77, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[6] + TRIGGER_TCPWM0_TR_IN7 = 78, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[7] + TRIGGER_TCPWM0_TR_IN8 = 79, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[8] + TRIGGER_TCPWM0_TR_IN9 = 80, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[9] + TRIGGER_TCPWM0_TR_IN10 = 81, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[10] + TRIGGER_TCPWM0_TR_IN11 = 82, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[11] + TRIGGER_TCPWM0_TR_IN12 = 83, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[12] + TRIGGER_TCPWM0_TR_IN13 = 84, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[13] + TRIGGER_TCPWM1_TR_IN0 = 85, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[0] + TRIGGER_TCPWM1_TR_IN1 = 86, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[1] + TRIGGER_TCPWM1_TR_IN2 = 87, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[2] + TRIGGER_TCPWM1_TR_IN3 = 88, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[3] + TRIGGER_TCPWM1_TR_IN4 = 89, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[4] + TRIGGER_TCPWM1_TR_IN5 = 90, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[5] + TRIGGER_TCPWM1_TR_IN6 = 91, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[6] + TRIGGER_TCPWM1_TR_IN7 = 92, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[7] + TRIGGER_TCPWM1_TR_IN8 = 93, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[8] + TRIGGER_TCPWM1_TR_IN9 = 94, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[9] + TRIGGER_TCPWM1_TR_IN10 = 95, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[10] + TRIGGER_TCPWM1_TR_IN11 = 96, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[11] + TRIGGER_TCPWM1_TR_IN12 = 97, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[12] + TRIGGER_TCPWM1_TR_IN13 = 98, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[13] + TRIGGER_USB_DMA_BURSTEND0 = 99, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0] + TRIGGER_USB_DMA_BURSTEND1 = 100, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1] + TRIGGER_USB_DMA_BURSTEND2 = 101, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2] + TRIGGER_USB_DMA_BURSTEND3 = 102, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3] + TRIGGER_USB_DMA_BURSTEND4 = 103, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4] + TRIGGER_USB_DMA_BURSTEND5 = 104, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5] + TRIGGER_USB_DMA_BURSTEND6 = 105, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6] + TRIGGER_USB_DMA_BURSTEND7 = 106, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7] +} cyhal_trigger_dest_psoc6_02_t; + +/** Typedef from device family specific trigger dest to generic trigger dest */ +typedef cyhal_trigger_dest_psoc6_02_t cyhal_dest_t; + +/** \cond INTERNAL */ +/** Maps each cyhal_destination_t to a mux index. + * If bit 8 of the mux index is set, this denotes that the trigger is a + * one to one trigger. + */ +extern const uint8_t cyhal_dest_to_mux[107]; + +/* Maps each cyhal_destination_t to a specific output in its mux */ +extern const uint8_t cyhal_mux_dest_index[107]; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +/** \} group_hal_psoc6_triggers_psoc6_02 */ +#endif /* _CYHAL_TRIGGERS_PSOC6_02_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_03.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_03.h new file mode 100644 index 0000000000..e9504eba62 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_03.h @@ -0,0 +1,176 @@ +/***************************************************************************//** +* \file cyhal_triggers_psoc6_03.h +* +* \brief +* PSoC6_03 family HAL triggers header +* +* \note +* Generator version: 1.5.7254.19579 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYHAL_TRIGGERS_PSOC6_03_H_ +#define _CYHAL_TRIGGERS_PSOC6_03_H_ + +/** + * \addtogroup group_hal_psoc6_triggers_psoc6_03 PSOC6_03 + * \ingroup group_hal_psoc6_triggers + * \{ + * Trigger connections for psoc6_03 + */ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** @brief Name of each output trigger. */ +typedef enum +{ + TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[0] + TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 1, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[0] + TRIGGER_CPUSS_CTI_TR_IN0 = 2, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[0] + TRIGGER_CPUSS_CTI_TR_IN1 = 3, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[1] + TRIGGER_CPUSS_DMAC_TR_IN0 = 4, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[0] + TRIGGER_CPUSS_DMAC_TR_IN1 = 5, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[1] + TRIGGER_CPUSS_DW0_TR_IN0 = 6, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[0] + TRIGGER_CPUSS_DW0_TR_IN1 = 7, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[1] + TRIGGER_CPUSS_DW0_TR_IN2 = 8, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[2] + TRIGGER_CPUSS_DW0_TR_IN3 = 9, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[3] + TRIGGER_CPUSS_DW0_TR_IN4 = 10, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[4] + TRIGGER_CPUSS_DW0_TR_IN5 = 11, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[5] + TRIGGER_CPUSS_DW0_TR_IN6 = 12, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[6] + TRIGGER_CPUSS_DW0_TR_IN7 = 13, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[7] + TRIGGER_CPUSS_DW0_TR_IN8 = 14, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[8] + TRIGGER_CPUSS_DW0_TR_IN9 = 15, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[9] + TRIGGER_CPUSS_DW0_TR_IN10 = 16, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[10] + TRIGGER_CPUSS_DW0_TR_IN11 = 17, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[11] + TRIGGER_CPUSS_DW0_TR_IN12 = 18, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[12] + TRIGGER_CPUSS_DW0_TR_IN13 = 19, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[13] + TRIGGER_CPUSS_DW0_TR_IN14 = 20, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[14] + TRIGGER_CPUSS_DW0_TR_IN15 = 21, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[15] + TRIGGER_CPUSS_DW0_TR_IN16 = 22, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[16] + TRIGGER_CPUSS_DW0_TR_IN17 = 23, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[17] + TRIGGER_CPUSS_DW0_TR_IN18 = 24, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[18] + TRIGGER_CPUSS_DW0_TR_IN19 = 25, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[19] + TRIGGER_CPUSS_DW0_TR_IN20 = 26, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[20] + TRIGGER_CPUSS_DW0_TR_IN21 = 27, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[21] + TRIGGER_CPUSS_DW0_TR_IN22 = 28, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[22] + TRIGGER_CPUSS_DW0_TR_IN23 = 29, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[23] + TRIGGER_CPUSS_DW0_TR_IN24 = 30, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[24] + TRIGGER_CPUSS_DW0_TR_IN25 = 31, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[25] + TRIGGER_CPUSS_DW0_TR_IN26 = 32, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[26] + TRIGGER_CPUSS_DW0_TR_IN27 = 33, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[27] + TRIGGER_CPUSS_DW0_TR_IN28 = 34, //!< SAR to PDMA1 direct connect - cpuss.dw0_tr_in[28] + TRIGGER_CPUSS_DW1_TR_IN0 = 35, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[0] + TRIGGER_CPUSS_DW1_TR_IN1 = 36, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[1] + TRIGGER_CPUSS_DW1_TR_IN2 = 37, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[2] + TRIGGER_CPUSS_DW1_TR_IN3 = 38, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[3] + TRIGGER_CPUSS_DW1_TR_IN4 = 39, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[4] + TRIGGER_CPUSS_DW1_TR_IN5 = 40, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[5] + TRIGGER_CPUSS_DW1_TR_IN6 = 41, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[6] + TRIGGER_CPUSS_DW1_TR_IN7 = 42, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[7] + TRIGGER_CPUSS_DW1_TR_IN8 = 43, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[8] + TRIGGER_CPUSS_DW1_TR_IN9 = 44, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[9] + TRIGGER_CPUSS_DW1_TR_IN10 = 45, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[10] + TRIGGER_CPUSS_DW1_TR_IN11 = 46, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[11] + TRIGGER_CPUSS_DW1_TR_IN12 = 47, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[12] + TRIGGER_CPUSS_DW1_TR_IN13 = 48, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[13] + TRIGGER_CPUSS_DW1_TR_IN14 = 49, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[14] + TRIGGER_CPUSS_DW1_TR_IN15 = 50, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[15] + TRIGGER_CPUSS_DW1_TR_IN16 = 51, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[16] + TRIGGER_CPUSS_DW1_TR_IN17 = 52, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[17] + TRIGGER_CPUSS_DW1_TR_IN18 = 53, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[18] + TRIGGER_CPUSS_DW1_TR_IN19 = 54, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[19] + TRIGGER_CPUSS_DW1_TR_IN20 = 55, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[20] + TRIGGER_CPUSS_DW1_TR_IN21 = 56, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[21] + TRIGGER_CPUSS_DW1_TR_IN22 = 57, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22] + TRIGGER_CPUSS_DW1_TR_IN23 = 58, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23] + TRIGGER_CPUSS_DW1_TR_IN24 = 59, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[24] + TRIGGER_CPUSS_DW1_TR_IN25 = 60, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[25] + TRIGGER_CPUSS_DW1_TR_IN26 = 61, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[26] + TRIGGER_CPUSS_DW1_TR_IN27 = 62, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[27] + TRIGGER_CPUSS_DW1_TR_IN28 = 63, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[28] + TRIGGER_CPUSS_DW1_TR_IN29 = 64, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[29] + TRIGGER_CPUSS_DW1_TR_IN30 = 65, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[30] + TRIGGER_CPUSS_DW1_TR_IN31 = 66, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[31] + TRIGGER_CSD_DSI_START = 67, //!< Capsense trigger multiplexer - csd.dsi_start + TRIGGER_PASS_TR_SAR_IN = 68, //!< ADC trigger multiplexer - pass.tr_sar_in + TRIGGER_PERI_TR_DBG_FREEZE = 69, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze + TRIGGER_PERI_TR_IO_OUTPUT0 = 70, //!< HSIOM trigger multiplexer - peri.tr_io_output[0] + TRIGGER_PERI_TR_IO_OUTPUT1 = 71, //!< HSIOM trigger multiplexer - peri.tr_io_output[1] + TRIGGER_TCPWM0_TR_IN0 = 72, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[0] + TRIGGER_TCPWM0_TR_IN1 = 73, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[1] + TRIGGER_TCPWM0_TR_IN2 = 74, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[2] + TRIGGER_TCPWM0_TR_IN3 = 75, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[3] + TRIGGER_TCPWM0_TR_IN4 = 76, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[4] + TRIGGER_TCPWM0_TR_IN5 = 77, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[5] + TRIGGER_TCPWM0_TR_IN6 = 78, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[6] + TRIGGER_TCPWM0_TR_IN7 = 79, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[7] + TRIGGER_TCPWM0_TR_IN8 = 80, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[8] + TRIGGER_TCPWM0_TR_IN9 = 81, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[9] + TRIGGER_TCPWM0_TR_IN10 = 82, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[10] + TRIGGER_TCPWM0_TR_IN11 = 83, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[11] + TRIGGER_TCPWM0_TR_IN12 = 84, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[12] + TRIGGER_TCPWM0_TR_IN13 = 85, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[13] + TRIGGER_TCPWM1_TR_IN0 = 86, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[0] + TRIGGER_TCPWM1_TR_IN1 = 87, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[1] + TRIGGER_TCPWM1_TR_IN2 = 88, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[2] + TRIGGER_TCPWM1_TR_IN3 = 89, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[3] + TRIGGER_TCPWM1_TR_IN4 = 90, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[4] + TRIGGER_TCPWM1_TR_IN5 = 91, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[5] + TRIGGER_TCPWM1_TR_IN6 = 92, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[6] + TRIGGER_TCPWM1_TR_IN7 = 93, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[7] + TRIGGER_TCPWM1_TR_IN8 = 94, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[8] + TRIGGER_TCPWM1_TR_IN9 = 95, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[9] + TRIGGER_TCPWM1_TR_IN10 = 96, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[10] + TRIGGER_TCPWM1_TR_IN11 = 97, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[11] + TRIGGER_TCPWM1_TR_IN12 = 98, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[12] + TRIGGER_TCPWM1_TR_IN13 = 99, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[13] + TRIGGER_USB_DMA_BURSTEND0 = 100, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0] + TRIGGER_USB_DMA_BURSTEND1 = 101, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1] + TRIGGER_USB_DMA_BURSTEND2 = 102, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2] + TRIGGER_USB_DMA_BURSTEND3 = 103, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3] + TRIGGER_USB_DMA_BURSTEND4 = 104, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4] + TRIGGER_USB_DMA_BURSTEND5 = 105, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5] + TRIGGER_USB_DMA_BURSTEND6 = 106, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6] + TRIGGER_USB_DMA_BURSTEND7 = 107, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7] +} cyhal_trigger_dest_psoc6_03_t; + +/** Typedef from device family specific trigger dest to generic trigger dest */ +typedef cyhal_trigger_dest_psoc6_03_t cyhal_dest_t; + +/** \cond INTERNAL */ +/** Maps each cyhal_destination_t to a mux index. + * If bit 8 of the mux index is set, this denotes that the trigger is a + * one to one trigger. + */ +extern const uint8_t cyhal_dest_to_mux[108]; + +/* Maps each cyhal_destination_t to a specific output in its mux */ +extern const uint8_t cyhal_mux_dest_index[108]; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +/** \} group_hal_psoc6_triggers_psoc6_03 */ +#endif /* _CYHAL_TRIGGERS_PSOC6_03_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c index 4072f59864..4a7f8a9a30 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -185,7 +185,7 @@ cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_d cy_rslt_t result = CY_RSLT_SUCCESS; - if (CYHAL_NC_PIN_VALUE == pin) + if (CYHAL_NC_PIN_VALUE == pin) result = CYHAL_ADC_RSLT_BAD_ARGUMENT; if (CY_RSLT_SUCCESS == result) @@ -228,7 +228,7 @@ cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_d } if (CY_RSLT_SUCCESS == result) - { + { if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num)) result = CYHAL_ADC_RSLT_FAILED_CLOCK; } @@ -355,7 +355,7 @@ void cyhal_adc_channel_free(cyhal_adc_channel_t *obj) Cy_SAR_SetSwitchSarSeqCtrl(obj->adc->base, mux_ctrl, CY_SAR_SWITCH_SEQ_CTRL_DISABLE); obj->adc->base->CHAN_CONFIG[obj->channel_idx] = 0; - cyhal_gpio_free(obj->pin); + cyhal_utils_release_if_used(&(obj->pin)); obj->adc = NULL; } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_analog_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_analog_common.c similarity index 96% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_analog_common.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_analog_common.c index 33e55ad749..55a618fb76 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_analog_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_analog_common.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crc.c similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crc.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crc.c index 867c0056af..0bcd511961 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crc.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crypto_common.c similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crypto_common.c index 2397ba0d8b..3079c1cc91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crypto_common.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dac.c similarity index 96% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dac.c index f0805d15ee..4442257fcb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dac.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -148,11 +148,7 @@ void cyhal_dac_free(cyhal_dac_t *obj) cyhal_hwmgr_free(&obj->resource); - if(obj->pin != CYHAL_NC_PIN_VALUE) - { - cyhal_gpio_free(obj->pin); - obj->pin = CYHAL_NC_PIN_VALUE; - } + cyhal_utils_release_if_used(&(obj->pin)); obj->base = NULL; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma.c new file mode 100644 index 0000000000..438311d7b4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma.c @@ -0,0 +1,206 @@ +/***************************************************************************//** +* \file cyhal_dma.c +* +* \brief +* Implements a high level interface for interacting with the Cypress DMA. +* This implementation abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cyhal_dma_dmac.h" +#include "cyhal_dma_dw.h" +#include "cyhal_hwmgr.h" +#include "cyhal_system.h" +#include "cyhal_utils.h" + +/** +* \addtogroup group_hal_dma DMA (Direct Memory Access) +* \ingroup group_hal +* \{ +*/ + +#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +cy_rslt_t cyhal_dma_init(cyhal_dma_t *obj, uint8_t priority, cyhal_dma_direction_t direction) +{ + CY_ASSERT(NULL != obj); + +#if !defined(CY_IP_M4CPUSS_DMAC) && defined(CY_IP_M4CPUSS_DMA) + /* Only DW available. Ignore direction for purpose of choosing DMA type. */ + CY_UNUSED_PARAMETER(direction); + return cyhal_dma_init_dw(obj, priority); +#elif defined(CY_IP_M4CPUSS_DMAC) && !defined(CY_IP_M4CPUSS_DMA) + /* Only DMAC available. Ignore direction for purpose of choosing DMA type. */ + CY_UNUSED_PARAMETER(direction); + return cyhal_dma_init_dmac(obj, priority); +#else + /* DMAC is designed with high memory bandwidth for memory to memory + * transfers so prefer it when direction is MEM2MEM. Otherwise prefer + * Datawire as it is designed for low latency memory to peripheral or + * peripheral to memory transfers. Note: Both DMA types can handle any + * direction value so using a non-ideal DMA type is ok.*/ + cy_rslt_t rslt; + if(direction == CYHAL_DMA_DIRECTION_MEM2MEM) + { + rslt = cyhal_dma_init_dmac(obj, priority); + /* If no DMAC channels are available fall back on DW. */ + if(CYHAL_HWMGR_RSLT_ERR_NONE_FREE == rslt) + rslt = cyhal_dma_init_dw(obj, priority); + } + else + { + rslt = cyhal_dma_init_dw(obj, priority); + /* If no DW channels are available fall back on DMAC. */ + if(CYHAL_HWMGR_RSLT_ERR_NONE_FREE == rslt) + rslt = cyhal_dma_init_dmac(obj, priority); + } + return rslt; +#endif +} + +void cyhal_dma_free(cyhal_dma_t *obj) +{ + CY_ASSERT(NULL != obj); + + CY_ASSERT(!cyhal_dma_is_busy(obj)); + +#ifdef CY_IP_M4CPUSS_DMAC + if(obj->resource.type == CYHAL_RSC_DMA) + { + cyhal_dma_free_dmac(obj); + } +#endif +#ifdef CY_IP_M4CPUSS_DMA + if(obj->resource.type == CYHAL_RSC_DW) + { + cyhal_dma_free_dw(obj); + } +#endif +} + +cy_rslt_t cyhal_dma_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg) +{ + CY_ASSERT(NULL != obj); + +#ifdef CY_IP_M4CPUSS_DMAC + if(obj->resource.type == CYHAL_RSC_DMA) + { + return cyhal_dma_configure_dmac(obj, cfg); + } +#endif +#ifdef CY_IP_M4CPUSS_DMA + if(obj->resource.type == CYHAL_RSC_DW) + { + return cyhal_dma_configure_dw(obj, cfg); + } +#endif + + /* Control should never reach here but return value anyway to appease + * compilers */ + CY_ASSERT(false); + return CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE; +} + +cy_rslt_t cyhal_dma_start_transfer(cyhal_dma_t *obj) +{ + CY_ASSERT(NULL != obj); + +#ifdef CY_IP_M4CPUSS_DMAC + if(obj->resource.type == CYHAL_RSC_DMA) + { + return cyhal_dma_start_transfer_dmac(obj); + } +#endif +#ifdef CY_IP_M4CPUSS_DMA + if(obj->resource.type == CYHAL_RSC_DW) + { + return cyhal_dma_start_transfer_dw(obj); + } +#endif + + /* Control should never reach here but return value anyway to appease + * compilers */ + CY_ASSERT(false); + return CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE; +} + +bool cyhal_dma_is_busy(cyhal_dma_t *obj) +{ + CY_ASSERT(NULL != obj); + +#ifdef CY_IP_M4CPUSS_DMAC + if(obj->resource.type == CYHAL_RSC_DMA) + { + return cyhal_dma_is_busy_dmac(obj); + } +#endif +#ifdef CY_IP_M4CPUSS_DMA + if(obj->resource.type == CYHAL_RSC_DW) + { + return cyhal_dma_is_busy_dw(obj); + } +#endif + + /* Control should never reach here but return value anyway to appease + * compilers */ + CY_ASSERT(false); + return CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE; +} + +void cyhal_dma_register_callback(cyhal_dma_t *obj, cyhal_dma_event_callback_t callback, void *callback_arg) +{ + CY_ASSERT(NULL != obj); + + uint32_t saved_intr_status = cyhal_system_critical_section_enter(); + obj->callback_data.callback = (cy_israddress)callback; + obj->callback_data.callback_arg = callback_arg; + cyhal_system_critical_section_exit(saved_intr_status); +} + +void cyhal_dma_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable) +{ + CY_ASSERT(NULL != obj); + +#ifdef CY_IP_M4CPUSS_DMAC + if(obj->resource.type == CYHAL_RSC_DMA) + { + cyhal_dma_enable_event_dmac(obj, event, intrPriority, enable); + } +#endif +#ifdef CY_IP_M4CPUSS_DMA + if(obj->resource.type == CYHAL_RSC_DW) + { + cyhal_dma_enable_event_dw(obj, event, intrPriority, enable); + } +#endif +} + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) */ + +/** \} group_hal_dma */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dmac.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dmac.c new file mode 100644 index 0000000000..9d4923b3fd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dmac.c @@ -0,0 +1,364 @@ +/***************************************************************************//** +* \file cyhal_dma_dmac.c +* +* \brief +* Implements a high level interface for interacting with the Cypress DMAC. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cyhal_dma.h" +#include "cyhal_dma_dmac.h" +#include "cyhal_dma_impl.h" +#include "cyhal_hwmgr.h" +#include "cyhal_system.h" +#include "cyhal_utils.h" +#include "cyhal_triggers.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#ifdef CY_IP_M4CPUSS_DMAC + +static cyhal_dma_t* cyhal_dmac_config_structs[CPUSS_DMAC_CH_NR]; + +/** Default dmac descriptor config */ +static const cy_stc_dmac_descriptor_config_t default_descriptor_config_dmac = +{ + .retrigger = CY_DMAC_RETRIG_IM, + .interruptType = CY_DMAC_DESCR, + .triggerOutType = CY_DMAC_DESCR_CHAIN, + .channelState = CY_DMAC_CHANNEL_ENABLED, + .triggerInType = CY_DMAC_DESCR, + .dataPrefetch = false, + .dataSize = CY_DMAC_WORD, + .srcTransferSize = CY_DMAC_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMAC_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMAC_1D_TRANSFER, + .srcAddress = 0, + .dstAddress = 0, + .srcXincrement = 1U, + .dstXincrement = 1U, + .xCount = 1UL, + .srcYincrement = 0U, + .dstYincrement = 0U, + .yCount = 1UL, + .nextDescriptor = 0, +}; + +/** Default dmac channel config */ +static const cy_stc_dmac_channel_config_t default_channel_config_dmac = +{ + .descriptor = 0, + .priority = 1, + .enable = false, + .bufferable = false, +}; + +/** Sets the dmac configuration struct */ +static inline void cyhal_dma_set_dmac_obj(cyhal_dma_t *obj) +{ + cyhal_dmac_config_structs[obj->resource.block_num * CPUSS_DMAC_CH_NR + obj->resource.channel_num] = obj; +} + +/** Zeros the dmac configuration struct */ +static inline void cyhal_dma_free_dmac_obj(cyhal_dma_t *obj) +{ + cyhal_dmac_config_structs[obj->resource.block_num * CPUSS_DMAC_CH_NR + obj->resource.channel_num] = NULL; +} + +/** Gets the dmac configuration struct from block and channel */ +static inline cyhal_dma_t* cyhal_dma_get_dmac_obj(uint8_t block, uint8_t channel) +{ + return cyhal_dmac_config_structs[block * CPUSS_DMAC_CH_NR + channel]; +} + +/** Gets the dmac block number from irq number */ +/** This should never be called from a non-dma IRQn */ +static inline uint8_t cyhal_dma_get_dmac_block_from_irqn(IRQn_Type irqn) +{ + /* Since there is only one dmac block this function always returns 0. diff + * is calculated here only to verify that this was called from a valid + * IRQn. */ + CY_UNUSED uint8_t diff = irqn - cpuss_interrupts_dmac_0_IRQn; + + CY_ASSERT(diff < CPUSS_DMAC_CH_NR); + + return 0; +} + +/** Gets the dmac channel number from irq number */ +/** This should never be called from a non-dma IRQn */ +static inline uint8_t cyhal_dma_get_dmac_channel_from_irqn(IRQn_Type irqn) +{ + uint8_t diff = irqn - cpuss_interrupts_dmac_0_IRQn; + + CY_ASSERT(diff < CPUSS_DMAC_CH_NR); + + return diff; +} + +/** Gets the irqn corresponding to a particular cyhal_dma_t config struct */ +static inline IRQn_Type cyhal_dma_get_dmac_irqn(cyhal_dma_t *obj) +{ + return (IRQn_Type)((uint8_t)cpuss_interrupts_dmac_0_IRQn + (obj->resource.block_num * CPUSS_DMAC_CH_NR + obj->resource.channel_num)); +} + +/** Gets the dmac base pointer from block number */ +static inline DMAC_Type* cyhal_dma_get_dmac_base(uint8_t block_num) +{ + return DMAC; +} + +/** Uses tables provided as part of the hal interconnect driver to determine mux + * trigger group and mux trigger index and then construct the trigger line + * input parameter to Cy_TrigMux_SwTrigger. */ +static inline uint32_t cyhal_dma_get_dmac_trigger_line(uint8_t block_num, uint8_t channel_num) +{ + /* cyhal_dest_t triggers are guaranteed to be sorted by trigger type, block + * num, then channel num, therefore, we can just directly find the proper + * trigger by calculating an offset. */ + cyhal_dest_t trigger = (cyhal_dest_t)(TRIGGER_CPUSS_DMAC_TR_IN0 + (block_num * CPUSS_DMAC_CH_NR) + channel_num); + + /* One to one triggers have bit 8 set in cyhal_dest_to_mux but + * Cy_TrigMux_SwTrigger wants the trigger group field to have bit 5 set to + * denote one to one triggers. */ + uint8_t trig_group = cyhal_dest_to_mux[trigger]; + /* If hal one to one triggers bit is set: mask it out and set pdl one to + * one bit */ + if(trig_group & HAL_TRIGGERS_1TO1_MASK) + trig_group = (trig_group & ~HAL_TRIGGERS_1TO1_MASK) | PDL_TRIGGERS_1TO1_MASK; + + /* Construct trigger line which consists of three fields packed into a + * uint32_t: + * Bits 30: Input/output bit. Set to 1 for output. + * Bits 12-8: Trigger group selection. + * Bits 7-0: Select the output trigger number in the trigger group. */ + return PERI_TR_CMD_OUT_SEL_Msk | trig_group << 8 | cyhal_mux_dest_index[trigger]; +} + +/** Convert PDL interrupt cause to hal dma event */ +static inline cyhal_dma_event_t cyhal_dma_convert_dmac_interrupt_cause(uint32_t cause) +{ + switch(cause) + { + case CY_DMAC_INTR_COMPLETION: + return CYHAL_DMA_TRANSFER_COMPLETE; + case CY_DMAC_INTR_SRC_BUS_ERROR: + return CYHAL_DMA_SRC_BUS_ERROR; + case CY_DMAC_INTR_DST_BUS_ERROR: + return CYHAL_DMA_DST_BUS_ERROR; + case CY_DMAC_INTR_SRC_MISAL: + return CYHAL_DMA_SRC_MISAL; + case CY_DMAC_INTR_DST_MISAL: + return CYHAL_DMA_DST_MISAL; + case CY_DMAC_INTR_CURR_PTR_NULL: + return CYHAL_DMA_CURR_PTR_NULL; + case CY_DMAC_INTR_ACTIVE_CH_DISABLED: + return CYHAL_DMA_ACTIVE_CH_DISABLED; + case CY_DMAC_INTR_DESCR_BUS_ERROR: + return CYHAL_DMA_DESCR_BUS_ERROR; + default: + return CYHAL_DMA_NO_INTR; + } +} + +/** DMAC irq handler */ +static void cyhal_dma_irq_handler_dmac(void) +{ + /* Use irqn to get appropriate config structure */ + uint8_t block = cyhal_dma_get_dmac_block_from_irqn(CYHAL_GET_CURRENT_IRQN()); + uint8_t channel = cyhal_dma_get_dmac_channel_from_irqn(CYHAL_GET_CURRENT_IRQN()); + cyhal_dma_t *obj = cyhal_dma_get_dmac_obj(block, channel); + + /* Get interrupt type and call users event callback if they have enabled that event */ + uint32_t cause = Cy_DMAC_Channel_GetInterruptStatusMasked(cyhal_dma_get_dmac_base(block), channel); + cyhal_dma_event_t event_type = cyhal_dma_convert_dmac_interrupt_cause(cause); + uint32_t events_to_callback = event_type && obj->irq_cause; + if(obj->callback_data.callback != NULL && events_to_callback) + { + ((cyhal_dma_event_callback_t)obj->callback_data.callback)(obj->callback_data.callback_arg, (cyhal_dma_event_t)events_to_callback); + } + + /* Clear all interrupts */ + Cy_DMAC_Channel_ClearInterrupt(cyhal_dma_get_dmac_base(block), channel, CY_DMAC_INTR_MASK); +} + +cy_rslt_t cyhal_dma_init_dmac(cyhal_dma_t *obj, uint8_t priority) +{ + if(!CY_DMAC_IS_PRIORITY_VALID(priority)) + return CYHAL_DMA_RSLT_ERR_INVALID_PRIORITY; + + cy_rslt_t rslt = cyhal_hwmgr_allocate(CYHAL_RSC_DMA, &obj->resource); + if(rslt != CY_RSLT_SUCCESS) + return rslt; + + /* Setup descriptor and channel configs */ + obj->descriptor_config.dmac = default_descriptor_config_dmac; + obj->channel_config.dmac = default_channel_config_dmac; + obj->channel_config.dmac.descriptor = &obj->descriptor.dmac; + obj->channel_config.dmac.priority = priority; + + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + obj->irq_cause = 0; + + cyhal_dma_set_dmac_obj(obj); + + return CY_RSLT_SUCCESS; +} + +void cyhal_dma_free_dmac(cyhal_dma_t *obj) +{ + Cy_DMAC_Descriptor_DeInit(&obj->descriptor.dmac); + Cy_DMAC_Channel_DeInit(cyhal_dma_get_dmac_base(obj->resource.block_num), obj->resource.channel_num); + + NVIC_DisableIRQ(cyhal_dma_get_dmac_irqn(obj)); + + cyhal_dma_free_dmac_obj(obj); + cyhal_hwmgr_free(&obj->resource); +} + +/* Initalize descriptor, initialize channel, enable channel, enable channel + * interrupt, and enable DMAC controller */ +cy_rslt_t cyhal_dma_configure_dmac(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg) +{ + /* Do not reconfigure if transfer is pending/active already */ + if(cyhal_dma_is_busy_dmac(obj)) + return CYHAL_DMA_RSLT_ERR_CHANNEL_BUSY; + + obj->descriptor_config.dmac.srcAddress = (void*)cfg->src_addr; + obj->descriptor_config.dmac.dstAddress = (void*)cfg->dst_addr; + obj->descriptor_config.dmac.nextDescriptor = &obj->descriptor.dmac; + + if(cfg->transfer_width == 8) + obj->descriptor_config.dmac.dataSize = CY_DMAC_BYTE; + else if(cfg->transfer_width == 16) + obj->descriptor_config.dmac.dataSize = CY_DMAC_HALFWORD; + else if(cfg->transfer_width == 32) + obj->descriptor_config.dmac.dataSize = CY_DMAC_WORD; + else + return CYHAL_DMA_RSLT_ERR_INVALID_TRANSFER_WIDTH; + + /* Length must be a multiple of burst_size */ + if(cfg->burst_size != 0 && cfg->length % cfg->burst_size != 0) + return CYHAL_DMA_RSLT_ERR_INVALID_BURST_SIZE; + + /* Setup 2D transfer if burst_size is being used otherwise set up 1D + * transfer */ + if(cfg->burst_size != 0) + { + obj->descriptor_config.dmac.descriptorType = CY_DMAC_2D_TRANSFER; + obj->descriptor_config.dmac.xCount = cfg->burst_size; + obj->descriptor_config.dmac.yCount = cfg->length / cfg->burst_size; + obj->descriptor_config.dmac.srcXincrement = cfg->src_increment; + obj->descriptor_config.dmac.dstXincrement = cfg->dst_increment; + obj->descriptor_config.dmac.srcYincrement = cfg->src_increment * cfg->burst_size; + obj->descriptor_config.dmac.dstYincrement = cfg->dst_increment * cfg->burst_size; + + /* If burst action, configure trigger and interrupt actions */ + if(cfg->action == CYHAL_DMA_TRANSFER_BURST) + { + obj->descriptor_config.dmac.interruptType = CY_DMAC_X_LOOP; + obj->descriptor_config.dmac.triggerInType = CY_DMAC_X_LOOP; + } + } + else + { + obj->descriptor_config.dmac.descriptorType = CY_DMAC_1D_TRANSFER; + obj->descriptor_config.dmac.xCount = cfg->length; + obj->descriptor_config.dmac.srcXincrement = cfg->src_increment; + obj->descriptor_config.dmac.dstXincrement = cfg->dst_increment; + + obj->descriptor_config.dmac.interruptType = CY_DMAC_DESCR; + obj->descriptor_config.dmac.triggerInType = CY_DMAC_DESCR; + } + + if(CY_DMAC_SUCCESS != Cy_DMAC_Descriptor_Init(&obj->descriptor.dmac, &obj->descriptor_config.dmac)) + return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER; + + /* Setup channel and enable */ + DMAC_Type* base = cyhal_dma_get_dmac_base(obj->resource.block_num); + if(CY_DMAC_SUCCESS != Cy_DMAC_Channel_Init(base, obj->resource.channel_num, &obj->channel_config.dmac)) + return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER; + Cy_DMAC_Channel_SetDescriptor(base, obj->resource.channel_num, &obj->descriptor.dmac); + Cy_DMAC_Channel_SetPriority(base, obj->resource.channel_num, obj->channel_config.dmac.priority); + Cy_DMAC_Channel_Enable(base, obj->resource.channel_num); + Cy_DMAC_Channel_SetInterruptMask (base, obj->resource.channel_num, CY_DMAC_INTR_MASK); + + Cy_DMAC_Enable(base); + + /* src_misal and dst_misal interrupts are triggered immediately on enable + * so return those errors here */ + uint32_t status = Cy_DMAC_Channel_GetInterruptStatus(base, obj->resource.channel_num); + if((status & CY_DMAC_INTR_SRC_MISAL) || + (status & CY_DMAC_INTR_DST_MISAL)) + { + /* Clear all interrupts and return error */ + Cy_DMAC_Channel_ClearInterrupt(base, obj->resource.channel_num, CY_DMAC_INTR_MASK); + return CYHAL_DMA_RSLT_ERR_INVALID_ALIGNMENT; + } + + /* Enable interrupt for this channel */ + cy_stc_sysint_t irqCfg = { cyhal_dma_get_dmac_irqn(obj), CYHAL_ISR_PRIORITY_DEFAULT }; + if(CY_SYSINT_SUCCESS != Cy_SysInt_Init(&irqCfg, cyhal_dma_irq_handler_dmac)) + return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER; + NVIC_EnableIRQ(irqCfg.intrSrc); + + return CY_RSLT_SUCCESS; +} + +cy_rslt_t cyhal_dma_start_transfer_dmac(cyhal_dma_t *obj) +{ + /* Return warning if channel is busy */ + if(cyhal_dma_is_busy_dmac(obj)) + return CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED; + + uint32_t trigline = cyhal_dma_get_dmac_trigger_line(obj->resource.block_num, obj->resource.channel_num); + cy_en_trigmux_status_t trig_status = Cy_TrigMux_SwTrigger(trigline, CY_TRIGGER_TWO_CYCLES); + + /* Also return warning if SW trigger is already initated but DMA hardware + * has not seen it yet */ + if(trig_status == CY_TRIGMUX_INVALID_STATE) + return CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED; + else + return CY_RSLT_SUCCESS; +} + +void cyhal_dma_enable_event_dmac(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable) +{ + if(enable) + obj->irq_cause |= event; + else + obj->irq_cause &= ~event; + + NVIC_SetPriority(cyhal_dma_get_dmac_irqn(obj), intrPriority); +} + +bool cyhal_dma_is_busy_dmac(cyhal_dma_t *obj) +{ + /* The ACTIVE register is a bit field of all pending or active channels */ + return cyhal_dma_get_dmac_base(obj->resource.block_num)->ACTIVE & (1 << obj->resource.channel_num); +} + +#endif /* CY_IP_M4CPUSS_DMAC */ + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dw.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dw.c new file mode 100644 index 0000000000..694ef842eb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dw.c @@ -0,0 +1,402 @@ +/***************************************************************************//** +* \file cyhal_dma_dw.c +* +* \brief +* Implements a high level interface for interacting with the Cypress Datawire DMA. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cyhal_dma.h" +#include "cyhal_dma_dw.h" +#include "cyhal_dma_impl.h" +#include "cyhal_hwmgr.h" +#include "cyhal_system.h" +#include "cyhal_utils.h" +#include "cyhal_triggers.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#ifdef CY_IP_M4CPUSS_DMA + +#if (CPUSS_DW0_PRESENT==1) && (CPUSS_DW1_PRESENT==1) +#define NUM_DW_CHANNELS (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR) +#elif (CPUSS_DW0_PRESENT==1) +#define NUM_DW_CHANNELS (CPUSS_DW0_CH_NR) +#endif + +static cyhal_dma_t* cyhal_dw_config_structs[NUM_DW_CHANNELS]; + +/** Default dw descriptor config */ +static const cy_stc_dma_descriptor_config_t default_descriptor_config_dw = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_DESCR_CHAIN, + .channelState = CY_DMA_CHANNEL_ENABLED, + .triggerInType = CY_DMA_DESCR, + .dataSize = CY_DMA_WORD, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = 0, + .dstAddress = 0, + .srcXincrement = 1U, + .dstXincrement = 1U, + .xCount = 1UL, + .srcYincrement = 0U, + .dstYincrement = 0U, + .yCount = 1UL, + .nextDescriptor = 0, +}; + +/** Default dw channel config */ +static const cy_stc_dma_channel_config_t default_channel_config_dw = +{ + .descriptor = 0, + .preemptable = false, + .priority = 1, + .enable = false, + .bufferable = false, +}; + +/** Sets the dw configuration struct */ +static inline void cyhal_dma_set_dw_obj(cyhal_dma_t *obj) +{ + cyhal_dw_config_structs[obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num] = obj; +} + +/** Zeros the dw configuration struct */ +static inline void cyhal_dma_free_dw_obj(cyhal_dma_t *obj) +{ + cyhal_dw_config_structs[obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num] = NULL; +} + +/** Gets the dw configuration struct from block and channel */ +static inline cyhal_dma_t* cyhal_dma_get_dw_obj(uint8_t block, uint8_t channel) +{ + return cyhal_dw_config_structs[block * CPUSS_DW0_CH_NR + channel]; +} + +/** Gets the dw block number from irq number */ +/** This should never be called from a non-dma IRQn */ +static inline uint8_t cyhal_dma_get_dw_block_from_irqn(IRQn_Type irqn) +{ + uint8_t diff = irqn - cpuss_interrupts_dw0_0_IRQn; +#if defined(CPUSS_DW0_CH_NR) && !defined(CPUSS_DW1_CH_NR) + CY_ASSERT(diff < CPUSS_DW0_CH_NR); + + if(diff < CPUSS_DW0_CH_NR) + return 0; +#elif defined(CPUSS_DW0_CH_NR) && defined(CPUSS_DW1_CH_NR) + CY_ASSERT(diff < CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR); + + if(diff < CPUSS_DW0_CH_NR) + return 0; + if(diff < CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR) + return 1; +#endif + + // Should never reach here. Just silencing compiler warnings. + CY_ASSERT(false); + return 255; +} + +/** Gets the dw channel number from irq number */ +/** This should never be called from a non-dma IRQn */ +static inline uint8_t cyhal_dma_get_dw_channel_from_irqn(IRQn_Type irqn) +{ + uint8_t diff = irqn - cpuss_interrupts_dw0_0_IRQn; +#if defined(CPUSS_DW0_CH_NR) && !defined(CPUSS_DW1_CH_NR) + CY_ASSERT(diff < CPUSS_DW0_CH_NR); + + if(diff < CPUSS_DW0_CH_NR) + return diff; +#elif defined(CPUSS_DW0_CH_NR) && defined(CPUSS_DW1_CH_NR) + CY_ASSERT(diff < CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR); + + if(diff < CPUSS_DW0_CH_NR) + return diff; + else + return diff - CPUSS_DW0_CH_NR; +#endif +} + +/** Gets the irqn corresponding to a particular cyhal_dma_t config struct */ +static inline IRQn_Type cyhal_dma_get_dw_irqn(cyhal_dma_t *obj) +{ + return (IRQn_Type)((uint8_t)cpuss_interrupts_dw0_0_IRQn + (obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num)); +} + +/** Gets the dw base pointer from block number */ +static inline DW_Type* cyhal_dma_get_dw_base(uint8_t block_num) +{ + return block_num == 0 ? DW0 : DW1; +} + +/** Uses tables provided as part of the hal interconnect driver to determine mux + * trigger group and mux trigger index and then construct the trigger line + * input parameter to Cy_TrigMux_SwTrigger. */ +static inline uint32_t cyhal_dma_get_dw_trigger_line(uint8_t block_num, uint8_t channel_num) +{ + /* cyhal_dest_t triggers are guaranteed to be sorted by trigger type, block + * num, then channel num, therefore, we can just directly find the proper + * trigger by calculating an offset. */ + cyhal_dest_t trigger = (cyhal_dest_t)(TRIGGER_CPUSS_DW0_TR_IN0 + (block_num * CPUSS_DW0_CH_NR) + channel_num); + + /* One to one triggers have bit 8 set in cyhal_dest_to_mux but + * Cy_TrigMux_SwTrigger wants the trigger group field to have bit 5 set to + * denote one to one triggers. */ + uint8_t trig_group = cyhal_dest_to_mux[trigger]; + /* If hal one to one triggers bit is set: mask it out and set pdl one to + * one bit */ + if(trig_group & HAL_TRIGGERS_1TO1_MASK) + trig_group = (trig_group & ~HAL_TRIGGERS_1TO1_MASK) | PDL_TRIGGERS_1TO1_MASK; + + /* Construct trigger line which consists of three fields packed into a + * uint32_t: + * Bits 30: Input/output bit. Set to 1 for output. + * Bits 12-8: Trigger group selection. + * Bits 7-0: Select the output trigger number in the trigger group. */ + return PERI_TR_CMD_OUT_SEL_Msk | trig_group << 8 | cyhal_mux_dest_index[trigger]; +} + +/** Convert PDL interrupt cause to hal dma event */ +static inline cyhal_dma_event_t cyhal_dma_convert_dw_interrupt_cause(cy_en_dma_intr_cause_t cause) +{ + switch(cause) + { + case CY_DMA_INTR_CAUSE_NO_INTR: + return CYHAL_DMA_NO_INTR; + case CY_DMA_INTR_CAUSE_COMPLETION: + return CYHAL_DMA_TRANSFER_COMPLETE; + case CY_DMA_INTR_CAUSE_SRC_BUS_ERROR: + return CYHAL_DMA_SRC_BUS_ERROR; + case CY_DMA_INTR_CAUSE_DST_BUS_ERROR: + return CYHAL_DMA_DST_BUS_ERROR; + case CY_DMA_INTR_CAUSE_SRC_MISAL: + return CYHAL_DMA_SRC_MISAL; + case CY_DMA_INTR_CAUSE_DST_MISAL: + return CYHAL_DMA_DST_MISAL; + case CY_DMA_INTR_CAUSE_CURR_PTR_NULL: + return CYHAL_DMA_CURR_PTR_NULL; + case CY_DMA_INTR_CAUSE_ACTIVE_CH_DISABLED: + return CYHAL_DMA_ACTIVE_CH_DISABLED; + case CY_DMA_INTR_CAUSE_DESCR_BUS_ERROR: + return CYHAL_DMA_DESCR_BUS_ERROR; + default: + return CYHAL_DMA_NO_INTR; + } +} + +/** DW irq handler */ +static void cyhal_dma_irq_handler_dw(void) +{ + /* Use irqn to get appropriate config structure */ + uint8_t block = cyhal_dma_get_dw_block_from_irqn(CYHAL_GET_CURRENT_IRQN()); + uint8_t channel = cyhal_dma_get_dw_channel_from_irqn(CYHAL_GET_CURRENT_IRQN()); + cyhal_dma_t *obj = cyhal_dma_get_dw_obj(block, channel); + + /* Get interrupt type and call users event callback if they have enabled that event */ + cy_en_dma_intr_cause_t cause = Cy_DMA_Channel_GetStatus(cyhal_dma_get_dw_base(block), channel); + cyhal_dma_event_t event_type = cyhal_dma_convert_dw_interrupt_cause(cause); + uint32_t events_to_callback = event_type && obj->irq_cause; + if(obj->callback_data.callback != NULL && events_to_callback) + { + ((cyhal_dma_event_callback_t)obj->callback_data.callback)(obj->callback_data.callback_arg, (cyhal_dma_event_t)events_to_callback); + } + + /* Clear all interrupts */ + Cy_DMA_Channel_ClearInterrupt(cyhal_dma_get_dw_base(block), channel); +} + +cy_rslt_t cyhal_dma_init_dw(cyhal_dma_t *obj, uint8_t priority) +{ + if(!CY_DMA_IS_PRIORITY_VALID(priority)) + return CYHAL_DMA_RSLT_ERR_INVALID_PRIORITY; + + cy_rslt_t rslt = cyhal_hwmgr_allocate(CYHAL_RSC_DW, &obj->resource); + if(rslt != CY_RSLT_SUCCESS) + return rslt; + + /* Setup descriptor and channel configs */ + obj->descriptor_config.dw = default_descriptor_config_dw; + obj->channel_config.dw = default_channel_config_dw; + obj->channel_config.dw.descriptor = &obj->descriptor.dw; + obj->channel_config.dw.priority = priority; + + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + obj->irq_cause = 0; + + cyhal_dma_set_dw_obj(obj); + + return CY_RSLT_SUCCESS; +} + +void cyhal_dma_free_dw(cyhal_dma_t *obj) +{ + Cy_DMA_Descriptor_DeInit(&obj->descriptor.dw); + Cy_DMA_Channel_DeInit(cyhal_dma_get_dw_base(obj->resource.block_num), obj->resource.channel_num); + + NVIC_DisableIRQ(cyhal_dma_get_dw_irqn(obj)); + + cyhal_dma_free_dw_obj(obj); + cyhal_hwmgr_free(&obj->resource); +} + +/* Initalize descriptor, initialize channel, enable channel, enable channel + * interrupt, and enable DW controller */ +cy_rslt_t cyhal_dma_configure_dw(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg) +{ + /* Do not reconfigure if transfer is pending/active already */ + if(cyhal_dma_is_busy_dw(obj)) + return CYHAL_DMA_RSLT_ERR_CHANNEL_BUSY; + + obj->descriptor_config.dw.srcAddress = (void*)cfg->src_addr; + obj->descriptor_config.dw.dstAddress = (void*)cfg->dst_addr; + obj->descriptor_config.dw.nextDescriptor = &obj->descriptor.dw; + + if(cfg->transfer_width == 8) + obj->descriptor_config.dw.dataSize = CY_DMA_BYTE; + else if(cfg->transfer_width == 16) + obj->descriptor_config.dw.dataSize = CY_DMA_HALFWORD; + else if(cfg->transfer_width == 32) + obj->descriptor_config.dw.dataSize = CY_DMA_WORD; + else + return CYHAL_DMA_RSLT_ERR_INVALID_TRANSFER_WIDTH; + + /* Length must be a multiple of burst_size */ + if(cfg->burst_size != 0 && cfg->length % cfg->burst_size != 0) + return CYHAL_DMA_RSLT_ERR_INVALID_BURST_SIZE; + + /* Setup 2D transfer if burst_size is being used otherwise set up 1D + * transfer */ + if(cfg->burst_size != 0) + { + obj->descriptor_config.dw.descriptorType = CY_DMA_2D_TRANSFER; + obj->descriptor_config.dw.xCount = cfg->burst_size; + obj->descriptor_config.dw.yCount = cfg->length / cfg->burst_size; + obj->descriptor_config.dw.srcXincrement = cfg->src_increment; + obj->descriptor_config.dw.dstXincrement = cfg->dst_increment; + obj->descriptor_config.dw.srcYincrement = cfg->src_increment * cfg->burst_size; + obj->descriptor_config.dw.dstYincrement = cfg->dst_increment * cfg->burst_size; + + /* If burst action, configure trigger and interrupt actions */ + if(cfg->action == CYHAL_DMA_TRANSFER_BURST) + { + obj->descriptor_config.dw.interruptType = CY_DMA_X_LOOP; + obj->descriptor_config.dw.triggerInType = CY_DMA_X_LOOP; + } + } + else + { + obj->descriptor_config.dw.descriptorType = CY_DMA_1D_TRANSFER; + obj->descriptor_config.dw.xCount = cfg->length; + obj->descriptor_config.dw.srcXincrement = cfg->src_increment; + obj->descriptor_config.dw.dstXincrement = cfg->dst_increment; + + obj->descriptor_config.dw.interruptType = CY_DMA_DESCR; + obj->descriptor_config.dw.triggerInType = CY_DMA_DESCR; + } + + if(CY_DMA_SUCCESS != Cy_DMA_Descriptor_Init(&obj->descriptor.dw, &obj->descriptor_config.dw)) + return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER; + + /* Setup channel and enable */ + DW_Type* base = cyhal_dma_get_dw_base(obj->resource.block_num); + if(CY_DMA_SUCCESS != Cy_DMA_Channel_Init(base, obj->resource.channel_num, &obj->channel_config.dw)) + return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER; + Cy_DMA_Channel_SetDescriptor(base, obj->resource.channel_num, &obj->descriptor.dw); + Cy_DMA_Channel_SetPriority(base, obj->resource.channel_num, obj->channel_config.dw.priority); + Cy_DMA_Channel_Enable(base, obj->resource.channel_num); + Cy_DMA_Channel_SetInterruptMask (base, obj->resource.channel_num, CY_DMA_INTR_MASK); + + Cy_DMA_Enable(base); + + /* src_misal and dst_misal interrupts are triggered immediately on enable + * so return those errors here */ + uint32_t status = Cy_DMA_Channel_GetInterruptStatus(base, obj->resource.channel_num); + if((status & CY_DMA_INTR_CAUSE_SRC_MISAL) || + (status & CY_DMA_INTR_CAUSE_DST_MISAL)) + { + Cy_DMA_Channel_ClearInterrupt(base, obj->resource.channel_num); + return CYHAL_DMA_RSLT_ERR_INVALID_ALIGNMENT; + } + + /* Enable interrupt for this channel */ + cy_stc_sysint_t irqCfg = { cyhal_dma_get_dw_irqn(obj), CYHAL_ISR_PRIORITY_DEFAULT }; + if(CY_SYSINT_SUCCESS != Cy_SysInt_Init(&irqCfg, cyhal_dma_irq_handler_dw)) + return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER; + NVIC_EnableIRQ(irqCfg.intrSrc); + + return CY_RSLT_SUCCESS; +} + +cy_rslt_t cyhal_dma_start_transfer_dw(cyhal_dma_t *obj) +{ + /* Return warning if channel is busy */ + if(cyhal_dma_is_busy_dw(obj)) + return CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED; + + uint32_t trigline = cyhal_dma_get_dw_trigger_line(obj->resource.block_num, obj->resource.channel_num); + cy_en_trigmux_status_t trig_status = Cy_TrigMux_SwTrigger(trigline, CY_TRIGGER_TWO_CYCLES); + + /* Also return warning if SW trigger is already initated but DMA hardware + * has not seen it yet */ + if(trig_status == CY_TRIGMUX_INVALID_STATE) + return CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED; + else + return CY_RSLT_SUCCESS; +} + +void cyhal_dma_enable_event_dw(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable) +{ + if(enable) + obj->irq_cause |= event; + else + obj->irq_cause &= ~event; + + NVIC_SetPriority(cyhal_dma_get_dw_irqn(obj), intrPriority); +} + +bool cyhal_dma_is_busy_dw(cyhal_dma_t *obj) +{ +#if CY_IP_M4CPUSS_DMA_VERSION == 1 + /* In DW_V1 the pending channel information is stored in the PENDING + * register of the DW block and is a bit field of all pending or active + * channels */ + return cyhal_dma_get_dw_base(obj->resource.block_num)->PENDING & (1 << obj->resource.channel_num); +#elif CY_IP_M4CPUSS_DMA_VERSION == 2 + /* In DW_V2 the pending channel information is stored in the STATUS + * register of the channel itself */ + return DW_CH_STATUS(cyhal_dma_get_dw_base(obj->resource.block_num), obj->resource.channel_num) & (1UL << DW_CH_STRUCT_V2_CH_STATUS_PENDING_Pos); +#else + // Should never reach here. Just silencing compiler warnings. + CY_ASSERT(false); + return false; +#endif +} + +#endif /* CY_IP_M4CPUSS_DMA */ + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_ezi2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_ezi2c.c new file mode 100644 index 0000000000..278e5e5b0d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_ezi2c.c @@ -0,0 +1,289 @@ +/******************************************************************************* +* File Name: cyhal_ezi2c.c +* +* Description: +* Provides a high level interface for interacting with the Cypress I2C. This is +* a wrapper around the lower level PDL API. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cyhal_ezi2c.h" +#include "cyhal_scb_common.h" +#include "cyhal_gpio.h" +#include "cyhal_interconnect.h" +#include "cyhal_system_impl.h" +#include "cyhal_hwmgr.h" + +#ifdef CY_IP_MXSCB + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/* Peripheral clock values for different EZI2C speeds according PDL API Reference Guide */ +#define SCB_PERI_CLOCK_SLAVE_STD 8000000 +#define SCB_PERI_CLOCK_SLAVE_FST 12500000 +#define SCB_PERI_CLOCK_SLAVE_FSTP 50000000 +#define SCB_PERI_CLOCK_MASTER_STD 2000000 +#define SCB_PERI_CLOCK_MASTER_FST 8500000 +#define SCB_PERI_CLOCK_MASTER_FSTP 20000000 + +/* Implement ISR for EZI2C */ +static void cyhal_ezi2c_irq_handler(void) +{ + cyhal_ezi2c_t *obj = (cyhal_ezi2c_t*) cyhal_scb_get_irq_obj(); + Cy_SCB_EZI2C_Interrupt(obj->base, &(obj->context)); + + /* Call if registered callback here */ + cyhal_ezi2c_event_callback_t callback = (cyhal_ezi2c_event_callback_t) obj->callback_data.callback; + if (callback != NULL) + { + callback(obj->callback_data.callback_arg, CYHAL_EZI2C_EVENT_NONE); + } +} + +static uint32_t cyhal_set_peri_divider(cyhal_ezi2c_t *obj, uint32_t freq) +{ + /* Return the actual data rate on success, 0 otherwise */ + uint32_t peri_freq = 0; + if (freq == 0) + { + return 0; + } + if (freq <= CY_SCB_I2C_STD_DATA_RATE) + { + peri_freq = SCB_PERI_CLOCK_SLAVE_STD; + } + else if (freq <= CY_SCB_I2C_FST_DATA_RATE) + { + peri_freq = SCB_PERI_CLOCK_SLAVE_FST; + } + else if (freq <= CY_SCB_I2C_FSTP_DATA_RATE) + { + peri_freq = SCB_PERI_CLOCK_SLAVE_FSTP; + } + else + { + return 0; + } + + /* Connect assigned divider to be a clock source for EZI2C */ + cy_en_sysclk_status_t status = Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)((uint8_t)PCLK_SCB0_CLOCK + obj->resource.block_num), obj->clock.div_type, obj->clock.div_num); + if (status == CY_SYSCLK_SUCCESS) + status = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); + if (status == CY_SYSCLK_SUCCESS) + status = Cy_SysClk_PeriphSetDivider (obj->clock.div_type, obj->clock.div_num, cyhal_divider_value(peri_freq, 0u)); + if (status == CY_SYSCLK_SUCCESS) + status = Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num); + CY_ASSERT(CY_SYSCLK_SUCCESS == status); + + return Cy_SCB_I2C_SetDataRate(obj->base, freq, Cy_SysClk_PeriphGetFrequency(obj->clock.div_type, obj->clock.div_num)); +} + +cy_rslt_t cyhal_ezi2c_init(cyhal_ezi2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, const cyhal_clock_divider_t *clk, const cyhal_ezi2c_cfg_t *cfg) +{ + /* Validate input configuration structure */ + if ((0 == cfg->slave1_cfg.slave_address) || ((cfg->two_addresses) && (0 == cfg->slave2_cfg.slave_address))) + { + return CYHAL_EZI2C_RSLT_ERR_CHECK_USER_CONFIG; + } + + CY_ASSERT(NULL != obj); + + /* Populate configuration structure */ + const cy_stc_scb_ezi2c_config_t ezI2cConfig = + { + .numberOfAddresses = cfg->two_addresses ? CY_SCB_EZI2C_TWO_ADDRESSES : CY_SCB_EZI2C_ONE_ADDRESS, + .slaveAddress1 = cfg->slave1_cfg.slave_address, + .slaveAddress2 = cfg->slave2_cfg.slave_address, + .subAddressSize = (cy_en_scb_ezi2c_sub_addr_size_t)cfg->sub_address_size, + .enableWakeFromSleep = cfg->enable_wake_from_sleep, + }; + + /* Explicitly marked not allocated resources as invalid to prevent freeing them. */ + obj->resource.type = CYHAL_RSC_INVALID; + obj->pin_scl = CYHAL_NC_PIN_VALUE; + obj->pin_sda = CYHAL_NC_PIN_VALUE; + obj->is_shared_clock = true; + + cy_rslt_t result; + + /* Reserve the I2C */ + const cyhal_resource_pin_mapping_t *sda_map = CY_UTILS_GET_RESOURCE(sda, cyhal_pin_map_scb_i2c_sda); + const cyhal_resource_pin_mapping_t *scl_map = CY_UTILS_GET_RESOURCE(scl, cyhal_pin_map_scb_i2c_scl); + if ((NULL == sda_map) || (NULL == scl_map) || (sda_map->inst->block_num != scl_map->inst->block_num)) + { + return CYHAL_EZI2C_RSLT_ERR_INVALID_PIN; + } + + result = cyhal_hwmgr_reserve(scl_map->inst); + + /* Reserve the SDA pin */ + if (result == CY_RSLT_SUCCESS) + { + cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(sda); + result = cyhal_hwmgr_reserve(&pin_rsc); + if (result == CY_RSLT_SUCCESS) + { + obj->pin_sda = sda; + /* Configures the HSIOM connection to the pin */ + Cy_GPIO_SetHSIOM(CYHAL_GET_PORTADDR(sda), CYHAL_GET_PIN(sda), CY_GPIO_CFG_GET_HSIOM(scl_map->cfg)); + /* Configures the pin output buffer drive mode and input buffer enable */ + Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(sda), CYHAL_GET_PIN(sda), CY_GPIO_DM_OD_DRIVESLOW); + } + } + + /* Reserve the SCL pin */ + if (result == CY_RSLT_SUCCESS) + { + cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(scl); + /* Connect SCB I2C function to pins */ + cy_rslt_t result = cyhal_hwmgr_reserve(&pin_rsc); + if (result == CY_RSLT_SUCCESS) + { + obj->pin_scl = scl; + /* Configures the HSIOM connection to the pin */ + Cy_GPIO_SetHSIOM(CYHAL_GET_PORTADDR(scl), CYHAL_GET_PIN(scl), CY_GPIO_CFG_GET_HSIOM(scl_map->cfg)); + /* Configures the pin output buffer drive mode and input buffer enable */ + Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(scl), CYHAL_GET_PIN(scl), CY_GPIO_DM_OD_DRIVESLOW); + } + } + + if (result == CY_RSLT_SUCCESS) + { + obj->is_shared_clock = (clk != NULL); + if (clk == NULL) + { + result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false); + } + else + { + obj->clock = *clk; + } + } + + obj->resource = *(scl_map->inst); + obj->base = CYHAL_SCB_BASE_ADDRESSES[obj->resource.block_num]; + + if (result == CY_RSLT_SUCCESS) + { + /* Configure I2C to operate */ + result = Cy_SCB_EZI2C_Init(obj->base, &ezI2cConfig, &(obj->context)); + } + + int32_t ezi2c_freq; + switch(cfg->data_rate) + { + case CYHAL_EZI2C_DATA_RATE_100KHZ: + ezi2c_freq = 100000; + break; + case CYHAL_EZI2C_DATA_RATE_400KHZ: + ezi2c_freq = 400000; + break; + case CYHAL_EZI2C_DATA_RATE_1MHZ: + ezi2c_freq = 1000000; + break; + default: + return CYHAL_EZI2C_RSLT_ERR_CHECK_USER_CONFIG; + } + + /* Set data rate */ + int32_t dataRate = cyhal_set_peri_divider(obj, ezi2c_freq); + if (dataRate == 0) + { + /* Can not reach desired data rate */ + return CYHAL_EZI2C_RSLT_ERR_CAN_NOT_REACH_DR; + } + + if (result == CY_RSLT_SUCCESS) + { + /* Configure buffer for communication with master */ + Cy_SCB_EZI2C_SetBuffer1(obj->base, cfg->slave1_cfg.buf, cfg->slave1_cfg.buf_size, cfg->slave1_cfg.buf_rw_boundary, &(obj->context)); + /* Check if user set one or two addresses */ + if(cfg->two_addresses) + { + Cy_SCB_EZI2C_SetBuffer2(obj->base, cfg->slave2_cfg.buf, cfg->slave2_cfg.buf_size, cfg->slave2_cfg.buf_rw_boundary, &(obj->context)); + } + } + + if (result == CY_RSLT_SUCCESS) + { + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + obj->irq_cause = 0; + cyhal_scb_config_structs[obj->resource.block_num] = obj; + + cy_stc_sysint_t irqCfg = { CYHAL_SCB_IRQ_N[obj->resource.block_num], CYHAL_ISR_PRIORITY_DEFAULT }; + Cy_SysInt_Init(&irqCfg, cyhal_ezi2c_irq_handler); + NVIC_EnableIRQ(CYHAL_SCB_IRQ_N[obj->resource.block_num]); + + /* Enable EZI2C to operate */ + (void)Cy_SCB_EZI2C_Enable(obj->base); + } + + if (result != CY_RSLT_SUCCESS) + { + cyhal_ezi2c_free(obj); + } + return result; +} + +void cyhal_ezi2c_free(cyhal_ezi2c_t *obj) +{ + CY_ASSERT(NULL != obj); + + if (CYHAL_RSC_INVALID != obj->resource.type) + { + IRQn_Type irqn = CYHAL_SCB_IRQ_N[obj->resource.block_num]; + NVIC_DisableIRQ(irqn); + + cyhal_hwmgr_free(&(obj->resource)); + obj->base = NULL; + obj->resource.type = CYHAL_RSC_INVALID; + } + + cyhal_utils_release_if_used(&(obj->pin_sda)); + cyhal_utils_release_if_used(&(obj->pin_scl)); + + if (!obj->is_shared_clock) + { + cyhal_hwmgr_free_clock(&(obj->clock)); + } +} + +cyhal_ezi2c_status_t cyhal_ezi2c_get_activity_status(cyhal_ezi2c_t *obj) +{ + return (cyhal_ezi2c_status_t)Cy_SCB_EZI2C_GetActivity(obj->base, &(obj->context)); +} + +void cyhal_ezi2c_register_callback(cyhal_ezi2c_t *obj, cyhal_ezi2c_event_callback_t callback, void *callback_arg) +{ + uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); + obj->callback_data.callback = (cy_israddress) callback; + obj->callback_data.callback_arg = callback_arg; + cyhal_system_critical_section_exit(savedIntrStatus); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_IP_MXSCB */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_flash.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_flash.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_flash.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_flash.c index 6b0feb80d9..d901e2e333 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_flash.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_flash.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_gpio.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_gpio.c similarity index 92% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_gpio.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_gpio.c index 0be8107e40..8faf937514 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_gpio.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_gpio.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -83,10 +83,15 @@ static uint32_t cyhal_gpio_convert_drive_mode(cyhal_gpio_drive_mode_t drive_mode uint32_t drvMode; switch (drive_mode) { + /* For DRIVE_NONE and DRIVE_ANALOG: Return immediately so drvMode is + * not modified after switch statement based on direction as direction + * does not make sense for input only drive modes */ case CYHAL_GPIO_DRIVE_NONE: - case CYHAL_GPIO_DRIVE_ANALOG: drvMode = CY_GPIO_DM_HIGHZ; - break; + return drvMode; + case CYHAL_GPIO_DRIVE_ANALOG: + drvMode = CY_GPIO_DM_ANALOG; + return drvMode; case CYHAL_GPIO_DRIVE_PULLUP: drvMode = CY_GPIO_DM_PULLUP; break; @@ -155,6 +160,8 @@ void cyhal_gpio_free(cyhal_gpio_t pin) if (pin != CYHAL_NC_PIN_VALUE) { Cy_GPIO_SetInterruptMask(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), 0); + hal_gpio_callbacks[CYHAL_GET_PORT(pin)][CYHAL_GET_PIN(pin)] = NULL; + hal_gpio_callback_args[CYHAL_GET_PORT(pin)][CYHAL_GET_PIN(pin)] = NULL; Cy_GPIO_Pin_FastInit(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO); /* Do not attempt to free the resource we don't reserve in mbed. */ @@ -183,9 +190,10 @@ void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intrPriority, bool enable) { + Cy_GPIO_ClearInterrupt(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin)); Cy_GPIO_SetInterruptEdge(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (uint32_t)event); Cy_GPIO_SetInterruptMask(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (uint32_t)enable); - + /* Only enable if it's not already enabled */ IRQn_Type irqn = (IRQn_Type)(ioss_interrupts_gpio_0_IRQn + CYHAL_GET_PORT(pin)); if (NVIC_GetEnableIRQ(irqn) == 0) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_hwmgr.c similarity index 95% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_hwmgr.c index 1d66606cba..b14629220e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_hwmgr.c @@ -8,7 +8,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -105,18 +105,22 @@ extern "C" #define CY_BLOCK_COUNT_DAC 0 #endif -#if defined(CY_IP_M4CPUSS_DMAC_INSTANCES) || defined(CY_IP_M4CPUSS_DMA_INSTANCES) - #ifndef CPUSS_DMAC_CH_NR - #define CPUSS_DMAC_CH_NR (0u) - #endif - - #define CY_BLOCK_COUNT_DMA 3 - #define CY_CHANNEL_COUNT_DMA (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR + CPUSS_DMAC_CH_NR) +#if defined(CY_IP_M4CPUSS_DMAC_INSTANCES) + #define CY_BLOCK_COUNT_DMA (CY_IP_M4CPUSS_DMAC_INSTANCES) + #define CY_CHANNEL_COUNT_DMA (CPUSS_DMAC_CH_NR) #else #define CY_BLOCK_COUNT_DMA 0 #define CY_CHANNEL_COUNT_DMA 0 #endif +#if defined(CY_IP_M4CPUSS_DMA_INSTANCES) + #define CY_BLOCK_COUNT_DW (CY_IP_M4CPUSS_DMA_INSTANCES) + #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR) +#else + #define CY_BLOCK_COUNT_DW 0 + #define CY_CHANNEL_COUNT_DW 0 +#endif + #ifdef IOSS_GPIO_GPIO_PORT_NR #define CY_BLOCK_COUNT_GPIO IOSS_GPIO_GPIO_PORT_NR #define CY_CHANNEL_COUNT_GPIO (8 * IOSS_GPIO_GPIO_PORT_NR) @@ -259,7 +263,9 @@ extern "C" #define CY_SIZE_DAC CY_BLOCK_COUNT_DAC #define CY_OFFSET_DMA (CY_OFFSET_DAC + CY_SIZE_DAC) #define CY_SIZE_DMA CY_CHANNEL_COUNT_DMA -#define CY_OFFSET_GPIO (CY_OFFSET_DMA + CY_SIZE_DMA) +#define CY_OFFSET_DW (CY_OFFSET_DMA + CY_SIZE_DMA) +#define CY_SIZE_DW CY_CHANNEL_COUNT_DW +#define CY_OFFSET_GPIO (CY_OFFSET_DW + CY_SIZE_DW) #define CY_SIZE_GPIO CY_CHANNEL_COUNT_GPIO #define CY_OFFSET_I2S (CY_OFFSET_GPIO + CY_SIZE_GPIO) #define CY_SIZE_I2S CY_BLOCK_COUNT_I2S @@ -306,10 +312,14 @@ static const uint8_t cyhal_block_offsets_clock[4] = }; static const uint8_t cyhal_block_offsets_dma[] = +{ + 0, +}; + +static const uint8_t cyhal_block_offsets_dw[] = { 0, CPUSS_DW0_CH_NR, - CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR, }; static const uint8_t cyhal_block_offsets_gpio[] = @@ -415,6 +425,7 @@ static const uint16_t cyhal_resource_offsets[] = CY_OFFSET_CRYPTO, CY_OFFSET_DAC, CY_OFFSET_DMA, + CY_OFFSET_DW, CY_OFFSET_GPIO, CY_OFFSET_I2S, CY_OFFSET_LCD, @@ -435,6 +446,7 @@ static const uint32_t cyhal_has_channels = (1 << CYHAL_RSC_CAN) | (1 << CYHAL_RSC_CLOCK) | (1 << CYHAL_RSC_DMA) | + (1 << CYHAL_RSC_DW) | (1 << CYHAL_RSC_GPIO) | (1 << CYHAL_RSC_TCPWM) ; @@ -449,6 +461,9 @@ static const uint32_t cyhal_has_channels = static inline void check_array_size() __attribute__ ((deprecated)); #if __ICCARM__ #pragma diag_suppress=Pe177 +#elif __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wunused-function" #endif static inline void check_array_size() { @@ -457,6 +472,8 @@ static inline void check_array_size() } #if __ICCARM__ #pragma diag_default=Pe177 +#elif __clang__ +#pragma clang diagnostic pop #endif /******************************************************************************* @@ -483,6 +500,8 @@ static inline const uint8_t* cyhal_get_block_offsets(cyhal_resource_t type) return cyhal_block_offsets_clock; case CYHAL_RSC_DMA: return cyhal_block_offsets_dma; + case CYHAL_RSC_DW: + return cyhal_block_offsets_dw; case CYHAL_RSC_GPIO: return cyhal_block_offsets_gpio; case CYHAL_RSC_TCPWM: @@ -504,6 +523,8 @@ static inline uint8_t cyhal_get_block_offset_length(cyhal_resource_t type) return sizeof(cyhal_block_offsets_clock)/sizeof(cyhal_block_offsets_clock[0]); case CYHAL_RSC_DMA: return sizeof(cyhal_block_offsets_dma)/sizeof(cyhal_block_offsets_dma[0]); + case CYHAL_RSC_DW: + return sizeof(cyhal_block_offsets_dw)/sizeof(cyhal_block_offsets_dw[0]); case CYHAL_RSC_GPIO: return sizeof(cyhal_block_offsets_gpio)/sizeof(cyhal_block_offsets_gpio[0]); case CYHAL_RSC_TCPWM: @@ -708,11 +729,6 @@ void cyhal_hwmgr_free_clock(cyhal_clock_divider_t* obj) cyhal_hwmgr_free(&res); } -cy_rslt_t cyhal_hwmgr_allocate_dma(cyhal_resource_inst_t* obj) -{ - return cyhal_hwmgr_allocate(CYHAL_RSC_DMA, obj); -} - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_i2c.c similarity index 95% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_i2c.c index 3d9d26e311..f5ae876193 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_i2c.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -134,10 +134,14 @@ static uint32_t cyhal_set_peri_divider(cyhal_i2c_t *obj, uint32_t freq, bool is_ { return 0; } - Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)((uint8_t)PCLK_SCB0_CLOCK + obj->resource.block_num), obj->clock.div_type, obj->clock.div_num); - Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); - Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, cyhal_divider_value(peri_freq, 0u)); - Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num); + cy_en_sysclk_status_t status = Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)((uint8_t)PCLK_SCB0_CLOCK + obj->resource.block_num), obj->clock.div_type, obj->clock.div_num); + if (status == CY_SYSCLK_SUCCESS) + status = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); + if (status == CY_SYSCLK_SUCCESS) + status = Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, cyhal_divider_value(peri_freq, 0u)); + if (status == CY_SYSCLK_SUCCESS) + status = Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num); + CY_ASSERT(CY_SYSCLK_SUCCESS == status); /* According to PDL API Reference Guide - Cy_SysClk_PeriphGetFrequency() use only for i2c master role */ if(!is_slave) @@ -148,7 +152,6 @@ static uint32_t cyhal_set_peri_divider(cyhal_i2c_t *obj, uint32_t freq, bool is_ { return Cy_SCB_I2C_GetDataRate(obj->base, Cy_SysClk_PeriphGetFrequency(obj->clock.div_type, obj->clock.div_num)); } - } /* Start API implementing */ @@ -268,16 +271,9 @@ void cyhal_i2c_free(cyhal_i2c_t *obj) obj->base = NULL; obj->resource.type = CYHAL_RSC_INVALID; } - if (CYHAL_NC_PIN_VALUE != obj->pin_sda) - { - cyhal_utils_disconnect_and_free(obj->pin_sda); - obj->pin_sda = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_scl) - { - cyhal_utils_disconnect_and_free(obj->pin_scl); - obj->pin_scl = CYHAL_NC_PIN_VALUE; - } + + cyhal_utils_release_if_used(&(obj->pin_sda)); + cyhal_utils_release_if_used(&(obj->pin_scl)); if (!obj->is_shared_clock) { @@ -417,7 +413,7 @@ cy_rslt_t cyhal_i2c_master_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_ } cy_rslt_t status = cyhal_i2c_master_write(obj, address, mem_addr_buf, mem_addr_size, timeout, false); - + if (status == CY_RSLT_SUCCESS) { while (size > 0) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_interconnect.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_interconnect.c similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_interconnect.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_interconnect.c index 27c569a02f..15800bc0f2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_interconnect.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_interconnect.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_lptimer.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_lptimer.c index 2c57d0fc8c..0884fe4612 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_lptimer.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -110,7 +110,7 @@ cy_rslt_t cyhal_lptimer_init(cyhal_lptimer_t *obj) obj->callback_data.callback_arg = NULL; cyhal_lptimer_config_structs[obj->resource.block_num] = obj; } - + if (CY_RSLT_SUCCESS == rslt) { IRQn_Type irqn = (IRQn_Type) (srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); @@ -167,7 +167,7 @@ cy_rslt_t cyhal_lptimer_set_delay(cyhal_lptimer_t *obj, uint32_t delay) * 16 bit C0/C1 are cascaded to generated a 32 bit counter. * Counter0 continues counting after reaching its match value * Interrupt is generated on Counter1 match. - * + * * Supposed T=C0=C1=0, and we need to trigger an interrupt at T=0x28000. * We set C0_match to 0x8000 and C1 match to 1. * At T = 0x8000, C0_value matches C0_match so C1 get incremented. C1/C0=0x18000. @@ -189,7 +189,7 @@ cy_rslt_t cyhal_lptimer_set_delay(cyhal_lptimer_t *obj, uint32_t delay) uint16_t c1_increment = (uint16_t)(delay >> 16); Cy_MCWDT_ClearInterrupt(obj->base, CY_MCWDT_CTR1); - + uint16_t c0_old_match = Cy_MCWDT_GetMatch(obj->base, CY_MCWDT_COUNTER0); uint32_t critical_section = cyhal_system_critical_section_enter(); @@ -244,7 +244,7 @@ void cyhal_lptimer_enable_event(cyhal_lptimer_t *obj, cyhal_lptimer_event_t even CY_ASSERT(event == CYHAL_LPTIMER_COMPARE_MATCH); Cy_MCWDT_ClearInterrupt(obj->base, CY_MCWDT_CTR1); Cy_MCWDT_SetInterruptMask(obj->base, enable ? CY_MCWDT_CTR1 : 0); - + IRQn_Type irqn = (IRQn_Type)(srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); NVIC_SetPriority(irqn, intrPriority); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_not_implemented.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_not_implemented.c similarity index 87% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_not_implemented.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_not_implemented.c index bedd38d6eb..ee1b7ceb14 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_not_implemented.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_not_implemented.c @@ -10,7 +10,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,6 +27,8 @@ *******************************************************************************/ #include "cyhal_interconnect.h" +#include "cyhal_triggers.h" +#include "cy_utils.h" #if defined(__cplusplus) extern "C" @@ -46,12 +48,13 @@ typedef enum } cyhal_trigger_src; /* Trigger type for each output ~100b */ +/* Note: Non-fake version implemented in cyhal_triggers */ typedef enum { DEST0, DEST1, MUX_IN1, -} cyhal_trigger_dest; +} cyhal_trigger_dest_fake; // Two fake muxes. // Mux0 @@ -62,7 +65,8 @@ typedef enum // Outputs: DEST1 /* Maps each cyhal_destination_t to a mux index ~100b */ -const uint8_t cyhal_dest_to_mux[] = +/* Note: Non-fake version implemented in cyhal_triggers */ +const uint8_t cyhal_dest_to_mux_fake[] = { 0, // DEST0 1, // DEST1 @@ -70,7 +74,8 @@ const uint8_t cyhal_dest_to_mux[] = }; /* Maps each cyhal_destination_t to a specific output in its mux ~100b */ -const uint8_t cyhal_mux_dest_index[] = +/* Note: Non-fake version implemented in cyhal_triggers */ +const uint8_t cyhal_mux_dest_index_fake[] = { 0, // DEST0 0, // DEST1 @@ -87,10 +92,10 @@ const cyhal_source_t* cyhal_mux_to_sources[] = { cyhal_mux0_sources, cyhal_mux1_ /* Mapping from cyhal_source_t to cyhal_destination_t for intra mux connections ~80b*/ const cyhal_dest_t cyhal_intra_trigger_source[] = { - CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC0 - CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC1, - CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC2, - MUX_IN1 // MUX_OUT0 + (cyhal_dest_t)CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC0 + (cyhal_dest_t)CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC1, + (cyhal_dest_t)CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC2, + (cyhal_dest_t)MUX_IN1 // MUX_OUT0 }; @@ -111,7 +116,7 @@ typedef enum #define ONE_TO_ONE_IDENT 0x80 /** Determines whether a mux is one-to-one */ #define IS_1TO1(muxId) (ONE_TO_ONE_IDENT == (muxId & ONE_TO_ONE_IDENT)) -#define WRITE_REGISTER(muxIdx, sourceId, destId) /* TODO */ +#define WRITE_REGISTER(muxIdx, sourceId, destId) /* Maps each cyhal_destination_t to a mux index */ //extern uint8_t cyhal_dest_to_mux[]; @@ -126,7 +131,8 @@ typedef enum bool cyhal_has_connection(uint8_t mux, uint8_t outputIdx) { - // TODO + CY_UNUSED_PARAMETER(mux); + CY_UNUSED_PARAMETER(outputIdx); return false; } @@ -138,8 +144,8 @@ bool cyhal_has_connection(uint8_t mux, uint8_t outputIdx) */ cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest) { - uint8_t muxIdx = cyhal_dest_to_mux[dest]; - uint8_t destId = dest - cyhal_mux_dest_index[dest]; + uint8_t muxIdx = cyhal_dest_to_mux_fake[dest]; + uint8_t destId = dest - cyhal_mux_dest_index_fake[dest]; uint8_t sourceCount = cyhal_source_count_per_mux[muxIdx]; if (cyhal_has_connection(muxIdx, destId)) @@ -166,8 +172,8 @@ cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest) if (CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION != intraDest) { // This destination can be driven by the output of another mux. - uint8_t upstreamMuxIdx = cyhal_dest_to_mux[intraDest]; - uint8_t intraDestId = intraDest - cyhal_mux_dest_index[intraDest]; + uint8_t upstreamMuxIdx = cyhal_dest_to_mux_fake[intraDest]; + uint8_t intraDestId = intraDest - cyhal_mux_dest_index_fake[intraDest]; uint8_t upstreamMuxSourceCount = cyhal_source_count_per_mux[upstreamMuxIdx]; cy_rslt_t result = CYHAL_CONNECT_RSLT_NO_CONNECTION; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_pwm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_pwm.c new file mode 100644 index 0000000000..880bf46486 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_pwm.c @@ -0,0 +1,340 @@ +/***************************************************************************//** +* \file cyhal_pwm.c +* +* \brief +* Provides a high level interface for interacting with the Cypress PWM. This is +* a wrapper around the lower level PDL API. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** + * \addtogroup group_hal_psoc6_pwm PWM (Pulse Width Modulator) + * \ingroup group_hal_psoc6 + * \{ + * \section section_psoc6_pwm_compl_pins Complementary PWM output + * The PWM HAL driver allows generation of a normal and an inverted output. PSoC 6 devices support complementary pin pairs to which the normal and + * inverted signals can be routed. To identify the complementary pin for a given pin, open the PSoC 6 device datasheet and navigate to the 'Multiple Alternate Functions' table. Each + * column represents an alternate function of the pin in the corresponding row. Find your pin and make a note of the tcpwm[X].line[Y]:Z. The + * complementary pin is found by looking up the pin against tcpwm[X].line_compl[Y]:Z from the same column. + * For example, the image below shows a pair of complementary pins (P0.0 and P0.1) identified by the tcpwm[0].line[0]:0 and tcpwm[0].line_compl[0]:0 mapping. + * These complementary pins can be supplied to \ref cyhal_pwm_init_adv using pin and compl_pin parameters in any order. + * \image html pwm_compl_pins.png "Complementary PWM pins" + * + * \} group_hal_psoc6_pwm + */ + +#include +#include "cyhal_pwm_impl.h" +#include "cyhal_gpio.h" +#include "cyhal_hwmgr.h" +#include "cyhal_interconnect.h" +#include "cyhal_utils.h" + +#ifdef CY_IP_MXTCPWM + +#if defined(__cplusplus) +extern "C" { +#endif + +#define TCPWM_MAX_WIDTH 32 +#define MAX_DEAD_TIME_CYCLES 255 +static const uint32_t US_PER_SEC = 1000000u; + +/** The configuration of PWM output signal for Center and Asymmetric alignment with overflow and underflow swapped */ +#define CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM_UO_SWAPPED (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_INVERT) | \ + _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_CLEAR) | \ + _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_SET)) + +static const cyhal_resource_pin_mapping_t* try_alloc_pwm(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pin_map, size_t count) +{ + for (uint32_t i = 0; i < count; i++) + { + if (pin == pin_map[i].pin) + { + if (CY_RSLT_SUCCESS == cyhal_hwmgr_reserve(pin_map[i].inst)) + { + return &pin_map[i]; + } + } + } + return NULL; +} + +static cy_rslt_t convert_alignment(cyhal_pwm_alignment_t hal_alignment, uint32_t *pdl_alignment, bool swapped) +{ + switch (hal_alignment) + { + case CYHAL_PWM_LEFT_ALIGN: + *pdl_alignment = (swapped) ? CY_TCPWM_PWM_RIGHT_ALIGN : CY_TCPWM_PWM_LEFT_ALIGN; + return CY_RSLT_SUCCESS; + case CYHAL_PWM_RIGHT_ALIGN: + *pdl_alignment = (swapped) ? CY_TCPWM_PWM_LEFT_ALIGN : CY_TCPWM_PWM_RIGHT_ALIGN; + return CY_RSLT_SUCCESS; + case CYHAL_PWM_CENTER_ALIGN: + *pdl_alignment = CY_TCPWM_PWM_CENTER_ALIGN; + return CY_RSLT_SUCCESS; + default: + return CYHAL_PWM_RSLT_BAD_ARGUMENT; + } +} + +cy_rslt_t cyhal_pwm_init_adv(cyhal_pwm_t *obj, cyhal_gpio_t pin, cyhal_gpio_t pin_compl, cyhal_pwm_alignment_t pwm_alignment, bool continuous, uint32_t dead_time_us, bool invert, const cyhal_clock_divider_t *clk) +{ + CY_ASSERT(NULL != obj); + + cy_rslt_t result = CY_RSLT_SUCCESS; + bool swapped = false; + + const cyhal_resource_pin_mapping_t* map = try_alloc_pwm(pin, cyhal_pin_map_tcpwm_line, sizeof(cyhal_pin_map_tcpwm_line) / sizeof(cyhal_resource_pin_mapping_t)); + if (map == NULL) + { + swapped = true; + map = try_alloc_pwm(pin, cyhal_pin_map_tcpwm_line_compl, sizeof(cyhal_pin_map_tcpwm_line_compl) / sizeof(cyhal_resource_pin_mapping_t)); + } + if (map == NULL) + { + return CYHAL_PWM_RSLT_BAD_ARGUMENT; + } + else + { + /* Explicitly marked not allocated resources as invalid to prevent freeing them. */ + obj->resource.type = CYHAL_RSC_INVALID; + obj->dedicated_clock = false; + obj->resource = *map->inst; + obj->base = CYHAL_TCPWM_DATA[obj->resource.block_num].base; + obj->pin = CYHAL_NC_PIN_VALUE; + obj->pin_compl = CYHAL_NC_PIN_VALUE; + + result = cyhal_utils_reserve_and_connect(pin, map); + if (CY_RSLT_SUCCESS == result) + { + obj->pin = pin; + } + } + + if (CY_RSLT_SUCCESS == result && NC != pin_compl) + { + const cyhal_resource_pin_mapping_t *map_compl = swapped + ? CY_UTILS_GET_RESOURCE(pin_compl, cyhal_pin_map_tcpwm_line) + : CY_UTILS_GET_RESOURCE(pin_compl, cyhal_pin_map_tcpwm_line_compl); + + if ((NULL == map_compl) || !cyhal_utils_resources_equal(map->inst, map_compl->inst)) + { + result = CYHAL_PWM_RSLT_BAD_ARGUMENT; + } + else + { + result = cyhal_utils_reserve_and_connect(pin_compl, map_compl); + if (CY_RSLT_SUCCESS == result) + { + obj->pin_compl = pin_compl; + } + } + } + + if (CY_RSLT_SUCCESS == result) + { + uint32_t source_hz = Cy_SysClk_ClkPeriGetFrequency(); + en_clk_dst_t pclk = (en_clk_dst_t)(CYHAL_TCPWM_DATA[obj->resource.block_num].clock_dst + obj->resource.channel_num); + if (NULL != clk) + { + obj->clock_hz = source_hz / (1 + Cy_SysClk_PeriphGetDivider(clk->div_type, clk->div_num)); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, clk->div_type, clk->div_num)) + { + result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT; + } + } + else + { + if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false))) + { + obj->dedicated_clock = true; + uint32_t div = (dead_time_us > 0) + ? (((uint64_t)source_hz * dead_time_us) / (US_PER_SEC * MAX_DEAD_TIME_CYCLES)) + 1 + : (uint32_t)(1 << (TCPWM_MAX_WIDTH - CYHAL_TCPWM_DATA[obj->resource.block_num].max_count)); + + if (0 == div || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num) || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num)) + { + result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT; + } + else + { + obj->clock_hz = source_hz / div; + } + } + } + } + + uint32_t pdl_alignment = CY_TCPWM_PWM_LEFT_ALIGN; + if (CY_RSLT_SUCCESS == result) + { + result = convert_alignment(pwm_alignment, &pdl_alignment, swapped); + } + + if (CY_RSLT_SUCCESS == result) + { + uint8_t dead_time = dead_time_us * obj->clock_hz / US_PER_SEC; + + cy_stc_tcpwm_pwm_config_t config = + { + .pwmMode = (dead_time == 0) ? CY_TCPWM_PWM_MODE_PWM : CY_TCPWM_PWM_MODE_DEADTIME, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = pdl_alignment, + .deadTimeClocks = dead_time, + .runMode = (continuous) ? CY_TCPWM_PWM_CONTINUOUS : CY_TCPWM_PWM_ONESHOT, + .period0 = 0UL, + .period1 = 0UL, + .enablePeriodSwap = false, + .compare0 = 0UL, + .compare1 = 0UL, + .enableCompareSwap = false, + .interruptSources = CY_TCPWM_INT_NONE, + .invertPWMOut = (invert) ? CY_TCPWM_PWM_INVERT_ENABLE : CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = (invert) ? CY_TCPWM_PWM_INVERT_ENABLE : CY_TCPWM_PWM_INVERT_DISABLE, + .killMode = CY_TCPWM_PWM_STOP_ON_KILL, + .swapInputMode = CY_TCPWM_INPUT_RISINGEDGE, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = CY_TCPWM_INPUT_RISINGEDGE, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = CY_TCPWM_INPUT_RISINGEDGE, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = CY_TCPWM_INPUT_RISINGEDGE, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = CY_TCPWM_INPUT_LEVEL, + .countInput = CY_TCPWM_INPUT_1 + }; + result = Cy_TCPWM_PWM_Init(obj->base, obj->resource.channel_num, &config); + if ((swapped) && (pwm_alignment == CYHAL_PWM_CENTER_ALIGN)) + { + TCPWM_CNT_TR_CTRL2(obj->base, obj->resource.channel_num) = CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM_UO_SWAPPED; + } + } + + if (CY_RSLT_SUCCESS == result) + { + cyhal_tcpwm_init_callback_data(&(obj->resource), &(obj->callback_data)); + Cy_TCPWM_PWM_Enable(obj->base, obj->resource.channel_num); + } + else + { + cyhal_pwm_free(obj); + } + + return result; +} + +void cyhal_pwm_free(cyhal_pwm_t *obj) +{ + CY_ASSERT(NULL != obj); + + IRQn_Type irqn = (IRQn_Type)(CYHAL_TCPWM_DATA[obj->resource.block_num].isr_offset + obj->resource.channel_num); + NVIC_DisableIRQ(irqn); + + cyhal_utils_release_if_used(&(obj->pin)); + cyhal_utils_release_if_used(&(obj->pin_compl)); + + if (NULL != obj->base) + { + Cy_TCPWM_PWM_Disable(obj->base, obj->resource.channel_num); + + cyhal_hwmgr_free(&(obj->resource)); + obj->base = NULL; + obj->resource.type = CYHAL_RSC_INVALID; + } + + if (obj->dedicated_clock) + { + cy_en_sysclk_status_t rslt = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); + CY_UNUSED_PARAMETER(rslt); /* CY_ASSERT only processes in DEBUG, ignores for others */ + CY_ASSERT(CY_SYSCLK_SUCCESS == rslt); + cyhal_hwmgr_free_clock(&(obj->clock)); + obj->dedicated_clock = false; + } +} + +static cy_rslt_t cyhal_pwm_set_period_and_compare(cyhal_pwm_t *obj, uint32_t period, uint32_t compare) +{ + if (period < 1 || period > (uint32_t)((1 << CYHAL_TCPWM_DATA[obj->resource.block_num].max_count)) - 1) + return CYHAL_PWM_RSLT_BAD_ARGUMENT; + if (compare > period) + compare = period; + + cyhal_gpio_t pin = obj->pin; + cyhal_gpio_t pin_compl = obj->pin_compl; + + Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, 0u); + Cy_TCPWM_PWM_SetPeriod0(obj->base, obj->resource.channel_num, period - 1u); + + bool swapped_pins = (CY_UTILS_GET_RESOURCE(pin, cyhal_pin_map_tcpwm_line_compl) != NULL) && (CY_UTILS_GET_RESOURCE(pin_compl, cyhal_pin_map_tcpwm_line) != NULL); + bool is_center_aligned = (TCPWM_CNT_TR_CTRL2(obj->base, obj->resource.channel_num) == CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM) || + (TCPWM_CNT_TR_CTRL2(obj->base, obj->resource.channel_num) == CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM_UO_SWAPPED); + + if ((swapped_pins) && (!is_center_aligned)) + { + Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, period - compare); + } + else + { + Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, compare); + } + + + return CY_RSLT_SUCCESS; +} + +cy_rslt_t cyhal_pwm_set_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us) +{ + CY_ASSERT(NULL != obj); + uint32_t period = (uint32_t)((uint64_t)period_us * obj->clock_hz / US_PER_SEC); + uint32_t width = (uint32_t)((uint64_t)pulse_width_us * obj->clock_hz / US_PER_SEC); + return cyhal_pwm_set_period_and_compare(obj, period, width); +} + +cy_rslt_t cyhal_pwm_set_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz) +{ + CY_ASSERT(NULL != obj); + if (duty_cycle < 0.0f || duty_cycle > 100.0f || frequencyhal_hz < 1) + return CYHAL_PWM_RSLT_BAD_ARGUMENT; + uint32_t period = obj->clock_hz / frequencyhal_hz; + uint32_t width = (uint32_t)(duty_cycle * 0.01f * period); + return cyhal_pwm_set_period_and_compare(obj, period, width); +} + +cy_rslt_t cyhal_pwm_start(cyhal_pwm_t *obj) +{ + CY_ASSERT(NULL != obj); + Cy_TCPWM_TriggerReloadOrIndex(obj->base, 1u << obj->resource.channel_num); + return CY_RSLT_SUCCESS; +} + +cy_rslt_t cyhal_pwm_stop(cyhal_pwm_t *obj) +{ + CY_ASSERT(NULL != obj); + Cy_TCPWM_TriggerStopOrKill(obj->base, 1u << obj->resource.channel_num); + return CY_RSLT_SUCCESS; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_IP_MXTCPWM */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_qspi.c similarity index 86% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_qspi.c index 5c4c852a6d..8673da20f1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_qspi.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -207,30 +207,6 @@ static cy_rslt_t make_pin_reservations(cyhal_qspi_t *obj) #endif -/* Free all QSPI pins */ -static void free_pin_connections(cyhal_qspi_t *obj) -{ - if (CYHAL_NC_PIN_VALUE != obj->pin_sclk) - { - cyhal_utils_disconnect_and_free(obj->pin_sclk); - obj->pin_sclk = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_ssel) - { - cyhal_utils_disconnect_and_free(obj->pin_ssel); - obj->pin_ssel = CYHAL_NC_PIN_VALUE; - } - - for (uint8_t i = 0; (i < MAX_DATA_PINS); i++) - { - if (CYHAL_NC_PIN_VALUE != obj->pin_ios[i]) - { - cyhal_utils_disconnect_and_free(obj->pin_ios[i]); - obj->pin_ios[i] = CYHAL_NC_PIN_VALUE; - } - } -} - /******************************************************************************* * (Internal) QSPI Config Related Functions *******************************************************************************/ @@ -292,45 +268,16 @@ static inline uint32_t get_size(cyhal_qspi_size_t hal_size) return ((uint32_t)hal_size >> 3); /* convert bits to bytes */ } -/* cyhal_qspi_bus_width_t to number of bus lines used */ -static uint8_t get_lines(cyhal_qspi_bus_width_t hal_width) -{ - uint8_t lines; - - switch (hal_width) - { - case CYHAL_QSPI_CFG_BUS_SINGLE: - lines = 1; - break; - case CYHAL_QSPI_CFG_BUS_DUAL: - lines = 2; - break; - case CYHAL_QSPI_CFG_BUS_QUAD: - lines = 4; - break; - case CYHAL_QSPI_CFG_BUS_OCTAL: - lines = 8; - break; - default: - lines = 0; - } - - return lines; -} - /* Sends QSPI command with certain set of data */ /* Address passed through 'command' is not used, instead the value in 'addr' is used. */ static cy_rslt_t qspi_command_transfer(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, - uint32_t addr, bool endOfTransfer, uint8_t *dummy_cycles) + uint32_t addr, bool endOfTransfer) { /* max address size is 4 bytes and max mode bits size is 4 bytes */ uint8_t cmd_param[8] = {0}; uint32_t start_pos = 0; uint32_t addr_size = 0; - uint32_t mode_size = 0; - uint8_t leftover_bits = 0; - uint8_t lines = 0; - uint8_t integrated_dummy_cycles = 0; + uint32_t mode_bits_size = 0; cy_en_smif_txfr_width_t bus_width = CY_SMIF_WIDTH_SINGLE; cy_stc_smif_mem_cmd_t cyhal_cmd_config; cy_rslt_t result = CY_RSLT_SUCCESS; @@ -361,67 +308,22 @@ static cy_rslt_t qspi_command_transfer(cyhal_qspi_t *obj, const cyhal_qspi_comma if (!command->address.disabled) { addr_size = get_size(command->address.size); - if (addr_size == 0) - { - result = CYHAL_QSPI_RSLT_ERR_SIZE; - } - else - { - uint32_to_byte_array(addr, cmd_param, start_pos, addr_size); - start_pos += addr_size; - bus_width = cyhal_cmd_config.addrWidth; - } + uint32_to_byte_array(addr, cmd_param, start_pos, addr_size); + start_pos += addr_size; + bus_width = cyhal_cmd_config.addrWidth; } if (!command->mode_bits.disabled) { - // Mode size must be a multiple of the number of bus lines used (i.e. a whole number of cycles) - lines = get_lines(command->mode_bits.bus_width); - if (lines == 0) - { - result = CYHAL_QSPI_RSLT_ERR_BUS_WIDTH; - } - else if (command->mode_bits.size % lines != 0) - { - result = CYHAL_QSPI_RSLT_ERR_ALT_SIZE_WIDTH_MISMATCH; - } - else - { - // Round mode size up to nearest byte - unused parts of byte act as dummy cycles - mode_size = get_size(command->mode_bits.size - 1) + 1; - - // Unused bits in most significant byte of mode - leftover_bits = (mode_size << 3) - command->mode_bits.size; - if (leftover_bits != 0) - { - // Account for dummy cycles that will be spent in the mode portion of the command - integrated_dummy_cycles = (8 - (command->mode_bits.size % 8)) / lines; - if (*dummy_cycles < integrated_dummy_cycles) - { - // Not enough dummy cycles to account for a short mode - result = CYHAL_QSPI_RSLT_ERR_ALT_SIZE_DUMMY_CYCLES_MISMATCH; - } - else - { - *dummy_cycles -= integrated_dummy_cycles; - } - - // Align mode value to the end of the most significant byte - cyhal_cmd_config.mode <<= leftover_bits; - } - - uint32_to_byte_array(cyhal_cmd_config.mode, cmd_param, start_pos, mode_size); - bus_width = cyhal_cmd_config.modeWidth; - } + mode_bits_size = get_size(command->mode_bits.size); + uint32_to_byte_array(cyhal_cmd_config.mode, cmd_param, start_pos, mode_bits_size); + bus_width = cyhal_cmd_config.modeWidth; } - if (CY_RSLT_SUCCESS == result) - { - uint32_t cmpltTxfr = ((endOfTransfer) ? 1UL : 0UL); - result = (cy_rslt_t)Cy_SMIF_TransmitCommand(obj->base, cyhal_cmd_config.command, - cyhal_cmd_config.cmdWidth, cmd_param, (addr_size + mode_size), - bus_width, obj->slave_select, cmpltTxfr, &obj->context); - } + uint32_t cmpltTxfr = ((endOfTransfer) ? 1UL : 0UL); + result = (cy_rslt_t)Cy_SMIF_TransmitCommand(obj->base, cyhal_cmd_config.command, + cyhal_cmd_config.cmdWidth, cmd_param, (addr_size + mode_bits_size), + bus_width, obj->slave_select, cmpltTxfr, &obj->context); } return result; } @@ -817,10 +719,10 @@ cy_rslt_t cyhal_qspi_init( } } - if (CY_RSLT_SUCCESS == result) - { - result = cyhal_qspi_set_frequency(obj, hz); - } + /* cyhal_qspi_set_frequency should be called here. + Changing clock frequency is not supported on this device. + */ + (void)hz; if (CY_RSLT_SUCCESS == result) { @@ -866,15 +768,20 @@ void cyhal_qspi_free(cyhal_qspi_t *obj) obj->resource.type = CYHAL_RSC_INVALID; } - free_pin_connections(obj); + cyhal_utils_release_if_used(&(obj->pin_sclk)); + cyhal_utils_release_if_used(&(obj->pin_ssel)); + for (uint8_t i = 0; (i < MAX_DATA_PINS); i++) + { + cyhal_utils_release_if_used(&(obj->pin_ios[i])); + } } cy_rslt_t cyhal_qspi_set_frequency(cyhal_qspi_t *obj, uint32_t hz) { - /* TODO after HAL clock management implemented JIRA: BSP-510 */ + /* Changing clock frequency is not supported on this device. */ (void) obj; (void) hz; - return CY_RSLT_SUCCESS; + return CYHAL_QSPI_RSLT_ERR_FREQUENCY; } /* no restriction on the value of length. This function splits the read into multiple chunked transfers. */ @@ -884,7 +791,6 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command uint32_t chunk = 0; size_t read_bytes = *length; uint32_t addr = command->address.value; - uint8_t dummy_cycles = command->dummy_count; /* SMIF can read only up to 65536 bytes in one go. Split the larger read into multiple chunks */ while (read_bytes > 0) @@ -898,11 +804,11 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command * to create a copy of the command object. Instead of copying the object, the address is * passed separately. */ - status = qspi_command_transfer(obj, command, addr, false, &dummy_cycles); + status = qspi_command_transfer(obj, command, addr, false); if (CY_RSLT_SUCCESS == status) { - if (dummy_cycles > 0u) + if (command->dummy_count > 0u) { status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count); } @@ -927,15 +833,13 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command cy_rslt_t cyhal_qspi_read_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, void *data, size_t *length) { - cy_rslt_t status = CY_RSLT_SUCCESS; - uint32_t addr = command->address.value; - uint8_t dummy_cycles = command->dummy_count; - status = qspi_command_transfer(obj, command, addr, false, &dummy_cycles); + cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false); + if (CY_RSLT_SUCCESS == status) { if (command->dummy_count > 0u) { - status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, dummy_cycles); + status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count); } if (CY_RSLT_SUCCESS == status) @@ -950,14 +854,13 @@ cy_rslt_t cyhal_qspi_read_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *c /* length can be up to 65536. */ cy_rslt_t cyhal_qspi_write(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, const void *data, size_t *length) { - uint8_t dummy_cycles = command->dummy_count; - cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false, &dummy_cycles); + cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false); if (CY_RSLT_SUCCESS == status) { if (command->dummy_count > 0u) { - status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, dummy_cycles); + status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count); } if ((CY_SMIF_SUCCESS == status) && (*length > 0)) @@ -973,14 +876,13 @@ cy_rslt_t cyhal_qspi_write(cyhal_qspi_t *obj, const cyhal_qspi_command_t *comman /* length can be up to 65536. */ cy_rslt_t cyhal_qspi_write_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, const void *data, size_t *length) { - uint8_t dummy_cycles = command->dummy_count; - cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false, &dummy_cycles); + cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false); if (CY_RSLT_SUCCESS == status) { if (command->dummy_count > 0u) { - status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, dummy_cycles); + status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count); } if ((CY_SMIF_SUCCESS == status) && (*length > 0)) @@ -1001,7 +903,7 @@ cy_rslt_t cyhal_qspi_transfer( if ((tx_data == NULL || tx_size == 0) && (rx_data == NULL || rx_size == 0)) { /* only command, no rx or tx */ - status = qspi_command_transfer(obj, command, command->address.value, true, NULL); + status = qspi_command_transfer(obj, command, command->address.value, true); } else { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_rtc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_rtc.c similarity index 57% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_rtc.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_rtc.c index c0042f70e2..28172f5efb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_rtc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_rtc.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,9 +26,29 @@ *******************************************************************************/ #include "cy_rtc.h" +#include "cy_utils.h" #include "cyhal_rtc.h" #include "cyhal_system.h" +/** +* \addtogroup group_hal_psoc6_rtc RTC (Real Time Clock) +* \ingroup group_hal_psoc6 +* \{ +* +* Internally the PSoC6 RTC only stores the year as a two digit BCD value +* (0-99); no century information is stored. On RTC initialization the HAL must, +* as a result, assume a default century. If cyhal_rtc_write has been called +* with a different century than the default, its value must be stored and that +* value must persist through deep sleep, hibernate, software resets, etc. PSoC6 +* hardware provides a number of BREG registers which exist in the BACKUP domain +* and will persist over these power modes and resets. The HAL uses the highest +* indexed BACKUP->BREG register to store the century for the RTC. +* +* Therefore do not use the highest indexed BACKUP->BREG register as it is +* reserved for internal HAL usage. +* \} group_hal_psoc6_wdt +*/ + #ifdef CY_IP_MXS40SRSS_RTC_INSTANCES #if defined(__cplusplus) @@ -42,28 +62,59 @@ extern "C" { #define CYHAL_RTC_INIT_CENTURY 2000 #define CYHAL_TM_YEAR_BASE 1900 +#define CYHAL_RTC_BREG (BACKUP->BREG[SRSS_BACKUP_NUM_BREG-1]) +#define CYHAL_RTC_BREG_CENTURY_Pos 0UL +#define CYHAL_RTC_BREG_CENTURY_Msk 0x0000FFFFUL +#define CYHAL_RTC_BREG_STATE_Pos 16UL +#define CYHAL_RTC_BREG_STATE_Msk 0xFFFF0000UL + /** Wrapper around the PDL Cy_RTC_DeepSleepCallback to adapt the function signature */ static cy_en_syspm_status_t cyhal_rtc_syspm_callback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode) { return Cy_RTC_DeepSleepCallback(params, mode); } +static cy_stc_rtc_dst_t *dst; static cy_stc_syspm_callback_params_t cyhal_rtc_pm_cb_params = {NULL, NULL}; static cy_stc_syspm_callback_t cyhal_rtc_pm_cb = { .callback = &cyhal_rtc_syspm_callback, .type = CY_SYSPM_DEEPSLEEP, .callbackParams = &cyhal_rtc_pm_cb_params, }; + static cyhal_rtc_event_callback_t cyhal_rtc_user_handler; static void *cyhal_rtc_handler_arg; -#define CYHAL_RTC_INITIAL_CENTURY 1900 -static uint16_t cyhal_rtc_century = CYHAL_RTC_INITIAL_CENTURY; -static uint8_t cyhal_rtc_initialized = CYHAL_RTC_STATE_UNINITIALIZED; + +/* Returns century portion of BREG register used to store century info */ +static inline uint16_t get_rtc_century() +{ + return _FLD2VAL(CYHAL_RTC_BREG_CENTURY, CYHAL_RTC_BREG); +} + +/* Sets century portion of BREG register used to store century info */ +static inline void set_rtc_century(uint16_t century) +{ + CYHAL_RTC_BREG &= CYHAL_RTC_BREG_STATE_Msk; + CYHAL_RTC_BREG |= _VAL2FLD(CYHAL_RTC_BREG_CENTURY, century); +} + +/* Returns state portion of BREG register used to store century info */ +static inline uint16_t get_rtc_state() +{ + return _FLD2VAL(CYHAL_RTC_BREG_STATE, CYHAL_RTC_BREG); +} + +/* Sets state portion of BREG register used to store century info */ +static inline void set_rtc_state(uint16_t init) +{ + CYHAL_RTC_BREG &= CYHAL_RTC_BREG_CENTURY_Msk; + CYHAL_RTC_BREG |= _VAL2FLD(CYHAL_RTC_BREG_STATE, init); +} /** Wrapper around the PDL RTC interrupt handler to adapt the function signature */ static void cyhal_rtc_internal_handler(void) { - Cy_RTC_Interrupt(NULL, false); + Cy_RTC_Interrupt(dst, NULL != dst); } void Cy_RTC_Alarm1Interrupt(void) @@ -76,63 +127,84 @@ void Cy_RTC_Alarm1Interrupt(void) void Cy_RTC_CenturyInterrupt(void) { - cyhal_rtc_century += 100; + set_rtc_century(get_rtc_century() + 100); } cy_rslt_t cyhal_rtc_init(cyhal_rtc_t *obj) { CY_ASSERT(NULL != obj); cy_rslt_t rslt = CY_RSLT_SUCCESS; - if (cyhal_rtc_initialized == CYHAL_RTC_STATE_UNINITIALIZED) + if (get_rtc_state() == CYHAL_RTC_STATE_UNINITIALIZED) { if (Cy_RTC_IsExternalResetOccurred()) { // Reset to default time static const cy_stc_rtc_config_t defaultTime = { - .dayOfWeek = CY_RTC_THURSDAY, + .dayOfWeek = CY_RTC_SATURDAY, .date = 1, .month = 1, - .year = 70 + .year = 0, }; Cy_RTC_SetDateAndTime(&defaultTime); + set_rtc_century(CYHAL_RTC_INIT_CENTURY); + } + + if (Cy_SysPm_RegisterCallback(&cyhal_rtc_pm_cb)) + { + set_rtc_state(CYHAL_RTC_STATE_ENABLED); } else { - // Time is already set (possibly after sw reset). Assume century. - cyhal_rtc_century = CYHAL_RTC_INIT_CENTURY; + rslt = CY_RSLT_RTC_NOT_INITIALIZED; } - Cy_RTC_ClearInterrupt(CY_RTC_INTR_CENTURY); - Cy_RTC_SetInterruptMask(CY_RTC_INTR_CENTURY); - static const cy_stc_sysint_t irqCfg = {.intrSrc = srss_interrupt_backup_IRQn, .intrPriority = CYHAL_RTC_DEFAULT_PRIORITY}; - Cy_SysInt_Init(&irqCfg, &cyhal_rtc_internal_handler); - Cy_SysPm_RegisterCallback(&cyhal_rtc_pm_cb); - cyhal_rtc_initialized = CYHAL_RTC_STATE_ENABLED; } - NVIC_EnableIRQ(srss_interrupt_backup_IRQn); + else if(get_rtc_state() == CYHAL_RTC_STATE_ENABLED || get_rtc_state() == CYHAL_RTC_STATE_TIME_SET) + { + if(Cy_RTC_GetInterruptStatus() & CY_RTC_INTR_CENTURY) + Cy_RTC_CenturyInterrupt(); + } + + Cy_RTC_ClearInterrupt(CY_RTC_INTR_CENTURY); + Cy_RTC_SetInterruptMask(CY_RTC_INTR_CENTURY); + static const cy_stc_sysint_t irqCfg = {.intrSrc = srss_interrupt_backup_IRQn, .intrPriority = CYHAL_RTC_DEFAULT_PRIORITY}; + Cy_SysInt_Init(&irqCfg, &cyhal_rtc_internal_handler); + + if (rslt == CY_RSLT_SUCCESS) + { + dst = NULL; + NVIC_EnableIRQ(srss_interrupt_backup_IRQn); + } + return rslt; } void cyhal_rtc_free(cyhal_rtc_t *obj) { + CY_ASSERT(NULL != obj); NVIC_DisableIRQ(srss_interrupt_backup_IRQn); Cy_RTC_SetInterruptMask(CY_RTC_INTR_CENTURY); + dst = NULL; } bool cyhal_rtc_is_enabled(cyhal_rtc_t *obj) { - return (cyhal_rtc_initialized == CYHAL_RTC_STATE_TIME_SET); + CY_ASSERT(NULL != obj); + return (get_rtc_state() == CYHAL_RTC_STATE_TIME_SET); } cy_rslt_t cyhal_rtc_read(cyhal_rtc_t *obj, struct tm *time) { + CY_ASSERT(NULL != obj); // The number of days that precede each month of the year, not including Feb 29 static const uint16_t CUMULATIVE_DAYS[] = {0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334}; + cy_stc_rtc_config_t dateTime; uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); Cy_RTC_GetDateAndTime(&dateTime); - int year = dateTime.year + cyhal_rtc_century; + int year = dateTime.year + get_rtc_century(); cyhal_system_critical_section_exit(savedIntrStatus); + time->tm_sec = dateTime.sec; time->tm_min = dateTime.min; time->tm_hour = dateTime.hour; @@ -143,11 +215,13 @@ cy_rslt_t cyhal_rtc_read(cyhal_rtc_t *obj, struct tm *time) time->tm_yday = CUMULATIVE_DAYS[time->tm_mon] + dateTime.date - 1u + ((dateTime.month >= 3 && Cy_RTC_IsLeapYear(year)) ? 1u : 0u); time->tm_isdst = -1; + return CY_RSLT_SUCCESS; } cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time) { + CY_ASSERT(NULL != obj); uint32_t year2digit = time->tm_year % 100; cy_stc_rtc_config_t newtime = { .sec = time->tm_sec, @@ -159,6 +233,7 @@ cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time) .month = time->tm_mon + 1, .year = year2digit }; + cy_rslt_t rslt; uint32_t retry = 0; static const uint32_t MAX_RETRY = 10, RETRY_DELAY_MS = 1; @@ -168,19 +243,58 @@ cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time) uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); rslt = (cy_rslt_t)Cy_RTC_SetDateAndTime(&newtime); if (rslt == CY_RSLT_SUCCESS) - cyhal_rtc_century = time->tm_year - year2digit + CYHAL_TM_YEAR_BASE; + set_rtc_century(time->tm_year - year2digit + CYHAL_TM_YEAR_BASE); cyhal_system_critical_section_exit(savedIntrStatus); ++retry; } while (rslt == CY_RTC_INVALID_STATE && retry < MAX_RETRY); + while (CY_RTC_BUSY == Cy_RTC_GetSyncStatus()) { } + if (rslt == CY_RSLT_SUCCESS) - cyhal_rtc_initialized = CYHAL_RTC_STATE_TIME_SET; + set_rtc_state(CYHAL_RTC_STATE_TIME_SET); return rslt; } +static void initialize_dst(const cyhal_rtc_dst_t *hal, cy_stc_rtc_dst_format_t *pdl) +{ + pdl->format = (hal->format == CYHAL_RTC_DST_FIXED) ? CY_RTC_DST_FIXED : CY_RTC_DST_RELATIVE; + pdl->hour = hal->hour; + pdl->dayOfMonth = (hal->format == CYHAL_RTC_DST_FIXED) ? hal->dayOfMonth : 1; + pdl->weekOfMonth = (hal->format == CYHAL_RTC_DST_FIXED) ? 1 : hal->weekOfMonth + 1; + pdl->dayOfWeek = (hal->format == CYHAL_RTC_DST_FIXED) ? 1 : hal->dayOfWeek + 1; + pdl->month = hal->month; +} + +cy_rslt_t cyhal_rtc_set_dst(cyhal_rtc_t *obj, const cyhal_rtc_dst_t *start, const cyhal_rtc_dst_t *stop) +{ + CY_ASSERT(NULL != obj); + CY_ASSERT(NULL != start); + CY_ASSERT(NULL != stop); + + initialize_dst(start, &(obj->dst.startDst)); + initialize_dst(stop, &(obj->dst.stopDst)); + + cy_stc_rtc_config_t dateTime; + Cy_RTC_GetDateAndTime(&dateTime); + cy_rslt_t rslt = Cy_RTC_EnableDstTime(&(obj->dst), &dateTime); + if (rslt == CY_RSLT_SUCCESS) + dst = &(obj->dst); + return rslt; +} + +bool cyhal_rtc_is_dst(cyhal_rtc_t *obj) +{ + CY_ASSERT(NULL != obj); + + cy_stc_rtc_config_t dateTime; + Cy_RTC_GetDateAndTime(&dateTime); + return Cy_RTC_GetDstStatus(&(obj->dst), &dateTime); +} + cy_rslt_t cyhal_rtc_set_alarm(cyhal_rtc_t *obj, const struct tm *time, cyhal_alarm_active_t active) { // Note: the hardware does not support year matching + CY_ASSERT(NULL != obj); cy_stc_rtc_alarm_t alarm = { .sec = time->tm_sec, .secEn = active.en_sec ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE, @@ -201,16 +315,20 @@ cy_rslt_t cyhal_rtc_set_alarm(cyhal_rtc_t *obj, const struct tm *time, cyhal_ala void cyhal_rtc_register_callback(cyhal_rtc_t *obj, cyhal_rtc_event_callback_t callback, void *callback_arg) { + CY_ASSERT(NULL != obj); uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); cyhal_rtc_handler_arg = callback_arg; cyhal_rtc_user_handler = callback; cyhal_system_critical_section_exit(savedIntrStatus); } -void cyhal_rtc_enable_event(cyhal_rtc_t *obj, cyhal_rtc_event_t event, uint8_t intrPriority, bool enable) +void cyhal_rtc_enable_event(cyhal_rtc_t *obj, cyhal_rtc_event_t event, uint8_t intr_priority, bool enable) { + CY_ASSERT(NULL != obj); + CY_ASSERT(CYHAL_RTC_ALARM == event); Cy_RTC_ClearInterrupt(CY_RTC_INTR_ALARM1 | CY_RTC_INTR_ALARM2); Cy_RTC_SetInterruptMask((enable ? CY_RTC_INTR_ALARM1 : 0) | CY_RTC_INTR_CENTURY); + NVIC_SetPriority(srss_interrupt_backup_IRQn, intr_priority); } #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_scb_common.c similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_scb_common.c index 2b640f5e65..ee2e994c4a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_scb_common.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_sdhc.c similarity index 92% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_sdhc.c index da2f6108f3..2671b13d2a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_sdhc.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,6 +26,7 @@ #include /* For memcpy */ #include #include "cy_pdl.h" +#include "cy_utils.h" #include "cy_result.h" #include "cyhal_sdhc.h" #include "cyhal_sdio.h" @@ -71,12 +72,9 @@ extern "C" #define BIT_MASK( x ) (( 1 << x ) - 1 ) -#define SDIO_PINS_NC ((cyhal_gpio_t) CYHAL_NC_PIN_VALUE) - /* Macro-function to calculate pin mapping number */ #define COUNT(pin_mapping) (sizeof(pin_mapping)/sizeof(cyhal_resource_pin_mapping_t)) - #if (defined(SDHC_CHIP_TOP_DATA8_PRESENT) && (SDHC_CHIP_TOP_DATA8_PRESENT)) || \ (defined(SDHC0_CHIP_TOP_DATA8_PRESENT) && (SDHC0_CHIP_TOP_DATA8_PRESENT)) || \ (defined(SDHC1_CHIP_TOP_DATA8_PRESENT) && (SDHC1_CHIP_TOP_DATA8_PRESENT)) @@ -224,20 +222,11 @@ static const uint32_t eventMap[SDHC_EVENTS_NUM][SDHC_EVENTS_MAP_NUM] = { (uint32_t)CYHAL_SDHC_ERR_INTERRUPT, (uint32_t)CY_SD_HOST_ERR_INTERRUPT }, }; -static void release_pin_if_used(cyhal_gpio_t *pin) -{ - if (CYHAL_NC_PIN_VALUE != *pin) - { - cyhal_utils_disconnect_and_free(*pin); - *pin = CYHAL_NC_PIN_VALUE; - } -} - static cy_rslt_t setup_pin(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pinmap, size_t count, cyhal_gpio_t *objRef) { cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(pin); cy_rslt_t result = cyhal_hwmgr_reserve(&pin_rsc); - + if (result == CY_RSLT_SUCCESS) { const cyhal_resource_pin_mapping_t *map = cyhal_utils_get_resource(pin, pinmap, count); @@ -269,9 +258,9 @@ static cy_rslt_t setup_pin(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t static bool isTransferInProcess = false; /* Internal functions */ -static cy_en_sd_host_status_t Cy_SD_Host_PollTransferComplete(SDHC_Type *base, const uint16_t delay); -static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base); -static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency); +static cy_en_sd_host_status_t cyhal_sd_host_polltransfercomplete(SDHC_Type *base, const uint16_t delay); +static cy_en_sd_host_status_t cyhal_sd_host_pollcmdcomplete(SDHC_Type *base); +static cy_en_sd_host_status_t cyhal_sd_host_sdcardchangeclock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency); static cy_en_sd_host_bus_width_t convert_buswidth(uint8_t stopbits); static cy_en_syspm_status_t cyhal_sdio_syspm_callback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode); @@ -363,7 +352,7 @@ static cy_en_sd_host_bus_width_t convert_buswidth(uint8_t stopbits) /******************************************************************************* -* Function Name: Cy_SD_Host_SdCardChangeClock +* Function Name: cyhal_sd_host_sdcardchangeclock ****************************************************************************//** * * Changes the Host controller SD clock. @@ -380,19 +369,19 @@ static cy_en_sd_host_bus_width_t convert_buswidth(uint8_t stopbits) * \return \ref cy_en_sd_host_status_t * *******************************************************************************/ -static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency) +static cy_en_sd_host_status_t cyhal_sd_host_sdcardchangeclock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency) { cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_INVALID_PARAMETER; uint32_t clockInput = 0; - - cy_rslt_t get_frequency_result = + + cy_rslt_t get_frequency_result = cyhal_system_clock_get_frequency(CYHAL_SDHC_HF_CLOCKS[instance_num], &clockInput); if ((NULL != base) && (get_frequency_result == CY_RSLT_SUCCESS) && (0U != clockInput)) { /* Update SD Host clock divider */ uint16_t clkDiv = (uint16_t) ((clockInput / frequency) >> 1UL); - + Cy_SD_Host_DisableSdClk(base); ret = Cy_SD_Host_SetSdClkDiv(base, clkDiv); Cy_SD_Host_EnableSdClk(base); @@ -424,7 +413,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint /******************************************************************************* -* Function Name: Cy_SD_Host_PollCmdComplete +* Function Name: cyhal_sd_host_pollcmdcomplete ****************************************************************************//** * * Waits for the command complete event. @@ -435,7 +424,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint * \return \ref cy_en_sd_host_status_t * *******************************************************************************/ -static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base) +static cy_en_sd_host_status_t cyhal_sd_host_pollcmdcomplete(SDHC_Type *base) { cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_TIMEOUT; uint32_t retry = SDHC_RETRY_TIMES; @@ -461,7 +450,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base) /******************************************************************************* -* Function Name: Cy_SD_Host_PollTransferComplete +* Function Name: cyhal_sd_host_polltransfercomplete ****************************************************************************//** * * Waits for the command complete event. @@ -477,7 +466,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base) * If the pointer is NULL, returns error. * *******************************************************************************/ -static cy_en_sd_host_status_t Cy_SD_Host_PollTransferComplete(SDHC_Type *base, const uint16_t delay) +static cy_en_sd_host_status_t cyhal_sd_host_polltransfercomplete(SDHC_Type *base, const uint16_t delay) { cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_TIMEOUT; uint32_t retry = SDHC_RW_RETRY_CYCLES; @@ -578,9 +567,9 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, CY_ASSERT(NULL != obj); cy_rslt_t result = CY_RSLT_SUCCESS; - + obj->base = NULL; - + obj->pin_clk = CYHAL_NC_PIN_VALUE; obj->pin_cmd = CYHAL_NC_PIN_VALUE; obj->pin_data[0] = CYHAL_NC_PIN_VALUE; @@ -655,8 +644,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, if ((NC != cardDetect) && (CY_RSLT_SUCCESS == result)) { #if CARD_DETECT_PRESENT - result = setup_pin(cardDetect, cyhal_pin_map_sdhc_card_detect_n, - COUNT(cyhal_pin_map_sdhc_card_detect_n), &(obj->pin_cardDetect)); + result = setup_pin(cardDetect, cyhal_pin_map_sdhc_card_detect_n, + COUNT(cyhal_pin_map_sdhc_card_detect_n), &(obj->pin_cardDetect)); #else result = CYHAL_SDHC_RSLT_ERR_PIN; #endif @@ -665,8 +654,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, if ((NC != ioVoltSel) && (CY_RSLT_SUCCESS == result)) { #if IO_VOLT_SEL_PRESENT - result = setup_pin(ioVoltSel, cyhal_pin_map_sdhc_io_volt_sel, - COUNT(cyhal_pin_map_sdhc_io_volt_sel), &(obj->pin_ioVoltSel)); + result = setup_pin(ioVoltSel, cyhal_pin_map_sdhc_io_volt_sel, + COUNT(cyhal_pin_map_sdhc_io_volt_sel), &(obj->pin_ioVoltSel)); #else result = CYHAL_SDHC_RSLT_ERR_PIN; #endif @@ -675,8 +664,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, if ((NC != cardIfPwrEn) && (CY_RSLT_SUCCESS == result)) { #if CARD_IF_PWR_EN_PRESENT - result = setup_pin(cardIfPwrEn, cyhal_pin_map_sdhc_card_if_pwr_en, - COUNT(cyhal_pin_map_sdhc_card_if_pwr_en), &(obj->pin_cardIfPwrEn)); + result = setup_pin(cardIfPwrEn, cyhal_pin_map_sdhc_card_if_pwr_en, + COUNT(cyhal_pin_map_sdhc_card_if_pwr_en), &(obj->pin_cardIfPwrEn)); #else result = CYHAL_SDHC_RSLT_ERR_PIN; #endif @@ -685,8 +674,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, if ((NC != cardMechWriteProt) && (CY_RSLT_SUCCESS == result)) { #if CARD_WRITE_PROT_PRESENT - result = setup_pin(cardMechWriteProt, cyhal_pin_map_sdhc_card_mech_write_prot, - COUNT(cyhal_pin_map_sdhc_card_mech_write_prot), &(obj->pin_cardMechWriteProt)); + result = setup_pin(cardMechWriteProt, cyhal_pin_map_sdhc_card_mech_write_prot, + COUNT(cyhal_pin_map_sdhc_card_mech_write_prot), &(obj->pin_cardMechWriteProt)); #else result = CYHAL_SDHC_RSLT_ERR_PIN; #endif @@ -695,8 +684,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, if ((NC != ledCtrl) && (CY_RSLT_SUCCESS == result)) { #if LED_CTRL_PRESENT - result = setup_pin(ledCtrl, cyhal_pin_map_sdhc_led_ctrl, - COUNT(cyhal_pin_map_sdhc_led_ctrl), &(obj->pin_ledCtrl)); + result = setup_pin(ledCtrl, cyhal_pin_map_sdhc_led_ctrl, + COUNT(cyhal_pin_map_sdhc_led_ctrl), &(obj->pin_ledCtrl)); #else result = CYHAL_SDHC_RSLT_ERR_PIN; #endif @@ -705,8 +694,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, if ((NC != cardEmmcReset) && (CY_RSLT_SUCCESS == result)) { #if CARD_EMMC_RESET_PRESENT - result = setup_pin(cardEmmcReset, cyhal_pin_map_sdhc_card_emmc_reset_n, - COUNT(cyhal_pin_map_sdhc_card_emmc_reset_n), &(obj->pin_cardEmmcReset)); + result = setup_pin(cardEmmcReset, cyhal_pin_map_sdhc_card_emmc_reset_n, + COUNT(cyhal_pin_map_sdhc_card_emmc_reset_n), &(obj->pin_cardEmmcReset)); #else result = CYHAL_SDHC_RSLT_ERR_PIN; #endif @@ -755,7 +744,7 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, cy_stc_sysint_t irqCfg = { irqn, CYHAL_ISR_PRIORITY_DEFAULT }; Cy_SysInt_Init(&irqCfg, cyhal_sdhc_irq_handler); NVIC_EnableIRQ(irqn); - + result = (cy_rslt_t) Cy_SD_Host_Init(obj->base, &hostConfig, &obj->context); } @@ -776,11 +765,11 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, /* Initialize the card */ result = (cy_rslt_t)Cy_SD_Host_InitCard(obj->base, &stcSdcardCfg, &obj->context); - + if (result == CY_RSLT_SUCCESS) { /* Update SD Card frequency to be 25 Mhz */ - result = (cy_rslt_t) Cy_SD_Host_SdCardChangeClock(obj->base, obj->resource.block_num, CY_SD_HOST_CLK_25M); + result = (cy_rslt_t) cyhal_sd_host_sdcardchangeclock(obj->base, obj->resource.block_num, CY_SD_HOST_CLK_25M); } } } @@ -803,15 +792,15 @@ void cyhal_sdhc_free(cyhal_sdhc_t *obj) NVIC_DisableIRQ(irqn); Cy_SD_Host_DeInit(obj->base); - + cyhal_hwmgr_free(&(obj->resource)); obj->base = NULL; obj->resource.type = CYHAL_RSC_INVALID; } /* Free pins */ - release_pin_if_used(&obj->pin_cmd); - release_pin_if_used(&obj->pin_clk); + cyhal_utils_release_if_used(&(obj->pin_cmd)); + cyhal_utils_release_if_used(&(obj->pin_clk)); #if DATA8_PRESENT const uint8_t max_idx = 8; @@ -820,31 +809,31 @@ void cyhal_sdhc_free(cyhal_sdhc_t *obj) #endif for (uint8_t i = 0; i < max_idx; i++) { - release_pin_if_used(&obj->pin_data[i]); + cyhal_utils_release_if_used(&(obj->pin_data[i])); } #if CARD_DETECT_PRESENT - release_pin_if_used(&obj->pin_cardDetect); + cyhal_utils_release_if_used(&(obj->pin_cardDetect)); #endif #if IO_VOLT_SEL_PRESENT - release_pin_if_used(&obj->pin_ioVoltSel); + cyhal_utils_release_if_used(&(obj->pin_ioVoltSel)); #endif #if CARD_IF_PWR_EN_PRESENT - release_pin_if_used(&obj->pin_cardIfPwrEn); + cyhal_utils_release_if_used(&(obj->pin_cardIfPwrEn)); #endif #if CARD_WRITE_PROT_PRESENT - release_pin_if_used(&obj->pin_cardMechWriteProt); + cyhal_utils_release_if_used(&(obj->pin_cardMechWriteProt)); #endif #if LED_CTRL_PRESENT - release_pin_if_used(&obj->pin_ledCtrl); + cyhal_utils_release_if_used(&(obj->pin_ledCtrl)); #endif #if CARD_EMMC_RESET_PRESENT - release_pin_if_used(&obj->pin_cardEmmcReset); + cyhal_utils_release_if_used(&(obj->pin_cardEmmcReset)); #endif } @@ -879,14 +868,14 @@ cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *da } else { - driverRet = Cy_SD_Host_PollTransferComplete(obj->base, SDHC_RW_TIMEOUT_US); - + driverRet = cyhal_sd_host_polltransfercomplete(obj->base, SDHC_RW_TIMEOUT_US); + if (CY_SD_HOST_SUCCESS != driverRet) { ret = CY_RSLT_TYPE_ERROR; } } - + /* Restore interrupts after transition */ Cy_SD_Host_SetNormalInterruptMask(obj->base, regIntrSts); @@ -933,7 +922,7 @@ cy_rslt_t cyhal_sdhc_write(const cyhal_sdhc_t *obj, uint32_t address, const uint } else { - driverRet = Cy_SD_Host_PollTransferComplete(obj->base, SDHC_RW_TIMEOUT_US); + driverRet = cyhal_sd_host_polltransfercomplete(obj->base, SDHC_RW_TIMEOUT_US); if (CY_SD_HOST_SUCCESS != driverRet) { @@ -984,7 +973,7 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t l } else { - driverRet = Cy_SD_Host_PollCmdComplete(obj->base); + driverRet = cyhal_sd_host_pollcmdcomplete(obj->base); } if (CY_SD_HOST_SUCCESS != driverRet) @@ -1037,15 +1026,23 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t l cy_rslt_t cyhal_sdhc_read_async(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *data, size_t *length) { - cy_rslt_t ret = CY_RSLT_SUCCESS; - //TODO: implement + /* Not yet implemented for this device. */ + CY_UNUSED_PARAMETER(obj); + CY_UNUSED_PARAMETER(address); + CY_UNUSED_PARAMETER(data); + CY_UNUSED_PARAMETER(length); + cy_rslt_t ret = CYHAL_SDHC_RSLT_ERR_UNSUPPORTED; return ret; } cy_rslt_t cyhal_sdhc_write_async(const cyhal_sdhc_t *obj, uint32_t address, const uint8_t *data, size_t *length) { - cy_rslt_t ret = CY_RSLT_SUCCESS; - //TODO: implement + /* Not yet implemented for this device. */ + CY_UNUSED_PARAMETER(obj); + CY_UNUSED_PARAMETER(address); + CY_UNUSED_PARAMETER(data); + CY_UNUSED_PARAMETER(length); + cy_rslt_t ret = CYHAL_SDHC_RSLT_ERR_UNSUPPORTED; return ret; } @@ -1186,37 +1183,37 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, obj->pin_data2 = CYHAL_NC_PIN_VALUE; obj->pin_data3 = CYHAL_NC_PIN_VALUE; - result = setup_pin( - cmd, cyhal_pin_map_sdhc_card_cmd, COUNT(cyhal_pin_map_sdhc_card_cmd), &(obj->pin_cmd)); + result = setup_pin(cmd, cyhal_pin_map_sdhc_card_cmd, + COUNT(cyhal_pin_map_sdhc_card_cmd), &(obj->pin_cmd)); if (CY_RSLT_SUCCESS == result) { - result = setup_pin( - clk, cyhal_pin_map_sdhc_clk_card, COUNT(cyhal_pin_map_sdhc_clk_card), &(obj->pin_clk)); + result = setup_pin(clk, cyhal_pin_map_sdhc_clk_card, + COUNT(cyhal_pin_map_sdhc_clk_card), &(obj->pin_clk)); } if (CY_RSLT_SUCCESS == result) { - result = setup_pin( - data0, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data0)); + result = setup_pin(data0, cyhal_pin_map_sdhc_card_dat_3to0, + COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data0)); } - + if (CY_RSLT_SUCCESS == result) { - result = setup_pin( - data1, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data1)); + result = setup_pin(data1, cyhal_pin_map_sdhc_card_dat_3to0, + COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data1)); } - + if (CY_RSLT_SUCCESS == result) { - result = setup_pin( - data2, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data2)); + result = setup_pin(data2, cyhal_pin_map_sdhc_card_dat_3to0, + COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data2)); } - + if (CY_RSLT_SUCCESS == result) { - result = setup_pin( - data3, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data3)); + result = setup_pin(data3, cyhal_pin_map_sdhc_card_dat_3to0, + COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data3)); } if (result == CY_RSLT_SUCCESS) @@ -1228,7 +1225,7 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, if (result == CY_RSLT_SUCCESS) { obj->resource = sdhc; - + if (result == CY_RSLT_SUCCESS) { obj->base = CYHAL_SDHC_BASE_ADDRESSES[obj->resource.block_num]; @@ -1265,9 +1262,6 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, if (result == CY_RSLT_SUCCESS) { - /* Only enable the SDMA interrupt */ - Cy_SD_Host_SetNormalInterruptMask(obj->base, CY_SD_HOST_DMA_INTERRUPT); - /* Don't enable any error interrupts for now */ Cy_SD_Host_SetErrorInterruptMask(obj->base, 0UL); @@ -1290,7 +1284,7 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, (void)Cy_SD_Host_SetHostBusWidth(obj->base, CY_SD_HOST_BUS_WIDTH_4_BIT); /* Change the host SD clock to 400 kHz */ - (void) Cy_SD_Host_SdCardChangeClock(obj->base, obj->resource.block_num, SDIO_HOST_CLK_400K); + (void) cyhal_sd_host_sdcardchangeclock(obj->base, obj->resource.block_num, SDIO_HOST_CLK_400K); obj->frequencyhal_hz = SDIO_HOST_CLK_400K; obj->block_size = SDIO_64B_BLOCK; @@ -1327,27 +1321,26 @@ void cyhal_sdio_free(cyhal_sdio_t *obj) } /* Free pins */ - release_pin_if_used(&obj->pin_clk); - release_pin_if_used(&obj->pin_cmd); - release_pin_if_used(&obj->pin_data0); - release_pin_if_used(&obj->pin_data1); - release_pin_if_used(&obj->pin_data2); - release_pin_if_used(&obj->pin_data3); + cyhal_utils_release_if_used(&obj->pin_clk); + cyhal_utils_release_if_used(&obj->pin_cmd); + cyhal_utils_release_if_used(&obj->pin_data0); + cyhal_utils_release_if_used(&obj->pin_data1); + cyhal_utils_release_if_used(&obj->pin_data2); + cyhal_utils_release_if_used(&obj->pin_data3); } - cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config) { cy_en_sd_host_status_t result = CY_SD_HOST_ERROR_TIMEOUT; - if ((NULL == obj) && (config == NULL)) + if ((NULL == obj) || (config == NULL)) { return CYHAL_SDIO_RSLT_ERR_BAD_PARAM; } if (config->frequencyhal_hz != 0U) { - result = Cy_SD_Host_SdCardChangeClock(obj->base, obj->resource.block_num, config->frequencyhal_hz); + result = cyhal_sd_host_sdcardchangeclock(obj->base, obj->resource.block_num, config->frequencyhal_hz); obj->frequencyhal_hz = config->frequencyhal_hz; } @@ -1371,6 +1364,7 @@ cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, \ cyhal_sdio_command_t command, uint32_t argument, uint32_t* response) { + (void)direction; if (NULL == obj) { return CYHAL_SDIO_RSLT_ERR_BAD_PARAM; @@ -1423,7 +1417,7 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio if (CY_SD_HOST_SUCCESS == result) { - result = Cy_SD_Host_PollCmdComplete(obj->base); + result = cyhal_sd_host_pollcmdcomplete(obj->base); } } @@ -1480,7 +1474,7 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction *response = 0UL; } - while ((CY_SD_HOST_SUCCESS != result) && (retry-- > 0UL)) + while ((CY_SD_HOST_SUCCESS != result) && (retry > 0UL)) { /* Add SDIO Error Handling * SDIO write timeout is expected when doing first write to register @@ -1544,13 +1538,14 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction result = Cy_SD_Host_SendCommand(obj->base, &cmd); if ( CY_SD_HOST_SUCCESS == result ) { - result = Cy_SD_Host_PollCmdComplete(obj->base); + result = cyhal_sd_host_pollcmdcomplete(obj->base); if ( CY_SD_HOST_SUCCESS == result ) { - result = Cy_SD_Host_PollTransferComplete(obj->base, SDIO_RW_TIMEOUT_US); + result = cyhal_sd_host_polltransfercomplete(obj->base, SDIO_RW_TIMEOUT_US); } } + retry--; } if (response != NULL ) @@ -1621,7 +1616,7 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio dat.enReliableWrite = false; dat.enableDma = true; - while ((CY_SD_HOST_SUCCESS != result) && (retry-- > 0UL)) + while ((CY_SD_HOST_SUCCESS != result) && (retry > 0UL)) { /* Check if an error occurred on any previous transactions or reset after the first unsuccessful bulk transfer try */ if( (Cy_SD_Host_GetNormalInterruptStatus(obj->base) & CY_SD_HOST_ERR_INTERRUPT) || @@ -1671,6 +1666,7 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio (void)Cy_SD_Host_InitDataTransfer(obj->base, &dat); result = Cy_SD_Host_SendCommand(obj->base, &cmd); + retry--; } if (CY_SD_HOST_SUCCESS != result) @@ -1702,7 +1698,7 @@ bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj) if (!isCmdComplete) { - result = Cy_SD_Host_PollCmdComplete(obj->base); + result = cyhal_sd_host_pollcmdcomplete(obj->base); if (CY_SD_HOST_SUCCESS == result) { @@ -1712,7 +1708,7 @@ bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj) if (isCmdComplete) { - result = Cy_SD_Host_PollTransferComplete(obj->base, SDIO_RW_TIMEOUT_US); + result = cyhal_sd_host_polltransfercomplete(obj->base, SDIO_RW_TIMEOUT_US); if (CY_SD_HOST_SUCCESS == result) { @@ -1785,6 +1781,7 @@ void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, ui obj->irq_cause &= ~event; } + Cy_SD_Host_ClearNormalInterruptStatus(obj->base, interruptMask); Cy_SD_Host_SetNormalInterruptMask(obj->base, interruptMask); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_spi.c similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_spi.c index c11081404b..53e666e5ec 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_spi.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -203,6 +203,7 @@ cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, uint8_t bits, cyhal_spi_mode_t mode, bool is_slave) { CY_ASSERT(NULL != obj); + memset(obj, 0, sizeof(cyhal_spi_t)); cy_rslt_t result = CY_RSLT_SUCCESS; cyhal_resource_inst_t pin_rsc; @@ -436,33 +437,12 @@ void cyhal_spi_free(cyhal_spi_t *obj) cyhal_hwmgr_free(&(obj->resource)); obj->resource.type = CYHAL_RSC_INVALID; } - if (CYHAL_NC_PIN_VALUE != obj->pin_miso) - { - cyhal_utils_disconnect_and_free(obj->pin_miso); - obj->pin_miso = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_mosi) - { - cyhal_utils_disconnect_and_free(obj->pin_mosi); - obj->pin_mosi = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_sclk) - { - cyhal_utils_disconnect_and_free(obj->pin_sclk); - obj->pin_sclk = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_ssel) - { - if (obj->is_slave) - { - cyhal_utils_disconnect_and_free(obj->pin_ssel); - obj->pin_ssel = CYHAL_NC_PIN_VALUE; - } - else - { - cyhal_gpio_free(obj->pin_ssel); - } - } + + cyhal_utils_release_if_used(&(obj->pin_miso)); + cyhal_utils_release_if_used(&(obj->pin_mosi)); + cyhal_utils_release_if_used(&(obj->pin_sclk)); + cyhal_utils_release_if_used(&(obj->pin_ssel)); + if (obj->alloc_clock) { cyhal_hwmgr_free_clock(&(obj->clock)); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_system.c similarity index 81% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_system.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_system.c index cdd57a5eae..c4e9594800 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_system.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,6 +27,9 @@ #include "cyhal_system.h" #include "cyhal_hwmgr.h" +#ifdef CY_RTOS_AWARE +#include "cyabs_rtos.h" +#endif #ifdef CY_IP_MXS40SRSS @@ -51,6 +54,16 @@ cy_rslt_t cyhal_system_unregister_callback(cyhal_system_callback_t const *handle : CYHAL_SYSTEM_RSLT_ERROR; } +cy_rslt_t cyhal_system_delay_ms(uint32_t milliseconds) +{ +#ifdef CY_RTOS_AWARE + return cy_rtos_delay_milliseconds(milliseconds); +#else + Cy_SysLib_Delay(milliseconds); + return CY_RSLT_SUCCESS; +#endif +} + uint32_t get_src_freq(cy_en_clkpath_in_sources_t source) { /* get the frequency of the source, i.e., the path mux input */ @@ -67,7 +80,7 @@ uint32_t get_src_freq(cy_en_clkpath_in_sources_t source) } } -uint32_t get_clkpath_freq(cy_en_clkhf_in_sources_t path, uint32_t freq, uint8_t *fll_pll_used) +static uint32_t get_clkpath_freq(cy_en_clkhf_in_sources_t path, uint32_t freq, uint8_t *fll_pll_used) { *fll_pll_used = 0xff; if (path == CY_SYSCLK_CLKHF_IN_CLKPATH0) @@ -97,7 +110,7 @@ uint32_t get_clkpath_freq(cy_en_clkhf_in_sources_t path, uint32_t freq, uint8_t return freq; } -cy_rslt_t try_set_hf_divider(uint8_t clock, uint32_t input_freq, uint32_t target_freq) +static cy_rslt_t try_set_hf_divider(uint8_t clock, uint32_t input_freq, uint32_t target_freq) { bool divider_found = false; cy_en_clkhf_dividers_t divider; @@ -134,7 +147,7 @@ cy_rslt_t try_set_hf_divider(uint8_t clock, uint32_t input_freq, uint32_t target } } -cy_rslt_t try_set_fll(uint8_t clock, uint32_t target_freq) +static cy_rslt_t try_set_fll(uint8_t clock, uint32_t target_freq) { Cy_SysClk_FllDisable(); Cy_SysClk_ClkHfSetSource(clock, CY_SYSCLK_CLKHF_IN_CLKPATH0); @@ -153,7 +166,7 @@ cy_rslt_t try_set_fll(uint8_t clock, uint32_t target_freq) return rslt; } -cy_rslt_t try_set_pll(uint8_t clock, uint8_t pll, uint32_t target_freq) +static cy_rslt_t try_set_pll(uint8_t clock, uint8_t pll, uint32_t target_freq) { Cy_SysClk_PllDisable(pll); Cy_SysClk_ClkHfSetSource(clock, (cy_en_clkhf_in_sources_t)(pll)); @@ -180,7 +193,7 @@ cy_rslt_t try_set_pll(uint8_t clock, uint8_t pll, uint32_t target_freq) } /* This should be part of the PDL */ -static inline bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf) +static inline bool cyhal_sysclk_clkhfisenabled(uint32_t clkHf) { bool retVal = false; if (clkHf < CY_SRSS_NUM_HFROOT) @@ -216,7 +229,7 @@ cy_rslt_t cyhal_system_clock_set_frequency(uint8_t clock, uint32_t frequency_hz) return rslt; } - bool enabled = Cy_SysClk_ClkHfIsEnabled(clock); + bool enabled = cyhal_sysclk_clkhfisenabled(clock); if (enabled && fll_pll_used == 0) { return try_set_fll(clock, frequency_hz); @@ -292,6 +305,39 @@ cy_rslt_t cyhal_system_clock_set_divider(cyhal_system_clock_t clock, cyhal_syste return CY_RSLT_SUCCESS; } +cyhal_reset_reason_t cyhal_system_get_reset_reason(void) +{ + uint32_t pdl_reason = Cy_SysLib_GetResetReason(); + cyhal_reset_reason_t reason = CYHAL_SYSTEM_RESET_NONE; + + if (CY_SYSLIB_RESET_ACT_FAULT & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_ACTIVE_FAULT; + if (CY_SYSLIB_RESET_DPSLP_FAULT & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_DEEPSLEEP_FAULT; + if (CY_SYSLIB_RESET_SOFT & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_SOFT; + if (CY_SYSLIB_RESET_HIB_WAKEUP & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_HIB_WAKEUP; + if ((CY_SYSLIB_RESET_HWWDT | CY_SYSLIB_RESET_SWWDT0 | CY_SYSLIB_RESET_SWWDT1 | + CY_SYSLIB_RESET_SWWDT2 | CY_SYSLIB_RESET_SWWDT3) & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_WDT; +#if (SRSS_WCOCSV_PRESENT != 0U) + if (CY_SYSLIB_RESET_CSV_WCO_LOSS & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_WCO_ERR; +#endif +#if (SRSS_MASK_HFCSV != 0) + if ((CY_SYSLIB_RESET_HFCLK_LOSS | CY_SYSLIB_RESET_HFCLK_ERR) & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_SYS_CLK_ERR; +#endif + + return reason; +} + +void cyhal_system_clear_reset_reason(void) +{ + Cy_SysLib_ClearResetReason(); +} + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_tcpwm_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_tcpwm_common.c similarity index 85% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_tcpwm_common.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_tcpwm_common.c index 26e2670f1c..00368586ec 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_tcpwm_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_tcpwm_common.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -79,24 +79,27 @@ void cyhal_tcpwm_irq_handler() channel = irqn - CYHAL_TCPWM_DATA[block].isr_offset; break; } - else - { - CY_ASSERT(block != CY_IP_MXTCPWM_INSTANCES - 1); // IRQn should always be in one of those ranges - } } - TCPWM_Type *blockAddr = CYHAL_TCPWM_DATA[block].base; - uint32_t index = GET_ARRAY_INDEX(block, channel); - - cyhal_event_callback_data_t *callback_data = cyhal_tcpwm_callback_data_structs[index]; - if (callback_data->callback != NULL) + if (block < CY_IP_MXTCPWM_INSTANCES) { - cyhal_tcpwm_event_callback_t callback = (cyhal_tcpwm_event_callback_t) callback_data->callback; - /* Call registered callbacks here */ - (void) (callback) (callback_data->callback_arg, Cy_TCPWM_GetInterruptStatus(blockAddr, channel)); - } + TCPWM_Type *blockAddr = CYHAL_TCPWM_DATA[block].base; + uint32_t index = GET_ARRAY_INDEX(block, channel); - Cy_TCPWM_ClearInterrupt(blockAddr, channel, CY_TCPWM_INT_ON_CC_OR_TC); + cyhal_event_callback_data_t *callback_data = cyhal_tcpwm_callback_data_structs[index]; + if (callback_data->callback != NULL) + { + cyhal_tcpwm_event_callback_t callback = (cyhal_tcpwm_event_callback_t) callback_data->callback; + /* Call registered callbacks here */ + (void) (callback) (callback_data->callback_arg, Cy_TCPWM_GetInterruptStatus(blockAddr, channel)); + } + + Cy_TCPWM_ClearInterrupt(blockAddr, channel, CY_TCPWM_INT_ON_CC_OR_TC); + } + else + { + CY_HALT(); // Could not determine the block/channel for IRQn + } } /******************************************************************************* diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_timer.c similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_timer.c index 1491d45890..a7a755edb7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_timer.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -59,7 +59,7 @@ static const cy_stc_tcpwm_counter_config_t default_config = }; /** Convert timer direction from the HAL enum to the corresponding PDL constant - * + * * @param[in] direction The direction, as a HAL enum value * @return The direction, as a PDL constant */ @@ -85,7 +85,7 @@ cy_rslt_t cyhal_timer_init(cyhal_timer_t *obj, cyhal_gpio_t pin, const cyhal_clo { CY_ASSERT(NULL != obj); - //TODO: Handle Trigger mux pin assignments + // No support currently for pin connections on this device if (CYHAL_NC_PIN_VALUE != pin) return CYHAL_TIMER_RSLT_ERR_BAD_ARGUMENT; @@ -148,7 +148,7 @@ void cyhal_timer_free(cyhal_timer_t *obj) IRQn_Type irqn = (IRQn_Type)(CYHAL_TCPWM_DATA[obj->resource.block_num].isr_offset + obj->resource.channel_num); NVIC_DisableIRQ(irqn); - if (NULL != obj && NULL != obj->base) + if (NULL != obj->base) { Cy_TCPWM_Counter_Disable(obj->base, obj->resource.channel_num); @@ -159,6 +159,7 @@ void cyhal_timer_free(cyhal_timer_t *obj) if (obj->dedicated_clock) { cy_en_sysclk_status_t rslt = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); + CY_UNUSED_PARAMETER(rslt); /* CY_ASSERT only processes in DEBUG, ignores for others */ CY_ASSERT(CY_SYSCLK_SUCCESS == rslt); cyhal_hwmgr_free_clock(&(obj->clock)); obj->dedicated_clock = false; @@ -217,6 +218,7 @@ cy_rslt_t cyhal_timer_set_frequency(cyhal_timer_t *obj, uint32_t hz) { uint32_t div = Cy_SysClk_ClkPeriGetFrequency() / hz; if (0 == div || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num) || CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num)) { @@ -245,6 +247,12 @@ cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj) return CY_RSLT_SUCCESS; } +uint32_t cyhal_timer_read(const cyhal_timer_t *obj) +{ + CY_ASSERT(NULL != obj); + return Cy_TCPWM_Counter_GetCounter(obj->base, obj->resource.channel_num); +} + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_trng.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_trng.c similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_trng.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_trng.c index c18117eb57..6248b3d0b1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_trng.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_trng.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_uart.c similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_uart.c index fe5b2ea491..f5897ee09c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_uart.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -322,22 +322,12 @@ void cyhal_uart_free(cyhal_uart_t *obj) cyhal_hwmgr_free(&(obj->resource)); Cy_SysPm_UnregisterCallback(&(obj->pm_callback)); } - if (CYHAL_NC_PIN_VALUE != obj->pin_rx) - { - cyhal_utils_disconnect_and_free(obj->pin_rx); - } - if (CYHAL_NC_PIN_VALUE != obj->pin_tx) - { - cyhal_utils_disconnect_and_free(obj->pin_tx); - } - if (CYHAL_NC_PIN_VALUE != obj->pin_rts) - { - cyhal_utils_disconnect_and_free(obj->pin_rts); - } - if (CYHAL_NC_PIN_VALUE != obj->pin_cts) - { - cyhal_utils_disconnect_and_free(obj->pin_cts); - } + + cyhal_utils_release_if_used(&(obj->pin_rx)); + cyhal_utils_release_if_used(&(obj->pin_tx)); + cyhal_utils_release_if_used(&(obj->pin_rts)); + cyhal_utils_release_if_used(&(obj->pin_cts)); + if (!(obj->is_user_clock)) { cyhal_hwmgr_free_clock(&(obj->clock)); @@ -634,7 +624,7 @@ cy_rslt_t cyhal_uart_read_async(cyhal_uart_t *obj, void *rx, size_t length) bool cyhal_uart_is_tx_active(cyhal_uart_t *obj) { - return (0UL != (obj->context.txStatus & CY_SCB_UART_TRANSMIT_ACTIVE)) || !Cy_SCB_IsTxComplete(obj->base); + return (0UL != (obj->context.txStatus & CY_SCB_UART_TRANSMIT_ACTIVE)); } bool cyhal_uart_is_rx_active(cyhal_uart_t *obj) @@ -708,10 +698,12 @@ void cyhal_uart_enable_event(cyhal_uart_t *obj, cyhal_uart_event_t event, uint8_ obj->irq_cause |= event; if (event & CYHAL_UART_IRQ_RX_NOT_EMPTY) { + Cy_SCB_ClearRxInterrupt(obj->base, CY_SCB_RX_INTR_NOT_EMPTY); Cy_SCB_SetRxInterruptMask(obj->base, Cy_SCB_GetRxInterruptMask(obj->base) | CY_SCB_RX_INTR_NOT_EMPTY); } if (event & CYHAL_UART_IRQ_TX_EMPTY) { + Cy_SCB_ClearTxInterrupt(obj->base, CY_SCB_UART_TX_EMPTY); Cy_SCB_SetTxInterruptMask(obj->base, Cy_SCB_GetTxInterruptMask(obj->base) | CY_SCB_UART_TX_EMPTY); } } @@ -720,12 +712,10 @@ void cyhal_uart_enable_event(cyhal_uart_t *obj, cyhal_uart_event_t event, uint8_ obj->irq_cause &= ~event; if (event & CYHAL_UART_IRQ_RX_NOT_EMPTY) { - Cy_SCB_ClearRxInterrupt(obj->base, CY_SCB_RX_INTR_NOT_EMPTY); Cy_SCB_SetRxInterruptMask(obj->base, Cy_SCB_GetRxInterruptMask(obj->base) & ~CY_SCB_RX_INTR_NOT_EMPTY); } if (event & CYHAL_UART_IRQ_TX_EMPTY) { - Cy_SCB_ClearTxInterrupt(obj->base, CY_SCB_UART_TX_EMPTY); Cy_SCB_SetTxInterruptMask(obj->base, Cy_SCB_GetTxInterruptMask(obj->base) & ~CY_SCB_UART_TX_EMPTY); } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_udb_sdio.c similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_udb_sdio.c index 5725c0c913..9402f609aa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_udb_sdio.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ *******************************************************************************/ #include "cyhal_hwmgr.h" +#include "cy_utils.h" #if defined(CYHAL_UDB_SDIO) @@ -39,9 +40,6 @@ extern "C" #include "cyhal_gpio.h" #include "cyhal_interconnect.h" -/* Not connected pin define */ -#define SDIO_PINS_NC ((cyhal_gpio_t) CYHAL_NC_PIN_VALUE) - #define CY_HAL_SDIO_CLK_DIV_VALUE ((uint8_t) 0xFF) /* Not configured clock divider define*/ @@ -128,7 +126,6 @@ static const cy_stc_gpio_pin_config_t pin_clk_config = /******************************************************************************* * Internal functions *******************************************************************************/ -static void cyhal_free_pins(cyhal_sdio_t *obj); static cy_en_syspm_status_t cyhal_sdio_ds_callback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode); /****************************************************************************** @@ -235,22 +232,6 @@ static void cyhal_sdio_interrupts_dispatcher_IRQHandler(void) } } -static void cyhal_free_pins(cyhal_sdio_t *obj) -{ - cyhal_gpio_free(obj->pin_clk); - obj->pin_clk = SDIO_PINS_NC; - cyhal_gpio_free(obj->pin_cmd); - obj->pin_cmd = SDIO_PINS_NC; - cyhal_gpio_free(obj->pin_data0); - obj->pin_data0 = SDIO_PINS_NC; - cyhal_gpio_free(obj->pin_data1); - obj->pin_data1 = SDIO_PINS_NC; - cyhal_gpio_free(obj->pin_data2); - obj->pin_data2 = SDIO_PINS_NC; - cyhal_gpio_free(obj->pin_data3); - obj->pin_data3 = SDIO_PINS_NC; -} - static void cyhal_free_clocks(cyhal_sdio_t *obj) { cyhal_resource_inst_t udbClkRsc; @@ -260,10 +241,10 @@ static void cyhal_free_clocks(cyhal_sdio_t *obj) cyhal_hwmgr_free(&udbClkRsc); } -static void cyhal_free_dmas(cyhal_sdio_t *obj) +static void cyhal_free_dmas() { cyhal_resource_inst_t dmaRsc; - dmaRsc.type = CYHAL_RSC_DMA; + dmaRsc.type = CYHAL_RSC_DW; dmaRsc.block_num = 0; dmaRsc.channel_num = 0; @@ -295,12 +276,12 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, * SDIO. */ obj->resource.type = CYHAL_RSC_INVALID; - obj->pin_cmd = SDIO_PINS_NC; - obj->pin_clk = SDIO_PINS_NC; - obj->pin_data0 = SDIO_PINS_NC; - obj->pin_data1 = SDIO_PINS_NC; - obj->pin_data2 = SDIO_PINS_NC; - obj->pin_data3 = SDIO_PINS_NC; + obj->pin_cmd = CYHAL_NC_PIN_VALUE; + obj->pin_clk = CYHAL_NC_PIN_VALUE; + obj->pin_data0 = CYHAL_NC_PIN_VALUE; + obj->pin_data1 = CYHAL_NC_PIN_VALUE; + obj->pin_data2 = CYHAL_NC_PIN_VALUE; + obj->pin_data3 = CYHAL_NC_PIN_VALUE; obj->dma0Ch0.resource.type = CYHAL_RSC_INVALID; obj->dma0Ch1.resource.type = CYHAL_RSC_INVALID; obj->dma1Ch1.resource.type = CYHAL_RSC_INVALID; @@ -336,28 +317,28 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, if (retVal == CY_RSLT_SUCCESS) { /* Reserve DMA0 CH0 */ - cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 0, 0 }; + cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DW, 0, 0 }; retVal = cyhal_hwmgr_reserve(&dmaRsc); } if (retVal == CY_RSLT_SUCCESS) { /* Reserve DMA0 CH1 */ - cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 0, 1 }; + cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DW, 0, 1 }; retVal = cyhal_hwmgr_reserve(&dmaRsc); } if (retVal == CY_RSLT_SUCCESS) { /* Reserve DMA1 CH1 */ - cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 1, 1 }; + cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DW, 1, 1 }; retVal = cyhal_hwmgr_reserve(&dmaRsc); } if (retVal == CY_RSLT_SUCCESS) { /* Reserve DMA1 CH3 */ - cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 1, 3 }; + cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DW, 1, 3 }; retVal = cyhal_hwmgr_reserve(&dmaRsc); } @@ -502,9 +483,15 @@ void cyhal_sdio_free(cyhal_sdio_t *obj) NVIC_DisableIRQ(cpuss_interrupts_dw1_1_IRQn); NVIC_DisableIRQ(cpuss_interrupts_dw1_3_IRQn); - cyhal_free_pins(obj); + cyhal_utils_release_if_used(&(obj->pin_clk)); + cyhal_utils_release_if_used(&(obj->pin_cmd)); + cyhal_utils_release_if_used(&(obj->pin_data0)); + cyhal_utils_release_if_used(&(obj->pin_data1)); + cyhal_utils_release_if_used(&(obj->pin_data2)); + cyhal_utils_release_if_used(&(obj->pin_data3)); + cyhal_free_clocks(obj); - cyhal_free_dmas(obj); + cyhal_free_dmas(); cyhal_hwmgr_free(&(obj->resource)); SDIO_Free(); @@ -675,12 +662,14 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj) { /* UDB SDIO does not support async transfers */ + CY_UNUSED_PARAMETER(obj); return false; } cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj) { /* Reset UDB SDIO */ + CY_UNUSED_PARAMETER(obj); SDIO_Reset(); return CY_RSLT_SUCCESS; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_usb_dev.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_usb_dev.c index 884bec75c7..29a30358ab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_usb_dev.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -470,15 +470,8 @@ static void cyhal_usb_dev_free_resources(cyhal_usb_dev_t *obj) cyhal_hwmgr_free_clock(&(obj->clock)); } - if (CYHAL_NC_PIN_VALUE != obj->pin_dp) - { - cyhal_utils_disconnect_and_free(obj->pin_dp); - } - - if (CYHAL_NC_PIN_VALUE != obj->pin_dm) - { - cyhal_utils_disconnect_and_free(obj->pin_dm); - } + cyhal_utils_release_if_used(&(obj->pin_dp)); + cyhal_utils_release_if_used(&(obj->pin_dm)); } cy_rslt_t cyhal_usb_dev_init(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, cyhal_gpio_t dm, const cyhal_clock_divider_t *clk) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_utils.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_utils.c similarity index 60% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_utils.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_utils.c index 2492d4952e..adba880a49 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_utils.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_utils.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,10 +22,10 @@ * limitations under the License. *******************************************************************************/ -#include "cy_result.h" #include "cyhal_utils.h" #include "cyhal_hwmgr.h" #include "cyhal_interconnect.h" +#include "cyhal_gpio.h" #if defined(__cplusplus) extern "C" @@ -44,14 +44,46 @@ const cyhal_resource_pin_mapping_t *cyhal_utils_get_resource(cyhal_gpio_t pin, c return NULL; } +cy_rslt_t cyhal_utils_reserve_and_connect(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *mapping) +{ + cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin); + cy_rslt_t status = cyhal_hwmgr_reserve(&pinRsc); + if (CY_RSLT_SUCCESS == status) + { + status = cyhal_connect_pin(mapping); + if (CY_RSLT_SUCCESS != status) + { + cyhal_hwmgr_free(&pinRsc); + } + } + return status; +} + void cyhal_utils_disconnect_and_free(cyhal_gpio_t pin) { cy_rslt_t rslt = cyhal_disconnect_pin(pin); + CY_UNUSED_PARAMETER(rslt); /* CY_ASSERT only processes in DEBUG, ignores for others */ CY_ASSERT(CY_RSLT_SUCCESS == rslt); cyhal_resource_inst_t rsc = cyhal_utils_get_gpio_resource(pin); cyhal_hwmgr_free(&rsc); } +void cyhal_utils_release_if_used(cyhal_gpio_t *pin) +{ + if (CYHAL_NC_PIN_VALUE != *pin) + { + cyhal_utils_disconnect_and_free(*pin); + *pin = CYHAL_NC_PIN_VALUE; + } +} + +bool cyhal_utils_resources_equal(const cyhal_resource_inst_t *resource1, const cyhal_resource_inst_t *resource2) +{ + return (resource1->type == resource2->type) && + (resource1->block_num == resource2->block_num) && + (resource1->channel_num == resource2->channel_num); +} + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_wdt.c similarity index 95% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_wdt.c index 731122736a..794051fbaa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_wdt.c @@ -10,7 +10,7 @@ * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,8 +27,8 @@ *******************************************************************************/ /** -* \addtogroup group_hal_psoc6_wdt (WDT) Watchdog Timer -* \ingroup group_hal_psoc6 +* \addtogroup group_hal_psoc6_wdt WDT (Watchdog Timer) +* \ingroup group_hal_psoc6 * \{ * The PSoC 6 WDT is only capable of supporting certain timeout ranges below its maximum timeout of 6000ms. * As a result, any unsupported timeouts given to the HAL WDT are rounded up to the nearest supported value. @@ -87,6 +87,7 @@ #include "cyhal_wdt.h" #include "cy_wdt.h" #include "cy_lvd.h" +#include "cy_utils.h" #if defined(__cplusplus) extern "C" { @@ -187,6 +188,7 @@ cy_rslt_t cyhal_wdt_init(cyhal_wdt_t *obj, uint32_t timeout_ms) void cyhal_wdt_free(cyhal_wdt_t *obj) { + CY_UNUSED_PARAMETER(obj); cyhal_wdt_stop(obj); cyhal_wdt_initialized = false; @@ -194,11 +196,13 @@ void cyhal_wdt_free(cyhal_wdt_t *obj) void cyhal_wdt_kick(cyhal_wdt_t *obj) { + CY_UNUSED_PARAMETER(obj); Cy_WDT_ClearWatchdog(); } void cyhal_wdt_start(cyhal_wdt_t *obj) { + CY_UNUSED_PARAMETER(obj); Cy_WDT_Unlock(); Cy_WDT_Enable(); Cy_WDT_Lock(); @@ -206,12 +210,14 @@ void cyhal_wdt_start(cyhal_wdt_t *obj) void cyhal_wdt_stop(cyhal_wdt_t *obj) { + CY_UNUSED_PARAMETER(obj); Cy_WDT_Unlock(); Cy_WDT_Disable(); } uint32_t cyhal_wdt_get_timeout_ms(cyhal_wdt_t *obj) { + CY_UNUSED_PARAMETER(obj); return cyhal_wdt_initial_timeout_ms; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c index aba6f0c098..d403b9754b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c index 52632bfbe3..b0b16967a7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_ble.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_ble.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_ble.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_ble.c index d3739e8152..f99c7e46e2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_ble.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_ble.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_usb.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_usb.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_usb.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_usb.c index cfbe3be6e6..fd7d26cbfd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_usb.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_usb.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga.c index 5c60a3377b..ee1079ad01 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga_sip.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga_sip.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga_sip.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga_sip.c index b054780a44..f9cefebc94 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga_sip.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga_sip.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_43_smt.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_43_smt.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_43_smt.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_43_smt.c index 99139febff..1ea1fe0099 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_43_smt.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_43_smt.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_68_qfn_ble.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_68_qfn_ble.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_68_qfn_ble.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_68_qfn_ble.c index f16ceef071..5720e7acaf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_68_qfn_ble.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_68_qfn_ble.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_80_wlcsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_80_wlcsp.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_80_wlcsp.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_80_wlcsp.c index 32f8410d03..ebbe5ea36e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_80_wlcsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_80_wlcsp.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_100_wlcsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_100_wlcsp.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_100_wlcsp.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_100_wlcsp.c index eff52802c5..10cce48154 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_100_wlcsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_100_wlcsp.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_124_bga.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_124_bga.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_124_bga.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_124_bga.c index 04c906e0ef..a4e9d65f4d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_124_bga.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_124_bga.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_128_tqfp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_128_tqfp.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_128_tqfp.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_128_tqfp.c index 4a0fe2db8d..a2003cb859 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_128_tqfp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_128_tqfp.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_68_qfn.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_68_qfn.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_68_qfn.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_68_qfn.c index b08ff8ecb6..1a57ede495 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_68_qfn.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_68_qfn.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_100_tqfp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_100_tqfp.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_100_tqfp.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_100_tqfp.c index b3dd0ba45f..74c69f0fdb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_100_tqfp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_100_tqfp.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_49_wlcsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_49_wlcsp.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_49_wlcsp.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_49_wlcsp.c index 4cc2c80792..2af3573012 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_49_wlcsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_49_wlcsp.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_68_qfn.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_68_qfn.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_68_qfn.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_68_qfn.c index f9ff30a847..2795847881 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_68_qfn.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_68_qfn.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_01.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_01.c new file mode 100644 index 0000000000..7953c1e6b3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_01.c @@ -0,0 +1,999 @@ +/***************************************************************************//** +* \file cyhal_triggers_psoc6_01.c +* +* \brief +* PSoC6_01 family HAL triggers header +* +* \note +* Generator version: 1.5.7254.19579 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cy_device_headers.h" +#include "cyhal_hw_types.h" + +#ifdef CY_DEVICE_PSOC6ABLE2 +#include "triggers/cyhal_triggers_psoc6_01.h" + +const uint8_t cyhal_dest_to_mux[479] = +{ + 5, /* TRIGGER_CPUSS_CTI_TR_IN0 */ + 5, /* TRIGGER_CPUSS_CTI_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN0 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN2 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN3 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN4 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN5 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN6 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN7 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN8 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN9 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN10 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN11 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN12 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN13 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN14 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN15 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN1 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN2 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN3 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN4 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN5 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN6 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN7 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN8 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN9 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN10 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN11 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN12 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN13 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN14 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN15 */ + 6, /* TRIGGER_PASS_TR_SAR_IN */ + 8, /* TRIGGER_PERI_TR_IO_OUTPUT0 */ + 8, /* TRIGGER_PERI_TR_IO_OUTPUT1 */ + 4, /* TRIGGER_PROFILE_TR_START */ + 4, /* TRIGGER_PROFILE_TR_STOP */ + 2, /* TRIGGER_TCPWM0_TR_IN0 */ + 2, /* TRIGGER_TCPWM0_TR_IN1 */ + 2, /* TRIGGER_TCPWM0_TR_IN2 */ + 2, /* TRIGGER_TCPWM0_TR_IN3 */ + 2, /* TRIGGER_TCPWM0_TR_IN4 */ + 2, /* TRIGGER_TCPWM0_TR_IN5 */ + 2, /* TRIGGER_TCPWM0_TR_IN6 */ + 2, /* TRIGGER_TCPWM0_TR_IN7 */ + 2, /* TRIGGER_TCPWM0_TR_IN8 */ + 2, /* TRIGGER_TCPWM0_TR_IN9 */ + 2, /* TRIGGER_TCPWM0_TR_IN10 */ + 2, /* TRIGGER_TCPWM0_TR_IN11 */ + 2, /* TRIGGER_TCPWM0_TR_IN12 */ + 2, /* TRIGGER_TCPWM0_TR_IN13 */ + 3, /* TRIGGER_TCPWM1_TR_IN0 */ + 3, /* TRIGGER_TCPWM1_TR_IN1 */ + 3, /* TRIGGER_TCPWM1_TR_IN2 */ + 3, /* TRIGGER_TCPWM1_TR_IN3 */ + 3, /* TRIGGER_TCPWM1_TR_IN4 */ + 3, /* TRIGGER_TCPWM1_TR_IN5 */ + 3, /* TRIGGER_TCPWM1_TR_IN6 */ + 3, /* TRIGGER_TCPWM1_TR_IN7 */ + 3, /* TRIGGER_TCPWM1_TR_IN8 */ + 3, /* TRIGGER_TCPWM1_TR_IN9 */ + 3, /* TRIGGER_TCPWM1_TR_IN10 */ + 3, /* TRIGGER_TCPWM1_TR_IN11 */ + 3, /* TRIGGER_TCPWM1_TR_IN12 */ + 3, /* TRIGGER_TCPWM1_TR_IN13 */ + 10, /* TRIGGER_TR_GROUP0_INPUT1 */ + 10, /* TRIGGER_TR_GROUP0_INPUT2 */ + 10, /* TRIGGER_TR_GROUP0_INPUT3 */ + 10, /* TRIGGER_TR_GROUP0_INPUT4 */ + 10, /* TRIGGER_TR_GROUP0_INPUT5 */ + 10, /* TRIGGER_TR_GROUP0_INPUT6 */ + 10, /* TRIGGER_TR_GROUP0_INPUT7 */ + 10, /* TRIGGER_TR_GROUP0_INPUT8 */ + 11, /* TRIGGER_TR_GROUP0_INPUT9 */ + 11, /* TRIGGER_TR_GROUP0_INPUT10 */ + 11, /* TRIGGER_TR_GROUP0_INPUT11 */ + 11, /* TRIGGER_TR_GROUP0_INPUT12 */ + 11, /* TRIGGER_TR_GROUP0_INPUT13 */ + 11, /* TRIGGER_TR_GROUP0_INPUT14 */ + 11, /* TRIGGER_TR_GROUP0_INPUT15 */ + 11, /* TRIGGER_TR_GROUP0_INPUT16 */ + 11, /* TRIGGER_TR_GROUP0_INPUT17 */ + 11, /* TRIGGER_TR_GROUP0_INPUT18 */ + 11, /* TRIGGER_TR_GROUP0_INPUT19 */ + 11, /* TRIGGER_TR_GROUP0_INPUT20 */ + 11, /* TRIGGER_TR_GROUP0_INPUT21 */ + 11, /* TRIGGER_TR_GROUP0_INPUT22 */ + 11, /* TRIGGER_TR_GROUP0_INPUT23 */ + 11, /* TRIGGER_TR_GROUP0_INPUT24 */ + 12, /* TRIGGER_TR_GROUP0_INPUT25 */ + 12, /* TRIGGER_TR_GROUP0_INPUT26 */ + 13, /* TRIGGER_TR_GROUP0_INPUT27 */ + 13, /* TRIGGER_TR_GROUP0_INPUT28 */ + 13, /* TRIGGER_TR_GROUP0_INPUT29 */ + 13, /* TRIGGER_TR_GROUP0_INPUT30 */ + 13, /* TRIGGER_TR_GROUP0_INPUT31 */ + 13, /* TRIGGER_TR_GROUP0_INPUT32 */ + 13, /* TRIGGER_TR_GROUP0_INPUT33 */ + 13, /* TRIGGER_TR_GROUP0_INPUT34 */ + 13, /* TRIGGER_TR_GROUP0_INPUT35 */ + 13, /* TRIGGER_TR_GROUP0_INPUT36 */ + 13, /* TRIGGER_TR_GROUP0_INPUT37 */ + 13, /* TRIGGER_TR_GROUP0_INPUT38 */ + 13, /* TRIGGER_TR_GROUP0_INPUT39 */ + 13, /* TRIGGER_TR_GROUP0_INPUT40 */ + 13, /* TRIGGER_TR_GROUP0_INPUT41 */ + 13, /* TRIGGER_TR_GROUP0_INPUT42 */ + 14, /* TRIGGER_TR_GROUP0_INPUT43 */ + 14, /* TRIGGER_TR_GROUP0_INPUT44 */ + 14, /* TRIGGER_TR_GROUP0_INPUT45 */ + 14, /* TRIGGER_TR_GROUP0_INPUT46 */ + 14, /* TRIGGER_TR_GROUP0_INPUT47 */ + 14, /* TRIGGER_TR_GROUP0_INPUT48 */ + 14, /* TRIGGER_TR_GROUP0_INPUT49 */ + 14, /* TRIGGER_TR_GROUP0_INPUT50 */ + 10, /* TRIGGER_TR_GROUP1_INPUT1 */ + 10, /* TRIGGER_TR_GROUP1_INPUT2 */ + 10, /* TRIGGER_TR_GROUP1_INPUT3 */ + 10, /* TRIGGER_TR_GROUP1_INPUT4 */ + 10, /* TRIGGER_TR_GROUP1_INPUT5 */ + 10, /* TRIGGER_TR_GROUP1_INPUT6 */ + 10, /* TRIGGER_TR_GROUP1_INPUT7 */ + 10, /* TRIGGER_TR_GROUP1_INPUT8 */ + 11, /* TRIGGER_TR_GROUP1_INPUT9 */ + 11, /* TRIGGER_TR_GROUP1_INPUT10 */ + 11, /* TRIGGER_TR_GROUP1_INPUT11 */ + 11, /* TRIGGER_TR_GROUP1_INPUT12 */ + 11, /* TRIGGER_TR_GROUP1_INPUT13 */ + 11, /* TRIGGER_TR_GROUP1_INPUT14 */ + 11, /* TRIGGER_TR_GROUP1_INPUT15 */ + 11, /* TRIGGER_TR_GROUP1_INPUT16 */ + 11, /* TRIGGER_TR_GROUP1_INPUT17 */ + 11, /* TRIGGER_TR_GROUP1_INPUT18 */ + 11, /* TRIGGER_TR_GROUP1_INPUT19 */ + 11, /* TRIGGER_TR_GROUP1_INPUT20 */ + 11, /* TRIGGER_TR_GROUP1_INPUT21 */ + 11, /* TRIGGER_TR_GROUP1_INPUT22 */ + 11, /* TRIGGER_TR_GROUP1_INPUT23 */ + 11, /* TRIGGER_TR_GROUP1_INPUT24 */ + 12, /* TRIGGER_TR_GROUP1_INPUT25 */ + 12, /* TRIGGER_TR_GROUP1_INPUT26 */ + 13, /* TRIGGER_TR_GROUP1_INPUT27 */ + 13, /* TRIGGER_TR_GROUP1_INPUT28 */ + 13, /* TRIGGER_TR_GROUP1_INPUT29 */ + 13, /* TRIGGER_TR_GROUP1_INPUT30 */ + 13, /* TRIGGER_TR_GROUP1_INPUT31 */ + 13, /* TRIGGER_TR_GROUP1_INPUT32 */ + 13, /* TRIGGER_TR_GROUP1_INPUT33 */ + 13, /* TRIGGER_TR_GROUP1_INPUT34 */ + 13, /* TRIGGER_TR_GROUP1_INPUT35 */ + 13, /* TRIGGER_TR_GROUP1_INPUT36 */ + 13, /* TRIGGER_TR_GROUP1_INPUT37 */ + 13, /* TRIGGER_TR_GROUP1_INPUT38 */ + 13, /* TRIGGER_TR_GROUP1_INPUT39 */ + 13, /* TRIGGER_TR_GROUP1_INPUT40 */ + 13, /* TRIGGER_TR_GROUP1_INPUT41 */ + 13, /* TRIGGER_TR_GROUP1_INPUT42 */ + 14, /* TRIGGER_TR_GROUP1_INPUT43 */ + 14, /* TRIGGER_TR_GROUP1_INPUT44 */ + 14, /* TRIGGER_TR_GROUP1_INPUT45 */ + 14, /* TRIGGER_TR_GROUP1_INPUT46 */ + 14, /* TRIGGER_TR_GROUP1_INPUT47 */ + 14, /* TRIGGER_TR_GROUP1_INPUT48 */ + 14, /* TRIGGER_TR_GROUP1_INPUT49 */ + 14, /* TRIGGER_TR_GROUP1_INPUT50 */ + 10, /* TRIGGER_TR_GROUP2_INPUT1 */ + 10, /* TRIGGER_TR_GROUP2_INPUT2 */ + 10, /* TRIGGER_TR_GROUP2_INPUT3 */ + 10, /* TRIGGER_TR_GROUP2_INPUT4 */ + 10, /* TRIGGER_TR_GROUP2_INPUT5 */ + 10, /* TRIGGER_TR_GROUP2_INPUT6 */ + 10, /* TRIGGER_TR_GROUP2_INPUT7 */ + 10, /* TRIGGER_TR_GROUP2_INPUT8 */ + 11, /* TRIGGER_TR_GROUP2_INPUT9 */ + 11, /* TRIGGER_TR_GROUP2_INPUT10 */ + 11, /* TRIGGER_TR_GROUP2_INPUT11 */ + 11, /* TRIGGER_TR_GROUP2_INPUT12 */ + 11, /* TRIGGER_TR_GROUP2_INPUT13 */ + 11, /* TRIGGER_TR_GROUP2_INPUT14 */ + 11, /* TRIGGER_TR_GROUP2_INPUT15 */ + 11, /* TRIGGER_TR_GROUP2_INPUT16 */ + 11, /* TRIGGER_TR_GROUP2_INPUT17 */ + 11, /* TRIGGER_TR_GROUP2_INPUT18 */ + 11, /* TRIGGER_TR_GROUP2_INPUT19 */ + 11, /* TRIGGER_TR_GROUP2_INPUT20 */ + 11, /* TRIGGER_TR_GROUP2_INPUT21 */ + 11, /* TRIGGER_TR_GROUP2_INPUT22 */ + 11, /* TRIGGER_TR_GROUP2_INPUT23 */ + 11, /* TRIGGER_TR_GROUP2_INPUT24 */ + 12, /* TRIGGER_TR_GROUP2_INPUT25 */ + 12, /* TRIGGER_TR_GROUP2_INPUT26 */ + 12, /* TRIGGER_TR_GROUP2_INPUT27 */ + 12, /* TRIGGER_TR_GROUP2_INPUT28 */ + 12, /* TRIGGER_TR_GROUP2_INPUT29 */ + 12, /* TRIGGER_TR_GROUP2_INPUT30 */ + 12, /* TRIGGER_TR_GROUP2_INPUT31 */ + 12, /* TRIGGER_TR_GROUP2_INPUT32 */ + 13, /* TRIGGER_TR_GROUP2_INPUT33 */ + 13, /* TRIGGER_TR_GROUP2_INPUT34 */ + 14, /* TRIGGER_TR_GROUP2_INPUT35 */ + 14, /* TRIGGER_TR_GROUP2_INPUT36 */ + 14, /* TRIGGER_TR_GROUP2_INPUT37 */ + 14, /* TRIGGER_TR_GROUP2_INPUT38 */ + 14, /* TRIGGER_TR_GROUP2_INPUT39 */ + 14, /* TRIGGER_TR_GROUP2_INPUT40 */ + 14, /* TRIGGER_TR_GROUP2_INPUT41 */ + 14, /* TRIGGER_TR_GROUP2_INPUT42 */ + 10, /* TRIGGER_TR_GROUP3_INPUT1 */ + 10, /* TRIGGER_TR_GROUP3_INPUT2 */ + 10, /* TRIGGER_TR_GROUP3_INPUT3 */ + 10, /* TRIGGER_TR_GROUP3_INPUT4 */ + 10, /* TRIGGER_TR_GROUP3_INPUT5 */ + 10, /* TRIGGER_TR_GROUP3_INPUT6 */ + 10, /* TRIGGER_TR_GROUP3_INPUT7 */ + 10, /* TRIGGER_TR_GROUP3_INPUT8 */ + 11, /* TRIGGER_TR_GROUP3_INPUT9 */ + 11, /* TRIGGER_TR_GROUP3_INPUT10 */ + 11, /* TRIGGER_TR_GROUP3_INPUT11 */ + 11, /* TRIGGER_TR_GROUP3_INPUT12 */ + 11, /* TRIGGER_TR_GROUP3_INPUT13 */ + 11, /* TRIGGER_TR_GROUP3_INPUT14 */ + 11, /* TRIGGER_TR_GROUP3_INPUT15 */ + 11, /* TRIGGER_TR_GROUP3_INPUT16 */ + 11, /* TRIGGER_TR_GROUP3_INPUT17 */ + 11, /* TRIGGER_TR_GROUP3_INPUT18 */ + 11, /* TRIGGER_TR_GROUP3_INPUT19 */ + 11, /* TRIGGER_TR_GROUP3_INPUT20 */ + 11, /* TRIGGER_TR_GROUP3_INPUT21 */ + 11, /* TRIGGER_TR_GROUP3_INPUT22 */ + 11, /* TRIGGER_TR_GROUP3_INPUT23 */ + 11, /* TRIGGER_TR_GROUP3_INPUT24 */ + 12, /* TRIGGER_TR_GROUP3_INPUT25 */ + 12, /* TRIGGER_TR_GROUP3_INPUT26 */ + 12, /* TRIGGER_TR_GROUP3_INPUT27 */ + 12, /* TRIGGER_TR_GROUP3_INPUT28 */ + 12, /* TRIGGER_TR_GROUP3_INPUT29 */ + 12, /* TRIGGER_TR_GROUP3_INPUT30 */ + 12, /* TRIGGER_TR_GROUP3_INPUT31 */ + 12, /* TRIGGER_TR_GROUP3_INPUT32 */ + 13, /* TRIGGER_TR_GROUP3_INPUT33 */ + 13, /* TRIGGER_TR_GROUP3_INPUT34 */ + 14, /* TRIGGER_TR_GROUP3_INPUT35 */ + 14, /* TRIGGER_TR_GROUP3_INPUT36 */ + 14, /* TRIGGER_TR_GROUP3_INPUT37 */ + 14, /* TRIGGER_TR_GROUP3_INPUT38 */ + 14, /* TRIGGER_TR_GROUP3_INPUT39 */ + 14, /* TRIGGER_TR_GROUP3_INPUT40 */ + 14, /* TRIGGER_TR_GROUP3_INPUT41 */ + 14, /* TRIGGER_TR_GROUP3_INPUT42 */ + 10, /* TRIGGER_TR_GROUP4_INPUT1 */ + 10, /* TRIGGER_TR_GROUP4_INPUT2 */ + 10, /* TRIGGER_TR_GROUP4_INPUT3 */ + 10, /* TRIGGER_TR_GROUP4_INPUT4 */ + 10, /* TRIGGER_TR_GROUP4_INPUT5 */ + 10, /* TRIGGER_TR_GROUP4_INPUT6 */ + 10, /* TRIGGER_TR_GROUP4_INPUT7 */ + 10, /* TRIGGER_TR_GROUP4_INPUT8 */ + 11, /* TRIGGER_TR_GROUP4_INPUT9 */ + 11, /* TRIGGER_TR_GROUP4_INPUT10 */ + 11, /* TRIGGER_TR_GROUP4_INPUT11 */ + 11, /* TRIGGER_TR_GROUP4_INPUT12 */ + 11, /* TRIGGER_TR_GROUP4_INPUT13 */ + 11, /* TRIGGER_TR_GROUP4_INPUT14 */ + 11, /* TRIGGER_TR_GROUP4_INPUT15 */ + 11, /* TRIGGER_TR_GROUP4_INPUT16 */ + 11, /* TRIGGER_TR_GROUP4_INPUT17 */ + 11, /* TRIGGER_TR_GROUP4_INPUT18 */ + 11, /* TRIGGER_TR_GROUP4_INPUT19 */ + 11, /* TRIGGER_TR_GROUP4_INPUT20 */ + 11, /* TRIGGER_TR_GROUP4_INPUT21 */ + 11, /* TRIGGER_TR_GROUP4_INPUT22 */ + 11, /* TRIGGER_TR_GROUP4_INPUT23 */ + 11, /* TRIGGER_TR_GROUP4_INPUT24 */ + 12, /* TRIGGER_TR_GROUP4_INPUT25 */ + 12, /* TRIGGER_TR_GROUP4_INPUT26 */ + 12, /* TRIGGER_TR_GROUP4_INPUT27 */ + 12, /* TRIGGER_TR_GROUP4_INPUT28 */ + 12, /* TRIGGER_TR_GROUP4_INPUT29 */ + 12, /* TRIGGER_TR_GROUP4_INPUT30 */ + 12, /* TRIGGER_TR_GROUP4_INPUT31 */ + 12, /* TRIGGER_TR_GROUP4_INPUT32 */ + 13, /* TRIGGER_TR_GROUP4_INPUT33 */ + 13, /* TRIGGER_TR_GROUP4_INPUT34 */ + 14, /* TRIGGER_TR_GROUP4_INPUT35 */ + 14, /* TRIGGER_TR_GROUP4_INPUT36 */ + 14, /* TRIGGER_TR_GROUP4_INPUT37 */ + 14, /* TRIGGER_TR_GROUP4_INPUT38 */ + 14, /* TRIGGER_TR_GROUP4_INPUT39 */ + 14, /* TRIGGER_TR_GROUP4_INPUT40 */ + 14, /* TRIGGER_TR_GROUP4_INPUT41 */ + 14, /* TRIGGER_TR_GROUP4_INPUT42 */ + 10, /* TRIGGER_TR_GROUP5_INPUT1 */ + 10, /* TRIGGER_TR_GROUP5_INPUT2 */ + 10, /* TRIGGER_TR_GROUP5_INPUT3 */ + 10, /* TRIGGER_TR_GROUP5_INPUT4 */ + 10, /* TRIGGER_TR_GROUP5_INPUT5 */ + 10, /* TRIGGER_TR_GROUP5_INPUT6 */ + 10, /* TRIGGER_TR_GROUP5_INPUT7 */ + 10, /* TRIGGER_TR_GROUP5_INPUT8 */ + 11, /* TRIGGER_TR_GROUP5_INPUT9 */ + 11, /* TRIGGER_TR_GROUP5_INPUT10 */ + 11, /* TRIGGER_TR_GROUP5_INPUT11 */ + 11, /* TRIGGER_TR_GROUP5_INPUT12 */ + 11, /* TRIGGER_TR_GROUP5_INPUT13 */ + 11, /* TRIGGER_TR_GROUP5_INPUT14 */ + 11, /* TRIGGER_TR_GROUP5_INPUT15 */ + 11, /* TRIGGER_TR_GROUP5_INPUT16 */ + 11, /* TRIGGER_TR_GROUP5_INPUT17 */ + 11, /* TRIGGER_TR_GROUP5_INPUT18 */ + 11, /* TRIGGER_TR_GROUP5_INPUT19 */ + 11, /* TRIGGER_TR_GROUP5_INPUT20 */ + 11, /* TRIGGER_TR_GROUP5_INPUT21 */ + 11, /* TRIGGER_TR_GROUP5_INPUT22 */ + 11, /* TRIGGER_TR_GROUP5_INPUT23 */ + 11, /* TRIGGER_TR_GROUP5_INPUT24 */ + 12, /* TRIGGER_TR_GROUP5_INPUT25 */ + 12, /* TRIGGER_TR_GROUP5_INPUT26 */ + 12, /* TRIGGER_TR_GROUP5_INPUT27 */ + 12, /* TRIGGER_TR_GROUP5_INPUT28 */ + 12, /* TRIGGER_TR_GROUP5_INPUT29 */ + 12, /* TRIGGER_TR_GROUP5_INPUT30 */ + 12, /* TRIGGER_TR_GROUP5_INPUT31 */ + 12, /* TRIGGER_TR_GROUP5_INPUT32 */ + 13, /* TRIGGER_TR_GROUP5_INPUT33 */ + 13, /* TRIGGER_TR_GROUP5_INPUT34 */ + 14, /* TRIGGER_TR_GROUP5_INPUT35 */ + 14, /* TRIGGER_TR_GROUP5_INPUT36 */ + 14, /* TRIGGER_TR_GROUP5_INPUT37 */ + 14, /* TRIGGER_TR_GROUP5_INPUT38 */ + 14, /* TRIGGER_TR_GROUP5_INPUT39 */ + 14, /* TRIGGER_TR_GROUP5_INPUT40 */ + 14, /* TRIGGER_TR_GROUP5_INPUT41 */ + 14, /* TRIGGER_TR_GROUP5_INPUT42 */ + 10, /* TRIGGER_TR_GROUP6_INPUT1 */ + 10, /* TRIGGER_TR_GROUP6_INPUT2 */ + 10, /* TRIGGER_TR_GROUP6_INPUT3 */ + 10, /* TRIGGER_TR_GROUP6_INPUT4 */ + 10, /* TRIGGER_TR_GROUP6_INPUT5 */ + 10, /* TRIGGER_TR_GROUP6_INPUT6 */ + 10, /* TRIGGER_TR_GROUP6_INPUT7 */ + 10, /* TRIGGER_TR_GROUP6_INPUT8 */ + 11, /* TRIGGER_TR_GROUP6_INPUT9 */ + 11, /* TRIGGER_TR_GROUP6_INPUT10 */ + 11, /* TRIGGER_TR_GROUP6_INPUT11 */ + 11, /* TRIGGER_TR_GROUP6_INPUT12 */ + 11, /* TRIGGER_TR_GROUP6_INPUT13 */ + 11, /* TRIGGER_TR_GROUP6_INPUT14 */ + 11, /* TRIGGER_TR_GROUP6_INPUT15 */ + 11, /* TRIGGER_TR_GROUP6_INPUT16 */ + 11, /* TRIGGER_TR_GROUP6_INPUT17 */ + 11, /* TRIGGER_TR_GROUP6_INPUT18 */ + 11, /* TRIGGER_TR_GROUP6_INPUT19 */ + 11, /* TRIGGER_TR_GROUP6_INPUT20 */ + 11, /* TRIGGER_TR_GROUP6_INPUT21 */ + 11, /* TRIGGER_TR_GROUP6_INPUT22 */ + 11, /* TRIGGER_TR_GROUP6_INPUT23 */ + 11, /* TRIGGER_TR_GROUP6_INPUT24 */ + 12, /* TRIGGER_TR_GROUP6_INPUT25 */ + 12, /* TRIGGER_TR_GROUP6_INPUT26 */ + 12, /* TRIGGER_TR_GROUP6_INPUT27 */ + 12, /* TRIGGER_TR_GROUP6_INPUT28 */ + 12, /* TRIGGER_TR_GROUP6_INPUT29 */ + 12, /* TRIGGER_TR_GROUP6_INPUT30 */ + 12, /* TRIGGER_TR_GROUP6_INPUT31 */ + 12, /* TRIGGER_TR_GROUP6_INPUT32 */ + 13, /* TRIGGER_TR_GROUP6_INPUT33 */ + 13, /* TRIGGER_TR_GROUP6_INPUT34 */ + 14, /* TRIGGER_TR_GROUP6_INPUT35 */ + 14, /* TRIGGER_TR_GROUP6_INPUT36 */ + 14, /* TRIGGER_TR_GROUP6_INPUT37 */ + 14, /* TRIGGER_TR_GROUP6_INPUT38 */ + 14, /* TRIGGER_TR_GROUP6_INPUT39 */ + 14, /* TRIGGER_TR_GROUP6_INPUT40 */ + 14, /* TRIGGER_TR_GROUP6_INPUT41 */ + 14, /* TRIGGER_TR_GROUP6_INPUT42 */ + 10, /* TRIGGER_TR_GROUP7_INPUT1 */ + 10, /* TRIGGER_TR_GROUP7_INPUT2 */ + 10, /* TRIGGER_TR_GROUP7_INPUT3 */ + 10, /* TRIGGER_TR_GROUP7_INPUT4 */ + 10, /* TRIGGER_TR_GROUP7_INPUT5 */ + 10, /* TRIGGER_TR_GROUP7_INPUT6 */ + 10, /* TRIGGER_TR_GROUP7_INPUT7 */ + 10, /* TRIGGER_TR_GROUP7_INPUT8 */ + 11, /* TRIGGER_TR_GROUP7_INPUT9 */ + 11, /* TRIGGER_TR_GROUP7_INPUT10 */ + 11, /* TRIGGER_TR_GROUP7_INPUT11 */ + 11, /* TRIGGER_TR_GROUP7_INPUT12 */ + 11, /* TRIGGER_TR_GROUP7_INPUT13 */ + 11, /* TRIGGER_TR_GROUP7_INPUT14 */ + 11, /* TRIGGER_TR_GROUP7_INPUT15 */ + 11, /* TRIGGER_TR_GROUP7_INPUT16 */ + 11, /* TRIGGER_TR_GROUP7_INPUT17 */ + 11, /* TRIGGER_TR_GROUP7_INPUT18 */ + 11, /* TRIGGER_TR_GROUP7_INPUT19 */ + 11, /* TRIGGER_TR_GROUP7_INPUT20 */ + 11, /* TRIGGER_TR_GROUP7_INPUT21 */ + 11, /* TRIGGER_TR_GROUP7_INPUT22 */ + 11, /* TRIGGER_TR_GROUP7_INPUT23 */ + 11, /* TRIGGER_TR_GROUP7_INPUT24 */ + 12, /* TRIGGER_TR_GROUP7_INPUT25 */ + 12, /* TRIGGER_TR_GROUP7_INPUT26 */ + 12, /* TRIGGER_TR_GROUP7_INPUT27 */ + 12, /* TRIGGER_TR_GROUP7_INPUT28 */ + 12, /* TRIGGER_TR_GROUP7_INPUT29 */ + 12, /* TRIGGER_TR_GROUP7_INPUT30 */ + 12, /* TRIGGER_TR_GROUP7_INPUT31 */ + 12, /* TRIGGER_TR_GROUP7_INPUT32 */ + 13, /* TRIGGER_TR_GROUP7_INPUT33 */ + 13, /* TRIGGER_TR_GROUP7_INPUT34 */ + 14, /* TRIGGER_TR_GROUP7_INPUT35 */ + 14, /* TRIGGER_TR_GROUP7_INPUT36 */ + 14, /* TRIGGER_TR_GROUP7_INPUT37 */ + 14, /* TRIGGER_TR_GROUP7_INPUT38 */ + 14, /* TRIGGER_TR_GROUP7_INPUT39 */ + 14, /* TRIGGER_TR_GROUP7_INPUT40 */ + 14, /* TRIGGER_TR_GROUP7_INPUT41 */ + 14, /* TRIGGER_TR_GROUP7_INPUT42 */ + 10, /* TRIGGER_TR_GROUP8_INPUT1 */ + 10, /* TRIGGER_TR_GROUP8_INPUT2 */ + 10, /* TRIGGER_TR_GROUP8_INPUT3 */ + 10, /* TRIGGER_TR_GROUP8_INPUT4 */ + 10, /* TRIGGER_TR_GROUP8_INPUT5 */ + 10, /* TRIGGER_TR_GROUP8_INPUT6 */ + 10, /* TRIGGER_TR_GROUP8_INPUT7 */ + 10, /* TRIGGER_TR_GROUP8_INPUT8 */ + 11, /* TRIGGER_TR_GROUP8_INPUT9 */ + 11, /* TRIGGER_TR_GROUP8_INPUT10 */ + 11, /* TRIGGER_TR_GROUP8_INPUT11 */ + 11, /* TRIGGER_TR_GROUP8_INPUT12 */ + 11, /* TRIGGER_TR_GROUP8_INPUT13 */ + 11, /* TRIGGER_TR_GROUP8_INPUT14 */ + 11, /* TRIGGER_TR_GROUP8_INPUT15 */ + 11, /* TRIGGER_TR_GROUP8_INPUT16 */ + 11, /* TRIGGER_TR_GROUP8_INPUT17 */ + 11, /* TRIGGER_TR_GROUP8_INPUT18 */ + 11, /* TRIGGER_TR_GROUP8_INPUT19 */ + 11, /* TRIGGER_TR_GROUP8_INPUT20 */ + 11, /* TRIGGER_TR_GROUP8_INPUT21 */ + 11, /* TRIGGER_TR_GROUP8_INPUT22 */ + 11, /* TRIGGER_TR_GROUP8_INPUT23 */ + 11, /* TRIGGER_TR_GROUP8_INPUT24 */ + 12, /* TRIGGER_TR_GROUP8_INPUT25 */ + 12, /* TRIGGER_TR_GROUP8_INPUT26 */ + 12, /* TRIGGER_TR_GROUP8_INPUT27 */ + 12, /* TRIGGER_TR_GROUP8_INPUT28 */ + 12, /* TRIGGER_TR_GROUP8_INPUT29 */ + 12, /* TRIGGER_TR_GROUP8_INPUT30 */ + 12, /* TRIGGER_TR_GROUP8_INPUT31 */ + 12, /* TRIGGER_TR_GROUP8_INPUT32 */ + 13, /* TRIGGER_TR_GROUP8_INPUT33 */ + 13, /* TRIGGER_TR_GROUP8_INPUT34 */ + 14, /* TRIGGER_TR_GROUP8_INPUT35 */ + 14, /* TRIGGER_TR_GROUP8_INPUT36 */ + 14, /* TRIGGER_TR_GROUP8_INPUT37 */ + 14, /* TRIGGER_TR_GROUP8_INPUT38 */ + 14, /* TRIGGER_TR_GROUP8_INPUT39 */ + 14, /* TRIGGER_TR_GROUP8_INPUT40 */ + 14, /* TRIGGER_TR_GROUP8_INPUT41 */ + 14, /* TRIGGER_TR_GROUP8_INPUT42 */ + 10, /* TRIGGER_UDB_TR_DW_ACK0 */ + 10, /* TRIGGER_UDB_TR_DW_ACK1 */ + 10, /* TRIGGER_UDB_TR_DW_ACK2 */ + 10, /* TRIGGER_UDB_TR_DW_ACK3 */ + 10, /* TRIGGER_UDB_TR_DW_ACK4 */ + 10, /* TRIGGER_UDB_TR_DW_ACK5 */ + 10, /* TRIGGER_UDB_TR_DW_ACK6 */ + 10, /* TRIGGER_UDB_TR_DW_ACK7 */ + 7, /* TRIGGER_UDB_TR_IN0 */ + 7, /* TRIGGER_UDB_TR_IN1 */ + 9, /* TRIGGER_USB_DMA_BURSTEND0 */ + 9, /* TRIGGER_USB_DMA_BURSTEND1 */ + 9, /* TRIGGER_USB_DMA_BURSTEND2 */ + 9, /* TRIGGER_USB_DMA_BURSTEND3 */ + 9, /* TRIGGER_USB_DMA_BURSTEND4 */ + 9, /* TRIGGER_USB_DMA_BURSTEND5 */ + 9, /* TRIGGER_USB_DMA_BURSTEND6 */ + 9, /* TRIGGER_USB_DMA_BURSTEND7 */ +}; + +const uint8_t cyhal_mux_dest_index[479] = +{ + 0, /* TRIGGER_CPUSS_CTI_TR_IN0 */ + 1, /* TRIGGER_CPUSS_CTI_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN3 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN4 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN5 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN6 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN7 */ + 8, /* TRIGGER_CPUSS_DW0_TR_IN8 */ + 9, /* TRIGGER_CPUSS_DW0_TR_IN9 */ + 10, /* TRIGGER_CPUSS_DW0_TR_IN10 */ + 11, /* TRIGGER_CPUSS_DW0_TR_IN11 */ + 12, /* TRIGGER_CPUSS_DW0_TR_IN12 */ + 13, /* TRIGGER_CPUSS_DW0_TR_IN13 */ + 14, /* TRIGGER_CPUSS_DW0_TR_IN14 */ + 15, /* TRIGGER_CPUSS_DW0_TR_IN15 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN3 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN4 */ + 5, /* TRIGGER_CPUSS_DW1_TR_IN5 */ + 6, /* TRIGGER_CPUSS_DW1_TR_IN6 */ + 7, /* TRIGGER_CPUSS_DW1_TR_IN7 */ + 8, /* TRIGGER_CPUSS_DW1_TR_IN8 */ + 9, /* TRIGGER_CPUSS_DW1_TR_IN9 */ + 10, /* TRIGGER_CPUSS_DW1_TR_IN10 */ + 11, /* TRIGGER_CPUSS_DW1_TR_IN11 */ + 12, /* TRIGGER_CPUSS_DW1_TR_IN12 */ + 13, /* TRIGGER_CPUSS_DW1_TR_IN13 */ + 14, /* TRIGGER_CPUSS_DW1_TR_IN14 */ + 15, /* TRIGGER_CPUSS_DW1_TR_IN15 */ + 0, /* TRIGGER_PASS_TR_SAR_IN */ + 0, /* TRIGGER_PERI_TR_IO_OUTPUT0 */ + 1, /* TRIGGER_PERI_TR_IO_OUTPUT1 */ + 0, /* TRIGGER_PROFILE_TR_START */ + 1, /* TRIGGER_PROFILE_TR_STOP */ + 0, /* TRIGGER_TCPWM0_TR_IN0 */ + 1, /* TRIGGER_TCPWM0_TR_IN1 */ + 2, /* TRIGGER_TCPWM0_TR_IN2 */ + 3, /* TRIGGER_TCPWM0_TR_IN3 */ + 4, /* TRIGGER_TCPWM0_TR_IN4 */ + 5, /* TRIGGER_TCPWM0_TR_IN5 */ + 6, /* TRIGGER_TCPWM0_TR_IN6 */ + 7, /* TRIGGER_TCPWM0_TR_IN7 */ + 8, /* TRIGGER_TCPWM0_TR_IN8 */ + 9, /* TRIGGER_TCPWM0_TR_IN9 */ + 10, /* TRIGGER_TCPWM0_TR_IN10 */ + 11, /* TRIGGER_TCPWM0_TR_IN11 */ + 12, /* TRIGGER_TCPWM0_TR_IN12 */ + 13, /* TRIGGER_TCPWM0_TR_IN13 */ + 0, /* TRIGGER_TCPWM1_TR_IN0 */ + 1, /* TRIGGER_TCPWM1_TR_IN1 */ + 2, /* TRIGGER_TCPWM1_TR_IN2 */ + 3, /* TRIGGER_TCPWM1_TR_IN3 */ + 4, /* TRIGGER_TCPWM1_TR_IN4 */ + 5, /* TRIGGER_TCPWM1_TR_IN5 */ + 6, /* TRIGGER_TCPWM1_TR_IN6 */ + 7, /* TRIGGER_TCPWM1_TR_IN7 */ + 8, /* TRIGGER_TCPWM1_TR_IN8 */ + 9, /* TRIGGER_TCPWM1_TR_IN9 */ + 10, /* TRIGGER_TCPWM1_TR_IN10 */ + 11, /* TRIGGER_TCPWM1_TR_IN11 */ + 12, /* TRIGGER_TCPWM1_TR_IN12 */ + 13, /* TRIGGER_TCPWM1_TR_IN13 */ + 0, /* TRIGGER_TR_GROUP0_INPUT1 */ + 1, /* TRIGGER_TR_GROUP0_INPUT2 */ + 2, /* TRIGGER_TR_GROUP0_INPUT3 */ + 3, /* TRIGGER_TR_GROUP0_INPUT4 */ + 4, /* TRIGGER_TR_GROUP0_INPUT5 */ + 5, /* TRIGGER_TR_GROUP0_INPUT6 */ + 6, /* TRIGGER_TR_GROUP0_INPUT7 */ + 7, /* TRIGGER_TR_GROUP0_INPUT8 */ + 0, /* TRIGGER_TR_GROUP0_INPUT9 */ + 1, /* TRIGGER_TR_GROUP0_INPUT10 */ + 2, /* TRIGGER_TR_GROUP0_INPUT11 */ + 3, /* TRIGGER_TR_GROUP0_INPUT12 */ + 4, /* TRIGGER_TR_GROUP0_INPUT13 */ + 5, /* TRIGGER_TR_GROUP0_INPUT14 */ + 6, /* TRIGGER_TR_GROUP0_INPUT15 */ + 7, /* TRIGGER_TR_GROUP0_INPUT16 */ + 8, /* TRIGGER_TR_GROUP0_INPUT17 */ + 9, /* TRIGGER_TR_GROUP0_INPUT18 */ + 10, /* TRIGGER_TR_GROUP0_INPUT19 */ + 11, /* TRIGGER_TR_GROUP0_INPUT20 */ + 12, /* TRIGGER_TR_GROUP0_INPUT21 */ + 13, /* TRIGGER_TR_GROUP0_INPUT22 */ + 14, /* TRIGGER_TR_GROUP0_INPUT23 */ + 15, /* TRIGGER_TR_GROUP0_INPUT24 */ + 8, /* TRIGGER_TR_GROUP0_INPUT25 */ + 9, /* TRIGGER_TR_GROUP0_INPUT26 */ + 0, /* TRIGGER_TR_GROUP0_INPUT27 */ + 1, /* TRIGGER_TR_GROUP0_INPUT28 */ + 2, /* TRIGGER_TR_GROUP0_INPUT29 */ + 3, /* TRIGGER_TR_GROUP0_INPUT30 */ + 4, /* TRIGGER_TR_GROUP0_INPUT31 */ + 5, /* TRIGGER_TR_GROUP0_INPUT32 */ + 6, /* TRIGGER_TR_GROUP0_INPUT33 */ + 7, /* TRIGGER_TR_GROUP0_INPUT34 */ + 8, /* TRIGGER_TR_GROUP0_INPUT35 */ + 9, /* TRIGGER_TR_GROUP0_INPUT36 */ + 10, /* TRIGGER_TR_GROUP0_INPUT37 */ + 11, /* TRIGGER_TR_GROUP0_INPUT38 */ + 12, /* TRIGGER_TR_GROUP0_INPUT39 */ + 13, /* TRIGGER_TR_GROUP0_INPUT40 */ + 14, /* TRIGGER_TR_GROUP0_INPUT41 */ + 15, /* TRIGGER_TR_GROUP0_INPUT42 */ + 0, /* TRIGGER_TR_GROUP0_INPUT43 */ + 1, /* TRIGGER_TR_GROUP0_INPUT44 */ + 2, /* TRIGGER_TR_GROUP0_INPUT45 */ + 3, /* TRIGGER_TR_GROUP0_INPUT46 */ + 4, /* TRIGGER_TR_GROUP0_INPUT47 */ + 5, /* TRIGGER_TR_GROUP0_INPUT48 */ + 6, /* TRIGGER_TR_GROUP0_INPUT49 */ + 7, /* TRIGGER_TR_GROUP0_INPUT50 */ + 0, /* TRIGGER_TR_GROUP1_INPUT1 */ + 1, /* TRIGGER_TR_GROUP1_INPUT2 */ + 2, /* TRIGGER_TR_GROUP1_INPUT3 */ + 3, /* TRIGGER_TR_GROUP1_INPUT4 */ + 4, /* TRIGGER_TR_GROUP1_INPUT5 */ + 5, /* TRIGGER_TR_GROUP1_INPUT6 */ + 6, /* TRIGGER_TR_GROUP1_INPUT7 */ + 7, /* TRIGGER_TR_GROUP1_INPUT8 */ + 0, /* TRIGGER_TR_GROUP1_INPUT9 */ + 1, /* TRIGGER_TR_GROUP1_INPUT10 */ + 2, /* TRIGGER_TR_GROUP1_INPUT11 */ + 3, /* TRIGGER_TR_GROUP1_INPUT12 */ + 4, /* TRIGGER_TR_GROUP1_INPUT13 */ + 5, /* TRIGGER_TR_GROUP1_INPUT14 */ + 6, /* TRIGGER_TR_GROUP1_INPUT15 */ + 7, /* TRIGGER_TR_GROUP1_INPUT16 */ + 8, /* TRIGGER_TR_GROUP1_INPUT17 */ + 9, /* TRIGGER_TR_GROUP1_INPUT18 */ + 10, /* TRIGGER_TR_GROUP1_INPUT19 */ + 11, /* TRIGGER_TR_GROUP1_INPUT20 */ + 12, /* TRIGGER_TR_GROUP1_INPUT21 */ + 13, /* TRIGGER_TR_GROUP1_INPUT22 */ + 14, /* TRIGGER_TR_GROUP1_INPUT23 */ + 15, /* TRIGGER_TR_GROUP1_INPUT24 */ + 8, /* TRIGGER_TR_GROUP1_INPUT25 */ + 9, /* TRIGGER_TR_GROUP1_INPUT26 */ + 0, /* TRIGGER_TR_GROUP1_INPUT27 */ + 1, /* TRIGGER_TR_GROUP1_INPUT28 */ + 2, /* TRIGGER_TR_GROUP1_INPUT29 */ + 3, /* TRIGGER_TR_GROUP1_INPUT30 */ + 4, /* TRIGGER_TR_GROUP1_INPUT31 */ + 5, /* TRIGGER_TR_GROUP1_INPUT32 */ + 6, /* TRIGGER_TR_GROUP1_INPUT33 */ + 7, /* TRIGGER_TR_GROUP1_INPUT34 */ + 8, /* TRIGGER_TR_GROUP1_INPUT35 */ + 9, /* TRIGGER_TR_GROUP1_INPUT36 */ + 10, /* TRIGGER_TR_GROUP1_INPUT37 */ + 11, /* TRIGGER_TR_GROUP1_INPUT38 */ + 12, /* TRIGGER_TR_GROUP1_INPUT39 */ + 13, /* TRIGGER_TR_GROUP1_INPUT40 */ + 14, /* TRIGGER_TR_GROUP1_INPUT41 */ + 15, /* TRIGGER_TR_GROUP1_INPUT42 */ + 0, /* TRIGGER_TR_GROUP1_INPUT43 */ + 1, /* TRIGGER_TR_GROUP1_INPUT44 */ + 2, /* TRIGGER_TR_GROUP1_INPUT45 */ + 3, /* TRIGGER_TR_GROUP1_INPUT46 */ + 4, /* TRIGGER_TR_GROUP1_INPUT47 */ + 5, /* TRIGGER_TR_GROUP1_INPUT48 */ + 6, /* TRIGGER_TR_GROUP1_INPUT49 */ + 7, /* TRIGGER_TR_GROUP1_INPUT50 */ + 0, /* TRIGGER_TR_GROUP2_INPUT1 */ + 1, /* TRIGGER_TR_GROUP2_INPUT2 */ + 2, /* TRIGGER_TR_GROUP2_INPUT3 */ + 3, /* TRIGGER_TR_GROUP2_INPUT4 */ + 4, /* TRIGGER_TR_GROUP2_INPUT5 */ + 5, /* TRIGGER_TR_GROUP2_INPUT6 */ + 6, /* TRIGGER_TR_GROUP2_INPUT7 */ + 7, /* TRIGGER_TR_GROUP2_INPUT8 */ + 0, /* TRIGGER_TR_GROUP2_INPUT9 */ + 1, /* TRIGGER_TR_GROUP2_INPUT10 */ + 2, /* TRIGGER_TR_GROUP2_INPUT11 */ + 3, /* TRIGGER_TR_GROUP2_INPUT12 */ + 4, /* TRIGGER_TR_GROUP2_INPUT13 */ + 5, /* TRIGGER_TR_GROUP2_INPUT14 */ + 6, /* TRIGGER_TR_GROUP2_INPUT15 */ + 7, /* TRIGGER_TR_GROUP2_INPUT16 */ + 8, /* TRIGGER_TR_GROUP2_INPUT17 */ + 9, /* TRIGGER_TR_GROUP2_INPUT18 */ + 10, /* TRIGGER_TR_GROUP2_INPUT19 */ + 11, /* TRIGGER_TR_GROUP2_INPUT20 */ + 12, /* TRIGGER_TR_GROUP2_INPUT21 */ + 13, /* TRIGGER_TR_GROUP2_INPUT22 */ + 14, /* TRIGGER_TR_GROUP2_INPUT23 */ + 15, /* TRIGGER_TR_GROUP2_INPUT24 */ + 0, /* TRIGGER_TR_GROUP2_INPUT25 */ + 1, /* TRIGGER_TR_GROUP2_INPUT26 */ + 2, /* TRIGGER_TR_GROUP2_INPUT27 */ + 3, /* TRIGGER_TR_GROUP2_INPUT28 */ + 4, /* TRIGGER_TR_GROUP2_INPUT29 */ + 5, /* TRIGGER_TR_GROUP2_INPUT30 */ + 6, /* TRIGGER_TR_GROUP2_INPUT31 */ + 7, /* TRIGGER_TR_GROUP2_INPUT32 */ + 16, /* TRIGGER_TR_GROUP2_INPUT33 */ + 17, /* TRIGGER_TR_GROUP2_INPUT34 */ + 8, /* TRIGGER_TR_GROUP2_INPUT35 */ + 9, /* TRIGGER_TR_GROUP2_INPUT36 */ + 10, /* TRIGGER_TR_GROUP2_INPUT37 */ + 11, /* TRIGGER_TR_GROUP2_INPUT38 */ + 12, /* TRIGGER_TR_GROUP2_INPUT39 */ + 13, /* TRIGGER_TR_GROUP2_INPUT40 */ + 14, /* TRIGGER_TR_GROUP2_INPUT41 */ + 15, /* TRIGGER_TR_GROUP2_INPUT42 */ + 0, /* TRIGGER_TR_GROUP3_INPUT1 */ + 1, /* TRIGGER_TR_GROUP3_INPUT2 */ + 2, /* TRIGGER_TR_GROUP3_INPUT3 */ + 3, /* TRIGGER_TR_GROUP3_INPUT4 */ + 4, /* TRIGGER_TR_GROUP3_INPUT5 */ + 5, /* TRIGGER_TR_GROUP3_INPUT6 */ + 6, /* TRIGGER_TR_GROUP3_INPUT7 */ + 7, /* TRIGGER_TR_GROUP3_INPUT8 */ + 0, /* TRIGGER_TR_GROUP3_INPUT9 */ + 1, /* TRIGGER_TR_GROUP3_INPUT10 */ + 2, /* TRIGGER_TR_GROUP3_INPUT11 */ + 3, /* TRIGGER_TR_GROUP3_INPUT12 */ + 4, /* TRIGGER_TR_GROUP3_INPUT13 */ + 5, /* TRIGGER_TR_GROUP3_INPUT14 */ + 6, /* TRIGGER_TR_GROUP3_INPUT15 */ + 7, /* TRIGGER_TR_GROUP3_INPUT16 */ + 8, /* TRIGGER_TR_GROUP3_INPUT17 */ + 9, /* TRIGGER_TR_GROUP3_INPUT18 */ + 10, /* TRIGGER_TR_GROUP3_INPUT19 */ + 11, /* TRIGGER_TR_GROUP3_INPUT20 */ + 12, /* TRIGGER_TR_GROUP3_INPUT21 */ + 13, /* TRIGGER_TR_GROUP3_INPUT22 */ + 14, /* TRIGGER_TR_GROUP3_INPUT23 */ + 15, /* TRIGGER_TR_GROUP3_INPUT24 */ + 0, /* TRIGGER_TR_GROUP3_INPUT25 */ + 1, /* TRIGGER_TR_GROUP3_INPUT26 */ + 2, /* TRIGGER_TR_GROUP3_INPUT27 */ + 3, /* TRIGGER_TR_GROUP3_INPUT28 */ + 4, /* TRIGGER_TR_GROUP3_INPUT29 */ + 5, /* TRIGGER_TR_GROUP3_INPUT30 */ + 6, /* TRIGGER_TR_GROUP3_INPUT31 */ + 7, /* TRIGGER_TR_GROUP3_INPUT32 */ + 16, /* TRIGGER_TR_GROUP3_INPUT33 */ + 17, /* TRIGGER_TR_GROUP3_INPUT34 */ + 8, /* TRIGGER_TR_GROUP3_INPUT35 */ + 9, /* TRIGGER_TR_GROUP3_INPUT36 */ + 10, /* TRIGGER_TR_GROUP3_INPUT37 */ + 11, /* TRIGGER_TR_GROUP3_INPUT38 */ + 12, /* TRIGGER_TR_GROUP3_INPUT39 */ + 13, /* TRIGGER_TR_GROUP3_INPUT40 */ + 14, /* TRIGGER_TR_GROUP3_INPUT41 */ + 15, /* TRIGGER_TR_GROUP3_INPUT42 */ + 0, /* TRIGGER_TR_GROUP4_INPUT1 */ + 1, /* TRIGGER_TR_GROUP4_INPUT2 */ + 2, /* TRIGGER_TR_GROUP4_INPUT3 */ + 3, /* TRIGGER_TR_GROUP4_INPUT4 */ + 4, /* TRIGGER_TR_GROUP4_INPUT5 */ + 5, /* TRIGGER_TR_GROUP4_INPUT6 */ + 6, /* TRIGGER_TR_GROUP4_INPUT7 */ + 7, /* TRIGGER_TR_GROUP4_INPUT8 */ + 0, /* TRIGGER_TR_GROUP4_INPUT9 */ + 1, /* TRIGGER_TR_GROUP4_INPUT10 */ + 2, /* TRIGGER_TR_GROUP4_INPUT11 */ + 3, /* TRIGGER_TR_GROUP4_INPUT12 */ + 4, /* TRIGGER_TR_GROUP4_INPUT13 */ + 5, /* TRIGGER_TR_GROUP4_INPUT14 */ + 6, /* TRIGGER_TR_GROUP4_INPUT15 */ + 7, /* TRIGGER_TR_GROUP4_INPUT16 */ + 8, /* TRIGGER_TR_GROUP4_INPUT17 */ + 9, /* TRIGGER_TR_GROUP4_INPUT18 */ + 10, /* TRIGGER_TR_GROUP4_INPUT19 */ + 11, /* TRIGGER_TR_GROUP4_INPUT20 */ + 12, /* TRIGGER_TR_GROUP4_INPUT21 */ + 13, /* TRIGGER_TR_GROUP4_INPUT22 */ + 14, /* TRIGGER_TR_GROUP4_INPUT23 */ + 15, /* TRIGGER_TR_GROUP4_INPUT24 */ + 0, /* TRIGGER_TR_GROUP4_INPUT25 */ + 1, /* TRIGGER_TR_GROUP4_INPUT26 */ + 2, /* TRIGGER_TR_GROUP4_INPUT27 */ + 3, /* TRIGGER_TR_GROUP4_INPUT28 */ + 4, /* TRIGGER_TR_GROUP4_INPUT29 */ + 5, /* TRIGGER_TR_GROUP4_INPUT30 */ + 6, /* TRIGGER_TR_GROUP4_INPUT31 */ + 7, /* TRIGGER_TR_GROUP4_INPUT32 */ + 16, /* TRIGGER_TR_GROUP4_INPUT33 */ + 17, /* TRIGGER_TR_GROUP4_INPUT34 */ + 8, /* TRIGGER_TR_GROUP4_INPUT35 */ + 9, /* TRIGGER_TR_GROUP4_INPUT36 */ + 10, /* TRIGGER_TR_GROUP4_INPUT37 */ + 11, /* TRIGGER_TR_GROUP4_INPUT38 */ + 12, /* TRIGGER_TR_GROUP4_INPUT39 */ + 13, /* TRIGGER_TR_GROUP4_INPUT40 */ + 14, /* TRIGGER_TR_GROUP4_INPUT41 */ + 15, /* TRIGGER_TR_GROUP4_INPUT42 */ + 0, /* TRIGGER_TR_GROUP5_INPUT1 */ + 1, /* TRIGGER_TR_GROUP5_INPUT2 */ + 2, /* TRIGGER_TR_GROUP5_INPUT3 */ + 3, /* TRIGGER_TR_GROUP5_INPUT4 */ + 4, /* TRIGGER_TR_GROUP5_INPUT5 */ + 5, /* TRIGGER_TR_GROUP5_INPUT6 */ + 6, /* TRIGGER_TR_GROUP5_INPUT7 */ + 7, /* TRIGGER_TR_GROUP5_INPUT8 */ + 0, /* TRIGGER_TR_GROUP5_INPUT9 */ + 1, /* TRIGGER_TR_GROUP5_INPUT10 */ + 2, /* TRIGGER_TR_GROUP5_INPUT11 */ + 3, /* TRIGGER_TR_GROUP5_INPUT12 */ + 4, /* TRIGGER_TR_GROUP5_INPUT13 */ + 5, /* TRIGGER_TR_GROUP5_INPUT14 */ + 6, /* TRIGGER_TR_GROUP5_INPUT15 */ + 7, /* TRIGGER_TR_GROUP5_INPUT16 */ + 8, /* TRIGGER_TR_GROUP5_INPUT17 */ + 9, /* TRIGGER_TR_GROUP5_INPUT18 */ + 10, /* TRIGGER_TR_GROUP5_INPUT19 */ + 11, /* TRIGGER_TR_GROUP5_INPUT20 */ + 12, /* TRIGGER_TR_GROUP5_INPUT21 */ + 13, /* TRIGGER_TR_GROUP5_INPUT22 */ + 14, /* TRIGGER_TR_GROUP5_INPUT23 */ + 15, /* TRIGGER_TR_GROUP5_INPUT24 */ + 0, /* TRIGGER_TR_GROUP5_INPUT25 */ + 1, /* TRIGGER_TR_GROUP5_INPUT26 */ + 2, /* TRIGGER_TR_GROUP5_INPUT27 */ + 3, /* TRIGGER_TR_GROUP5_INPUT28 */ + 4, /* TRIGGER_TR_GROUP5_INPUT29 */ + 5, /* TRIGGER_TR_GROUP5_INPUT30 */ + 6, /* TRIGGER_TR_GROUP5_INPUT31 */ + 7, /* TRIGGER_TR_GROUP5_INPUT32 */ + 16, /* TRIGGER_TR_GROUP5_INPUT33 */ + 17, /* TRIGGER_TR_GROUP5_INPUT34 */ + 8, /* TRIGGER_TR_GROUP5_INPUT35 */ + 9, /* TRIGGER_TR_GROUP5_INPUT36 */ + 10, /* TRIGGER_TR_GROUP5_INPUT37 */ + 11, /* TRIGGER_TR_GROUP5_INPUT38 */ + 12, /* TRIGGER_TR_GROUP5_INPUT39 */ + 13, /* TRIGGER_TR_GROUP5_INPUT40 */ + 14, /* TRIGGER_TR_GROUP5_INPUT41 */ + 15, /* TRIGGER_TR_GROUP5_INPUT42 */ + 0, /* TRIGGER_TR_GROUP6_INPUT1 */ + 1, /* TRIGGER_TR_GROUP6_INPUT2 */ + 2, /* TRIGGER_TR_GROUP6_INPUT3 */ + 3, /* TRIGGER_TR_GROUP6_INPUT4 */ + 4, /* TRIGGER_TR_GROUP6_INPUT5 */ + 5, /* TRIGGER_TR_GROUP6_INPUT6 */ + 6, /* TRIGGER_TR_GROUP6_INPUT7 */ + 7, /* TRIGGER_TR_GROUP6_INPUT8 */ + 0, /* TRIGGER_TR_GROUP6_INPUT9 */ + 1, /* TRIGGER_TR_GROUP6_INPUT10 */ + 2, /* TRIGGER_TR_GROUP6_INPUT11 */ + 3, /* TRIGGER_TR_GROUP6_INPUT12 */ + 4, /* TRIGGER_TR_GROUP6_INPUT13 */ + 5, /* TRIGGER_TR_GROUP6_INPUT14 */ + 6, /* TRIGGER_TR_GROUP6_INPUT15 */ + 7, /* TRIGGER_TR_GROUP6_INPUT16 */ + 8, /* TRIGGER_TR_GROUP6_INPUT17 */ + 9, /* TRIGGER_TR_GROUP6_INPUT18 */ + 10, /* TRIGGER_TR_GROUP6_INPUT19 */ + 11, /* TRIGGER_TR_GROUP6_INPUT20 */ + 12, /* TRIGGER_TR_GROUP6_INPUT21 */ + 13, /* TRIGGER_TR_GROUP6_INPUT22 */ + 14, /* TRIGGER_TR_GROUP6_INPUT23 */ + 15, /* TRIGGER_TR_GROUP6_INPUT24 */ + 0, /* TRIGGER_TR_GROUP6_INPUT25 */ + 1, /* TRIGGER_TR_GROUP6_INPUT26 */ + 2, /* TRIGGER_TR_GROUP6_INPUT27 */ + 3, /* TRIGGER_TR_GROUP6_INPUT28 */ + 4, /* TRIGGER_TR_GROUP6_INPUT29 */ + 5, /* TRIGGER_TR_GROUP6_INPUT30 */ + 6, /* TRIGGER_TR_GROUP6_INPUT31 */ + 7, /* TRIGGER_TR_GROUP6_INPUT32 */ + 16, /* TRIGGER_TR_GROUP6_INPUT33 */ + 17, /* TRIGGER_TR_GROUP6_INPUT34 */ + 8, /* TRIGGER_TR_GROUP6_INPUT35 */ + 9, /* TRIGGER_TR_GROUP6_INPUT36 */ + 10, /* TRIGGER_TR_GROUP6_INPUT37 */ + 11, /* TRIGGER_TR_GROUP6_INPUT38 */ + 12, /* TRIGGER_TR_GROUP6_INPUT39 */ + 13, /* TRIGGER_TR_GROUP6_INPUT40 */ + 14, /* TRIGGER_TR_GROUP6_INPUT41 */ + 15, /* TRIGGER_TR_GROUP6_INPUT42 */ + 0, /* TRIGGER_TR_GROUP7_INPUT1 */ + 1, /* TRIGGER_TR_GROUP7_INPUT2 */ + 2, /* TRIGGER_TR_GROUP7_INPUT3 */ + 3, /* TRIGGER_TR_GROUP7_INPUT4 */ + 4, /* TRIGGER_TR_GROUP7_INPUT5 */ + 5, /* TRIGGER_TR_GROUP7_INPUT6 */ + 6, /* TRIGGER_TR_GROUP7_INPUT7 */ + 7, /* TRIGGER_TR_GROUP7_INPUT8 */ + 0, /* TRIGGER_TR_GROUP7_INPUT9 */ + 1, /* TRIGGER_TR_GROUP7_INPUT10 */ + 2, /* TRIGGER_TR_GROUP7_INPUT11 */ + 3, /* TRIGGER_TR_GROUP7_INPUT12 */ + 4, /* TRIGGER_TR_GROUP7_INPUT13 */ + 5, /* TRIGGER_TR_GROUP7_INPUT14 */ + 6, /* TRIGGER_TR_GROUP7_INPUT15 */ + 7, /* TRIGGER_TR_GROUP7_INPUT16 */ + 8, /* TRIGGER_TR_GROUP7_INPUT17 */ + 9, /* TRIGGER_TR_GROUP7_INPUT18 */ + 10, /* TRIGGER_TR_GROUP7_INPUT19 */ + 11, /* TRIGGER_TR_GROUP7_INPUT20 */ + 12, /* TRIGGER_TR_GROUP7_INPUT21 */ + 13, /* TRIGGER_TR_GROUP7_INPUT22 */ + 14, /* TRIGGER_TR_GROUP7_INPUT23 */ + 15, /* TRIGGER_TR_GROUP7_INPUT24 */ + 0, /* TRIGGER_TR_GROUP7_INPUT25 */ + 1, /* TRIGGER_TR_GROUP7_INPUT26 */ + 2, /* TRIGGER_TR_GROUP7_INPUT27 */ + 3, /* TRIGGER_TR_GROUP7_INPUT28 */ + 4, /* TRIGGER_TR_GROUP7_INPUT29 */ + 5, /* TRIGGER_TR_GROUP7_INPUT30 */ + 6, /* TRIGGER_TR_GROUP7_INPUT31 */ + 7, /* TRIGGER_TR_GROUP7_INPUT32 */ + 16, /* TRIGGER_TR_GROUP7_INPUT33 */ + 17, /* TRIGGER_TR_GROUP7_INPUT34 */ + 8, /* TRIGGER_TR_GROUP7_INPUT35 */ + 9, /* TRIGGER_TR_GROUP7_INPUT36 */ + 10, /* TRIGGER_TR_GROUP7_INPUT37 */ + 11, /* TRIGGER_TR_GROUP7_INPUT38 */ + 12, /* TRIGGER_TR_GROUP7_INPUT39 */ + 13, /* TRIGGER_TR_GROUP7_INPUT40 */ + 14, /* TRIGGER_TR_GROUP7_INPUT41 */ + 15, /* TRIGGER_TR_GROUP7_INPUT42 */ + 0, /* TRIGGER_TR_GROUP8_INPUT1 */ + 1, /* TRIGGER_TR_GROUP8_INPUT2 */ + 2, /* TRIGGER_TR_GROUP8_INPUT3 */ + 3, /* TRIGGER_TR_GROUP8_INPUT4 */ + 4, /* TRIGGER_TR_GROUP8_INPUT5 */ + 5, /* TRIGGER_TR_GROUP8_INPUT6 */ + 6, /* TRIGGER_TR_GROUP8_INPUT7 */ + 7, /* TRIGGER_TR_GROUP8_INPUT8 */ + 0, /* TRIGGER_TR_GROUP8_INPUT9 */ + 1, /* TRIGGER_TR_GROUP8_INPUT10 */ + 2, /* TRIGGER_TR_GROUP8_INPUT11 */ + 3, /* TRIGGER_TR_GROUP8_INPUT12 */ + 4, /* TRIGGER_TR_GROUP8_INPUT13 */ + 5, /* TRIGGER_TR_GROUP8_INPUT14 */ + 6, /* TRIGGER_TR_GROUP8_INPUT15 */ + 7, /* TRIGGER_TR_GROUP8_INPUT16 */ + 8, /* TRIGGER_TR_GROUP8_INPUT17 */ + 9, /* TRIGGER_TR_GROUP8_INPUT18 */ + 10, /* TRIGGER_TR_GROUP8_INPUT19 */ + 11, /* TRIGGER_TR_GROUP8_INPUT20 */ + 12, /* TRIGGER_TR_GROUP8_INPUT21 */ + 13, /* TRIGGER_TR_GROUP8_INPUT22 */ + 14, /* TRIGGER_TR_GROUP8_INPUT23 */ + 15, /* TRIGGER_TR_GROUP8_INPUT24 */ + 0, /* TRIGGER_TR_GROUP8_INPUT25 */ + 1, /* TRIGGER_TR_GROUP8_INPUT26 */ + 2, /* TRIGGER_TR_GROUP8_INPUT27 */ + 3, /* TRIGGER_TR_GROUP8_INPUT28 */ + 4, /* TRIGGER_TR_GROUP8_INPUT29 */ + 5, /* TRIGGER_TR_GROUP8_INPUT30 */ + 6, /* TRIGGER_TR_GROUP8_INPUT31 */ + 7, /* TRIGGER_TR_GROUP8_INPUT32 */ + 16, /* TRIGGER_TR_GROUP8_INPUT33 */ + 17, /* TRIGGER_TR_GROUP8_INPUT34 */ + 8, /* TRIGGER_TR_GROUP8_INPUT35 */ + 9, /* TRIGGER_TR_GROUP8_INPUT36 */ + 10, /* TRIGGER_TR_GROUP8_INPUT37 */ + 11, /* TRIGGER_TR_GROUP8_INPUT38 */ + 12, /* TRIGGER_TR_GROUP8_INPUT39 */ + 13, /* TRIGGER_TR_GROUP8_INPUT40 */ + 14, /* TRIGGER_TR_GROUP8_INPUT41 */ + 15, /* TRIGGER_TR_GROUP8_INPUT42 */ + 0, /* TRIGGER_UDB_TR_DW_ACK0 */ + 1, /* TRIGGER_UDB_TR_DW_ACK1 */ + 2, /* TRIGGER_UDB_TR_DW_ACK2 */ + 3, /* TRIGGER_UDB_TR_DW_ACK3 */ + 4, /* TRIGGER_UDB_TR_DW_ACK4 */ + 5, /* TRIGGER_UDB_TR_DW_ACK5 */ + 6, /* TRIGGER_UDB_TR_DW_ACK6 */ + 7, /* TRIGGER_UDB_TR_DW_ACK7 */ + 0, /* TRIGGER_UDB_TR_IN0 */ + 1, /* TRIGGER_UDB_TR_IN1 */ + 0, /* TRIGGER_USB_DMA_BURSTEND0 */ + 1, /* TRIGGER_USB_DMA_BURSTEND1 */ + 2, /* TRIGGER_USB_DMA_BURSTEND2 */ + 3, /* TRIGGER_USB_DMA_BURSTEND3 */ + 4, /* TRIGGER_USB_DMA_BURSTEND4 */ + 5, /* TRIGGER_USB_DMA_BURSTEND5 */ + 6, /* TRIGGER_USB_DMA_BURSTEND6 */ + 7, /* TRIGGER_USB_DMA_BURSTEND7 */ +}; +#endif /* CY_DEVICE_PSOC6ABLE2 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_02.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_02.c new file mode 100644 index 0000000000..7ee8b54015 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_02.c @@ -0,0 +1,255 @@ +/***************************************************************************//** +* \file cyhal_triggers_psoc6_02.c +* +* \brief +* PSoC6_02 family HAL triggers header +* +* \note +* Generator version: 1.5.7254.19579 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cy_device_headers.h" +#include "cyhal_hw_types.h" + +#ifdef CY_DEVICE_PSOC6A2M +#include "triggers/cyhal_triggers_psoc6_02.h" + +const uint8_t cyhal_dest_to_mux[107] = +{ + 5, /* TRIGGER_CPUSS_CTI_TR_IN0 */ + 5, /* TRIGGER_CPUSS_CTI_TR_IN1 */ + 6, /* TRIGGER_CPUSS_DMAC_TR_IN0 */ + 6, /* TRIGGER_CPUSS_DMAC_TR_IN1 */ + 6, /* TRIGGER_CPUSS_DMAC_TR_IN2 */ + 6, /* TRIGGER_CPUSS_DMAC_TR_IN3 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN0 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN2 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN3 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN4 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN5 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN6 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN7 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN8 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN9 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN10 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN11 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN12 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN13 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN14 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN15 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN16 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN17 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN18 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN19 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN20 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN21 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN22 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN23 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN24 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN25 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN26 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN27 */ + 130, /* TRIGGER_CPUSS_DW0_TR_IN28 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN1 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN2 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN3 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN4 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN5 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN6 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN7 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN8 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN9 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN10 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN11 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN12 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN13 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN14 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN15 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN16 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN17 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN18 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN19 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN20 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN21 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN22 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN23 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN24 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN25 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN26 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN27 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN28 */ + 8, /* TRIGGER_CSD_DSI_START */ + 9, /* TRIGGER_PASS_TR_SAR_IN */ + 7, /* TRIGGER_PERI_TR_DBG_FREEZE */ + 4, /* TRIGGER_PERI_TR_IO_OUTPUT0 */ + 4, /* TRIGGER_PERI_TR_IO_OUTPUT1 */ + 5, /* TRIGGER_PROFILE_TR_START */ + 5, /* TRIGGER_PROFILE_TR_STOP */ + 2, /* TRIGGER_TCPWM0_TR_IN0 */ + 2, /* TRIGGER_TCPWM0_TR_IN1 */ + 2, /* TRIGGER_TCPWM0_TR_IN2 */ + 2, /* TRIGGER_TCPWM0_TR_IN3 */ + 2, /* TRIGGER_TCPWM0_TR_IN4 */ + 2, /* TRIGGER_TCPWM0_TR_IN5 */ + 2, /* TRIGGER_TCPWM0_TR_IN6 */ + 2, /* TRIGGER_TCPWM0_TR_IN7 */ + 2, /* TRIGGER_TCPWM0_TR_IN8 */ + 2, /* TRIGGER_TCPWM0_TR_IN9 */ + 2, /* TRIGGER_TCPWM0_TR_IN10 */ + 2, /* TRIGGER_TCPWM0_TR_IN11 */ + 2, /* TRIGGER_TCPWM0_TR_IN12 */ + 2, /* TRIGGER_TCPWM0_TR_IN13 */ + 3, /* TRIGGER_TCPWM1_TR_IN0 */ + 3, /* TRIGGER_TCPWM1_TR_IN1 */ + 3, /* TRIGGER_TCPWM1_TR_IN2 */ + 3, /* TRIGGER_TCPWM1_TR_IN3 */ + 3, /* TRIGGER_TCPWM1_TR_IN4 */ + 3, /* TRIGGER_TCPWM1_TR_IN5 */ + 3, /* TRIGGER_TCPWM1_TR_IN6 */ + 3, /* TRIGGER_TCPWM1_TR_IN7 */ + 3, /* TRIGGER_TCPWM1_TR_IN8 */ + 3, /* TRIGGER_TCPWM1_TR_IN9 */ + 3, /* TRIGGER_TCPWM1_TR_IN10 */ + 3, /* TRIGGER_TCPWM1_TR_IN11 */ + 3, /* TRIGGER_TCPWM1_TR_IN12 */ + 3, /* TRIGGER_TCPWM1_TR_IN13 */ + 134, /* TRIGGER_USB_DMA_BURSTEND0 */ + 134, /* TRIGGER_USB_DMA_BURSTEND1 */ + 134, /* TRIGGER_USB_DMA_BURSTEND2 */ + 134, /* TRIGGER_USB_DMA_BURSTEND3 */ + 134, /* TRIGGER_USB_DMA_BURSTEND4 */ + 134, /* TRIGGER_USB_DMA_BURSTEND5 */ + 134, /* TRIGGER_USB_DMA_BURSTEND6 */ + 134, /* TRIGGER_USB_DMA_BURSTEND7 */ +}; + +const uint8_t cyhal_mux_dest_index[107] = +{ + 0, /* TRIGGER_CPUSS_CTI_TR_IN0 */ + 1, /* TRIGGER_CPUSS_CTI_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DMAC_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DMAC_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DMAC_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DMAC_TR_IN3 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN3 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN4 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN5 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN6 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN7 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN8 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN9 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN10 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN11 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN12 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN13 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN14 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN15 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN16 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN17 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN18 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN19 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN20 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN21 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN22 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN23 */ + 8, /* TRIGGER_CPUSS_DW0_TR_IN24 */ + 9, /* TRIGGER_CPUSS_DW0_TR_IN25 */ + 10, /* TRIGGER_CPUSS_DW0_TR_IN26 */ + 11, /* TRIGGER_CPUSS_DW0_TR_IN27 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN28 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN3 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN4 */ + 5, /* TRIGGER_CPUSS_DW1_TR_IN5 */ + 6, /* TRIGGER_CPUSS_DW1_TR_IN6 */ + 7, /* TRIGGER_CPUSS_DW1_TR_IN7 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN8 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN9 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN10 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN11 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN12 */ + 5, /* TRIGGER_CPUSS_DW1_TR_IN13 */ + 6, /* TRIGGER_CPUSS_DW1_TR_IN14 */ + 7, /* TRIGGER_CPUSS_DW1_TR_IN15 */ + 8, /* TRIGGER_CPUSS_DW1_TR_IN16 */ + 9, /* TRIGGER_CPUSS_DW1_TR_IN17 */ + 10, /* TRIGGER_CPUSS_DW1_TR_IN18 */ + 11, /* TRIGGER_CPUSS_DW1_TR_IN19 */ + 12, /* TRIGGER_CPUSS_DW1_TR_IN20 */ + 13, /* TRIGGER_CPUSS_DW1_TR_IN21 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN22 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN23 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN24 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN25 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN26 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN27 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN28 */ + 0, /* TRIGGER_CSD_DSI_START */ + 0, /* TRIGGER_PASS_TR_SAR_IN */ + 0, /* TRIGGER_PERI_TR_DBG_FREEZE */ + 0, /* TRIGGER_PERI_TR_IO_OUTPUT0 */ + 1, /* TRIGGER_PERI_TR_IO_OUTPUT1 */ + 2, /* TRIGGER_PROFILE_TR_START */ + 3, /* TRIGGER_PROFILE_TR_STOP */ + 0, /* TRIGGER_TCPWM0_TR_IN0 */ + 1, /* TRIGGER_TCPWM0_TR_IN1 */ + 2, /* TRIGGER_TCPWM0_TR_IN2 */ + 3, /* TRIGGER_TCPWM0_TR_IN3 */ + 4, /* TRIGGER_TCPWM0_TR_IN4 */ + 5, /* TRIGGER_TCPWM0_TR_IN5 */ + 6, /* TRIGGER_TCPWM0_TR_IN6 */ + 7, /* TRIGGER_TCPWM0_TR_IN7 */ + 8, /* TRIGGER_TCPWM0_TR_IN8 */ + 9, /* TRIGGER_TCPWM0_TR_IN9 */ + 10, /* TRIGGER_TCPWM0_TR_IN10 */ + 11, /* TRIGGER_TCPWM0_TR_IN11 */ + 12, /* TRIGGER_TCPWM0_TR_IN12 */ + 13, /* TRIGGER_TCPWM0_TR_IN13 */ + 0, /* TRIGGER_TCPWM1_TR_IN0 */ + 1, /* TRIGGER_TCPWM1_TR_IN1 */ + 2, /* TRIGGER_TCPWM1_TR_IN2 */ + 3, /* TRIGGER_TCPWM1_TR_IN3 */ + 4, /* TRIGGER_TCPWM1_TR_IN4 */ + 5, /* TRIGGER_TCPWM1_TR_IN5 */ + 6, /* TRIGGER_TCPWM1_TR_IN6 */ + 7, /* TRIGGER_TCPWM1_TR_IN7 */ + 8, /* TRIGGER_TCPWM1_TR_IN8 */ + 9, /* TRIGGER_TCPWM1_TR_IN9 */ + 10, /* TRIGGER_TCPWM1_TR_IN10 */ + 11, /* TRIGGER_TCPWM1_TR_IN11 */ + 12, /* TRIGGER_TCPWM1_TR_IN12 */ + 13, /* TRIGGER_TCPWM1_TR_IN13 */ + 0, /* TRIGGER_USB_DMA_BURSTEND0 */ + 1, /* TRIGGER_USB_DMA_BURSTEND1 */ + 2, /* TRIGGER_USB_DMA_BURSTEND2 */ + 3, /* TRIGGER_USB_DMA_BURSTEND3 */ + 4, /* TRIGGER_USB_DMA_BURSTEND4 */ + 5, /* TRIGGER_USB_DMA_BURSTEND5 */ + 6, /* TRIGGER_USB_DMA_BURSTEND6 */ + 7, /* TRIGGER_USB_DMA_BURSTEND7 */ +}; +#endif /* CY_DEVICE_PSOC6A2M */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_03.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_03.c new file mode 100644 index 0000000000..2dcccdbd5a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_03.c @@ -0,0 +1,257 @@ +/***************************************************************************//** +* \file cyhal_triggers_psoc6_03.c +* +* \brief +* PSoC6_03 family HAL triggers header +* +* \note +* Generator version: 1.5.7254.19579 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cy_device_headers.h" +#include "cyhal_hw_types.h" + +#ifdef CY_DEVICE_PSOC6A512K +#include "triggers/cyhal_triggers_psoc6_03.h" + +const uint8_t cyhal_dest_to_mux[108] = +{ + 135, /* TRIGGER_CANFD0_TR_DBG_DMA_ACK0 */ + 10, /* TRIGGER_CANFD0_TR_EVT_SWT_IN0 */ + 5, /* TRIGGER_CPUSS_CTI_TR_IN0 */ + 5, /* TRIGGER_CPUSS_CTI_TR_IN1 */ + 6, /* TRIGGER_CPUSS_DMAC_TR_IN0 */ + 6, /* TRIGGER_CPUSS_DMAC_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN0 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN2 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN3 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN4 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN5 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN6 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN7 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN8 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN9 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN10 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN11 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN12 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN13 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN14 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN15 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN16 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN17 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN18 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN19 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN20 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN21 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN22 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN23 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN24 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN25 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN26 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN27 */ + 130, /* TRIGGER_CPUSS_DW0_TR_IN28 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN1 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN2 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN3 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN4 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN5 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN6 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN7 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN8 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN9 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN10 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN11 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN12 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN13 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN14 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN15 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN16 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN17 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN18 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN19 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN20 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN21 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN22 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN23 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN24 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN25 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN26 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN27 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN28 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN29 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN30 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN31 */ + 8, /* TRIGGER_CSD_DSI_START */ + 9, /* TRIGGER_PASS_TR_SAR_IN */ + 7, /* TRIGGER_PERI_TR_DBG_FREEZE */ + 4, /* TRIGGER_PERI_TR_IO_OUTPUT0 */ + 4, /* TRIGGER_PERI_TR_IO_OUTPUT1 */ + 2, /* TRIGGER_TCPWM0_TR_IN0 */ + 2, /* TRIGGER_TCPWM0_TR_IN1 */ + 2, /* TRIGGER_TCPWM0_TR_IN2 */ + 2, /* TRIGGER_TCPWM0_TR_IN3 */ + 2, /* TRIGGER_TCPWM0_TR_IN4 */ + 2, /* TRIGGER_TCPWM0_TR_IN5 */ + 2, /* TRIGGER_TCPWM0_TR_IN6 */ + 2, /* TRIGGER_TCPWM0_TR_IN7 */ + 2, /* TRIGGER_TCPWM0_TR_IN8 */ + 2, /* TRIGGER_TCPWM0_TR_IN9 */ + 2, /* TRIGGER_TCPWM0_TR_IN10 */ + 2, /* TRIGGER_TCPWM0_TR_IN11 */ + 2, /* TRIGGER_TCPWM0_TR_IN12 */ + 2, /* TRIGGER_TCPWM0_TR_IN13 */ + 3, /* TRIGGER_TCPWM1_TR_IN0 */ + 3, /* TRIGGER_TCPWM1_TR_IN1 */ + 3, /* TRIGGER_TCPWM1_TR_IN2 */ + 3, /* TRIGGER_TCPWM1_TR_IN3 */ + 3, /* TRIGGER_TCPWM1_TR_IN4 */ + 3, /* TRIGGER_TCPWM1_TR_IN5 */ + 3, /* TRIGGER_TCPWM1_TR_IN6 */ + 3, /* TRIGGER_TCPWM1_TR_IN7 */ + 3, /* TRIGGER_TCPWM1_TR_IN8 */ + 3, /* TRIGGER_TCPWM1_TR_IN9 */ + 3, /* TRIGGER_TCPWM1_TR_IN10 */ + 3, /* TRIGGER_TCPWM1_TR_IN11 */ + 3, /* TRIGGER_TCPWM1_TR_IN12 */ + 3, /* TRIGGER_TCPWM1_TR_IN13 */ + 134, /* TRIGGER_USB_DMA_BURSTEND0 */ + 134, /* TRIGGER_USB_DMA_BURSTEND1 */ + 134, /* TRIGGER_USB_DMA_BURSTEND2 */ + 134, /* TRIGGER_USB_DMA_BURSTEND3 */ + 134, /* TRIGGER_USB_DMA_BURSTEND4 */ + 134, /* TRIGGER_USB_DMA_BURSTEND5 */ + 134, /* TRIGGER_USB_DMA_BURSTEND6 */ + 134, /* TRIGGER_USB_DMA_BURSTEND7 */ +}; + +const uint8_t cyhal_mux_dest_index[108] = +{ + 0, /* TRIGGER_CANFD0_TR_DBG_DMA_ACK0 */ + 0, /* TRIGGER_CANFD0_TR_EVT_SWT_IN0 */ + 0, /* TRIGGER_CPUSS_CTI_TR_IN0 */ + 1, /* TRIGGER_CPUSS_CTI_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DMAC_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DMAC_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN3 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN4 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN5 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN6 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN7 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN8 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN9 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN10 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN11 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN12 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN13 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN14 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN15 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN16 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN17 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN18 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN19 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN20 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN21 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN22 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN23 */ + 8, /* TRIGGER_CPUSS_DW0_TR_IN24 */ + 9, /* TRIGGER_CPUSS_DW0_TR_IN25 */ + 10, /* TRIGGER_CPUSS_DW0_TR_IN26 */ + 11, /* TRIGGER_CPUSS_DW0_TR_IN27 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN28 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN3 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN4 */ + 5, /* TRIGGER_CPUSS_DW1_TR_IN5 */ + 6, /* TRIGGER_CPUSS_DW1_TR_IN6 */ + 7, /* TRIGGER_CPUSS_DW1_TR_IN7 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN8 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN9 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN10 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN11 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN12 */ + 5, /* TRIGGER_CPUSS_DW1_TR_IN13 */ + 6, /* TRIGGER_CPUSS_DW1_TR_IN14 */ + 7, /* TRIGGER_CPUSS_DW1_TR_IN15 */ + 8, /* TRIGGER_CPUSS_DW1_TR_IN16 */ + 9, /* TRIGGER_CPUSS_DW1_TR_IN17 */ + 10, /* TRIGGER_CPUSS_DW1_TR_IN18 */ + 11, /* TRIGGER_CPUSS_DW1_TR_IN19 */ + 12, /* TRIGGER_CPUSS_DW1_TR_IN20 */ + 13, /* TRIGGER_CPUSS_DW1_TR_IN21 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN22 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN23 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN24 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN25 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN26 */ + 5, /* TRIGGER_CPUSS_DW1_TR_IN27 */ + 6, /* TRIGGER_CPUSS_DW1_TR_IN28 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN29 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN30 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN31 */ + 0, /* TRIGGER_CSD_DSI_START */ + 0, /* TRIGGER_PASS_TR_SAR_IN */ + 0, /* TRIGGER_PERI_TR_DBG_FREEZE */ + 0, /* TRIGGER_PERI_TR_IO_OUTPUT0 */ + 1, /* TRIGGER_PERI_TR_IO_OUTPUT1 */ + 0, /* TRIGGER_TCPWM0_TR_IN0 */ + 1, /* TRIGGER_TCPWM0_TR_IN1 */ + 2, /* TRIGGER_TCPWM0_TR_IN2 */ + 3, /* TRIGGER_TCPWM0_TR_IN3 */ + 4, /* TRIGGER_TCPWM0_TR_IN4 */ + 5, /* TRIGGER_TCPWM0_TR_IN5 */ + 6, /* TRIGGER_TCPWM0_TR_IN6 */ + 7, /* TRIGGER_TCPWM0_TR_IN7 */ + 8, /* TRIGGER_TCPWM0_TR_IN8 */ + 9, /* TRIGGER_TCPWM0_TR_IN9 */ + 10, /* TRIGGER_TCPWM0_TR_IN10 */ + 11, /* TRIGGER_TCPWM0_TR_IN11 */ + 12, /* TRIGGER_TCPWM0_TR_IN12 */ + 13, /* TRIGGER_TCPWM0_TR_IN13 */ + 0, /* TRIGGER_TCPWM1_TR_IN0 */ + 1, /* TRIGGER_TCPWM1_TR_IN1 */ + 2, /* TRIGGER_TCPWM1_TR_IN2 */ + 3, /* TRIGGER_TCPWM1_TR_IN3 */ + 4, /* TRIGGER_TCPWM1_TR_IN4 */ + 5, /* TRIGGER_TCPWM1_TR_IN5 */ + 6, /* TRIGGER_TCPWM1_TR_IN6 */ + 7, /* TRIGGER_TCPWM1_TR_IN7 */ + 8, /* TRIGGER_TCPWM1_TR_IN8 */ + 9, /* TRIGGER_TCPWM1_TR_IN9 */ + 10, /* TRIGGER_TCPWM1_TR_IN10 */ + 11, /* TRIGGER_TCPWM1_TR_IN11 */ + 12, /* TRIGGER_TCPWM1_TR_IN12 */ + 13, /* TRIGGER_TCPWM1_TR_IN13 */ + 0, /* TRIGGER_USB_DMA_BURSTEND0 */ + 1, /* TRIGGER_USB_DMA_BURSTEND1 */ + 2, /* TRIGGER_USB_DMA_BURSTEND2 */ + 3, /* TRIGGER_USB_DMA_BURSTEND3 */ + 4, /* TRIGGER_USB_DMA_BURSTEND4 */ + 5, /* TRIGGER_USB_DMA_BURSTEND5 */ + 6, /* TRIGGER_USB_DMA_BURSTEND6 */ + 7, /* TRIGGER_USB_DMA_BURSTEND7 */ +}; +#endif /* CY_DEVICE_PSOC6A512K */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c deleted file mode 100644 index 844ea2239d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c +++ /dev/null @@ -1,239 +0,0 @@ -/***************************************************************************//** -* \file cyhal_pwm.c -* -* \brief -* Provides a high level interface for interacting with the Cypress PWM. This is -* a wrapper around the lower level PDL API. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "cyhal_pwm_impl.h" -#include "cyhal_gpio.h" -#include "cyhal_hwmgr.h" -#include "cyhal_interconnect.h" -#include "cyhal_utils.h" - -#ifdef CY_IP_MXTCPWM - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYHAL_TCPWM_MAX_WIDTH 32 - -static const cyhal_resource_pin_mapping_t* try_alloc_pwm(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pin_map, size_t count) -{ - for (uint32_t i = 0; i < count; i++) - { - if (pin == pin_map[i].pin) - { - if (CY_RSLT_SUCCESS == cyhal_hwmgr_reserve(pin_map[i].inst)) - { - return &pin_map[i]; - } - } - } - return NULL; -} - -cy_rslt_t cyhal_pwm_init(cyhal_pwm_t *obj, cyhal_gpio_t pin, const cyhal_clock_divider_t *clk) -{ - CY_ASSERT(NULL != obj); - - cy_rslt_t result = CY_RSLT_SUCCESS; - /* Explicitly marked not allocated resources as invalid to prevent freeing them. */ - obj->resource.type = CYHAL_RSC_INVALID; - obj->pin = CYHAL_NC_PIN_VALUE; - obj->dedicated_clock = false; - - const cyhal_resource_pin_mapping_t* map = try_alloc_pwm(pin, cyhal_pin_map_tcpwm_line, sizeof(cyhal_pin_map_tcpwm_line) / sizeof(cyhal_resource_pin_mapping_t)); - if (map == NULL) - { - map = try_alloc_pwm(pin, cyhal_pin_map_tcpwm_line_compl, sizeof(cyhal_pin_map_tcpwm_line_compl) / sizeof(cyhal_resource_pin_mapping_t)); - } - if (map == NULL) - { - result = CYHAL_PWM_RSLT_BAD_ARGUMENT; - } - - if(CY_RSLT_SUCCESS == result) - { - obj->resource = *map->inst; - obj->base = CYHAL_TCPWM_DATA[obj->resource.block_num].base; - result = cyhal_gpio_init(pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, true); - } - - if (CY_RSLT_SUCCESS == result) - { - obj->pin = pin; - result = cyhal_connect_pin(map); - } - if (CY_RSLT_SUCCESS == result) - { - en_clk_dst_t pclk = (en_clk_dst_t)(CYHAL_TCPWM_DATA[obj->resource.block_num].clock_dst + obj->resource.channel_num); - if (NULL != clk) - { - obj->clock_hz = Cy_SysClk_ClkPeriGetFrequency() / (1 + Cy_SysClk_PeriphGetDivider(clk->div_type, clk->div_num)); - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, clk->div_type, clk->div_num)) - result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT; - } - else if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false))) - { - obj->dedicated_clock = true; - uint32_t div = (uint32_t)(1 << (CYHAL_TCPWM_MAX_WIDTH - CYHAL_TCPWM_DATA[obj->resource.block_num].max_count)); - if (0 == div || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num) || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num)) - result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT; - else - { - obj->clock_hz = Cy_SysClk_ClkPeriGetFrequency() / div; - } - } - } - - if (CY_RSLT_SUCCESS == result) - { - static const cy_stc_tcpwm_pwm_config_t config = - { - .pwmMode = CY_TCPWM_PWM_MODE_PWM, - .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, - .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, - .deadTimeClocks = 0UL, - .runMode = CY_TCPWM_PWM_CONTINUOUS, - .period0 = 0UL, - .period1 = 0UL, - .enablePeriodSwap = false, - .compare0 = 0UL, - .compare1 = 0UL, - .enableCompareSwap = false, - .interruptSources = CY_TCPWM_INT_NONE, - .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, - .invertPWMOutN = CY_TCPWM_PWM_INVERT_ENABLE, - .killMode = CY_TCPWM_PWM_STOP_ON_KILL, - .swapInputMode = CY_TCPWM_INPUT_RISINGEDGE, - .swapInput = CY_TCPWM_INPUT_0, - .reloadInputMode = CY_TCPWM_INPUT_RISINGEDGE, - .reloadInput = CY_TCPWM_INPUT_0, - .startInputMode = CY_TCPWM_INPUT_RISINGEDGE, - .startInput = CY_TCPWM_INPUT_0, - .killInputMode = CY_TCPWM_INPUT_RISINGEDGE, - .killInput = CY_TCPWM_INPUT_0, - .countInputMode = CY_TCPWM_INPUT_LEVEL, - .countInput = CY_TCPWM_INPUT_1 - }; - result = Cy_TCPWM_PWM_Init(obj->base, obj->resource.channel_num, &config); - } - - if (CY_RSLT_SUCCESS == result) - { - cyhal_tcpwm_init_callback_data(&(obj->resource), &(obj->callback_data)); - Cy_TCPWM_PWM_Enable(obj->base, obj->resource.channel_num); - } - else - { - cyhal_pwm_free(obj); - } - - return result; -} - -void cyhal_pwm_free(cyhal_pwm_t *obj) -{ - CY_ASSERT(NULL != obj); - - IRQn_Type irqn = (IRQn_Type)(CYHAL_TCPWM_DATA[obj->resource.block_num].isr_offset + obj->resource.channel_num); - NVIC_DisableIRQ(irqn); - - if (CYHAL_NC_PIN_VALUE != obj->pin) - { - cyhal_gpio_free(obj->pin); - obj->pin = CYHAL_NC_PIN_VALUE; - } - - if (NULL != obj->base) - { - Cy_TCPWM_PWM_Disable(obj->base, obj->resource.channel_num); - - cyhal_hwmgr_free(&(obj->resource)); - obj->base = NULL; - obj->resource.type = CYHAL_RSC_INVALID; - } - - if (obj->dedicated_clock) - { - cy_en_sysclk_status_t rslt = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); - CY_ASSERT(CY_SYSCLK_SUCCESS == rslt); - cyhal_hwmgr_free_clock(&(obj->clock)); - obj->dedicated_clock = false; - } -} - -static cy_rslt_t cyhal_pwm_set_period_and_compare(cyhal_pwm_t *obj, uint32_t period, uint32_t compare) -{ - if (period < 1 || period > (uint32_t)((1 << CYHAL_TCPWM_DATA[obj->resource.block_num].max_count)) - 1) - return CYHAL_PWM_RSLT_BAD_ARGUMENT; - if (compare > period) - compare = period; - Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, 0u); - Cy_TCPWM_PWM_SetPeriod0(obj->base, obj->resource.channel_num, period - 1u); - Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, compare); - return CY_RSLT_SUCCESS; -} - -cy_rslt_t cyhal_pwm_set_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us) -{ - static const uint32_t US_PER_SEC = 1000000u; - CY_ASSERT(NULL != obj); - uint32_t period = (uint32_t)((uint64_t)period_us * obj->clock_hz / US_PER_SEC); - uint32_t width = (uint32_t)((uint64_t)pulse_width_us * obj->clock_hz / US_PER_SEC); - return cyhal_pwm_set_period_and_compare(obj, period, width); -} - -cy_rslt_t cyhal_pwm_set_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz) -{ - CY_ASSERT(NULL != obj); - if (duty_cycle < 0.0f || duty_cycle > 100.0f || frequencyhal_hz < 1) - return CYHAL_PWM_RSLT_BAD_ARGUMENT; - uint32_t period = obj->clock_hz / frequencyhal_hz; - uint32_t width = (uint32_t)(duty_cycle * 0.01f * period); - return cyhal_pwm_set_period_and_compare(obj, period, width); -} - -cy_rslt_t cyhal_pwm_start(cyhal_pwm_t *obj) -{ - CY_ASSERT(NULL != obj); - Cy_TCPWM_TriggerReloadOrIndex(obj->base, 1u << obj->resource.channel_num); - return CY_RSLT_SUCCESS; -} - -cy_rslt_t cyhal_pwm_stop(cyhal_pwm_t *obj) -{ - CY_ASSERT(NULL != obj); - Cy_TCPWM_TriggerStopOrKill(obj->base, 1u << obj->resource.channel_num); - return CY_RSLT_SUCCESS; -} - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_MXTCPWM */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/version.xml new file mode 100644 index 0000000000..3d2fa6b4cb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/version.xml @@ -0,0 +1 @@ +1.1.1.11145 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md index 5f1875379b..f5b45dfb31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md @@ -41,4 +41,4 @@ See the [PDL API Reference Manual Getting Started section](https://cypresssemico * [Cypress Semiconductor](http://www.cypress.com) --- -© Cypress Semiconductor Corporation, 2019. \ No newline at end of file +© Cypress Semiconductor Corporation, 2020. \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md index 246c6bdffd..1bb6397e98 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md @@ -1,37 +1,35 @@ -# PSoC 6 Peripheral Driver Library v1.4.0 +# PSoC 6 Peripheral Driver Library v1.4.1 Please refer to the [README.md](./README.md) and the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html) for a complete description of the Peripheral Driver Library. ### New Features -* The structure of BSP startup templates directory (devices/templates) is updated to match the BSP layout. * The updated core-lib is reused - see [SysLib changelog](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) for details. -* Removed redundant legacy PSoC Creator-compatibility macros. -* The startup code reuses sysclk driver API - see [Startup changelog](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html) for details. + Updated Personalities -* CSD -* Power -* SegLCD -* WiFi -Updated the configurators launch parameters in CSD and SegLCD personalities: switched from GUI to console applications for regenerating the source code without opening the configurator itself. This improves the user experience, performance, and enables using machines without a GUI. -The Power personality code generation is corrected due to the customer's request. -The TCP Keepalive Offload feature support is added to the WiFi Low Power Assistant (LPA) personality. +* CAN FD - Fix filter configuration issue. +* DMA - Fixed the Trigger Input parameter behaviour. +* WiFi - Update for LPA TCP keepalive offload. +* I2S - Fixed the IRQn generation for all supported devices. +* PDM-PCM - Fixed the IRQn generation for all supported devices. +* QSPI - Data terminals UI enhancement. +* SegLCD - Added the ability to route output signals to Smart I/O. +* Smart I/O - GUI improvement. +* SysClocks - Disable ILO in Hibernate. Updated Drivers -* [BLE_CLK 3.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ble__clk.html) -* [SCB 2.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__scb.html) -* [Startup 2.70](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html) -* [SysClk 1.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) -* [SysLib 2.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) -* [SysPm 4.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html) -* [WDT 1.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__wdt.html) +* [BLE_CLK 3.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ble__clk.html) +* [CAN FD 1.10](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__canfd.html) +* [RTC 2.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__rtc.html) +* [SMIF 1.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__smif.html) +* [SysClk 1.60](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) +* [SysPm 5.0](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html) Drivers with patch version updates -* [Flash 3.30.3](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html) -* [SAR 1.20.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sar.html) -* [SegLCD 1.0.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__seglcd.html) -* [SMIF 1.40.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__smif.html) -* [TrigMux 1.20.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__trigmux.html) +* [eFuse 1.10.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__efuse.html) +* [Flash 3.30.4](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html) +* [Prot 1.30.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__prot.html) +* [SysLib 2.50.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) ### Known Issues None @@ -44,11 +42,12 @@ This version of PDL was validated for compatibility with the following Software | Software and Tools | Version | | :--- | :---- | +| [Cypress Core Library](https://github.com/cypresssemiconductorco/core-lib) | 1.1.1 | +| [Cypress HAL](https://github.com/cypresssemiconductorco/psoc6hal) | 1.1.1 | | CMSIS-Core(M) | 5.2.1 | -| GCC Compiler | 7.2.1 | +| GCC Compiler | 9.2.1 | | IAR Compiler | 8.32 | -| ARM Compiler 6 | 6.11 | -| MBED OS | 5.13.1 | +| ARM Compiler 6 | 6.13 | | FreeRTOS | 10.0.1 | ### More information @@ -62,4 +61,4 @@ This version of PDL was validated for compatibility with the following Software * [Cypress Semiconductor](http://www.cypress.com) --- -© Cypress Semiconductor Corporation, 2019. \ No newline at end of file +© Cypress Semiconductor Corporation, 2020. \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h index da1cc41e2c..e9ec4b4b80 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h @@ -5,7 +5,7 @@ * CY8C6245FNI-S3D11 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -489,9 +489,6 @@ typedef enum { #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u @@ -1103,16 +1100,6 @@ typedef enum { #define LCD0_BASE 0x403B0000UL #define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ -/******************************************************************************* -* USBFS -*******************************************************************************/ - -#define USBFS0_BASE 0x403F0000UL -#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ -#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ -#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ -#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ - /******************************************************************************* * SMIF *******************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h index 770c0186cb..5b1fe6c31d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h @@ -5,7 +5,7 @@ * CY8C6245FNI-S3D41 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -492,9 +492,6 @@ typedef enum { #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u @@ -1113,16 +1110,6 @@ typedef enum { #define LCD0_BASE 0x403B0000UL #define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ -/******************************************************************************* -* USBFS -*******************************************************************************/ - -#define USBFS0_BASE 0x403F0000UL -#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ -#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ -#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ -#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ - /******************************************************************************* * SMIF *******************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h index 4192d7bf9a..0c7af9deef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h @@ -5,7 +5,7 @@ * CY8C6245FNI-S3D71 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -492,9 +492,6 @@ typedef enum { #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u @@ -1113,16 +1110,6 @@ typedef enum { #define LCD0_BASE 0x403B0000UL #define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ -/******************************************************************************* -* USBFS -*******************************************************************************/ - -#define USBFS0_BASE 0x403F0000UL -#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ -#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ -#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ -#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ - /******************************************************************************* * SMIF *******************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h index 4a0d2bdfb5..8f1be62fdd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h @@ -5,11 +5,11 @@ * Common header file to be included by the drivers. * * \note -* Generator version: 1.5.0.1292 +* Generator version: 1.6.0.81 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -184,6 +184,8 @@ #include "cy8c624alqi_d42.h" #elif defined (CYB0644ABZI_S2D44) #include "cyb0644abzi_s2d44.h" +#elif defined (CYS0644ABZI_S2D44) + #include "cys0644abzi_s2d44.h" #elif defined (CY8C624ABZI_S2D44A0) #include "cy8c624abzi_s2d44a0.h" #elif defined (CY8C624ABZI_S2D44) @@ -236,6 +238,8 @@ #include "cy8c6245lqi_s3d02.h" #elif defined (CY8C6245W_S3D72) #include "cy8c6245w_s3d72.h" +#elif defined (PSoC6A256K) + #include "psoc6a256k.h" #else #include "cy_device_common.h" #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h index e5a3c7c1c1..fae778ff48 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h @@ -5,11 +5,11 @@ * CYB0644ABZI-S2D44 device header * * \note -* Generator version: 1.5.0.1292 +* Generator version: 1.6.0.81 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -572,7 +572,7 @@ typedef enum { #include "gpio_psoc6_02_124_bga.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4301102UL +#define CY_SILICON_ID 0xE4701202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h new file mode 100644 index 0000000000..1894820ddf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h @@ -0,0 +1,1329 @@ +/***************************************************************************//** +* \file cys0644abzi_s2d44.h +* +* \brief +* CYS0644ABZI-S2D44 device header +* +* \note +* Generator version: 1.6.0.81 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYS0644ABZI_S2D44_H_ +#define _CYS0644ABZI_S2D44_H_ + +/** +* \addtogroup group_device CYS0644ABZI-S2D44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CYS0644ABZI-S2D44 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CYS0644ABZI-S2D44 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CYS0644ABZI-S2D44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CYS0644ABZI-S2D44 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x001D0000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4A01202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CYS0644ABZI-S2D44 */ + +#endif /* _CYS0644ABZI_S2D44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h new file mode 100644 index 0000000000..fb586f7d65 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h @@ -0,0 +1,1166 @@ +/***************************************************************************//** +* \file gpio_psoc6_04_68_qfn.h +* +* \brief +* PSoC6_04 device GPIO header for 68-QFN package +* +* \note +* Generator version: 1.5.1.36 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _GPIO_PSOC6_04_68_QFN_H_ +#define _GPIO_PSOC6_04_68_QFN_H_ + +/* Package type */ +enum +{ + CY_GPIO_PACKAGE_QFN, + CY_GPIO_PACKAGE_BGA, + CY_GPIO_PACKAGE_CSP, + CY_GPIO_PACKAGE_WLCSP, + CY_GPIO_PACKAGE_LQFP, + CY_GPIO_PACKAGE_TQFP, + CY_GPIO_PACKAGE_SMT, +}; + +#define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_QFN +#define CY_GPIO_PIN_COUNT 68u + +/* AMUXBUS Segments */ +enum +{ + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, + AMUXBUS_VSSA, + AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, + AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, +}; + +/* AMUX Splitter Controls */ +typedef enum +{ + AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ + AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ + AMUX_SPLIT_CTL_5 = 0x0005u /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ +} cy_en_amux_split_t; + +/* Port List */ +/* PORT 0 (GPIO) */ +#define P0_0_PORT GPIO_PRT0 +#define P0_0_PIN 0u +#define P0_0_NUM 0u +#define P0_1_PORT GPIO_PRT0 +#define P0_1_PIN 1u +#define P0_1_NUM 1u +#define P0_2_PORT GPIO_PRT0 +#define P0_2_PIN 2u +#define P0_2_NUM 2u +#define P0_3_PORT GPIO_PRT0 +#define P0_3_PIN 3u +#define P0_3_NUM 3u +#define P0_4_PORT GPIO_PRT0 +#define P0_4_PIN 4u +#define P0_4_NUM 4u +#define P0_5_PORT GPIO_PRT0 +#define P0_5_PIN 5u +#define P0_5_NUM 5u + +/* PORT 2 (GPIO) */ +#define P2_0_PORT GPIO_PRT2 +#define P2_0_PIN 0u +#define P2_0_NUM 0u +#define P2_1_PORT GPIO_PRT2 +#define P2_1_PIN 1u +#define P2_1_NUM 1u +#define P2_2_PORT GPIO_PRT2 +#define P2_2_PIN 2u +#define P2_2_NUM 2u +#define P2_3_PORT GPIO_PRT2 +#define P2_3_PIN 3u +#define P2_3_NUM 3u +#define P2_4_PORT GPIO_PRT2 +#define P2_4_PIN 4u +#define P2_4_NUM 4u +#define P2_5_PORT GPIO_PRT2 +#define P2_5_PIN 5u +#define P2_5_NUM 5u +#define P2_6_PORT GPIO_PRT2 +#define P2_6_PIN 6u +#define P2_6_NUM 6u +#define P2_7_PORT GPIO_PRT2 +#define P2_7_PIN 7u +#define P2_7_NUM 7u + +/* PORT 3 (GPIO_OVT) */ +#define P3_0_PORT GPIO_PRT3 +#define P3_0_PIN 0u +#define P3_0_NUM 0u +#define P3_0_AMUXSEGMENT AMUXBUS_VSSA +#define P3_1_PORT GPIO_PRT3 +#define P3_1_PIN 1u +#define P3_1_NUM 1u +#define P3_1_AMUXSEGMENT AMUXBUS_VSSA + +/* PORT 5 (GPIO) */ +#define P5_0_PORT GPIO_PRT5 +#define P5_0_PIN 0u +#define P5_0_NUM 0u +#define P5_1_PORT GPIO_PRT5 +#define P5_1_PIN 1u +#define P5_1_NUM 1u +#define P5_6_PORT GPIO_PRT5 +#define P5_6_PIN 6u +#define P5_6_NUM 6u +#define P5_7_PORT GPIO_PRT5 +#define P5_7_PIN 7u +#define P5_7_NUM 7u + +/* PORT 6 (GPIO) */ +#define P6_2_PORT GPIO_PRT6 +#define P6_2_PIN 2u +#define P6_2_NUM 2u +#define P6_3_PORT GPIO_PRT6 +#define P6_3_PIN 3u +#define P6_3_NUM 3u +#define P6_4_PORT GPIO_PRT6 +#define P6_4_PIN 4u +#define P6_4_NUM 4u +#define P6_5_PORT GPIO_PRT6 +#define P6_5_PIN 5u +#define P6_5_NUM 5u +#define P6_6_PORT GPIO_PRT6 +#define P6_6_PIN 6u +#define P6_6_NUM 6u +#define P6_7_PORT GPIO_PRT6 +#define P6_7_PIN 7u +#define P6_7_NUM 7u + +/* PORT 7 (GPIO) */ +#define P7_0_PORT GPIO_PRT7 +#define P7_0_PIN 0u +#define P7_0_NUM 0u +#define P7_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_1_PORT GPIO_PRT7 +#define P7_1_PIN 1u +#define P7_1_NUM 1u +#define P7_1_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_2_PORT GPIO_PRT7 +#define P7_2_PIN 2u +#define P7_2_NUM 2u +#define P7_2_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_3_PORT GPIO_PRT7 +#define P7_3_PIN 3u +#define P7_3_NUM 3u +#define P7_3_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_7_PORT GPIO_PRT7 +#define P7_7_PIN 7u +#define P7_7_NUM 7u +#define P7_7_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 8 (GPIO) */ +#define P8_0_PORT GPIO_PRT8 +#define P8_0_PIN 0u +#define P8_0_NUM 0u +#define P8_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P8_1_PORT GPIO_PRT8 +#define P8_1_PIN 1u +#define P8_1_NUM 1u +#define P8_1_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 9 (GPIO) */ +#define P9_0_PORT GPIO_PRT9 +#define P9_0_PIN 0u +#define P9_0_NUM 0u +#define P9_0_AMUXSEGMENT AMUXBUS_SAR +#define P9_1_PORT GPIO_PRT9 +#define P9_1_PIN 1u +#define P9_1_NUM 1u +#define P9_1_AMUXSEGMENT AMUXBUS_SAR +#define P9_2_PORT GPIO_PRT9 +#define P9_2_PIN 2u +#define P9_2_NUM 2u +#define P9_2_AMUXSEGMENT AMUXBUS_SAR +#define P9_3_PORT GPIO_PRT9 +#define P9_3_PIN 3u +#define P9_3_NUM 3u +#define P9_3_AMUXSEGMENT AMUXBUS_SAR + +/* PORT 10 (GPIO) */ +#define P10_0_PORT GPIO_PRT10 +#define P10_0_PIN 0u +#define P10_0_NUM 0u +#define P10_0_AMUXSEGMENT AMUXBUS_SAR +#define P10_1_PORT GPIO_PRT10 +#define P10_1_PIN 1u +#define P10_1_NUM 1u +#define P10_1_AMUXSEGMENT AMUXBUS_SAR +#define P10_2_PORT GPIO_PRT10 +#define P10_2_PIN 2u +#define P10_2_NUM 2u +#define P10_2_AMUXSEGMENT AMUXBUS_SAR +#define P10_3_PORT GPIO_PRT10 +#define P10_3_PIN 3u +#define P10_3_NUM 3u +#define P10_3_AMUXSEGMENT AMUXBUS_SAR +#define P10_4_PORT GPIO_PRT10 +#define P10_4_PIN 4u +#define P10_4_NUM 4u +#define P10_4_AMUXSEGMENT AMUXBUS_SAR +#define P10_5_PORT GPIO_PRT10 +#define P10_5_PIN 5u +#define P10_5_NUM 5u +#define P10_5_AMUXSEGMENT AMUXBUS_SAR +#define P10_6_PORT GPIO_PRT10 +#define P10_6_PIN 6u +#define P10_6_NUM 6u +#define P10_6_AMUXSEGMENT AMUXBUS_SAR +#define P10_7_PORT GPIO_PRT10 +#define P10_7_PIN 7u +#define P10_7_NUM 7u +#define P10_7_AMUXSEGMENT AMUXBUS_SAR + +/* PORT 11 (GPIO) */ +#define P11_2_PORT GPIO_PRT11 +#define P11_2_PIN 2u +#define P11_2_NUM 2u +#define P11_3_PORT GPIO_PRT11 +#define P11_3_PIN 3u +#define P11_3_NUM 3u +#define P11_4_PORT GPIO_PRT11 +#define P11_4_PIN 4u +#define P11_4_NUM 4u +#define P11_5_PORT GPIO_PRT11 +#define P11_5_PIN 5u +#define P11_5_NUM 5u +#define P11_6_PORT GPIO_PRT11 +#define P11_6_PIN 6u +#define P11_6_NUM 6u +#define P11_7_PORT GPIO_PRT11 +#define P11_7_PIN 7u +#define P11_7_NUM 7u + +/* PORT 12 (GPIO) */ +#define P12_6_PORT GPIO_PRT12 +#define P12_6_PIN 6u +#define P12_6_NUM 6u +#define P12_7_PORT GPIO_PRT12 +#define P12_7_PIN 7u +#define P12_7_NUM 7u + +/* PORT 14 (AUX) */ +#define USBDP_PORT GPIO_PRT14 +#define USBDP_PIN 0u +#define USBDP_NUM 0u +#define USBDM_PORT GPIO_PRT14 +#define USBDM_PIN 1u +#define USBDM_NUM 1u + +/* Analog Connections */ +#define CSD_CMODPADD_PORT 7u +#define CSD_CMODPADD_PIN 1u +#define CSD_CMODPADS_PORT 7u +#define CSD_CMODPADS_PIN 1u +#define CSD_CSH_TANKPADD_PORT 7u +#define CSD_CSH_TANKPADD_PIN 2u +#define CSD_CSH_TANKPADS_PORT 7u +#define CSD_CSH_TANKPADS_PIN 2u +#define CSD_CSHIELDPADS_PORT 8u +#define CSD_CSHIELDPADS_PIN 1u +#define CSD_VREF_EXT_PORT 7u +#define CSD_VREF_EXT_PIN 3u +#define IOSS_ADFT0_NET_PORT 10u +#define IOSS_ADFT0_NET_PIN 0u +#define IOSS_ADFT1_NET_PORT 10u +#define IOSS_ADFT1_NET_PIN 1u +#define LPCOMP_INN_COMP0_PORT 5u +#define LPCOMP_INN_COMP0_PIN 7u +#define LPCOMP_INN_COMP1_PORT 6u +#define LPCOMP_INN_COMP1_PIN 3u +#define LPCOMP_INP_COMP0_PORT 5u +#define LPCOMP_INP_COMP0_PIN 6u +#define LPCOMP_INP_COMP1_PORT 6u +#define LPCOMP_INP_COMP1_PIN 2u +#define PASS_CTB_OA0_OUT_10X_PORT 9u +#define PASS_CTB_OA0_OUT_10X_PIN 2u +#define PASS_CTB_OA1_OUT_10X_PORT 9u +#define PASS_CTB_OA1_OUT_10X_PIN 3u +#define PASS_CTB_PADS0_PORT 9u +#define PASS_CTB_PADS0_PIN 0u +#define PASS_CTB_PADS1_PORT 9u +#define PASS_CTB_PADS1_PIN 1u +#define PASS_CTB_PADS2_PORT 9u +#define PASS_CTB_PADS2_PIN 2u +#define PASS_CTB_PADS3_PORT 9u +#define PASS_CTB_PADS3_PIN 3u +#define PASS_SARMUX_PADS0_PORT 10u +#define PASS_SARMUX_PADS0_PIN 0u +#define PASS_SARMUX_PADS1_PORT 10u +#define PASS_SARMUX_PADS1_PIN 1u +#define PASS_SARMUX_PADS10_PORT 10u +#define PASS_SARMUX_PADS10_PIN 2u +#define PASS_SARMUX_PADS11_PORT 10u +#define PASS_SARMUX_PADS11_PIN 3u +#define PASS_SARMUX_PADS12_PORT 10u +#define PASS_SARMUX_PADS12_PIN 4u +#define PASS_SARMUX_PADS13_PORT 10u +#define PASS_SARMUX_PADS13_PIN 5u +#define PASS_SARMUX_PADS14_PORT 10u +#define PASS_SARMUX_PADS14_PIN 6u +#define PASS_SARMUX_PADS15_PORT 10u +#define PASS_SARMUX_PADS15_PIN 7u +#define PASS_SARMUX_PADS2_PORT 10u +#define PASS_SARMUX_PADS2_PIN 2u +#define PASS_SARMUX_PADS3_PORT 10u +#define PASS_SARMUX_PADS3_PIN 3u +#define PASS_SARMUX_PADS4_PORT 10u +#define PASS_SARMUX_PADS4_PIN 4u +#define PASS_SARMUX_PADS5_PORT 10u +#define PASS_SARMUX_PADS5_PIN 5u +#define PASS_SARMUX_PADS6_PORT 10u +#define PASS_SARMUX_PADS6_PIN 6u +#define PASS_SARMUX_PADS7_PORT 10u +#define PASS_SARMUX_PADS7_PIN 7u +#define PASS_SARMUX_PADS8_PORT 10u +#define PASS_SARMUX_PADS8_PIN 0u +#define PASS_SARMUX_PADS9_PORT 10u +#define PASS_SARMUX_PADS9_PIN 1u +#define SRSS_ADFT_PIN0_PORT 10u +#define SRSS_ADFT_PIN0_PIN 0u +#define SRSS_ADFT_PIN1_PORT 10u +#define SRSS_ADFT_PIN1_PIN 1u +#define SRSS_ECO_IN_PORT 12u +#define SRSS_ECO_IN_PIN 6u +#define SRSS_ECO_OUT_PORT 12u +#define SRSS_ECO_OUT_PIN 7u +#define SRSS_WCO_IN_PORT 0u +#define SRSS_WCO_IN_PIN 0u +#define SRSS_WCO_OUT_PORT 0u +#define SRSS_WCO_OUT_PIN 1u + +/* HSIOM Connections */ +typedef enum +{ + /* Generic HSIOM connections */ + HSIOM_SEL_GPIO = 0, /* N/A */ + HSIOM_SEL_GPIO_DSI = 1, /* N/A */ + HSIOM_SEL_DSI_DSI = 2, /* N/A */ + HSIOM_SEL_DSI_GPIO = 3, /* N/A */ + HSIOM_SEL_AMUXA = 4, /* AMUXBUS A */ + HSIOM_SEL_AMUXB = 5, /* AMUXBUS B */ + HSIOM_SEL_AMUXA_DSI = 6, /* N/A */ + HSIOM_SEL_AMUXB_DSI = 7, /* N/A */ + HSIOM_SEL_ACT_0 = 8, /* Active peripherals 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active peripherals 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active peripherals 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active peripherals 4 */ + HSIOM_SEL_DS_0 = 12, /* Deep Sleep peripherals 0 */ + HSIOM_SEL_DS_1 = 13, /* Deep Sleep peripherals 1 */ + HSIOM_SEL_DS_2 = 14, /* Deep Sleep peripherals 2 */ + HSIOM_SEL_DS_3 = 15, /* Deep Sleep peripherals 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active peripherals 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active peripherals 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active peripherals 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active peripherals 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active peripherals 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active peripherals 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active peripherals 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active peripherals 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active peripherals 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active peripherals 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active peripherals 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active peripherals 15 */ + HSIOM_SEL_DS_4 = 28, /* N/A */ + HSIOM_SEL_DS_5 = 29, /* N/A */ + HSIOM_SEL_DS_6 = 30, /* N/A */ + HSIOM_SEL_DS_7 = 31, /* N/A */ + + /* P0.0 */ + P0_0_GPIO = 0, /* N/A */ + P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ + P0_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:0 */ + P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ + P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ + P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ + P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ + P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ + P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ + P0_0_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ + P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ + + /* P0.1 */ + P0_1_GPIO = 0, /* N/A */ + P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ + P0_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ + P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ + P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ + P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ + P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ + P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ + P0_1_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ + P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ + P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ + + /* P0.2 */ + P0_2_GPIO = 0, /* N/A */ + P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ + P0_2_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:0 */ + P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ + P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ + P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ + P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ + P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ + P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ + P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ + P0_2_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:0 */ + + /* P0.3 */ + P0_3_GPIO = 0, /* N/A */ + P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ + P0_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ + P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ + P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ + P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ + P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ + P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ + P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ + P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ + P0_3_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ + + /* P0.4 */ + P0_4_GPIO = 0, /* N/A */ + P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ + P0_4_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:0 */ + P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ + P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ + P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ + P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ + P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ + P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ + P0_4_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:0 */ + P0_4_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ + P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ + + /* P0.5 */ + P0_5_GPIO = 0, /* N/A */ + P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ + P0_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ + P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ + P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ + P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ + P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ + P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ + P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ + P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ + P0_5_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:0 */ + P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ + P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ + + /* USBDM */ + USBDM_GPIO = 0, /* N/A */ + + /* USBDP */ + USBDP_GPIO = 0, /* N/A */ + + /* P2.0 */ + P2_0_GPIO = 0, /* N/A */ + P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ + P2_0_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:0 */ + P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ + P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ + P2_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ + P2_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ + P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ + P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ + P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ + P2_0_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:0 */ + P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ + + /* P2.1 */ + P2_1_GPIO = 0, /* N/A */ + P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ + P2_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ + P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ + P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ + P2_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ + P2_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ + P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ + P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ + P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ + P2_1_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:0 */ + P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ + + /* P2.2 */ + P2_2_GPIO = 0, /* N/A */ + P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ + P2_2_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:0 */ + P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ + P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ + P2_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ + P2_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ + P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ + P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ + P2_2_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:0 */ + + /* P2.3 */ + P2_3_GPIO = 0, /* N/A */ + P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ + P2_3_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ + P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ + P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ + P2_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ + P2_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ + P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ + P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ + P2_3_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ + + /* P2.4 */ + P2_4_GPIO = 0, /* N/A */ + P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ + P2_4_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:0 */ + P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ + P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ + P2_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ + P2_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ + P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ + P2_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:1 */ + + /* P2.5 */ + P2_5_GPIO = 0, /* N/A */ + P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ + P2_5_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ + P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ + P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ + P2_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ + P2_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ + P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ + P2_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:1 */ + + /* P2.6 */ + P2_6_GPIO = 0, /* N/A */ + P2_6_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ + P2_6_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:0 */ + P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ + P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ + P2_6_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ + P2_6_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ + P2_6_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ + P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ + P2_6_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:1 */ + P2_6_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ + + /* P2.7 */ + P2_7_GPIO = 0, /* N/A */ + P2_7_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ + P2_7_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ + P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ + P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ + P2_7_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ + P2_7_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ + P2_7_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ + P2_7_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:1 */ + P2_7_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ + + /* P3.0 */ + P3_0_GPIO = 0, /* N/A */ + P3_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ + P3_0_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:0 */ + P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ + P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ + P3_0_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ + P3_0_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ + P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ + P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ + P3_0_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:1 */ + P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ + + /* P3.1 */ + P3_1_GPIO = 0, /* N/A */ + P3_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ + P3_1_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:0 */ + P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ + P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ + P3_1_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ + P3_1_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ + P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ + P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ + P3_1_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:1 */ + P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ + + /* P5.0 */ + P5_0_GPIO = 0, /* N/A */ + P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ + P5_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:1 */ + P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ + P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ + P5_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ + P5_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ + P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ + P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ + P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ + P5_0_CANFD0_TTCAN_RX0 = 22, /* Digital Active - canfd[0].ttcan_rx[0] */ + P5_0_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:1 */ + P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ + + /* P5.1 */ + P5_1_GPIO = 0, /* N/A */ + P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ + P5_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ + P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ + P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:20 */ + P5_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ + P5_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ + P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ + P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ + P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ + P5_1_CANFD0_TTCAN_TX0 = 22, /* Digital Active - canfd[0].ttcan_tx[0] */ + P5_1_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:1 */ + P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ + + /* P5.6 */ + P5_6_GPIO = 0, /* N/A */ + P5_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ + P5_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:1 */ + P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ + P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ + P5_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ + P5_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ + P5_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:1 */ + + /* P5.7 */ + P5_7_GPIO = 0, /* N/A */ + P5_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ + P5_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:1 */ + P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ + P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ + P5_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ + P5_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ + P5_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:1 */ + + /* P6.2 */ + P6_2_GPIO = 0, /* N/A */ + P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ + P6_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:1 */ + P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ + P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ + P6_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ + P6_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ + P6_2_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:2 */ + P6_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ + + /* P6.3 */ + P6_3_GPIO = 0, /* N/A */ + P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ + P6_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ + P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ + P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ + P6_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ + P6_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ + P6_3_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:2 */ + P6_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ + + /* P6.4 */ + P6_4_GPIO = 0, /* N/A */ + P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ + P6_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:1 */ + P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ + P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ + P6_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ + P6_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ + P6_4_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:0 */ + P6_4_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:2 */ + P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ + P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ + P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ + P6_4_SCB6_SPI_MOSI = 30, /* Digital Deep Sleep - scb[6].spi_mosi:0 */ + P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ + + /* P6.5 */ + P6_5_GPIO = 0, /* N/A */ + P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ + P6_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:1 */ + P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ + P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ + P6_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ + P6_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ + P6_5_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:0 */ + P6_5_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:2 */ + P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ + P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ + P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ + P6_5_SCB6_SPI_MISO = 30, /* Digital Deep Sleep - scb[6].spi_miso:0 */ + P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ + + /* P6.6 */ + P6_6_GPIO = 0, /* N/A */ + P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ + P6_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:1 */ + P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ + P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:28 */ + P6_6_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ + P6_6_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ + P6_6_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:2 */ + P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ + P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ + + /* P6.7 */ + P6_7_GPIO = 0, /* N/A */ + P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ + P6_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ + P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ + P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:29 */ + P6_7_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ + P6_7_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ + P6_7_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:2 */ + P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ + P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ + + /* P7.0 */ + P7_0_GPIO = 0, /* N/A */ + P7_0_AMUXA = 4, /* AMUXBUS A */ + P7_0_AMUXB = 5, /* AMUXBUS B */ + P7_0_AMUXA_DSI = 6, /* N/A */ + P7_0_AMUXB_DSI = 7, /* N/A */ + P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ + P7_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:1 */ + P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ + P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ + P7_0_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:0 */ + P7_0_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:0 */ + P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ + P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ + P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ + P7_0_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:2 */ + P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ + P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ + + /* P7.1 */ + P7_1_GPIO = 0, /* N/A */ + P7_1_AMUXA = 4, /* AMUXBUS A */ + P7_1_AMUXB = 5, /* AMUXBUS B */ + P7_1_AMUXA_DSI = 6, /* N/A */ + P7_1_AMUXB_DSI = 7, /* N/A */ + P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ + P7_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ + P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ + P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ + P7_1_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:0 */ + P7_1_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:0 */ + P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ + P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ + P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ + P7_1_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:2 */ + P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ + + /* P7.2 */ + P7_2_GPIO = 0, /* N/A */ + P7_2_AMUXA = 4, /* AMUXBUS A */ + P7_2_AMUXB = 5, /* AMUXBUS B */ + P7_2_AMUXA_DSI = 6, /* N/A */ + P7_2_AMUXB_DSI = 7, /* N/A */ + P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ + P7_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:1 */ + P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ + P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ + P7_2_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ + P7_2_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ + P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ + P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ + P7_2_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:2 */ + + /* P7.3 */ + P7_3_GPIO = 0, /* N/A */ + P7_3_AMUXA = 4, /* AMUXBUS A */ + P7_3_AMUXB = 5, /* AMUXBUS B */ + P7_3_AMUXA_DSI = 6, /* N/A */ + P7_3_AMUXB_DSI = 7, /* N/A */ + P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ + P7_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ + P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ + P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ + P7_3_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ + P7_3_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ + P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ + P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ + P7_3_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:2 */ + + /* P7.7 */ + P7_7_GPIO = 0, /* N/A */ + P7_7_AMUXA = 4, /* AMUXBUS A */ + P7_7_AMUXB = 5, /* AMUXBUS B */ + P7_7_AMUXA_DSI = 6, /* N/A */ + P7_7_AMUXB_DSI = 7, /* N/A */ + P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ + P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ + P7_7_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ + P7_7_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ + P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ + P7_7_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:3 */ + + /* P8.0 */ + P8_0_GPIO = 0, /* N/A */ + P8_0_AMUXA = 4, /* AMUXBUS A */ + P8_0_AMUXB = 5, /* AMUXBUS B */ + P8_0_AMUXA_DSI = 6, /* N/A */ + P8_0_AMUXB_DSI = 7, /* N/A */ + P8_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ + P8_0_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:1 */ + P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ + P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ + P8_0_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ + P8_0_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ + P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ + P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ + P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ + P8_0_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:3 */ + P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ + + /* P8.1 */ + P8_1_GPIO = 0, /* N/A */ + P8_1_AMUXA = 4, /* AMUXBUS A */ + P8_1_AMUXB = 5, /* AMUXBUS B */ + P8_1_AMUXA_DSI = 6, /* N/A */ + P8_1_AMUXB_DSI = 7, /* N/A */ + P8_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ + P8_1_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ + P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ + P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ + P8_1_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ + P8_1_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ + P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ + P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ + P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ + P8_1_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:3 */ + P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ + + /* P9.0 */ + P9_0_GPIO = 0, /* N/A */ + P9_0_AMUXA = 4, /* AMUXBUS A */ + P9_0_AMUXB = 5, /* AMUXBUS B */ + P9_0_AMUXA_DSI = 6, /* N/A */ + P9_0_AMUXB_DSI = 7, /* N/A */ + P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ + P9_0_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:2 */ + P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ + P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ + P9_0_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ + P9_0_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ + P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ + P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ + P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ + P9_0_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:3 */ + P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ + P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ + + /* P9.1 */ + P9_1_GPIO = 0, /* N/A */ + P9_1_AMUXA = 4, /* AMUXBUS A */ + P9_1_AMUXB = 5, /* AMUXBUS B */ + P9_1_AMUXA_DSI = 6, /* N/A */ + P9_1_AMUXB_DSI = 7, /* N/A */ + P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ + P9_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:2 */ + P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ + P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ + P9_1_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ + P9_1_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ + P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ + P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ + P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ + P9_1_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:3 */ + P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ + P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ + P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ + + /* P9.2 */ + P9_2_GPIO = 0, /* N/A */ + P9_2_AMUXA = 4, /* AMUXBUS A */ + P9_2_AMUXB = 5, /* AMUXBUS B */ + P9_2_AMUXA_DSI = 6, /* N/A */ + P9_2_AMUXB_DSI = 7, /* N/A */ + P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ + P9_2_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:2 */ + P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ + P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ + P9_2_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ + P9_2_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ + P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ + P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ + P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ + P9_2_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:3 */ + P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ + + /* P9.3 */ + P9_3_GPIO = 0, /* N/A */ + P9_3_AMUXA = 4, /* AMUXBUS A */ + P9_3_AMUXB = 5, /* AMUXBUS B */ + P9_3_AMUXA_DSI = 6, /* N/A */ + P9_3_AMUXB_DSI = 7, /* N/A */ + P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ + P9_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:3 */ + P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ + P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ + P9_3_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ + P9_3_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ + P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ + P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ + P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ + P9_3_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:3 */ + P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ + P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ + + /* P10.0 */ + P10_0_GPIO = 0, /* N/A */ + P10_0_AMUXA = 4, /* AMUXBUS A */ + P10_0_AMUXB = 5, /* AMUXBUS B */ + P10_0_AMUXA_DSI = 6, /* N/A */ + P10_0_AMUXB_DSI = 7, /* N/A */ + P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ + P10_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:2 */ + P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ + P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ + P10_0_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ + P10_0_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ + P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ + P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ + P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ + P10_0_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:3 */ + P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ + P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ + + /* P10.1 */ + P10_1_GPIO = 0, /* N/A */ + P10_1_AMUXA = 4, /* AMUXBUS A */ + P10_1_AMUXB = 5, /* AMUXBUS B */ + P10_1_AMUXA_DSI = 6, /* N/A */ + P10_1_AMUXB_DSI = 7, /* N/A */ + P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ + P10_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:2 */ + P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ + P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ + P10_1_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ + P10_1_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ + P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ + P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ + P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ + P10_1_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:3 */ + P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ + P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ + + /* P10.2 */ + P10_2_GPIO = 0, /* N/A */ + P10_2_AMUXA = 4, /* AMUXBUS A */ + P10_2_AMUXB = 5, /* AMUXBUS B */ + P10_2_AMUXA_DSI = 6, /* N/A */ + P10_2_AMUXB_DSI = 7, /* N/A */ + P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ + P10_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:2 */ + P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ + P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ + P10_2_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ + P10_2_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ + P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ + P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ + P10_2_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:3 */ + P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ + + /* P10.3 */ + P10_3_GPIO = 0, /* N/A */ + P10_3_AMUXA = 4, /* AMUXBUS A */ + P10_3_AMUXB = 5, /* AMUXBUS B */ + P10_3_AMUXA_DSI = 6, /* N/A */ + P10_3_AMUXB_DSI = 7, /* N/A */ + P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ + P10_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:2 */ + P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ + P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ + P10_3_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ + P10_3_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ + P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ + P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ + P10_3_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:4 */ + P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ + + /* P10.4 */ + P10_4_GPIO = 0, /* N/A */ + P10_4_AMUXA = 4, /* AMUXBUS A */ + P10_4_AMUXB = 5, /* AMUXBUS B */ + P10_4_AMUXA_DSI = 6, /* N/A */ + P10_4_AMUXB_DSI = 7, /* N/A */ + P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ + P10_4_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:2 */ + P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ + P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ + P10_4_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ + P10_4_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ + P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ + P10_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:4 */ + + /* P10.5 */ + P10_5_GPIO = 0, /* N/A */ + P10_5_AMUXA = 4, /* AMUXBUS A */ + P10_5_AMUXB = 5, /* AMUXBUS B */ + P10_5_AMUXA_DSI = 6, /* N/A */ + P10_5_AMUXB_DSI = 7, /* N/A */ + P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ + P10_5_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:2 */ + P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ + P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ + P10_5_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ + P10_5_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ + P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ + P10_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:4 */ + + /* P10.6 */ + P10_6_GPIO = 0, /* N/A */ + P10_6_AMUXA = 4, /* AMUXBUS A */ + P10_6_AMUXB = 5, /* AMUXBUS B */ + P10_6_AMUXA_DSI = 6, /* N/A */ + P10_6_AMUXB_DSI = 7, /* N/A */ + P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ + P10_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:2 */ + P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ + P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ + P10_6_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ + P10_6_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ + P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ + P10_6_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:4 */ + P10_6_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ + + /* P10.7 */ + P10_7_GPIO = 0, /* N/A */ + P10_7_AMUXA = 4, /* AMUXBUS A */ + P10_7_AMUXB = 5, /* AMUXBUS B */ + P10_7_AMUXA_DSI = 6, /* N/A */ + P10_7_AMUXB_DSI = 7, /* N/A */ + P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ + P10_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:2 */ + P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ + P10_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ + P10_7_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ + P10_7_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ + P10_7_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ + P10_7_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:4 */ + P10_7_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ + + /* P11.2 */ + P11_2_GPIO = 0, /* N/A */ + P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ + P11_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:2 */ + P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ + P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ + P11_2_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ + P11_2_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ + P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ + P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ + P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ + P11_2_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:4 */ + + /* P11.3 */ + P11_3_GPIO = 0, /* N/A */ + P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ + P11_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ + P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ + P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ + P11_3_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ + P11_3_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ + P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ + P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ + P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ + P11_3_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:4 */ + P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ + + /* P11.4 */ + P11_4_GPIO = 0, /* N/A */ + P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ + P11_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:3 */ + P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ + P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ + P11_4_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ + P11_4_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ + P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ + P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ + P11_4_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:4 */ + P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ + + /* P11.5 */ + P11_5_GPIO = 0, /* N/A */ + P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ + P11_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:3 */ + P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ + P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ + P11_5_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ + P11_5_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ + P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ + P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ + P11_5_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:4 */ + + /* P11.6 */ + P11_6_GPIO = 0, /* N/A */ + P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ + P11_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:3 */ + P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ + P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ + P11_6_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ + P11_6_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ + P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ + P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ + P11_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:4 */ + + /* P11.7 */ + P11_7_GPIO = 0, /* N/A */ + P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ + P11_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:2 */ + P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ + P11_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ + P11_7_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ + P11_7_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ + P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ + P11_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:4 */ + + /* P12.6 */ + P12_6_GPIO = 0, /* N/A */ + P12_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ + P12_6_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:3 */ + P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ + P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ + P12_6_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ + P12_6_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ + P12_6_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:5 */ + + /* P12.7 */ + P12_7_GPIO = 0, /* N/A */ + P12_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ + P12_7_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:3 */ + P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ + P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ + P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ + P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ + P12_7_TCPWM0_TR_ONE_CNT_IN1 = 23 /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:5 */ +} en_hsiom_sel_t; + +#endif /* _GPIO_PSOC6_04_68_QFN_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h new file mode 100644 index 0000000000..54b84f2af6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h @@ -0,0 +1,271 @@ +/***************************************************************************//** +* \file cyip_ctbm_v2.h +* +* \brief +* CTBM IP definitions +* +* \note +* Generator version: 1.5.1.36 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_CTBM_V2_H_ +#define _CYIP_CTBM_V2_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM_V2_SECTION_SIZE 0x00010000UL + +/** + * \brief Continuous Time Block Mini (CTBM) + */ +typedef struct { + __IOM uint32_t CTB_CTRL; /*!< 0x00000000 global CTB and power control */ + __IOM uint32_t OA_RES0_CTRL; /*!< 0x00000004 Opamp0 and resistor0 control */ + __IOM uint32_t OA_RES1_CTRL; /*!< 0x00000008 Opamp1 and resistor1 control */ + __IM uint32_t COMP_STAT; /*!< 0x0000000C Comparator status */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t INTR; /*!< 0x00000020 Interrupt request register */ + __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt request set register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt request mask */ + __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt request masked */ + __IM uint32_t RESERVED1[20]; + __IOM uint32_t OA0_SW; /*!< 0x00000080 Opamp0 switch control */ + __IOM uint32_t OA0_SW_CLEAR; /*!< 0x00000084 Opamp0 switch control clear */ + __IOM uint32_t OA1_SW; /*!< 0x00000088 Opamp1 switch control */ + __IOM uint32_t OA1_SW_CLEAR; /*!< 0x0000008C Opamp1 switch control clear */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t CTD_SW; /*!< 0x000000A0 CTDAC connection switch control */ + __IOM uint32_t CTD_SW_CLEAR; /*!< 0x000000A4 CTDAC connection switch control clear */ + __IM uint32_t RESERVED3[6]; + __IOM uint32_t CTB_SW_DS_CTRL; /*!< 0x000000C0 CTB bus switch control */ + __IOM uint32_t CTB_SW_SQ_CTRL; /*!< 0x000000C4 CTB bus switch Sar Sequencer control */ + __IM uint32_t CTB_SW_STATUS; /*!< 0x000000C8 CTB bus switch control status */ +} CTBM_V2_Type; /*!< Size = 204 (0xCC) */ + + +/* CTBM.CTB_CTRL */ +#define CTBM_V2_CTB_CTRL_DEEPSLEEP_ON_Pos 30UL +#define CTBM_V2_CTB_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL +#define CTBM_V2_CTB_CTRL_ENABLED_Pos 31UL +#define CTBM_V2_CTB_CTRL_ENABLED_Msk 0x80000000UL +/* CTBM.OA_RES0_CTRL */ +#define CTBM_V2_OA_RES0_CTRL_OA0_PWR_MODE_Pos 0UL +#define CTBM_V2_OA_RES0_CTRL_OA0_PWR_MODE_Msk 0x7UL +#define CTBM_V2_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos 3UL +#define CTBM_V2_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Msk 0x8UL +#define CTBM_V2_OA_RES0_CTRL_OA0_COMP_EN_Pos 4UL +#define CTBM_V2_OA_RES0_CTRL_OA0_COMP_EN_Msk 0x10UL +#define CTBM_V2_OA_RES0_CTRL_OA0_HYST_EN_Pos 5UL +#define CTBM_V2_OA_RES0_CTRL_OA0_HYST_EN_Msk 0x20UL +#define CTBM_V2_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Pos 6UL +#define CTBM_V2_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk 0x40UL +#define CTBM_V2_OA_RES0_CTRL_OA0_DSI_LEVEL_Pos 7UL +#define CTBM_V2_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk 0x80UL +#define CTBM_V2_OA_RES0_CTRL_OA0_COMPINT_Pos 8UL +#define CTBM_V2_OA_RES0_CTRL_OA0_COMPINT_Msk 0x300UL +#define CTBM_V2_OA_RES0_CTRL_OA0_PUMP_EN_Pos 11UL +#define CTBM_V2_OA_RES0_CTRL_OA0_PUMP_EN_Msk 0x800UL +#define CTBM_V2_OA_RES0_CTRL_OA0_BOOST_EN_Pos 12UL +#define CTBM_V2_OA_RES0_CTRL_OA0_BOOST_EN_Msk 0x1000UL +/* CTBM.OA_RES1_CTRL */ +#define CTBM_V2_OA_RES1_CTRL_OA1_PWR_MODE_Pos 0UL +#define CTBM_V2_OA_RES1_CTRL_OA1_PWR_MODE_Msk 0x7UL +#define CTBM_V2_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Pos 3UL +#define CTBM_V2_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Msk 0x8UL +#define CTBM_V2_OA_RES1_CTRL_OA1_COMP_EN_Pos 4UL +#define CTBM_V2_OA_RES1_CTRL_OA1_COMP_EN_Msk 0x10UL +#define CTBM_V2_OA_RES1_CTRL_OA1_HYST_EN_Pos 5UL +#define CTBM_V2_OA_RES1_CTRL_OA1_HYST_EN_Msk 0x20UL +#define CTBM_V2_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Pos 6UL +#define CTBM_V2_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk 0x40UL +#define CTBM_V2_OA_RES1_CTRL_OA1_DSI_LEVEL_Pos 7UL +#define CTBM_V2_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk 0x80UL +#define CTBM_V2_OA_RES1_CTRL_OA1_COMPINT_Pos 8UL +#define CTBM_V2_OA_RES1_CTRL_OA1_COMPINT_Msk 0x300UL +#define CTBM_V2_OA_RES1_CTRL_OA1_PUMP_EN_Pos 11UL +#define CTBM_V2_OA_RES1_CTRL_OA1_PUMP_EN_Msk 0x800UL +#define CTBM_V2_OA_RES1_CTRL_OA1_BOOST_EN_Pos 12UL +#define CTBM_V2_OA_RES1_CTRL_OA1_BOOST_EN_Msk 0x1000UL +/* CTBM.COMP_STAT */ +#define CTBM_V2_COMP_STAT_OA0_COMP_Pos 0UL +#define CTBM_V2_COMP_STAT_OA0_COMP_Msk 0x1UL +#define CTBM_V2_COMP_STAT_OA1_COMP_Pos 16UL +#define CTBM_V2_COMP_STAT_OA1_COMP_Msk 0x10000UL +/* CTBM.INTR */ +#define CTBM_V2_INTR_COMP0_Pos 0UL +#define CTBM_V2_INTR_COMP0_Msk 0x1UL +#define CTBM_V2_INTR_COMP1_Pos 1UL +#define CTBM_V2_INTR_COMP1_Msk 0x2UL +/* CTBM.INTR_SET */ +#define CTBM_V2_INTR_SET_COMP0_SET_Pos 0UL +#define CTBM_V2_INTR_SET_COMP0_SET_Msk 0x1UL +#define CTBM_V2_INTR_SET_COMP1_SET_Pos 1UL +#define CTBM_V2_INTR_SET_COMP1_SET_Msk 0x2UL +/* CTBM.INTR_MASK */ +#define CTBM_V2_INTR_MASK_COMP0_MASK_Pos 0UL +#define CTBM_V2_INTR_MASK_COMP0_MASK_Msk 0x1UL +#define CTBM_V2_INTR_MASK_COMP1_MASK_Pos 1UL +#define CTBM_V2_INTR_MASK_COMP1_MASK_Msk 0x2UL +/* CTBM.INTR_MASKED */ +#define CTBM_V2_INTR_MASKED_COMP0_MASKED_Pos 0UL +#define CTBM_V2_INTR_MASKED_COMP0_MASKED_Msk 0x1UL +#define CTBM_V2_INTR_MASKED_COMP1_MASKED_Pos 1UL +#define CTBM_V2_INTR_MASKED_COMP1_MASKED_Msk 0x2UL +/* CTBM.OA0_SW */ +#define CTBM_V2_OA0_SW_OA0P_A00_Pos 0UL +#define CTBM_V2_OA0_SW_OA0P_A00_Msk 0x1UL +#define CTBM_V2_OA0_SW_OA0P_A20_Pos 2UL +#define CTBM_V2_OA0_SW_OA0P_A20_Msk 0x4UL +#define CTBM_V2_OA0_SW_OA0P_A30_Pos 3UL +#define CTBM_V2_OA0_SW_OA0P_A30_Msk 0x8UL +#define CTBM_V2_OA0_SW_OA0M_A11_Pos 8UL +#define CTBM_V2_OA0_SW_OA0M_A11_Msk 0x100UL +#define CTBM_V2_OA0_SW_OA0M_A81_Pos 14UL +#define CTBM_V2_OA0_SW_OA0M_A81_Msk 0x4000UL +#define CTBM_V2_OA0_SW_OA0O_D51_Pos 18UL +#define CTBM_V2_OA0_SW_OA0O_D51_Msk 0x40000UL +#define CTBM_V2_OA0_SW_OA0O_D81_Pos 21UL +#define CTBM_V2_OA0_SW_OA0O_D81_Msk 0x200000UL +/* CTBM.OA0_SW_CLEAR */ +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A00_Pos 0UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A00_Msk 0x1UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A20_Pos 2UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A20_Msk 0x4UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A30_Pos 3UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A30_Msk 0x8UL +#define CTBM_V2_OA0_SW_CLEAR_OA0M_A11_Pos 8UL +#define CTBM_V2_OA0_SW_CLEAR_OA0M_A11_Msk 0x100UL +#define CTBM_V2_OA0_SW_CLEAR_OA0M_A81_Pos 14UL +#define CTBM_V2_OA0_SW_CLEAR_OA0M_A81_Msk 0x4000UL +#define CTBM_V2_OA0_SW_CLEAR_OA0O_D51_Pos 18UL +#define CTBM_V2_OA0_SW_CLEAR_OA0O_D51_Msk 0x40000UL +#define CTBM_V2_OA0_SW_CLEAR_OA0O_D81_Pos 21UL +#define CTBM_V2_OA0_SW_CLEAR_OA0O_D81_Msk 0x200000UL +/* CTBM.OA1_SW */ +#define CTBM_V2_OA1_SW_OA1P_A03_Pos 0UL +#define CTBM_V2_OA1_SW_OA1P_A03_Msk 0x1UL +#define CTBM_V2_OA1_SW_OA1P_A13_Pos 1UL +#define CTBM_V2_OA1_SW_OA1P_A13_Msk 0x2UL +#define CTBM_V2_OA1_SW_OA1P_A43_Pos 4UL +#define CTBM_V2_OA1_SW_OA1P_A43_Msk 0x10UL +#define CTBM_V2_OA1_SW_OA1P_A73_Pos 7UL +#define CTBM_V2_OA1_SW_OA1P_A73_Msk 0x80UL +#define CTBM_V2_OA1_SW_OA1M_A22_Pos 8UL +#define CTBM_V2_OA1_SW_OA1M_A22_Msk 0x100UL +#define CTBM_V2_OA1_SW_OA1M_A82_Pos 14UL +#define CTBM_V2_OA1_SW_OA1M_A82_Msk 0x4000UL +#define CTBM_V2_OA1_SW_OA1O_D52_Pos 18UL +#define CTBM_V2_OA1_SW_OA1O_D52_Msk 0x40000UL +#define CTBM_V2_OA1_SW_OA1O_D62_Pos 19UL +#define CTBM_V2_OA1_SW_OA1O_D62_Msk 0x80000UL +#define CTBM_V2_OA1_SW_OA1O_D82_Pos 21UL +#define CTBM_V2_OA1_SW_OA1O_D82_Msk 0x200000UL +/* CTBM.OA1_SW_CLEAR */ +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A03_Pos 0UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A03_Msk 0x1UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A13_Pos 1UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A13_Msk 0x2UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A43_Pos 4UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A43_Msk 0x10UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A73_Pos 7UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A73_Msk 0x80UL +#define CTBM_V2_OA1_SW_CLEAR_OA1M_A22_Pos 8UL +#define CTBM_V2_OA1_SW_CLEAR_OA1M_A22_Msk 0x100UL +#define CTBM_V2_OA1_SW_CLEAR_OA1M_A82_Pos 14UL +#define CTBM_V2_OA1_SW_CLEAR_OA1M_A82_Msk 0x4000UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D52_Pos 18UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D52_Msk 0x40000UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D62_Pos 19UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D62_Msk 0x80000UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D82_Pos 21UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D82_Msk 0x200000UL +/* CTBM.CTD_SW */ +#define CTBM_V2_CTD_SW_CTDD_CRD_Pos 1UL +#define CTBM_V2_CTD_SW_CTDD_CRD_Msk 0x2UL +#define CTBM_V2_CTD_SW_CTDS_CRS_Pos 4UL +#define CTBM_V2_CTD_SW_CTDS_CRS_Msk 0x10UL +#define CTBM_V2_CTD_SW_CTDS_COR_Pos 5UL +#define CTBM_V2_CTD_SW_CTDS_COR_Msk 0x20UL +#define CTBM_V2_CTD_SW_CTDO_C6H_Pos 8UL +#define CTBM_V2_CTD_SW_CTDO_C6H_Msk 0x100UL +#define CTBM_V2_CTD_SW_CTDO_COS_Pos 9UL +#define CTBM_V2_CTD_SW_CTDO_COS_Msk 0x200UL +#define CTBM_V2_CTD_SW_CTDH_COB_Pos 10UL +#define CTBM_V2_CTD_SW_CTDH_COB_Msk 0x400UL +#define CTBM_V2_CTD_SW_CTDH_CHD_Pos 12UL +#define CTBM_V2_CTD_SW_CTDH_CHD_Msk 0x1000UL +#define CTBM_V2_CTD_SW_CTDH_CA0_Pos 13UL +#define CTBM_V2_CTD_SW_CTDH_CA0_Msk 0x2000UL +#define CTBM_V2_CTD_SW_CTDH_CIS_Pos 14UL +#define CTBM_V2_CTD_SW_CTDH_CIS_Msk 0x4000UL +#define CTBM_V2_CTD_SW_CTDH_ILR_Pos 15UL +#define CTBM_V2_CTD_SW_CTDH_ILR_Msk 0x8000UL +/* CTBM.CTD_SW_CLEAR */ +#define CTBM_V2_CTD_SW_CLEAR_CTDD_CRD_Pos 1UL +#define CTBM_V2_CTD_SW_CLEAR_CTDD_CRD_Msk 0x2UL +#define CTBM_V2_CTD_SW_CLEAR_CTDS_CRS_Pos 4UL +#define CTBM_V2_CTD_SW_CLEAR_CTDS_CRS_Msk 0x10UL +#define CTBM_V2_CTD_SW_CLEAR_CTDS_COR_Pos 5UL +#define CTBM_V2_CTD_SW_CLEAR_CTDS_COR_Msk 0x20UL +#define CTBM_V2_CTD_SW_CLEAR_CTDO_C6H_Pos 8UL +#define CTBM_V2_CTD_SW_CLEAR_CTDO_C6H_Msk 0x100UL +#define CTBM_V2_CTD_SW_CLEAR_CTDO_COS_Pos 9UL +#define CTBM_V2_CTD_SW_CLEAR_CTDO_COS_Msk 0x200UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_COB_Pos 10UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_COB_Msk 0x400UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CHD_Pos 12UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CHD_Msk 0x1000UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CA0_Pos 13UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CA0_Msk 0x2000UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CIS_Pos 14UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CIS_Msk 0x4000UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_ILR_Pos 15UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_ILR_Msk 0x8000UL +/* CTBM.CTB_SW_DS_CTRL */ +#define CTBM_V2_CTB_SW_DS_CTRL_P2_DS_CTRL23_Pos 10UL +#define CTBM_V2_CTB_SW_DS_CTRL_P2_DS_CTRL23_Msk 0x400UL +#define CTBM_V2_CTB_SW_DS_CTRL_P3_DS_CTRL23_Pos 11UL +#define CTBM_V2_CTB_SW_DS_CTRL_P3_DS_CTRL23_Msk 0x800UL +#define CTBM_V2_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Pos 31UL +#define CTBM_V2_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Msk 0x80000000UL +/* CTBM.CTB_SW_SQ_CTRL */ +#define CTBM_V2_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Pos 10UL +#define CTBM_V2_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk 0x400UL +#define CTBM_V2_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Pos 11UL +#define CTBM_V2_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk 0x800UL +/* CTBM.CTB_SW_STATUS */ +#define CTBM_V2_CTB_SW_STATUS_OA0O_D51_STAT_Pos 28UL +#define CTBM_V2_CTB_SW_STATUS_OA0O_D51_STAT_Msk 0x10000000UL +#define CTBM_V2_CTB_SW_STATUS_OA1O_D52_STAT_Pos 29UL +#define CTBM_V2_CTB_SW_STATUS_OA1O_D52_STAT_Msk 0x20000000UL +#define CTBM_V2_CTB_SW_STATUS_OA1O_D62_STAT_Pos 30UL +#define CTBM_V2_CTB_SW_STATUS_OA1O_D62_STAT_Msk 0x40000000UL +#define CTBM_V2_CTB_SW_STATUS_CTD_COS_STAT_Pos 31UL +#define CTBM_V2_CTB_SW_STATUS_CTD_COS_STAT_Msk 0x80000000UL + + +#endif /* _CYIP_CTBM_V2_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_04.h new file mode 100644 index 0000000000..9e2a5d929a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_04.h @@ -0,0 +1,250 @@ +/***************************************************************************//** +* \file cyip_efuse_data_psoc6_04.h +* +* \brief +* EFUSE_DATA IP definitions +* +* \note +* Generator version: 1.5.1.21 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_EFUSE_DATA_PSOC6_04_H_ +#define _CYIP_EFUSE_DATA_PSOC6_04_H_ + +#include "cyip_headers.h" + +/** + * \brief Access restrictions for DEAD life cycle stage (DEAD_ACCESS_RESTRICT0) + */ +typedef struct { + uint8_t CM0_DISABLE; + uint8_t CM4_DISABLE; + uint8_t SYS_DISABLE; + uint8_t SYS_AP_MPU_ENABLE; + uint8_t SFLASH_ALLOWED[2]; + uint8_t MMIO_ALLOWED[2]; +} cy_stc_dead_access_restrict0_t; + +/** + * \brief Access restrictions for DEAD life cycle stage (DEAD_ACCESS_RESTRICT1) + */ +typedef struct { + uint8_t FLASH_ALLOWED[3]; + uint8_t SRAM_ALLOWED[3]; + uint8_t UNUSED; + uint8_t DIRECT_EXECUTE_DISABLE; +} cy_stc_dead_access_restrict1_t; + +/** + * \brief Access restrictions for SECURE life cycle stage (SECURE_ACCESS_RESTRICT0) + */ +typedef struct { + uint8_t CM0_DISABLE; + uint8_t CM4_DISABLE; + uint8_t SYS_DISABLE; + uint8_t SYS_AP_MPU_ENABLE; + uint8_t SFLASH_ALLOWED[2]; + uint8_t MMIO_ALLOWED[2]; +} cy_stc_secure_access_restrict0_t; + +/** + * \brief Access restrictions for SECURE life cycle stage (SECURE_ACCESS_RESTRICT1) + */ +typedef struct { + uint8_t FLASH_ALLOWED[3]; + uint8_t SRAM_ALLOWED[3]; + uint8_t UNUSED; + uint8_t DIRECT_EXECUTE_DISABLE; +} cy_stc_secure_access_restrict1_t; + +/** + * \brief NORMAL, SECURE_WITH_DEBUG, SECURE, and RMA fuse bits (LIFECYCLE_STAGE) + */ +typedef struct { + uint8_t NORMAL; + uint8_t SECURE_WITH_DEBUG; + uint8_t SECURE; + uint8_t RMA; + uint8_t RESERVED[4]; +} cy_stc_lifecycle_stage_t; + +/** + * \brief Cypress asset hash byte 0 (CY_ASSET_HASH0) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash0_t; + +/** + * \brief Cypress asset hash byte 1 (CY_ASSET_HASH1) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash1_t; + +/** + * \brief Cypress asset hash byte 2 (CY_ASSET_HASH2) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash2_t; + +/** + * \brief Cypress asset hash byte 3 (CY_ASSET_HASH3) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash3_t; + +/** + * \brief Cypress asset hash byte 4 (CY_ASSET_HASH4) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash4_t; + +/** + * \brief Cypress asset hash byte 5 (CY_ASSET_HASH5) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash5_t; + +/** + * \brief Cypress asset hash byte 6 (CY_ASSET_HASH6) + */ +typedef struct { + uint8_t CY_ASSET_HASH[8]; +} cy_stc_cy_asset_hash6_t; + +/** + * \brief Cypress asset hash byte 7 (CY_ASSET_HASH7) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash7_t; + +/** + * \brief Cypress asset hash byte 8 (CY_ASSET_HASH8) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash8_t; + +/** + * \brief Cypress asset hash byte 9 (CY_ASSET_HASH9) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash9_t; + +/** + * \brief Cypress asset hash byte 10 (CY_ASSET_HASH10) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash10_t; + +/** + * \brief Cypress asset hash byte 11 (CY_ASSET_HASH11) + */ +typedef struct { + uint8_t CY_ASSET_HASH[8]; +} cy_stc_cy_asset_hash11_t; + +/** + * \brief Cypress asset hash byte 12 (CY_ASSET_HASH12) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash12_t; + +/** + * \brief Cypress asset hash byte 13 (CY_ASSET_HASH13) + */ +typedef struct { + uint8_t CY_ASSET_HASH[8]; +} cy_stc_cy_asset_hash13_t; + +/** + * \brief Cypress asset hash byte 14 (CY_ASSET_HASH14) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash14_t; + +/** + * \brief Cypress asset hash byte 15 (CY_ASSET_HASH15) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash15_t; + +/** + * \brief Number of zeros in Cypress asset hash (CY_ASSET_HASH_ZEROS) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash_zeros_t; + +/** + * \brief Customer data (CUSTOMER_DATA) + */ +typedef struct { + uint8_t CUSTOMER_USE[8]; +} cy_stc_customer_data_t; + + +/** + * \brief eFUSE memory (EFUSE_DATA) + */ +typedef struct { + uint8_t RESERVED[312]; + cy_stc_dead_access_restrict0_t DEAD_ACCESS_RESTRICT0; + cy_stc_dead_access_restrict1_t DEAD_ACCESS_RESTRICT1; + cy_stc_secure_access_restrict0_t SECURE_ACCESS_RESTRICT0; + cy_stc_secure_access_restrict1_t SECURE_ACCESS_RESTRICT1; + cy_stc_lifecycle_stage_t LIFECYCLE_STAGE; + uint8_t RESERVED1[160]; + cy_stc_cy_asset_hash0_t CY_ASSET_HASH0; + cy_stc_cy_asset_hash1_t CY_ASSET_HASH1; + cy_stc_cy_asset_hash2_t CY_ASSET_HASH2; + cy_stc_cy_asset_hash3_t CY_ASSET_HASH3; + cy_stc_cy_asset_hash4_t CY_ASSET_HASH4; + cy_stc_cy_asset_hash5_t CY_ASSET_HASH5; + cy_stc_cy_asset_hash6_t CY_ASSET_HASH6; + cy_stc_cy_asset_hash7_t CY_ASSET_HASH7; + cy_stc_cy_asset_hash8_t CY_ASSET_HASH8; + cy_stc_cy_asset_hash9_t CY_ASSET_HASH9; + cy_stc_cy_asset_hash10_t CY_ASSET_HASH10; + cy_stc_cy_asset_hash11_t CY_ASSET_HASH11; + cy_stc_cy_asset_hash12_t CY_ASSET_HASH12; + cy_stc_cy_asset_hash13_t CY_ASSET_HASH13; + cy_stc_cy_asset_hash14_t CY_ASSET_HASH14; + cy_stc_cy_asset_hash15_t CY_ASSET_HASH15; + cy_stc_cy_asset_hash_zeros_t CY_ASSET_HASH_ZEROS; + cy_stc_customer_data_t CUSTOMER_DATA[47]; +} cy_stc_efuse_data_t; + + +#endif /* _CYIP_EFUSE_DATA_PSOC6_04_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h new file mode 100644 index 0000000000..5d104f621d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h @@ -0,0 +1,342 @@ +/***************************************************************************//** +* \file cyip_pass_v2.h +* +* \brief +* PASS IP definitions +* +* \note +* Generator version: 1.6.0.81 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_PASS_V2_H_ +#define _CYIP_PASS_V2_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_TIMER_V2_SECTION_SIZE 0x00000100UL +#define PASS_LPOSC_V2_SECTION_SIZE 0x00000100UL +#define PASS_FIFO_V2_SECTION_SIZE 0x00000100UL +#define PASS_AREFV2_V2_SECTION_SIZE 0x00000100UL +#define PASS_V2_SECTION_SIZE 0x00010000UL + +/** + * \brief Programmable Analog Subsystem (PASS_TIMER) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 Timer control register */ + __IOM uint32_t CONFIG; /*!< 0x00000004 Timer configuration register */ + __IOM uint32_t TIMER_PERIOD; /*!< 0x00000008 Timer period register */ + __IM uint32_t RESERVED[61]; +} PASS_TIMER_V2_Type; /*!< Size = 256 (0x100) */ + +/** + * \brief LPOSC configuration (PASS_LPOSC) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 Low Power Oscillator control */ + __IOM uint32_t CONFIG; /*!< 0x00000004 Low Power Oscillator configuration register */ + __IOM uint32_t ADFT; /*!< 0x00000008 Retention */ + __IM uint32_t RESERVED[61]; +} PASS_LPOSC_V2_Type; /*!< Size = 256 (0x100) */ + +/** + * \brief FIFO configuration (PASS_FIFO) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 FIFO control register */ + __IOM uint32_t CONFIG; /*!< 0x00000004 FIFO configuration register */ + __IM uint32_t STATUS; /*!< 0x00000008 FIFO status register */ + __IM uint32_t RD_DATA; /*!< 0x0000000C FIFO read data register */ + __IOM uint32_t INTR; /*!< 0x00000010 Interrupt register */ + __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked register */ + __IM uint32_t RESERVED[56]; +} PASS_FIFO_V2_Type; /*!< Size = 256 (0x100) */ + +/** + * \brief AREF configuration (PASS_AREFV2) + */ +typedef struct { + __IOM uint32_t AREF_CTRL; /*!< 0x00000000 global AREF control */ + __IM uint32_t RESERVED[63]; +} PASS_AREFV2_V2_Type; /*!< Size = 256 (0x100) */ + +/** + * \brief PASS top-level MMIO (AREF, LPOSC, FIFO, INTR, Trigger) (PASS) + */ +typedef struct { + __IM uint32_t INTR_CAUSE; /*!< 0x00000000 Interrupt cause register */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t DPSLP_CLOCK_SEL; /*!< 0x00000010 Deepsleep clock select */ + __IOM uint32_t PWR_WAKE_CTRL; /*!< 0x00000014 Deepsleep wakeup control */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t CTBM_CLOCK_SEL; /*!< 0x00000020 Clock select for CTBm */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t SAR_DPSLP_CTRL[2]; /*!< 0x00000030 Deepsleep control for SARv3 */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t SAR_DPSLP_CONFIG[2]; /*!< 0x00000040 Deepsleep configuration for SARv3 */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t SAR_HW_TR_SMP_CNT; /*!< 0x00000050 SAR HW trigger sample control */ + __IOM uint32_t SAR_HW_TR_CTRL; /*!< 0x00000054 SAR HW trigger override */ + __IOM uint32_t SAR_SIMULT_HW_TR_CTRL; /*!< 0x00000058 SAR simultaneous trigger control */ + __IOM uint32_t SAR_SIMULT_FW_START_CTRL; /*!< 0x0000005C SAR simultaneous start control */ + __IOM uint32_t SAR_TR_OUT_CTRL; /*!< 0x00000060 SAR trigger out control */ + __IM uint32_t RESERVED5[39]; + PASS_TIMER_V2_Type TIMER; /*!< 0x00000100 Programmable Analog Subsystem */ + PASS_LPOSC_V2_Type LPOSC; /*!< 0x00000200 LPOSC configuration */ + PASS_FIFO_V2_Type FIFO[2]; /*!< 0x00000300 FIFO configuration */ + __IM uint32_t RESERVED6[576]; + PASS_AREFV2_V2_Type AREFV2; /*!< 0x00000E00 AREF configuration */ + __IOM uint32_t VREF_TRIM0; /*!< 0x00000F00 VREF Trim bits */ + __IOM uint32_t VREF_TRIM1; /*!< 0x00000F04 VREF Trim bits */ + __IOM uint32_t VREF_TRIM2; /*!< 0x00000F08 VREF Trim bits */ + __IOM uint32_t VREF_TRIM3; /*!< 0x00000F0C VREF Trim bits */ + __IOM uint32_t IZTAT_TRIM0; /*!< 0x00000F10 VREF Trim bits */ + __IOM uint32_t IZTAT_TRIM1; /*!< 0x00000F14 IZTAT Trim bits */ + __IOM uint32_t IPTAT_TRIM0; /*!< 0x00000F18 IPTAT Trim bits */ + __IOM uint32_t ICTAT_TRIM0; /*!< 0x00000F1C ICTAT Trim bits */ +} PASS_V2_Type; /*!< Size = 3872 (0xF20) */ + + +/* PASS_TIMER.CTRL */ +#define PASS_TIMER_V2_CTRL_ENABLED_Pos 31UL +#define PASS_TIMER_V2_CTRL_ENABLED_Msk 0x80000000UL +/* PASS_TIMER.CONFIG */ +#define PASS_TIMER_V2_CONFIG_CLOCK_SEL_Pos 0UL +#define PASS_TIMER_V2_CONFIG_CLOCK_SEL_Msk 0x3UL +/* PASS_TIMER.TIMER_PERIOD */ +#define PASS_TIMER_V2_TIMER_PERIOD_PER_VAL_Pos 0UL +#define PASS_TIMER_V2_TIMER_PERIOD_PER_VAL_Msk 0xFFFFUL + + +/* PASS_LPOSC.CTRL */ +#define PASS_LPOSC_V2_CTRL_ENABLED_Pos 31UL +#define PASS_LPOSC_V2_CTRL_ENABLED_Msk 0x80000000UL +/* PASS_LPOSC.CONFIG */ +#define PASS_LPOSC_V2_CONFIG_DEEPSLEEP_MODE_Pos 0UL +#define PASS_LPOSC_V2_CONFIG_DEEPSLEEP_MODE_Msk 0x1UL +/* PASS_LPOSC.ADFT */ +#define PASS_LPOSC_V2_ADFT_ADFT_SEL_Pos 0UL +#define PASS_LPOSC_V2_ADFT_ADFT_SEL_Msk 0x3UL + + +/* PASS_FIFO.CTRL */ +#define PASS_FIFO_V2_CTRL_ENABLED_Pos 31UL +#define PASS_FIFO_V2_CTRL_ENABLED_Msk 0x80000000UL +/* PASS_FIFO.CONFIG */ +#define PASS_FIFO_V2_CONFIG_LEVEL_Pos 0UL +#define PASS_FIFO_V2_CONFIG_LEVEL_Msk 0xFFUL +#define PASS_FIFO_V2_CONFIG_CHAN_ID_EN_Pos 8UL +#define PASS_FIFO_V2_CONFIG_CHAN_ID_EN_Msk 0x100UL +#define PASS_FIFO_V2_CONFIG_CHAIN_EN_Pos 9UL +#define PASS_FIFO_V2_CONFIG_CHAIN_EN_Msk 0x200UL +/* PASS_FIFO.STATUS */ +#define PASS_FIFO_V2_STATUS_USED_Pos 0UL +#define PASS_FIFO_V2_STATUS_USED_Msk 0xFFUL +#define PASS_FIFO_V2_STATUS_RD_PTR_Pos 16UL +#define PASS_FIFO_V2_STATUS_RD_PTR_Msk 0xFF0000UL +#define PASS_FIFO_V2_STATUS_WR_PTR_Pos 24UL +#define PASS_FIFO_V2_STATUS_WR_PTR_Msk 0xFF000000UL +/* PASS_FIFO.RD_DATA */ +#define PASS_FIFO_V2_RD_DATA_RESULT_Pos 0UL +#define PASS_FIFO_V2_RD_DATA_RESULT_Msk 0xFFFFUL +#define PASS_FIFO_V2_RD_DATA_CHAN_ID_Pos 16UL +#define PASS_FIFO_V2_RD_DATA_CHAN_ID_Msk 0xF0000UL +/* PASS_FIFO.INTR */ +#define PASS_FIFO_V2_INTR_FIFO_LEVEL_Pos 0UL +#define PASS_FIFO_V2_INTR_FIFO_LEVEL_Msk 0x1UL +#define PASS_FIFO_V2_INTR_FIFO_OVERFLOW_Pos 1UL +#define PASS_FIFO_V2_INTR_FIFO_OVERFLOW_Msk 0x2UL +#define PASS_FIFO_V2_INTR_FIFO_UNDERFLOW_Pos 2UL +#define PASS_FIFO_V2_INTR_FIFO_UNDERFLOW_Msk 0x4UL +/* PASS_FIFO.INTR_SET */ +#define PASS_FIFO_V2_INTR_SET_FIFO_LEVEL_Pos 0UL +#define PASS_FIFO_V2_INTR_SET_FIFO_LEVEL_Msk 0x1UL +#define PASS_FIFO_V2_INTR_SET_FIFO_OVERFLOW_Pos 1UL +#define PASS_FIFO_V2_INTR_SET_FIFO_OVERFLOW_Msk 0x2UL +#define PASS_FIFO_V2_INTR_SET_FIFO_UNDERFLOW_Pos 2UL +#define PASS_FIFO_V2_INTR_SET_FIFO_UNDERFLOW_Msk 0x4UL +/* PASS_FIFO.INTR_MASK */ +#define PASS_FIFO_V2_INTR_MASK_FIFO_LEVEL_Pos 0UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_LEVEL_Msk 0x1UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_OVERFLOW_Pos 1UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_OVERFLOW_Msk 0x2UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_UNDERFLOW_Pos 2UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_UNDERFLOW_Msk 0x4UL +/* PASS_FIFO.INTR_MASKED */ +#define PASS_FIFO_V2_INTR_MASKED_FIFO_LEVEL_Pos 0UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_LEVEL_Msk 0x1UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_OVERFLOW_Pos 1UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_OVERFLOW_Msk 0x2UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_UNDERFLOW_Pos 2UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_UNDERFLOW_Msk 0x4UL + + +/* PASS_AREFV2.AREF_CTRL */ +#define PASS_AREFV2_V2_AREF_CTRL_AREF_MODE_Pos 0UL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_MODE_Msk 0x1UL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_BIAS_SCALE_Pos 2UL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_BIAS_SCALE_Msk 0xCUL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_RMB_Pos 4UL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_RMB_Msk 0x70UL +#define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_SCALE_Pos 7UL +#define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_SCALE_Msk 0x80UL +#define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_REDIRECT_Pos 8UL +#define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk 0xFF00UL +#define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SEL_Pos 16UL +#define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SEL_Msk 0x10000UL +#define PASS_AREFV2_V2_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos 19UL +#define PASS_AREFV2_V2_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Msk 0x80000UL +#define PASS_AREFV2_V2_AREF_CTRL_VREF_SEL_Pos 20UL +#define PASS_AREFV2_V2_AREF_CTRL_VREF_SEL_Msk 0x300000UL +#define PASS_AREFV2_V2_AREF_CTRL_LP_VREF_EN_Pos 22UL +#define PASS_AREFV2_V2_AREF_CTRL_LP_VREF_EN_Msk 0x400000UL +#define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SCALE_Pos 23UL +#define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SCALE_Msk 0x800000UL +#define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_MODE_Pos 28UL +#define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_MODE_Msk 0x30000000UL +#define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_ON_Pos 30UL +#define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL +#define PASS_AREFV2_V2_AREF_CTRL_ENABLED_Pos 31UL +#define PASS_AREFV2_V2_AREF_CTRL_ENABLED_Msk 0x80000000UL + + +/* PASS.INTR_CAUSE */ +#define PASS_V2_INTR_CAUSE_CTB0_INT_Pos 0UL +#define PASS_V2_INTR_CAUSE_CTB0_INT_Msk 0x1UL +#define PASS_V2_INTR_CAUSE_CTB1_INT_Pos 1UL +#define PASS_V2_INTR_CAUSE_CTB1_INT_Msk 0x2UL +#define PASS_V2_INTR_CAUSE_CTB2_INT_Pos 2UL +#define PASS_V2_INTR_CAUSE_CTB2_INT_Msk 0x4UL +#define PASS_V2_INTR_CAUSE_CTB3_INT_Pos 3UL +#define PASS_V2_INTR_CAUSE_CTB3_INT_Msk 0x8UL +#define PASS_V2_INTR_CAUSE_CTDAC0_INT_Pos 4UL +#define PASS_V2_INTR_CAUSE_CTDAC0_INT_Msk 0x10UL +#define PASS_V2_INTR_CAUSE_CTDAC1_INT_Pos 5UL +#define PASS_V2_INTR_CAUSE_CTDAC1_INT_Msk 0x20UL +#define PASS_V2_INTR_CAUSE_CTDAC2_INT_Pos 6UL +#define PASS_V2_INTR_CAUSE_CTDAC2_INT_Msk 0x40UL +#define PASS_V2_INTR_CAUSE_CTDAC3_INT_Pos 7UL +#define PASS_V2_INTR_CAUSE_CTDAC3_INT_Msk 0x80UL +#define PASS_V2_INTR_CAUSE_SAR0_INT_Pos 8UL +#define PASS_V2_INTR_CAUSE_SAR0_INT_Msk 0x100UL +#define PASS_V2_INTR_CAUSE_SAR1_INT_Pos 9UL +#define PASS_V2_INTR_CAUSE_SAR1_INT_Msk 0x200UL +#define PASS_V2_INTR_CAUSE_SAR2_INT_Pos 10UL +#define PASS_V2_INTR_CAUSE_SAR2_INT_Msk 0x400UL +#define PASS_V2_INTR_CAUSE_SAR3_INT_Pos 11UL +#define PASS_V2_INTR_CAUSE_SAR3_INT_Msk 0x800UL +#define PASS_V2_INTR_CAUSE_FIFO0_INT_Pos 12UL +#define PASS_V2_INTR_CAUSE_FIFO0_INT_Msk 0x1000UL +#define PASS_V2_INTR_CAUSE_FIFO1_INT_Pos 13UL +#define PASS_V2_INTR_CAUSE_FIFO1_INT_Msk 0x2000UL +#define PASS_V2_INTR_CAUSE_FIFO2_INT_Pos 14UL +#define PASS_V2_INTR_CAUSE_FIFO2_INT_Msk 0x4000UL +#define PASS_V2_INTR_CAUSE_FIFO3_INT_Pos 15UL +#define PASS_V2_INTR_CAUSE_FIFO3_INT_Msk 0x8000UL +/* PASS.DPSLP_CLOCK_SEL */ +#define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_SEL_Pos 0UL +#define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_SEL_Msk 0x1UL +#define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_DIV_Pos 4UL +#define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_DIV_Msk 0x70UL +/* PASS.PWR_WAKE_CTRL */ +#define PASS_V2_PWR_WAKE_CTRL_WAKE_DELAY_Pos 0UL +#define PASS_V2_PWR_WAKE_CTRL_WAKE_DELAY_Msk 0x3FUL +/* PASS.CTBM_CLOCK_SEL */ +#define PASS_V2_CTBM_CLOCK_SEL_PUMP_CLOCK_SEL_Pos 0UL +#define PASS_V2_CTBM_CLOCK_SEL_PUMP_CLOCK_SEL_Msk 0x1UL +/* PASS.SAR_DPSLP_CTRL */ +#define PASS_V2_SAR_DPSLP_CTRL_ENABLED_Pos 31UL +#define PASS_V2_SAR_DPSLP_CTRL_ENABLED_Msk 0x80000000UL +/* PASS.SAR_DPSLP_CONFIG */ +#define PASS_V2_SAR_DPSLP_CONFIG_DEEPSLEEP_ON_Pos 30UL +#define PASS_V2_SAR_DPSLP_CONFIG_DEEPSLEEP_ON_Msk 0x40000000UL +/* PASS.SAR_HW_TR_SMP_CNT */ +#define PASS_V2_SAR_HW_TR_SMP_CNT_SMP_CNT_Pos 0UL +#define PASS_V2_SAR_HW_TR_SMP_CNT_SMP_CNT_Msk 0x3FUL +/* PASS.SAR_HW_TR_CTRL */ +#define PASS_V2_SAR_HW_TR_CTRL_HW_TR_TIMER_SEL_Pos 0UL +#define PASS_V2_SAR_HW_TR_CTRL_HW_TR_TIMER_SEL_Msk 0xFUL +#define PASS_V2_SAR_HW_TR_CTRL_HW_TR_SMP_CNT_SEL_Pos 4UL +#define PASS_V2_SAR_HW_TR_CTRL_HW_TR_SMP_CNT_SEL_Msk 0xF0UL +/* PASS.SAR_SIMULT_HW_TR_CTRL */ +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_EN_Pos 0UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_EN_Msk 0xFUL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_SRC_Pos 4UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_SRC_Msk 0x30UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_TIMER_SEL_Pos 8UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_TIMER_SEL_Msk 0x100UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_LEVEL_Pos 18UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_LEVEL_Msk 0x40000UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_SYNC_TR_Pos 19UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_SYNC_TR_Msk 0x80000UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_SMP_CNT_SEL_Pos 20UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_SMP_CNT_SEL_Msk 0x100000UL +/* PASS.SAR_SIMULT_FW_START_CTRL */ +#define PASS_V2_SAR_SIMULT_FW_START_CTRL_FW_TRIGGER_Pos 0UL +#define PASS_V2_SAR_SIMULT_FW_START_CTRL_FW_TRIGGER_Msk 0xFUL +#define PASS_V2_SAR_SIMULT_FW_START_CTRL_CONTINUOUS_Pos 16UL +#define PASS_V2_SAR_SIMULT_FW_START_CTRL_CONTINUOUS_Msk 0xF0000UL +/* PASS.SAR_TR_OUT_CTRL */ +#define PASS_V2_SAR_TR_OUT_CTRL_SAR0_TR_OUT_SEL_Pos 0UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR0_TR_OUT_SEL_Msk 0x1UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR1_TR_OUT_SEL_Pos 1UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR1_TR_OUT_SEL_Msk 0x2UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR2_TR_OUT_SEL_Pos 2UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR2_TR_OUT_SEL_Msk 0x4UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR3_TR_OUT_SEL_Pos 3UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR3_TR_OUT_SEL_Msk 0x8UL +/* PASS.VREF_TRIM0 */ +#define PASS_V2_VREF_TRIM0_VREF_ABS_TRIM_Pos 0UL +#define PASS_V2_VREF_TRIM0_VREF_ABS_TRIM_Msk 0xFFUL +/* PASS.VREF_TRIM1 */ +#define PASS_V2_VREF_TRIM1_VREF_TEMPCO_TRIM_Pos 0UL +#define PASS_V2_VREF_TRIM1_VREF_TEMPCO_TRIM_Msk 0xFFUL +/* PASS.VREF_TRIM2 */ +#define PASS_V2_VREF_TRIM2_VREF_CURV_TRIM_Pos 0UL +#define PASS_V2_VREF_TRIM2_VREF_CURV_TRIM_Msk 0xFFUL +/* PASS.VREF_TRIM3 */ +#define PASS_V2_VREF_TRIM3_VREF_ATTEN_TRIM_Pos 0UL +#define PASS_V2_VREF_TRIM3_VREF_ATTEN_TRIM_Msk 0xFUL +/* PASS.IZTAT_TRIM0 */ +#define PASS_V2_IZTAT_TRIM0_IZTAT_ABS_TRIM_Pos 0UL +#define PASS_V2_IZTAT_TRIM0_IZTAT_ABS_TRIM_Msk 0xFFUL +/* PASS.IZTAT_TRIM1 */ +#define PASS_V2_IZTAT_TRIM1_IZTAT_TC_TRIM_Pos 0UL +#define PASS_V2_IZTAT_TRIM1_IZTAT_TC_TRIM_Msk 0xFFUL +/* PASS.IPTAT_TRIM0 */ +#define PASS_V2_IPTAT_TRIM0_IPTAT_CORE_TRIM_Pos 0UL +#define PASS_V2_IPTAT_TRIM0_IPTAT_CORE_TRIM_Msk 0xFUL +#define PASS_V2_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Pos 4UL +#define PASS_V2_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Msk 0xF0UL +/* PASS.ICTAT_TRIM0 */ +#define PASS_V2_ICTAT_TRIM0_ICTAT_TRIM_Pos 0UL +#define PASS_V2_ICTAT_TRIM0_ICTAT_TRIM_Msk 0xFUL + + +#endif /* _CYIP_PASS_V2_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h new file mode 100644 index 0000000000..40d096bbeb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h @@ -0,0 +1,563 @@ +/***************************************************************************//** +* \file cyip_sar_v2.h +* +* \brief +* SAR IP definitions +* +* \note +* Generator version: 1.5.1.36 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_SAR_V2_H_ +#define _CYIP_SAR_V2_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_V2_SECTION_SIZE 0x00010000UL + +/** + * \brief SAR ADC with Sequencer (SAR) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 Analog control register. */ + __IOM uint32_t SAMPLE_CTRL; /*!< 0x00000004 Sample control register. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t SAMPLE_TIME01; /*!< 0x00000010 Sample time specification ST0 and ST1 */ + __IOM uint32_t SAMPLE_TIME23; /*!< 0x00000014 Sample time specification ST2 and ST3 */ + __IOM uint32_t RANGE_THRES; /*!< 0x00000018 Global range detect threshold register. */ + __IOM uint32_t RANGE_COND; /*!< 0x0000001C Global range detect mode register. */ + __IOM uint32_t CHAN_EN; /*!< 0x00000020 Enable bits for the channels */ + __IOM uint32_t START_CTRL; /*!< 0x00000024 Start control register (firmware trigger). */ + __IM uint32_t RESERVED1[22]; + __IOM uint32_t CHAN_CONFIG[16]; /*!< 0x00000080 Channel configuration register. */ + __IM uint32_t RESERVED2[16]; + __IM uint32_t CHAN_WORK[16]; /*!< 0x00000100 Channel working data register */ + __IM uint32_t RESERVED3[16]; + __IM uint32_t CHAN_RESULT[16]; /*!< 0x00000180 Channel result data register */ + __IM uint32_t RESERVED4[16]; + __IM uint32_t CHAN_WORK_UPDATED; /*!< 0x00000200 Channel working data register 'updated' bits */ + __IM uint32_t CHAN_RESULT_UPDATED; /*!< 0x00000204 Channel result data register 'updated' bits */ + __IM uint32_t CHAN_WORK_NEWVALUE; /*!< 0x00000208 Channel working data register 'new value' bits */ + __IM uint32_t CHAN_RESULT_NEWVALUE; /*!< 0x0000020C Channel result data register 'new value' bits */ + __IOM uint32_t INTR; /*!< 0x00000210 Interrupt request register. */ + __IOM uint32_t INTR_SET; /*!< 0x00000214 Interrupt set request register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000218 Interrupt mask register. */ + __IM uint32_t INTR_MASKED; /*!< 0x0000021C Interrupt masked request register */ + __IOM uint32_t SATURATE_INTR; /*!< 0x00000220 Saturate interrupt request register. */ + __IOM uint32_t SATURATE_INTR_SET; /*!< 0x00000224 Saturate interrupt set request register */ + __IOM uint32_t SATURATE_INTR_MASK; /*!< 0x00000228 Saturate interrupt mask register. */ + __IM uint32_t SATURATE_INTR_MASKED; /*!< 0x0000022C Saturate interrupt masked request register */ + __IOM uint32_t RANGE_INTR; /*!< 0x00000230 Range detect interrupt request register. */ + __IOM uint32_t RANGE_INTR_SET; /*!< 0x00000234 Range detect interrupt set request register */ + __IOM uint32_t RANGE_INTR_MASK; /*!< 0x00000238 Range detect interrupt mask register. */ + __IM uint32_t RANGE_INTR_MASKED; /*!< 0x0000023C Range interrupt masked request register */ + __IM uint32_t INTR_CAUSE; /*!< 0x00000240 Interrupt cause register */ + __IM uint32_t RESERVED5[23]; + __IM uint32_t STATUS; /*!< 0x000002A0 Current status of internal SAR registers (mostly for debug) */ + __IM uint32_t AVG_STAT; /*!< 0x000002A4 Current averaging status (for debug) */ + __IM uint32_t RESERVED6[22]; + __IOM uint32_t MUX_SWITCH0; /*!< 0x00000300 SARMUX Firmware switch controls */ + __IOM uint32_t MUX_SWITCH_CLEAR0; /*!< 0x00000304 SARMUX Firmware switch control clear */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t MUX_SWITCH_SQ_CTRL; /*!< 0x00000344 SARMUX switch Sar Sequencer control */ + __IM uint32_t MUX_SWITCH_STATUS; /*!< 0x00000348 SARMUX switch status */ +} SAR_V2_Type; /*!< Size = 844 (0x34C) */ + + +/* SAR.CTRL */ +#define SAR_V2_CTRL_PWR_CTRL_VREF_Pos 0UL +#define SAR_V2_CTRL_PWR_CTRL_VREF_Msk 0x7UL +#define SAR_V2_CTRL_VREF_SEL_Pos 4UL +#define SAR_V2_CTRL_VREF_SEL_Msk 0x70UL +#define SAR_V2_CTRL_VREF_BYP_CAP_EN_Pos 7UL +#define SAR_V2_CTRL_VREF_BYP_CAP_EN_Msk 0x80UL +#define SAR_V2_CTRL_NEG_SEL_Pos 9UL +#define SAR_V2_CTRL_NEG_SEL_Msk 0xE00UL +#define SAR_V2_CTRL_SAR_HW_CTRL_NEGVREF_Pos 13UL +#define SAR_V2_CTRL_SAR_HW_CTRL_NEGVREF_Msk 0x2000UL +#define SAR_V2_CTRL_COMP_DLY_Pos 14UL +#define SAR_V2_CTRL_COMP_DLY_Msk 0xC000UL +#define SAR_V2_CTRL_SPARE_Pos 16UL +#define SAR_V2_CTRL_SPARE_Msk 0xF0000UL +#define SAR_V2_CTRL_BOOSTPUMP_EN_Pos 20UL +#define SAR_V2_CTRL_BOOSTPUMP_EN_Msk 0x100000UL +#define SAR_V2_CTRL_REFBUF_EN_Pos 21UL +#define SAR_V2_CTRL_REFBUF_EN_Msk 0x200000UL +#define SAR_V2_CTRL_COMP_PWR_Pos 24UL +#define SAR_V2_CTRL_COMP_PWR_Msk 0x7000000UL +#define SAR_V2_CTRL_DEEPSLEEP_ON_Pos 27UL +#define SAR_V2_CTRL_DEEPSLEEP_ON_Msk 0x8000000UL +#define SAR_V2_CTRL_DSI_SYNC_CONFIG_Pos 28UL +#define SAR_V2_CTRL_DSI_SYNC_CONFIG_Msk 0x10000000UL +#define SAR_V2_CTRL_DSI_MODE_Pos 29UL +#define SAR_V2_CTRL_DSI_MODE_Msk 0x20000000UL +#define SAR_V2_CTRL_SWITCH_DISABLE_Pos 30UL +#define SAR_V2_CTRL_SWITCH_DISABLE_Msk 0x40000000UL +#define SAR_V2_CTRL_ENABLED_Pos 31UL +#define SAR_V2_CTRL_ENABLED_Msk 0x80000000UL +/* SAR.SAMPLE_CTRL */ +#define SAR_V2_SAMPLE_CTRL_LEFT_ALIGN_Pos 1UL +#define SAR_V2_SAMPLE_CTRL_LEFT_ALIGN_Msk 0x2UL +#define SAR_V2_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Pos 2UL +#define SAR_V2_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk 0x4UL +#define SAR_V2_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Pos 3UL +#define SAR_V2_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Msk 0x8UL +#define SAR_V2_SAMPLE_CTRL_AVG_CNT_Pos 4UL +#define SAR_V2_SAMPLE_CTRL_AVG_CNT_Msk 0x70UL +#define SAR_V2_SAMPLE_CTRL_AVG_SHIFT_Pos 7UL +#define SAR_V2_SAMPLE_CTRL_AVG_SHIFT_Msk 0x80UL +#define SAR_V2_SAMPLE_CTRL_AVG_MODE_Pos 8UL +#define SAR_V2_SAMPLE_CTRL_AVG_MODE_Msk 0x100UL +#define SAR_V2_SAMPLE_CTRL_CONTINUOUS_Pos 16UL +#define SAR_V2_SAMPLE_CTRL_CONTINUOUS_Msk 0x10000UL +#define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_EN_Pos 17UL +#define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk 0x20000UL +#define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Pos 18UL +#define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Msk 0x40000UL +#define SAR_V2_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Pos 19UL +#define SAR_V2_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Msk 0x80000UL +#define SAR_V2_SAMPLE_CTRL_UAB_SCAN_MODE_Pos 22UL +#define SAR_V2_SAMPLE_CTRL_UAB_SCAN_MODE_Msk 0x400000UL +#define SAR_V2_SAMPLE_CTRL_REPEAT_INVALID_Pos 23UL +#define SAR_V2_SAMPLE_CTRL_REPEAT_INVALID_Msk 0x800000UL +#define SAR_V2_SAMPLE_CTRL_VALID_SEL_Pos 24UL +#define SAR_V2_SAMPLE_CTRL_VALID_SEL_Msk 0x7000000UL +#define SAR_V2_SAMPLE_CTRL_VALID_SEL_EN_Pos 27UL +#define SAR_V2_SAMPLE_CTRL_VALID_SEL_EN_Msk 0x8000000UL +#define SAR_V2_SAMPLE_CTRL_VALID_IGNORE_Pos 28UL +#define SAR_V2_SAMPLE_CTRL_VALID_IGNORE_Msk 0x10000000UL +#define SAR_V2_SAMPLE_CTRL_TRIGGER_OUT_EN_Pos 30UL +#define SAR_V2_SAMPLE_CTRL_TRIGGER_OUT_EN_Msk 0x40000000UL +#define SAR_V2_SAMPLE_CTRL_EOS_DSI_OUT_EN_Pos 31UL +#define SAR_V2_SAMPLE_CTRL_EOS_DSI_OUT_EN_Msk 0x80000000UL +/* SAR.SAMPLE_TIME01 */ +#define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME0_Pos 0UL +#define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME0_Msk 0x3FFUL +#define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME1_Pos 16UL +#define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME1_Msk 0x3FF0000UL +/* SAR.SAMPLE_TIME23 */ +#define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME2_Pos 0UL +#define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME2_Msk 0x3FFUL +#define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME3_Pos 16UL +#define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME3_Msk 0x3FF0000UL +/* SAR.RANGE_THRES */ +#define SAR_V2_RANGE_THRES_RANGE_LOW_Pos 0UL +#define SAR_V2_RANGE_THRES_RANGE_LOW_Msk 0xFFFFUL +#define SAR_V2_RANGE_THRES_RANGE_HIGH_Pos 16UL +#define SAR_V2_RANGE_THRES_RANGE_HIGH_Msk 0xFFFF0000UL +/* SAR.RANGE_COND */ +#define SAR_V2_RANGE_COND_RANGE_COND_Pos 30UL +#define SAR_V2_RANGE_COND_RANGE_COND_Msk 0xC0000000UL +/* SAR.CHAN_EN */ +#define SAR_V2_CHAN_EN_CHAN_EN_Pos 0UL +#define SAR_V2_CHAN_EN_CHAN_EN_Msk 0xFFFFUL +/* SAR.START_CTRL */ +#define SAR_V2_START_CTRL_FW_TRIGGER_Pos 0UL +#define SAR_V2_START_CTRL_FW_TRIGGER_Msk 0x1UL +/* SAR.CHAN_CONFIG */ +#define SAR_V2_CHAN_CONFIG_POS_PIN_ADDR_Pos 0UL +#define SAR_V2_CHAN_CONFIG_POS_PIN_ADDR_Msk 0x7UL +#define SAR_V2_CHAN_CONFIG_POS_PORT_ADDR_Pos 4UL +#define SAR_V2_CHAN_CONFIG_POS_PORT_ADDR_Msk 0x70UL +#define SAR_V2_CHAN_CONFIG_DIFFERENTIAL_EN_Pos 8UL +#define SAR_V2_CHAN_CONFIG_DIFFERENTIAL_EN_Msk 0x100UL +#define SAR_V2_CHAN_CONFIG_AVG_EN_Pos 10UL +#define SAR_V2_CHAN_CONFIG_AVG_EN_Msk 0x400UL +#define SAR_V2_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos 12UL +#define SAR_V2_CHAN_CONFIG_SAMPLE_TIME_SEL_Msk 0x3000UL +#define SAR_V2_CHAN_CONFIG_NEG_PIN_ADDR_Pos 16UL +#define SAR_V2_CHAN_CONFIG_NEG_PIN_ADDR_Msk 0x70000UL +#define SAR_V2_CHAN_CONFIG_NEG_PORT_ADDR_Pos 20UL +#define SAR_V2_CHAN_CONFIG_NEG_PORT_ADDR_Msk 0x700000UL +#define SAR_V2_CHAN_CONFIG_NEG_ADDR_EN_Pos 24UL +#define SAR_V2_CHAN_CONFIG_NEG_ADDR_EN_Msk 0x1000000UL +#define SAR_V2_CHAN_CONFIG_DSI_OUT_EN_Pos 31UL +#define SAR_V2_CHAN_CONFIG_DSI_OUT_EN_Msk 0x80000000UL +/* SAR.CHAN_WORK */ +#define SAR_V2_CHAN_WORK_WORK_Pos 0UL +#define SAR_V2_CHAN_WORK_WORK_Msk 0xFFFFUL +#define SAR_V2_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Pos 27UL +#define SAR_V2_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Msk 0x8000000UL +#define SAR_V2_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Pos 31UL +#define SAR_V2_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Msk 0x80000000UL +/* SAR.CHAN_RESULT */ +#define SAR_V2_CHAN_RESULT_RESULT_Pos 0UL +#define SAR_V2_CHAN_RESULT_RESULT_Msk 0xFFFFUL +#define SAR_V2_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Pos 27UL +#define SAR_V2_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Msk 0x8000000UL +#define SAR_V2_CHAN_RESULT_SATURATE_INTR_MIR_Pos 29UL +#define SAR_V2_CHAN_RESULT_SATURATE_INTR_MIR_Msk 0x20000000UL +#define SAR_V2_CHAN_RESULT_RANGE_INTR_MIR_Pos 30UL +#define SAR_V2_CHAN_RESULT_RANGE_INTR_MIR_Msk 0x40000000UL +#define SAR_V2_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Pos 31UL +#define SAR_V2_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Msk 0x80000000UL +/* SAR.CHAN_WORK_UPDATED */ +#define SAR_V2_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Pos 0UL +#define SAR_V2_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Msk 0xFFFFUL +/* SAR.CHAN_RESULT_UPDATED */ +#define SAR_V2_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Pos 0UL +#define SAR_V2_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Msk 0xFFFFUL +/* SAR.CHAN_WORK_NEWVALUE */ +#define SAR_V2_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Pos 0UL +#define SAR_V2_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Msk 0xFFFFUL +/* SAR.CHAN_RESULT_NEWVALUE */ +#define SAR_V2_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Pos 0UL +#define SAR_V2_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Msk 0xFFFFUL +/* SAR.INTR */ +#define SAR_V2_INTR_EOS_INTR_Pos 0UL +#define SAR_V2_INTR_EOS_INTR_Msk 0x1UL +#define SAR_V2_INTR_OVERFLOW_INTR_Pos 1UL +#define SAR_V2_INTR_OVERFLOW_INTR_Msk 0x2UL +#define SAR_V2_INTR_FW_COLLISION_INTR_Pos 2UL +#define SAR_V2_INTR_FW_COLLISION_INTR_Msk 0x4UL +#define SAR_V2_INTR_DSI_COLLISION_INTR_Pos 3UL +#define SAR_V2_INTR_DSI_COLLISION_INTR_Msk 0x8UL +#define SAR_V2_INTR_INJ_EOC_INTR_Pos 4UL +#define SAR_V2_INTR_INJ_EOC_INTR_Msk 0x10UL +#define SAR_V2_INTR_INJ_SATURATE_INTR_Pos 5UL +#define SAR_V2_INTR_INJ_SATURATE_INTR_Msk 0x20UL +#define SAR_V2_INTR_INJ_RANGE_INTR_Pos 6UL +#define SAR_V2_INTR_INJ_RANGE_INTR_Msk 0x40UL +#define SAR_V2_INTR_INJ_COLLISION_INTR_Pos 7UL +#define SAR_V2_INTR_INJ_COLLISION_INTR_Msk 0x80UL +/* SAR.INTR_SET */ +#define SAR_V2_INTR_SET_EOS_SET_Pos 0UL +#define SAR_V2_INTR_SET_EOS_SET_Msk 0x1UL +#define SAR_V2_INTR_SET_OVERFLOW_SET_Pos 1UL +#define SAR_V2_INTR_SET_OVERFLOW_SET_Msk 0x2UL +#define SAR_V2_INTR_SET_FW_COLLISION_SET_Pos 2UL +#define SAR_V2_INTR_SET_FW_COLLISION_SET_Msk 0x4UL +#define SAR_V2_INTR_SET_DSI_COLLISION_SET_Pos 3UL +#define SAR_V2_INTR_SET_DSI_COLLISION_SET_Msk 0x8UL +#define SAR_V2_INTR_SET_INJ_EOC_SET_Pos 4UL +#define SAR_V2_INTR_SET_INJ_EOC_SET_Msk 0x10UL +#define SAR_V2_INTR_SET_INJ_SATURATE_SET_Pos 5UL +#define SAR_V2_INTR_SET_INJ_SATURATE_SET_Msk 0x20UL +#define SAR_V2_INTR_SET_INJ_RANGE_SET_Pos 6UL +#define SAR_V2_INTR_SET_INJ_RANGE_SET_Msk 0x40UL +#define SAR_V2_INTR_SET_INJ_COLLISION_SET_Pos 7UL +#define SAR_V2_INTR_SET_INJ_COLLISION_SET_Msk 0x80UL +/* SAR.INTR_MASK */ +#define SAR_V2_INTR_MASK_EOS_MASK_Pos 0UL +#define SAR_V2_INTR_MASK_EOS_MASK_Msk 0x1UL +#define SAR_V2_INTR_MASK_OVERFLOW_MASK_Pos 1UL +#define SAR_V2_INTR_MASK_OVERFLOW_MASK_Msk 0x2UL +#define SAR_V2_INTR_MASK_FW_COLLISION_MASK_Pos 2UL +#define SAR_V2_INTR_MASK_FW_COLLISION_MASK_Msk 0x4UL +#define SAR_V2_INTR_MASK_DSI_COLLISION_MASK_Pos 3UL +#define SAR_V2_INTR_MASK_DSI_COLLISION_MASK_Msk 0x8UL +#define SAR_V2_INTR_MASK_INJ_EOC_MASK_Pos 4UL +#define SAR_V2_INTR_MASK_INJ_EOC_MASK_Msk 0x10UL +#define SAR_V2_INTR_MASK_INJ_SATURATE_MASK_Pos 5UL +#define SAR_V2_INTR_MASK_INJ_SATURATE_MASK_Msk 0x20UL +#define SAR_V2_INTR_MASK_INJ_RANGE_MASK_Pos 6UL +#define SAR_V2_INTR_MASK_INJ_RANGE_MASK_Msk 0x40UL +#define SAR_V2_INTR_MASK_INJ_COLLISION_MASK_Pos 7UL +#define SAR_V2_INTR_MASK_INJ_COLLISION_MASK_Msk 0x80UL +/* SAR.INTR_MASKED */ +#define SAR_V2_INTR_MASKED_EOS_MASKED_Pos 0UL +#define SAR_V2_INTR_MASKED_EOS_MASKED_Msk 0x1UL +#define SAR_V2_INTR_MASKED_OVERFLOW_MASKED_Pos 1UL +#define SAR_V2_INTR_MASKED_OVERFLOW_MASKED_Msk 0x2UL +#define SAR_V2_INTR_MASKED_FW_COLLISION_MASKED_Pos 2UL +#define SAR_V2_INTR_MASKED_FW_COLLISION_MASKED_Msk 0x4UL +#define SAR_V2_INTR_MASKED_DSI_COLLISION_MASKED_Pos 3UL +#define SAR_V2_INTR_MASKED_DSI_COLLISION_MASKED_Msk 0x8UL +#define SAR_V2_INTR_MASKED_INJ_EOC_MASKED_Pos 4UL +#define SAR_V2_INTR_MASKED_INJ_EOC_MASKED_Msk 0x10UL +#define SAR_V2_INTR_MASKED_INJ_SATURATE_MASKED_Pos 5UL +#define SAR_V2_INTR_MASKED_INJ_SATURATE_MASKED_Msk 0x20UL +#define SAR_V2_INTR_MASKED_INJ_RANGE_MASKED_Pos 6UL +#define SAR_V2_INTR_MASKED_INJ_RANGE_MASKED_Msk 0x40UL +#define SAR_V2_INTR_MASKED_INJ_COLLISION_MASKED_Pos 7UL +#define SAR_V2_INTR_MASKED_INJ_COLLISION_MASKED_Msk 0x80UL +/* SAR.SATURATE_INTR */ +#define SAR_V2_SATURATE_INTR_SATURATE_INTR_Pos 0UL +#define SAR_V2_SATURATE_INTR_SATURATE_INTR_Msk 0xFFFFUL +/* SAR.SATURATE_INTR_SET */ +#define SAR_V2_SATURATE_INTR_SET_SATURATE_SET_Pos 0UL +#define SAR_V2_SATURATE_INTR_SET_SATURATE_SET_Msk 0xFFFFUL +/* SAR.SATURATE_INTR_MASK */ +#define SAR_V2_SATURATE_INTR_MASK_SATURATE_MASK_Pos 0UL +#define SAR_V2_SATURATE_INTR_MASK_SATURATE_MASK_Msk 0xFFFFUL +/* SAR.SATURATE_INTR_MASKED */ +#define SAR_V2_SATURATE_INTR_MASKED_SATURATE_MASKED_Pos 0UL +#define SAR_V2_SATURATE_INTR_MASKED_SATURATE_MASKED_Msk 0xFFFFUL +/* SAR.RANGE_INTR */ +#define SAR_V2_RANGE_INTR_RANGE_INTR_Pos 0UL +#define SAR_V2_RANGE_INTR_RANGE_INTR_Msk 0xFFFFUL +/* SAR.RANGE_INTR_SET */ +#define SAR_V2_RANGE_INTR_SET_RANGE_SET_Pos 0UL +#define SAR_V2_RANGE_INTR_SET_RANGE_SET_Msk 0xFFFFUL +/* SAR.RANGE_INTR_MASK */ +#define SAR_V2_RANGE_INTR_MASK_RANGE_MASK_Pos 0UL +#define SAR_V2_RANGE_INTR_MASK_RANGE_MASK_Msk 0xFFFFUL +/* SAR.RANGE_INTR_MASKED */ +#define SAR_V2_RANGE_INTR_MASKED_RANGE_MASKED_Pos 0UL +#define SAR_V2_RANGE_INTR_MASKED_RANGE_MASKED_Msk 0xFFFFUL +/* SAR.INTR_CAUSE */ +#define SAR_V2_INTR_CAUSE_EOS_MASKED_MIR_Pos 0UL +#define SAR_V2_INTR_CAUSE_EOS_MASKED_MIR_Msk 0x1UL +#define SAR_V2_INTR_CAUSE_OVERFLOW_MASKED_MIR_Pos 1UL +#define SAR_V2_INTR_CAUSE_OVERFLOW_MASKED_MIR_Msk 0x2UL +#define SAR_V2_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Pos 2UL +#define SAR_V2_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Msk 0x4UL +#define SAR_V2_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Pos 3UL +#define SAR_V2_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Msk 0x8UL +#define SAR_V2_INTR_CAUSE_INJ_EOC_MASKED_MIR_Pos 4UL +#define SAR_V2_INTR_CAUSE_INJ_EOC_MASKED_MIR_Msk 0x10UL +#define SAR_V2_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Pos 5UL +#define SAR_V2_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Msk 0x20UL +#define SAR_V2_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Pos 6UL +#define SAR_V2_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Msk 0x40UL +#define SAR_V2_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Pos 7UL +#define SAR_V2_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Msk 0x80UL +#define SAR_V2_INTR_CAUSE_SATURATE_MASKED_RED_Pos 30UL +#define SAR_V2_INTR_CAUSE_SATURATE_MASKED_RED_Msk 0x40000000UL +#define SAR_V2_INTR_CAUSE_RANGE_MASKED_RED_Pos 31UL +#define SAR_V2_INTR_CAUSE_RANGE_MASKED_RED_Msk 0x80000000UL +/* SAR.STATUS */ +#define SAR_V2_STATUS_CUR_CHAN_Pos 0UL +#define SAR_V2_STATUS_CUR_CHAN_Msk 0x1FUL +#define SAR_V2_STATUS_SW_VREF_NEG_Pos 30UL +#define SAR_V2_STATUS_SW_VREF_NEG_Msk 0x40000000UL +#define SAR_V2_STATUS_BUSY_Pos 31UL +#define SAR_V2_STATUS_BUSY_Msk 0x80000000UL +/* SAR.AVG_STAT */ +#define SAR_V2_AVG_STAT_CUR_AVG_ACCU_Pos 0UL +#define SAR_V2_AVG_STAT_CUR_AVG_ACCU_Msk 0xFFFFFUL +#define SAR_V2_AVG_STAT_INTRLV_BUSY_Pos 23UL +#define SAR_V2_AVG_STAT_INTRLV_BUSY_Msk 0x800000UL +#define SAR_V2_AVG_STAT_CUR_AVG_CNT_Pos 24UL +#define SAR_V2_AVG_STAT_CUR_AVG_CNT_Msk 0xFF000000UL +/* SAR.MUX_SWITCH0 */ +#define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VPLUS_Pos 0UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VPLUS_Msk 0x1UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VPLUS_Pos 1UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VPLUS_Msk 0x2UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VPLUS_Pos 2UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VPLUS_Msk 0x4UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VPLUS_Pos 3UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VPLUS_Msk 0x8UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VPLUS_Pos 4UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VPLUS_Msk 0x10UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VPLUS_Pos 5UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VPLUS_Msk 0x20UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VPLUS_Pos 6UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VPLUS_Msk 0x40UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VPLUS_Pos 7UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VPLUS_Msk 0x80UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VMINUS_Pos 8UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VMINUS_Msk 0x100UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VMINUS_Pos 9UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VMINUS_Msk 0x200UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VMINUS_Pos 10UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VMINUS_Msk 0x400UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VMINUS_Pos 11UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VMINUS_Msk 0x800UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VMINUS_Pos 12UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VMINUS_Msk 0x1000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VMINUS_Pos 13UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VMINUS_Msk 0x2000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VMINUS_Pos 14UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VMINUS_Msk 0x4000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VMINUS_Pos 15UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VMINUS_Msk 0x8000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Pos 16UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Pos 17UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Pos 22UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Pos 23UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Pos 24UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Pos 25UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_COREIO0_Pos 26UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_COREIO0_Msk 0x4000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_COREIO1_Pos 27UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_COREIO1_Msk 0x8000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_COREIO2_Pos 28UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_COREIO2_Msk 0x10000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_COREIO3_Pos 29UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_COREIO3_Msk 0x20000000UL +/* SAR.MUX_SWITCH_CLEAR0 */ +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Pos 0UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Msk 0x1UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Pos 1UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Msk 0x2UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Pos 2UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Msk 0x4UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Pos 3UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Msk 0x8UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Pos 4UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Msk 0x10UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Pos 5UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Msk 0x20UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Pos 6UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Msk 0x40UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Pos 7UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Msk 0x80UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Pos 8UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Msk 0x100UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Pos 9UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Msk 0x200UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Pos 10UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Msk 0x400UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Pos 11UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Msk 0x800UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Pos 12UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Msk 0x1000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Pos 13UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Msk 0x2000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Pos 14UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Msk 0x4000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Pos 15UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Msk 0x8000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Pos 16UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Pos 17UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Pos 22UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Pos 23UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Pos 24UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Pos 25UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Pos 26UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Msk 0x4000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Pos 27UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Msk 0x8000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Pos 28UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Msk 0x10000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Pos 29UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Msk 0x20000000UL +/* SAR.MUX_SWITCH_SQ_CTRL */ +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Pos 0UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Msk 0x1UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Pos 1UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Msk 0x2UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Pos 2UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Msk 0x4UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Pos 3UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Msk 0x8UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Pos 4UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Msk 0x10UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Pos 5UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Msk 0x20UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Pos 6UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Msk 0x40UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Pos 7UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Msk 0x80UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Pos 16UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk 0x10000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Pos 17UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Msk 0x20000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Pos 18UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Msk 0x40000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Pos 19UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Msk 0x80000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Pos 22UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Msk 0x400000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Pos 23UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Msk 0x800000UL +/* SAR.MUX_SWITCH_STATUS */ +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Pos 0UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Msk 0x1UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Pos 1UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Msk 0x2UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Pos 2UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Msk 0x4UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Pos 3UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Msk 0x8UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Pos 4UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Msk 0x10UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Pos 5UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Msk 0x20UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Pos 6UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Msk 0x40UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Pos 7UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Msk 0x80UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Pos 8UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Msk 0x100UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Pos 9UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Msk 0x200UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Pos 10UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Msk 0x400UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Pos 11UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Msk 0x800UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Pos 12UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Msk 0x1000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Pos 13UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Msk 0x2000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Pos 14UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Msk 0x4000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Pos 15UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Msk 0x8000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Pos 16UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Msk 0x10000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Pos 17UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Msk 0x20000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Pos 22UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Pos 23UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Pos 24UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Pos 25UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL + + +#endif /* _CYIP_SAR_V2_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h index f824008671..16fcf8f444 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h @@ -5,7 +5,7 @@ * SFLASH IP definitions * * \note -* Generator version: 1.5.0.1287 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -47,7 +47,14 @@ typedef struct { __IOM uint16_t FAMILY_ID; /*!< 0x0000000C Indicates Family ID of the device */ __IM uint16_t RESERVED2[3]; __IOM uint32_t CPUSS_WOUNDING; /*!< 0x00000014 CPUSS Wounding */ - __IM uint32_t RESERVED3[378]; + __IM uint32_t RESERVED3[2]; + __IOM uint8_t SORT_REV[3]; /*!< 0x00000020 SORT Revision */ + __IOM uint8_t CRI_BB_REV; /*!< 0x00000023 CRI BB Revision */ + __IOM uint8_t CRI_AB_REV; /*!< 0x00000024 CRI AB Revision */ + __IOM uint8_t CHI_AB_REV; /*!< 0x00000025 CHI AB Revision */ + __IM uint16_t RESERVED4[43]; + __IOM uint32_t FB_FLAGS; /*!< 0x0000007C Flash boot flags */ + __IM uint32_t RESERVED5[352]; __IOM uint8_t DIE_LOT[3]; /*!< 0x00000600 Lot Number (3 bytes) */ __IOM uint8_t DIE_WAFER; /*!< 0x00000603 Wafer Number */ __IOM uint8_t DIE_X; /*!< 0x00000604 X Position on Wafer, CRI Pass/Fail Bin */ @@ -57,20 +64,20 @@ typedef struct { __IOM uint8_t DIE_DAY; /*!< 0x00000608 Day number */ __IOM uint8_t DIE_MONTH; /*!< 0x00000609 Month number */ __IOM uint8_t DIE_YEAR; /*!< 0x0000060A Year number */ - __IM uint8_t RESERVED4[61]; + __IM uint8_t RESERVED6[61]; __IOM uint16_t SAR_TEMP_MULTIPLIER; /*!< 0x00000648 SAR Temperature Sensor Multiplication Factor */ __IOM uint16_t SAR_TEMP_OFFSET; /*!< 0x0000064A SAR Temperature Sensor Offset */ - __IM uint32_t RESERVED5[8]; + __IM uint32_t RESERVED7[8]; __IOM uint32_t CSP_PANEL_ID; /*!< 0x0000066C CSP Panel Id to record panel ID of CSP die */ - __IM uint32_t RESERVED6[52]; + __IM uint32_t RESERVED8[52]; __IOM uint8_t LDO_0P9V_TRIM; /*!< 0x00000740 LDO_0P9V_TRIM */ __IOM uint8_t LDO_1P1V_TRIM; /*!< 0x00000741 LDO_1P1V_TRIM */ - __IM uint16_t RESERVED7[95]; + __IM uint16_t RESERVED9[95]; __IOM uint32_t BLE_DEVICE_ADDRESS[128]; /*!< 0x00000800 BLE_DEVICE_ADDRESS */ __IOM uint32_t USER_FREE_ROW1[128]; /*!< 0x00000A00 USER_FREE_ROW1 */ __IOM uint32_t USER_FREE_ROW2[128]; /*!< 0x00000C00 USER_FREE_ROW2 */ __IOM uint32_t USER_FREE_ROW3[128]; /*!< 0x00000E00 USER_FREE_ROW3 */ - __IM uint32_t RESERVED8[302]; + __IM uint32_t RESERVED10[302]; __IOM uint8_t DEVICE_UID[16]; /*!< 0x000014B8 Unique Identifier Number for each device */ __IOM uint8_t MASTER_KEY[16]; /*!< 0x000014C8 Master key to change other keys */ __IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ADDR[16]; /*!< 0x000014D8 Standard SMPU STRUCT Slave Address value */ @@ -78,36 +85,36 @@ typedef struct { __IOM uint32_t STANDARD_SMPU_STRUCT_MASTER_ATTR[16]; /*!< 0x00001558 Standard SMPU STRUCT Master Attribute value */ __IOM uint32_t STANDARD_MPU_STRUCT[16]; /*!< 0x00001598 Standard MPU STRUCT */ __IOM uint32_t STANDARD_PPU_STRUCT[16]; /*!< 0x000015D8 Standard PPU STRUCT */ - __IM uint32_t RESERVED9[122]; + __IM uint32_t RESERVED11[122]; __IOM uint16_t PILO_FREQ_STEP; /*!< 0x00001800 Resolution step for PILO at class in BCD format */ - __IM uint16_t RESERVED10; + __IM uint16_t RESERVED12; __IOM uint32_t CSDV2_CSD0_ADC_VREF0; /*!< 0x00001804 CSD 1p2 & 1p6 voltage levels for accuracy */ __IOM uint32_t CSDV2_CSD0_ADC_VREF1; /*!< 0x00001808 CSD 2p1 & 0p8 voltage levels for accuracy */ __IOM uint32_t CSDV2_CSD0_ADC_VREF2; /*!< 0x0000180C CSD calibration spare voltage level for accuracy */ __IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00001810 Wakeup delay */ - __IM uint16_t RESERVED11; + __IM uint16_t RESERVED13; __IOM uint16_t RADIO_LDO_TRIMS; /*!< 0x00001816 Radio LDO Trims */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_ULP; /*!< 0x00001818 CPUSS TRIM ROM CTL ULP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_ULP; /*!< 0x0000181C CPUSS TRIM RAM CTL ULP value */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_LP; /*!< 0x00001820 CPUSS TRIM ROM CTL LP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_LP; /*!< 0x00001824 CPUSS TRIM RAM CTL LP value */ - __IM uint32_t RESERVED12[7]; + __IM uint32_t RESERVED14[7]; __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_ULP; /*!< 0x00001844 CPUSS TRIM ROM CTL HALF ULP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_ULP; /*!< 0x00001848 CPUSS TRIM RAM CTL HALF ULP value */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_LP; /*!< 0x0000184C CPUSS TRIM ROM CTL HALF LP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_LP; /*!< 0x00001850 CPUSS TRIM RAM CTL HALF LP value */ - __IM uint32_t RESERVED13[491]; + __IM uint32_t RESERVED15[491]; __IOM uint32_t FLASH_BOOT_OBJECT_SIZE; /*!< 0x00002000 Flash Boot - Object Size */ __IOM uint32_t FLASH_BOOT_APP_ID; /*!< 0x00002004 Flash Boot - Application ID/Version */ __IOM uint32_t FLASH_BOOT_ATTRIBUTE; /*!< 0x00002008 N/A */ __IOM uint32_t FLASH_BOOT_N_CORES; /*!< 0x0000200C Flash Boot - Number of Cores(N) */ __IOM uint32_t FLASH_BOOT_VT_OFFSET; /*!< 0x00002010 Flash Boot - Core Vector Table offset */ __IOM uint32_t FLASH_BOOT_CORE_CPUID; /*!< 0x00002014 Flash Boot - Core CPU ID/Core Index */ - __IM uint32_t RESERVED14[48]; + __IM uint32_t RESERVED16[48]; __IOM uint8_t FLASH_BOOT_CODE[14632]; /*!< 0x000020D8 Flash Boot - Code and Data */ __IOM uint8_t PUBLIC_KEY[3072]; /*!< 0x00005A00 Public key for signature verification (max RSA key size 4096) */ __IOM uint32_t BOOT_PROT_SETTINGS[384]; /*!< 0x00006600 Boot protection settings (not present in PSOC6ABLE2) */ - __IM uint32_t RESERVED15[768]; + __IM uint32_t RESERVED17[768]; __IOM uint32_t TOC1_OBJECT_SIZE; /*!< 0x00007800 Object size in bytes for CRC calculation starting from offset 0x00 */ __IOM uint32_t TOC1_MAGIC_NUMBER; /*!< 0x00007804 Magic number(0x01211219) */ @@ -118,7 +125,7 @@ typedef struct { __IOM uint32_t TOC1_FB_OBJECT_ADDR; /*!< 0x00007814 Addresss of FLASH Boot(FB) object that include FLASH patch also */ __IOM uint32_t TOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007818 Unused (Address is Hardcoded in ROM) */ __IOM uint32_t TOC1_OBJECT_ADDR_UNUSED; /*!< 0x0000781C Unused (Address is Hardcoded in ROM) */ - __IM uint32_t RESERVED16[119]; + __IM uint32_t RESERVED18[119]; __IOM uint32_t TOC1_CRC_ADDR; /*!< 0x000079FC Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ __IOM uint32_t RTOC1_OBJECT_SIZE; /*!< 0x00007A00 Redundant Object size in bytes for CRC calculation starting from offset 0x00 */ @@ -131,7 +138,7 @@ typedef struct { patch also */ __IOM uint32_t RTOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007A18 Redundant Unused (Address is Hardcoded in ROM) */ __IOM uint32_t RTOC1_OBJECT_ADDR_UNUSED; /*!< 0x00007A1C Redundant Unused (Address is Hardcoded in ROM) */ - __IM uint32_t RESERVED17[119]; + __IM uint32_t RESERVED19[119]; __IOM uint32_t RTOC1_CRC_ADDR; /*!< 0x00007BFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ __IOM uint32_t TOC2_OBJECT_SIZE; /*!< 0x00007C00 Object size in bytes for CRC calculation starting from offset @@ -151,7 +158,7 @@ typedef struct { SECURE_HASH(SHASH) */ __IOM uint32_t TOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007C24 Address of signature verification key (0 if none).The object is signature specific key. It is the public key in case of RSA */ - __IM uint32_t RESERVED18[115]; + __IM uint32_t RESERVED20[115]; __IOM uint32_t TOC2_REVISION; /*!< 0x00007DF4 Indicates TOC2 Revision. It is not used now. */ __IOM uint32_t TOC2_FLAGS; /*!< 0x00007DF8 TOC2_FLAGS */ __IOM uint32_t TOC2_CRC_ADDR; /*!< 0x00007DFC CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ @@ -173,7 +180,7 @@ typedef struct { __IOM uint32_t RTOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007E24 Redundant Address of signature verification key (0 if none).The object is signature specific key. It is the public key in case of RSA */ - __IM uint32_t RESERVED19[115]; + __IM uint32_t RESERVED21[115]; __IOM uint32_t RTOC2_REVISION; /*!< 0x00007FF4 Indicates RTOC2 Revision. It is not used now. */ __IOM uint32_t RTOC2_FLAGS; /*!< 0x00007FF8 RTOC2_FLAGS */ __IOM uint32_t RTOC2_CRC_ADDR; /*!< 0x00007FFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 @@ -193,6 +200,25 @@ typedef struct { /* SFLASH.CPUSS_WOUNDING */ #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Pos 0UL #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Msk 0xFFFFFFFFUL +/* SFLASH.SORT_REV */ +#define SFLASH_SORT_REV_DATA_Pos 0UL +#define SFLASH_SORT_REV_DATA_Msk 0xFFUL +/* SFLASH.CRI_BB_REV */ +#define SFLASH_CRI_BB_REV_DATA_Pos 0UL +#define SFLASH_CRI_BB_REV_DATA_Msk 0xFFUL +/* SFLASH.CRI_AB_REV */ +#define SFLASH_CRI_AB_REV_DATA_Pos 0UL +#define SFLASH_CRI_AB_REV_DATA_Msk 0xFFUL +/* SFLASH.CHI_AB_REV */ +#define SFLASH_CHI_AB_REV_DATA_Pos 0UL +#define SFLASH_CHI_AB_REV_DATA_Msk 0xFFUL +/* SFLASH.FB_FLAGS */ +#define SFLASH_FB_FLAGS_FB_PIN_CTL_Pos 0UL +#define SFLASH_FB_FLAGS_FB_PIN_CTL_Msk 0x3UL +#define SFLASH_FB_FLAGS_FB_RSA3K_CTL_Pos 2UL +#define SFLASH_FB_FLAGS_FB_RSA3K_CTL_Msk 0xCUL +#define SFLASH_FB_FLAGS_FB_RSA4K_CTL_Pos 4UL +#define SFLASH_FB_FLAGS_FB_RSA4K_CTL_Msk 0x30UL /* SFLASH.DIE_LOT */ #define SFLASH_DIE_LOT_LOT_Pos 0UL #define SFLASH_DIE_LOT_LOT_Msk 0xFFUL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_tcpwm_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_tcpwm_v2.h new file mode 100644 index 0000000000..fadb32dcaf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_tcpwm_v2.h @@ -0,0 +1,272 @@ +/***************************************************************************//** +* \file cyip_tcpwm_v2.h +* +* \brief +* TCPWM IP definitions +* +* \note +* Generator version: 1.5.1.36 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_TCPWM_V2_H_ +#define _CYIP_TCPWM_V2_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM_GRP_CNT_V2_SECTION_SIZE 0x00000080UL +#define TCPWM_GRP_V2_SECTION_SIZE 0x00008000UL +#define TCPWM_V2_SECTION_SIZE 0x00020000UL + +/** + * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 Counter control register */ + __IM uint32_t STATUS; /*!< 0x00000004 Counter status register */ + __IOM uint32_t COUNTER; /*!< 0x00000008 Counter count register */ + __IM uint32_t RESERVED; + __IOM uint32_t CC0; /*!< 0x00000010 Counter compare/capture 0 register */ + __IOM uint32_t CC0_BUFF; /*!< 0x00000014 Counter buffered compare/capture 0 register */ + __IOM uint32_t CC1; /*!< 0x00000018 Counter compare/capture 1 register */ + __IOM uint32_t CC1_BUFF; /*!< 0x0000001C Counter buffered compare/capture 1 register */ + __IOM uint32_t PERIOD; /*!< 0x00000020 Counter period register */ + __IOM uint32_t PERIOD_BUFF; /*!< 0x00000024 Counter buffered period register */ + __IOM uint32_t LINE_SEL; /*!< 0x00000028 Counter line selection register */ + __IOM uint32_t LINE_SEL_BUFF; /*!< 0x0000002C Counter buffered line selection register */ + __IOM uint32_t DT; /*!< 0x00000030 Counter PWM dead time register */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t TR_CMD; /*!< 0x00000040 Counter trigger command register */ + __IOM uint32_t TR_IN_SEL0; /*!< 0x00000044 Counter input trigger selection register 0 */ + __IOM uint32_t TR_IN_SEL1; /*!< 0x00000048 Counter input trigger selection register 1 */ + __IOM uint32_t TR_IN_EDGE_SEL; /*!< 0x0000004C Counter input trigger edge selection register */ + __IOM uint32_t TR_PWM_CTRL; /*!< 0x00000050 Counter trigger PWM control register */ + __IOM uint32_t TR_OUT_SEL; /*!< 0x00000054 Counter output trigger selection register */ + __IM uint32_t RESERVED2[6]; + __IOM uint32_t INTR; /*!< 0x00000070 Interrupt request register */ + __IOM uint32_t INTR_SET; /*!< 0x00000074 Interrupt set request register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000078 Interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x0000007C Interrupt masked request register */ +} TCPWM_GRP_CNT_V2_Type; /*!< Size = 128 (0x80) */ + +/** + * \brief Group of counters (TCPWM_GRP) + */ +typedef struct { + TCPWM_GRP_CNT_V2_Type CNT[256]; /*!< 0x00000000 Timer/Counter/PWM Counter Module */ +} TCPWM_GRP_V2_Type; /*!< Size = 32768 (0x8000) */ + +/** + * \brief Timer/Counter/PWM (TCPWM) + */ +typedef struct { + TCPWM_GRP_V2_Type GRP[4]; /*!< 0x00000000 Group of counters */ +} TCPWM_V2_Type; /*!< Size = 131072 (0x20000) */ + + +/* TCPWM_GRP_CNT.CTRL */ +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Pos 0UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Pos 1UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Pos 2UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Msk 0x4UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Pos 3UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Msk 0x8UL +#define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Pos 4UL +#define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Msk 0x10UL +#define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Pos 5UL +#define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Msk 0x20UL +#define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Pos 6UL +#define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Msk 0x40UL +#define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Pos 7UL +#define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Msk 0x80UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Pos 8UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Msk 0x100UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Pos 9UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Msk 0x200UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Pos 10UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Msk 0x400UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Pos 12UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Msk 0x3000UL +#define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Pos 16UL +#define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Msk 0x30000UL +#define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Pos 18UL +#define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Msk 0x40000UL +#define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Pos 20UL +#define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk 0x300000UL +#define TCPWM_GRP_CNT_V2_CTRL_MODE_Pos 24UL +#define TCPWM_GRP_CNT_V2_CTRL_MODE_Msk 0x7000000UL +#define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Pos 30UL +#define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Msk 0x40000000UL +#define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Pos 31UL +#define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Msk 0x80000000UL +/* TCPWM_GRP_CNT.STATUS */ +#define TCPWM_GRP_CNT_V2_STATUS_DOWN_Pos 0UL +#define TCPWM_GRP_CNT_V2_STATUS_DOWN_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Pos 4UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Msk 0x10UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Pos 5UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Msk 0x20UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Pos 6UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Msk 0x40UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Pos 7UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Msk 0x80UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_START_Pos 8UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_START_Msk 0x100UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Pos 9UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Msk 0x200UL +#define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Pos 10UL +#define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Msk 0x400UL +#define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Pos 11UL +#define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Msk 0x800UL +#define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Pos 15UL +#define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Msk 0x8000UL +#define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Pos 16UL +#define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Msk 0xFF0000UL +#define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Pos 24UL +#define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Msk 0xFF000000UL +/* TCPWM_GRP_CNT.COUNTER */ +#define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Pos 0UL +#define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.CC0 */ +#define TCPWM_GRP_CNT_V2_CC0_CC_Pos 0UL +#define TCPWM_GRP_CNT_V2_CC0_CC_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.CC0_BUFF */ +#define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Pos 0UL +#define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.CC1 */ +#define TCPWM_GRP_CNT_V2_CC1_CC_Pos 0UL +#define TCPWM_GRP_CNT_V2_CC1_CC_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.CC1_BUFF */ +#define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Pos 0UL +#define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.PERIOD */ +#define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Pos 0UL +#define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.PERIOD_BUFF */ +#define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Pos 0UL +#define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.LINE_SEL */ +#define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Pos 0UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Msk 0x7UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Pos 4UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Msk 0x70UL +/* TCPWM_GRP_CNT.LINE_SEL_BUFF */ +#define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Pos 0UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Msk 0x7UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos 4UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk 0x70UL +/* TCPWM_GRP_CNT.DT */ +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Pos 0UL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Msk 0xFFUL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Pos 8UL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Msk 0xFF00UL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Pos 16UL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Msk 0xFFFF0000UL +/* TCPWM_GRP_CNT.TR_CMD */ +#define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Pos 2UL +#define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Msk 0x4UL +#define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Pos 3UL +#define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Msk 0x8UL +#define TCPWM_GRP_CNT_V2_TR_CMD_START_Pos 4UL +#define TCPWM_GRP_CNT_V2_TR_CMD_START_Msk 0x10UL +#define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Pos 5UL +#define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Msk 0x20UL +/* TCPWM_GRP_CNT.TR_IN_SEL0 */ +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Msk 0xFFUL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Pos 8UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Msk 0xFF00UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Pos 16UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Msk 0xFF0000UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Pos 24UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Msk 0xFF000000UL +/* TCPWM_GRP_CNT.TR_IN_SEL1 */ +#define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Msk 0xFFUL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Pos 8UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Msk 0xFF00UL +/* TCPWM_GRP_CNT.TR_IN_EDGE_SEL */ +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk 0x3UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Pos 2UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Msk 0xCUL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos 4UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk 0x30UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Pos 6UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Msk 0xC0UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Pos 8UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Msk 0x300UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos 10UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk 0xC00UL +/* TCPWM_GRP_CNT.TR_PWM_CTRL */ +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Msk 0x3UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Pos 2UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Msk 0xCUL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Pos 4UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Msk 0x30UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Pos 6UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Msk 0xC0UL +/* TCPWM_GRP_CNT.TR_OUT_SEL */ +#define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Msk 0x7UL +#define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Pos 4UL +#define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Msk 0x70UL +/* TCPWM_GRP_CNT.INTR */ +#define TCPWM_GRP_CNT_V2_INTR_TC_Pos 0UL +#define TCPWM_GRP_CNT_V2_INTR_TC_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Pos 1UL +#define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Pos 2UL +#define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Msk 0x4UL +/* TCPWM_GRP_CNT.INTR_SET */ +#define TCPWM_GRP_CNT_V2_INTR_SET_TC_Pos 0UL +#define TCPWM_GRP_CNT_V2_INTR_SET_TC_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Pos 1UL +#define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Pos 2UL +#define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Msk 0x4UL +/* TCPWM_GRP_CNT.INTR_MASK */ +#define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Pos 0UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Pos 1UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Pos 2UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Msk 0x4UL +/* TCPWM_GRP_CNT.INTR_MASKED */ +#define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Pos 0UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Pos 1UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Pos 2UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Msk 0x4UL + + +#endif /* _CYIP_TCPWM_V2_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_usbfs.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_usbfs.h index 2c2d5df640..8ea26a2fe0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_usbfs.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_usbfs.h @@ -5,7 +5,7 @@ * USBFS IP definitions * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -99,10 +99,10 @@ typedef struct { __IOM uint32_t ARB_EP1_INT_EN; /*!< 0x00000204 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP1_SR; /*!< 0x00000208 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED13; - __IOM uint32_t ARB_RW1_WA; /*!< 0x00000210 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW1_WA_MSB; /*!< 0x00000214 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW1_RA; /*!< 0x00000218 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW1_RA_MSB; /*!< 0x0000021C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW1_WA; /*!< 0x00000210 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW1_WA_MSB; /*!< 0x00000214 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW1_RA; /*!< 0x00000218 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW1_RA_MSB; /*!< 0x0000021C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW1_DR; /*!< 0x00000220 Endpoint Data Register */ __IM uint32_t RESERVED14[3]; __IOM uint32_t BUF_SIZE; /*!< 0x00000230 Dedicated Endpoint Buffer Size Register *1 */ @@ -113,10 +113,10 @@ typedef struct { __IOM uint32_t ARB_EP2_INT_EN; /*!< 0x00000244 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP2_SR; /*!< 0x00000248 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED16; - __IOM uint32_t ARB_RW2_WA; /*!< 0x00000250 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW2_WA_MSB; /*!< 0x00000254 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW2_RA; /*!< 0x00000258 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW2_RA_MSB; /*!< 0x0000025C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW2_WA; /*!< 0x00000250 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW2_WA_MSB; /*!< 0x00000254 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW2_RA; /*!< 0x00000258 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW2_RA_MSB; /*!< 0x0000025C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW2_DR; /*!< 0x00000260 Endpoint Data Register */ __IM uint32_t RESERVED17[3]; __IOM uint32_t ARB_CFG; /*!< 0x00000270 Arbiter Configuration Register *1 */ @@ -127,10 +127,10 @@ typedef struct { __IOM uint32_t ARB_EP3_INT_EN; /*!< 0x00000284 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP3_SR; /*!< 0x00000288 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED18; - __IOM uint32_t ARB_RW3_WA; /*!< 0x00000290 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW3_WA_MSB; /*!< 0x00000294 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW3_RA; /*!< 0x00000298 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW3_RA_MSB; /*!< 0x0000029C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW3_WA; /*!< 0x00000290 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW3_WA_MSB; /*!< 0x00000294 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW3_RA; /*!< 0x00000298 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW3_RA_MSB; /*!< 0x0000029C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW3_DR; /*!< 0x000002A0 Endpoint Data Register */ __IM uint32_t RESERVED19[3]; __IOM uint32_t CWA; /*!< 0x000002B0 Common Area Write Address *1 */ @@ -140,10 +140,10 @@ typedef struct { __IOM uint32_t ARB_EP4_INT_EN; /*!< 0x000002C4 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP4_SR; /*!< 0x000002C8 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED21; - __IOM uint32_t ARB_RW4_WA; /*!< 0x000002D0 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW4_WA_MSB; /*!< 0x000002D4 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW4_RA; /*!< 0x000002D8 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW4_RA_MSB; /*!< 0x000002DC Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW4_WA; /*!< 0x000002D0 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW4_WA_MSB; /*!< 0x000002D4 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW4_RA; /*!< 0x000002D8 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW4_RA_MSB; /*!< 0x000002DC Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW4_DR; /*!< 0x000002E0 Endpoint Data Register */ __IM uint32_t RESERVED22[3]; __IOM uint32_t DMA_THRES; /*!< 0x000002F0 DMA Burst / Threshold Configuration */ @@ -153,10 +153,10 @@ typedef struct { __IOM uint32_t ARB_EP5_INT_EN; /*!< 0x00000304 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP5_SR; /*!< 0x00000308 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED24; - __IOM uint32_t ARB_RW5_WA; /*!< 0x00000310 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW5_WA_MSB; /*!< 0x00000314 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW5_RA; /*!< 0x00000318 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW5_RA_MSB; /*!< 0x0000031C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW5_WA; /*!< 0x00000310 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW5_WA_MSB; /*!< 0x00000314 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW5_RA; /*!< 0x00000318 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW5_RA_MSB; /*!< 0x0000031C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW5_DR; /*!< 0x00000320 Endpoint Data Register */ __IM uint32_t RESERVED25[3]; __IOM uint32_t BUS_RST_CNT; /*!< 0x00000330 Bus Reset Count Register */ @@ -165,30 +165,30 @@ typedef struct { __IOM uint32_t ARB_EP6_INT_EN; /*!< 0x00000344 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP6_SR; /*!< 0x00000348 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED27; - __IOM uint32_t ARB_RW6_WA; /*!< 0x00000350 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW6_WA_MSB; /*!< 0x00000354 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW6_RA; /*!< 0x00000358 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW6_RA_MSB; /*!< 0x0000035C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW6_WA; /*!< 0x00000350 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW6_WA_MSB; /*!< 0x00000354 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW6_RA; /*!< 0x00000358 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW6_RA_MSB; /*!< 0x0000035C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW6_DR; /*!< 0x00000360 Endpoint Data Register */ __IM uint32_t RESERVED28[7]; __IOM uint32_t ARB_EP7_CFG; /*!< 0x00000380 Endpoint Configuration Register *1 */ __IOM uint32_t ARB_EP7_INT_EN; /*!< 0x00000384 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP7_SR; /*!< 0x00000388 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED29; - __IOM uint32_t ARB_RW7_WA; /*!< 0x00000390 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW7_WA_MSB; /*!< 0x00000394 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW7_RA; /*!< 0x00000398 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW7_RA_MSB; /*!< 0x0000039C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW7_WA; /*!< 0x00000390 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW7_WA_MSB; /*!< 0x00000394 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW7_RA; /*!< 0x00000398 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW7_RA_MSB; /*!< 0x0000039C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW7_DR; /*!< 0x000003A0 Endpoint Data Register */ __IM uint32_t RESERVED30[7]; __IOM uint32_t ARB_EP8_CFG; /*!< 0x000003C0 Endpoint Configuration Register *1 */ __IOM uint32_t ARB_EP8_INT_EN; /*!< 0x000003C4 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP8_SR; /*!< 0x000003C8 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED31; - __IOM uint32_t ARB_RW8_WA; /*!< 0x000003D0 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW8_WA_MSB; /*!< 0x000003D4 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW8_RA; /*!< 0x000003D8 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW8_RA_MSB; /*!< 0x000003DC Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW8_WA; /*!< 0x000003D0 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW8_WA_MSB; /*!< 0x000003D4 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW8_RA; /*!< 0x000003D8 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW8_RA_MSB; /*!< 0x000003DC Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW8_DR; /*!< 0x000003E0 Endpoint Data Register */ __IM uint32_t RESERVED32[7]; __IOM uint32_t MEM_DATA[512]; /*!< 0x00000400 DATA */ @@ -197,55 +197,55 @@ typedef struct { __IM uint32_t RESERVED34[7]; __IM uint32_t OSCLK_DR16; /*!< 0x00001080 Oscillator lock data register */ __IM uint32_t RESERVED35[99]; - __IOM uint32_t ARB_RW1_WA16; /*!< 0x00001210 Endpoint Write Address value */ + __IOM uint32_t ARB_RW1_WA16; /*!< 0x00001210 Endpoint Write Address value *3 */ __IM uint32_t RESERVED36; - __IOM uint32_t ARB_RW1_RA16; /*!< 0x00001218 Endpoint Read Address value */ + __IOM uint32_t ARB_RW1_RA16; /*!< 0x00001218 Endpoint Read Address value *3 */ __IM uint32_t RESERVED37; __IOM uint32_t ARB_RW1_DR16; /*!< 0x00001220 Endpoint Data Register */ __IM uint32_t RESERVED38[11]; - __IOM uint32_t ARB_RW2_WA16; /*!< 0x00001250 Endpoint Write Address value */ + __IOM uint32_t ARB_RW2_WA16; /*!< 0x00001250 Endpoint Write Address value *3 */ __IM uint32_t RESERVED39; - __IOM uint32_t ARB_RW2_RA16; /*!< 0x00001258 Endpoint Read Address value */ + __IOM uint32_t ARB_RW2_RA16; /*!< 0x00001258 Endpoint Read Address value *3 */ __IM uint32_t RESERVED40; __IOM uint32_t ARB_RW2_DR16; /*!< 0x00001260 Endpoint Data Register */ __IM uint32_t RESERVED41[11]; - __IOM uint32_t ARB_RW3_WA16; /*!< 0x00001290 Endpoint Write Address value */ + __IOM uint32_t ARB_RW3_WA16; /*!< 0x00001290 Endpoint Write Address value *3 */ __IM uint32_t RESERVED42; - __IOM uint32_t ARB_RW3_RA16; /*!< 0x00001298 Endpoint Read Address value */ + __IOM uint32_t ARB_RW3_RA16; /*!< 0x00001298 Endpoint Read Address value *3 */ __IM uint32_t RESERVED43; __IOM uint32_t ARB_RW3_DR16; /*!< 0x000012A0 Endpoint Data Register */ __IM uint32_t RESERVED44[3]; __IOM uint32_t CWA16; /*!< 0x000012B0 Common Area Write Address */ __IM uint32_t RESERVED45[7]; - __IOM uint32_t ARB_RW4_WA16; /*!< 0x000012D0 Endpoint Write Address value */ + __IOM uint32_t ARB_RW4_WA16; /*!< 0x000012D0 Endpoint Write Address value *3 */ __IM uint32_t RESERVED46; - __IOM uint32_t ARB_RW4_RA16; /*!< 0x000012D8 Endpoint Read Address value */ + __IOM uint32_t ARB_RW4_RA16; /*!< 0x000012D8 Endpoint Read Address value *3 */ __IM uint32_t RESERVED47; __IOM uint32_t ARB_RW4_DR16; /*!< 0x000012E0 Endpoint Data Register */ __IM uint32_t RESERVED48[3]; __IOM uint32_t DMA_THRES16; /*!< 0x000012F0 DMA Burst / Threshold Configuration */ __IM uint32_t RESERVED49[7]; - __IOM uint32_t ARB_RW5_WA16; /*!< 0x00001310 Endpoint Write Address value */ + __IOM uint32_t ARB_RW5_WA16; /*!< 0x00001310 Endpoint Write Address value *3 */ __IM uint32_t RESERVED50; - __IOM uint32_t ARB_RW5_RA16; /*!< 0x00001318 Endpoint Read Address value */ + __IOM uint32_t ARB_RW5_RA16; /*!< 0x00001318 Endpoint Read Address value *3 */ __IM uint32_t RESERVED51; __IOM uint32_t ARB_RW5_DR16; /*!< 0x00001320 Endpoint Data Register */ __IM uint32_t RESERVED52[11]; - __IOM uint32_t ARB_RW6_WA16; /*!< 0x00001350 Endpoint Write Address value */ + __IOM uint32_t ARB_RW6_WA16; /*!< 0x00001350 Endpoint Write Address value *3 */ __IM uint32_t RESERVED53; - __IOM uint32_t ARB_RW6_RA16; /*!< 0x00001358 Endpoint Read Address value */ + __IOM uint32_t ARB_RW6_RA16; /*!< 0x00001358 Endpoint Read Address value *3 */ __IM uint32_t RESERVED54; __IOM uint32_t ARB_RW6_DR16; /*!< 0x00001360 Endpoint Data Register */ __IM uint32_t RESERVED55[11]; - __IOM uint32_t ARB_RW7_WA16; /*!< 0x00001390 Endpoint Write Address value */ + __IOM uint32_t ARB_RW7_WA16; /*!< 0x00001390 Endpoint Write Address value *3 */ __IM uint32_t RESERVED56; - __IOM uint32_t ARB_RW7_RA16; /*!< 0x00001398 Endpoint Read Address value */ + __IOM uint32_t ARB_RW7_RA16; /*!< 0x00001398 Endpoint Read Address value *3 */ __IM uint32_t RESERVED57; __IOM uint32_t ARB_RW7_DR16; /*!< 0x000013A0 Endpoint Data Register */ __IM uint32_t RESERVED58[11]; - __IOM uint32_t ARB_RW8_WA16; /*!< 0x000013D0 Endpoint Write Address value */ + __IOM uint32_t ARB_RW8_WA16; /*!< 0x000013D0 Endpoint Write Address value *3 */ __IM uint32_t RESERVED59; - __IOM uint32_t ARB_RW8_RA16; /*!< 0x000013D8 Endpoint Read Address value */ + __IOM uint32_t ARB_RW8_RA16; /*!< 0x000013D8 Endpoint Read Address value *3 */ __IM uint32_t RESERVED60; __IOM uint32_t ARB_RW8_DR16; /*!< 0x000013E0 Endpoint Data Register */ __IM uint32_t RESERVED61[775]; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h new file mode 100644 index 0000000000..d4ebde4806 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h @@ -0,0 +1,2972 @@ +/***************************************************************************//** +* \file psoc6_04_config.h +* +* \brief +* PSoC6_04 device configuration header +* +* \note +* Generator version: 1.6.0.76 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _PSOC6_04_CONFIG_H_ +#define _PSOC6_04_CONFIG_H_ + +/* Clock Connections */ +typedef enum +{ + PCLK_SCB0_CLOCK = 0x0000u, /* scb[0].clock */ + PCLK_SCB1_CLOCK = 0x0001u, /* scb[1].clock */ + PCLK_SCB2_CLOCK = 0x0002u, /* scb[2].clock */ + PCLK_SCB4_CLOCK = 0x0003u, /* scb[4].clock */ + PCLK_SCB5_CLOCK = 0x0004u, /* scb[5].clock */ + PCLK_SCB6_CLOCK = 0x0005u, /* scb[6].clock */ + PCLK_SMARTIO9_CLOCK = 0x0006u, /* smartio[9].clock */ + PCLK_TCPWM0_CLOCKS0 = 0x0007u, /* tcpwm[0].clocks[0] */ + PCLK_TCPWM0_CLOCKS1 = 0x0008u, /* tcpwm[0].clocks[1] */ + PCLK_TCPWM0_CLOCKS2 = 0x0009u, /* tcpwm[0].clocks[2] */ + PCLK_TCPWM0_CLOCKS3 = 0x000Au, /* tcpwm[0].clocks[3] */ + PCLK_TCPWM0_CLOCKS256 = 0x000Bu, /* tcpwm[0].clocks[256] */ + PCLK_TCPWM0_CLOCKS257 = 0x000Cu, /* tcpwm[0].clocks[257] */ + PCLK_TCPWM0_CLOCKS258 = 0x000Du, /* tcpwm[0].clocks[258] */ + PCLK_TCPWM0_CLOCKS259 = 0x000Eu, /* tcpwm[0].clocks[259] */ + PCLK_TCPWM0_CLOCKS260 = 0x000Fu, /* tcpwm[0].clocks[260] */ + PCLK_TCPWM0_CLOCKS261 = 0x0010u, /* tcpwm[0].clocks[261] */ + PCLK_TCPWM0_CLOCKS262 = 0x0011u, /* tcpwm[0].clocks[262] */ + PCLK_TCPWM0_CLOCKS263 = 0x0012u, /* tcpwm[0].clocks[263] */ + PCLK_CSD_CLOCK = 0x0013u, /* csd.clock */ + PCLK_LCD_CLOCK = 0x0014u, /* lcd.clock */ + PCLK_CPUSS_CLOCK_TRACE_IN = 0x0015u, /* cpuss.clock_trace_in */ + PCLK_PASS_CLOCK_PUMP_PERI = 0x0016u, /* pass.clock_pump_peri */ + PCLK_PASS_CLOCK_SAR0 = 0x0017u, /* pass.clock_sar[0] */ + PCLK_CANFD0_CLOCK_CAN0 = 0x0018u, /* canfd[0].clock_can[0] */ + PCLK_USB_CLOCK_DEV_BRS = 0x0019u, /* usb.clock_dev_brs */ + PCLK_PASS_CLOCK_CTDAC = 0x001Au, /* pass.clock_ctdac */ + PCLK_PASS_CLOCK_SAR1 = 0x001Bu /* pass.clock_sar[1] */ +} en_clk_dst_t; + +/* Trigger Group */ +/* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. +* Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. +*/ +/* Trigger Group Inputs */ +/* Trigger Input Group 0 - PDMA0 Request Assignments */ +typedef enum +{ + TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT4 = 0x00000005u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT5 = 0x00000006u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT6 = 0x00000007u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT7 = 0x00000008u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT0 = 0x00000009u, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT1 = 0x0000000Au, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT2 = 0x0000000Bu, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT3 = 0x0000000Cu, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT4 = 0x0000000Du, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT5 = 0x0000000Eu, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT6 = 0x0000000Fu, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT7 = 0x00000010u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT00 = 0x00000011u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT10 = 0x00000012u, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT01 = 0x00000014u, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT11 = 0x00000015u, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT02 = 0x00000017u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT12 = 0x00000018u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT03 = 0x0000001Au, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT13 = 0x0000001Bu, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0256 = 0x0000001Du, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1256 = 0x0000001Eu, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0257 = 0x00000020u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1257 = 0x00000021u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0258 = 0x00000023u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1258 = 0x00000024u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0259 = 0x00000026u, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1259 = 0x00000027u, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0260 = 0x00000029u, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1260 = 0x0000002Au, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0261 = 0x0000002Cu, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1261 = 0x0000002Du, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0262 = 0x0000002Fu, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1262 = 0x00000030u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0263 = 0x00000032u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1263 = 0x00000033u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_0_MDMA_TR_OUT0 = 0x00000041u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_0_MDMA_TR_OUT1 = 0x00000042u, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT0 = 0x00000045u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT1 = 0x00000046u, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT2 = 0x00000047u, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT3 = 0x00000048u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT4 = 0x00000049u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT5 = 0x0000004Au, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT6 = 0x0000004Bu, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT7 = 0x0000004Cu, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT8 = 0x0000004Du, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT9 = 0x0000004Eu, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT10 = 0x0000004Fu, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT11 = 0x00000050u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT12 = 0x00000051u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT13 = 0x00000052u, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_0_CTI_TR_OUT0 = 0x00000053u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_0_CTI_TR_OUT1 = 0x00000054u, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_0_FAULT_TR_OUT0 = 0x00000055u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_0_FAULT_TR_OUT1 = 0x00000056u /* cpuss.tr_fault[1] */ +} en_trig_input_pdma0_tr_t; + +/* Trigger Input Group 1 - PDMA1 Request Assignments */ +typedef enum +{ + TRIG_IN_MUX_1_PDMA0_TR_OUT0 = 0x00000101u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT1 = 0x00000102u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT2 = 0x00000103u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT3 = 0x00000104u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT4 = 0x00000105u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT5 = 0x00000106u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT6 = 0x00000107u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT7 = 0x00000108u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT0 = 0x00000109u, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT1 = 0x0000010Au, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT2 = 0x0000010Bu, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT3 = 0x0000010Cu, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT4 = 0x0000010Du, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT5 = 0x0000010Eu, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT6 = 0x0000010Fu, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT7 = 0x00000110u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_1_MDMA_TR_OUT0 = 0x00000141u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_1_MDMA_TR_OUT1 = 0x00000142u, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_1_CSD_ADC_DONE = 0x00000145u, /* csd.tr_adc_done */ + TRIG_IN_MUX_1_HSIOM_TR_OUT14 = 0x00000146u, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT15 = 0x00000147u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT16 = 0x00000148u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT17 = 0x00000149u, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT18 = 0x0000014Au, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT19 = 0x0000014Bu, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT20 = 0x0000014Cu, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT21 = 0x0000014Du, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT22 = 0x0000014Eu, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT23 = 0x0000014Fu, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_1_LPCOMP_DSI_COMP0 = 0x00000154u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_1_LPCOMP_DSI_COMP1 = 0x00000155u, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_1_CANFD_TT_TR_OUT0 = 0x00000156u /* canfd[0].tr_tmp_rtp_out[0] */ +} en_trig_input_pdma1_tr_t; + +/* Trigger Input Group 2 - TCPWM0 trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_2_PDMA0_TR_OUT0 = 0x00000201u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT1 = 0x00000202u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT2 = 0x00000203u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT3 = 0x00000204u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT4 = 0x00000205u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT5 = 0x00000206u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT6 = 0x00000207u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT7 = 0x00000208u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT00 = 0x00000209u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT10 = 0x0000020Au, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT01 = 0x0000020Cu, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT11 = 0x0000020Du, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT02 = 0x0000020Fu, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT12 = 0x00000210u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT03 = 0x00000212u, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT13 = 0x00000213u, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0256 = 0x00000221u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1256 = 0x00000222u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0257 = 0x00000224u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1257 = 0x00000225u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0258 = 0x00000227u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1258 = 0x00000228u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0259 = 0x0000022Au, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1259 = 0x0000022Bu, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0260 = 0x0000022Du, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1260 = 0x0000022Eu, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0261 = 0x00000230u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1261 = 0x00000231u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0262 = 0x00000233u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1262 = 0x00000234u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0263 = 0x00000236u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1263 = 0x00000237u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_2_MDMA_TR_OUT0 = 0x00000239u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_2_MDMA_TR_OUT1 = 0x0000023Au, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_2_SCB_I2C_SCL0 = 0x0000023Du, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX0 = 0x0000023Eu, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX0 = 0x0000023Fu, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL1 = 0x00000240u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX1 = 0x00000241u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX1 = 0x00000242u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL2 = 0x00000243u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX2 = 0x00000244u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX2 = 0x00000245u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL4 = 0x00000249u, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX4 = 0x0000024Au, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX4 = 0x0000024Bu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL5 = 0x0000024Cu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX5 = 0x0000024Du, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX5 = 0x0000024Eu, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL6 = 0x0000024Fu, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX6 = 0x00000250u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX6 = 0x00000251u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_2_SMIF_TX = 0x00000264u, /* smif.tr_tx_req */ + TRIG_IN_MUX_2_SMIF_RX = 0x00000265u, /* smif.tr_rx_req */ + TRIG_IN_MUX_2_USB_DMA0 = 0x00000266u, /* usb.dma_req[0] */ + TRIG_IN_MUX_2_USB_DMA1 = 0x00000267u, /* usb.dma_req[1] */ + TRIG_IN_MUX_2_USB_DMA2 = 0x00000268u, /* usb.dma_req[2] */ + TRIG_IN_MUX_2_USB_DMA3 = 0x00000269u, /* usb.dma_req[3] */ + TRIG_IN_MUX_2_USB_DMA4 = 0x0000026Au, /* usb.dma_req[4] */ + TRIG_IN_MUX_2_USB_DMA5 = 0x0000026Bu, /* usb.dma_req[5] */ + TRIG_IN_MUX_2_USB_DMA6 = 0x0000026Cu, /* usb.dma_req[6] */ + TRIG_IN_MUX_2_USB_DMA7 = 0x0000026Du, /* usb.dma_req[7] */ + TRIG_IN_MUX_2_PASS_SAR0_DONE = 0x00000273u, /* pass.tr_sar_out[0] */ + TRIG_IN_MUX_2_CSD_SENSE = 0x00000274u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_2_HSIOM_TR_OUT0 = 0x00000275u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT1 = 0x00000276u, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT2 = 0x00000277u, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT3 = 0x00000278u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT4 = 0x00000279u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT5 = 0x0000027Au, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT6 = 0x0000027Bu, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT7 = 0x0000027Cu, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT8 = 0x0000027Du, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT9 = 0x0000027Eu, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT10 = 0x0000027Fu, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT11 = 0x00000280u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT12 = 0x00000281u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT13 = 0x00000282u, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_2_CTI_TR_OUT0 = 0x00000283u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_2_CTI_TR_OUT1 = 0x00000284u, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_2_LPCOMP_DSI_COMP0 = 0x00000285u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_2_LPCOMP_DSI_COMP1 = 0x00000286u, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_2_CANFD_TT_TR_OUT0 = 0x00000287u, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_2_PASS_CTDAC_EMPTY = 0x00000288u, /* pass.tr_ctdac_empty */ + TRIG_IN_MUX_2_PASS_CTB_CMP0 = 0x00000289u, /* pass.dsi_ctb_cmp0 */ + TRIG_IN_MUX_2_PASS_SAR1_DONE = 0x0000028Au /* pass.tr_sar_out[1] */ +} en_trig_input_tcpwm0_t; + +/* Trigger Input Group 3 - TCPWM0 trigger multiplexer - 2nd */ +typedef enum +{ + TRIG_IN_MUX_3_PDMA1_TR_OUT0 = 0x00000301u, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT1 = 0x00000302u, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT2 = 0x00000303u, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT3 = 0x00000304u, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT4 = 0x00000305u, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT5 = 0x00000306u, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT6 = 0x00000307u, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT7 = 0x00000308u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT00 = 0x00000309u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT10 = 0x0000030Au, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT01 = 0x0000030Cu, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT11 = 0x0000030Du, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT02 = 0x0000030Fu, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT12 = 0x00000310u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT03 = 0x00000312u, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT13 = 0x00000313u, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0256 = 0x00000321u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1256 = 0x00000322u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0257 = 0x00000324u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1257 = 0x00000325u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0258 = 0x00000327u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1258 = 0x00000328u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0259 = 0x0000032Au, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1259 = 0x0000032Bu, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0260 = 0x0000032Du, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1260 = 0x0000032Eu, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0261 = 0x00000330u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1261 = 0x00000331u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0262 = 0x00000333u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1262 = 0x00000334u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0263 = 0x00000336u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1263 = 0x00000337u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_3_MDMA_TR_OUT0 = 0x00000339u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_3_MDMA_TR_OUT1 = 0x0000033Au, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_3_SCB_I2C_SCL0 = 0x0000033Du, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX0 = 0x0000033Eu, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX0 = 0x0000033Fu, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL1 = 0x00000340u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX1 = 0x00000341u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX1 = 0x00000342u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL2 = 0x00000343u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX2 = 0x00000344u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX2 = 0x00000345u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL4 = 0x00000349u, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX4 = 0x0000034Au, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX4 = 0x0000034Bu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL5 = 0x0000034Cu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX5 = 0x0000034Du, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX5 = 0x0000034Eu, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL6 = 0x0000034Fu, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX6 = 0x00000350u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX6 = 0x00000351u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_3_SMIF_TX = 0x00000364u, /* smif.tr_tx_req */ + TRIG_IN_MUX_3_SMIF_RX = 0x00000365u, /* smif.tr_rx_req */ + TRIG_IN_MUX_3_USB_DMA0 = 0x00000366u, /* usb.dma_req[0] */ + TRIG_IN_MUX_3_USB_DMA1 = 0x00000367u, /* usb.dma_req[1] */ + TRIG_IN_MUX_3_USB_DMA2 = 0x00000368u, /* usb.dma_req[2] */ + TRIG_IN_MUX_3_USB_DMA3 = 0x00000369u, /* usb.dma_req[3] */ + TRIG_IN_MUX_3_USB_DMA4 = 0x0000036Au, /* usb.dma_req[4] */ + TRIG_IN_MUX_3_USB_DMA5 = 0x0000036Bu, /* usb.dma_req[5] */ + TRIG_IN_MUX_3_USB_DMA6 = 0x0000036Cu, /* usb.dma_req[6] */ + TRIG_IN_MUX_3_USB_DMA7 = 0x0000036Du, /* usb.dma_req[7] */ + TRIG_IN_MUX_3_PASS_SAR0_DONE = 0x00000373u, /* pass.tr_sar_out[0] */ + TRIG_IN_MUX_3_CSD_SENSE = 0x00000374u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_3_HSIOM_TR_OUT14 = 0x00000375u, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT15 = 0x00000376u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT16 = 0x00000377u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT17 = 0x00000378u, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT18 = 0x00000379u, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT19 = 0x0000037Au, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT20 = 0x0000037Bu, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT21 = 0x0000037Cu, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT22 = 0x0000037Du, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT23 = 0x0000037Eu, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_3_FAULT_TR_OUT0 = 0x00000383u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_3_FAULT_TR_OUT1 = 0x00000384u, /* cpuss.tr_fault[1] */ + TRIG_IN_MUX_3_LPCOMP_DSI_COMP0 = 0x00000385u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_3_LPCOMP_DSI_COMP1 = 0x00000386u, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_3_CANFD_TT_TR_OUT0 = 0x00000387u, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_3_PASS_CTDAC_EMPTY = 0x00000388u, /* pass.tr_ctdac_empty */ + TRIG_IN_MUX_3_PASS_CTB_CMP0 = 0x00000389u, /* pass.dsi_ctb_cmp1 */ + TRIG_IN_MUX_3_PASS_SAR1_DONE = 0x0000038Au /* pass.tr_sar_out[1] */ +} en_trig_input_tcpwm0_2_t; + +/* Trigger Input Group 4 - HSIOM trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_4_PDMA0_TR_OUT0 = 0x00000401u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT1 = 0x00000402u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT2 = 0x00000403u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT3 = 0x00000404u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT4 = 0x00000405u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT5 = 0x00000406u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT6 = 0x00000407u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT7 = 0x00000408u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT8 = 0x00000409u, /* cpuss.dw0_tr_out[8] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT9 = 0x0000040Au, /* cpuss.dw0_tr_out[9] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT10 = 0x0000040Bu, /* cpuss.dw0_tr_out[10] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT11 = 0x0000040Cu, /* cpuss.dw0_tr_out[11] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT12 = 0x0000040Du, /* cpuss.dw0_tr_out[12] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT13 = 0x0000040Eu, /* cpuss.dw0_tr_out[13] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT14 = 0x0000040Fu, /* cpuss.dw0_tr_out[14] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT15 = 0x00000410u, /* cpuss.dw0_tr_out[15] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT16 = 0x00000411u, /* cpuss.dw0_tr_out[16] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT17 = 0x00000412u, /* cpuss.dw0_tr_out[17] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT18 = 0x00000413u, /* cpuss.dw0_tr_out[18] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT19 = 0x00000414u, /* cpuss.dw0_tr_out[19] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT20 = 0x00000415u, /* cpuss.dw0_tr_out[20] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT21 = 0x00000416u, /* cpuss.dw0_tr_out[21] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT22 = 0x00000417u, /* cpuss.dw0_tr_out[22] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT23 = 0x00000418u, /* cpuss.dw0_tr_out[23] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT24 = 0x00000419u, /* cpuss.dw0_tr_out[24] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT25 = 0x0000041Au, /* cpuss.dw0_tr_out[25] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT26 = 0x0000041Bu, /* cpuss.dw0_tr_out[26] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT27 = 0x0000041Cu, /* cpuss.dw0_tr_out[27] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT28 = 0x0000041Du, /* cpuss.dw0_tr_out[28] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT0 = 0x0000041Eu, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT1 = 0x0000041Fu, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT2 = 0x00000420u, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT3 = 0x00000421u, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT4 = 0x00000422u, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT5 = 0x00000423u, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT6 = 0x00000424u, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT7 = 0x00000425u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT8 = 0x00000426u, /* cpuss.dw1_tr_out[8] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT9 = 0x00000427u, /* cpuss.dw1_tr_out[9] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT10 = 0x00000428u, /* cpuss.dw1_tr_out[10] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT11 = 0x00000429u, /* cpuss.dw1_tr_out[11] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT12 = 0x0000042Au, /* cpuss.dw1_tr_out[12] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT13 = 0x0000042Bu, /* cpuss.dw1_tr_out[13] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT14 = 0x0000042Cu, /* cpuss.dw1_tr_out[14] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT15 = 0x0000042Du, /* cpuss.dw1_tr_out[15] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT16 = 0x0000042Eu, /* cpuss.dw1_tr_out[16] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT17 = 0x0000042Fu, /* cpuss.dw1_tr_out[17] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT18 = 0x00000430u, /* cpuss.dw1_tr_out[18] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT19 = 0x00000431u, /* cpuss.dw1_tr_out[19] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT20 = 0x00000432u, /* cpuss.dw1_tr_out[20] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT21 = 0x00000433u, /* cpuss.dw1_tr_out[21] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT22 = 0x00000434u, /* cpuss.dw1_tr_out[22] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT23 = 0x00000435u, /* cpuss.dw1_tr_out[23] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT24 = 0x00000436u, /* cpuss.dw1_tr_out[24] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT25 = 0x00000437u, /* cpuss.dw1_tr_out[25] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT26 = 0x00000438u, /* cpuss.dw1_tr_out[26] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT27 = 0x00000439u, /* cpuss.dw1_tr_out[27] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT28 = 0x0000043Au, /* cpuss.dw1_tr_out[28] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT00 = 0x0000043Bu, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT10 = 0x0000043Cu, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT01 = 0x0000043Eu, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT11 = 0x0000043Fu, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT02 = 0x00000441u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT12 = 0x00000442u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT03 = 0x00000444u, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT13 = 0x00000445u, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0256 = 0x00000453u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1256 = 0x00000454u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0257 = 0x00000456u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1257 = 0x00000457u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0258 = 0x00000459u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1258 = 0x0000045Au, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0259 = 0x0000045Cu, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1259 = 0x0000045Du, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0260 = 0x0000045Fu, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1260 = 0x00000460u, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0261 = 0x00000462u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1261 = 0x00000463u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0262 = 0x00000465u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1262 = 0x00000466u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0263 = 0x00000468u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1263 = 0x00000469u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_4_MDMA_TR_OUT0 = 0x0000049Bu, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_4_MDMA_TR_OUT1 = 0x0000049Cu, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_4_SCB_I2C_SCL0 = 0x0000049Fu, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX0 = 0x000004A0u, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX0 = 0x000004A1u, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL1 = 0x000004A2u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX1 = 0x000004A3u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX1 = 0x000004A4u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL2 = 0x000004A5u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX2 = 0x000004A6u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX2 = 0x000004A7u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL4 = 0x000004ABu, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX4 = 0x000004ACu, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX4 = 0x000004ADu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL5 = 0x000004AEu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX5 = 0x000004AFu, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX5 = 0x000004B0u, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL6 = 0x000004B1u, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX6 = 0x000004B2u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX6 = 0x000004B3u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_4_SMIF_TX = 0x000004C6u, /* smif.tr_tx_req */ + TRIG_IN_MUX_4_SMIF_RX = 0x000004C7u, /* smif.tr_rx_req */ + TRIG_IN_MUX_4_USB_DMA0 = 0x000004C8u, /* usb.dma_req[0] */ + TRIG_IN_MUX_4_USB_DMA1 = 0x000004C9u, /* usb.dma_req[1] */ + TRIG_IN_MUX_4_USB_DMA2 = 0x000004CAu, /* usb.dma_req[2] */ + TRIG_IN_MUX_4_USB_DMA3 = 0x000004CBu, /* usb.dma_req[3] */ + TRIG_IN_MUX_4_USB_DMA4 = 0x000004CCu, /* usb.dma_req[4] */ + TRIG_IN_MUX_4_USB_DMA5 = 0x000004CDu, /* usb.dma_req[5] */ + TRIG_IN_MUX_4_USB_DMA6 = 0x000004CEu, /* usb.dma_req[6] */ + TRIG_IN_MUX_4_USB_DMA7 = 0x000004CFu, /* usb.dma_req[7] */ + TRIG_IN_MUX_4_CSD_SENSE = 0x000004D5u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_4_CSD_SAMPLE = 0x000004D6u, /* csd.dsi_sample_out */ + TRIG_IN_MUX_4_CSD_ADC_DONE = 0x000004D7u, /* csd.tr_adc_done */ + TRIG_IN_MUX_4_PASS_SAR0_DONE = 0x000004D8u, /* pass.tr_sar_out[0] */ + TRIG_IN_MUX_4_FAULT_TR_OUT0 = 0x000004D9u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_4_FAULT_TR_OUT1 = 0x000004DAu, /* cpuss.tr_fault[1] */ + TRIG_IN_MUX_4_CTI_TR_OUT0 = 0x000004DBu, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_4_CTI_TR_OUT1 = 0x000004DCu, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_4_LPCOMP_DSI_COMP0 = 0x000004DDu, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_4_LPCOMP_DSI_COMP1 = 0x000004DEu, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_4_CANFD_TT_TR_OUT0 = 0x000004DFu, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT29 = 0x000004E0u, /* cpuss.dw1_tr_out[29] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT30 = 0x000004E1u, /* cpuss.dw1_tr_out[30] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT31 = 0x000004E2u, /* cpuss.dw1_tr_out[31] */ + TRIG_IN_MUX_4_PASS_SAR1_DONE = 0x000004E3u, /* pass.tr_sar_out[1] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT29 = 0x000004E4u /* cpuss.dw0_tr_out[29] */ +} en_trig_input_hsiom_t; + +/* Trigger Input Group 5 - CPUSS Debug trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_5_PDMA0_TR_OUT0 = 0x00000501u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT1 = 0x00000502u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT2 = 0x00000503u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT3 = 0x00000504u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT4 = 0x00000505u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT5 = 0x00000506u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT6 = 0x00000507u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT7 = 0x00000508u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT8 = 0x00000509u, /* cpuss.dw0_tr_out[8] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT9 = 0x0000050Au, /* cpuss.dw0_tr_out[9] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT10 = 0x0000050Bu, /* cpuss.dw0_tr_out[10] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT11 = 0x0000050Cu, /* cpuss.dw0_tr_out[11] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT12 = 0x0000050Du, /* cpuss.dw0_tr_out[12] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT13 = 0x0000050Eu, /* cpuss.dw0_tr_out[13] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT14 = 0x0000050Fu, /* cpuss.dw0_tr_out[14] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT15 = 0x00000510u, /* cpuss.dw0_tr_out[15] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT16 = 0x00000511u, /* cpuss.dw0_tr_out[16] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT17 = 0x00000512u, /* cpuss.dw0_tr_out[17] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT18 = 0x00000513u, /* cpuss.dw0_tr_out[18] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT19 = 0x00000514u, /* cpuss.dw0_tr_out[19] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT20 = 0x00000515u, /* cpuss.dw0_tr_out[20] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT21 = 0x00000516u, /* cpuss.dw0_tr_out[21] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT22 = 0x00000517u, /* cpuss.dw0_tr_out[22] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT23 = 0x00000518u, /* cpuss.dw0_tr_out[23] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT24 = 0x00000519u, /* cpuss.dw0_tr_out[24] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT25 = 0x0000051Au, /* cpuss.dw0_tr_out[25] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT26 = 0x0000051Bu, /* cpuss.dw0_tr_out[26] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT27 = 0x0000051Cu, /* cpuss.dw0_tr_out[27] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT28 = 0x0000051Du, /* cpuss.dw0_tr_out[28] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT0 = 0x0000051Eu, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT1 = 0x0000051Fu, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT2 = 0x00000520u, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT3 = 0x00000521u, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT4 = 0x00000522u, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT5 = 0x00000523u, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT6 = 0x00000524u, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT7 = 0x00000525u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT8 = 0x00000526u, /* cpuss.dw1_tr_out[8] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT9 = 0x00000527u, /* cpuss.dw1_tr_out[9] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT10 = 0x00000528u, /* cpuss.dw1_tr_out[10] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT11 = 0x00000529u, /* cpuss.dw1_tr_out[11] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT12 = 0x0000052Au, /* cpuss.dw1_tr_out[12] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT13 = 0x0000052Bu, /* cpuss.dw1_tr_out[13] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT14 = 0x0000052Cu, /* cpuss.dw1_tr_out[14] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT15 = 0x0000052Du, /* cpuss.dw1_tr_out[15] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT16 = 0x0000052Eu, /* cpuss.dw1_tr_out[16] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT17 = 0x0000052Fu, /* cpuss.dw1_tr_out[17] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT18 = 0x00000530u, /* cpuss.dw1_tr_out[18] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT19 = 0x00000531u, /* cpuss.dw1_tr_out[19] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT20 = 0x00000532u, /* cpuss.dw1_tr_out[20] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT21 = 0x00000533u, /* cpuss.dw1_tr_out[21] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT22 = 0x00000534u, /* cpuss.dw1_tr_out[22] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT23 = 0x00000535u, /* cpuss.dw1_tr_out[23] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT24 = 0x00000536u, /* cpuss.dw1_tr_out[24] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT25 = 0x00000537u, /* cpuss.dw1_tr_out[25] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT26 = 0x00000538u, /* cpuss.dw1_tr_out[26] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT27 = 0x00000539u, /* cpuss.dw1_tr_out[27] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT28 = 0x0000053Au, /* cpuss.dw1_tr_out[28] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT00 = 0x0000053Bu, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT10 = 0x0000053Cu, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT01 = 0x0000053Eu, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT11 = 0x0000053Fu, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT02 = 0x00000541u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT12 = 0x00000542u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT03 = 0x00000544u, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT13 = 0x00000545u, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0256 = 0x00000553u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1256 = 0x00000554u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0257 = 0x00000556u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1257 = 0x00000557u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0258 = 0x00000559u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1258 = 0x0000055Au, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0259 = 0x0000055Cu, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1259 = 0x0000055Du, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0260 = 0x0000055Fu, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1260 = 0x00000560u, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0261 = 0x00000562u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1261 = 0x00000563u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0262 = 0x00000565u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1262 = 0x00000566u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0263 = 0x00000568u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1263 = 0x00000569u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_5_MDMA_TR_OUT0 = 0x0000059Bu, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_5_MDMA_TR_OUT1 = 0x0000059Cu, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_5_SCB_I2C_SCL0 = 0x0000059Fu, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX0 = 0x000005A0u, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX0 = 0x000005A1u, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL1 = 0x000005A2u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX1 = 0x000005A3u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX1 = 0x000005A4u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL2 = 0x000005A5u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX2 = 0x000005A6u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX2 = 0x000005A7u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL4 = 0x000005ABu, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX4 = 0x000005ACu, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX4 = 0x000005ADu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL5 = 0x000005AEu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX5 = 0x000005AFu, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX5 = 0x000005B0u, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL6 = 0x000005B1u, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX6 = 0x000005B2u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX6 = 0x000005B3u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_5_SMIF_TX = 0x000005C6u, /* smif.tr_tx_req */ + TRIG_IN_MUX_5_SMIF_RX = 0x000005C7u, /* smif.tr_rx_req */ + TRIG_IN_MUX_5_USB_DMA0 = 0x000005C8u, /* usb.dma_req[0] */ + TRIG_IN_MUX_5_USB_DMA1 = 0x000005C9u, /* usb.dma_req[1] */ + TRIG_IN_MUX_5_USB_DMA2 = 0x000005CAu, /* usb.dma_req[2] */ + TRIG_IN_MUX_5_USB_DMA3 = 0x000005CBu, /* usb.dma_req[3] */ + TRIG_IN_MUX_5_USB_DMA4 = 0x000005CCu, /* usb.dma_req[4] */ + TRIG_IN_MUX_5_USB_DMA5 = 0x000005CDu, /* usb.dma_req[5] */ + TRIG_IN_MUX_5_USB_DMA6 = 0x000005CEu, /* usb.dma_req[6] */ + TRIG_IN_MUX_5_USB_DMA7 = 0x000005CFu, /* usb.dma_req[7] */ + TRIG_IN_MUX_5_CSD_SENSE = 0x000005D5u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_5_CSD_SAMPLE = 0x000005D6u, /* csd.dsi_sample_out */ + TRIG_IN_MUX_5_CSD_ADC_DONE = 0x000005D7u, /* csd.tr_adc_done */ + TRIG_IN_MUX_5_PASS_SAR0_DONE = 0x000005D8u, /* pass.tr_sar_out[0] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT0 = 0x000005D9u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT1 = 0x000005DAu, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT2 = 0x000005DBu, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT3 = 0x000005DCu, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT4 = 0x000005DDu, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT5 = 0x000005DEu, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT6 = 0x000005DFu, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT7 = 0x000005E0u, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT8 = 0x000005E1u, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT9 = 0x000005E2u, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT10 = 0x000005E3u, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT11 = 0x000005E4u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT12 = 0x000005E5u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT13 = 0x000005E6u, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT14 = 0x000005E7u, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT15 = 0x000005E8u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT16 = 0x000005E9u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT17 = 0x000005EAu, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT18 = 0x000005EBu, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT19 = 0x000005ECu, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT20 = 0x000005EDu, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT21 = 0x000005EEu, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT22 = 0x000005EFu, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT23 = 0x000005F0u, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_5_FAULT_TR_OUT0 = 0x000005F5u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_5_FAULT_TR_OUT1 = 0x000005F6u, /* cpuss.tr_fault[1] */ + TRIG_IN_MUX_5_CTI_TR_OUT0 = 0x000005F7u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_5_CTI_TR_OUT1 = 0x000005F8u, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_5_LPCOMP_DSI_COMP0 = 0x000005F9u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_5_LPCOMP_DSI_COMP1 = 0x000005FAu, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_5_CANFD_TT_TR_OUT0 = 0x000005FBu, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT29 = 0x000005FCu, /* cpuss.dw1_tr_out[29] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT30 = 0x000005FDu, /* cpuss.dw1_tr_out[30] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT31 = 0x000005FEu, /* cpuss.dw1_tr_out[31] */ + TRIG_IN_MUX_5_PASS_SAR1_DONE = 0x000005FFu /* pass.tr_sar_out[1] */ +} en_trig_input_cpuss_cti_t; + +/* Trigger Input Group 6 - MDMA trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0256 = 0x00000601u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1256 = 0x00000602u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0257 = 0x00000604u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1257 = 0x00000605u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0258 = 0x00000607u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1258 = 0x00000608u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0259 = 0x0000060Au, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1259 = 0x0000060Bu, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0260 = 0x0000060Du, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1260 = 0x0000060Eu, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0261 = 0x00000610u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1261 = 0x00000611u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0262 = 0x00000613u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1262 = 0x00000614u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0263 = 0x00000616u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1263 = 0x00000617u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_6_SMIF_TX = 0x00000619u, /* smif.tr_tx_req */ + TRIG_IN_MUX_6_SMIF_RX = 0x0000061Au /* smif.tr_rx_req */ +} en_trig_input_mdma_t; + +/* Trigger Input Group 7 - PERI Freeze trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_7_CTI_TR_OUT0 = 0x00000701u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_7_CTI_TR_OUT1 = 0x00000702u /* cpuss.cti_tr_out[1] */ +} en_trig_input_peri_freeze_t; + +/* Trigger Input Group 8 - Capsense trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_8_TCPWM0_TR_OUT00 = 0x00000801u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT10 = 0x00000802u, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT01 = 0x00000804u, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT11 = 0x00000805u, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT02 = 0x00000807u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT12 = 0x00000808u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT03 = 0x0000080Au, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT13 = 0x0000080Bu, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0256 = 0x00000819u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1256 = 0x0000081Au, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0257 = 0x0000081Cu, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1257 = 0x0000081Du, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0258 = 0x0000081Fu, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1258 = 0x00000820u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0259 = 0x00000822u, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1259 = 0x00000823u, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0260 = 0x00000825u, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1260 = 0x00000826u, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0261 = 0x00000828u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1261 = 0x00000829u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0262 = 0x0000082Bu, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1262 = 0x0000082Cu, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0263 = 0x0000082Eu, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1263 = 0x0000082Fu, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT0 = 0x0000086Du, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT1 = 0x0000086Eu, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT2 = 0x0000086Fu, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT3 = 0x00000870u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT4 = 0x00000871u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT5 = 0x00000872u, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT6 = 0x00000873u, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT7 = 0x00000874u, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT8 = 0x00000875u, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT9 = 0x00000876u, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT10 = 0x00000877u, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT11 = 0x00000878u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT12 = 0x00000879u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT13 = 0x0000087Au, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT14 = 0x0000087Bu, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT15 = 0x0000087Cu, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT16 = 0x0000087Du, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT17 = 0x0000087Eu, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT18 = 0x0000087Fu, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT19 = 0x00000880u, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT20 = 0x00000881u, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT21 = 0x00000882u, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT22 = 0x00000883u, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT23 = 0x00000884u, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_8_LPCOMP_DSI_COMP0 = 0x00000889u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_8_LPCOMP_DSI_COMP1 = 0x0000088Au /* lpcomp.dsi_comp1 */ +} en_trig_input_csd_t; + +/* Trigger Input Group 9 - ADC trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_9_TCPWM0_TR_OUT00 = 0x00000901u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT10 = 0x00000902u, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT01 = 0x00000904u, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT11 = 0x00000905u, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT02 = 0x00000907u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT12 = 0x00000908u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT03 = 0x0000090Au, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT13 = 0x0000090Bu, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0256 = 0x00000919u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1256 = 0x0000091Au, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0257 = 0x0000091Cu, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1257 = 0x0000091Du, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0258 = 0x0000091Fu, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1258 = 0x00000920u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0259 = 0x00000922u, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1259 = 0x00000923u, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0260 = 0x00000925u, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1260 = 0x00000926u, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0261 = 0x00000928u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1261 = 0x00000929u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0262 = 0x0000092Bu, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1262 = 0x0000092Cu, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0263 = 0x0000092Eu, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1263 = 0x0000092Fu, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT0 = 0x00000961u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT1 = 0x00000962u, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT2 = 0x00000963u, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT3 = 0x00000964u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT4 = 0x00000965u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT5 = 0x00000966u, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT6 = 0x00000967u, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT7 = 0x00000968u, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT8 = 0x00000969u, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT9 = 0x0000096Au, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT10 = 0x0000096Bu, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT11 = 0x0000096Cu, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT12 = 0x0000096Du, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT13 = 0x0000096Eu, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT14 = 0x0000096Fu, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT15 = 0x00000970u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT16 = 0x00000971u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT17 = 0x00000972u, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT18 = 0x00000973u, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT19 = 0x00000974u, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT20 = 0x00000975u, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT21 = 0x00000976u, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT22 = 0x00000977u, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT23 = 0x00000978u, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_9_LPCOMP_DSI_COMP0 = 0x0000097Du, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_9_LPCOMP_DSI_COMP1 = 0x0000097Eu /* lpcomp.dsi_comp1 */ +} en_trig_input_sar_adc_start_t; + +/* Trigger Input Group 10 - CAN TT Synchronization triggers */ +typedef enum +{ + TRIG_IN_MUX_10_CAN_TT_TR_OUT0 = 0x00000A01u /* canfd[0].tr_tmp_rtp_out[0] */ +} en_trig_input_cantt_t; + +/* Trigger Group Outputs */ +/* Trigger Output Group 0 - PDMA0 Request Assignments */ +typedef enum +{ + TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN7 = 0x40000007u /* cpuss.dw0_tr_in[7] */ +} en_trig_output_pdma0_tr_t; + +/* Trigger Output Group 1 - PDMA1 Request Assignments */ +typedef enum +{ + TRIG_OUT_MUX_1_PDMA1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN7 = 0x40000107u /* cpuss.dw1_tr_in[7] */ +} en_trig_output_pdma1_tr_t; + +/* Trigger Output Group 2 - TCPWM0 trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_2_TCPWM0_TR_IN0 = 0x40000200u, /* tcpwm[0].tr_all_cnt_in[0] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN1 = 0x40000201u, /* tcpwm[0].tr_all_cnt_in[1] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN2 = 0x40000202u, /* tcpwm[0].tr_all_cnt_in[2] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN3 = 0x40000203u, /* tcpwm[0].tr_all_cnt_in[3] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN4 = 0x40000204u, /* tcpwm[0].tr_all_cnt_in[4] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN5 = 0x40000205u, /* tcpwm[0].tr_all_cnt_in[5] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN6 = 0x40000206u, /* tcpwm[0].tr_all_cnt_in[6] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN7 = 0x40000207u, /* tcpwm[0].tr_all_cnt_in[7] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN8 = 0x40000208u, /* tcpwm[0].tr_all_cnt_in[8] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN9 = 0x40000209u, /* tcpwm[0].tr_all_cnt_in[9] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN10 = 0x4000020Au, /* tcpwm[0].tr_all_cnt_in[10] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_all_cnt_in[11] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN12 = 0x4000020Cu, /* tcpwm[0].tr_all_cnt_in[12] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN13 = 0x4000020Du /* tcpwm[0].tr_all_cnt_in[13] */ +} en_trig_output_tcpwm0_t; + +/* Trigger Output Group 3 - TCPWM0 trigger multiplexer - 2nd */ +typedef enum +{ + TRIG_OUT_MUX_3_TCPWM1_TR_IN0 = 0x40000300u, /* tcpwm[0].tr_all_cnt_in[14] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN1 = 0x40000301u, /* tcpwm[0].tr_all_cnt_in[15] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN2 = 0x40000302u, /* tcpwm[0].tr_all_cnt_in[16] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN3 = 0x40000303u, /* tcpwm[0].tr_all_cnt_in[17] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN4 = 0x40000304u, /* tcpwm[0].tr_all_cnt_in[18] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN5 = 0x40000305u, /* tcpwm[0].tr_all_cnt_in[19] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN6 = 0x40000306u, /* tcpwm[0].tr_all_cnt_in[20] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN7 = 0x40000307u, /* tcpwm[0].tr_all_cnt_in[21] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN8 = 0x40000308u, /* tcpwm[0].tr_all_cnt_in[22] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN9 = 0x40000309u, /* tcpwm[0].tr_all_cnt_in[23] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN10 = 0x4000030Au, /* tcpwm[0].tr_all_cnt_in[24] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN11 = 0x4000030Bu, /* tcpwm[0].tr_all_cnt_in[25] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN12 = 0x4000030Cu, /* tcpwm[0].tr_all_cnt_in[26] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN13 = 0x4000030Du /* tcpwm[0].tr_all_cnt_in[27] */ +} en_trig_output_tcpwm0_2_t; + +/* Trigger Output Group 4 - HSIOM trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT0 = 0x40000400u, /* peri.tr_io_output[0] */ + TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT1 = 0x40000401u /* peri.tr_io_output[1] */ +} en_trig_output_hsiom_t; + +/* Trigger Output Group 5 - CPUSS Debug trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN0 = 0x40000500u, /* cpuss.cti_tr_in[0] */ + TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN1 = 0x40000501u /* cpuss.cti_tr_in[1] */ +} en_trig_output_cpuss_cti_t; + +/* Trigger Output Group 6 - MDMA trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_6_MDMA_TR_IN0 = 0x40000600u, /* cpuss.dmac_tr_in[0] */ + TRIG_OUT_MUX_6_MDMA_TR_IN1 = 0x40000601u /* cpuss.dmac_tr_in[1] */ +} en_trig_output_mdma_t; + +/* Trigger Output Group 7 - PERI Freeze trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_7_DEBUG_FREEZE_TR_IN = 0x40000700u, /* peri.tr_dbg_freeze */ + TRIG_OUT_MUX_7_TCPWM_DEBUG_FREEZE_TR_IN = 0x40000701u /* tcpwm[0].tr_debug_freeze */ +} en_trig_output_peri_freeze_t; + +/* Trigger Output Group 8 - Capsense trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_8_CSD_DSI_START = 0x40000800u /* csd.dsi_start */ +} en_trig_output_csd_t; + +/* Trigger Output Group 9 - ADC trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_9_PASS_TR_SAR_IN0 = 0x40000900u, /* pass.tr_sar_in[0] */ + TRIG_OUT_MUX_9_PASS_TR_SAR_IN1 = 0x40000901u /* pass.tr_sar_in[1] */ +} en_trig_output_sar_adc_start_t; + +/* Trigger Output Group 10 - CAN TT Synchronization triggers */ +typedef enum +{ + TRIG_OUT_MUX_10_CAN_TT_TR_IN0 = 0x40000A00u /* canfd[0].tr_evt_swt_in[0] */ +} en_trig_output_cantt_t; + +/* Trigger Output Group 0 - SCB PDMA0 Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_0_SCB0_TX_TO_PDMA0_TR_IN16 = 0x40001000u, /* From scb[0].tr_tx_req to cpuss.dw0_tr_in[16] */ + TRIG_OUT_1TO1_0_SCB0_RX_TO_PDMA0_TR_IN17 = 0x40001001u, /* From scb[0].tr_rx_req to cpuss.dw0_tr_in[17] */ + TRIG_OUT_1TO1_0_SCB1_TX_TO_PDMA0_TR_IN18 = 0x40001002u, /* From scb[1].tr_tx_req to cpuss.dw0_tr_in[18] */ + TRIG_OUT_1TO1_0_SCB1_RX_TO_PDMA0_TR_IN19 = 0x40001003u, /* From scb[1].tr_rx_req to cpuss.dw0_tr_in[19] */ + TRIG_OUT_1TO1_0_SCB2_TX_TO_PDMA0_TR_IN20 = 0x40001004u, /* From scb[2].tr_tx_req to cpuss.dw0_tr_in[20] */ + TRIG_OUT_1TO1_0_SCB2_RX_TO_PDMA0_TR_IN21 = 0x40001005u, /* From scb[2].tr_rx_req to cpuss.dw0_tr_in[21] */ + TRIG_OUT_1TO1_0_DUMMY_TO_PDMA0_TR_IN22 = 0x40001006u, /* From cpuss.zero to cpuss.dw0_tr_in[22] */ + TRIG_OUT_1TO1_0_DUMMY_TO_PDMA0_TR_IN23 = 0x40001007u, /* From cpuss.zero to cpuss.dw0_tr_in[23] */ + TRIG_OUT_1TO1_0_SCB4_TX_TO_PDMA0_TR_IN24 = 0x40001008u, /* From scb[4].tr_tx_req to cpuss.dw0_tr_in[24] */ + TRIG_OUT_1TO1_0_SCB4_RX_TO_PDMA0_TR_IN25 = 0x40001009u, /* From scb[4].tr_rx_req to cpuss.dw0_tr_in[25] */ + TRIG_OUT_1TO1_0_SCB5_TX_TO_PDMA0_TR_IN26 = 0x4000100Au, /* From scb[5].tr_tx_req to cpuss.dw0_tr_in[26] */ + TRIG_OUT_1TO1_0_SCB5_RX_TO_PDMA0_TR_IN27 = 0x4000100Bu /* From scb[5].tr_rx_req to cpuss.dw0_tr_in[27] */ +} en_trig_output_1to1_scb_pdma0_tr_t; + +/* Trigger Output Group 1 - SCB PDMA1 Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_1_SCB6_TX_TO_PDMA1_TR_IN8 = 0x40001100u, /* From scb[6].tr_tx_req to cpuss.dw1_tr_in[8] */ + TRIG_OUT_1TO1_1_SCB6_RX_TO_PDMA1_TR_IN9 = 0x40001101u, /* From scb[6].tr_rx_req to cpuss.dw1_tr_in[9] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN10 = 0x40001102u, /* From cpuss.zero to cpuss.dw1_tr_in[10] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN11 = 0x40001103u, /* From cpuss.zero to cpuss.dw1_tr_in[11] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN12 = 0x40001104u, /* From cpuss.zero to cpuss.dw1_tr_in[12] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN13 = 0x40001105u, /* From cpuss.zero to cpuss.dw1_tr_in[13] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN14 = 0x40001106u, /* From cpuss.zero to cpuss.dw1_tr_in[14] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN15 = 0x40001107u, /* From cpuss.zero to cpuss.dw1_tr_in[15] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN16 = 0x40001108u, /* From cpuss.zero to cpuss.dw1_tr_in[16] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN17 = 0x40001109u, /* From cpuss.zero to cpuss.dw1_tr_in[17] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN18 = 0x4000110Au, /* From cpuss.zero to cpuss.dw1_tr_in[18] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN19 = 0x4000110Bu, /* From cpuss.zero to cpuss.dw1_tr_in[19] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN20 = 0x4000110Cu, /* From cpuss.zero to cpuss.dw1_tr_in[20] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN21 = 0x4000110Du /* From cpuss.zero to cpuss.dw1_tr_in[21] */ +} en_trig_output_1to1_scb_pdma1_tr_t; + +/* Trigger Output Group 2 - PASS to PDMA0 direct connect (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_2_PASS_SAR0_DONE_TO_PDMA0_TR_IN28 = 0x40001200u /* From pass.tr_sar_out[0] to cpuss.dw0_tr_in[28] */ +} en_trig_output_1to1_sar0_to_pdma1_t; + +/* Trigger Output Group 3 - (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_3_SMIF_TX_TO_PDMA1_TR_IN22 = 0x40001300u, /* From smif.tr_tx_req to cpuss.dw1_tr_in[22] */ + TRIG_OUT_1TO1_3_SMIF_RX_TO_PDMA1_TR_IN23 = 0x40001301u, /* From smif.tr_rx_req to cpuss.dw1_tr_in[23] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN24 = 0x40001302u, /* From cpuss.zero to cpuss.dw1_tr_in[24] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN25 = 0x40001303u, /* From cpuss.zero to cpuss.dw1_tr_in[25] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN26 = 0x40001304u, /* From cpuss.zero to cpuss.dw1_tr_in[26] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN27 = 0x40001305u, /* From cpuss.zero to cpuss.dw1_tr_in[27] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN28 = 0x40001306u /* From cpuss.zero to cpuss.dw1_tr_in[28] */ +} en_trig_output_1to1_smif_to_pdma1_t; + +/* Trigger Output Group 4 - CAN DW triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_4_CAN_DBG_TO_PDMA1_TR_IN29 = 0x40001400u, /* From canfd[0].tr_dbg_dma_req[0] to cpuss.dw1_tr_in[29] */ + TRIG_OUT_1TO1_4_CAN_FIFO0_TO_PDMA1_TR_IN30 = 0x40001401u, /* From canfd[0].tr_fifo0[0] to cpuss.dw1_tr_in[30] */ + TRIG_OUT_1TO1_4_CAN_FIFO1_TO_PDMA1_TR_IN31 = 0x40001402u /* From canfd[0].tr_fifo1[0] to cpuss.dw1_tr_in[31] */ +} en_trig_output_1to1_can_dw_tr_t; + +/* Trigger Output Group 5 - USB PDMA0 Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_5_USB_DMA0_TO_PDMA0_TR_IN8 = 0x40001500u, /* From usb.dma_req[0] to cpuss.dw0_tr_in[8] */ + TRIG_OUT_1TO1_5_USB_DMA1_TO_PDMA0_TR_IN9 = 0x40001501u, /* From usb.dma_req[1] to cpuss.dw0_tr_in[9] */ + TRIG_OUT_1TO1_5_USB_DMA2_TO_PDMA0_TR_IN10 = 0x40001502u, /* From usb.dma_req[2] to cpuss.dw0_tr_in[10] */ + TRIG_OUT_1TO1_5_USB_DMA3_TO_PDMA0_TR_IN11 = 0x40001503u, /* From usb.dma_req[3] to cpuss.dw0_tr_in[11] */ + TRIG_OUT_1TO1_5_USB_DMA4_TO_PDMA0_TR_IN12 = 0x40001504u, /* From usb.dma_req[4] to cpuss.dw0_tr_in[12] */ + TRIG_OUT_1TO1_5_USB_DMA5_TO_PDMA0_TR_IN13 = 0x40001505u, /* From usb.dma_req[5] to cpuss.dw0_tr_in[13] */ + TRIG_OUT_1TO1_5_USB_DMA6_TO_PDMA0_TR_IN14 = 0x40001506u, /* From usb.dma_req[6] to cpuss.dw0_tr_in[14] */ + TRIG_OUT_1TO1_5_USB_DMA7_TO_PDMA0_TR_IN15 = 0x40001507u /* From usb.dma_req[7] to cpuss.dw0_tr_in[15] */ +} en_trig_output_1to1_usb_pdma0_tr_t; + +/* Trigger Output Group 6 - USB PDMA0 Acknowledge Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT8_TO_USB_ACK0 = 0x40001600u, /* From cpuss.dw0_tr_out[8] to usb.dma_burstend[0] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT9_TO_USB_ACK1 = 0x40001601u, /* From cpuss.dw0_tr_out[9] to usb.dma_burstend[1] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT10_TO_USB_ACK2 = 0x40001602u, /* From cpuss.dw0_tr_out[10] to usb.dma_burstend[2] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT11_TO_USB_ACK3 = 0x40001603u, /* From cpuss.dw0_tr_out[11] to usb.dma_burstend[3] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT12_TO_USB_ACK4 = 0x40001604u, /* From cpuss.dw0_tr_out[12] to usb.dma_burstend[4] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT13_TO_USB_ACK5 = 0x40001605u, /* From cpuss.dw0_tr_out[13] to usb.dma_burstend[5] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT14_TO_USB_ACK6 = 0x40001606u, /* From cpuss.dw0_tr_out[14] to usb.dma_burstend[6] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT15_TO_USB_ACK7 = 0x40001607u /* From cpuss.dw0_tr_out[15] to usb.dma_burstend[7] */ +} en_trig_output_1to1_usb_pdma0_ack_tr_t; + +/* Trigger Output Group 7 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_7_PDMA1_TR_OUT29_ACK_TO_CAN_0 = 0x40001700u /* From cpuss.dw1_tr_out[29] to canfd[0].tr_dbg_dma_ack[0] */ +} en_trig_output_1to1_can0_dw_ack_t; + +/* Trigger Output Group 8 - PASS SAR1 to PDMA0 direct connect (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_8_PASS_SAR1_DONE_TO_PDMA0_TR_IN29 = 0x40001800u /* From pass.tr_sar_out[1] to cpuss.dw0_tr_in[29] */ +} en_trig_output_1to1_sar1_to_pdma1_t; + +/* Level or edge detection setting for a trigger mux */ +typedef enum +{ + /* The trigger is a simple level output */ + TRIGGER_TYPE_LEVEL = 0u, + /* The trigger is synchronized to the consumer blocks clock + and a two cycle pulse is generated on this clock */ + TRIGGER_TYPE_EDGE = 1u +} en_trig_type_t; + +/* Trigger Type Defines */ +/* CANFD Trigger Types */ +#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE +/* CPUSS Trigger Types */ +#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE +/* CSD Trigger Types */ +#define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE +/* LPCOMP Trigger Types */ +#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL +/* PASS Trigger Types */ +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE +/* PERI Trigger Types */ +#define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE +/* SCB Trigger Types */ +#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* SMIF Trigger Types */ +#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* TCPWM Trigger Types */ +#define TRIGGER_TYPE_TCPWM_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL +/* USB Trigger Types */ +#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE + +/* Bus masters */ +typedef enum +{ + CPUSS_MS_ID_CM0 = 0, + CPUSS_MS_ID_CRYPTO = 1, + CPUSS_MS_ID_DW0 = 2, + CPUSS_MS_ID_DW1 = 3, + CPUSS_MS_ID_DMAC = 4, + CPUSS_MS_ID_SLOW0 = 5, + CPUSS_MS_ID_SLOW1 = 6, + CPUSS_MS_ID_CM4 = 14, + CPUSS_MS_ID_TC = 15 +} en_prot_master_t; + +/* Pointer to device configuration structure */ +#define CY_DEVICE_CFG (&cy_deviceIpBlockCfgPSoC6_04) + +/* Include IP definitions */ +#include "ip/cyip_sflash.h" +#include "ip/cyip_peri_v2.h" +#include "ip/cyip_peri_ms_v2.h" +#include "ip/cyip_crypto_v2.h" +#include "ip/cyip_cpuss_v2.h" +#include "ip/cyip_fault_v2.h" +#include "ip/cyip_ipc_v2.h" +#include "ip/cyip_prot_v2.h" +#include "ip/cyip_flashc_v2.h" +#include "ip/cyip_srss.h" +#include "ip/cyip_backup.h" +#include "ip/cyip_dw_v2.h" +#include "ip/cyip_dmac_v2.h" +#include "ip/cyip_efuse.h" +#include "ip/cyip_efuse_data_psoc6_04.h" +#include "ip/cyip_hsiom_v2.h" +#include "ip/cyip_gpio_v2.h" +#include "ip/cyip_smartio_v2.h" +#include "ip/cyip_lpcomp.h" +#include "ip/cyip_csd.h" +#include "ip/cyip_tcpwm_v2.h" +#include "ip/cyip_lcd_v2.h" +#include "ip/cyip_usbfs.h" +#include "ip/cyip_smif.h" +#include "ip/cyip_canfd.h" +#include "ip/cyip_scb.h" +#include "ip/cyip_scb.h" +#include "ip/cyip_ctbm_v2.h" +#include "ip/cyip_ctdac.h" +#include "ip/cyip_sar_v2.h" +#include "ip/cyip_pass_v2.h" + +/* IP type definitions */ +typedef SFLASH_V1_Type SFLASH_Type; +typedef PERI_GR_V2_Type PERI_GR_Type; +typedef PERI_TR_GR_V2_Type PERI_TR_GR_Type; +typedef PERI_TR_1TO1_GR_V2_Type PERI_TR_1TO1_GR_Type; +typedef PERI_V2_Type PERI_Type; +typedef PERI_MS_PPU_PR_V2_Type PERI_MS_PPU_PR_Type; +typedef PERI_MS_PPU_FX_V2_Type PERI_MS_PPU_FX_Type; +typedef PERI_MS_V2_Type PERI_MS_Type; +typedef CRYPTO_V2_Type CRYPTO_Type; +typedef CPUSS_V2_Type CPUSS_Type; +typedef FAULT_STRUCT_V2_Type FAULT_STRUCT_Type; +typedef FAULT_V2_Type FAULT_Type; +typedef IPC_STRUCT_V2_Type IPC_STRUCT_Type; +typedef IPC_INTR_STRUCT_V2_Type IPC_INTR_STRUCT_Type; +typedef IPC_V2_Type IPC_Type; +typedef PROT_SMPU_SMPU_STRUCT_V2_Type PROT_SMPU_SMPU_STRUCT_Type; +typedef PROT_SMPU_V2_Type PROT_SMPU_Type; +typedef PROT_MPU_MPU_STRUCT_V2_Type PROT_MPU_MPU_STRUCT_Type; +typedef PROT_MPU_V2_Type PROT_MPU_Type; +typedef PROT_V2_Type PROT_Type; +typedef FLASHC_FM_CTL_V2_Type FLASHC_FM_CTL_Type; +typedef FLASHC_V2_Type FLASHC_Type; +typedef MCWDT_STRUCT_V1_Type MCWDT_STRUCT_Type; +typedef SRSS_V1_Type SRSS_Type; +typedef BACKUP_V1_Type BACKUP_Type; +typedef DW_CH_STRUCT_V2_Type DW_CH_STRUCT_Type; +typedef DW_V2_Type DW_Type; +typedef DMAC_CH_V2_Type DMAC_CH_Type; +typedef DMAC_V2_Type DMAC_Type; +typedef EFUSE_V1_Type EFUSE_Type; +typedef HSIOM_PRT_V2_Type HSIOM_PRT_Type; +typedef HSIOM_V2_Type HSIOM_Type; +typedef GPIO_PRT_V2_Type GPIO_PRT_Type; +typedef GPIO_V2_Type GPIO_Type; +typedef SMARTIO_PRT_V2_Type SMARTIO_PRT_Type; +typedef SMARTIO_V2_Type SMARTIO_Type; +typedef LPCOMP_V1_Type LPCOMP_Type; +typedef CSD_V1_Type CSD_Type; +typedef TCPWM_GRP_CNT_V2_Type TCPWM_GRP_CNT_Type; +typedef TCPWM_GRP_V2_Type TCPWM_GRP_Type; +typedef TCPWM_V2_Type TCPWM_Type; +typedef LCD_V2_Type LCD_Type; +typedef USBFS_USBDEV_V1_Type USBFS_USBDEV_Type; +typedef USBFS_USBLPM_V1_Type USBFS_USBLPM_Type; +typedef USBFS_USBHOST_V1_Type USBFS_USBHOST_Type; +typedef USBFS_V1_Type USBFS_Type; +typedef SMIF_DEVICE_V1_Type SMIF_DEVICE_Type; +typedef SMIF_V1_Type SMIF_Type; +typedef CANFD_CH_M_TTCAN_V1_Type CANFD_CH_M_TTCAN_Type; +typedef CANFD_CH_V1_Type CANFD_CH_Type; +typedef CANFD_V1_Type CANFD_Type; +typedef CySCB_V1_Type CySCB_Type; +typedef CTBM_V2_Type CTBM_Type; +typedef CTDAC_V1_Type CTDAC_Type; +typedef SAR_V2_Type SAR_Type; +typedef PASS_TIMER_V2_Type PASS_TIMER_Type; +typedef PASS_LPOSC_V2_Type PASS_LPOSC_Type; +typedef PASS_FIFO_V2_Type PASS_FIFO_Type; +typedef PASS_AREFV2_V2_Type PASS_AREFV2_Type; +typedef PASS_V2_Type PASS_Type; + +/* Parameter Defines */ +/* Number of TTCAN instances */ +#define CANFD_CAN_NR 1u +/* ECC logic present or not */ +#define CANFD_ECC_PRESENT 0u +/* address included in ECC logic or not */ +#define CANFD_ECC_ADDR_PRESENT 0u +/* Time Stamp counter present or not (required for instance 0, otherwise not + allowed) */ +#define CANFD_TS_PRESENT 1u +/* Message RAM size in KB */ +#define CANFD_MRAM_SIZE 4u +/* Message RAM address width */ +#define CANFD_MRAM_ADDR_WIDTH 10u +/* UDB present or not ('0': no, '1': yes) */ +#define CPUSS_UDB_PRESENT 0u +/* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the + chips which doesn't use mxdft. */ +#define CPUSS_MBIST_MMIO_PRESENT 1u +/* System RAM 0 size in kilobytes */ +#define CPUSS_SRAM0_SIZE 128u +/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System + SRAM0 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC0_MACRO_NR 4u +/* System RAM 1 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC1_PRESENT 0u +/* System RAM 1 size in kilobytes */ +#define CPUSS_SRAM1_SIZE 1u +/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System + RAM 1 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC1_MACRO_NR 1u +/* System RAM 2 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC2_PRESENT 0u +/* System RAM 2 size in kilobytes */ +#define CPUSS_SRAM2_SIZE 1u +/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System + RAM 2 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC2_MACRO_NR 1u +/* System SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_PRESENT 0u +/* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_ADDR_PRESENT 0u +/* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ +#define CPUSS_ECC_PRESENT 0u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_ADDR_PRESENT 0u +/* System ROM size in KB */ +#define CPUSS_ROM_SIZE 64u +/* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM + is implemented with 4 128KB macros. */ +#define CPUSS_ROMC_MACRO_NR 1u +/* Flash memory present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_PRESENT 1u +/* Flash memory type ('0' : SONOS, '1': ECT) */ +#define CPUSS_FLASHC_ECT 0u +/* Flash main region size in KB */ +#define CPUSS_FLASH_SIZE 256u +/* Flash work region size in KB (EEPROM emulation, data) */ +#define CPUSS_WFLASH_SIZE 0u +/* Flash supervisory region size in KB */ +#define CPUSS_SFLASH_SIZE 32u +/* Flash data output word size (in Bytes) */ +#define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u +/* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special + sectors present in Flash. Part of main sector 0 is allowcated for Supervisory + Flash, and no Work Flash present. */ +#define CPUSS_FLASHC_SONOS_RWW 1u +/* SONOS Flash, number of main sectors. */ +#define CPUSS_FLASHC_SONOS_MAIN_SECTORS 2u +/* SONOS Flash, number of rows per main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_ROWS 256u +/* SONOS Flash, number of words per row of main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u +/* SONOS Flash, number of special sectors. */ +#define CPUSS_FLASHC_SONOS_SPL_SECTORS 1u +/* SONOS Flash, number of rows per special sector. */ +#define CPUSS_FLASHC_SONOS_SPL_ROWS 64u +/* Flash memory ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u +/* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_RAM_ECC_PRESENT 0u +/* Number of external slaves directly connected to slow AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_SLOW_SL_PRESENT 1u +/* Number of external slaves directly connected to fast AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_FAST_SL_PRESENT 1u +/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum + number of masters supported is 2. Width of this parameter is 2-bits. 1-bit + mask for each master indicating present or not. Example: 2'b01 - master 0 is + present. */ +#define CPUSS_SLOW_MS_PRESENT 0u +/* System interrupt functionality present or not ('0': no; '1': yes). Not used for + CM0+ PCU, which always uses system interrupt functionality. */ +#define CPUSS_SYSTEM_IRQ_PRESENT 0u +/* Number of total interrupt request inputs to CPUSS */ +#define CPUSS_SYSTEM_INT_NR 175u +/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ +#define CPUSS_SYSTEM_DPSLP_INT_NR 45u +/* CM4 CPU present or not ('0': no, '1': yes) */ +#define CPUSS_CM4_PRESENT 1u +/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 + levels of priority 8 = 256 levels of priority */ +#define CPUSS_CM4_LVL_WIDTH 3u +/* CM4 Floating point unit present or not (0=No, 1=Yes) */ +#define CPUSS_CM4_FPU_PRESENT 1u +/* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 + breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 + watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ +#define CPUSS_DEBUG_LVL 3u +/* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + + ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace + level is not supported in CPUSS. */ +#define CPUSS_TRACE_LVL 2u +/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ +#define CPUSS_ETB_PRESENT 0u +/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_MTB_SRAM_SIZE 4u +/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_ETB_SRAM_SIZE 8u +/* PTM interface present (0=No, 1=Yes) */ +#define CPUSS_PTM_PRESENT 0u +/* Width of the PTM interface in bits ([2,32]) */ +#define CPUSS_PTM_WIDTH 1u +/* Width of the TPIU interface in bits ([1,4]) */ +#define CPUSS_TPIU_WIDTH 4u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPID 52u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPCONTINUATION 0u +/* CoreSight Part Identification Number */ +#define CPUSS_FAMILYID 270u +/* ROM trim register width (for ARM 3, for Synopsys 5) */ +#define CPUSS_ROM_TRIM_WIDTH 5u +/* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ +#define CPUSS_ROM_TRIM_DEFAULT 18u +/* RAM trim register width (for ARM 8, for Synopsys 15) */ +#define CPUSS_RAM_TRIM_WIDTH 15u +/* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ +#define CPUSS_RAM_TRIM_DEFAULT 24594u +/* Cryptography IP present or not (0=No, 1=Yes) */ +#define CPUSS_CRYPTO_PRESENT 1u +/* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_SW_TR_PRESENT 0u +/* DataWire 0 present or not (0=No, 1=Yes) */ +#define CPUSS_DW0_PRESENT 1u +/* Number of DataWire 0 channels (8, 16 or 32) */ +#define CPUSS_DW0_CH_NR 30u +/* DataWire 1 present or not (0=No, 1=Yes) */ +#define CPUSS_DW1_PRESENT 1u +/* Number of DataWire 1 channels (8, 16 or 32) */ +#define CPUSS_DW1_CH_NR 32u +/* DMA controller present or not ('0': no, '1': yes) */ +#define CPUSS_DMAC_PRESENT 1u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 2u +/* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_SW_TR_PRESENT 0u +/* Copy value from Globals */ +#define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u +/* ETAS Calibration support pin out present (automotive only) */ +#define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u +/* TRACE_LVL>0 */ +#define CPUSS_CHIP_TOP_TRACE_PRESENT 1u +/* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u +/* Number of DataWire controllers present (max 2) (same as DW.NR above) */ +#define CPUSS_CPUSS_DW_DW_NR 2u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 30u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 32u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u +/* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_PRESENT 0u +/* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u +/* AES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_AES 1u +/* (Tripple) DES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_DES 1u +/* Chacha support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CHACHA 1u +/* Pseudo random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_PR 1u +/* SHA1 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA1 1u +/* SHA2 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA2 1u +/* SHA3 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA3 1u +/* Cyclic Redundancy Check support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CRC 1u +/* True random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_TR 1u +/* Vector unit support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_VU 1u +/* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_GCM 1u +/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, + 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 + kB and 16 kB memory buffer) */ +#define CPUSS_CRYPTO_BUFF_SIZE 1024u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 2u +/* Number of DataWire controllers present (max 2) */ +#define CPUSS_DW_NR 2u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* Number of fault structures. Legal range [1, 4] */ +#define CPUSS_FAULT_FAULT_NR 2u +/* Number of Flash BIST_DATA registers */ +#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u +/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ +#define CPUSS_FLASHC_PA_SIZE 128u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_SONOS 1u +/* eCT Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_ECT 0u +/* CM4 CPU present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_CM4_PRESENT 1u +/* Number of IPC structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_NR 16u +/* Number of IPC interrupt structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_IRQ_NR 16u +/* Master 0 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u +/* Master 1 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u +/* Master 2 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u +/* Master 3 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u +/* Master 4 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u +/* Master 5 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u +/* Master 6 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u +/* Master 7 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u +/* Master 8 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u +/* Master 9 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u +/* Master 10 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u +/* Master 11 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u +/* Master 12 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u +/* Master 13 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u +/* Master 14 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u +/* Master 15 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u +/* Number of SMPU protection structures */ +#define CPUSS_PROT_SMPU_STRUCT_NR 16u +/* Number of protection contexts supported minus 1. Legal range [1,16] */ +#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u +/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ +#define EFUSE_EFUSE_NR 4u +/* Number of GPIO ports in range 0..31 */ +#define IOSS_GPIO_GPIO_PORT_NR_0_31 15u +/* Number of GPIO ports in range 32..63 */ +#define IOSS_GPIO_GPIO_PORT_NR_32_63 0u +/* Number of GPIO ports in range 64..95 */ +#define IOSS_GPIO_GPIO_PORT_NR_64_95 0u +/* Number of GPIO ports in range 96..127 */ +#define IOSS_GPIO_GPIO_PORT_NR_96_127 0u +/* Number of ports in device */ +#define IOSS_GPIO_GPIO_PORT_NR 15u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 0u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_GPIO 0u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_GPIO 0u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u +/* Number of AMUX splitter cells */ +#define IOSS_HSIOM_AMUX_SPLIT_NR 6u +/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ +#define IOSS_HSIOM_HSIOM_PORT_NR 15u +/* Number of PWR/GND MONITOR CELLs in the device */ +#define IOSS_HSIOM_MONITOR_NR 0u +/* Number of PWR/GND MONITOR CELLs in range 0..31 */ +#define IOSS_HSIOM_MONITOR_NR_0_31 0u +/* Number of PWR/GND MONITOR CELLs in range 32..63 */ +#define IOSS_HSIOM_MONITOR_NR_32_63 0u +/* Number of PWR/GND MONITOR CELLs in range 64..95 */ +#define IOSS_HSIOM_MONITOR_NR_64_95 0u +/* Number of PWR/GND MONITOR CELLs in range 96..127 */ +#define IOSS_HSIOM_MONITOR_NR_96_127 0u +/* Indicates the presence of alternate JTAG interface */ +#define IOSS_HSIOM_ALTJTAG_PRESENT 0u +/* Mask of SMARTIO instances presence */ +#define IOSS_SMARTIO_SMARTIO_MASK 512u +/* Number of ports supoprting up to 4 COMs */ +#define LCD_NUMPORTS 8u +/* Number of ports supporting up to 8 COMs */ +#define LCD_NUMPORTS8 8u +/* Number of ports supporting up to 16 COMs */ +#define LCD_NUMPORTS16 0u +/* Max number of LCD commons supported */ +#define LCD_CHIP_TOP_COM_NR 8u +/* Max number of LCD pins (total) supported */ +#define LCD_CHIP_TOP_PIN_NR 60u +/* Number of CTBs in the Subsystem */ +#define PASS_NR_CTBS 1u +/* Number of CTDACs in the Subsystem */ +#define PASS_NR_CTDACS 1u +/* Number of SARs in the Subsystem */ +#define PASS_NR_SARS 2u +/* Number of IREF outputs from AREF */ +#define PASS_NR_IREFS 4u +/* CTB0 Exists */ +#define PASS_CTB0_EXISTS 1u +/* CTB1 Exists */ +#define PASS_CTB1_EXISTS 0u +/* CTB2 Exists */ +#define PASS_CTB2_EXISTS 0u +/* CTB3 Exists */ +#define PASS_CTB3_EXISTS 0u +/* CTDAC0 Exists */ +#define PASS_CTDAC0_EXISTS 1u +/* CTDAC1 Exists */ +#define PASS_CTDAC1_EXISTS 0u +/* CTDAC2 Exists */ +#define PASS_CTDAC2_EXISTS 0u +/* CTDAC3 Exists */ +#define PASS_CTDAC3_EXISTS 0u +/* SAR0 Exists */ +#define PASS_SAR0_EXISTS 1u +/* SAR1 Exists */ +#define PASS_SAR1_EXISTS 1u +/* SAR2 Exists */ +#define PASS_SAR2_EXISTS 0u +/* SAR3 Exists */ +#define PASS_SAR3_EXISTS 0u +/* NR_SARS*UDB_PRESENT */ +#define PASS_SAR_UDB_IF 0u +/* NR_CTBS*UDB_PRESENT */ +#define PASS_CTB_UDB_IF 0u +/* NR_CTDACS*UDB_PRESENT */ +#define PASS_CTDAC_UDB_IF 0u +#define PASS_CTBM_CTDAC_PRESENT 1u +#define PASS_CTBM_UDB_PRESENT 0u +/* Number of SAR channels */ +#define PASS_SAR_SAR_CHANNELS 16u +/* Averaging logic present in SAR */ +#define PASS_SAR_SAR_AVERAGE 1u +/* Range detect logic present in SAR */ +#define PASS_SAR_SAR_RANGEDET 1u +/* Support for UAB sampling */ +#define PASS_SAR_SAR_UAB 0u +#define PASS_SAR_CTB0_EXISTS 1u +#define PASS_SAR_UDB_PRESENT 0u +/* The number of protection contexts ([2, 16]). */ +#define PERI_PC_NR 8u +/* Master interface presence mask (4 bits) */ +#define PERI_MS_PRESENT 15u +/* Protection structures SRAM ECC present or not ('0': no, '1': yes) */ +#define PERI_ECC_PRESENT 0u +/* Protection structures SRAM address ECC present or not ('0': no, '1': yes) */ +#define PERI_ECC_ADDR_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 1u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Number of programmable clocks (outputs) */ +#define PERI_CLOCK_NR 28u +/* Number of 8.0 dividers */ +#define PERI_DIV_8_NR 4u +/* Number of 16.0 dividers */ +#define PERI_DIV_16_NR 8u +/* Number of 16.5 (fractional) dividers */ +#define PERI_DIV_16_5_NR 2u +/* Number of 24.5 (fractional) dividers */ +#define PERI_DIV_24_5_NR 1u +/* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ +#define PERI_DIV_ADDR_WIDTH 3u +/* Timeout functionality present ('0': no, '1': yes) */ +#define PERI_TIMEOUT_PRESENT 1u +/* Trigger module present (0=No, 1=Yes) */ +#define PERI_TR 1u +/* Number of trigger groups */ +#define PERI_TR_GROUP_NR 11u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR10_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR5_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR7_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR8_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ +#define PERI_MASTER_WIDTH 8u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB0_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB0_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB0_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB0_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB0_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB0_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB0_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB0_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB0_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB0_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB0_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB0_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB0_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB0_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB0_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB0_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB0_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB0_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB0_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB0_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB0_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB0_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB0_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB0_CHIP_TOP_SPI_SEL_NR 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB1_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB1_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB1_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB1_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB1_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB1_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB1_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB1_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB1_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB1_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB1_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB1_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB1_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB1_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB1_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB1_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB1_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB1_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB1_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB1_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB1_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB1_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB1_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB1_CHIP_TOP_SPI_SEL_NR 4u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB2_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB2_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB2_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB2_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB2_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB2_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB2_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB2_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB2_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB2_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB2_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB2_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB2_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB2_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB2_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB2_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB2_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB2_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB2_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB2_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB2_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB2_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB2_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB2_CHIP_TOP_SPI_SEL_NR 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB3_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB3_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB3_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB3_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB3_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB3_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB3_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB3_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB3_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB3_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB3_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB3_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB3_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB3_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB3_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB3_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB3_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB3_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB3_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB3_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB3_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB3_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB3_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB3_CHIP_TOP_SPI_SEL_NR 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB4_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB4_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB4_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB4_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB4_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB4_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB4_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB4_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB4_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB4_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB4_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB4_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB4_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB4_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB4_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB4_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB4_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB4_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB4_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB4_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB4_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB4_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB4_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB4_CHIP_TOP_SPI_SEL_NR 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB5_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB5_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB5_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB5_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB5_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB5_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB5_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB5_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB5_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB5_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB5_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB5_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB5_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB5_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB5_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB5_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB5_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB5_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB5_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB5_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB5_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB5_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB5_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB5_CHIP_TOP_SPI_SEL_NR 4u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define SFLASH_FLASHC_IS_SONOS 1u +/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ +#define SFLASH_CPUSS_WOUNDING_PRESENT 0u +/* Base address of the SMIF XIP memory region. This address must be a multiple of + the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This + address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP + memory region should NOT overlap with other memory regions. */ +#define SMIF_SMIF_XIP_ADDR 402653184u +/* Capacity of the SMIF XIP memory region. The more significant bits of this + parameter must be '1' and the lesser significant bits of this paramter must + be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are + {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, + 0xffe0:0000, ..., 0xe000:0000}. */ +#define SMIF_SMIF_XIP_MASK 4160749568u +/* Cryptography (AES) support ('0' = no support, '1' = support) */ +#define SMIF_CRYPTO 1u +/* Number of external devices supported ([1,4]) */ +#define SMIF_DEVICE_NR 3u +/* External device write support. This is a 4-bit field. Each external device has + a dedicated bit. E.g., if bit 2 is '1', external device 2 has write support. */ +#define SMIF_DEVICE_WR_EN 15u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ +#define SMIF_MASTER_WIDTH 8u +/* Chip top connect all 8 data pins (0= connect 4 or 6 data pins based on + DATA6_PRESENT, 1= connect 8 data pins) */ +#define SMIF_CHIP_TOP_DATA8_PRESENT 0u +/* Number of used spi_select signals (max 4) */ +#define SMIF_CHIP_TOP_SPI_SEL_NR 3u +/* Number of regulator modules instantiated within SRSS, start with estimate, + update after CMR feedback */ +#define SRSS_NUM_ACTREG_PWRMOD 2u +/* Number of shorting switches between vccd and vccact (target dynamic voltage + drop < 10mV) */ +#define SRSS_NUM_ACTIVE_SWITCH 3u +/* ULP linear regulator system is present */ +#define SRSS_ULPLINREG_PRESENT 1u +/* HT linear regulator system is present */ +#define SRSS_HTLINREG_PRESENT 0u +/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT + or SIMOBUCK_PRESENT. */ +#define SRSS_BUCKCTL_PRESENT 1u +/* Low-current SISO buck core regulator is present. Only compatible with ULP + linear regulator system (ULPLINREG_PRESENT==1). */ +#define SRSS_S40S_SISOBUCKLC_PRESENT 1u +/* SIMO buck core regulator is present. Only compatible with ULP linear regulator + system (ULPLINREG_PRESENT==1). */ +#define SRSS_SIMOBUCK_PRESENT 0u +/* Precision ILO (PILO) is present */ +#define SRSS_PILO_PRESENT 0u +/* External Crystal Oscillator is present (high frequency) */ +#define SRSS_ECO_PRESENT 1u +/* System Buck-Boost is present */ +#define SRSS_SYSBB_PRESENT 0u +/* Number of clock paths. Must be > 0 */ +#define SRSS_NUM_CLKPATH 5u +/* Number of PLLs present. Must be <= NUM_CLKPATH */ +#define SRSS_NUM_PLL 1u +/* Number of HFCLK roots present. Must be > 0 */ +#define SRSS_NUM_HFROOT 4u +/* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ +#define SRSS_NUM_HIBDATA 1u +/* Backup domain is present (includes RTC and WCO) */ +#define SRSS_BACKUP_PRESENT 1u +/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of + mask indicates presence of a CSV. */ +#define SRSS_MASK_HFCSV 0u +/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ +#define SRSS_WCOCSV_PRESENT 0u +/* Number of software watchdog timers. */ +#define SRSS_NUM_MCWDT 2u +/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ +#define SRSS_NUM_DSI 0u +/* Alternate high-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTHF_PRESENT 0u +/* Alternate low-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTLF_PRESENT 0u +/* Use the hardened clkactfllmux block */ +#define SRSS_USE_HARD_CLKACTFLLMUX 1u +/* Number of clock paths, including direct paths in hardened clkactfllmux block + (Must be >= NUM_CLKPATH) */ +#define SRSS_HARD_CLKPATH 6u +/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= + NUM_PLL+1) */ +#define SRSS_HARD_CLKPATHMUX 6u +/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ +#define SRSS_HARD_HFROOT 6u +/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ +#define SRSS_HARD_ECOMUX_PRESENT 1u +/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ +#define SRSS_HARD_ALTHFMUX_PRESENT 1u +/* SRSS version is at least SRSS_VER1P3. Set to 1 for new products. Set to 0 for + PSoC6ABLE2, PSoC6A2M. */ +#define SRSS_SRSS_VER1P3 1u +/* Backup memory is present (only used when BACKUP_PRESENT==1) */ +#define SRSS_BACKUP_BMEM_PRESENT 0u +/* Number of Backup registers to include (each is 32b). Only used when + BACKUP_PRESENT==1. */ +#define SRSS_BACKUP_NUM_BREG 16u +/* Number of input triggers per counter only routed to one counter (0..8) */ +#define TCPWM_TR_ONE_CNT_NR 1u +/* Number of input triggers routed to all counters (0..254), TR_ONE_CNT_NR+TR_ALL + CNT_NR <= 254 */ +#define TCPWM_TR_ALL_CNT_NR 28u +/* Number of TCPWM counter groups (1..4) */ +#define TCPWM_GRP_NR 2u +/* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ +#define TCPWM_GRP_NR0_CNT_GRP_CNT_WIDTH 32u +/* Second Capture / Compare Unit is present (0, 1) */ +#define TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT 0u +/* Advanced Motor Control features are present (0, 1). Should only be 1 when + GRP_CC1_PRESENT = 1 */ +#define TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT 0u +/* Stepper Motor Control features are present (0, 1). */ +#define TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT 0u +/* Number of counters per TCPWM group (1..256) */ +#define TCPWM_GRP_NR0_GRP_GRP_CNT_NR 4u +/* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ +#define TCPWM_GRP_NR1_CNT_GRP_CNT_WIDTH 16u +/* Second Capture / Compare Unit is present (0, 1) */ +#define TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT 1u +/* Advanced Motor Control features are present (0, 1). Should only be 1 when + GRP_CC1_PRESENT = 1 */ +#define TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT 1u +/* Stepper Motor Control features are present (0, 1). */ +#define TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT 0u +/* Number of counters per TCPWM group (1..256) */ +#define TCPWM_GRP_NR1_GRP_GRP_CNT_NR 8u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ +#define TCPWM_MASTER_WIDTH 8u + +/* MMIO Targets Defines */ +#define CY_MMIO_CRYPTO_GROUP_NR 1u +#define CY_MMIO_CRYPTO_SLAVE_NR 0u +#define CY_MMIO_CPUSS_GROUP_NR 2u +#define CY_MMIO_CPUSS_SLAVE_NR 0u +#define CY_MMIO_FAULT_GROUP_NR 2u +#define CY_MMIO_FAULT_SLAVE_NR 1u +#define CY_MMIO_IPC_GROUP_NR 2u +#define CY_MMIO_IPC_SLAVE_NR 2u +#define CY_MMIO_PROT_GROUP_NR 2u +#define CY_MMIO_PROT_SLAVE_NR 3u +#define CY_MMIO_FLASHC_GROUP_NR 2u +#define CY_MMIO_FLASHC_SLAVE_NR 4u +#define CY_MMIO_SRSS_GROUP_NR 2u +#define CY_MMIO_SRSS_SLAVE_NR 6u +#define CY_MMIO_BACKUP_GROUP_NR 2u +#define CY_MMIO_BACKUP_SLAVE_NR 7u +#define CY_MMIO_DW_GROUP_NR 2u +#define CY_MMIO_DW_SLAVE_NR 8u +#define CY_MMIO_DMAC_GROUP_NR 2u +#define CY_MMIO_DMAC_SLAVE_NR 10u +#define CY_MMIO_EFUSE_GROUP_NR 2u +#define CY_MMIO_EFUSE_SLAVE_NR 12u +#define CY_MMIO_HSIOM_GROUP_NR 3u +#define CY_MMIO_HSIOM_SLAVE_NR 0u +#define CY_MMIO_GPIO_GROUP_NR 3u +#define CY_MMIO_GPIO_SLAVE_NR 1u +#define CY_MMIO_SMARTIO_GROUP_NR 3u +#define CY_MMIO_SMARTIO_SLAVE_NR 2u +#define CY_MMIO_LPCOMP_GROUP_NR 3u +#define CY_MMIO_LPCOMP_SLAVE_NR 5u +#define CY_MMIO_CSD0_GROUP_NR 3u +#define CY_MMIO_CSD0_SLAVE_NR 6u +#define CY_MMIO_TCPWM0_GROUP_NR 3u +#define CY_MMIO_TCPWM0_SLAVE_NR 8u +#define CY_MMIO_LCD0_GROUP_NR 3u +#define CY_MMIO_LCD0_SLAVE_NR 11u +#define CY_MMIO_USBFS0_GROUP_NR 3u +#define CY_MMIO_USBFS0_SLAVE_NR 15u +#define CY_MMIO_SMIF0_GROUP_NR 4u +#define CY_MMIO_SMIF0_SLAVE_NR 2u +#define CY_MMIO_CANFD0_GROUP_NR 5u +#define CY_MMIO_CANFD0_SLAVE_NR 2u +#define CY_MMIO_SCB0_GROUP_NR 6u +#define CY_MMIO_SCB0_SLAVE_NR 0u +#define CY_MMIO_SCB1_GROUP_NR 6u +#define CY_MMIO_SCB1_SLAVE_NR 1u +#define CY_MMIO_SCB2_GROUP_NR 6u +#define CY_MMIO_SCB2_SLAVE_NR 2u +#define CY_MMIO_SCB04_GROUP_NR 6u +#define CY_MMIO_SCB04_SLAVE_NR 4u +#define CY_MMIO_SCB05_GROUP_NR 6u +#define CY_MMIO_SCB05_SLAVE_NR 5u +#define CY_MMIO_SCB06_GROUP_NR 6u +#define CY_MMIO_SCB06_SLAVE_NR 6u +#define CY_MMIO_PASS_GROUP_NR 9u +#define CY_MMIO_PASS_SLAVE_NR 0u + +/* Backward compatibility definitions */ +#define CPUSS_IRQ_NR CPUSS_SYSTEM_INT_NR +#define CPUSS_DPSLP_IRQ_NR CPUSS_SYSTEM_DPSLP_INT_NR + +#endif /* _PSOC6_04_CONFIG_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6a256k.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6a256k.h new file mode 100644 index 0000000000..c0284864da --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6a256k.h @@ -0,0 +1,1197 @@ +/***************************************************************************//** +* \file psoc6a256k.h +* +* \brief +* PSoC6A256K device header +* +* \note +* Generator version: 1.5.1.42 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _PSOC6A256K_H_ +#define _PSOC6A256K_H_ + +/** +* \addtogroup group_device PSoC6A256K +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* PSoC6A256K User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* PSoC6A256K Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* PSoC6A256K Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* PSoC6A256K interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +//#define CY_IP_MXS40PASS 1u +//#define CY_IP_MXS40PASS_INSTANCES 1u +//#define CY_IP_MXS40PASS_VERSION 2u +//#define CY_IP_MXS40PASS_SAR 1u +//#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +//#define CY_IP_MXS40PASS_SAR_VERSION 2u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +//#define CY_IP_MXTCPWM 1u +//#define CY_IP_MXTCPWM_INSTANCES 1u +//#define CY_IP_MXTCPWM_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_68_qfn.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xFFFFFFFFUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409D0000UL +#define SAR1_BASE 0x409E0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409D0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409E0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} PSoC6A256K */ + +#endif /* _PSOC6A256K_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h index b75868e107..c23e6316f9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_ble_clk.h -* \version 3.30 +* \version 3.40 * * The header file of the BLE ECO clock driver. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -70,6 +70,11 @@ * * * +* +* +* +* +* * * * @@ -127,7 +132,7 @@ extern "C" { #define CY_BLE_CLK_DRV_VERSION_MAJOR (3) /** Driver minor version */ -#define CY_BLE_CLK_DRV_VERSION_MINOR (20) +#define CY_BLE_CLK_DRV_VERSION_MINOR (40) /** Driver ID */ #define CY_BLE_CLK_ID (0x05UL << 18U) @@ -272,10 +277,28 @@ typedef struct * \{ */ cy_en_ble_eco_status_t Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq, - cy_en_ble_eco_sys_clk_div_t sysClkDiv, - uint32_t cLoad, uint32_t xtalStartUpTime, - cy_en_ble_eco_voltage_reg_t voltageReg); + cy_en_ble_eco_sys_clk_div_t sysClkDiv, + uint32_t cLoad, + uint32_t xtalStartUpTime, + cy_en_ble_eco_voltage_reg_t voltageReg); void Cy_BLE_EcoReset(void); +__STATIC_INLINE bool Cy_BLE_EcoIsEnabled(void); + + +/******************************************************************************* +* Function Name: Cy_BLE_EcoIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled BLE ECO status. +* +* \return Boolean status of BLE ECO: true - Enabled, false - Disabled. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_BLE_EcoIsEnabled(void) +{ + return (((BLE_BLESS_MT_CFG & BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk) != 0u) && + ((BLE_BLESS_MT_STATUS & BLE_BLESS_MT_STATUS_BLESS_STATE_Msk) != 0u)); +} /** \} */ /** \cond INTERNAL */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_canfd.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_canfd.h index 09dd4119d6..d551291f59 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_canfd.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_canfd.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_canfd.h -* \version 1.0.1 +* \version 1.10 * * This file provides constants and parameter values for * the CAN FD driver. * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -217,6 +217,11 @@ *
VersionChangesReason of Change
3.40A new API function \ref Cy_BLE_EcoIsEnabled() is added.API enhancement.
3.30Updated the \ref Cy_BLE_EcoConfigure() to reuse the \ref Cy_SysClk_ClkPeriGetFrequency().API enhancement.
* * +* +* +* +* +* * * * @@ -266,7 +271,7 @@ extern "C" { #define CY_CANFD_DRV_VERSION_MAJOR 1U /** Driver minor version */ -#define CY_CANFD_DRV_VERSION_MINOR 0U +#define CY_CANFD_DRV_VERSION_MINOR 10U /** CAN FD driver ID */ #define CY_CANFD_ID CY_PDL_DRV_ID (0x45U) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h index 1f2060bf82..d438e510a1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -200,6 +200,7 @@ typedef struct extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01; extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02; extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03; +extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_04; extern const cy_stc_device_t * cy_device; @@ -1084,26 +1085,26 @@ void Cy_PDL_Init(const cy_stc_device_t * device); * BLE *******************************************************************************/ -#define BLE_RCB_INTR (((BLE_V1_Type *) BLE)->RCB.INTR) -#define BLE_RCB_TX_FIFO_WR (((BLE_V1_Type *) BLE)->RCB.TX_FIFO_WR) -#define BLE_RCB_RX_FIFO_RD (((BLE_V1_Type *) BLE)->RCB.RX_FIFO_RD) -#define BLE_RCB_CTRL (((BLE_V1_Type *) BLE)->RCB.CTRL) -#define BLE_RCB_RCBLL_CTRL (((BLE_V1_Type *) BLE)->RCB.RCBLL.CTRL) -#define BLE_BLESS_XTAL_CLK_DIV_CONFIG (((BLE_V1_Type *) BLE)->BLESS.XTAL_CLK_DIV_CONFIG) -#define BLE_BLESS_MT_CFG (((BLE_V1_Type *) BLE)->BLESS.MT_CFG) -#define BLE_BLESS_MT_STATUS (((BLE_V1_Type *) BLE)->BLESS.MT_STATUS) -#define BLE_BLESS_MT_DELAY_CFG (((BLE_V1_Type *) BLE)->BLESS.MT_DELAY_CFG) -#define BLE_BLESS_MT_DELAY_CFG2 (((BLE_V1_Type *) BLE)->BLESS.MT_DELAY_CFG2) -#define BLE_BLESS_MT_DELAY_CFG3 (((BLE_V1_Type *) BLE)->BLESS.MT_DELAY_CFG3) -#define BLE_BLESS_MT_VIO_CTRL (((BLE_V1_Type *) BLE)->BLESS.MT_VIO_CTRL) -#define BLE_BLESS_LL_CLK_EN (((BLE_V1_Type *) BLE)->BLESS.LL_CLK_EN) -#define BLE_BLESS_MISC_EN_CTRL (((BLE_V1_Type *) BLE)->BLESS.MISC_EN_CTRL) -#define BLE_BLESS_INTR_STAT (((BLE_V1_Type *) BLE)->BLESS.INTR_STAT) -#define BLE_BLELL_EVENT_INTR (((BLE_V1_Type *) BLE)->BLELL.EVENT_INTR) -#define BLE_BLELL_CONN_INTR (((BLE_V1_Type *) BLE)->BLELL.CONN_INTR) -#define BLE_BLELL_CONN_EXT_INTR (((BLE_V1_Type *) BLE)->BLELL.CONN_EXT_INTR) -#define BLE_BLELL_SCAN_INTR (((BLE_V1_Type *) BLE)->BLELL.SCAN_INTR) -#define BLE_BLELL_ADV_INTR (((BLE_V1_Type *) BLE)->BLELL.ADV_INTR) +#define BLE_RCB_INTR (((BLE_V1_Type *) BLE_BASE)->RCB.INTR) +#define BLE_RCB_TX_FIFO_WR (((BLE_V1_Type *) BLE_BASE)->RCB.TX_FIFO_WR) +#define BLE_RCB_RX_FIFO_RD (((BLE_V1_Type *) BLE_BASE)->RCB.RX_FIFO_RD) +#define BLE_RCB_CTRL (((BLE_V1_Type *) BLE_BASE)->RCB.CTRL) +#define BLE_RCB_RCBLL_CTRL (((BLE_V1_Type *) BLE_BASE)->RCB.RCBLL.CTRL) +#define BLE_BLESS_XTAL_CLK_DIV_CONFIG (((BLE_V1_Type *) BLE_BASE)->BLESS.XTAL_CLK_DIV_CONFIG) +#define BLE_BLESS_MT_CFG (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_CFG) +#define BLE_BLESS_MT_STATUS (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_STATUS) +#define BLE_BLESS_MT_DELAY_CFG (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG) +#define BLE_BLESS_MT_DELAY_CFG2 (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG2) +#define BLE_BLESS_MT_DELAY_CFG3 (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG3) +#define BLE_BLESS_MT_VIO_CTRL (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_VIO_CTRL) +#define BLE_BLESS_LL_CLK_EN (((BLE_V1_Type *) BLE_BASE)->BLESS.LL_CLK_EN) +#define BLE_BLESS_MISC_EN_CTRL (((BLE_V1_Type *) BLE_BASE)->BLESS.MISC_EN_CTRL) +#define BLE_BLESS_INTR_STAT (((BLE_V1_Type *) BLE_BASE)->BLESS.INTR_STAT) +#define BLE_BLELL_EVENT_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.EVENT_INTR) +#define BLE_BLELL_CONN_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_INTR) +#define BLE_BLELL_CONN_EXT_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_EXT_INTR) +#define BLE_BLELL_SCAN_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.SCAN_INTR) +#define BLE_BLELL_ADV_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.ADV_INTR) /******************************************************************************* diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_efuse.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_efuse.h index cb14d9c97f..caa6a62517 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_efuse.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_efuse.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_efuse.h -* \version 1.10.1 +* \version 1.10.2 * * Provides the API declarations of the eFuse driver. * @@ -85,6 +85,11 @@ *
VersionChangesReason for Change
1.10Updated of the \ref Cy_CANFD_Init() functionsAllow initing CANFD with 0 number of SID/XID filters
1.0.1Updated description of the \ref Cy_CANFD_Init() and \ref Cy_CANFD_DeInit() functionsDocumentation update and clarification
* * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h index f39679c5a6..582734bbe5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_flash.h -* \version 3.30.3 +* \version 3.30.4 * * Provides the API declarations of the Flash driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,8 +42,8 @@ * or modify the SROM code. The driver API requests the system call by acquiring * the Inter-processor communication (IPC) and writing the SROM function opcode * and parameters to its input registers. As a result, an NMI interrupt is invoked -* and the requested SROM API is executed. The operation status is returned to the -* driver context and a release interrupt is triggered. +* and the requested SROM function is executed. The operation status is returned +* to the driver context and a release interrupt is triggered. * * Writing to flash can take up to 20 milliseconds. During this time, * the device should not be reset (including XRES pin, software reset, and @@ -55,7 +55,7 @@ * in the same or neighboring (neighboring restriction is applicable just for the * CY8C6xx6, CY8C6xx7 devices) flash sector where the flash Write, Erase, or * Program operation is working. This violation may cause a HardFault exception. -* To avoid the Read while Write violation, the user must carefully split the +* To avoid the Read while Write violation, carefully split the * Read and Write operation on flash sectors which are not neighboring, * considering both cores in the multi-processor device. If the flash is divided * into four equal sectors, you may edit the linker script to place the code @@ -66,18 +66,18 @@ * * \subsection group_flash_config_intro Introduction: * The PSoC 6 MCU user-programmable Flash consists of: -* - User Flash sectors (from 4 to 8) - 256KB each. -* - EEPROM emulation sector - 32KB. +* - Application flash memory (from 2 to 8 sectors) - 128KB/256KB each. +* - EE emulation flash memory - 32KB. * -* Write operations are performed on a per-sector basis and may be done as -* Blocking or Partially Blocking, defined as follows: +* Write operation may be done as Blocking or Partially Blocking, +* defined as follows: * * \subsection group_flash_config_blocking Blocking: * In this case, the entire Flash block is not available for the duration of the * Write (∼16ms). Therefore, no Flash accesses (from any Bus Master) can * occur during that time. CPU execution can be performed from SRAM. All -* pre-fetching must be disabled. Application code execution from Flash is -* blocked for the Flash Write duration for both cores. +* pre-fetching must be disabled. Code execution from Flash is blocked for the +* Flash Write duration for both cores. * * \subsection group_flash_config_block_const Constraints for Blocking Flash operations: * -# During write to flash, the device should not be reset (including XRES pin, @@ -85,16 +85,16 @@ * of the flash. * -# The low-voltage detect circuits should be configured to generate an * interrupt instead of a reset. -* -# Flash write operation is allowed only in one of the following CM4 states: +* -# Flash rite operation is allowed only in one of the following CM4 states: * -# CM4 is Active and initialized:
* call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)". * Note: If desired user may put CM4 core in Deep Sleep any time * after calling Cy_SysEnableCM4(). -* -# CM4 is Off:
+* -# CM4 is Off and disabled:
* call Cy_SysDisableCM4(). Note: In this state Debug mode is not * supported. * . -* -# Flash write cannot be performed in ULP (core voltage 0.9V) mode. +* -# Flash Write cannot be performed in Ultra Low Power (core voltage 0.9V) mode. * -# Interrupts must be enabled on both active cores. Do not enter a critical * section during flash operation. * -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe @@ -115,8 +115,7 @@ * sequence used. * * For API sequence Cy_Flash_StartEraseRow() + Cy_Flash_StartProgram() there are -* four block-out regions during which the read is blocked using the software -* driver (PDL). See Figure 1. +* four block-out regions during which Read is blocked. See Figure 1. * *
*
VersionChangesReason for Change
1.10.2Fix driver header path.Folder structure changed.
1.10.1Added header guard CY_IP_MXEFUSE.To enable the PDL compilation with wounded out IP blocks.
@@ -150,7 +149,7 @@ *
* * -* This allows both cores to execute an application for about 80% of Flash Write +* This allows both cores to execute for about 80% of Flash Write * operation - see Figure 1. * This capability is important for communication protocols that rely on fast * response. @@ -167,9 +166,9 @@ * The core that performs read/execute is blocked identically to the previous * scenario - see Figure 1. * -* This allows the core that initiates Cy_Flash_StartWrite() to execute an -* application for about 20% of the Flash Write operation. The other core executes -* the application for about 80% of the Flash Write operation. +* This allows the core that initiates Cy_Flash_StartWrite() to execute for about +* 20% of Flash Write operation. The other core executes for about 80% of Flash +* Write operation. * * Some constraints must be planned for in the Partially Blocking mode which are * described in detail below. @@ -190,7 +189,7 @@ * call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)". * Note: If desired user may put CM4 core in Deep Sleep any time * after calling Cy_SysEnableCM4(). -* -# CM4 is Off:
+* -# CM4 is Off and disabled:
* call Cy_SysDisableCM4(). Note: In this state Debug mode is not * supported. * . @@ -198,8 +197,8 @@ * read of any bus master: CM0+, CM4, DMA, Crypto, etc.) * -# Do not write to and read/execute from the same flash sector at the same * time. This is true for all sectors. -* -# Writing rules in User Flash (this restriction is applicable just for the -* CY8C6xx6, CY8C6xx7 devices): +* -# Writing rules in application flash (this restriction is applicable just +* for CY8C6xx6, CY8C6xx7 devices): * -# Any bus master can read/execute from UFLASH S0 and/or S1, during * flash write to UFLASH S2 or S3. * -# Any bus master can read/execute from UFLASH S2 and/or S3, during @@ -209,16 +208,13 @@ * code for CM4 in either S0 or S1. CM0+ code resides in S0. Write data * to S2 and S3 sections. * . -* -# Flash write cannot be performed in ULP mode (core voltage 0.9V). +* -# Flash Write cannot be performed in Ultra Low Power mode (core voltage 0.9V). * -# Interrupts must be enabled on both active cores. Do not enter a critical * section during flash operation. * -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe * interrupts (IPC interrupts 3 and 4) have the highest priority, or at * least that pipe interrupts are not interrupted or in a pending state * for more than 700 µs. -* -# User must guarantee that during flash write operation no flash read -* operations are performed by bus masters other than CM0+ and CM4 -* (DMA and Crypto). * -# If you do not use the default startup, perform the following steps * before any flash write/erase operations: * \snippet flash/snippet/main.c Flash Initialization @@ -260,6 +256,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h index c51985c421..b4ba383adf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_prot.h -* \version 1.30.1 +* \version 1.30.2 * * \brief * Provides an API declaration of the Protection Unit driver * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -390,6 +390,12 @@ *
VersionChangesReason for Change
3.30.4Improved documentation.User experience enhancement.
3.30.3Updated documentation to limit devices with the restrictions. Improved calculation of the CY_FLASH_DELAY_CORRECTIVE macro.User experience enhancement.
* * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_rtc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_rtc.h index 36cac15f57..f8b90ae8a7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_rtc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_rtc.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_rtc.h -* \version 2.20.1 +* \version 2.30 * * This file provides constants and parameter values for the APIs for the * Real-Time Clock (RTC). * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -228,6 +228,18 @@ *
VersionChangesReason for Change
1.30.2Clarified the description of the next API functions: \ref Cy_Prot_ConfigPpuProgMasterAtt,\n +* \ref Cy_Prot_ConfigPpuProgSlaveAtt, \ref Cy_Prot_ConfigPpuFixedMasterAtt, \ref Cy_Prot_ConfigPpuFixedSlaveAtt.API enhancement based on usability feedback.
1.30.1Snippet updated.Old snippet outdated.
* * +* +* +* +* +* * * * @@ -326,7 +338,7 @@ extern "C" { #define CY_RTC_DRV_VERSION_MAJOR 2 /** Driver minor version */ -#define CY_RTC_DRV_VERSION_MINOR 20 +#define CY_RTC_DRV_VERSION_MINOR 30 /** \} group_rtc_macros */ /******************************************************************************* @@ -548,8 +560,6 @@ cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, * \{ */ cy_en_rtc_status_t Cy_RTC_EnableDstTime(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate); -cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst); -bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate); /** \} group_rtc_dst_functions */ /** @@ -594,6 +604,9 @@ __STATIC_INLINE bool Cy_RTC_IsExternalResetOccurred(void); __STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t dateBcd); __STATIC_INLINE void Cy_RTC_SyncToRtcAhbAlarm(uint32_t alarmTimeBcd, uint32_t alarmDateBcd, cy_en_rtc_alarm_t alarmIndex); + +cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst); +bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate); /** \} group_rtc_low_level_functions */ /** \} group_rtc_functions */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h index c109bac045..606d8204c5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif.h -* \version 1.40.1 +* \version 1.50 * * Provides an API declaration of the Cypress SMIF driver. * @@ -214,6 +214,15 @@ *
VersionChangesReason for Change
2.30 +* * Corrected the Cy_RTC_GetDstStatus() and Cy_RTC_SetNextDstTime() +* documentation. +* * Fixed the Cy_RTC_GetDstStatus() behaviour in the 'an hour before/after the DST stop event' period. +* +* * Collateral Review: user experience enhancement. +* * Bug fix. +*
2.20.1Modified header guard CY_IP_MXS40SRSS_RTC.To enable the PDL compilation with wounded out IP blocks.
* * +* +* +* +* +* * * * @@ -450,7 +459,7 @@ extern "C" { #define CY_SMIF_DRV_VERSION_MAJOR 1 /** The driver minor version */ -#define CY_SMIF_DRV_VERSION_MINOR 40 +#define CY_SMIF_DRV_VERSION_MINOR 50 /** One microsecond timeout for Cy_SMIF_TimeoutRun() */ #define CY_SMIF_WAIT_1_UNIT (1U) @@ -679,6 +688,8 @@ typedef enum CY_SMIF_NO_QE_BIT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x03U, CY_SMIF_BAD_PARAM = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x04U, /**< The SMIF API received the wrong parameter */ CY_SMIF_NO_SFDP_SUPPORT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x05U, /**< The external memory does not support SFDP (JESD216B). */ + CY_SMIF_NOT_HYBRID_MEM = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x06U, /**< The external memory is not hybrid */ + CY_SMIF_SFDP_CORRUPTED_TABLE = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x07U, /**< The SFDP table is corrupted */ /** Failed to initialize the slave select 0 external memory by auto detection (SFDP). */ CY_SMIF_SFDP_SS0_FAILED = CY_SMIF_ID |CY_PDL_STATUS_ERROR | ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS0_POS), diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h index b4f1d2760d..69341a275f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif_memslot.h -* \version 1.40.1 +* \version 1.50 * * \brief * This file provides the constants and parameter values for the memory-level @@ -201,11 +201,24 @@ extern "C" { #define CY_SMIF_SFDP_BFPT_BYTE_23 (0x23U) /**< The byte 0x23 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_BYTE_28 (0x28U) /**< The byte 0x28 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_BYTE_3A (0x3AU) /**< The byte 0x3A of the JEDEC Basic Flash Parameter Table */ +#define CY_SMIF_SFDP_BFPT_BYTE_3C (0x3CU) /**< The byte 0x3C of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_ERASE_BYTE (36U) /**< The byte 36 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_JEDEC_BFPT_10TH_DWORD (9U) /**< Offset to JEDEC Basic Flash Parameter Table: 10th DWORD */ #define CY_SMIF_JEDEC_BFPT_11TH_DWORD (10U) /**< Offset to JEDEC Basic Flash Parameter Table: 11th DWORD */ + +#define CY_SMIF_SFDP_SECTOR_MAP_CMD_OFFSET (1UL) /**< The offset for the detection command instruction in the Sector Map command descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_ADDR_CODE_OFFSET (2UL) /**< The offset for the detection command address length in the Sector Map command descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_REG_MSK_OFFSET (3UL) /**< The offset for the read data mask in the Sector Map command descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_REG_ADDR_OFFSET (4UL) /**< The offset for the detection command address in the Sector Map command descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_REGION_COUNT_OFFSET (2UL) /**< The offset for the regions count in the Sector Map descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_CONFIG_ID_OFFSET (2UL) /**< The offset for the configuration ID in the Sector Map descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_SUPPORTED_ET_MASK (0xFU) /**< The mask for the supported erase type code in the Sector Map descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Msk (0xC0UL) /**< The mask for the configuration detection command address bytes in the Sector Map descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Pos (6UL) /**< The position of the configuration detection command address bytes in the Sector Map descriptor */ + + /* ---------------------------- 1st DWORD ---------------------------- */ #define CY_SMIF_SFDP_FAST_READ_1_1_4_Pos (6UL) /**< The SFDP 1-1-4 fast read support (Bit 6) */ #define CY_SMIF_SFDP_FAST_READ_1_1_4_Msk (0x40UL) /**< The SFDP 1-1-4 fast read support (Bitfield-Mask: 0x01) */ @@ -268,6 +281,14 @@ extern "C" { #define CY_SMIF_SFDP_QE_REQUIREMENTS_Pos (4UL) /**< The SFDP quad enable requirements field (Bit 4) */ #define CY_SMIF_SFDP_QE_REQUIREMENTS_Msk (0x70UL) /**< The SFDP quad enable requirements field (Bitfield-Mask: 0x07) */ + +/* ---------------------------- 16th DWORD --------------------------- */ +#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7 (1U) /**< Issue 0xB7 instruction */ +#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_WR_EN_B7 (2U) /**< Issue write enable instruction followed with 0xB7 */ +#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_ALWAYS_4_BYTE (0x40U) /**< Memory always operates in 4-byte mode */ +#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7_CMD (0xB7U) /**< The instruction required to enter 4-byte addressing mode */ + + /** \cond INTERNAL */ /******************************************************************************* * These are legacy constants and API. They are left here just @@ -327,6 +348,16 @@ typedef struct cy_en_smif_txfr_width_t dataWidth; /**< The width of the data transfer */ } cy_stc_smif_mem_cmd_t; +/** This structure specifies data used for memory with hybrid sectors */ +typedef struct +{ + uint32_t regionAddress; /**< This specifies the address where a region starts */ + uint32_t sectorsCount; /**< This specifies the number of sectors in the region */ + uint32_t eraseCmd; /**< This specifies the region specific erase instruction*/ + uint32_t eraseSize; /**< This specifies the size of one sector */ + uint32_t eraseTime; /**< Max time for sector erase type 1 cycle time in ms*/ +} cy_stc_smif_hybrid_region_info_t; + /** * @@ -337,31 +368,33 @@ typedef struct */ typedef struct { - uint32_t numOfAddrBytes; /**< This specifies the number of address bytes used by the - * memory slave device, valid values 1-4 */ - uint32_t memSize; /**< The memory size: For densities of 2 gigabits or less - the size in bytes; - * For densities 4 gigabits and above - bit-31 is set to 1b to define that - * this memory is 4 gigabits and above; and other 30:0 bits define N where - * the density is computed as 2^N bytes. - * For example, 0x80000021 corresponds to 2^30 = 1 gigabyte. - */ - cy_stc_smif_mem_cmd_t* readCmd; /**< This specifies the Read command */ - cy_stc_smif_mem_cmd_t* writeEnCmd; /**< This specifies the Write Enable command */ - cy_stc_smif_mem_cmd_t* writeDisCmd; /**< This specifies the Write Disable command */ - cy_stc_smif_mem_cmd_t* eraseCmd; /**< This specifies the Erase command */ - uint32_t eraseSize; /**< This specifies the sector size of each Erase */ - cy_stc_smif_mem_cmd_t* chipEraseCmd; /**< This specifies the Chip Erase command */ - cy_stc_smif_mem_cmd_t* programCmd; /**< This specifies the Program command */ - uint32_t programSize; /**< This specifies the page size for programming */ - cy_stc_smif_mem_cmd_t* readStsRegWipCmd; /**< This specifies the command to read the WIP-containing status register */ - cy_stc_smif_mem_cmd_t* readStsRegQeCmd; /**< This specifies the command to read the QE-containing status register */ - cy_stc_smif_mem_cmd_t* writeStsRegQeCmd; /**< This specifies the command to write into the QE-containing status register */ - cy_stc_smif_mem_cmd_t* readSfdpCmd; /**< This specifies the read SFDP command */ - uint32_t stsRegBusyMask; /**< The Busy mask for the status registers */ - uint32_t stsRegQuadEnableMask; /**< The QE mask for the status registers */ - uint32_t eraseTime; /**< Max time for erase type 1 cycle time in ms */ - uint32_t chipEraseTime; /**< Max time for chip erase cycle time in ms */ - uint32_t programTime; /**< Max time for page program cycle time in us */ + uint32_t numOfAddrBytes; /**< This specifies the number of address bytes used by the + * memory slave device, valid values 1-4 */ + uint32_t memSize; /**< The memory size: For densities of 2 gigabits or less - the size in bytes; + * For densities 4 gigabits and above - bit-31 is set to 1b to define that + * this memory is 4 gigabits and above; and other 30:0 bits define N where + * the density is computed as 2^N bytes. + * For example, 0x80000021 corresponds to 2^30 = 1 gigabyte. + */ + cy_stc_smif_mem_cmd_t* readCmd; /**< This specifies the Read command */ + cy_stc_smif_mem_cmd_t* writeEnCmd; /**< This specifies the Write Enable command */ + cy_stc_smif_mem_cmd_t* writeDisCmd; /**< This specifies the Write Disable command */ + cy_stc_smif_mem_cmd_t* eraseCmd; /**< This specifies the Erase command */ + uint32_t eraseSize; /**< This specifies the sector size of each Erase */ + cy_stc_smif_mem_cmd_t* chipEraseCmd; /**< This specifies the Chip Erase command */ + cy_stc_smif_mem_cmd_t* programCmd; /**< This specifies the Program command */ + uint32_t programSize; /**< This specifies the page size for programming */ + cy_stc_smif_mem_cmd_t* readStsRegWipCmd; /**< This specifies the command to read the WIP-containing status register */ + cy_stc_smif_mem_cmd_t* readStsRegQeCmd; /**< This specifies the command to read the QE-containing status register */ + cy_stc_smif_mem_cmd_t* writeStsRegQeCmd; /**< This specifies the command to write into the QE-containing status register */ + cy_stc_smif_mem_cmd_t* readSfdpCmd; /**< This specifies the read SFDP command */ + uint32_t stsRegBusyMask; /**< The Busy mask for the status registers */ + uint32_t stsRegQuadEnableMask; /**< The QE mask for the status registers */ + uint32_t eraseTime; /**< Max time for erase type 1 cycle time in ms */ + uint32_t chipEraseTime; /**< Max time for chip erase cycle time in ms */ + uint32_t programTime; /**< Max time for page program cycle time in us */ + uint32_t hybridRegionCount; /**< This specifies the number of regions for memory with hybrid sectors */ + cy_stc_smif_hybrid_region_info_t** hybridRegionInfo; /**< This specifies data for memory with hybrid sectors */ } cy_stc_smif_mem_device_cfg_t; @@ -490,7 +523,8 @@ cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_conf cy_stc_smif_context_t const *context); cy_en_smif_status_t Cy_SMIF_MemEraseChip(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, cy_stc_smif_context_t const *context); - +cy_en_smif_status_t Cy_SMIF_MemLocateHybridRegion(cy_stc_smif_mem_config_t const *memDevice, + cy_stc_smif_hybrid_region_info_t** regionInfo, uint32_t address); /** \} group_smif_mem_slot_functions */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h index f49264089b..9123dbccfb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_sysclk.h -* \version 1.50 +* \version 1.60 * * Provides an API declaration of the sysclk driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -43,8 +43,8 @@ * clock system. * * The PDL defines clock system capabilities in:\n -* devices\//include\_config.h. (E.g. -* devices/psoc6/include/psoc6_01_config.h). +* devices/include/\_config.h. (E.g. +* devices/include/psoc6_01_config.h). * User-configurable clock speeds are defined in the file system_.h. * * As an illustration of the clocking system, the following diagram shows the @@ -104,6 +104,15 @@ *
VersionChangesReason for Change
1.50Added a new function: \ref Cy_SMIF_MemLocateHybridRegion.\n +* Added a new structure \ref cy_stc_smif_hybrid_region_info_t.\n +* Updated the \ref Cy_SMIF_MemEraseSector and \ref Cy_SMIF_MemCmdSectorErase functions.\n +* Updated the \ref Cy_SMIF_MemSfdpDetect function. \n +* Updated the \ref cy_stc_smif_mem_device_cfg_t structure.Support for memories with hybrid regions.
1.40.1The \ref Cy_SMIF_MemInit is changed. Corrected a false assertion during initialization in SFDP mode.
* * +* +* +* +* +* * * * @@ -277,7 +286,7 @@ * - IMO: 8 MHz Internal Main Oscillator (Default) * - EXTCLK: External clock (signal brought in through dedicated pins) * - ECO: External Crystal Oscillator (requires external crystal on dedicated pins) -* - ALTHF: Select on-chip signals (e.g. BLE ECO) +* - ALTHF: Select on-chip signals (e.g. \ref group_ble_clk) * - Digital Signal (DSI): Digital signal from a UDB source * * Some clock paths such as path 0 and path 1 have additional resources @@ -559,6 +568,13 @@ * ![](sysclk_slow.png) * * \defgroup group_sysclk_clk_slow_funcs Functions +* \} + * \defgroup group_sysclk_alt_hf Alternative High-Frequency Clock +* \{ +* In the BLE-enabled PSoC6 devices, the \ref group_ble_clk clock is +* connected to the system Alternative High-Frequency Clock input. +* +* \defgroup group_sysclk_alt_hf_funcs Functions * \} * \defgroup group_sysclk_clk_lf Low-Frequency Clock * \{ @@ -642,7 +658,7 @@ extern "C" { /** Driver major version */ #define CY_SYSCLK_DRV_VERSION_MAJOR 1 /** Driver minor version */ -#define CY_SYSCLK_DRV_VERSION_MINOR 40 +#define CY_SYSCLK_DRV_VERSION_MINOR 60 /** Sysclk driver identifier */ #define CY_SYSCLK_ID CY_PDL_DRV_ID(0x12U) @@ -685,6 +701,7 @@ typedef enum * \{ */ void Cy_SysClk_ExtClkSetFrequency(uint32_t freq); +uint32_t Cy_SysClk_ExtClkGetFrequency(void); /** \} group_sysclk_ext_funcs */ /* ========================================================================== */ @@ -719,6 +736,7 @@ void Cy_SysClk_ExtClkSetFrequency(uint32_t freq); */ cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint32_t esr, uint32_t driveLevel); cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus); +uint32_t Cy_SysClk_EcoGetFrequency(void); __STATIC_INLINE void Cy_SysClk_EcoDisable(void); __STATIC_INLINE uint32_t Cy_SysClk_EcoGetStatus(void); @@ -802,6 +820,8 @@ typedef enum */ cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source); cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath); +uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath); +uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath); /** \} group_sysclk_path_src_funcs */ @@ -1121,9 +1141,11 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath) * \{ */ __STATIC_INLINE void Cy_SysClk_IloEnable(void); +__STATIC_INLINE bool Cy_SysClk_IloIsEnabled(void); __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void); __STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on); + /******************************************************************************* * Function Name: Cy_SysClk_IloEnable ****************************************************************************//** @@ -1142,6 +1164,24 @@ __STATIC_INLINE void Cy_SysClk_IloEnable(void) } +/******************************************************************************* +* Function Name: Cy_SysClk_IloIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of the ILO. +* +* \return Boolean status of ILO: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_IloIsEnabled(void) +{ + return (_FLD2BOOL(SRSS_CLK_ILO_CONFIG_ENABLE, SRSS_CLK_ILO_CONFIG)); +} + + /******************************************************************************* * Function Name: Cy_SysClk_IloDisable ****************************************************************************//** @@ -1204,6 +1244,7 @@ __STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on) * \{ */ __STATIC_INLINE void Cy_SysClk_PiloEnable(void); +__STATIC_INLINE bool Cy_SysClk_PiloIsEnabled(void); __STATIC_INLINE void Cy_SysClk_PiloDisable(void); __STATIC_INLINE void Cy_SysClk_PiloSetTrim(uint32_t trimVal); __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void); @@ -1223,7 +1264,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void); *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_PiloEnable(void) { - SRSS_CLK_PILO_CONFIG |= _VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_EN, 1U); /* 1 = enable */ + SRSS_CLK_PILO_CONFIG |= SRSS_CLK_PILO_CONFIG_PILO_EN_Msk; /* 1 = enable */ Cy_SysLib_Delay(1U/*msec*/); /* release the reset and enable clock output */ SRSS_CLK_PILO_CONFIG |= SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk | @@ -1231,6 +1272,24 @@ __STATIC_INLINE void Cy_SysClk_PiloEnable(void) } +/******************************************************************************* +* Function Name: Cy_SysClk_PiloIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of the PILO. +* +* \return Boolean status of PILO: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_PiloIsEnabled(void) +{ + return (_FLD2BOOL(SRSS_CLK_PILO_CONFIG_PILO_CLK_EN, SRSS_CLK_PILO_CONFIG)); +} + + /******************************************************************************* * Function Name: Cy_SysClk_PiloDisable ****************************************************************************//** @@ -1275,7 +1334,7 @@ __STATIC_INLINE void Cy_SysClk_PiloSetTrim(uint32_t trimVal) * Reports the current PILO trim bits value. * * \funcusage -* Refer to the Cy_SysClk_PiloSetTrim() function usage. +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloSetTrim * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void) @@ -1285,6 +1344,53 @@ __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void) /** \} group_sysclk_pilo_funcs */ +/* ========================================================================== */ +/* ========================== ALTHF SECTION =========================== */ +/* ========================================================================== */ +/** +* \addtogroup group_sysclk_alt_hf_funcs +* \{ +*/ +__STATIC_INLINE uint32_t Cy_SysClk_AltHfGetFrequency(void); + + +/******************************************************************************* +* Function Name: Cy_SysClk_AltHfGetFrequency +****************************************************************************//** +* +* Reports the frequency of the Alternative High-Frequency Clock +* +* \funcusage +* \snippet bleclk/snippet/main.c BLE ECO clock API: Cy_BLE_EcoConfigure() +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_AltHfGetFrequency(void) +{ + #if defined(CY_IP_MXBLESS) + return (cy_BleEcoClockFreqHz); + #else /* CY_IP_MXBLESS */ + return (0UL); + #endif /* CY_IP_MXBLESS */ +} +/** \} group_sysclk_alt_hf_funcs */ + + +/* ========================================================================== */ +/* ========================== ALTLF SECTION =========================== */ +/* ========================================================================== */ +/** \cond For future usage */ +__STATIC_INLINE uint32_t Cy_SysClk_AltLfGetFrequency(void) +{ + return (0UL); +} + +__STATIC_INLINE bool Cy_SysClk_AltLfIsEnabled(void) +{ + return (false); +} +/** \endcond */ + + /* ========================================================================== */ /* ==================== CLOCK MEASUREMENT SECTION ===================== */ /* ========================================================================== */ @@ -1845,6 +1951,7 @@ typedef struct * \{ */ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf); +__STATIC_INLINE bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf); __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf); __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source); __STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf); @@ -1879,6 +1986,31 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf) } +/******************************************************************************* +* Function Name: Cy_SysClk_ClkHfIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of clkHf. +* +* \param clkHf Selects which clkHf to check. +* +* \return Boolean status of clkHf: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf) +{ + bool retVal = false; + if (clkHf < CY_SRSS_NUM_HFROOT) + { + retVal = _FLD2BOOL(SRSS_CLK_ROOT_SELECT_ENABLE, SRSS_CLK_ROOT_SELECT[clkHf]); + } + return (retVal); +} + + /******************************************************************************* * Function Name: Cy_SysClk_ClkHfDisable ****************************************************************************//** @@ -2853,7 +2985,9 @@ __STATIC_INLINE cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void); __STATIC_INLINE void Cy_SysClk_ClkTimerSetDivider(uint8_t divider); __STATIC_INLINE uint8_t Cy_SysClk_ClkTimerGetDivider(void); __STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void); +__STATIC_INLINE bool Cy_SysClk_ClkTimerIsEnabled(void); __STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void); + uint32_t Cy_SysClk_ClkTimerGetFrequency(void); /******************************************************************************* * Function Name: Cy_SysClk_ClkTimerSetSource @@ -2953,6 +3087,24 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void) } +/******************************************************************************* +* Function Name: Cy_SysClk_ClkTimerIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of the Timer. +* +* \return Boolean status of Timer: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_ClkTimerIsEnabled(void) +{ + return (_FLD2BOOL(SRSS_CLK_TIMER_CTL_ENABLE, SRSS_CLK_TIMER_CTL)); +} + + /******************************************************************************* * Function Name: Cy_SysClk_ClkTimerDisable ****************************************************************************//** @@ -2984,22 +3136,22 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void) */ typedef enum { - CY_SYSCLK_PUMP_IN_CLKPATH0, /**< Pump clock input is clock path 0 */ - CY_SYSCLK_PUMP_IN_CLKPATH1, /**< Pump clock input is clock path 1 */ - CY_SYSCLK_PUMP_IN_CLKPATH2, /**< Pump clock input is clock path 2 */ - CY_SYSCLK_PUMP_IN_CLKPATH3, /**< Pump clock input is clock path 3 */ - CY_SYSCLK_PUMP_IN_CLKPATH4, /**< Pump clock input is clock path 4 */ - CY_SYSCLK_PUMP_IN_CLKPATH5, /**< Pump clock input is clock path 5 */ - CY_SYSCLK_PUMP_IN_CLKPATH6, /**< Pump clock input is clock path 6 */ - CY_SYSCLK_PUMP_IN_CLKPATH7, /**< Pump clock input is clock path 7 */ - CY_SYSCLK_PUMP_IN_CLKPATH8, /**< Pump clock input is clock path 8 */ - CY_SYSCLK_PUMP_IN_CLKPATH9, /**< Pump clock input is clock path 9 */ - CY_SYSCLK_PUMP_IN_CLKPATH10, /**< Pump clock input is clock path 10 */ - CY_SYSCLK_PUMP_IN_CLKPATH11, /**< Pump clock input is clock path 11 */ - CY_SYSCLK_PUMP_IN_CLKPATH12, /**< Pump clock input is clock path 12 */ - CY_SYSCLK_PUMP_IN_CLKPATH13, /**< Pump clock input is clock path 13 */ - CY_SYSCLK_PUMP_IN_CLKPATH14, /**< Pump clock input is clock path 14 */ - CY_SYSCLK_PUMP_IN_CLKPATH15 /**< Pump clock input is clock path 15 */ + CY_SYSCLK_PUMP_IN_CLKPATH0 = 0UL, /**< Pump clock input is clock path 0 */ + CY_SYSCLK_PUMP_IN_CLKPATH1 = 1UL, /**< Pump clock input is clock path 1 */ + CY_SYSCLK_PUMP_IN_CLKPATH2 = 2UL, /**< Pump clock input is clock path 2 */ + CY_SYSCLK_PUMP_IN_CLKPATH3 = 3UL, /**< Pump clock input is clock path 3 */ + CY_SYSCLK_PUMP_IN_CLKPATH4 = 4UL, /**< Pump clock input is clock path 4 */ + CY_SYSCLK_PUMP_IN_CLKPATH5 = 5UL, /**< Pump clock input is clock path 5 */ + CY_SYSCLK_PUMP_IN_CLKPATH6 = 6UL, /**< Pump clock input is clock path 6 */ + CY_SYSCLK_PUMP_IN_CLKPATH7 = 7UL, /**< Pump clock input is clock path 7 */ + CY_SYSCLK_PUMP_IN_CLKPATH8 = 8UL, /**< Pump clock input is clock path 8 */ + CY_SYSCLK_PUMP_IN_CLKPATH9 = 9UL, /**< Pump clock input is clock path 9 */ + CY_SYSCLK_PUMP_IN_CLKPATH10 = 10UL, /**< Pump clock input is clock path 10 */ + CY_SYSCLK_PUMP_IN_CLKPATH11 = 11UL, /**< Pump clock input is clock path 11 */ + CY_SYSCLK_PUMP_IN_CLKPATH12 = 12UL, /**< Pump clock input is clock path 12 */ + CY_SYSCLK_PUMP_IN_CLKPATH13 = 13UL, /**< Pump clock input is clock path 13 */ + CY_SYSCLK_PUMP_IN_CLKPATH14 = 14UL, /**< Pump clock input is clock path 14 */ + CY_SYSCLK_PUMP_IN_CLKPATH15 = 15UL /**< Pump clock input is clock path 15 */ } cy_en_clkpump_in_sources_t; @@ -3035,7 +3187,9 @@ __STATIC_INLINE cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void); __STATIC_INLINE void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider); __STATIC_INLINE cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void); __STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void); +__STATIC_INLINE bool Cy_SysClk_ClkPumpIsEnabled(void); __STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void); +__STATIC_INLINE uint32_t Cy_SysClk_ClkPumpGetFrequency(void); /******************************************************************************* @@ -3136,6 +3290,24 @@ __STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void) } +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPumpIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of the ClkPump. +* +* \return Boolean status of ClkPump: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_ClkPumpIsEnabled(void) +{ + return (_FLD2BOOL(SRSS_CLK_SELECT_PUMP_ENABLE, SRSS_CLK_SELECT)); +} + + /******************************************************************************* * Function Name: Cy_SysClk_ClkPumpDisable ****************************************************************************//** @@ -3150,6 +3322,26 @@ __STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void) { SRSS_CLK_SELECT &= ~SRSS_CLK_SELECT_PUMP_ENABLE_Msk; } + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPumpGetFrequency +****************************************************************************//** +* +* Reports the frequency of the pump clock (clk_pump). +* \note If the the pump clock is not enabled - a zero frequency is reported. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpEnable +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_ClkPumpGetFrequency(void) +{ + /* Divide the input frequency down and return the result */ + return (Cy_SysClk_ClkPumpIsEnabled() ? + (Cy_SysClk_ClkPathGetFrequency((uint32_t)Cy_SysClk_ClkPumpGetSource()) / + (1UL << (uint32_t)Cy_SysClk_ClkPumpGetDivider())) : 0UL); +} /** \} group_sysclk_clk_pump_funcs */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h index 0d7777895b..2cc53537a0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib.h -* \version 2.50 +* \version 2.50.1 * * Provides an API declaration of the SysLib driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -139,6 +139,11 @@ *
VersionChangesReason for Change
1.60Added the following functions: \ref Cy_SysClk_ExtClkGetFrequency, \ref Cy_SysClk_EcoGetFrequency,\n +* \ref Cy_SysClk_ClkPathMuxGetFrequency, \ref Cy_SysClk_ClkPathGetFrequency, \ref Cy_SysClk_IloIsEnabled.\n +* \ref Cy_SysClk_PiloIsEnabled, \ref Cy_SysClk_AltHfGetFrequency, \ref Cy_SysClk_ClkHfIsEnabled,\n +* \ref Cy_SysClk_ClkTimerIsEnabled, \ref Cy_SysClk_ClkTimerGetFrequency, \ref Cy_SysClk_ClkPumpIsEnabled and\n +* \ref Cy_SysClk_ClkPumpGetFrequency.API enhancement.
1.50\ref Cy_SysClk_ClkHfGetFrequency is updated to reuse the \ref cy_BleEcoClockFreqHz global system variable.API enhancement.
* * +* +* +* +* * *
VersionChangesReason for Change
2.50.1Used the core library defines for the message codes forming. +* Improve PDL code base.
2.50Moved following macros to the core library: * CY_LO8,CY_HI8,CY_LO16,CY_HI16,CY_SWAP_ENDIAN16,CY_SWAP_ENDIAN32, @@ -250,6 +255,7 @@ #include #include #include "cy_utils.h" +#include "cy_result.h" #include "cy_device.h" #include "cy_device_headers.h" @@ -290,13 +296,13 @@ extern "C" { * \{ * Function status type codes */ -#define CY_PDL_STATUS_CODE_Pos (0U) /**< The module status code position in the status code */ -#define CY_PDL_STATUS_TYPE_Pos (16U) /**< The status type position in the status code */ -#define CY_PDL_MODULE_ID_Pos (18U) /**< The software module ID position in the status code */ -#define CY_PDL_STATUS_INFO (0UL << CY_PDL_STATUS_TYPE_Pos) /**< The information status type */ -#define CY_PDL_STATUS_WARNING (1UL << CY_PDL_STATUS_TYPE_Pos) /**< The warning status type */ -#define CY_PDL_STATUS_ERROR (2UL << CY_PDL_STATUS_TYPE_Pos) /**< The error status type */ -#define CY_PDL_MODULE_ID_Msk (0x3FFFU) /**< The software module ID mask */ +#define CY_PDL_STATUS_CODE_Pos (CY_RSLT_CODE_POSITION) /**< The module status code position in the status code */ +#define CY_PDL_STATUS_TYPE_Pos (CY_RSLT_TYPE_POSITION) /**< The status type position in the status code */ +#define CY_PDL_MODULE_ID_Pos (CY_RSLT_MODULE_POSITION) /**< The software module ID position in the status code */ +#define CY_PDL_STATUS_INFO ((uint32_t)CY_RSLT_TYPE_INFO << CY_PDL_STATUS_TYPE_Pos) /**< The information status type */ +#define CY_PDL_STATUS_WARNING ((uint32_t)CY_RSLT_TYPE_WARNING << CY_PDL_STATUS_TYPE_Pos) /**< The warning status type */ +#define CY_PDL_STATUS_ERROR ((uint32_t)CY_RSLT_TYPE_ERROR << CY_PDL_STATUS_TYPE_Pos) /**< The error status type */ +#define CY_PDL_MODULE_ID_Msk (CY_RSLT_MODULE_MASK) /**< The software module ID mask */ /** Get the software PDL module ID */ #define CY_PDL_DRV_ID(id) ((uint32_t)((uint32_t)((id) & CY_PDL_MODULE_ID_Msk) << CY_PDL_MODULE_ID_Pos)) #define CY_SYSLIB_ID CY_PDL_DRV_ID(0x11U) /**< SYSLIB PDL ID */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h index 85cd16688b..6d071770b2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syspm.h -* \version 4.50 +* \version 5.0 * * Provides the function definitions for the power management API. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -724,6 +724,23 @@ * * * +* +* +* +* +* * * *
VersionChangesReason for Change
5.0 +* Updated the internal IsVoltageChangePossible() function +* (\ref Cy_SysPm_LdoSetVoltage(), \ref Cy_SysPm_BuckEnable(), +* \ref Cy_SysPm_BuckSetVoltage1(), \ref Cy_SysPm_SystemEnterUlp() +* and \ref Cy_SysPm_SystemEnterLp() functions are affected). +* For all the devices except CY8C6xx6 and CY8C6xx7 added the check if +* modifying the RAM trim register is allowed. +* +* Protecting the system from a possible CPU hard-fault cause. If you +* are using PC > 0 in your project and you want to switch the power +* modes (LP<->ULP), you need to unprotect the CPUSS_TRIM_RAM_CTL and +* CPUSS_TRIM_ROM_CTL registers and can use a programmable PPU for that. +*
4.50Updated the \ref Cy_SysPm_CpuEnterDeepSleep() function. @@ -1239,10 +1256,10 @@ extern "C" { */ /** Driver major version */ -#define CY_SYSPM_DRV_VERSION_MAJOR 4 +#define CY_SYSPM_DRV_VERSION_MAJOR 5 /** Driver minor version */ -#define CY_SYSPM_DRV_VERSION_MINOR 50 +#define CY_SYSPM_DRV_VERSION_MINOR 0 /** SysPm driver identifier */ #define CY_SYSPM_ID (CY_PDL_DRV_ID(0x10U)) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S index 16e71def22..52069c4856 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S @@ -1,11 +1,11 @@ ;------------------------------------------------------------------------------- ; \file cy_syslib_mdk.s -; \version 2.50 +; \version 2.50.1 ; ; \brief Assembly routines for ARMCC. ; ;------------------------------------------------------------------------------- -; Copyright 2016-2019 Cypress Semiconductor Corporation +; Copyright 2016-2020 Cypress Semiconductor Corporation ; SPDX-License-Identifier: Apache-2.0 ; ; Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S index 68249d7077..62b526c401 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib_a_clang.S -* \version 2.50 +* \version 2.50.1 * * \brief Assembly routines for Apple Clang. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S index 1d6e16eba2..9af4ce1a61 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib_gcc.S -* \version 2.50 +* \version 2.50.1 * * \brief Assembly routines for GNU GCC. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S index 8847749100..ff7f89d5ac 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib_iar.s -* \version 2.50 +* \version 2.50.1 * * \brief Assembly routines for IAR Embedded Workbench IDE. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c index 8f92bd1df2..b9aefd8089 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_ble_clk.c -* \version 3.30 +* \version 3.40 * * \brief * This driver provides the source code for API BLE ECO clock. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -235,8 +235,7 @@ cy_en_ble_eco_status_t Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq, cy_en_ble_ Cy_SysPm_IoUnfreeze(); } - if(((BLE_BLESS_MT_CFG & BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk) != 0u) && - ((BLE_BLESS_MT_STATUS & BLE_BLESS_MT_STATUS_BLESS_STATE_Msk) != 0u)) + if(Cy_BLE_EcoIsEnabled()) { status = CY_BLE_ECO_ALREADY_STARTED; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_canfd.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_canfd.c index 4a8098fae6..1fd4028569 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_canfd.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_canfd.c @@ -1,13 +1,13 @@ /******************************************************************************* * \file cy_canfd.c -* \version 1.0.1 +* \version 1.10 * * \brief * Provides an API implementation of the CAN FD driver. * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -269,11 +269,8 @@ cy_en_canfd_status_t Cy_CANFD_Init(CANFD_Type *base, uint32_t chan, (NULL != config->bitrate) && (NULL != config->globalFilterConfig) && (NULL != config->rxFIFO0Config) && - (NULL != config->rxFIFO1Config) && - ((0U != config->sidFilterConfig->numberOfSIDFilters) && - (NULL != config->sidFilterConfig->sidFilter)) && - ((0U != config->extidFilterConfig->numberOfEXTIDFilters) && - (NULL != config->extidFilterConfig->extidFilter)) ) + (NULL != config->rxFIFO1Config) + ) { CY_ASSERT_L2(CY_CANFD_IS_CHANNEL_VALID(chan)); CY_ASSERT_L2(CY_CANFD_IS_NOM_PRESCALER_VALID(config->bitrate->prescaler)); @@ -318,25 +315,42 @@ cy_en_canfd_status_t Cy_CANFD_Init(CANFD_Type *base, uint32_t chan, context->messageRAMaddress = config->messageRAMaddress; context->messageRAMsize = config->messageRAMsize; - /* Configure a standard ID filter: - * The number of SID filters and Start address (word) of the SID filter - * configuration in Message RAM - */ - CANFD_SIDFC(base, chan) = - _VAL2FLD(CANFD_CH_M_TTCAN_SIDFC_LSS, config->sidFilterConfig->numberOfSIDFilters) | - _VAL2FLD(CANFD_CH_M_TTCAN_SIDFC_FLSSA, config->messageRAMaddress >> CY_CANFD_MRAM_SIGNIFICANT_BYTES_SHIFT); + if ((0U != config->sidFilterConfig->numberOfSIDFilters) && + (NULL != config->sidFilterConfig->sidFilter)) + { + /* Configure a standard ID filter: + * The number of SID filters and Start address (word) of the SID filter + * configuration in Message RAM + */ + CANFD_SIDFC(base, chan) = + _VAL2FLD(CANFD_CH_M_TTCAN_SIDFC_LSS, config->sidFilterConfig->numberOfSIDFilters) | + _VAL2FLD(CANFD_CH_M_TTCAN_SIDFC_FLSSA, config->messageRAMaddress >> CY_CANFD_MRAM_SIGNIFICANT_BYTES_SHIFT); + } + else + { + CANFD_SIDFC(base, chan) = 0U; + } - /* Configure an extended ID filter: - * The number of XID filters and start address (word) of the ext id - * filter configuration in Message RAM - */ - CANFD_XIDFC(base, chan) = - _VAL2FLD(CANFD_CH_M_TTCAN_XIDFC_LSE, config->extidFilterConfig->numberOfEXTIDFilters) | - _VAL2FLD(CANFD_CH_M_TTCAN_XIDFC_FLESA, _FLD2VAL(CANFD_CH_M_TTCAN_SIDFC_FLSSA, CANFD_SIDFC(base, chan)) + + if((0U != config->extidFilterConfig->numberOfEXTIDFilters) && + (NULL != config->extidFilterConfig->extidFilter)) + { + /* Configure an extended ID filter: + * The number of XID filters and start address (word) of the ext id + * filter configuration in Message RAM + */ + CANFD_XIDFC(base, chan) = + _VAL2FLD(CANFD_CH_M_TTCAN_XIDFC_LSE, config->extidFilterConfig->numberOfEXTIDFilters) | + _VAL2FLD(CANFD_CH_M_TTCAN_XIDFC_FLESA, _FLD2VAL(CANFD_CH_M_TTCAN_SIDFC_FLSSA, CANFD_SIDFC(base, chan)) + (config->sidFilterConfig->numberOfSIDFilters)); - /* Update the extended ID AND Mask */ - CANFD_XIDAM(base, chan) = _VAL2FLD(CANFD_CH_M_TTCAN_XIDAM_EIDM, config->extidFilterConfig->extIDANDMask); + /* Update the extended ID AND Mask */ + CANFD_XIDAM(base, chan) = _VAL2FLD(CANFD_CH_M_TTCAN_XIDAM_EIDM, config->extidFilterConfig->extIDANDMask); + } + else + { + CANFD_XIDFC(base, chan) = 0U; + CANFD_XIDAM(base, chan) = 0U; + } /* Configuration of Rx Buffer and Rx FIFO */ CANFD_RXESC(base, chan) = @@ -476,11 +490,17 @@ cy_en_canfd_status_t Cy_CANFD_Init(CANFD_Type *base, uint32_t chan, _VAL2FLD(CANFD_CH_M_TTCAN_GFC_RRFS, ((config->globalFilterConfig->rejectRemoteFramesStandard) ? 1UL : 0UL))| _VAL2FLD(CANFD_CH_M_TTCAN_GFC_RRFE, ((config->globalFilterConfig->rejectRemoteFramesExtended) ? 1UL : 0UL)); - /* Standard Message ID filters */ - Cy_CANFD_SidFiltersSetup(base, chan, config->sidFilterConfig, context); + if (0U != config->sidFilterConfig->numberOfSIDFilters) + { + /* Standard Message ID filters */ + Cy_CANFD_SidFiltersSetup(base, chan, config->sidFilterConfig, context); + } - /* Extended Message ID filters */ - Cy_CANFD_XidFiltersSetup(base, chan, config->extidFilterConfig, context); + if(0U != config->extidFilterConfig->numberOfEXTIDFilters) + { + /* Extended Message ID filters */ + Cy_CANFD_XidFiltersSetup(base, chan, config->extidFilterConfig, context); + } /* Configure the interrupt */ Cy_CANFD_SetInterruptMask(base, chan, CY_CANFD_INTERRUPT_ENABLE_DEFAULT); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c index c89104a36d..a3358e3dde 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c @@ -357,6 +357,113 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03 = /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS), }; +const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_04 = +{ + /* Base HW addresses */ + /* cpussBase */ 0x40200000UL, + /* flashcBase */ 0x40240000UL, + /* periBase */ 0x40000000UL, + /* udbBase */ 0UL, + /* protBase */ 0x40230000UL, + /* hsiomBase */ 0x40300000UL, + /* gpioBase */ 0x40310000UL, + /* passBase */ 0x409F0000UL, + /* ipcBase */ 0x40220000UL, + /* cryptoBase */ 0x40100000UL, + + /* IP block versions [7:4] major, [3:0] minor */ + /* cpussVersion */ 0x20U, + /* cryptoVersion */ 0x20U, + /* dwVersion */ 0x20U, + /* ipcVersion */ 0x20U, + /* periVersion */ 0x20U, + /* srssVersion */ 0x13U, + + /* Parameters */ + /* cpussIpcNr */ 16U, + /* cpussIpcIrqNr */ 16U, + /* cpussDw0ChNr */ 30U, + /* cpussDw1ChNr */ 32U, + /* cpussFlashPaSize */ 128U, + /* cpussIpc0Irq */ 23, + /* cpussFmIrq */ 117, + /* cpussNotConnectedIrq */ 1023, + /* srssNumClkpath */ 5U, + /* srssNumPll */ 1U, + /* srssNumHfroot */ 4U, + /* periClockNr */ 28U, + /* smifDeviceNr */ 3U, + /* passSarChannels */ 16U, + /* epMonitorNr */ 0u, + /* udbPresent */ 0U, + /* sysPmSimoPresent */ 1U, + /* protBusMasterMask */ 0xC01FUL, + /* cryptoMemSize */ 1024u, + /* flashRwwRequired */ 0U, + /* flashPipeRequired */ 0U, + /* flashWriteDelay */ 0U, + /* flashProgramDelay */ 0U, + /* flashEraseDelay */ 0U, + /* flashCtlMainWs0Freq */ 25U, + /* flashCtlMainWs1Freq */ 50U, + /* flashCtlMainWs2Freq */ 75U, + /* flashCtlMainWs3Freq */ 100U, + /* flashCtlMainWs4Freq */ 125U, + + /* Peripheral register offsets */ + + /* DW registers */ + /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT), + /* dwChSize */ sizeof(DW_CH_STRUCT_V2_Type), + /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos, + /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos, + /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos, + /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk, + + /* PERI registers */ + /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD), + /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk, + /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR), + /* periTrGrSize */ sizeof(PERI_TR_GR_V2_Type), + + /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk, + /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos, + /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos, + /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos, + + /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL), + /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL), + /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL), + /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL), + + /* GPIO registers */ + /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG), + /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG), + /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN), + /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT), + /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO), + + /* CPUSS registers */ + /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL), + /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL), + /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS), + /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS), + /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL), + /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL), + /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL), + /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL), + /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL), + /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL), + /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL), + /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0), + /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0), + /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0), + + /* IPC registers */ + /* ipcStructSize */ sizeof(IPC_STRUCT_V2_Type), + /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS), +}; + /****************************************************************************** * Function Name: Cy_PDL_Init diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_efuse.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_efuse.c index 308166311c..55e985f761 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_efuse.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_efuse.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_efuse.c -* \version 1.10.1 +* \version 1.10.2 * * \brief * Provides API implementation of the eFuse driver. @@ -62,7 +62,7 @@ static cy_en_efuse_status_t ProcessOpcode(void); * - 8 is a number of fuse bits in the byte. * * The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g -* \e \/devices/psoc6/include/psoc6_01_config.\e h +* \e \/devices/include/psoc6_01_config.\e h * * \param bitVal * The pointer to the location to store the bit value. @@ -119,7 +119,7 @@ cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal) * - 32 is a number of fuse bytes in one efuse macro. * * The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g -* \e \/devices/psoc6/include/psoc6_01_config.\e h +* \e \/devices/include/psoc6_01_config.\e h * * \param byteVal * The pointer to the location to store eFuse data. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c index f5bd30c9d4..1911b97783 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_flash.c -* \version 3.30.3 +* \version 3.30.4 * * \brief * Provides the public functions for the API for the PSoC 6 Flash Driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -668,8 +668,9 @@ cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr) * XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage * detect circuits should be configured to generate an interrupt instead of a reset. * Otherwise, portions of flash may undergo unexpected changes. -* \note Before reading data from previously programmed/erased flash rows, the -* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() +* \note To avoid situation of reading data from cache memory - before +* reading data from previously programmed/erased flash rows, the user must +* clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() * function. * * \param rowAddr Address of the flash row number. @@ -719,7 +720,7 @@ cy_en_flashdrv_status_t Cy_Flash_StartEraseRow(uint32_t rowAddr) * Function Name: Cy_Flash_EraseSector ****************************************************************************//** * -* This function erases a 256KB sector of flash. Reports success or +* This function erases a sector of flash. Reports success or * a reason for failure. Does not return until the Erase operation is * complete. Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in * the case when another process is writing to flash or erasing the row. @@ -772,7 +773,7 @@ cy_en_flashdrv_status_t Cy_Flash_EraseSector(uint32_t sectorAddr) * Function Name: Cy_Flash_StartEraseSector ****************************************************************************//** * -* Starts erasing a 256KB sector of flash. Returns immediately +* Starts erasing a sector of flash. Returns immediately * and reports a successful start or reason for failure. * Reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case when IPC structure is locked * by another process. User firmware should not enter the Hibernate or Deep Sleep mode until diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c index 4731fa7402..6ea05a012a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_prot.c -* \version 1.30.1 +* \version 1.30.2 * * \brief * Provides an API implementation of the Protection Unit driver * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -776,11 +776,12 @@ cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, * The register to update attributes in. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts. -* It is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK5. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission @@ -888,11 +889,12 @@ static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t p * The register base address of the protection structure is being configured. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts, -* it is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission @@ -1013,11 +1015,12 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAddr(PERI_MS_PPU_PR_Type* base, ui * The register base address of the protection structure is being configured. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts, -* it is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission @@ -1167,11 +1170,12 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base) * The register base address of the protection structure is being configured. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts, -* it is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission @@ -1232,11 +1236,12 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedMasterAtt(PERI_MS_PPU_FX_Type* base, u * The register base address of the protection structure is being configured. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts, -* it is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_rtc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_rtc.c index 35951666fc..8c9f953ee6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_rtc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_rtc.c @@ -1,12 +1,13 @@ /***************************************************************************//** * \file cy_rtc.c -* \version 2.20.1 +* \version 2.30 * * This file provides constants and parameter values for the APIs for the * Real-Time Clock (RTC). * ******************************************************************************** -* Copyright 2016-2019 Cypress Semiconductor Corporation +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -886,9 +887,10 @@ cy_en_rtc_status_t Cy_RTC_EnableDstTime(cy_stc_rtc_dst_t const *dstTime, cy_stc_ * Function Name: Cy_RTC_SetNextDstTime ****************************************************************************//** * -* Set the next time of the DST. This function sets the time to ALARM2 for a next -* DST event. If Cy_RTC_GetDSTStatus() is true(=1), the next DST event should be -* the DST stop, then this function should be called with the DST stop time. +* A low-level DST function sets ALARM2 for a next DST event. +* If Cy_RTC_GetDSTStatus() is true(=1), the next DST event should be +* the DST stop, then this function should be called with the DST stop time. +* Used by the \ref Cy_RTC_EnableDstTime and \ref Cy_RTC_DstInterrupt functions. * * If the time format(.format) is relative option(=0), the * RelativeToFixed() is called to convert to a fixed date. @@ -959,9 +961,11 @@ cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst) * Function Name: Cy_RTC_GetDstStatus ****************************************************************************//** * -* Returns the current DST status using given time information. This function -* is used in the initial state of a system. If the DST is enabled, the system -* sets the DST start or stop as a result of this function. +* A low-level DST function returns the current DST status using given time +* information. This function is used in the initial state of a system. +* If the DST is enabled, the system sets the DST start or stop as a result of +* this function. +* Used by the \ref Cy_RTC_EnableDstTime and \ref Cy_RTC_DstInterrupt functions. * * \param dstTime The DST configuration structure, see \ref cy_stc_rtc_dst_t. * @@ -981,6 +985,7 @@ bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t co uint32_t dstStopTime; uint32_t dstStartDayOfMonth; uint32_t dstStopDayOfMonth; + bool status = false; CY_ASSERT_L1(NULL != dstTime); CY_ASSERT_L1(NULL != timeDate); @@ -1019,11 +1024,41 @@ bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t co currentTime = ((uint32_t) (timeDate->month << CY_RTC_DST_MONTH_POSITION) | (timeDate->date << CY_RTC_DST_DAY_OF_MONTH_POSITION) | (timeDate->hour)); - + dstStopTime = ((uint32_t) (dstTime->stopDst.month << CY_RTC_DST_MONTH_POSITION) | (dstStopDayOfMonth << CY_RTC_DST_DAY_OF_MONTH_POSITION) | (dstTime->stopDst.hour)); - return((dstStartTime <= currentTime) && (dstStopTime > currentTime)); + if ((dstStartTime <= currentTime) && (dstStopTime > currentTime)) + { + status = true; + + if (1UL == (dstStopTime - currentTime)) /* Check for the 'an hour before/after stop DST event' period */ + { + cy_stc_rtc_alarm_t alarm; + uint32_t locDate = (CY_RTC_DST_FIXED != dstTime->startDst.format) ? RelativeToFixed(&dstTime->startDst) : dstTime->startDst.dayOfMonth; + Cy_RTC_GetAlarmDateAndTime(&alarm, CY_RTC_ALARM_2); + + /* If Alarm2 is set for the "Start DST" event - the "Stop DST" event is already passed: */ + if ((alarm.almEn == CY_RTC_ALARM_ENABLE ) && + (alarm.monthEn == CY_RTC_ALARM_ENABLE ) && + (alarm.month == dstTime->startDst.month) && + (alarm.dateEn == CY_RTC_ALARM_ENABLE ) && + (alarm.date == locDate ) && + (alarm.dayOfWeekEn == CY_RTC_ALARM_DISABLE ) && + (alarm.hourEn == CY_RTC_ALARM_ENABLE ) && + (alarm.hour == dstTime->startDst.hour ) && + (alarm.minEn == CY_RTC_ALARM_ENABLE ) && + (alarm.min == 0UL ) && + (alarm.secEn == CY_RTC_ALARM_ENABLE ) && + (alarm.sec == 0UL )) + { + status = false; + } + /* Otherwise, including the case when Alarm2 is not set at all (DST is not enabled yet) - return true. */ + } + } + + return (status); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c index 30cad1e32a..875573ab63 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif.c -* \version 1.40.1 +* \version 1.50 * * \brief * This file provides the source code for the SMIF driver APIs. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c index 114c5e5d93..5a28464ea3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif_memslot.c -* \version 1.40.1 +* \version 1.50 * * \brief * This file provides the source code for the memory-level APIs of the SMIF driver. @@ -66,10 +66,15 @@ extern "C" { #define INSTRUCTION_NOT_SUPPORTED (0XFFU) /* The code for the not supported instruction */ #define BASIC_SPI_ID_LSB (0X00UL) /* The JEDEC SFDP Basic SPI Flash Parameter ID LSB */ #define BASIC_SPI_ID_MSB (0XFFUL) /* The JEDEC SFDP Basic SPI Flash Parameter ID MSB */ +#define SECTOR_MAP_ID_LSB (0x81UL) /* The JEDEC SFDP Sector Map ID LSB */ +#define SECTOR_MAP_ID_MSB (0xFFUL) /* The JEDEC SFDP Sector Map ID MSB */ +#define SECTOR_MAP_DESCRIPTOR_MASK (0x2U) /* The mask for the type bit of the Sector Map descriptor */ +#define SECTOR_MAP_COMAND_DESCRIPTOR_TYPE (0U) /* Code for the command descriptor type */ +#define SECTOR_MAP_REGION_SIZE_MULTIPLIER (256UL) /* The multiplier for region size units */ #define FOUR_BYTE_ADDR_ID_LSB (0X84UL) /* The 4-byte Address Instruction Table is assigned the ID LSB of 84h */ #define FOUR_BYTE_ADDR_ID_MSB (0XFFUL) /* The 4-byte Address Instruction Table is assigned the ID MSB of FFh */ -#define FOUR_BYTE_ADDR_ERASE_TYPE_1 (0X4UL) /* The Erase Type 1 offset in 4-byte Address Instruction Table */ -#define FOUR_BYTE_ADDR_ERASE_TYPE_4 (0X7UL) /* The Erase Type 4 offset in 4-byte Address Instruction Table */ +#define FOUR_BYTE_ADDR_ERASE_TYPE_1 (0X4UL) /* The Erase Type 1 offset in 4-byte Address Instruction Table */ +#define FOUR_BYTE_ADDR_ERASE_TYPE_4 (0X7UL) /* The Erase Type 4 offset in 4-byte Address Instruction Table */ #define ERASE_T_COUNT_Pos (0UL) /* Erase Type X Erase, Typical time: count (Bits 4:0) */ #define ERASE_T_COUNT_Msk (0x1FUL) /* Erase Type X Erase, Typical time: count (Bitfield-Mask) */ #define ERASE_T_UNITS_Pos (5UL) /* Erase Type X Erase, Typical time: units (Bits 6:5) */ @@ -178,6 +183,21 @@ typedef enum /** \endcond*/ +/*************************************** +* Internal Structures +***************************************/ + +/** +* This internal structure is used to store data for erase types. +*/ +typedef struct +{ + uint8_t eraseCmd; /**< The instruction used for erase transaction*/ + uint32_t eraseSize; /**< The number of bytes to be erased at one erase transaction*/ + uint32_t eraseTime; /**< The maximum erase time for one erase transaction */ +} cy_stc_smif_erase_type_t; + + /*************************************** * Internal Function Prototypes ***************************************/ @@ -214,7 +234,7 @@ static void SfdpGetReadFourBytesCmd(uint8_t const sfdpBuffer[], cy_en_smif_protocol_mode_t protocolMode, cy_stc_smif_mem_cmd_t* cmdRead); static uint32_t SfdpGetPageSize(uint8_t const sfdpBuffer[]); -static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[]); +static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[], cy_stc_smif_erase_type_t eraseType[]); static uint32_t SfdpGetChipEraseTime(uint8_t const sfdpBuffer[]); static uint32_t SfdpGetPageProgramTime(uint8_t const sfdpBuffer[]); static void SfdpSetWriteEnableCommand(cy_stc_smif_mem_cmd_t* cmdWriteEnable); @@ -230,11 +250,25 @@ static void SfdpGetQuadEnableParameters(cy_stc_smif_mem_device_cfg_t *device, uint8_t const sfdpBuffer[]); static void SfdpSetChipEraseCommand(cy_stc_smif_mem_cmd_t* cmdChipErase); static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, - uint8_t const sfdpBuffer[]); + uint8_t const sfdpBuffer[], + cy_stc_smif_erase_type_t eraseTypeStc[]); +static cy_en_smif_status_t ReadAnyReg(SMIF_Type *base, cy_en_smif_slave_select_t slaveSelect, + uint8_t *value, uint8_t command, uint8_t const *address, + uint32_t addressSize, cy_stc_smif_context_t const *context); +static cy_en_smif_status_t SfdpEnterFourByteAddressing(SMIF_Type *base, uint8_t entryMethodByte, + cy_stc_smif_mem_device_cfg_t *device, + cy_en_smif_slave_select_t slaveSelect, + cy_stc_smif_context_t const *context); +static void SfdpGetEraseSizeAndCmd(uint8_t const sfdpBuffer[], cy_stc_smif_erase_type_t eraseType[]); +static cy_en_smif_status_t SfdpPopulateRegionInfo(SMIF_Type *base, uint8_t const sectorMapBuff[], + uint32_t const buffLength, cy_stc_smif_mem_device_cfg_t *device, + cy_en_smif_slave_select_t slaveSelect, const cy_stc_smif_context_t *context, + cy_stc_smif_erase_type_t eraseType[]); static void SfdpSetWipStatusRegisterCommand(cy_stc_smif_mem_cmd_t* readStsRegWipCmd); static cy_en_smif_status_t PollTransferStatus(SMIF_Type const *base, cy_en_smif_txfr_status_t transferStatus, cy_stc_smif_context_t const *context); static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startPos, uint32_t size); +static uint32_t ByteArrayToValue(uint8_t const *byteArray, uint32_t size); /******************************************************************************* * Function Name: Cy_SMIF_MemInit @@ -269,7 +303,10 @@ static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startP * mapped into the PSoC memory map. \ref cy_stc_smif_mem_config_t * * \param context -* The SMIF internal context structure of the block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The memory slot initialization status. * - \ref CY_SMIF_SUCCESS @@ -496,7 +533,10 @@ void Cy_SMIF_MemDeInit(SMIF_Type *base) * The device to which the command is sent. * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -523,7 +563,7 @@ cy_en_smif_status_t Cy_SMIF_MemCmdWriteEnable(SMIF_Type *base, memDevice->slaveSelect, CY_SMIF_TX_LAST_BYTE, context); - } + } return result; } @@ -546,7 +586,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdWriteEnable(SMIF_Type *base, * The device to which the command is sent. * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -597,7 +640,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdWriteDisable(SMIF_Type *base, * The device to which the command is sent. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the memory device. * - True - The device is busy or a timeout occurs. @@ -647,7 +693,10 @@ bool Cy_SMIF_MemIsBusy(SMIF_Type *base, cy_stc_smif_mem_config_t const *memDevic * The device to which the command is sent. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command. * - \ref CY_SMIF_SUCCESS @@ -750,7 +799,10 @@ cy_en_smif_status_t Cy_SMIF_MemQuadEnable(SMIF_Type *base, * The command required to read the status/configuration register. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command reception. * - \ref CY_SMIF_SUCCESS @@ -809,7 +861,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdReadStatus(SMIF_Type *base, * The command to write into the status/configuration register. * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -863,7 +918,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdWriteStatus(SMIF_Type *base, * The device to which the command is sent * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -911,7 +969,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdChipErase(SMIF_Type *base, * The sector address to erase. * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -927,15 +988,21 @@ cy_en_smif_status_t Cy_SMIF_MemCmdSectorErase(SMIF_Type *base, { cy_en_smif_status_t result = CY_SMIF_BAD_PARAM; + CY_ASSERT_L1(NULL != memDevice); + if (NULL != sectorAddr) { - cy_stc_smif_mem_device_cfg_t *device = memDevice->deviceCfg; cy_stc_smif_mem_cmd_t *cmdErase = device->eraseCmd; - - if ((NULL != cmdErase) && (CY_SMIF_WIDTH_NA != cmdErase->cmdWidth)) + cy_stc_smif_hybrid_region_info_t* hybrInfo = NULL; + + result = Cy_SMIF_MemLocateHybridRegion(memDevice, &hybrInfo, + ByteArrayToValue(sectorAddr, device->numOfAddrBytes)); + + if ((NULL != cmdErase) && (CY_SMIF_WIDTH_NA != cmdErase->cmdWidth) && (result != CY_SMIF_BAD_PARAM)) { - result = Cy_SMIF_TransmitCommand( base, (uint8_t)cmdErase->command, + uint8_t eraseCommand = (uint8_t)((result == CY_SMIF_SUCCESS) ? (hybrInfo->eraseCmd) : (cmdErase->command)); + result = Cy_SMIF_TransmitCommand( base, eraseCommand, cmdErase->cmdWidth, sectorAddr, device->numOfAddrBytes, cmdErase->cmdWidth, memDevice->slaveSelect, CY_SMIF_TX_LAST_BYTE, context); @@ -987,7 +1054,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdSectorErase(SMIF_Type *base, * as no callback. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of a transmission. * - \ref CY_SMIF_SUCCESS @@ -1092,7 +1162,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdProgram(SMIF_Type *base, * as no callback. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the transmission. * - \ref CY_SMIF_SUCCESS @@ -1160,6 +1233,72 @@ cy_en_smif_status_t Cy_SMIF_MemCmdRead(SMIF_Type *base, } +/******************************************************************************* +* Function Name: Cy_SMIF_MemLocateHybridRegion +****************************************************************************//** +* +* This function locates the region structure by the address which belongs to it. +* +* \note This function is valid for the memories with hybrid sectors. +* +* \param memDevice +* The memory device configuration. +* +* \param regionInfo +* Places a hybrid region configuration structure that contains the region +* specific parameters. See \ref cy_stc_smif_hybrid_region_info_t for +* reference. +* +* \param address +* The address for which a region is searched. +* +* \return A status of the region location. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_NOT_HYBRID_MEM +* - \ref CY_SMIF_BAD_PARAM +* +* \funcusage +* \snippet smif/snippet/main.c snippet_Cy_SMIF_MemLocateHybridRegion +* +*******************************************************************************/ +cy_en_smif_status_t Cy_SMIF_MemLocateHybridRegion(cy_stc_smif_mem_config_t const *memDevice, + cy_stc_smif_hybrid_region_info_t** regionInfo, + uint32_t address) +{ + cy_en_smif_status_t result = CY_SMIF_BAD_PARAM; + cy_stc_smif_hybrid_region_info_t* currInfo = NULL; + CY_ASSERT_L1(NULL != memDevice); + cy_stc_smif_mem_device_cfg_t *device = memDevice->deviceCfg; + + /* Check if the address exceeds the memory size */ + if(address <= device->memSize) + { + result = CY_SMIF_NOT_HYBRID_MEM; + /* Check if the memory is hybrid */ + if(NULL != device->hybridRegionInfo) + { + uint32_t idx; + uint32_t regionStartAddr; + uint32_t regionEndAddr; + for(idx = 0UL; idx < device->hybridRegionCount; idx++) + { + currInfo = device->hybridRegionInfo[idx]; + regionStartAddr = currInfo->regionAddress; + regionEndAddr = regionStartAddr + (currInfo->sectorsCount * currInfo->eraseSize); + if ((address >= regionStartAddr) && (address < regionEndAddr)) + { + *regionInfo = currInfo; + result = CY_SMIF_SUCCESS; + break; + } + } + } + } + + return result; +} + + /******************************************************************************* * Function Name: SfdpReadBuffer ****************************************************************************//** @@ -1192,7 +1331,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdRead(SMIF_Type *base, * The pointer to an array with the SDFP buffer. * * \param context -* Internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the transmission. * - \ref CY_SMIF_SUCCESS @@ -1828,48 +1970,53 @@ static uint32_t SfdpGetPageSize(uint8_t const sfdpBuffer[]) * \param sfdpBuffer * The pointer to an array with the SDFP buffer. * -* \return Erase time in us. +* \param eraseTypeTime +* The pointer to an array with the erase time in us for different erase types. +* +* \return Default erase time in us. * *******************************************************************************/ -static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[]) +static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[], cy_stc_smif_erase_type_t eraseType[]) { /* Get the value of 10th DWORD from the JEDEC basic flash parameter table */ uint32_t readEraseTime = ((uint32_t*)sfdpBuffer)[CY_SMIF_JEDEC_BFPT_10TH_DWORD]; - uint32_t eraseTimeMax; - uint32_t eraseTimeIndex = (((eraseOffset - CY_SMIF_SFDP_BFPT_BYTE_1D) + TYPE_STEP) / TYPE_STEP); - uint32_t eraseUnits = _FLD2VAL(ERASE_T_UNITS, - (readEraseTime >> ((eraseTimeIndex - 1UL) * ERASE_T_LENGTH)) - >> ERASE_T_COUNT_OFFSET); - uint32_t eraseCount = _FLD2VAL(ERASE_T_COUNT, - (readEraseTime >> ((eraseTimeIndex - 1UL) * ERASE_T_LENGTH)) - >> ERASE_T_COUNT_OFFSET); + uint32_t eraseTimeDefaultIndex = (((eraseOffset - CY_SMIF_SFDP_BFPT_BYTE_1D) + TYPE_STEP) / TYPE_STEP); uint32_t eraseMul = _FLD2VAL(CY_SMIF_SFDP_ERASE_MUL_COUNT, readEraseTime); + uint32_t eraseUnits = 0UL; + uint32_t eraseCount = 0UL; uint32_t eraseMs = 0UL; + uint32_t eraseTypeTypicalTime; - switch (eraseUnits) - { - case CY_SMIF_SFDP_UNIT_0: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_1MS; - break; - case CY_SMIF_SFDP_UNIT_1: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_16MS; - break; - case CY_SMIF_SFDP_UNIT_2: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_128MS; - break; - case CY_SMIF_SFDP_UNIT_3: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_1S; - break; - default: - /* An unsupported SFDP value */ - break; + for (uint32_t idx = 0UL; idx < ERASE_TYPE_COUNT; idx++){ + eraseTypeTypicalTime = (readEraseTime >> (idx * ERASE_T_LENGTH))>> ERASE_T_COUNT_OFFSET; + eraseUnits = _FLD2VAL(ERASE_T_UNITS, eraseTypeTypicalTime); + eraseCount = _FLD2VAL(ERASE_T_COUNT, eraseTypeTypicalTime); + + switch (eraseUnits) + { + case CY_SMIF_SFDP_UNIT_0: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_1MS; + break; + case CY_SMIF_SFDP_UNIT_1: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_16MS; + break; + case CY_SMIF_SFDP_UNIT_2: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_128MS; + break; + case CY_SMIF_SFDP_UNIT_3: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_1S; + break; + default: + /* An unsupported SFDP value */ + break; + } + + /* Convert typical time to max time */ + eraseType[idx].eraseTime = ((eraseCount + 1UL) * eraseMs) * (2UL * (eraseMul + 1UL)); } - /* Convert typical time to max time */ - eraseTimeMax = ((eraseCount + 1UL) * eraseMs) * (2UL * (eraseMul + 1UL)); - - return(eraseTimeMax); + return(eraseType[eraseTimeDefaultIndex - 1UL].eraseTime); } @@ -2328,12 +2475,16 @@ static void SfdpSetChipEraseCommand(cy_stc_smif_mem_cmd_t* cmdChipErase) * \param sfdpBuffer * The pointer to an array with the SDFP buffer. * +* \param eraseTypeCmd +* The pointer to an array with the erase commands for different erase types. +* * \return The offset of the Sector Erase command in the SFDP buffer. * Returns 0 when the Sector Erase command is not found. * *******************************************************************************/ static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, - uint8_t const sfdpBuffer[]) + uint8_t const sfdpBuffer[], + cy_stc_smif_erase_type_t eraseTypeStc[]) { uint32_t eraseOffset; if (FOUR_BYTE_ADDRESS == device->numOfAddrBytes) @@ -2364,6 +2515,11 @@ static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, /* Calculate the offset for the sector Erase command in the 4-byte Address Instruction Table, DWORD 2 */ eraseOffset = FOUR_BYTE_ADDR_ERASE_TYPE_1 + eraseType; + /* Update all erase commands for 4-bytes*/ + for(uint32_t i = 0UL; i< ERASE_TYPE_COUNT; i++) + { + eraseTypeStc[i].eraseCmd = sfdpBuffer[FOUR_BYTE_ADDR_ERASE_TYPE_1 + i]; + } /* Get the sector Erase command * from the 4-byte Address Instruction Table, DWORD 2 */ @@ -2413,6 +2569,371 @@ static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, } +/******************************************************************************* +* Function Name: ReadAnyReg +****************************************************************************//** +* +* This function reads any registers by address. This function is a blocking +* function, it will block the execution flow until the status register is read. +* +* \param base +* Holds the base address of the SMIF block registers. +* +* \param slaveSelect +* The slave select line for the device. +* +* \param value +* The value of the register. +* +* \param command +* The command required to read the status/configuration register. +* +* \param address +* The register address array. +* +* \param addressSize +* The size of the address array. +* +* \param context +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. +* +* \return A status of the command reception. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_CMD_FIFO_FULL +* - \ref CY_SMIF_EXCEED_TIMEOUT +* - \ref CY_SMIF_CMD_NOT_FOUND +* +*******************************************************************************/ +static cy_en_smif_status_t ReadAnyReg(SMIF_Type *base, + cy_en_smif_slave_select_t slaveSelect, + uint8_t *value, + uint8_t command, + uint8_t const *address, + uint32_t addressSize, + cy_stc_smif_context_t const *context) +{ + cy_en_smif_status_t result = CY_SMIF_CMD_NOT_FOUND; + + /* Read the memory register */ + result = Cy_SMIF_TransmitCommand(base, command, CY_SMIF_WIDTH_SINGLE, + address, addressSize, + CY_SMIF_WIDTH_SINGLE, slaveSelect, + CY_SMIF_TX_NOT_LAST_BYTE, context); + + if (CY_SMIF_SUCCESS == result) + { + result = Cy_SMIF_ReceiveDataBlocking( base, value, + CY_SMIF_READ_ONE_BYTE, CY_SMIF_WIDTH_SINGLE, context); + } + + return(result); +} + + +/******************************************************************************* +* Function Name: SfdpEnterFourByteAddressing +****************************************************************************//** +* +* This function sets 4-byte address mode for a memory device as defined in +* 16th DWORD of JEDEC Basic Flash Parameter Table. +* +* \note The entry methods which do not support the required +* operation of writing into the register. +* +* \param base +* Holds the base address of the SMIF block registers. +* +* \param entryMethodByte +* The byte which defines the supported method to enter 4-byte addressing mode. +* +* \param device +* The device structure instance declared by the user. This is where the detected +* parameters are stored and returned. +* +* \param slaveSelect +* The slave select line for the device. +* +* \param context +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. +* +* \return A status of 4-byte addressing mode command transmit. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_EXCEED_TIMEOUT +* - \ref CY_SMIF_CMD_NOT_FOUND +*******************************************************************************/ +static cy_en_smif_status_t SfdpEnterFourByteAddressing(SMIF_Type *base, uint8_t entryMethodByte, + cy_stc_smif_mem_device_cfg_t *device, + cy_en_smif_slave_select_t slaveSelect, + cy_stc_smif_context_t const *context) +{ + cy_en_smif_status_t result = CY_SMIF_CMD_NOT_FOUND; + if ((entryMethodByte & CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_ALWAYS_4_BYTE) != 0U) + { + /* Memory always operates in 4-byte mode */ + result = CY_SMIF_SUCCESS; + } + if ((entryMethodByte & CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7) != 0U) + { + if ((entryMethodByte & CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_WR_EN_B7) != 0U) + { + /* To enter a 4-byte addressing write enable is required */ + cy_stc_smif_mem_cmd_t* writeEn = device->writeEnCmd; + if(NULL != writeEn) + { + result = Cy_SMIF_TransmitCommand(base, + (uint8_t) writeEn->command, + writeEn->cmdWidth, + CY_SMIF_CMD_WITHOUT_PARAM, + CY_SMIF_CMD_WITHOUT_PARAM, + CY_SMIF_WIDTH_NA, + slaveSelect, + CY_SMIF_TX_LAST_BYTE, + context); + } + } + if ((CY_SMIF_CMD_NOT_FOUND == result) || (CY_SMIF_SUCCESS == result)) + { + /* To enter a 4-byte addressing B7 instruction is required*/ + result = Cy_SMIF_TransmitCommand(base, + CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7_CMD, + CY_SMIF_WIDTH_SINGLE, + CY_SMIF_CMD_WITHOUT_PARAM, + CY_SMIF_CMD_WITHOUT_PARAM, + CY_SMIF_WIDTH_NA, + slaveSelect, + CY_SMIF_TX_LAST_BYTE, + context); + } + } + + return result; +} + + +/******************************************************************************* +* Function Name: SfdpGetEraseSizeAndCmd +****************************************************************************//** +* +* Fills arrays with an erase size and cmd for all erase types. +* +* \param sfdpBuffer +* The pointer to an array with the Basic Flash Parameter table buffer. +* +* \param eraseTypeCmd +* The pointer to an array with the erase commands for all erase types. +* +* \param eraseTypeSize +* The pointer to an array with the erase size for all erase types. +* +*******************************************************************************/ +static void SfdpGetEraseSizeAndCmd(uint8_t const sfdpBuffer[], + cy_stc_smif_erase_type_t eraseType[]) +{ + uint32_t idx = 0UL; + for (uint32_t currET = 0UL; currET < ERASE_TYPE_COUNT; currET++) + { + /* The erase size in the SFDP buffer defined as power of two */ + eraseType[currET].eraseSize = 1UL << sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_1C + idx]; + eraseType[currET].eraseCmd = sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_1D + idx]; + idx += TYPE_STEP; + } +} + + +/******************************************************************************* +* Function Name: SfdpPopulateRegionInfo +****************************************************************************//** +* +* Reads the current configuration for regions and populates regionInfo +* structures. +* +* \param base +* Holds the base address of the SMIF block registers. +* +* \param sectorMapBuff +* The pointer to an array with the Sector Map Parameter Table buffer. +* +* \param device +* The device structure instance declared by the user. This is where the detected +* parameters are stored and returned. +* +* \param slaveSelect +* The slave select line for the device. +* +* \param context +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. +* +* \param eraseTypeSize +* The pointer to an array with the erase size for all erase types. +* +* \param eraseTypeCmd +* The pointer to an array with the erase commands for all erase types. +* +* \param eraseTypeTime +* The pointer to an array with the erase time for all erase types. +* +* \return A status of the Sector Map Parameter Table parsing. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_SFDP_CORRUPTED_TABLE +* - \ref CY_SMIF_NOT_HYBRID_MEM +* +*******************************************************************************/ +static cy_en_smif_status_t SfdpPopulateRegionInfo(SMIF_Type *base, + uint8_t const sectorMapBuff[], + uint32_t const buffLength, + cy_stc_smif_mem_device_cfg_t *device, + cy_en_smif_slave_select_t slaveSelect, + const cy_stc_smif_context_t *context, + cy_stc_smif_erase_type_t eraseType[]) +{ + uint8_t currCmd; + uint8_t regMask; + uint8_t regValue; + uint8_t currRegisterAddr[ERASE_TYPE_COUNT] = {0U}; + uint8_t regionInfoIdx = 0U; + uint32_t currTableIdx = 0UL; + uint32_t addrBytesNum = 0UL; + uint32_t addrCode = 0UL; + cy_en_smif_status_t result = CY_SMIF_NOT_HYBRID_MEM; + + /* Loop across all command descriptors to find current configuration */ + while(SECTOR_MAP_COMAND_DESCRIPTOR_TYPE == (sectorMapBuff[currTableIdx] & SECTOR_MAP_DESCRIPTOR_MASK)) + { + currCmd = sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_CMD_OFFSET]; + regMask = sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_REG_MSK_OFFSET]; + regValue = 0U; + + /* Get the address length for configuration detection */ + addrCode = _FLD2VAL(CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES, sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_ADDR_CODE_OFFSET]); + switch(addrCode) + { + case CY_SMIF_SFDP_THREE_BYTES_ADDR_CODE: + /* No address cycle */ + addrBytesNum = 0UL; + break; + case CY_SMIF_SFDP_THREE_OR_FOUR_BYTES_ADDR_CODE: + addrBytesNum = CY_SMIF_THREE_BYTES_ADDR; + break; + case CY_SMIF_SFDP_FOUR_BYTES_ADDR_CODE: + addrBytesNum = CY_SMIF_FOUR_BYTES_ADDR; + break; + default: + /* Use the current settings */ + addrBytesNum = device->numOfAddrBytes; + break; + } + + /* Get the control register address */ + for(uint32_t i = 0UL; i < addrBytesNum; i++) + { + /* Offset for control register in SFDP has little-endian byte order, need to swap it */ + currRegisterAddr[i] = sectorMapBuff[(currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_REG_ADDR_OFFSET + addrBytesNum) - i - 1UL]; + } + + /* Read the value of the register for the current configuration detection*/ + result = ReadAnyReg(base, slaveSelect, ®Value, currCmd, &currRegisterAddr[0], addrBytesNum, context); + + if (CY_SMIF_SUCCESS == result) + { + /* Set the bit of the region idx to 1 if the config matches */ + regionInfoIdx = ((uint8_t)(regionInfoIdx << 1U)) | (((regValue & regMask) == 0U)?(0U):(1U)); + } + + currTableIdx += HEADER_LENGTH; + if (currTableIdx > buffLength) + { + result = CY_SMIF_SFDP_CORRUPTED_TABLE; + break; + } + } + + if (CY_SMIF_SUCCESS == result) + { + /* Find the matching configuration map descriptor */ + while(regionInfoIdx != sectorMapBuff[currTableIdx + 1UL]) + { + /* Increment the table index to the next map */ + currTableIdx += (sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_CONFIG_ID_OFFSET] + 2UL) * BYTES_IN_DWORD; + if (currTableIdx > buffLength) + { + result = CY_SMIF_SFDP_CORRUPTED_TABLE; + break; + } + } + } + + if (CY_SMIF_SUCCESS == result) + { + /* Populate region data from the sector map */ + uint8_t numOfRegions = sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_REGION_COUNT_OFFSET] + 1U; + device->hybridRegionCount = (uint32_t) numOfRegions; + + if(numOfRegions <= 1U) + { + result = CY_SMIF_NOT_HYBRID_MEM; + } + else + { + uint8_t eraseTypeCode; + uint32_t currRegionAddr = 0UL; + uint32_t regionSize = 0UL; + uint8_t supportedEraseType; + uint8_t eraseTypeMask; + cy_stc_smif_hybrid_region_info_t *currRegionPtr; + for(uint8_t currRegion = 0U; currRegion< numOfRegions; currRegion++) + { + currRegionAddr = currRegionAddr + regionSize; + currTableIdx += BYTES_IN_DWORD; + + supportedEraseType = 0U; + eraseTypeMask = 1U; + eraseTypeCode = sectorMapBuff[currTableIdx] & CY_SMIF_SFDP_SECTOR_MAP_SUPPORTED_ET_MASK; + while(0U == (eraseTypeCode & eraseTypeMask)) + { + /* Erase type number defined as a bit position */ + eraseTypeMask = eraseTypeMask << 1; + supportedEraseType++; + if(supportedEraseType > ERASE_TYPE_COUNT) + { + result = CY_SMIF_SFDP_CORRUPTED_TABLE; + break; + } + } + + /* The region size as a zero-based count of 256 byte units */ + regionSize = ((*( (uint32_t*) §orMapBuff[currTableIdx]) >> BITS_IN_BYTE) + 1UL) * SECTOR_MAP_REGION_SIZE_MULTIPLIER; + currRegionPtr = device->hybridRegionInfo[currRegion]; + + currRegionPtr->regionAddress = currRegionAddr; + currRegionPtr->eraseCmd = (uint32_t)eraseType[supportedEraseType].eraseCmd; + currRegionPtr->eraseTime = eraseType[supportedEraseType].eraseTime; + if(regionSize < eraseType[supportedEraseType].eraseSize) + { + /* One region with a single sector */ + currRegionPtr->eraseSize = regionSize; + currRegionPtr->sectorsCount = 1UL; + } + else + { + currRegionPtr->eraseSize = eraseType[supportedEraseType].eraseSize; + currRegionPtr->sectorsCount = regionSize / eraseType[supportedEraseType].eraseSize; + } + } + } + } + return result; +} + + /******************************************************************************* * Function Name: Cy_SMIF_MemSfdpDetect ****************************************************************************//** @@ -2457,7 +2978,10 @@ static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, * The data line selection options for a slave device. * * \param context -* Internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the transmission. * - \ref CY_SMIF_SUCCESS @@ -2478,8 +3002,10 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, uint8_t sfdpBuffer[CY_SMIF_SFDP_LENGTH]; uint8_t sfdpAddress[CY_SMIF_SFDP_ADDRESS_LENGTH] = {0x00U, 0x00U, 0x00U}; uint8_t addr4ByteAddress[CY_SMIF_SFDP_ADDRESS_LENGTH] = {0x00U, 0x00U, 0x00U}; + uint8_t sectorMapAddr[CY_SMIF_SFDP_ADDRESS_LENGTH] = {0x00U, 0x00U, 0x00U}; cy_en_smif_status_t result = CY_SMIF_NO_SFDP_SUPPORT; cy_stc_smif_mem_cmd_t *cmdSfdp = device->readSfdpCmd; + cy_stc_smif_erase_type_t eraseType[ERASE_TYPE_COUNT]; /* Initialize the SFDP buffer */ for (uint32_t i = 0U; i < CY_SMIF_SFDP_LENGTH; i++) @@ -2522,11 +3048,21 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, uint32_t id = (FOUR_BYTE_ADDR_ID_MSB << BITS_IN_BYTE) | FOUR_BYTE_ADDR_ID_LSB; uint32_t addr4ByteTableLength = 0UL; result = SfdpFindParameterTableAddress(id, sfdpBuffer, addr4ByteAddress, &addr4ByteTableLength); - + + /* Find the Sector Map Parameter Header */ + id = (SECTOR_MAP_ID_MSB << BITS_IN_BYTE) | SECTOR_MAP_ID_LSB; + uint32_t sectorMapTableLength = 0UL; + result = SfdpFindParameterTableAddress(id, sfdpBuffer, sectorMapAddr, §orMapTableLength); + if (CY_SMIF_CMD_NOT_FOUND == result) + { + device->hybridRegionCount = 0UL; + device->hybridRegionInfo = NULL; + } + /* Find the JEDEC SFDP Basic SPI Flash Parameter Header */ id = (BASIC_SPI_ID_MSB << BITS_IN_BYTE) | BASIC_SPI_ID_LSB; uint32_t basicSpiTableLength = 0UL; - result = SfdpFindParameterTableAddress(id, sfdpBuffer, sfdpAddress, &basicSpiTableLength); + result = SfdpFindParameterTableAddress(id, sfdpBuffer, sfdpAddress, &basicSpiTableLength); if (CY_SMIF_SUCCESS == result) { @@ -2536,10 +3072,10 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, CY_ASSERT_L1(NULL != device->eraseCmd); CY_ASSERT_L1(NULL != device->chipEraseCmd); CY_ASSERT_L1(NULL != device->programCmd); - CY_ASSERT_L1(NULL != device->readStsRegWipCmd); + CY_ASSERT_L1(NULL != device->readStsRegWipCmd); /* Get the JEDEC basic flash parameter table content into sfdpBuffer[] */ - result = SfdpReadBuffer(base, + result = SfdpReadBuffer(base, cmdSfdp, sfdpAddress, slaveSelect, @@ -2547,24 +3083,27 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, sfdpBuffer, context); + /* The erase size and erase time for all 4 erase types */ + SfdpGetEraseSizeAndCmd(sfdpBuffer, eraseType); + /* The number of address bytes used by the memory slave device */ device->numOfAddrBytes = SfdpGetNumOfAddrBytes(sfdpBuffer); /* The external memory size */ device->memSize = SfdpGetMemoryDensity(sfdpBuffer); - + /* The page size */ device->programSize = SfdpGetPageSize(sfdpBuffer); /* The Write Enable command */ - SfdpSetWriteEnableCommand(device->writeEnCmd); + SfdpSetWriteEnableCommand(device->writeEnCmd); /* The Write Disable command */ SfdpSetWriteDisableCommand(device->writeDisCmd); /* The busy mask for the status registers */ device->stsRegBusyMask = CY_SMIF_STATUS_REG_BUSY_MASK; - + /* The command to read the WIP-containing status register */ SfdpSetWipStatusRegisterCommand(device->readStsRegWipCmd); @@ -2573,13 +3112,13 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, /* Chip Erase command */ SfdpSetChipEraseCommand(device->chipEraseCmd); - + /* Chip Erase Time */ device->chipEraseTime = SfdpGetChipEraseTime(sfdpBuffer); /* Page Program Time */ device->programTime = SfdpGetPageProgramTime(sfdpBuffer); - + /* The Read command for 3-byte addressing. The preference order quad > dual > single SPI */ cy_stc_smif_mem_cmd_t *cmdRead = device->readCmd; cy_en_smif_protocol_mode_t pMode = SfdpGetReadCmdParams(sfdpBuffer, dataSelect, cmdRead); @@ -2588,11 +3127,15 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, uint32_t eraseTypeOffset = 1UL; if (FOUR_BYTE_ADDRESS == device->numOfAddrBytes) { - /* Get the JEDEC 4-byte Address Instruction Table content into sfdpBuffer[] */ + /* Enter 4-byte addressing mode */ + result = SfdpEnterFourByteAddressing(base, sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_3C], device, slaveSelect, context); uint8_t fourByteAddressBuffer[CY_SMIF_SFDP_LENGTH]; - result = SfdpReadBuffer(base, cmdSfdp, addr4ByteAddress, slaveSelect, - addr4ByteTableLength, fourByteAddressBuffer, context); - + if (CY_SMIF_SUCCESS == result) + { + /* Get the JEDEC 4-byte Address Instruction Table content into sfdpBuffer[] */ + result = SfdpReadBuffer(base, cmdSfdp, addr4ByteAddress, slaveSelect, + addr4ByteTableLength, fourByteAddressBuffer, context); + } if (CY_SMIF_SUCCESS == result) { /* Rewrite the Read command instruction for 4-byte addressing mode */ @@ -2601,8 +3144,8 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, /* Get the Program command instruction for 4-byte addressing mode */ SfdpGetProgramFourBytesCmd(fourByteAddressBuffer, pMode, device->programCmd); - /* Find the sector Erase command type with 4-byte addressing */ - eraseTypeOffset = SfdpGetSectorEraseCommand(device, fourByteAddressBuffer); + /* Find the sector Erase command type with 4-byte addressing */ + eraseTypeOffset = SfdpGetSectorEraseCommand(device, fourByteAddressBuffer, eraseType); } } else @@ -2611,7 +3154,7 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, SfdpSetProgramCommand_1_1_1(device->programCmd); /* Find the sector Erase command type with 3-byte addressing */ - eraseTypeOffset = SfdpGetSectorEraseCommand(device, sfdpBuffer); + eraseTypeOffset = SfdpGetSectorEraseCommand(device, sfdpBuffer, eraseType); } if (COMMAND_IS_NOT_FOUND != eraseTypeOffset) @@ -2620,7 +3163,24 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, device->eraseSize = 0x01UL << sfdpBuffer[eraseTypeOffset - 1UL]; /* Erase Time Type (from the JEDEC basic flash parameter table) */ - device->eraseTime = SfdpGetEraseTime(eraseTypeOffset, sfdpBuffer); + device->eraseTime = SfdpGetEraseTime(eraseTypeOffset, sfdpBuffer, eraseType); + } + + if (NULL != device->hybridRegionInfo) + { + /* Get the Sector Map Parameter Table into sfdpBuffer[] */ + result = SfdpReadBuffer(base, cmdSfdp, sectorMapAddr, slaveSelect, + sectorMapTableLength, sfdpBuffer, context); + if (CY_SMIF_SUCCESS == result) + { + result = SfdpPopulateRegionInfo(base, sfdpBuffer, sectorMapTableLength, device, slaveSelect, context, eraseType); + if(result == CY_SMIF_NOT_HYBRID_MEM) + { + device->hybridRegionCount = 0UL; + device->hybridRegionInfo = NULL; + result = CY_SMIF_SUCCESS; + } + } } } } @@ -2653,8 +3213,10 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, * The timeout value in microseconds to apply while polling the memory. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. * \ref CY_SMIF_SUCCESS - Memory is ready to accept new commands. @@ -2721,8 +3283,10 @@ cy_en_smif_status_t Cy_SMIF_MemIsReady(SMIF_Type *base, cy_stc_smif_mem_config_t * CY_SMIF_SUCCESS. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * @@ -2771,8 +3335,10 @@ cy_en_smif_status_t Cy_SMIF_MemIsQuadEnabled(SMIF_Type *base, cy_stc_smif_mem_co * The timeout value in microseconds to apply while polling the memory. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * @@ -2821,8 +3387,10 @@ cy_en_smif_status_t Cy_SMIF_MemEnableQuadMode(SMIF_Type *base, cy_stc_smif_mem_c * Transfer status value to be checked. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. * \ref CY_SMIF_SUCCESS - SMIF block has completed the transfer @@ -2881,6 +3449,36 @@ static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startP } +/******************************************************************************* +* Function Name: ByteArrayToValue +****************************************************************************//** +* +* Packs the byte array into a single value. +* +* \param byteArray +* The byte array to unpack. +* +* \param size +* The size of the array. +* +* \return +* The 4-byte value filled from the array. +* +* +*******************************************************************************/ +static uint32_t ByteArrayToValue(uint8_t const *byteArray, uint32_t size) +{ + uint32_t value = 0UL; + uint32_t idx = 0UL; + for (idx = 0UL; idx < size; idx++) + { + value <<= 8; + value |= ((uint32_t) byteArray[idx]); + } + return value; +} + + /******************************************************************************* * Function Name: Cy_SMIF_MemRead ****************************************************************************//** @@ -2906,8 +3504,10 @@ static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startP * The size of data to read. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * @@ -2986,8 +3586,10 @@ cy_en_smif_status_t Cy_SMIF_MemRead(SMIF_Type *base, cy_stc_smif_mem_config_t co * The size of data to write. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * @@ -3084,67 +3686,120 @@ cy_en_smif_status_t Cy_SMIF_MemWrite(SMIF_Type *base, cy_stc_smif_mem_config_t c * The size of data to erase. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * +* \note The address should be aligned with the start address of the sector. \n +* The length should be equal to the sum of all erased sectors. +* * \funcusage * \snippet smif/snippet/main.c snippet_Cy_SMIF_MemEraseSector * *******************************************************************************/ -cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, - uint32_t address, uint32_t length, +cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, + uint32_t address, uint32_t length, cy_stc_smif_context_t const *context) { cy_en_smif_status_t status = CY_SMIF_BAD_PARAM; - uint32_t offset = 0UL; - uint32_t chunk = 0UL; + uint32_t endAddress = address + length; + uint32_t eraseEnd = 0UL; + uint32_t hybridRegionStart = 0UL; uint8_t addrArray[CY_SMIF_FOUR_BYTES_ADDR] = {0U}; + cy_stc_smif_hybrid_region_info_t* hybrInfo = NULL; CY_ASSERT_L1(NULL != memConfig); - uint32_t eraseSectorSize = memConfig->deviceCfg->eraseSize; + cy_stc_smif_mem_device_cfg_t *device = memConfig->deviceCfg; + uint32_t eraseSectorSize = device->eraseSize; + uint32_t maxEraseTime = device->eraseTime; - if(((address + length) <= memConfig->deviceCfg->memSize) && /* Check if the address exceeds the memory size */ - (0UL == (address % eraseSectorSize)) && /* Check if the start address and the sector size are aligned */ - (0UL == ((address + length) % eraseSectorSize))) /* Check if the end address and the sector size are aligned */ + /* In case of hybrid memory - update sector size and offset for first sector */ + status = Cy_SMIF_MemLocateHybridRegion(memConfig, &hybrInfo, address); + if (CY_SMIF_SUCCESS == status) { - while(length > 0UL) + hybridRegionStart = hybrInfo->regionAddress; + eraseSectorSize = hybrInfo->eraseSize; + eraseEnd = (hybrInfo->sectorsCount * eraseSectorSize) + hybridRegionStart; + } + + /* Check if the end address not equal to start address */ + if(length == 0UL) + { + status = CY_SMIF_BAD_PARAM; + } + + /* Check if the start address and the sector size are aligned */ + if((0UL == ((address - hybridRegionStart) % eraseSectorSize)) && (status != CY_SMIF_BAD_PARAM)) + { + /* If the memory is hybrid and there is more than one region to + * erase - update the sector size and offset for the last sector */ + if(endAddress < eraseEnd) { - /* Get the number of bytes which can be erase during one operation */ - offset = address % eraseSectorSize; - chunk = ((offset + length) < eraseSectorSize) ? length : (eraseSectorSize - offset); - - /* The Write Enable bit may be cleared by the memory after every successful - * operation of write/erase operations. Therefore, it must be set for - * every loop. - */ - status = Cy_SMIF_MemCmdWriteEnable(base, memConfig, context); - - if(CY_SMIF_SUCCESS == status) + status = Cy_SMIF_MemLocateHybridRegion(memConfig, &hybrInfo, (endAddress - 1UL)); + if (CY_SMIF_SUCCESS == status) { - ValueToByteArray(address, &addrArray[0], 0UL, - memConfig->deviceCfg->numOfAddrBytes); + hybridRegionStart = hybrInfo->regionAddress; + eraseSectorSize = hybrInfo->eraseSize; + } + } - /* Send the command to erase one sector */ - status = Cy_SMIF_MemCmdSectorErase(base, (cy_stc_smif_mem_config_t* )memConfig, - (const uint8_t *)addrArray, context); - - if(CY_SMIF_SUCCESS == status) + /* Check if the end address and the sector size are aligned */ + if((0UL == ((endAddress - hybridRegionStart) % eraseSectorSize)) && (status != CY_SMIF_BAD_PARAM)) + { + while(length > 0UL) + { + /* In case of hybrid memory - update erase size and time for current region */ + status = Cy_SMIF_MemLocateHybridRegion(memConfig, &hybrInfo, address); + if (CY_SMIF_SUCCESS == status) { - /* Wait until the erase operation is completed or a timeout occurs. eraseTime is in milliseconds */ - status = Cy_SMIF_MemIsReady(base, memConfig, - (memConfig->deviceCfg->eraseTime * ONE_MILLI_IN_MICRO), context); + maxEraseTime = hybrInfo->eraseTime; + eraseSectorSize = hybrInfo->eraseSize; + hybridRegionStart = hybrInfo->regionAddress; + eraseEnd = (hybrInfo->sectorsCount * eraseSectorSize) + hybridRegionStart; + if(endAddress < eraseEnd) + { + eraseEnd = endAddress; + } + } + else + { + eraseEnd = endAddress; + } - /* Recalculate the next sector address offset */ - address += chunk; - length -= chunk; + while (address < eraseEnd) + { + /* The Write Enable bit may be cleared by the memory after every successful + * operation of write/erase operations. Therefore, it must be set for + * every loop. + */ + status = Cy_SMIF_MemCmdWriteEnable(base, memConfig, context); + if(CY_SMIF_SUCCESS == status) + { + ValueToByteArray(address, &addrArray[0], 0UL, device->numOfAddrBytes); + + /* Send the command to erase one sector */ + status = Cy_SMIF_MemCmdSectorErase(base, (cy_stc_smif_mem_config_t* )memConfig, + (const uint8_t *)addrArray, context); + if(CY_SMIF_SUCCESS == status) + { + /* Wait until the erase operation is completed or a timeout occurs. + * Note: eraseTime is in milliseconds */ + status = Cy_SMIF_MemIsReady(base, memConfig, (maxEraseTime * ONE_MILLI_IN_MICRO), context); + + /* Recalculate the next sector address offset */ + address += eraseSectorSize; + length -= eraseSectorSize; + } + } + + if(CY_SMIF_SUCCESS != status) + { + break; + } } } - - if(CY_SMIF_SUCCESS != status) - { - break; - } } } @@ -3167,8 +3822,10 @@ cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_conf * The memory device configuration. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c index 73688148e5..e1c6b4de03 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_sysclk.c -* \version 1.50 +* \version 1.60 * * Provides an API implementation of the sysclk driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -63,6 +63,25 @@ void Cy_SysClk_ExtClkSetFrequency(uint32_t freq) extFreq = freq; } } + + +/******************************************************************************* +* Function Name: Cy_SysClk_ExtClkGetFrequency +****************************************************************************//** +* +* Returns the frequency of the External Clock Source (EXTCLK) from the +* internal storage. +* +* \return The frequency of the External Clock Source. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ExtClkSetFrequency +* +*******************************************************************************/ +uint32_t Cy_SysClk_ExtClkGetFrequency(void) +{ + return (extFreq); +} /** \} group_sysclk_ext_funcs */ @@ -280,6 +299,27 @@ cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus) return (retVal); } + + +/******************************************************************************* +* Function Name: Cy_SysClk_EcoGetFrequency +****************************************************************************//** +* +* Returns the frequency of the external crystal oscillator (ECO). +* +* \return The frequency of the ECO. +* +* \note If the ECO is not enabled or stable - a zero is returned. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoEnable +* +*******************************************************************************/ +uint32_t Cy_SysClk_EcoGetFrequency(void) +{ + return ((CY_SYSCLK_ECOSTAT_STABLE == Cy_SysClk_EcoGetStatus()) ? ecoFreq : 0UL); +} + /** \} group_sysclk_eco_funcs */ @@ -372,6 +412,131 @@ cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath) } return (retVal); } + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPathMuxGetFrequency +****************************************************************************//** +* +* Returns the output frequency of the clock path mux. +* +* \return The output frequency of the path mux. +* +* \note If the return value equals zero, that means either: +* - the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or +* - the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.). +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource +* +*******************************************************************************/ +uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath) +{ + CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); + + uint32_t freq = 0UL; /* The path mux output frequency in Hz, 0 = an unknown frequency */ + + /* Get the frequency of the source, i.e., the path mux input */ + switch(Cy_SysClk_ClkPathGetSource(clkPath)) + { + case CY_SYSCLK_CLKPATH_IN_IMO: /* The IMO frequency is fixed at 8 MHz */ + freq = CY_SYSCLK_IMO_FREQ; + break; + + case CY_SYSCLK_CLKPATH_IN_EXT: + freq = Cy_SysClk_ExtClkGetFrequency(); + break; + + case CY_SYSCLK_CLKPATH_IN_ECO: + freq = Cy_SysClk_EcoGetFrequency(); + break; + + case CY_SYSCLK_CLKPATH_IN_ALTHF: + freq = Cy_SysClk_AltHfGetFrequency(); + break; + + case CY_SYSCLK_CLKPATH_IN_ILO: + freq = (0UL != (SRSS_CLK_ILO_CONFIG & SRSS_CLK_ILO_CONFIG_ENABLE_Msk)) ? CY_SYSCLK_ILO_FREQ : 0UL; + break; + + case CY_SYSCLK_CLKPATH_IN_WCO: + freq = (Cy_SysClk_WcoOkay()) ? CY_SYSCLK_WCO_FREQ : 0UL; + break; + + case CY_SYSCLK_CLKPATH_IN_PILO: + freq = (0UL != (SRSS_CLK_PILO_CONFIG & SRSS_CLK_PILO_CONFIG_PILO_EN_Msk)) ? CY_SYSCLK_PILO_FREQ : 0UL; + break; + + case CY_SYSCLK_CLKPATH_IN_ALTLF: + freq = Cy_SysClk_AltLfGetFrequency(); + break; + + default: + /* Don't know the frequency of dsi_out, leave freq = 0UL */ + break; + } + + return (freq); +} + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPathGetFrequency +****************************************************************************//** +* +* Returns the output frequency of the clock path mux. +* +* \return The output frequency of the path mux. +* +* \note If the return value equals zero, that means either: +* - the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or +* - the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.). +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllEnable +* +*******************************************************************************/ +uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath) +{ + CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); + + uint32_t freq = Cy_SysClk_ClkPathMuxGetFrequency(clkPath); + uint32_t fDiv = 0UL; /* FLL/PLL multiplier/feedback divider */ + uint32_t rDiv = 0UL; /* FLL/PLL reference divider */ + uint32_t oDiv = 0UL; /* FLL/PLL output divider */ + bool enabled = false; /* FLL or PLL enable status; n/a for direct */ + + if (clkPath == (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */ + { + cy_stc_fll_manual_config_t fllCfg = {0UL,0U,CY_SYSCLK_FLL_CCO_RANGE0,false,0U,0U,0U,0U,CY_SYSCLK_FLLPLL_OUTPUT_AUTO,0U}; + Cy_SysClk_FllGetConfiguration(&fllCfg); + enabled = (Cy_SysClk_FllIsEnabled()) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != fllCfg.outputMode); + fDiv = fllCfg.fllMult; + rDiv = fllCfg.refDiv; + oDiv = (fllCfg.enableOutputDiv) ? 2UL : 1UL; + } + else if (clkPath <= CY_SRSS_NUM_PLL) /* PLL? (always path 1...N)*/ + { + cy_stc_pll_manual_config_t pllcfg = {0U,0U,0U,false,CY_SYSCLK_FLLPLL_OUTPUT_AUTO}; + (void)Cy_SysClk_PllGetConfiguration(clkPath, &pllcfg); + enabled = (Cy_SysClk_PllIsEnabled(clkPath)) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != pllcfg.outputMode); + fDiv = pllcfg.feedbackDiv; + rDiv = pllcfg.referenceDiv; + oDiv = pllcfg.outputDiv; + } + else + { + /* Do nothing with the path mux frequency */ + } + + if (enabled) /* If FLL or PLL is enabled and not bypassed */ + { + freq = (uint32_t)CY_SYSLIB_DIV_ROUND(((uint64_t)freq * (uint64_t)fDiv), + ((uint64_t)rDiv * (uint64_t)oDiv)); + } + + return (freq); +} /** \} group_sysclk_path_src_funcs */ @@ -1816,82 +1981,9 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf) { /* variables holding intermediate clock frequencies, dividers and FLL/PLL settings */ - bool enabled = false; /* FLL or PLL enable status; n/a for direct */ - uint32_t freq = 0UL; /* path (FLL, PLL, or direct) frequency, in Hz, 0 = unknown frequency */ - uint32_t fDiv = 0UL; /* FLL/PLL multiplier/feedback divider */ - uint32_t rDiv = 0UL; /* FLL/PLL reference divider */ - uint32_t oDiv = 0UL; /* FLL/PLL output divider */ uint32_t pDiv = 1UL << (uint32_t)Cy_SysClk_ClkHfGetDivider(clkHf); /* root prescaler (1/2/4/8) */ uint32_t path = (uint32_t) Cy_SysClk_ClkHfGetSource(clkHf); /* path input for root 0 (clkHf[0]) */ - cy_en_clkpath_in_sources_t source = Cy_SysClk_ClkPathGetSource((uint32_t)path); /* source input for path (FLL, PLL, or direct) */ - - /* get the frequency of the source, i.e., the path mux input */ - switch(source) - { - case CY_SYSCLK_CLKPATH_IN_IMO: /* IMO frequency is fixed at 8 MHz */ - freq = CY_SYSCLK_IMO_FREQ; - break; - - case CY_SYSCLK_CLKPATH_IN_EXT: - freq = extFreq; - break; - - case CY_SYSCLK_CLKPATH_IN_ECO: - freq = (CY_SYSCLK_ECOSTAT_STABLE == Cy_SysClk_EcoGetStatus()) ? ecoFreq : 0UL; - break; - - #if defined(CY_IP_MXBLESS) - case CY_SYSCLK_CLKPATH_IN_ALTHF: - freq = cy_BleEcoClockFreqHz; - break; - #endif /* CY_IP_MXBLESS */ - - case CY_SYSCLK_CLKPATH_IN_ILO: - freq = (0UL != (SRSS_CLK_ILO_CONFIG & SRSS_CLK_ILO_CONFIG_ENABLE_Msk)) ? CY_SYSCLK_ILO_FREQ : 0UL; - break; - - case CY_SYSCLK_CLKPATH_IN_WCO: - freq = (Cy_SysClk_WcoOkay()) ? CY_SYSCLK_WCO_FREQ : 0UL; - break; - - case CY_SYSCLK_CLKPATH_IN_PILO: - freq = (0UL != (SRSS_CLK_PILO_CONFIG & SRSS_CLK_PILO_CONFIG_PILO_EN_Msk)) ? CY_SYSCLK_PILO_FREQ : 0UL; - break; - - default: - /* don't know the frequency of dsi_out, or clk_altlf */ - freq = 0UL; /* unknown frequency */ - break; - } - - if (path == (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */ - { - cy_stc_fll_manual_config_t fllCfg = {0UL,0U,CY_SYSCLK_FLL_CCO_RANGE0,false,0U,0U,0U,0U,CY_SYSCLK_FLLPLL_OUTPUT_AUTO,0U}; - Cy_SysClk_FllGetConfiguration(&fllCfg); - enabled = (Cy_SysClk_FllIsEnabled()) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != fllCfg.outputMode); - fDiv = fllCfg.fllMult; - rDiv = fllCfg.refDiv; - oDiv = (fllCfg.enableOutputDiv) ? 2UL : 1UL; - } - else if (path <= CY_SRSS_NUM_PLL) /* PLL? (always path 1...N)*/ - { - cy_stc_pll_manual_config_t pllcfg = {0U,0U,0U,false,CY_SYSCLK_FLLPLL_OUTPUT_AUTO}; - (void)Cy_SysClk_PllGetConfiguration(path, &pllcfg); - enabled = (Cy_SysClk_PllIsEnabled(path)) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != pllcfg.outputMode); - fDiv = pllcfg.feedbackDiv; - rDiv = pllcfg.referenceDiv; - oDiv = pllcfg.outputDiv; - } - else - { - /* Direct select path */ - } - - if (enabled) /* if FLL or PLL enabled and not bypassed */ - { - freq = (uint32_t)CY_SYSLIB_DIV_ROUND(((uint64_t)freq * (uint64_t)fDiv), - ((uint64_t)rDiv * (uint64_t)oDiv)); - } + uint32_t freq = Cy_SysClk_ClkPathGetFrequency(path); /* Divide the path input frequency down and return the result */ return (CY_SYSLIB_DIV_ROUND(freq, pDiv)); @@ -1900,7 +1992,6 @@ uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf) /** \} group_sysclk_clk_hf_funcs */ - /* ========================================================================== */ /* ===================== clk_peripherals SECTION ====================== */ /* ========================================================================== */ @@ -1971,4 +2062,63 @@ uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_ /** \} group_sysclk_clk_peripheral_funcs */ +/** +* \addtogroup group_sysclk_clk_timer_funcs +* \{ +*/ + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkTimerGetFrequency +****************************************************************************//** +* +* Reports the frequency of the timer clock (clk_timer). +* \note If the the timer clock is not enabled - a zero frequency is reported. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerEnable +* +*******************************************************************************/ +uint32_t Cy_SysClk_ClkTimerGetFrequency(void) +{ + uint32_t freq = 0UL; + + if (Cy_SysClk_ClkTimerIsEnabled()) + { + freq = Cy_SysClk_ClkHfGetFrequency(0UL); + + switch (Cy_SysClk_ClkTimerGetSource()) + { + case CY_SYSCLK_CLKTIMER_IN_IMO: + freq = CY_SYSCLK_IMO_FREQ; + break; + + case CY_SYSCLK_CLKTIMER_IN_HF0_NODIV: + break; + + case CY_SYSCLK_CLKTIMER_IN_HF0_DIV2: + freq /= 2UL; + break; + + case CY_SYSCLK_CLKTIMER_IN_HF0_DIV4: + freq /= 4UL; + break; + + case CY_SYSCLK_CLKTIMER_IN_HF0_DIV8: + freq /= 8UL; + break; + + default: + freq = 0UL; + break; + } + } + + /* Divide the input frequency down and return the result */ + return (CY_SYSLIB_DIV_ROUND(freq, 1UL + (uint32_t)Cy_SysClk_ClkTimerGetDivider())); +} + +/** \} group_sysclk_clk_timer_funcs */ + + /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c index f2a231fd48..3121c7665b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib.c -* \version 2.50 +* \version 2.50.1 * * Description: * Provides system API implementation for the SysLib driver. * ******************************************************************************** -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c index 828d53fcfc..a2d7434da0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syspm.c -* \version 4.50 +* \version 5.0 * * This driver provides the source code for API power management. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -189,6 +189,9 @@ typedef void (*cy_cb_syspm_deep_sleep_t)(cy_en_syspm_waitfor_t waitFor, bool *wa /* Mask for the RAM read assist bits */ #define CPUSS_TRIM_RAM_CTL_RA_MASK ((uint32_t) 0x3U << 8U) +/* Mask for the RAM write check bits */ +#define CPUSS_TRIM_RAM_CTL_WC_MASK (0x3UL << 10U) + /* The define for SROM opcode to set the flash voltage bit */ #define FLASH_VOLTAGE_BIT_ULP_OPCODE (0x0C000003U) @@ -1057,7 +1060,7 @@ he LP mode * are registered. * * \return -* - CY_SYSPM_SUCCESS - Entered the system LP mode. +* - CY_SYSPM_SUCCESS - Entered the system LP mode or the device is already in LP mode. * - CY_SYSPM_INVALID_STATE - The system LP mode was not set. The system LP mode * was not set because the protection context value is higher than zero * (PC > 0) or the device revision does not support modifying registers @@ -1199,7 +1202,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void) * are registered. * * \return -* - CY_SYSPM_SUCCESS - Entered system ULP mode. +* - CY_SYSPM_SUCCESS - Entered the system ULP mode or the device is already in ULP mode. * - CY_SYSPM_INVALID_STATE - System ULP mode was not set. The ULP mode was not * set because the protection context value is higher than zero (PC > 0) or the * device revision does not support modifying registers (to enter system @@ -1687,7 +1690,8 @@ void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource) * See \ref cy_en_syspm_buck_voltage1_t. * * \return -* - CY_SYSPM_SUCCESS - The voltage is set. +* - CY_SYSPM_SUCCESS - The voltage is set as requested. +* (There is no change if the new voltage is the same as the previous voltage.) * - CY_SYSPM_INVALID_STATE - The voltage was not set. The voltage cannot be set * because the protection context value is higher than zero (PC > 0) or the * device revision does not support modifying registers via syscall. @@ -3143,7 +3147,9 @@ static void SetWriteAssistTrimLp(void) *******************************************************************************/ static bool IsVoltageChangePossible(void) { - bool retVal = true; + bool retVal = false; + uint32_t trimRamCheckVal = (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK); + if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) { @@ -3151,6 +3157,13 @@ static bool IsVoltageChangePossible(void) retVal = ((Cy_SysLib_GetDeviceRevision() > SYSPM_DEVICE_PSOC6ABLE2_REV_0B) || (curProtContext == 0U)); } + else + { + CPUSS_TRIM_RAM_CTL &= ~CPUSS_TRIM_RAM_CTL_WC_MASK; + CPUSS_TRIM_RAM_CTL |= ((~trimRamCheckVal) & CPUSS_TRIM_RAM_CTL_WC_MASK); + + retVal = (trimRamCheckVal != (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK)); + } return retVal; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/.cymigration b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/.cymigration index af97141caa..e7a0834a72 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/.cymigration +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/.cymigration @@ -61,7 +61,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/canfd-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/canfd-1.0.cypersonality index f0350f9bae..ef801e10d0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/canfd-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/canfd-1.0.cypersonality @@ -3,14 +3,14 @@ @@ -378,7 +381,7 @@ treated."> ((sfid2_10_9_SidFilter$idx << 9U) | sfid2_5_0_SidFilter$idx)}`U, \ .sfid1 = `${sfid1_SidFilter$idx}`U, \ .sfec = `${sfecSidFilter$idx}`, \ - .sft = `${sftSidFilter$idx}`, \ + .sft = `${sftSidFilterVal$idx}`, \ }" /> ((sfid2_10_9_SidFilter$idx << 9U) | sfid2_5_0_SidFilter$idx)}`U" /> - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality index b6af7770d7..766a22504e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality @@ -3,14 +3,14 @@ + @@ -296,8 +297,9 @@ - - + + + @@ -335,7 +337,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/pdm_pcm-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/pdm_pcm-1.0.cypersonality index 99503b3fd4..754a0f6fa0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/pdm_pcm-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/pdm_pcm-1.0.cypersonality @@ -3,14 +3,14 @@ + @@ -192,8 +193,9 @@ - - + + + @@ -218,7 +220,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/seglcd-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/seglcd-1.1.cypersonality index 2b6285774e..8c5c631cca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/seglcd-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/seglcd-1.1.cypersonality @@ -3,14 +3,14 @@ - - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/smif-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/smif-1.1.cypersonality index 4eacb689b1..9079ed46d1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/smif-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/smif-1.1.cypersonality @@ -3,14 +3,14 @@ - + @@ -70,7 +70,7 @@ - + @@ -78,7 +78,7 @@ - + @@ -86,7 +86,7 @@ - + @@ -94,7 +94,7 @@ - + @@ -102,7 +102,7 @@ - + @@ -110,7 +110,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -128,7 +128,7 @@ - + @@ -136,7 +136,7 @@ - + @@ -144,7 +144,7 @@ - + @@ -152,7 +152,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/dma-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/dma-1.0.cypersonality index 14847f18b3..4014dd92ec 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/dma-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/dma-1.0.cypersonality @@ -3,14 +3,14 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality index 4e4b6e146c..66c39e4696 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality @@ -343,6 +343,7 @@ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision new file mode 100644 index 0000000000..b5f9103268 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision @@ -0,0 +1 @@ +CG \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/MXS40.revision b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/MXS40.revision new file mode 100644 index 0000000000..3cafba36f1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/MXS40.revision @@ -0,0 +1 @@ +258628 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/base/view.xml new file mode 100644 index 0000000000..3900a174c7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/base/view.xml @@ -0,0 +1,16 @@ + + + 0x00000000 + 0x000 + 0 + 0 + CortexM4 + Cypress + 0 + 1310720 + 251-WLCSP + 251 + 3200 + 4400 + The CYW43012C0WKWBG device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/info.xml new file mode 100644 index 0000000000..9203713583 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/info.xml @@ -0,0 +1,6 @@ + + + CYW43012C0WKWBG + The CYW43012C0WKWBG devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/presentation new file mode 100644 index 0000000000..c4e820824c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/presentation @@ -0,0 +1,2 @@ +Connectivity +43012 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml new file mode 100644 index 0000000000..6edfd810af --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/presentation index 3d4d778bec..c4e820824c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/presentation @@ -1,2 +1,2 @@ -Connectivity -43012 +Connectivity +43012 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/presentation index 3d4d778bec..c4e820824c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/presentation @@ -1,2 +1,2 @@ -Connectivity -43012 +Connectivity +43012 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/presentation index 3d4d778bec..c4e820824c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/presentation @@ -1,2 +1,2 @@ -Connectivity -43012 +Connectivity +43012 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/presentation index 5ec34f1652..8d1f11ae89 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/presentation @@ -1,2 +1,2 @@ -Connectivity -43438 +Connectivity +43438 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/presentation index ffe8789035..2dfac14f37 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/presentation @@ -1,2 +1,2 @@ -Connectivity -4343W +Connectivity +4343W diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/presentation index ffe8789035..2dfac14f37 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/presentation @@ -1,2 +1,2 @@ -Connectivity -4343W +Connectivity +4343W diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/base/view.xml new file mode 100644 index 0000000000..1c0dee3462 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/base/view.xml @@ -0,0 +1,16 @@ + + + 0xFFFF + 0xFF + F + F + CortexM0p,CortexM4 + Cypress + 262144 + 131072 + 68-QFN + 68 + 1700 + 3600 + The PSoC6A256K device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/info.xml new file mode 100644 index 0000000000..bd1a5977c8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/info.xml @@ -0,0 +1,6 @@ + + + PSoC6A256K + The PSoC6A256K devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/info.xml new file mode 100644 index 0000000000..9b82c14cd4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/info.xml @@ -0,0 +1,5 @@ + + + PSoC6A256K + The PSoC6A256K devices + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml index 9e4a8b3ad5..a4d7d4e022 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml @@ -1,9 +1,9 @@  - 0xE430 + 0xE470 0x102 1 - 1 + 2 CortexM0p,CortexM4 Cypress 1900544 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/presentation index 6a8bdde3e3..6cd221015f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 64 +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml index 9b8bed892c..d3c5001c8e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml @@ -49,7 +49,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/base/view.xml new file mode 100644 index 0000000000..229a90da03 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/base/view.xml @@ -0,0 +1,16 @@ + + + 0xE4A0 + 0x102 + 1 + 2 + CortexM0p,CortexM4 + Cypress + 1900544 + 1048576 + 124-BGA + 124 + 1700 + 3600 + The CYS0644ABZI-S2D44 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/info.xml new file mode 100644 index 0000000000..a89889b763 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/info.xml @@ -0,0 +1,6 @@ + + + CYS0644ABZI-S2D44 + The CYS0644ABZI-S2D44 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/presentation new file mode 100644 index 0000000000..6cd221015f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml new file mode 100644 index 0000000000..1ca4a73bec --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/clocks.cysem b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/clocks.cysem index 44caf60459..25ec63fbdb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/clocks.cysem +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/clocks.cysem @@ -468,7 +468,7 @@ 2 - Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. + Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock runs in hibernate power mode. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml index 3770540593..f99a653de3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml @@ -33,7 +33,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml index a3fb55c953..9201578557 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml @@ -33,7 +33,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml index 08aaff161b..2e28ce6934 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml @@ -33,7 +33,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/presentation index 6a8bdde3e3..6cd221015f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 64 +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem index f160ae144a..b8d28ed2dc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem @@ -433,7 +433,7 @@ 2 - Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. + Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock runs in hibernate power mode. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/presentation index 976b687d88..23e88077a4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 60 +PSoC 6 +PSoC 60 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/presentation index 976b687d88..23e88077a4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 60 +PSoC 6 +PSoC 60 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/presentation index 7e90374eb1..5a9f775be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/presentation index 7e90374eb1..5a9f775be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/presentation index 7e90374eb1..5a9f775be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/presentation index 7e90374eb1..5a9f775be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/presentation index 7e90374eb1..5a9f775be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/presentation index 7e90374eb1..5a9f775be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/presentation index 7e90374eb1..5a9f775be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/presentation index 7e90374eb1..5a9f775be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/presentation index 7e90374eb1..5a9f775be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/presentation index 7e90374eb1..5a9f775be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/presentation index 7e90374eb1..5a9f775be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/presentation index 7e90374eb1..5a9f775be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/presentation index 7e90374eb1..5a9f775be9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/presentation index 2d84ef27e9..33e940a6d9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/presentation index 6a8bdde3e3..6cd221015f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 64 +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/presentation index 6a8bdde3e3..6cd221015f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 64 +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/presentation index 6a8bdde3e3..6cd221015f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 64 +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/presentation index d3b5d7b9fa..1bcadca24c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cysem b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cysem index fa25ded8e9..19d1b2f052 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cysem +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cysem @@ -1,5 +1,5 @@  - + @@ -1082,7 +1082,7 @@ SYS_TICK 2 - Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. + Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock runs in hibernate power mode. @@ -1628,8 +1628,8 @@ SYS_TICK - + @@ -1866,17 +1866,17 @@ SYS_TICK - + - - - + + - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cyvis b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cyvis index 709240dc82..a0265f82a9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cyvis +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cyvis @@ -1,5 +1,5 @@  - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxprofile_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxprofile_v1.cydata index 6b0476263f4494680beaa433b6983abef9266266..9f3fb6a694b5b06aecd2dd8b8c02f7cd29a2e18f 100644 GIT binary patch delta 281 zcmV+!0p|Xb1d{}i9e=HoQA@)x5Xay9DZ;(Gx;K$_W1vVuwBYs}N}8@=Z4&NowfXk8 zc5I-sq4V+XxZnSmBgwLF8_{Vb<7^7^*)0fdl`Dk1A}c*vfz_3C+a#Bpnk z$zJl!8pOLPN8KSb{?2e}Cy&zCpp0dWxc7Vx^SW7I;xJ0$0?%SD+k8@-|1IR_^Jp~E fJCfS|$F(WY9}a0rJpI~5^Z_+0w^`-_lOX}>){K#C delta 270 zcmV+p0rCEm1d{}i9e<^g!D_=W42JJ{3ZeU&^)^PFQrH-Qu?3c%LvWnNG_j4WX7SrE zSxO5Vw2U1kq3{0$N;YHP!Jx=%YXq)W_Xx^JTWhlyc;x2p0XJ!sY)Q6R4jh~k=*Tv@ zQwX*8uB$?6s(xxe8%6s7`7));*j3yL{0N>^kKikRTIk0!X@72BED$EEpSAG}x8|7a zE#DOgpSqrPr_lH}!^%T>mi`Y)8&*U|$Ja3LyW$pysq|dYRm^RhZ;Ew)g(UIv7ishb U5_}x8NCE%=0FyKU-;+QA83YxBWB>pF diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1-power.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1-power.cydata deleted file mode 100644 index a9be78bedbeaf80ba341cb45079b9769d4aa6e41..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 531 zcmWFt_IGv;a&-*x4{~t~adh+aagF&@QIuL-%)r7h_mX$^VFMn92i5hhA8S7|+4e5E zke9>qjblyf@ds9Ng1zz)r(WOJS8Q}j==q`%`70&y`0oX$Op>ou&nP(uut30GMiq2LJ#7 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1.cydata index 4c796d89b362855aeb5ef81ea1ac17fe10083624..6546bc53b448d2d736bb5f8310436d0e5bcec8a8 100644 GIT binary patch delta 1167 zcmV;A1aSMU5%&?0AAjF(;y4g~zWx=n(dyJn3zY6Yta>dgO1VAMQV`JXN!2Pfjwx1? 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This version is built with PSoC 6 Peripheral Driver Library (PDL) 1.4.1 --- .../COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c | 12752 ++++++++-------- .../psoc6_01_cm0p_crypto.c | 1300 +- .../psoc6_02_cm0p_crypto.c | 1077 +- .../psoc6_03_cm0p_crypto.c | 1077 +- .../psoc6_01_cm0p_sleep.c | 585 +- .../psoc6_02_cm0p_sleep.c | 561 +- .../psoc6_03_cm0p_sleep.c | 561 +- .../TARGET_PSOC6/psoc6cm0p/README.md | 5 + .../TARGET_PSOC6/psoc6cm0p/version.xml | 2 +- 9 files changed, 8975 insertions(+), 8945 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c index e1f4b05da4..0e0db96a84 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c @@ -41,45 +41,45 @@ const uint8_t cy_m0p_image[] = { 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0x60u, 0x05u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x3cu, 0x53u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xb4u, 0x53u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x64u, 0x05u, 0x00u, 0x08u, 0x3cu, 0x53u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0x64u, 0x05u, 0x00u, 0x08u, 0xb4u, 0x53u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x02u, 0xf0u, 0x6du, 0xfcu, 0x02u, 0xf0u, 0xf9u, 0xfbu, 0xfeu, 0xe7u, - 0xb0u, 0xa1u, 0x01u, 0x10u, 0xc8u, 0xa1u, 0x01u, 0x10u, 0x60u, 0x05u, 0x00u, 0x08u, 0xc8u, 0x12u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x02u, 0xf0u, 0xa9u, 0xfcu, 0x02u, 0xf0u, 0x35u, 0xfcu, 0xfeu, 0xe7u, + 0x28u, 0xa2u, 0x01u, 0x10u, 0x40u, 0xa2u, 0x01u, 0x10u, 0x60u, 0x05u, 0x00u, 0x08u, 0xccu, 0x12u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x01u, 0xf0u, 0xfbu, 0xfeu, 0xfeu, 0xe7u, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x5fu, 0xf8u, 0x10u, 0xbdu, + 0x04u, 0x30u, 0x01u, 0xf0u, 0x11u, 0xffu, 0xfeu, 0xe7u, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x5fu, 0xf8u, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x2bu, 0xfcu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x00u, 0xf0u, 0xbfu, 0xf8u, 0x10u, 0xbdu, - 0x10u, 0xb5u, 0x06u, 0xf0u, 0x6du, 0xffu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x0du, 0xf0u, 0x41u, 0xfdu, 0x10u, 0xbdu, - 0x10u, 0xb5u, 0x06u, 0xf0u, 0x7du, 0xffu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x05u, 0xf0u, 0x97u, 0xf9u, 0x10u, 0xbdu, + 0x10u, 0xb5u, 0x06u, 0xf0u, 0xa9u, 0xffu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x0du, 0xf0u, 0x7du, 0xfdu, 0x10u, 0xbdu, + 0x10u, 0xb5u, 0x06u, 0xf0u, 0xb9u, 0xffu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x05u, 0xf0u, 0xd3u, 0xf9u, 0x10u, 0xbdu, 0xf8u, 0xb5u, 0x0fu, 0x00u, 0x01u, 0x29u, 0x03u, 0xd0u, 0x08u, 0x29u, 0x34u, 0xd0u, 0x1cu, 0x48u, 0x17u, 0xe0u, 0x03u, 0x20u, 0x01u, 0xf0u, 0xb9u, 0xfbu, 0x1bu, 0x4bu, 0x98u, 0x42u, 0xf7u, 0xd0u, 0x00u, 0xf0u, 0x3cu, 0xfbu, 0x01u, 0x28u, 0xf3u, 0xd0u, 0x02u, 0x20u, 0xffu, 0xf7u, 0xe7u, 0xffu, 0x06u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xffu, - 0x15u, 0x4du, 0x28u, 0x60u, 0x05u, 0xf0u, 0x7eu, 0xf9u, 0x04u, 0x00u, 0x06u, 0x28u, 0x01u, 0xd1u, 0x00u, 0x20u, + 0x15u, 0x4du, 0x28u, 0x60u, 0x05u, 0xf0u, 0xbau, 0xf9u, 0x04u, 0x00u, 0x06u, 0x28u, 0x01u, 0xd1u, 0x00u, 0x20u, 0xf8u, 0xbdu, 0x02u, 0x2eu, 0x0du, 0xd1u, 0x03u, 0x3cu, 0xb4u, 0x43u, 0x30u, 0x00u, 0xe4u, 0xb2u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x00u, 0x2cu, 0x01u, 0xd1u, 0x00u, 0x28u, 0xf1u, 0xd0u, 0x28u, 0x68u, 0xffu, 0xf7u, 0x71u, 0xffu, 0xd4u, 0xe7u, 0x38u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu, 0x02u, 0x2cu, 0xf6u, 0xd0u, 0x00u, 0x28u, 0xf4u, 0xd1u, - 0x02u, 0xf0u, 0x92u, 0xf8u, 0xf1u, 0xe7u, 0x04u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x62u, 0xffu, 0xdeu, 0xe7u, + 0x02u, 0xf0u, 0xdau, 0xf8u, 0xf1u, 0xe7u, 0x04u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x62u, 0xffu, 0xdeu, 0xe7u, 0xffu, 0x00u, 0x42u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u, 0x88u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x28u, 0x05u, 0xd0u, 0x04u, 0x4bu, 0x18u, 0x60u, 0x00u, 0xf0u, 0x0bu, 0xfcu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x84u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x16u, 0x00u, 0x70u, 0xb5u, 0x28u, 0x4du, 0x94u, 0xb0u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x48u, 0xd0u, 0x01u, 0xacu, 0x4cu, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, - 0x04u, 0xf0u, 0xbeu, 0xf9u, 0x0au, 0x21u, 0x33u, 0x68u, 0x69u, 0x44u, 0x9au, 0x8au, 0xa2u, 0x81u, 0x5au, 0x89u, + 0x04u, 0xf0u, 0xfau, 0xf9u, 0x0au, 0x21u, 0x33u, 0x68u, 0x69u, 0x44u, 0x9au, 0x8au, 0xa2u, 0x81u, 0x5au, 0x89u, 0x22u, 0x83u, 0x9au, 0x89u, 0x62u, 0x83u, 0x1fu, 0x4au, 0xa2u, 0x83u, 0x1au, 0x89u, 0xcau, 0x87u, 0x59u, 0x1cu, 0xc8u, 0x7fu, 0x13u, 0xa9u, 0x08u, 0x70u, 0x69u, 0x46u, 0x98u, 0x7fu, 0x05u, 0x31u, 0xc8u, 0x77u, 0x69u, 0x46u, 0xd8u, 0x7fu, 0x06u, 0x31u, 0xc8u, 0x77u, 0x5bu, 0x7fu, 0xe3u, 0x77u, 0xd3u, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, - 0xf5u, 0xf8u, 0x2bu, 0x68u, 0x1bu, 0x68u, 0x1bu, 0x89u, 0x9bu, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, 0xf6u, 0xf8u, - 0x2bu, 0x68u, 0x1bu, 0x68u, 0x1bu, 0x89u, 0x1bu, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, 0xebu, 0xf8u, 0x07u, 0xa8u, - 0x05u, 0xf0u, 0x38u, 0xf9u, 0x00u, 0x28u, 0x0eu, 0xd1u, 0x2bu, 0x68u, 0x1bu, 0x68u, 0x9au, 0x69u, 0x59u, 0x68u, - 0x62u, 0x60u, 0x00u, 0x29u, 0x04u, 0xd0u, 0x26u, 0x30u, 0x22u, 0x22u, 0x68u, 0x44u, 0x04u, 0xf0u, 0x77u, 0xf9u, - 0x20u, 0x00u, 0x05u, 0xf0u, 0xfbu, 0xf8u, 0x14u, 0xb0u, 0x70u, 0xbdu, 0x03u, 0x48u, 0xfbu, 0xe7u, 0xc0u, 0x46u, + 0x31u, 0xf9u, 0x2bu, 0x68u, 0x1bu, 0x68u, 0x1bu, 0x89u, 0x9bu, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, 0x32u, 0xf9u, + 0x2bu, 0x68u, 0x1bu, 0x68u, 0x1bu, 0x89u, 0x1bu, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, 0x27u, 0xf9u, 0x07u, 0xa8u, + 0x05u, 0xf0u, 0x74u, 0xf9u, 0x00u, 0x28u, 0x0eu, 0xd1u, 0x2bu, 0x68u, 0x1bu, 0x68u, 0x9au, 0x69u, 0x59u, 0x68u, + 0x62u, 0x60u, 0x00u, 0x29u, 0x04u, 0xd0u, 0x26u, 0x30u, 0x22u, 0x22u, 0x68u, 0x44u, 0x04u, 0xf0u, 0xb3u, 0xf9u, + 0x20u, 0x00u, 0x05u, 0xf0u, 0x37u, 0xf9u, 0x14u, 0xb0u, 0x70u, 0xbdu, 0x03u, 0x48u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x84u, 0x05u, 0x00u, 0x08u, 0x03u, 0x04u, 0x00u, 0x00u, 0xffu, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x02u, 0x48u, - 0x01u, 0xf0u, 0x88u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x52u, 0x4eu, + 0x01u, 0xf0u, 0xd0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x52u, 0x4eu, 0x33u, 0x68u, 0x00u, 0x2bu, 0x7du, 0xd0u, 0x9au, 0x68u, 0x00u, 0x2au, 0x7au, 0xd0u, 0x02u, 0x24u, 0x22u, 0x42u, 0x6au, 0xd1u, 0x01u, 0x21u, 0x4du, 0x4du, 0x4eu, 0x4bu, 0xecu, 0x58u, 0x0cu, 0x40u, 0x04u, 0xd0u, 0x14u, 0x00u, 0x7fu, 0x31u, 0x0cu, 0x40u, 0x00u, 0xd0u, 0x0cu, 0x00u, 0xe9u, 0x58u, 0x89u, 0x07u, 0x03u, 0xd5u, 0x04u, 0x21u, @@ -99,17 +99,17 @@ const uint8_t cy_m0p_image[] = { 0xf2u, 0xd1u, 0x70u, 0xbdu, 0xdcu, 0x60u, 0x64u, 0x24u, 0x17u, 0x4bu, 0x31u, 0x68u, 0x1au, 0x68u, 0x08u, 0x7cu, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x43u, 0x43u, 0x10u, 0x6au, 0xb0u, 0x32u, 0x12u, 0x68u, 0x1bu, 0x18u, 0x9au, 0x18u, 0x12u, 0x68u, 0x00u, 0x2au, 0x06u, 0xdau, 0x00u, 0x2cu, 0xeau, 0xd0u, 0x01u, 0x20u, 0x01u, 0xf0u, - 0x7bu, 0xfdu, 0x01u, 0x3cu, 0xe8u, 0xe7u, 0x00u, 0x2cu, 0xe3u, 0xd0u, 0x80u, 0x22u, 0x49u, 0x7cu, 0x52u, 0x02u, + 0x91u, 0xfdu, 0x01u, 0x3cu, 0xe8u, 0xe7u, 0x00u, 0x2cu, 0xe3u, 0xd0u, 0x80u, 0x22u, 0x49u, 0x7cu, 0x52u, 0x02u, 0x8au, 0x40u, 0x12u, 0x0cu, 0x9au, 0x60u, 0xdcu, 0xe7u, 0x9cu, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x3cu, 0x40u, 0x68u, 0xf0u, 0x01u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0xa8u, 0x10u, 0x00u, 0x00u, 0x34u, 0x11u, 0x00u, 0x00u, - 0x38u, 0x10u, 0x00u, 0x00u, 0x94u, 0x05u, 0x00u, 0x08u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, + 0x38u, 0x10u, 0x00u, 0x00u, 0x94u, 0x05u, 0x00u, 0x08u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0x83u, 0xfeu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x00u, 0x28u, 0x00u, 0xd0u, 0x98u, 0x47u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x8cu, 0x05u, 0x00u, 0x08u, 0x00u, 0x28u, 0x05u, 0xdbu, 0x1fu, 0x23u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x01u, 0x4au, 0x13u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0x10u, 0xb5u, 0x02u, 0x4bu, 0x1bu, 0x68u, 0x98u, 0x47u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x90u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x1eu, 0x08u, 0xd0u, 0x0cu, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x45u, 0x78u, 0x01u, 0x2du, 0x02u, 0xd0u, 0xffu, 0x2du, 0x09u, 0xd0u, 0x70u, 0xbdu, 0x82u, 0x68u, 0x1au, 0x60u, 0x02u, 0xf0u, - 0x4fu, 0xfau, 0xffu, 0xf7u, 0xb3u, 0xfeu, 0x25u, 0x71u, 0xa0u, 0x60u, 0xf5u, 0xe7u, 0x03u, 0x4bu, 0x18u, 0x60u, + 0x8bu, 0xfau, 0xffu, 0xf7u, 0xb3u, 0xfeu, 0x25u, 0x71u, 0xa0u, 0x60u, 0xf5u, 0xe7u, 0x03u, 0x4bu, 0x18u, 0x60u, 0x01u, 0x23u, 0x03u, 0x71u, 0xf0u, 0xe7u, 0xc0u, 0x46u, 0x98u, 0x05u, 0x00u, 0x08u, 0x9cu, 0x05u, 0x00u, 0x08u, 0x1fu, 0x23u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x03u, 0x4au, 0xd3u, 0x67u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0xbfu, 0xf3u, 0x6fu, 0x8fu, 0x70u, 0x47u, 0xc0u, 0x46u, 0x04u, 0xe1u, 0x00u, 0xe0u, 0x10u, 0xb5u, 0x00u, 0xf0u, @@ -125,20 +125,20 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x91u, 0x4cu, 0xa5u, 0x44u, 0x0bu, 0x93u, 0x90u, 0x4bu, 0x08u, 0x90u, 0x0cu, 0x00u, 0x0au, 0x92u, 0x99u, 0x42u, 0x00u, 0xd8u, 0x11u, 0xe1u, 0x80u, 0x22u, 0x8du, 0x4bu, 0xd2u, 0x05u, 0x5du, 0x69u, 0x06u, 0x93u, 0x15u, 0x40u, 0x10u, 0xd0u, 0x07u, 0x22u, 0x5bu, 0x69u, 0x13u, 0x40u, 0x02u, 0x2bu, - 0x22u, 0xd1u, 0x05u, 0x20u, 0x01u, 0xf0u, 0x5cu, 0xffu, 0x87u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, + 0x22u, 0xd1u, 0x05u, 0x20u, 0x01u, 0xf0u, 0xa4u, 0xffu, 0x87u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x01u, 0x23u, 0x04u, 0x93u, 0xdbu, 0x18u, 0x03u, 0x93u, 0x1bu, 0xe0u, 0x06u, 0x9au, 0x83u, 0x4bu, 0xb0u, 0x21u, 0xd3u, 0x58u, 0xe8u, 0x22u, 0x49u, 0x05u, 0xd2u, 0x00u, 0x8au, 0x5cu, 0x1fu, 0x21u, 0x0bu, 0x40u, 0x93u, 0x42u, - 0x36u, 0xd1u, 0x01u, 0x20u, 0x01u, 0xf0u, 0x8cu, 0xffu, 0x7bu, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, + 0x36u, 0xd1u, 0x01u, 0x20u, 0x01u, 0xf0u, 0xceu, 0xffu, 0x7bu, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x00u, 0x23u, 0x04u, 0x93u, 0x05u, 0x33u, 0xe6u, 0xe7u, 0xdbu, 0xb2u, 0x03u, 0x93u, 0x01u, 0x23u, 0x00u, 0x25u, 0x04u, 0x93u, 0xf0u, 0x23u, 0x1bu, 0x06u, 0xe3u, 0x18u, 0x5eu, 0x0au, 0x09u, 0x93u, 0x76u, 0x02u, 0x00u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0xfdu, 0xf8u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x0cu, 0xabu, 0x9bu, 0x1bu, 0x02u, 0x93u, 0x05u, 0x90u, 0x02u, 0x00u, 0x00u, 0x90u, 0x04u, 0x00u, 0x00u, 0x2du, 0x42u, 0xd0u, 0x00u, 0x2au, 0x01u, 0xd0u, - 0x01u, 0xf0u, 0x74u, 0xfcu, 0x00u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0x24u, 0xf9u, 0x00u, 0x28u, 0xf9u, 0xd1u, + 0x01u, 0xf0u, 0x8au, 0xfcu, 0x00u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0x24u, 0xf9u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x00u, 0x2du, 0x00u, 0xd1u, 0x8eu, 0xe0u, 0x66u, 0x48u, 0x8du, 0x23u, 0x9bu, 0x00u, 0x9du, 0x44u, 0xf0u, 0xbdu, 0x01u, 0x23u, 0x04u, 0x93u, 0x04u, 0x33u, 0xb6u, 0xe7u, 0x80u, 0x23u, 0x5bu, 0x05u, 0xf3u, 0x18u, 0x1bu, 0x78u, 0x02u, 0x99u, 0x8bu, 0x55u, 0x4du, 0xe0u, 0x5fu, 0x4bu, 0x9cu, 0x42u, 0x00u, 0xd0u, 0xa9u, 0xe0u, 0x00u, 0xf0u, 0x43u, 0xfeu, 0x5du, 0x4bu, 0x04u, 0x00u, 0x98u, 0x42u, 0xf9u, 0xd0u, 0x00u, 0x28u, 0x62u, 0xd1u, 0xc8u, 0x27u, - 0x0cu, 0xa9u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x3cu, 0xfeu, 0x04u, 0x00u, 0x01u, 0x20u, 0x01u, 0xf0u, 0x3cu, 0xfcu, + 0x0cu, 0xa9u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x3cu, 0xfeu, 0x04u, 0x00u, 0x01u, 0x20u, 0x01u, 0xf0u, 0x52u, 0xfcu, 0xa4u, 0x23u, 0xa4u, 0x22u, 0xdbu, 0x03u, 0x23u, 0x40u, 0xd2u, 0x03u, 0x93u, 0x42u, 0x52u, 0xd1u, 0x01u, 0x3fu, 0x00u, 0x2fu, 0xedu, 0xd1u, 0x51u, 0x4au, 0x02u, 0x9bu, 0x94u, 0x46u, 0x07u, 0x9eu, 0x63u, 0x44u, 0x01u, 0x9au, 0x02u, 0x93u, 0x00u, 0x2cu, 0xbau, 0xd1u, 0x00u, 0x9bu, 0x0au, 0x99u, 0x8bu, 0x42u, 0xb6u, 0xd2u, 0x80u, 0x23u, @@ -148,14 +148,14 @@ const uint8_t cy_m0p_image[] = { 0x1bu, 0x78u, 0x5bu, 0x1au, 0x59u, 0x1eu, 0x8bu, 0x41u, 0xdbu, 0xb2u, 0x01u, 0x93u, 0x00u, 0x9bu, 0x01u, 0x33u, 0x00u, 0x93u, 0x07u, 0x9bu, 0x01u, 0x36u, 0xb3u, 0x42u, 0xdeu, 0xd1u, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x27u, 0xd0u, 0x05u, 0x9bu, 0x37u, 0x4au, 0x9eu, 0x18u, 0x07u, 0x9bu, 0xf6u, 0x18u, 0x0bu, 0x9bu, 0x00u, 0x2bu, 0x19u, 0xd1u, - 0xc8u, 0x27u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x74u, 0xfdu, 0x04u, 0x00u, 0x01u, 0x20u, 0x01u, 0xf0u, 0xecu, 0xfbu, + 0xc8u, 0x27u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x74u, 0xfdu, 0x04u, 0x00u, 0x01u, 0x20u, 0x01u, 0xf0u, 0x02u, 0xfcu, 0xa4u, 0x23u, 0xa4u, 0x22u, 0xdbu, 0x03u, 0x23u, 0x40u, 0xd2u, 0x03u, 0x93u, 0x42u, 0x93u, 0xd1u, 0x01u, 0x3fu, 0x00u, 0x2fu, 0xeeu, 0xd1u, 0x27u, 0x4bu, 0x9cu, 0x42u, 0xacu, 0xd1u, 0x00u, 0xf0u, 0xd5u, 0xfdu, 0x26u, 0x4bu, 0x04u, 0x00u, 0xf8u, 0xe7u, 0x0cu, 0xa9u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x98u, 0xfdu, 0x04u, 0x00u, 0xa1u, 0xe7u, 0x01u, 0x92u, 0x9fu, 0xe7u, 0x06u, 0x9bu, 0x5bu, 0x69u, 0x5bu, 0x00u, 0x09u, 0xd5u, 0x03u, 0x9bu, 0x02u, 0x2bu, - 0x06u, 0xd1u, 0x02u, 0x20u, 0x01u, 0xf0u, 0x7cu, 0xfeu, 0x17u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, + 0x06u, 0xd1u, 0x02u, 0x20u, 0x01u, 0xf0u, 0xc4u, 0xfeu, 0x17u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x06u, 0x9bu, 0x1bu, 0x68u, 0x1bu, 0x02u, 0x09u, 0xd4u, 0x04u, 0x9bu, 0x00u, 0x2bu, 0x06u, 0xd1u, 0x00u, 0x20u, - 0x01u, 0xf0u, 0xb6u, 0xfeu, 0x10u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x00u, 0x2du, 0x00u, 0xd0u, + 0x01u, 0xf0u, 0xf8u, 0xfeu, 0x10u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x00u, 0x2du, 0x00u, 0xd0u, 0x51u, 0xe7u, 0x14u, 0x4bu, 0x9cu, 0x42u, 0x0au, 0xd0u, 0x13u, 0x4bu, 0x9cu, 0x42u, 0x07u, 0xd0u, 0x60u, 0x42u, 0x60u, 0x41u, 0x12u, 0x4cu, 0x40u, 0x42u, 0x12u, 0x4bu, 0x20u, 0x40u, 0xc0u, 0x18u, 0x44u, 0xe7u, 0x11u, 0x48u, 0x42u, 0xe7u, 0x00u, 0x2cu, 0x00u, 0xd0u, 0x6du, 0xe7u, 0x59u, 0xe7u, 0xc0u, 0x46u, 0xccu, 0xfdu, 0xffu, 0xffu, @@ -164,37 +164,37 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0xfeu, 0xffu, 0x0fu, 0x02u, 0x00u, 0x52u, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0xedu, 0xffu, 0xe9u, 0xffu, 0x13u, 0x00u, 0x16u, 0x00u, 0x01u, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x24u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x3au, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, 0x01u, 0xd8u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x20u, 0x00u, 0x01u, 0xf0u, - 0xa1u, 0xf8u, 0x03u, 0x28u, 0x01u, 0xd0u, 0x01u, 0x34u, 0xf0u, 0xe7u, 0x01u, 0x20u, 0xf5u, 0xe7u, 0xc0u, 0x46u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x68u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xecu, 0x00u, 0x00u, 0x08u, + 0xadu, 0xf8u, 0x03u, 0x28u, 0x01u, 0xd0u, 0x01u, 0x34u, 0xf0u, 0xe7u, 0x01u, 0x20u, 0xf5u, 0xe7u, 0xc0u, 0x46u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x68u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x34u, 0x06u, 0x00u, 0x08u, 0xa0u, 0x23u, 0x03u, 0x4au, 0xdbu, 0x00u, 0xd0u, 0x58u, 0x01u, 0x23u, 0x18u, 0x40u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xa0u, 0x23u, 0x03u, 0x4au, 0xdbu, 0x00u, 0xd0u, 0x58u, 0x03u, 0x23u, 0x18u, 0x40u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x02u, 0x4au, 0x03u, 0x4bu, 0xd0u, 0x58u, 0xc0u, 0x0fu, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x01u, 0xf0u, - 0x97u, 0xf9u, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x20u, 0x0du, 0x00u, 0x16u, 0x00u, 0x01u, 0xf0u, + 0x45u, 0xfau, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x20u, 0x0du, 0x00u, 0x16u, 0x00u, 0x01u, 0xf0u, 0x33u, 0xf8u, 0x05u, 0x4bu, 0x98u, 0x42u, 0x05u, 0xd0u, 0x32u, 0x00u, 0x29u, 0x00u, 0x20u, 0x00u, 0x01u, 0xf0u, - 0xd1u, 0xf8u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x01u, 0x88u, 0x00u, 0x03u, 0x00u, 0x4au, 0x00u, + 0x7fu, 0xf9u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x01u, 0x88u, 0x00u, 0x03u, 0x00u, 0x4au, 0x00u, 0xf8u, 0xb5u, 0x0bu, 0x00u, 0x11u, 0x00u, 0xc2u, 0x1au, 0xd5u, 0x17u, 0x54u, 0x19u, 0x6cu, 0x40u, 0x8cu, 0x42u, 0x21u, 0xd3u, 0x12u, 0x4eu, 0x12u, 0x4du, 0x4fu, 0x08u, 0x74u, 0x59u, 0xa4u, 0x05u, 0xa4u, 0x0du, 0x98u, 0x42u, - 0x0fu, 0xd9u, 0xd0u, 0x19u, 0x02u, 0xf0u, 0x20u, 0xf9u, 0x20u, 0x1au, 0xc3u, 0x43u, 0xdbu, 0x17u, 0x18u, 0x40u, + 0x0fu, 0xd9u, 0xd0u, 0x19u, 0x02u, 0xf0u, 0x5cu, 0xf9u, 0x20u, 0x1au, 0xc3u, 0x43u, 0xdbu, 0x17u, 0x18u, 0x40u, 0x73u, 0x59u, 0x82u, 0x05u, 0x9bu, 0x0au, 0x9bu, 0x02u, 0x92u, 0x0du, 0x13u, 0x43u, 0x73u, 0x51u, 0x20u, 0x1au, - 0xf8u, 0xbdu, 0xdbu, 0x19u, 0x18u, 0x1au, 0x02u, 0xf0u, 0x0fu, 0xf9u, 0x06u, 0x4bu, 0x00u, 0x19u, 0x98u, 0x42u, + 0xf8u, 0xbdu, 0xdbu, 0x19u, 0x18u, 0x1au, 0x02u, 0xf0u, 0x4bu, 0xf9u, 0x06u, 0x4bu, 0x00u, 0x19u, 0x98u, 0x42u, 0xeeu, 0xd9u, 0x18u, 0x00u, 0xecu, 0xe7u, 0x00u, 0x24u, 0x20u, 0x00u, 0xf0u, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xffu, 0x03u, 0x00u, 0x00u, 0x80u, 0x21u, 0x10u, 0xb5u, 0x02u, 0x4bu, 0x09u, 0x02u, 0x1au, 0x68u, 0xffu, 0xf7u, 0xc5u, 0xffu, 0x10u, 0xbdu, 0xdcu, 0x00u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x01u, 0xf0u, - 0xebu, 0xfau, 0x10u, 0xbdu, 0x06u, 0x4bu, 0x10u, 0xb5u, 0x1bu, 0x68u, 0x5bu, 0x68u, 0x00u, 0x2bu, 0x06u, 0xd0u, + 0x01u, 0xfbu, 0x10u, 0xbdu, 0x06u, 0x4bu, 0x10u, 0xb5u, 0x1bu, 0x68u, 0x5bu, 0x68u, 0x00u, 0x2bu, 0x06u, 0xd0u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x00u, 0x20u, 0x18u, 0x5eu, 0xffu, 0xf7u, 0x8du, 0xfdu, 0x10u, 0xbdu, 0x98u, 0x05u, 0x00u, 0x08u, 0x07u, 0x4bu, 0x10u, 0xb5u, 0x1bu, 0x68u, 0x5bu, 0x68u, 0x00u, 0x2bu, 0x08u, 0xd0u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x05u, 0xd0u, 0x00u, 0x20u, 0x18u, 0x5eu, 0x00u, 0x28u, 0x01u, 0xdbu, 0xffu, 0xf7u, 0xafu, 0xfdu, 0x10u, 0xbdu, 0x98u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0x96u, 0xfbu, 0x10u, 0xbdu, - 0x10u, 0xb5u, 0xffu, 0xf7u, 0x96u, 0xfbu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x01u, 0xf0u, 0xbdu, 0xfcu, 0x10u, 0xbdu, - 0x10u, 0xb5u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x08u, 0xfcu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x03u, 0x22u, + 0x10u, 0xb5u, 0xffu, 0xf7u, 0x96u, 0xfbu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x01u, 0xf0u, 0x05u, 0xfdu, 0x10u, 0xbdu, + 0x10u, 0xb5u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x50u, 0xfcu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x03u, 0x22u, 0x05u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x38u, 0xfeu, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0x40u, 0x42u, 0x18u, 0x40u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x10u, 0xbdu, 0x01u, 0x05u, 0x00u, 0x10u, 0xfeu, 0xffu, 0xe9u, 0xffu, 0x02u, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x00u, 0x00u, 0x28u, 0x09u, 0xd0u, 0xfau, 0x23u, 0xffu, 0x33u, 0x99u, 0x42u, 0x05u, 0xd8u, 0xf9u, 0x3bu, 0xffu, 0x3bu, 0x02u, 0x49u, 0xffu, 0xf7u, 0xd3u, 0xfdu, 0x10u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x07u, 0x08u, 0x00u, 0x16u, 0x01u, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x00u, 0x00u, 0x28u, 0x08u, 0xd0u, 0xfau, 0x23u, 0xffu, 0x33u, 0x99u, 0x42u, 0x04u, 0xd8u, 0x03u, 0x49u, 0x03u, 0xf0u, - 0xceu, 0xfdu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x07u, 0x08u, 0x00u, 0x16u, + 0x0au, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x07u, 0x08u, 0x00u, 0x16u, 0x01u, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x84u, 0xfeu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x98u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x5eu, 0xfeu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x07u, 0x4bu, 0x10u, 0xb5u, 0x01u, 0x22u, 0x19u, 0x60u, @@ -203,55 +203,55 @@ const uint8_t cy_m0p_image[] = { 0x70u, 0xb5u, 0x0bu, 0x00u, 0x15u, 0x00u, 0x00u, 0x21u, 0x02u, 0x00u, 0x01u, 0x20u, 0x00u, 0xf0u, 0xa4u, 0xfdu, 0x04u, 0x1eu, 0x03u, 0xd0u, 0x29u, 0x00u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xe2u, 0xfdu, 0x20u, 0x00u, 0x70u, 0xbdu, 0x03u, 0x88u, 0xaeu, 0x20u, 0x58u, 0x43u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0xc0u, 0x18u, 0x0cu, 0x00u, 0x0au, 0x21u, - 0x02u, 0xf0u, 0x42u, 0xf8u, 0x20u, 0x80u, 0x10u, 0xbdu, 0x91u, 0xfcu, 0xffu, 0xffu, 0x00u, 0x22u, 0x83u, 0x5eu, - 0x04u, 0x48u, 0x10u, 0xb5u, 0x58u, 0x43u, 0x0cu, 0x00u, 0x03u, 0x49u, 0x02u, 0xf0u, 0xbfu, 0xf8u, 0xbdu, 0x30u, + 0x02u, 0xf0u, 0x7eu, 0xf8u, 0x20u, 0x80u, 0x10u, 0xbdu, 0x91u, 0xfcu, 0xffu, 0xffu, 0x00u, 0x22u, 0x83u, 0x5eu, + 0x04u, 0x48u, 0x10u, 0xb5u, 0x58u, 0x43u, 0x0cu, 0x00u, 0x03u, 0x49u, 0x02u, 0xf0u, 0xfbu, 0xf8u, 0xbdu, 0x30u, 0x20u, 0x80u, 0x10u, 0xbdu, 0xb5u, 0xd7u, 0xffu, 0xffu, 0x10u, 0x27u, 0x00u, 0x00u, 0xf8u, 0xb5u, 0x80u, 0x23u, 0xfau, 0x27u, 0x0eu, 0x00u, 0x01u, 0x25u, 0x1bu, 0x02u, 0x18u, 0x43u, 0x0cu, 0x4cu, 0x00u, 0x04u, 0xe0u, 0x61u, 0xbfu, 0x00u, 0x23u, 0x6cu, 0x2bu, 0x42u, 0x08u, 0xd1u, 0x00u, 0x2fu, 0x01u, 0xd1u, 0x08u, 0x48u, 0x0cu, 0xe0u, - 0x28u, 0x00u, 0x01u, 0x3fu, 0x01u, 0xf0u, 0x10u, 0xfau, 0xf3u, 0xe7u, 0x00u, 0x2fu, 0xf6u, 0xd0u, 0x00u, 0x20u, + 0x28u, 0x00u, 0x01u, 0x3fu, 0x01u, 0xf0u, 0x26u, 0xfau, 0xf3u, 0xe7u, 0x00u, 0x2fu, 0xf6u, 0xd0u, 0x00u, 0x20u, 0x23u, 0x6cu, 0x1du, 0x43u, 0x25u, 0x64u, 0xe3u, 0x6au, 0x33u, 0x80u, 0xf8u, 0xbdu, 0x00u, 0x00u, 0x3cu, 0x40u, 0x04u, 0x00u, 0x16u, 0x00u, 0x70u, 0xb5u, 0xfau, 0x26u, 0x01u, 0x25u, 0x00u, 0x04u, 0x0bu, 0x4cu, 0x01u, 0x43u, 0xe1u, 0x61u, 0xb6u, 0x00u, 0x23u, 0x6cu, 0x2bu, 0x42u, 0x08u, 0xd1u, 0x00u, 0x2eu, 0x01u, 0xd1u, 0x08u, 0x48u, - 0x0au, 0xe0u, 0x28u, 0x00u, 0x01u, 0x3eu, 0x01u, 0xf0u, 0xefu, 0xf9u, 0xf3u, 0xe7u, 0x00u, 0x2eu, 0xf6u, 0xd0u, + 0x0au, 0xe0u, 0x28u, 0x00u, 0x01u, 0x3eu, 0x01u, 0xf0u, 0x05u, 0xfau, 0xf3u, 0xe7u, 0x00u, 0x2eu, 0xf6u, 0xd0u, 0x00u, 0x20u, 0x23u, 0x6cu, 0x1du, 0x43u, 0x25u, 0x64u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x3cu, 0x40u, 0x04u, 0x00u, 0x16u, 0x00u, 0x10u, 0x23u, 0x04u, 0x49u, 0x04u, 0x4au, 0x88u, 0x58u, 0x03u, 0x43u, 0x8bu, 0x50u, 0x00u, 0x22u, 0x03u, 0x4bu, 0x1au, 0x60u, 0x70u, 0x47u, 0x00u, 0x00u, 0x3cu, 0x40u, 0x70u, 0xf0u, 0x01u, 0x00u, - 0xecu, 0x00u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xedu, 0xffu, 0x10u, 0xbdu, 0xf0u, 0xb5u, 0x1bu, 0x4bu, + 0x34u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xedu, 0xffu, 0x10u, 0xbdu, 0xf0u, 0xb5u, 0x1bu, 0x4bu, 0x9du, 0xb0u, 0x01u, 0xa9u, 0x0au, 0x00u, 0x18u, 0x00u, 0x70u, 0xc8u, 0x70u, 0xc2u, 0x70u, 0xc8u, 0x70u, 0xc2u, 0x70u, 0xc8u, 0x70u, 0xc2u, 0x0au, 0xacu, 0x1au, 0x00u, 0x20u, 0x00u, 0x24u, 0x32u, 0xe0u, 0xcau, 0xe0u, 0xc0u, 0xe0u, 0xcau, 0xe0u, 0xc0u, 0xe0u, 0xcau, 0xe0u, 0xc0u, 0x13u, 0xadu, 0x2au, 0x00u, 0x48u, 0x33u, 0xc1u, 0xcbu, 0xc1u, 0xc2u, 0xc1u, 0xcbu, 0xc1u, 0xc2u, 0xc1u, 0xcbu, 0xc1u, 0xc2u, 0x0du, 0x4eu, 0x33u, 0x68u, 0x98u, 0x69u, 0x01u, 0x30u, 0xffu, 0x30u, 0x00u, 0xf0u, 0x02u, 0xfcu, 0x33u, 0x68u, 0x21u, 0x00u, 0x98u, 0x69u, 0x81u, 0x30u, 0xffu, 0x30u, 0x00u, 0xf0u, 0xfbu, 0xfbu, 0x33u, 0x68u, 0x29u, 0x00u, 0x98u, 0x69u, 0x80u, 0x23u, 0x9bu, 0x00u, - 0xc0u, 0x18u, 0x00u, 0xf0u, 0xf3u, 0xfbu, 0x1du, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x68u, 0x46u, 0x00u, 0x10u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x02u, 0x93u, 0x0eu, 0xabu, 0x1bu, 0x78u, 0x03u, 0x90u, + 0xc0u, 0x18u, 0x00u, 0xf0u, 0xf3u, 0xfbu, 0x1du, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x46u, 0x00u, 0x10u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x02u, 0x93u, 0x0eu, 0xabu, 0x1bu, 0x78u, 0x03u, 0x90u, 0x00u, 0x91u, 0x04u, 0x92u, 0x05u, 0x93u, 0x01u, 0x28u, 0x00u, 0xd9u, 0x49u, 0xe1u, 0x03u, 0x29u, 0x00u, 0xd9u, 0x46u, 0xe1u, 0x02u, 0x9bu, 0x0cu, 0x3bu, 0x87u, 0x2bu, 0x00u, 0xd9u, 0x41u, 0xe1u, 0xfbu, 0x2au, 0x00u, 0xd9u, - 0x3eu, 0xe1u, 0xa2u, 0x4cu, 0x63u, 0x68u, 0x9bu, 0x03u, 0x01u, 0xd5u, 0x01u, 0xf0u, 0xafu, 0xfbu, 0x01u, 0x22u, + 0x3eu, 0xe1u, 0xa2u, 0x4cu, 0x63u, 0x68u, 0x9bu, 0x03u, 0x01u, 0xd5u, 0x01u, 0xf0u, 0xf7u, 0xfbu, 0x01u, 0x22u, 0x9fu, 0x4bu, 0xa0u, 0x49u, 0x1eu, 0x00u, 0x58u, 0x58u, 0x01u, 0x91u, 0x10u, 0x42u, 0x04u, 0xd0u, 0x9eu, 0x49u, 0x5bu, 0x58u, 0x13u, 0x42u, 0x00u, 0xd0u, 0x2du, 0xe1u, 0xffu, 0xf7u, 0x98u, 0xffu, 0x9bu, 0x4bu, 0x9cu, 0x4au, 0xf2u, 0x50u, 0xa0u, 0x23u, 0x02u, 0x9au, 0x1bu, 0x03u, 0x13u, 0x43u, 0x9au, 0x4au, 0xb3u, 0x50u, 0x9au, 0x4bu, 0x9au, 0x4au, 0xf2u, 0x50u, 0x9au, 0x4bu, 0x5au, 0x68u, 0x01u, 0x23u, 0x1au, 0x42u, 0x00u, 0xd0u, 0x1bu, 0xe1u, 0x98u, 0x4au, 0xb0u, 0x58u, 0x08u, 0x22u, 0x10u, 0x40u, 0x4bu, 0xd0u, 0x18u, 0x00u, 0x32u, 0x68u, 0x96u, 0x4bu, - 0x40u, 0x03u, 0x18u, 0x43u, 0x80u, 0x25u, 0x10u, 0x43u, 0x30u, 0x60u, 0x63u, 0x69u, 0xedu, 0x05u, 0x2bu, 0x42u, - 0x5bu, 0xd0u, 0x05u, 0x9bu, 0x00u, 0x2bu, 0x58u, 0xd1u, 0x01u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0x8cu, 0xfau, + 0x40u, 0x03u, 0x18u, 0x43u, 0x80u, 0x25u, 0x02u, 0x43u, 0x32u, 0x60u, 0x63u, 0x69u, 0xedu, 0x05u, 0x2bu, 0x42u, + 0x5bu, 0xd0u, 0x05u, 0x9bu, 0x00u, 0x2bu, 0x58u, 0xd1u, 0x01u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0xd4u, 0xfau, 0x8eu, 0x4bu, 0x62u, 0x69u, 0x1bu, 0x68u, 0x42u, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x2au, 0x42u, 0x02u, 0xd0u, 0xa3u, 0x69u, 0x1du, 0x43u, 0xa5u, 0x61u, 0x01u, 0x9bu, 0x01u, 0x9au, 0xf7u, 0x58u, 0x88u, 0x4bu, - 0x40u, 0x20u, 0x3bu, 0x43u, 0xb3u, 0x50u, 0x01u, 0xf0u, 0x27u, 0xf9u, 0x01u, 0x23u, 0x85u, 0x4cu, 0x32u, 0x59u, - 0x1au, 0x42u, 0x08u, 0xd1u, 0x33u, 0x51u, 0x40u, 0x20u, 0x01u, 0xf0u, 0x1eu, 0xf9u, 0x03u, 0x23u, 0x40u, 0x20u, - 0x33u, 0x51u, 0x01u, 0xf0u, 0x19u, 0xf9u, 0xfau, 0x25u, 0x7fu, 0x4bu, 0x80u, 0x4cu, 0x1fu, 0x40u, 0x01u, 0x9bu, + 0x40u, 0x20u, 0x3bu, 0x43u, 0xb3u, 0x50u, 0x01u, 0xf0u, 0x3du, 0xf9u, 0x01u, 0x23u, 0x85u, 0x4cu, 0x32u, 0x59u, + 0x1au, 0x42u, 0x08u, 0xd1u, 0x33u, 0x51u, 0x40u, 0x20u, 0x01u, 0xf0u, 0x34u, 0xf9u, 0x03u, 0x23u, 0x40u, 0x20u, + 0x33u, 0x51u, 0x01u, 0xf0u, 0x2fu, 0xf9u, 0xfau, 0x25u, 0x7fu, 0x4bu, 0x80u, 0x4cu, 0x1fu, 0x40u, 0x01u, 0x9bu, 0x3cu, 0x43u, 0xf4u, 0x50u, 0xedu, 0x00u, 0x79u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x69u, 0x7cu, 0x4bu, 0xd3u, 0x58u, 0x10u, 0x22u, 0x13u, 0x42u, 0x2cu, 0xd1u, 0x00u, 0x2du, 0x25u, 0xd1u, 0x7au, 0x4cu, 0x20u, 0x00u, 0x09u, 0xb0u, - 0xf0u, 0xbdu, 0x00u, 0xf0u, 0xadu, 0xffu, 0x71u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0xd2u, 0x6fu, 0x1bu, 0x68u, - 0x9bu, 0x18u, 0x19u, 0x68u, 0x09u, 0x0eu, 0x01u, 0x31u, 0x4bu, 0x08u, 0x18u, 0x18u, 0x01u, 0xf0u, 0xfcu, 0xfeu, - 0x71u, 0x49u, 0x88u, 0x42u, 0x02u, 0xd8u, 0x32u, 0x68u, 0x70u, 0x48u, 0xa3u, 0xe7u, 0x01u, 0xf0u, 0xf4u, 0xfeu, + 0xf0u, 0xbdu, 0x01u, 0xf0u, 0x5bu, 0xf8u, 0x71u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0xd2u, 0x6fu, 0x1bu, 0x68u, + 0x9bu, 0x18u, 0x19u, 0x68u, 0x09u, 0x0eu, 0x01u, 0x31u, 0x4bu, 0x08u, 0x18u, 0x18u, 0x01u, 0xf0u, 0x38u, 0xffu, + 0x71u, 0x49u, 0x88u, 0x42u, 0x02u, 0xd8u, 0x32u, 0x68u, 0x70u, 0x48u, 0xa3u, 0xe7u, 0x01u, 0xf0u, 0x30u, 0xffu, 0x01u, 0x38u, 0x32u, 0x68u, 0x00u, 0x28u, 0xf7u, 0xd0u, 0x99u, 0xe7u, 0x03u, 0x23u, 0x6cu, 0x4au, 0xb1u, 0x58u, - 0x0bu, 0x43u, 0xb3u, 0x50u, 0xb0u, 0xe7u, 0x01u, 0x20u, 0x01u, 0x3du, 0x01u, 0xf0u, 0xddu, 0xf8u, 0xcau, 0xe7u, + 0x0bu, 0x43u, 0xb3u, 0x50u, 0xb0u, 0xe7u, 0x01u, 0x20u, 0x01u, 0x3du, 0x01u, 0xf0u, 0xf3u, 0xf8u, 0xcau, 0xe7u, 0x00u, 0x2du, 0xd2u, 0xd0u, 0x08u, 0x23u, 0x67u, 0x4au, 0x01u, 0x20u, 0xb1u, 0x58u, 0x0bu, 0x43u, 0xb3u, 0x50u, - 0x01u, 0xf0u, 0x06u, 0xfau, 0x00u, 0x28u, 0x02u, 0xd0u, 0x05u, 0x9bu, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x62u, 0x4cu, + 0x01u, 0xf0u, 0x4eu, 0xfau, 0x00u, 0x28u, 0x02u, 0xd0u, 0x05u, 0x9bu, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x62u, 0x4cu, 0x3cu, 0x43u, 0x62u, 0x4bu, 0x01u, 0x9au, 0x23u, 0x40u, 0x01u, 0x24u, 0x61u, 0x4du, 0x23u, 0x43u, 0xb3u, 0x50u, 0x49u, 0x4bu, 0xf3u, 0x58u, 0x23u, 0x42u, 0x00u, 0xd0u, 0xceu, 0xe0u, 0x00u, 0x2du, 0xb5u, 0xd0u, 0x20u, 0x00u, - 0x01u, 0x3du, 0x01u, 0xf0u, 0xb9u, 0xf8u, 0xf3u, 0xe7u, 0x01u, 0x3du, 0x00u, 0x28u, 0x00u, 0xd0u, 0xdau, 0xe0u, + 0x01u, 0x3du, 0x01u, 0xf0u, 0xcfu, 0xf8u, 0xf3u, 0xe7u, 0x01u, 0x3du, 0x00u, 0x28u, 0x00u, 0xd0u, 0xdau, 0xe0u, 0x06u, 0xabu, 0xdbu, 0x88u, 0xbbu, 0x42u, 0x00u, 0xd0u, 0xc4u, 0xe0u, 0x06u, 0xabu, 0x99u, 0x1du, 0x55u, 0x48u, 0xffu, 0xf7u, 0x84u, 0xfeu, 0x04u, 0x1eu, 0x00u, 0xd0u, 0xcdu, 0xe0u, 0x06u, 0xabu, 0xdau, 0x88u, 0x80u, 0x23u, 0xdbu, 0x00u, 0x1au, 0x42u, 0x1bu, 0xd1u, 0x0au, 0x25u, 0x01u, 0x93u, 0x80u, 0x21u, 0x4du, 0x48u, 0xc9u, 0x00u, @@ -270,12 +270,12 @@ const uint8_t cy_m0p_image[] = { 0x22u, 0x4cu, 0x33u, 0xe7u, 0x22u, 0x4cu, 0x31u, 0xe7u, 0x22u, 0x4cu, 0x2fu, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, 0x00u, 0x00u, 0x3cu, 0x40u, 0xa0u, 0xf0u, 0x01u, 0x00u, 0xb4u, 0xf0u, 0x01u, 0x00u, 0xa4u, 0xf0u, 0x01u, 0x00u, 0x06u, 0x00u, 0x00u, 0x01u, 0xa8u, 0xf0u, 0x01u, 0x00u, 0xacu, 0xf0u, 0x01u, 0x00u, 0x01u, 0x00u, 0x01u, 0x00u, - 0xfcu, 0x00u, 0x3cu, 0x40u, 0x70u, 0xf0u, 0x01u, 0x00u, 0x04u, 0x1au, 0x00u, 0x80u, 0xc4u, 0x12u, 0x00u, 0x08u, + 0xfcu, 0x00u, 0x3cu, 0x40u, 0x70u, 0xf0u, 0x01u, 0x00u, 0x04u, 0x1au, 0x00u, 0x80u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x30u, 0x00u, 0x03u, 0x00u, 0xb0u, 0xf0u, 0x01u, 0x00u, 0xefu, 0xffu, 0xfeu, 0xffu, 0x20u, 0x00u, 0x02u, 0x00u, 0x10u, 0x40u, 0x00u, 0x00u, 0x04u, 0x00u, 0x16u, 0x00u, 0x00u, 0x09u, 0x3du, 0x00u, 0x04u, 0x0au, 0x00u, 0x80u, 0xc4u, 0xf0u, 0x01u, 0x00u, 0x68u, 0xf0u, 0x01u, 0x00u, 0x28u, 0x00u, 0x02u, 0x00u, 0xffu, 0xffu, 0xfbu, 0xffu, 0xf0u, 0x7eu, 0x0eu, 0x00u, 0x03u, 0x1eu, 0x00u, 0x00u, 0x09u, 0x1eu, 0x00u, 0x00u, 0x00u, 0x48u, 0xe8u, 0x01u, - 0xecu, 0x00u, 0x00u, 0x08u, 0x64u, 0xf0u, 0x01u, 0x00u, 0x00u, 0x24u, 0xf4u, 0x00u, 0x01u, 0x00u, 0x16u, 0x00u, + 0x34u, 0x06u, 0x00u, 0x08u, 0x64u, 0xf0u, 0x01u, 0x00u, 0x00u, 0x24u, 0xf4u, 0x00u, 0x01u, 0x00u, 0x16u, 0x00u, 0x03u, 0x00u, 0x16u, 0x00u, 0x02u, 0x00u, 0x16u, 0x00u, 0x00u, 0x2du, 0x00u, 0xd1u, 0xe5u, 0xe6u, 0xc0u, 0x27u, 0x0au, 0x25u, 0x7fu, 0x01u, 0xc0u, 0x21u, 0x3bu, 0x48u, 0x49u, 0x01u, 0xffu, 0xf7u, 0xe3u, 0xfdu, 0x04u, 0x1eu, 0x6cu, 0xd1u, 0x06u, 0xabu, 0x99u, 0x1du, 0x37u, 0x48u, 0xffu, 0xf7u, 0xb8u, 0xfdu, 0x04u, 0x00u, 0x00u, 0x2du, @@ -291,15 +291,15 @@ const uint8_t cy_m0p_image[] = { 0x93u, 0x43u, 0x19u, 0x43u, 0x31u, 0x80u, 0xffu, 0xf7u, 0x8du, 0xfdu, 0x04u, 0x00u, 0x00u, 0x2cu, 0x00u, 0xd0u, 0x84u, 0xe6u, 0x04u, 0x9bu, 0x12u, 0x49u, 0x5bu, 0x00u, 0x19u, 0x43u, 0x89u, 0xb2u, 0x11u, 0x48u, 0xffu, 0xf7u, 0x81u, 0xfdu, 0x04u, 0x1eu, 0x04u, 0xd1u, 0x10u, 0x49u, 0x10u, 0x48u, 0xffu, 0xf7u, 0x7bu, 0xfdu, 0x04u, 0x00u, - 0x02u, 0x9bu, 0x58u, 0x01u, 0x80u, 0xb2u, 0x00u, 0xf0u, 0x77u, 0xffu, 0x6fu, 0xe6u, 0x00u, 0x2du, 0x99u, 0xd0u, + 0x02u, 0x9bu, 0x58u, 0x01u, 0x80u, 0xb2u, 0x00u, 0xf0u, 0x8du, 0xffu, 0x6fu, 0xe6u, 0x00u, 0x2du, 0x99u, 0xd0u, 0x99u, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x1eu, 0x00u, 0x00u, 0x04u, 0x00u, 0x16u, 0x00u, 0x16u, 0x18u, 0x00u, 0x00u, 0x07u, 0x1eu, 0x00u, 0x00u, 0x7fu, 0xf5u, 0xffu, 0xffu, 0xffu, 0xe7u, 0xffu, 0xffu, 0x06u, 0x1eu, 0x00u, 0x00u, 0x01u, 0x10u, 0x00u, 0x00u, 0x08u, 0x1eu, 0x00u, 0x00u, 0x37u, 0x68u, 0x00u, 0x00u, 0x0fu, 0x1eu, 0x00u, 0x00u, 0x13u, 0xb5u, 0x00u, 0x28u, 0x08u, 0xd0u, 0x00u, 0x24u, 0x03u, 0x78u, 0x42u, 0x78u, 0xc1u, 0x78u, 0x80u, 0x78u, 0x00u, 0x94u, 0xffu, 0xf7u, 0xbfu, 0xfdu, 0x16u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x16u, 0x00u, - 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, + 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u, 0x1cu, 0xd0u, 0x12u, 0x4bu, @@ -310,78 +310,78 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0x00u, 0x52u, 0x00u, 0x01u, 0x00u, 0x00u, 0xf0u, 0x09u, 0x00u, 0x00u, 0xa0u, 0x04u, 0x00u, 0x00u, 0xf0u, 0x05u, 0x00u, 0x00u, 0xf0u, 0x03u, 0x00u, 0x00u, 0xf0u, 0x01u, 0x00u, 0x52u, 0x00u, 0x02u, 0x00u, 0x52u, 0x00u, 0x03u, 0x00u, 0x52u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, - 0x10u, 0xb5u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x8cu, 0xfdu, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0xd2u, 0x6fu, + 0x10u, 0xb5u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x3au, 0xfeu, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0xd2u, 0x6fu, 0x1bu, 0x68u, 0x9bu, 0x18u, 0x19u, 0x68u, 0x1cu, 0x68u, 0x09u, 0x0eu, 0x01u, 0x31u, 0x4bu, 0x08u, 0x18u, 0x18u, - 0x01u, 0xf0u, 0xdau, 0xfcu, 0x24u, 0x0au, 0xe4u, 0xb2u, 0x01u, 0x34u, 0x63u, 0x08u, 0xc0u, 0x18u, 0x21u, 0x00u, - 0x01u, 0xf0u, 0xd2u, 0xfcu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x20u, + 0x01u, 0xf0u, 0x16u, 0xfdu, 0x24u, 0x0au, 0xe4u, 0xb2u, 0x01u, 0x34u, 0x63u, 0x08u, 0xc0u, 0x18u, 0x21u, 0x00u, + 0x01u, 0xf0u, 0x0eu, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x7cu, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x7bu, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x0du, 0x4bu, 0x10u, 0xb5u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x0du, 0x4bu, 0x10u, 0xb5u, 0x18u, 0x60u, 0x00u, 0x28u, 0x04u, 0xd0u, 0xfeu, 0x23u, 0x5bu, 0x42u, 0x03u, 0x80u, 0x00u, 0x23u, 0x43u, 0x80u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0x4cu, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, 0x08u, 0xd0u, 0x4du, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x02u, 0x22u, 0x04u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x14u, 0xfau, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb0u, 0x05u, 0x00u, 0x08u, 0xc4u, 0x12u, 0x00u, 0x08u, 0xb1u, 0x02u, 0x00u, 0x08u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb0u, 0x05u, 0x00u, 0x08u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xadu, 0x02u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x05u, 0x00u, 0x08u, - 0x10u, 0xb5u, 0xc3u, 0x05u, 0x04u, 0x00u, 0x00u, 0x2bu, 0x29u, 0xd1u, 0x01u, 0xf0u, 0x99u, 0xfbu, 0xe0u, 0x22u, + 0x10u, 0xb5u, 0xc3u, 0x05u, 0x04u, 0x00u, 0x00u, 0x2bu, 0x29u, 0xd1u, 0x01u, 0xf0u, 0xd5u, 0xfbu, 0xe0u, 0x22u, 0x14u, 0x4bu, 0x52u, 0x05u, 0x1au, 0x60u, 0x14u, 0x4au, 0x12u, 0x78u, 0x00u, 0x2au, 0x04u, 0xd0u, 0x80u, 0x22u, 0x19u, 0x68u, 0x52u, 0x00u, 0x0au, 0x43u, 0x1au, 0x60u, 0x5cu, 0x60u, 0x00u, 0x24u, 0x9cu, 0x60u, 0xdcu, 0x60u, 0x0eu, 0x4bu, 0x1bu, 0x68u, 0x50u, 0x33u, 0x18u, 0x78u, 0x01u, 0x00u, 0xa0u, 0x42u, 0x0cu, 0xd0u, 0xffu, 0xf7u, - 0x77u, 0xffu, 0xfau, 0x21u, 0x89u, 0x00u, 0x01u, 0xf0u, 0x5fu, 0xfcu, 0x01u, 0x00u, 0x08u, 0x48u, 0x01u, 0xf0u, - 0x5bu, 0xfcu, 0x08u, 0x4bu, 0xc1u, 0x18u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xb6u, 0xf9u, 0x10u, 0xbdu, 0x06u, 0x48u, - 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x00u, 0x16u, 0xc4u, 0x12u, 0x00u, 0x08u, + 0x77u, 0xffu, 0xfau, 0x21u, 0x89u, 0x00u, 0x01u, 0xf0u, 0x9bu, 0xfcu, 0x01u, 0x00u, 0x08u, 0x48u, 0x01u, 0xf0u, + 0x97u, 0xfcu, 0x08u, 0x4bu, 0xc1u, 0x18u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xfau, 0xf9u, 0x10u, 0xbdu, 0x06u, 0x48u, + 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x00u, 0x16u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x60u, 0xf5u, 0x90u, 0x00u, 0x98u, 0x08u, 0x00u, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0x70u, 0xb5u, 0xc4u, 0x05u, - 0x06u, 0x00u, 0x0du, 0x00u, 0xe4u, 0x0du, 0x20u, 0xd1u, 0x00u, 0x29u, 0x1eu, 0xd0u, 0x01u, 0xf0u, 0x58u, 0xfbu, + 0x06u, 0x00u, 0x0du, 0x00u, 0xe4u, 0x0du, 0x20u, 0xd1u, 0x00u, 0x29u, 0x1eu, 0xd0u, 0x01u, 0xf0u, 0x94u, 0xfbu, 0x0fu, 0x4bu, 0x10u, 0x4au, 0x1au, 0x60u, 0x5cu, 0x60u, 0x9eu, 0x60u, 0xddu, 0x60u, 0x0eu, 0x4bu, 0x1bu, 0x68u, 0x4eu, 0x33u, 0x19u, 0x78u, 0x00u, 0x29u, 0x0bu, 0xd0u, 0xffu, 0xf7u, 0x42u, 0xffu, 0xfau, 0x21u, 0x89u, 0x00u, - 0x01u, 0xf0u, 0x2au, 0xfcu, 0x01u, 0x00u, 0x09u, 0x48u, 0x01u, 0xf0u, 0x26u, 0xfcu, 0x08u, 0x4bu, 0xc1u, 0x18u, - 0x80u, 0x20u, 0x40u, 0x00u, 0x03u, 0xf0u, 0x80u, 0xf9u, 0x70u, 0xbdu, 0x06u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, - 0xa0u, 0x05u, 0x00u, 0x08u, 0x00u, 0x01u, 0x00u, 0x05u, 0xc4u, 0x12u, 0x00u, 0x08u, 0xc0u, 0xeau, 0x21u, 0x01u, + 0x01u, 0xf0u, 0x66u, 0xfcu, 0x01u, 0x00u, 0x09u, 0x48u, 0x01u, 0xf0u, 0x62u, 0xfcu, 0x08u, 0x4bu, 0xc1u, 0x18u, + 0x80u, 0x20u, 0x40u, 0x00u, 0x03u, 0xf0u, 0xc4u, 0xf9u, 0x70u, 0xbdu, 0x06u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, + 0xa0u, 0x05u, 0x00u, 0x08u, 0x00u, 0x01u, 0x00u, 0x05u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xc0u, 0xeau, 0x21u, 0x01u, 0x48u, 0x26u, 0x00u, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0x3fu, 0xffu, 0x10u, 0xbdu, 0x70u, 0xb5u, 0xc3u, 0x05u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x00u, 0x2bu, 0x2au, 0xd1u, 0x00u, 0x29u, 0x28u, 0xd0u, - 0x01u, 0xf0u, 0x1eu, 0xfbu, 0xc0u, 0x22u, 0x80u, 0x21u, 0x13u, 0x4bu, 0xd2u, 0x04u, 0x1au, 0x60u, 0x13u, 0x4au, + 0x01u, 0xf0u, 0x5au, 0xfbu, 0xc0u, 0x22u, 0x80u, 0x21u, 0x13u, 0x4bu, 0xd2u, 0x04u, 0x1au, 0x60u, 0x13u, 0x4au, 0x49u, 0x00u, 0x12u, 0x78u, 0x00u, 0x2au, 0x02u, 0xd0u, 0x1au, 0x68u, 0x0au, 0x43u, 0x1au, 0x60u, 0x59u, 0x60u, 0x9du, 0x60u, 0xdcu, 0x60u, 0x0eu, 0x4bu, 0x1bu, 0x68u, 0x4fu, 0x33u, 0x18u, 0x78u, 0x01u, 0x1eu, 0x0du, 0xd0u, - 0xffu, 0xf7u, 0xfeu, 0xfeu, 0xfau, 0x21u, 0x89u, 0x00u, 0x01u, 0xf0u, 0xe6u, 0xfbu, 0x01u, 0x00u, 0x09u, 0x48u, - 0x01u, 0xf0u, 0xe2u, 0xfbu, 0xe1u, 0x23u, 0x9bu, 0x00u, 0xc1u, 0x18u, 0x00u, 0x20u, 0x03u, 0xf0u, 0x3cu, 0xf9u, + 0xffu, 0xf7u, 0xfeu, 0xfeu, 0xfau, 0x21u, 0x89u, 0x00u, 0x01u, 0xf0u, 0x22u, 0xfcu, 0x01u, 0x00u, 0x09u, 0x48u, + 0x01u, 0xf0u, 0x1eu, 0xfcu, 0xe1u, 0x23u, 0x9bu, 0x00u, 0xc1u, 0x18u, 0x00u, 0x20u, 0x03u, 0xf0u, 0x80u, 0xf9u, 0x70u, 0xbdu, 0x05u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x00u, 0x16u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0x80u, 0x8du, 0x5bu, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0x0eu, 0x4bu, 0x10u, 0xb5u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0x80u, 0x8du, 0x5bu, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0x0eu, 0x4bu, 0x10u, 0xb5u, 0x1bu, 0x68u, 0x9cu, 0x69u, 0x5bu, 0x69u, 0x00u, 0x1bu, 0xc0u, 0x09u, 0x00u, 0x01u, 0xc0u, 0x18u, 0x1fu, 0x23u, 0x1au, 0x40u, 0x03u, 0x29u, 0x07u, 0xd8u, 0xc9u, 0x00u, 0x8bu, 0x40u, 0x8au, 0x40u, 0x04u, 0x68u, 0x9cu, 0x43u, 0x22u, 0x43u, 0x02u, 0x60u, 0x10u, 0xbdu, 0x04u, 0x39u, 0xc9u, 0x00u, 0x8bu, 0x40u, 0x8au, 0x40u, 0x44u, 0x68u, - 0x9cu, 0x43u, 0x22u, 0x43u, 0x42u, 0x60u, 0xf5u, 0xe7u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x00u, 0x28u, + 0x9cu, 0x43u, 0x22u, 0x43u, 0x42u, 0x60u, 0xf5u, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x00u, 0x29u, 0x2eu, 0xd0u, 0x18u, 0x4bu, 0xcdu, 0x68u, 0x1au, 0x68u, 0x93u, 0x69u, 0x54u, 0x69u, 0xc3u, 0x1au, 0xdbu, 0x09u, 0x1bu, 0x01u, 0x1bu, 0x19u, 0x0cu, 0x68u, 0x04u, 0x60u, 0x14u, 0x00u, 0x79u, 0x34u, 0x24u, 0x78u, 0x24u, 0x18u, 0x25u, 0x60u, 0x14u, 0x00u, 0x7au, 0x34u, 0x24u, 0x78u, 0x0du, 0x69u, 0x24u, 0x18u, 0x25u, 0x60u, 0x14u, 0x00u, 0x7bu, 0x34u, 0x24u, 0x78u, 0x4du, 0x69u, 0x24u, 0x18u, 0x25u, 0x60u, 0x14u, 0x00u, 0x78u, 0x34u, 0x24u, 0x78u, 0x8du, 0x68u, 0x24u, 0x18u, 0x25u, 0x60u, 0x4cu, 0x68u, 0x7cu, 0x32u, 0x84u, 0x61u, 0x12u, 0x78u, 0x10u, 0x18u, 0x8au, 0x69u, 0x02u, 0x60u, 0x00u, 0x20u, 0xcau, 0x69u, 0x1au, 0x60u, 0x0au, 0x6au, - 0x5au, 0x60u, 0x30u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x5au, 0x00u, + 0x5au, 0x60u, 0x30u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x5au, 0x00u, 0xf7u, 0xb5u, 0x01u, 0x26u, 0x37u, 0x00u, 0x8fu, 0x40u, 0x33u, 0x40u, 0x8bu, 0x40u, 0x05u, 0x68u, 0x14u, 0x00u, 0xbdu, 0x43u, 0x0fu, 0x27u, 0x2bu, 0x43u, 0x03u, 0x60u, 0x0au, 0x4bu, 0x08u, 0xaau, 0x12u, 0x78u, 0x1bu, 0x68u, 0x01u, 0x92u, 0x79u, 0x33u, 0x1du, 0x78u, 0x8eu, 0x00u, 0x45u, 0x19u, 0x2bu, 0x68u, 0x3cu, 0x40u, 0x1au, 0x00u, 0x3bu, 0x00u, 0xb3u, 0x40u, 0xb4u, 0x40u, 0x9au, 0x43u, 0x14u, 0x43u, 0x2cu, 0x60u, 0x01u, 0x9au, 0xffu, 0xf7u, - 0x85u, 0xffu, 0xf7u, 0xbdu, 0xc4u, 0x12u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, + 0x85u, 0xffu, 0xf7u, 0xbdu, 0xc8u, 0x12u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0xb4u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1du, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x25u, 0x40u, 0x27u, 0x40u, 0x12u, 0x4cu, 0x1bu, 0x0cu, 0x26u, 0x68u, 0x07u, 0x60u, 0x34u, 0x6au, 0x45u, 0x60u, 0x83u, 0x60u, 0xacu, 0x36u, 0x36u, 0x88u, 0x77u, 0x43u, 0x3fu, 0x19u, 0x07u, 0x61u, 0x2fu, 0x00u, 0x80u, 0x37u, 0x6du, 0x01u, 0x7fu, 0x01u, 0xe7u, 0x19u, 0x64u, 0x19u, 0x0au, 0x4du, 0x47u, 0x61u, 0x1fu, 0x04u, 0x3bu, 0x43u, 0x64u, 0x19u, 0x23u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xb4u, 0x05u, 0x00u, 0x08u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xb4u, 0x05u, 0x00u, 0x08u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0xabu, 0x70u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xb5u, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, - 0x00u, 0xf0u, 0x56u, 0xfcu, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, + 0x00u, 0xf0u, 0x6cu, 0xfcu, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, @@ -399,7 +399,7 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0xe7u, 0xfeu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, - 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, + 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb4u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x22u, 0x0au, 0x4bu, 0x50u, 0x43u, 0x1bu, 0x68u, 0x18u, 0x18u, 0x0cu, 0x22u, 0x83u, 0x5eu, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x04u, 0x4au, 0xd3u, 0x67u, @@ -410,15 +410,15 @@ const uint8_t cy_m0p_image[] = { 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, - 0x78u, 0x68u, 0x34u, 0x60u, 0x02u, 0xf0u, 0x14u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x74u, 0xfeu, + 0x78u, 0x68u, 0x34u, 0x60u, 0x02u, 0xf0u, 0x50u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x74u, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0x81u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0x69u, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, - 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x12u, 0x00u, 0x08u, 0xb8u, 0x05u, 0x00u, 0x08u, + 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xb8u, 0x05u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0xb8u, 0x05u, 0x00u, 0x08u, 0x24u, 0x05u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0xb8u, 0x05u, 0x00u, 0x08u, 0x24u, 0x05u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xfeu, 0xf7u, 0x3fu, 0xfcu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, @@ -438,144 +438,153 @@ const uint8_t cy_m0p_image[] = { 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xb8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x04u, 0x4bu, 0x10u, 0x30u, 0x1bu, 0x68u, 0x80u, 0x02u, 0x1bu, 0x69u, 0xc0u, 0x58u, 0x0fu, 0x23u, 0x18u, 0x40u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xc4u, 0x12u, 0x00u, 0x08u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, - 0x00u, 0x00u, 0x26u, 0x40u, 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0x43u, 0x0bu, 0x60u, 0x11u, 0x00u, 0x98u, 0x31u, 0x13u, 0x68u, 0x0au, 0x68u, 0x9bu, 0x18u, 0x05u, 0x4au, + 0xa2u, 0x58u, 0xe3u, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xffu, 0x8fu, 0xffu, 0xffu, 0x50u, 0x18u, 0x00u, 0x00u, + 0xffu, 0xfcu, 0xffu, 0xffu, 0x4cu, 0x18u, 0x00u, 0x00u, 0xf8u, 0xb5u, 0x1fu, 0x4fu, 0xc0u, 0x25u, 0x3bu, 0x68u, + 0x2du, 0x01u, 0x1au, 0x00u, 0x94u, 0x32u, 0x1bu, 0x68u, 0x12u, 0x68u, 0x9bu, 0x18u, 0x1eu, 0x68u, 0xffu, 0xf7u, + 0xfbu, 0xfeu, 0x34u, 0x00u, 0x80u, 0x23u, 0x2cu, 0x40u, 0x5bu, 0x00u, 0x98u, 0x42u, 0x0fu, 0xd1u, 0x00u, 0x20u, + 0xffu, 0xf7u, 0xc6u, 0xfbu, 0xb0u, 0x23u, 0x5bu, 0x05u, 0x5au, 0x78u, 0x00u, 0x2au, 0x03u, 0xd0u, 0x5au, 0x78u, + 0x01u, 0x23u, 0x22u, 0x2au, 0x01u, 0xd8u, 0x43u, 0x42u, 0x43u, 0x41u, 0x18u, 0x00u, 0xf8u, 0xbdu, 0x3bu, 0x68u, + 0x0eu, 0x4fu, 0x19u, 0x00u, 0x94u, 0x31u, 0x1au, 0x68u, 0x08u, 0x68u, 0x12u, 0x18u, 0x10u, 0x68u, 0x38u, 0x40u, + 0x10u, 0x60u, 0x1au, 0x68u, 0x08u, 0x68u, 0x12u, 0x18u, 0x28u, 0x00u, 0x17u, 0x68u, 0xb0u, 0x43u, 0x38u, 0x43u, + 0x10u, 0x60u, 0x1bu, 0x68u, 0x0au, 0x68u, 0x9bu, 0x18u, 0x18u, 0x68u, 0x28u, 0x40u, 0x00u, 0x1bu, 0x43u, 0x1eu, + 0x98u, 0x41u, 0xc0u, 0xb2u, 0xe2u, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xffu, 0xf3u, 0xffu, 0xffu, 0x02u, 0x00u, 0x00u, 0x20u, 0x82u, 0x42u, 0x02u, 0xd1u, 0x09u, 0x4bu, 0x58u, 0x69u, 0xc0u, 0x0fu, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x42u, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x09u, 0xd0u, 0x01u, 0x2au, 0x07u, 0xd1u, 0x04u, 0x4bu, 0x10u, 0x00u, 0x99u, 0x69u, 0x49u, 0x00u, 0x01u, 0xd4u, 0x98u, 0x69u, 0xc0u, 0x0fu, 0x10u, 0x40u, 0x70u, 0x47u, - 0x00u, 0x00u, 0x26u, 0x40u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0cu, 0x4bu, 0x1bu, 0x68u, 0x42u, 0x33u, + 0x00u, 0x00u, 0x26u, 0x40u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0cu, 0x4bu, 0x1bu, 0x68u, 0x42u, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x11u, 0xd0u, 0x07u, 0x22u, 0x09u, 0x4du, 0xacu, 0x69u, 0x14u, 0x40u, 0xa0u, 0x42u, 0x0bu, 0xd0u, 0xabu, 0x69u, 0x93u, 0x43u, 0x02u, 0x40u, 0x13u, 0x43u, 0xabu, 0x61u, 0x00u, 0x29u, 0x04u, 0xd0u, - 0xa0u, 0x42u, 0x02u, 0xd9u, 0xc8u, 0x20u, 0xffu, 0xf7u, 0x97u, 0xfeu, 0x70u, 0xbdu, 0xc4u, 0x12u, 0x00u, 0x08u, + 0xa0u, 0x42u, 0x02u, 0xd9u, 0xc8u, 0x20u, 0xffu, 0xf7u, 0x65u, 0xfeu, 0x70u, 0xbdu, 0xc8u, 0x12u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x70u, 0xb5u, 0x03u, 0x1eu, 0x1bu, 0xd0u, 0xc0u, 0x68u, 0x00u, 0x28u, 0x18u, 0xd0u, 0x18u, 0x68u, 0x00u, 0x28u, 0x15u, 0xd0u, 0x1cu, 0x79u, 0x16u, 0x4du, 0xa4u, 0x00u, 0x62u, 0x59u, 0x11u, 0x1eu, 0x09u, 0xd1u, 0x63u, 0x51u, 0x5au, 0x61u, 0x1au, 0x61u, 0x19u, 0xe0u, 0x06u, 0x7eu, 0x1au, 0x7eu, 0x96u, 0x42u, @@ -595,6194 +604,6193 @@ const uint8_t cy_m0p_image[] = { 0x29u, 0x00u, 0x1au, 0x68u, 0x5bu, 0x68u, 0x02u, 0x92u, 0x01u, 0x93u, 0x03u, 0x93u, 0x02u, 0xa8u, 0x23u, 0x68u, 0x98u, 0x47u, 0x24u, 0x69u, 0xeeu, 0xe7u, 0xc0u, 0x46u, 0x10u, 0x06u, 0x00u, 0x08u, 0x0cu, 0x06u, 0x00u, 0x08u, 0xffu, 0x00u, 0x42u, 0x00u, 0xf8u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x19u, 0x4cu, 0x06u, 0x00u, 0x23u, 0x68u, - 0x00u, 0x2bu, 0x1au, 0xd1u, 0xfdu, 0xf7u, 0xc9u, 0xfeu, 0x23u, 0x68u, 0x05u, 0x00u, 0x00u, 0x2bu, 0x20u, 0xd1u, + 0x00u, 0x2bu, 0x1au, 0xd1u, 0xfdu, 0xf7u, 0x81u, 0xfeu, 0x23u, 0x68u, 0x05u, 0x00u, 0x00u, 0x2bu, 0x20u, 0xd1u, 0x04u, 0x21u, 0x14u, 0x4au, 0x13u, 0x69u, 0x8bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x2eu, 0x1eu, 0xd0u, 0x30u, 0xbfu, - 0x28u, 0x00u, 0xfdu, 0xf7u, 0xbeu, 0xfeu, 0x23u, 0x68u, 0x00u, 0x24u, 0xa3u, 0x42u, 0x03u, 0xd0u, 0x08u, 0x21u, + 0x28u, 0x00u, 0xfdu, 0xf7u, 0x76u, 0xfeu, 0x23u, 0x68u, 0x00u, 0x24u, 0xa3u, 0x42u, 0x03u, 0xd0u, 0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x89u, 0xffu, 0x20u, 0x00u, 0x70u, 0xbdu, 0x01u, 0x21u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x83u, 0xffu, 0x00u, 0x28u, 0xdeu, 0xd0u, 0x02u, 0x21u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x06u, 0x4cu, 0xf1u, 0xe7u, 0x04u, 0x21u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x77u, 0xffu, 0xd9u, 0xe7u, 0x20u, 0xbfu, 0xdfu, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, 0x00u, 0xedu, 0x00u, 0xe0u, 0xffu, 0x00u, 0x42u, 0x00u, 0x70u, 0xb5u, 0xfdu, 0xf7u, - 0x94u, 0xfeu, 0xe8u, 0x21u, 0x06u, 0x4bu, 0x07u, 0x4du, 0x5cu, 0x68u, 0x89u, 0x01u, 0x2cu, 0x40u, 0x21u, 0x43u, - 0x59u, 0x60u, 0x5au, 0x68u, 0x2au, 0x40u, 0x5au, 0x60u, 0x5bu, 0x68u, 0xfdu, 0xf7u, 0x8au, 0xfeu, 0x70u, 0xbdu, + 0x4cu, 0xfeu, 0xe8u, 0x21u, 0x06u, 0x4bu, 0x07u, 0x4du, 0x5cu, 0x68u, 0x89u, 0x01u, 0x2cu, 0x40u, 0x21u, 0x43u, + 0x59u, 0x60u, 0x5au, 0x68u, 0x2au, 0x40u, 0x5au, 0x60u, 0x5bu, 0x68u, 0xfdu, 0xf7u, 0x42u, 0xfeu, 0x70u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u, 0xffu, 0x00u, 0xfcu, 0x0fu, 0xb0u, 0x23u, 0x70u, 0xb5u, 0x5bu, 0x05u, 0x5au, 0x78u, - 0x04u, 0x00u, 0x21u, 0x25u, 0x00u, 0x2au, 0x01u, 0xd0u, 0x5du, 0x78u, 0xedu, 0xb2u, 0xffu, 0xf7u, 0xceu, 0xfdu, - 0x06u, 0x00u, 0x00u, 0x20u, 0xffu, 0xf7u, 0xb4u, 0xfau, 0x80u, 0x23u, 0xadu, 0xb2u, 0x5bu, 0x00u, 0x00u, 0x28u, + 0x04u, 0x00u, 0x21u, 0x25u, 0x00u, 0x2au, 0x01u, 0xd0u, 0x5du, 0x78u, 0xedu, 0xb2u, 0xffu, 0xf7u, 0x9cu, 0xfdu, + 0x06u, 0x00u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x6cu, 0xfau, 0x80u, 0x23u, 0xadu, 0xb2u, 0x5bu, 0x00u, 0x00u, 0x28u, 0x11u, 0xd1u, 0x9eu, 0x42u, 0x11u, 0xd1u, 0x22u, 0x2du, 0x0fu, 0xd8u, 0x80u, 0x25u, 0x1eu, 0x4bu, 0x6du, 0x04u, 0x1bu, 0x68u, 0x24u, 0x06u, 0x59u, 0x68u, 0x1du, 0x4bu, 0x2cu, 0x40u, 0xcau, 0x58u, 0x1cu, 0x4du, 0x2au, 0x40u, 0x14u, 0x43u, 0xccu, 0x50u, 0x70u, 0xbdu, 0x9eu, 0x42u, 0x28u, 0xd0u, 0x17u, 0x4au, 0x12u, 0x68u, 0x15u, 0x6au, 0x9eu, 0x42u, 0x0eu, 0xd1u, 0x62u, 0x42u, 0x62u, 0x41u, 0xffu, 0x23u, 0x52u, 0x42u, 0x9au, 0x43u, 0x15u, 0x4bu, - 0xd2u, 0x18u, 0x01u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x41u, 0xf8u, 0x00u, 0x28u, 0x08u, 0xd0u, 0x12u, 0x48u, + 0xd2u, 0x18u, 0x01u, 0x21u, 0x28u, 0x00u, 0xfeu, 0xf7u, 0xf9u, 0xffu, 0x00u, 0x28u, 0x08u, 0xd0u, 0x12u, 0x48u, 0xe8u, 0xe7u, 0x62u, 0x42u, 0x62u, 0x41u, 0x01u, 0x23u, 0x52u, 0x42u, 0x9au, 0x43u, 0x0fu, 0x4bu, 0xefu, 0xe7u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xebu, 0x18u, 0x1au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xdbu, 0xebu, 0x68u, 0x00u, 0x20u, 0x1bu, 0x0eu, 0xa0u, 0x2bu, 0xe9u, 0xd1u, 0xd3u, 0xe7u, 0x22u, 0x2du, 0xe6u, 0xd9u, - 0x01u, 0x4bu, 0x1bu, 0x68u, 0x1du, 0x6au, 0xd5u, 0xe7u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x18u, 0xf0u, 0x00u, 0x00u, + 0x01u, 0x4bu, 0x1bu, 0x68u, 0x1du, 0x6au, 0xd5u, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x18u, 0xf0u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0xfeu, 0x01u, 0x01u, 0x00u, 0x30u, 0x04u, 0x00u, 0x42u, 0x00u, 0x03u, 0x00u, 0x00u, 0x0cu, - 0x70u, 0xb5u, 0x05u, 0x00u, 0xffu, 0xf7u, 0x72u, 0xfdu, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0x1bu, 0xd0u, - 0xfdu, 0xf7u, 0x13u, 0xfeu, 0x06u, 0x00u, 0x02u, 0x2du, 0x1du, 0xd1u, 0x01u, 0x20u, 0xffu, 0xf7u, 0x8cu, 0xffu, - 0x04u, 0x1eu, 0x0du, 0xd1u, 0xffu, 0xf7u, 0x6eu, 0xfdu, 0x07u, 0x22u, 0x17u, 0x49u, 0x4bu, 0x69u, 0x93u, 0x43u, - 0x2au, 0x40u, 0x13u, 0x43u, 0x4bu, 0x61u, 0x02u, 0x2du, 0x1bu, 0xd1u, 0xffu, 0xf7u, 0xe3u, 0xfdu, 0x00u, 0x24u, - 0x30u, 0x00u, 0xfdu, 0xf7u, 0xfeu, 0xfdu, 0x04u, 0xe0u, 0xffu, 0xf7u, 0x48u, 0xfeu, 0x00u, 0x28u, 0xdfu, 0xd1u, - 0x0eu, 0x4cu, 0x20u, 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0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_01_cm0p_crypto.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_01_cm0p_crypto.c index f1e46b784b..29bc922310 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_01_cm0p_crypto.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_01_cm0p_crypto.c @@ -40,35 +40,35 @@ const uint8_t cy_m0p_image[] = { 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, - 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0x00u, 0x04u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x7fu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x30u, 0x7fu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x04u, 0x04u, 0x00u, 0x08u, 0x08u, 0x7fu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xfcu, 0x03u, 0x00u, 0x08u, 0x30u, 0x7fu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0xb1u, 0xfdu, 0x06u, 0xf0u, 0x51u, 0xfdu, 0xfeu, 0xe7u, - 0x14u, 0x7fu, 0x00u, 0x10u, 0x2cu, 0x7fu, 0x00u, 0x10u, 0x00u, 0x04u, 0x00u, 0x08u, 0x5cu, 0x06u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0xc7u, 0xfdu, 0x06u, 0xf0u, 0x67u, 0xfdu, 0xfeu, 0xe7u, + 0x3cu, 0x7fu, 0x00u, 0x10u, 0x54u, 0x7fu, 0x00u, 0x10u, 0xf8u, 0x03u, 0x00u, 0x08u, 0x58u, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x06u, 0xf0u, 0x43u, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, + 0x04u, 0x30u, 0x06u, 0xf0u, 0x59u, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x52u, 0x69u, 0x82u, 0x18u, 0x08u, 0x78u, 0x49u, 0x68u, 0x38u, 0x40u, 0x10u, 0x60u, 0x01u, 0x2cu, 0x00u, 0xd1u, 0x20u, 0x31u, 0x28u, 0x00u, 0x08u, 0x9au, 0x01u, 0x3cu, 0x03u, 0xf0u, 0x72u, 0xfdu, 0x0cu, 0x23u, 0x61u, 0x42u, 0x61u, 0x41u, 0x00u, 0x93u, 0x28u, 0x00u, 0x08u, 0x3bu, 0x44u, 0x31u, 0x00u, 0x22u, 0x03u, 0xf0u, 0xd0u, 0xfdu, 0x33u, 0x68u, 0x1bu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0x2au, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x03u, 0x26u, + 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x03u, 0x26u, 0x0eu, 0x4du, 0x19u, 0x00u, 0x2bu, 0x68u, 0x00u, 0x78u, 0x5bu, 0x69u, 0x30u, 0x40u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x00u, 0x20u, 0x00u, 0x06u, 0x9au, 0x03u, 0xf0u, 0x4du, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x48u, 0x21u, 0x03u, 0xf0u, 0xadu, 0xfdu, 0x2bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, - 0x01u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x73u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x01u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x73u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1du, 0x00u, 0x1au, 0x70u, 0x04u, 0x9bu, 0x02u, 0x32u, 0x6bu, 0x60u, 0xd3u, 0x00u, 0x0au, 0x00u, 0x04u, 0x99u, 0x04u, 0x00u, 0x03u, 0xf0u, 0xceu, 0xfdu, 0x03u, 0x21u, 0x0du, 0x4eu, 0x2au, 0x78u, 0x33u, 0x68u, 0x0au, 0x40u, 0x5bu, 0x69u, 0x69u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0au, 0x00u, 0x20u, 0x00u, 0x20u, 0x32u, 0x03u, 0xf0u, 0x06u, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x22u, 0x46u, 0x21u, 0x03u, 0xf0u, 0x6cu, 0xfdu, 0x33u, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0xfcu, 0xd1u, 0x70u, 0xbdu, - 0x20u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x16u, 0x00u, 0x1au, 0x00u, 0x0au, 0x9bu, 0x05u, 0x00u, + 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x16u, 0x00u, 0x1au, 0x00u, 0x0au, 0x9bu, 0x05u, 0x00u, 0x5cu, 0x68u, 0x03u, 0x91u, 0x27u, 0x00u, 0x40u, 0x37u, 0x39u, 0x00u, 0x50u, 0x34u, 0x10u, 0x23u, 0x03u, 0xf0u, 0xa1u, 0xfdu, 0x23u, 0x00u, 0x03u, 0x9au, 0x0au, 0x99u, 0x28u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x74u, 0xffu, 0x28u, 0x00u, 0x10u, 0x23u, 0x22u, 0x00u, 0x31u, 0x00u, 0x03u, 0xf0u, 0x94u, 0xfdu, 0x00u, 0x20u, 0x05u, 0xb0u, @@ -99,7 +99,7 @@ const uint8_t cy_m0p_image[] = { 0xd3u, 0xfeu, 0x10u, 0x23u, 0x2au, 0x00u, 0x07u, 0x99u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xcbu, 0xfcu, 0x10u, 0x3cu, 0xcfu, 0xe7u, 0x01u, 0x48u, 0xdfu, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x91u, 0xb0u, 0x19u, 0x9du, 0x04u, 0x00u, 0x06u, 0x91u, 0x0bu, 0x92u, 0x00u, 0x21u, 0x10u, 0x22u, 0x0cu, 0xa8u, 0x07u, 0x93u, - 0x06u, 0xf0u, 0xafu, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, + 0x06u, 0xf0u, 0xc5u, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, 0x10u, 0x32u, 0x04u, 0x92u, 0x05u, 0x93u, 0x07u, 0x9au, 0x10u, 0x23u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xaau, 0xfcu, 0x0fu, 0x9bu, 0x1bu, 0xbau, 0x08u, 0x93u, 0x06u, 0x9bu, 0x08u, 0x9eu, 0x1bu, 0x09u, 0x0au, 0x93u, 0x0eu, 0x9bu, 0x1fu, 0xbau, 0x08u, 0x9bu, 0x17u, 0x99u, 0xf3u, 0x1au, 0x1au, 0x01u, 0x89u, 0x18u, 0x09u, 0x91u, 0x18u, 0x99u, @@ -111,32 +111,32 @@ const uint8_t cy_m0p_image[] = { 0x0eu, 0x92u, 0x00u, 0x93u, 0x04u, 0x9au, 0x03u, 0x9bu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x6cu, 0xfeu, 0x10u, 0x23u, 0x04u, 0x9au, 0x09u, 0x99u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x64u, 0xfcu, 0xc1u, 0xe7u, 0x00u, 0x00u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, - 0xfcu, 0xd1u, 0x70u, 0x47u, 0x20u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u, 0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u, - 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, 0x20u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, + 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x38u, 0x00u, 0xffu, 0xf7u, 0xbau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x24u, 0x03u, 0x1bu, 0x68u, 0x2du, 0x04u, 0xd8u, 0x68u, 0x80u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, - 0x34u, 0x43u, 0x38u, 0x18u, 0x2cu, 0x43u, 0x04u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x34u, 0x43u, 0x38u, 0x18u, 0x2cu, 0x43u, 0x04u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u, - 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, + 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7bu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa2u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, - 0x20u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x78u, 0x4au, 0x68u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x78u, 0x4au, 0x68u, 0x02u, 0x34u, 0xe4u, 0x00u, 0x23u, 0x00u, 0x0eu, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x10u, 0x23u, 0x08u, 0x22u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x08u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xffu, 0x03u, 0x21u, 0x05u, 0x4bu, 0x32u, 0x78u, 0x1bu, 0x68u, 0x0au, 0x40u, 0x5bu, 0x69u, 0x28u, 0x00u, 0xebu, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, - 0x39u, 0xffu, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0bu, 0x78u, 0x02u, 0x33u, + 0x39u, 0xffu, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0bu, 0x78u, 0x02u, 0x33u, 0xdcu, 0x00u, 0xffu, 0xf7u, 0xd1u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0x23u, 0x06u, 0x22u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x5au, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x07u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x1au, 0xffu, @@ -164,7 +164,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe2u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0x02u, 0x21u, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x8fu, 0xfeu, 0x10u, 0x3du, - 0xdfu, 0xe7u, 0x04u, 0x48u, 0xbfu, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0xdfu, 0xe7u, 0x04u, 0x48u, 0xbfu, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x21u, 0xc0u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x0fu, 0x26u, 0x04u, 0x00u, 0x01u, 0x91u, 0x15u, 0x00u, 0x1fu, 0x00u, 0x16u, 0x40u, 0x5eu, 0xd1u, 0x0au, 0x99u, 0xffu, 0xf7u, 0xe5u, 0xfeu, 0x10u, 0x23u, 0x3au, 0x00u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfeu, 0x10u, 0x23u, 0x09u, 0x22u, 0x31u, 0x00u, @@ -178,7 +178,7 @@ const uint8_t cy_m0p_image[] = { 0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x31u, 0xfeu, 0x10u, 0x3du, 0x00u, 0x2du, 0xe8u, 0xd1u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfdu, 0x10u, 0x22u, 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x10u, 0x23u, 0x00u, 0x22u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x20u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, - 0xe9u, 0xfdu, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0xe9u, 0xfdu, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x01u, 0xc0u, 0x10u, 0x41u, 0x18u, 0x00u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x1du, 0x00u, 0x8bu, 0xb0u, 0x04u, 0x92u, 0x6au, 0x78u, 0x1bu, 0x78u, 0x12u, 0x02u, 0x1au, 0x43u, 0xabu, 0x78u, 0x04u, 0x00u, 0x1bu, 0x04u, 0x1au, 0x43u, 0xebu, 0x78u, 0x2eu, 0x7au, 0x1bu, 0x06u, 0x13u, 0x43u, 0x6au, 0x79u, 0x06u, 0x93u, @@ -203,7 +203,7 @@ const uint8_t cy_m0p_image[] = { 0xf2u, 0xb2u, 0x0fu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x28u, 0xfdu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1du, 0xfdu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x04u, 0x4au, 0x1bu, 0x68u, - 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xb3u, 0xe7u, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0x10u, 0x00u, 0x66u, + 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xb3u, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0x10u, 0x00u, 0x66u, 0x10u, 0x10u, 0x00u, 0x67u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, 0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0xf7u, 0xb5u, @@ -230,34 +230,34 @@ const uint8_t cy_m0p_image[] = { 0xa0u, 0x36u, 0x80u, 0x33u, 0x33u, 0x60u, 0x03u, 0x9bu, 0x90u, 0x34u, 0x73u, 0x60u, 0x32u, 0x00u, 0x0cu, 0x99u, 0x28u, 0x00u, 0xb4u, 0x60u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x02u, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0x28u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x61u, 0xffu, 0x28u, 0x00u, 0x0bu, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0xffu, 0xf7u, - 0x8du, 0xffu, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x8du, 0xffu, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf1u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, 0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x06u, 0x4bu, 0x07u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, + 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa8u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x07u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x23u, 0x60u, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, + 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x23u, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x00u, 0x23u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x0bu, 0x60u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x14u, 0x4du, 0x15u, 0x4au, 0x2bu, 0x68u, 0x20u, 0x00u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x71u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2au, 0x68u, 0x0du, 0x49u, 0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x70u, 0x68u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, - 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x4bu, 0x23u, 0x60u, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, + 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x4bu, 0x23u, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0x11u, 0x10u, 0x10u, 0x41u, 0x70u, 0xb5u, 0x0eu, 0x00u, 0x11u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x9cu, 0x18u, 0x1au, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x10u, 0x2cu, 0x01u, 0xd8u, 0x34u, 0x60u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x48u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x28u, 0x00u, 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, - 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0xf0u, 0xb5u, 0x10u, 0x25u, 0x87u, 0xb0u, 0x0fu, 0x00u, 0x04u, 0x00u, 0x01u, 0x92u, 0x00u, 0x21u, 0x2au, 0x00u, - 0x02u, 0xa8u, 0x06u, 0xf0u, 0xbeu, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, + 0x02u, 0xa8u, 0x06u, 0xf0u, 0xd4u, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, 0x02u, 0xa9u, 0xeau, 0x1bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x18u, 0x4du, 0x19u, 0x4au, 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0fu, 0x2fu, 0x02u, 0xd8u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x10u, 0x22u, 0x31u, 0x00u, 0x20u, 0x00u, @@ -265,10 +265,10 @@ const uint8_t cy_m0p_image[] = { 0x0fu, 0x4au, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x09u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4du, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf8u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2au, 0x68u, 0x08u, 0x49u, 0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe4u, 0x18u, 0x23u, 0x68u, - 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x08u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x1eu, 0x00u, 0xa7u, 0xb0u, 0x2cu, 0xabu, 0x0au, 0xadu, 0x1fu, 0x78u, 0x02u, 0x91u, 0x03u, 0x92u, 0x00u, 0x21u, 0x70u, 0x22u, 0x28u, 0x00u, - 0x06u, 0xf0u, 0x67u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x62u, 0xf9u, 0x3au, 0x00u, + 0x06u, 0xf0u, 0x7du, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x78u, 0xf9u, 0x3au, 0x00u, 0x2eu, 0x9bu, 0x31u, 0x00u, 0x00u, 0x95u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf3u, 0xfbu, 0x2eu, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfbu, 0x06u, 0xabu, 0x04u, 0xa9u, 0x20u, 0x00u, 0x05u, 0x93u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x03u, 0x9bu, 0x02u, 0x9au, 0x04u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x60u, 0xffu, 0x20u, 0x00u, 0x2du, 0x9au, @@ -276,30 +276,30 @@ const uint8_t cy_m0p_image[] = { 0x0cu, 0x4cu, 0x7fu, 0x00u, 0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u, 0x3cu, 0x40u, 0xffu, 0x3fu, 0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u, 0xabu, 0x6au, 0xc3u, 0x18u, 0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x86u, 0x22u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x86u, 0x22u, 0x04u, 0x00u, 0x04u, 0x98u, 0xd2u, 0x00u, 0xa0u, 0x50u, 0x1au, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x04u, 0x23u, 0x00u, 0x22u, 0x58u, 0x21u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xceu, 0xfeu, 0x08u, 0x21u, 0x06u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0x13u, 0x6bu, 0xe4u, 0x18u, - 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0xdcu, 0x68u, 0x06u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, - 0x21u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x21u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x70u, 0x10u, 0xb5u, 0x0fu, 0x24u, 0x06u, 0x4bu, 0x19u, 0x68u, 0x8bu, 0x68u, 0xc2u, 0x18u, 0x13u, 0x68u, 0x23u, 0x40u, 0x06u, 0x2bu, 0xfbu, 0xd8u, 0xcbu, 0x68u, 0xc0u, 0x18u, 0xb0u, 0x23u, 0xdbu, 0x05u, - 0x03u, 0x60u, 0x10u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x80u, 0x27u, 0x0cu, 0x4cu, 0x7fu, 0x00u, + 0x03u, 0x60u, 0x10u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x80u, 0x27u, 0x0cu, 0x4cu, 0x7fu, 0x00u, 0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u, 0x3cu, 0x40u, 0xffu, 0x3fu, 0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u, 0xabu, 0x6au, 0xc3u, 0x18u, 0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xffu, 0x8cu, 0x23u, 0x04u, 0x9au, 0x5bu, 0x01u, 0xe2u, 0x50u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9bu, 0xffu, 0x04u, 0x4bu, 0x00u, 0x20u, 0x1bu, 0x68u, 0x1bu, 0x6bu, 0xe4u, 0x18u, - 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x7fu, 0xb5u, 0x0du, 0x00u, + 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x7fu, 0xb5u, 0x0du, 0x00u, 0x19u, 0x00u, 0x0eu, 0x4bu, 0x16u, 0x00u, 0x03u, 0x93u, 0x09u, 0x9au, 0x08u, 0x9bu, 0x04u, 0x00u, 0x02u, 0xf0u, 0xf1u, 0xfdu, 0x03u, 0xabu, 0x69u, 0x00u, 0x59u, 0x18u, 0x08u, 0x23u, 0x89u, 0x5du, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x02u, 0xf0u, 0x4eu, 0xfeu, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x02u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x7fu, 0xbdu, 0xc0u, 0x46u, 0x70u, 0x71u, 0x72u, 0x73u, - 0x20u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x05u, 0x93u, 0x20u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, + 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x05u, 0x93u, 0x20u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x04u, 0x91u, 0x03u, 0x92u, 0x1fu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1fu, 0x68u, 0x00u, 0x26u, 0x1bu, 0x4bu, 0xf2u, 0x00u, 0xd2u, 0x18u, 0x03u, 0x99u, 0x08u, 0x23u, 0x28u, 0x00u, 0x02u, 0xf0u, 0x9cu, 0xfeu, 0x44u, 0x1eu, 0xa0u, 0x41u, 0x44u, 0x42u, 0x17u, 0x48u, 0x17u, 0x4bu, 0x04u, 0x40u, 0x01u, 0x36u, 0xe4u, 0x18u, @@ -307,8 +307,8 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x9au, 0x02u, 0x99u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x4cu, 0xfeu, 0x08u, 0x36u, 0x0cu, 0x9au, 0x39u, 0x00u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x45u, 0xfeu, 0x02u, 0x9bu, 0x04u, 0x9au, 0x28u, 0x00u, 0x01u, 0x97u, 0x00u, 0x96u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x28u, 0x00u, 0x08u, 0x23u, 0x32u, 0x00u, - 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, - 0x20u, 0x72u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, + 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, + 0x48u, 0x72u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x07u, 0x93u, 0x25u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x06u, 0x91u, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x03u, 0x93u, 0x00u, 0x27u, 0x1fu, 0x4bu, 0x04u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x05u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, @@ -318,20 +318,20 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0xf6u, 0xfdu, 0x03u, 0x9fu, 0x03u, 0x9bu, 0x08u, 0x37u, 0x01u, 0x93u, 0x06u, 0x9au, 0x33u, 0x00u, 0x20u, 0x00u, 0x00u, 0x97u, 0x01u, 0x21u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x3au, 0x00u, 0x07u, 0x99u, 0x02u, 0xf0u, 0xe5u, 0xfdu, 0x28u, 0x00u, 0x09u, 0xb0u, 0xf0u, 0xbdu, - 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0x20u, 0x04u, 0x00u, 0x08u, 0x20u, 0x72u, 0x00u, 0x10u, + 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, 0x48u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0x86u, 0x25u, 0x6du, 0x01u, 0x44u, 0x59u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0xdcu, 0x68u, 0x05u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, 0x21u, 0x60u, - 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, + 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x06u, 0x4bu, 0x1cu, 0x68u, 0xa3u, 0x68u, 0xc2u, 0x18u, 0x13u, 0x68u, 0x2bu, 0x40u, 0x06u, 0x2bu, 0xfbu, 0xd8u, 0xe3u, 0x68u, 0x09u, 0x06u, 0xc0u, 0x18u, 0x01u, 0x60u, 0x30u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x0fu, 0x27u, 0x09u, 0x4cu, 0x26u, 0x68u, 0xb4u, 0x68u, 0x05u, 0x19u, + 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x0fu, 0x27u, 0x09u, 0x4cu, 0x26u, 0x68u, 0xb4u, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x3cu, 0x40u, 0x06u, 0x2cu, 0xfbu, 0xd8u, 0xf4u, 0x68u, 0x09u, 0x03u, 0x00u, 0x19u, 0x80u, 0x24u, 0xe4u, 0x05u, 0x22u, 0x43u, 0x11u, 0x43u, 0x1bu, 0x04u, 0x19u, 0x43u, 0x01u, 0x60u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x68u, 0x84u, 0x18u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x68u, 0x84u, 0x18u, 0x22u, 0x68u, 0x2au, 0x40u, 0x04u, 0x2au, 0xfbu, 0xd8u, 0xdau, 0x68u, 0x06u, 0x4cu, 0x82u, 0x18u, 0x14u, 0x60u, 0xdau, 0x68u, 0x82u, 0x18u, 0x11u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x23u, 0x03u, 0x60u, 0x30u, 0xbdu, - 0x20u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u, 0x00u, 0x25u, 0x01u, 0x91u, 0x1cu, 0x4bu, 0xeau, 0x00u, 0xd2u, 0x18u, 0x31u, 0x00u, 0x08u, 0x23u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xb2u, 0xfeu, 0x00u, 0x28u, 0x2cu, 0xd0u, 0x01u, 0x35u, 0x10u, 0x2du, 0xf2u, 0xd1u, 0x00u, 0x25u, 0x31u, 0x00u, 0x20u, 0x00u, 0x08u, 0x22u, 0xffu, 0xf7u, 0x85u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, @@ -339,7 +339,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x52u, 0x31u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x28u, 0x00u, - 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xa0u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x27u, 0x85u, 0xb0u, 0x02u, 0x91u, 0x00u, 0x92u, 0x03u, 0x93u, 0x26u, 0x4bu, 0x00u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x01u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x00u, 0x28u, 0x04u, 0xd0u, 0x01u, 0x9bu, 0x9du, 0x42u, @@ -350,15 +350,15 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x02u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x54u, 0x31u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x3cu, 0xffu, 0x28u, 0x00u, 0x05u, 0xb0u, - 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xa0u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x42u, 0x1eu, 0x03u, 0x00u, 0x00u, 0x20u, 0x04u, 0x2au, 0x03u, 0xd8u, 0x28u, 0x30u, 0x58u, 0x43u, 0x01u, 0x4bu, - 0xc0u, 0x18u, 0x70u, 0x47u, 0x20u, 0x73u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0xc0u, 0x18u, 0x70u, 0x47u, 0x48u, 0x73u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xf2u, 0xf9u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0x28u, 0x06u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0xadu, 0xb0u, 0x04u, 0x00u, 0x04u, 0x91u, 0x05u, 0x92u, 0x03u, 0x93u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x15u, 0xe1u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x11u, 0xe1u, 0x32u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x0du, 0xe1u, 0x33u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x09u, 0xe1u, 0x32u, 0x9bu, 0x58u, 0x78u, 0xffu, 0xf7u, @@ -396,7 +396,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x00u, 0xd0u, 0x71u, 0xe7u, 0x03u, 0x9bu, 0xe9u, 0x1du, 0xc9u, 0x08u, 0x59u, 0x18u, 0x0au, 0x22u, 0x2bu, 0x00u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xc4u, 0xf8u, 0x68u, 0xe7u, 0x08u, 0x4eu, 0x6bu, 0xe7u, 0x07u, 0x4eu, 0x6eu, 0xe7u, 0x07u, 0x4eu, 0x6cu, 0xe7u, 0xc0u, 0x46u, 0x09u, 0x80u, 0x00u, 0x00u, 0x01u, 0x00u, 0x32u, 0x00u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, + 0x28u, 0x06u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0x0fu, 0x1eu, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0xd1u, 0x8bu, 0xe1u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x88u, 0xe1u, 0x0cu, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x84u, 0xe1u, 0x0du, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x80u, 0xe1u, 0x58u, 0x78u, 0xffu, 0xf7u, 0x78u, 0xfeu, @@ -448,11 +448,11 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x7au, 0xffu, 0x00u, 0x28u, 0x09u, 0xd0u, 0x01u, 0x23u, 0x0cu, 0x9au, 0x13u, 0x70u, 0x0eu, 0x49u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x27u, 0xfdu, 0x38u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x0cu, 0x9bu, 0x18u, 0x70u, 0xf5u, 0xe7u, 0x04u, 0x4fu, 0x09u, 0x49u, 0xf3u, 0xe7u, 0x02u, 0x4fu, 0xf4u, 0xe7u, - 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0x28u, 0x06u, 0x00u, 0x08u, 0x80u, 0x80u, 0x00u, 0x00u, 0x08u, 0x60u, 0x00u, 0x00u, 0x06u, 0x80u, 0x00u, 0x00u, 0xf1u, 0x7eu, 0x00u, 0x00u, 0x30u, 0x60u, 0x00u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0x28u, 0x06u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x85u, 0xb0u, 0x08u, 0x00u, 0x02u, 0x91u, 0x03u, 0x92u, 0x1eu, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xfcu, 0x07u, 0x1eu, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x77u, 0xe0u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x74u, 0xe0u, 0x73u, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x70u, 0xe0u, 0xb3u, 0x68u, @@ -476,25 +476,25 @@ const uint8_t cy_m0p_image[] = { 0x12u, 0x01u, 0x13u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x36u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x44u, 0xfeu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, - 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, - 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, + 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, + 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x0fu, 0xfeu, 0x10u, 0xbdu, 0x0fu, 0x23u, 0x13u, 0x43u, - 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, + 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x05u, 0xd8u, 0x05u, 0x4bu, 0x21u, 0x22u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0xc0u, 0xc0u, 0x00u, 0x00u, 0xcfu, 0xc0u, 0x00u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x10u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0xeau, 0xfdu, 0x10u, 0xbdu, 0x09u, 0x03u, 0x0bu, 0x00u, 0x13u, 0x43u, 0x00u, 0x22u, 0x10u, 0xb5u, 0x11u, 0x00u, 0x01u, 0xf0u, 0xe1u, 0xfdu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, + 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, 0x07u, 0x4au, 0x15u, 0x68u, 0x24u, 0x22u, 0x29u, 0x35u, 0x2du, 0x78u, 0x1fu, 0x2du, 0x00u, 0xd9u, 0x01u, 0x3au, 0x24u, 0x01u, 0x23u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xa5u, 0xfdu, 0x70u, 0xbdu, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, + 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x23u, 0x10u, 0xb5u, 0x11u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0x95u, 0xfdu, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x1bu, 0x4du, 0xffu, 0xf7u, 0x9fu, 0xffu, 0x20u, 0x00u, 0x01u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x9cu, 0xffu, 0x2au, 0x00u, @@ -527,7 +527,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x70u, 0xfeu, 0x94u, 0x4bu, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x0bu, 0xd0u, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x00u, 0xf0u, 0x35u, 0xfdu, 0x0eu, 0x9bu, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x00u, 0xf0u, 0x24u, 0xfdu, 0x8du, 0x4bu, 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0x01u, 0xd9u, 0x00u, 0xf0u, - 0x1du, 0xfdu, 0x04u, 0xf0u, 0x79u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, + 0x1du, 0xfdu, 0x04u, 0xf0u, 0x8fu, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xfeu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xfeu, 0x80u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xfeu, 0xc0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9du, 0xfeu, 0xc0u, 0x22u, @@ -561,7 +561,7 @@ const uint8_t cy_m0p_image[] = { 0x43u, 0xfdu, 0x16u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x9du, 0xfbu, 0x03u, 0x23u, 0x02u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfdu, 0x09u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x91u, 0xfbu, 0x00u, 0x21u, 0x06u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x01u, 0xf0u, - 0x8bu, 0xfbu, 0x0eu, 0x21u, 0x70u, 0xe7u, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x1cu, 0x04u, 0x00u, 0x08u, + 0x8bu, 0xfbu, 0x0eu, 0x21u, 0x70u, 0xe7u, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x14u, 0x04u, 0x00u, 0x08u, 0x4eu, 0x00u, 0x40u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x30u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0x10u, 0x20u, 0x00u, 0x00u, 0x2eu, 0x00u, 0x40u, 0x00u, 0x2eu, 0x20u, 0x30u, 0x00u, 0x2eu, 0x20u, 0x40u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xfdu, 0x01u, 0x22u, 0x0au, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu, @@ -692,7 +692,7 @@ const uint8_t cy_m0p_image[] = { 0x8bu, 0xffu, 0x00u, 0x21u, 0x44u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x85u, 0xffu, 0xe0u, 0x21u, 0x49u, 0x00u, 0xffu, 0xf7u, 0x69u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xeau, 0xf9u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xf9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdcu, 0xf9u, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x42u, 0x4bu, - 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x44u, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, + 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x5au, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, 0xd1u, 0x00u, 0xc7u, 0x01u, 0xedu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xf9u, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x73u, 0xf9u, 0x02u, 0x22u, 0x00u, 0x21u, 0xffu, 0x32u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x80u, 0x22u, 0x01u, 0x21u, @@ -708,7 +708,7 @@ const uint8_t cy_m0p_image[] = { 0x0bu, 0xffu, 0x00u, 0x21u, 0x0eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x05u, 0xffu, 0x03u, 0x21u, 0xffu, 0xf7u, 0xeau, 0xfau, 0x9eu, 0x00u, 0x40u, 0x00u, 0x9eu, 0x90u, 0x30u, 0x00u, 0x82u, 0x70u, 0x00u, 0x00u, 0x73u, 0x70u, 0x00u, 0x00u, 0x9eu, 0x90u, 0x40u, 0x00u, 0x72u, 0x70u, 0x00u, 0x00u, 0x70u, 0x70u, 0x00u, 0x00u, - 0x71u, 0x70u, 0x00u, 0x00u, 0x60u, 0x70u, 0x00u, 0x00u, 0x1cu, 0x04u, 0x00u, 0x08u, 0x12u, 0x10u, 0x00u, 0x00u, + 0x71u, 0x70u, 0x00u, 0x00u, 0x60u, 0x70u, 0x00u, 0x00u, 0x14u, 0x04u, 0x00u, 0x08u, 0x12u, 0x10u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0x20u, 0x00u, 0x01u, 0x22u, 0x04u, 0x21u, 0xffu, 0xf7u, 0xf9u, 0xf8u, 0x20u, 0x00u, 0x00u, 0x22u, 0x05u, 0x21u, 0xffu, 0xf7u, 0xf4u, 0xf8u, 0x42u, 0x22u, 0x20u, 0x00u, 0xffu, 0x32u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0xa0u, 0x22u, 0x20u, 0x00u, 0x52u, 0x00u, @@ -719,7 +719,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xb0u, 0xfeu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x01u, 0x23u, 0xffu, 0xf7u, 0x5du, 0xf8u, 0x20u, 0x00u, 0x03u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xf8u, 0x01u, 0x23u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3eu, 0xf8u, 0x7fu, 0xe7u, 0x1cu, 0x22u, - 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x44u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, + 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x5au, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xf8u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xf8u, 0xe0u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xf8u, 0xf0u, 0x22u, 0x00u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xf8u, 0x80u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, @@ -750,7 +750,7 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x69u, 0xffu, 0x3eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xb0u, 0xfdu, 0x00u, 0x21u, 0x3eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xaau, 0xfdu, 0x23u, 0x21u, 0xffu, 0xf7u, 0x8fu, 0xf9u, 0x39u, 0x49u, 0x11u, 0x22u, 0x1cu, 0x31u, - 0x01u, 0xa8u, 0x04u, 0xf0u, 0x4du, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, + 0x01u, 0xa8u, 0x04u, 0xf0u, 0x63u, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb0u, 0xffu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xabu, 0xffu, 0x31u, 0x4au, 0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xafu, 0xffu, 0xf0u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa9u, 0xffu, 0x81u, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa4u, 0xffu, @@ -764,7 +764,7 @@ const uint8_t cy_m0p_image[] = { 0x4bu, 0xfdu, 0x04u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf8u, 0xfeu, 0x4eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x3fu, 0xfdu, 0x00u, 0x21u, 0x07u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x39u, 0xfdu, 0x43u, 0x21u, 0xffu, 0xf7u, 0x1eu, 0xf9u, 0x12u, 0x10u, 0x00u, 0x00u, - 0x15u, 0x79u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, + 0x3du, 0x79u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0xfeu, 0xf7u, 0xdau, 0xfeu, 0x09u, 0x4bu, 0x26u, 0x01u, 0x33u, 0x43u, 0x28u, 0x00u, 0x3du, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x1fu, 0xfdu, 0x24u, 0x03u, 0x05u, 0x4bu, 0x34u, 0x43u, 0x28u, 0x00u, 0x23u, 0x43u, 0x37u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x16u, 0xfdu, 0x70u, 0xbdu, 0xc0u, 0x46u, @@ -776,7 +776,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xfcu, 0x0bu, 0x4bu, 0x2du, 0x03u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x07u, 0xd8u, 0x2bu, 0x00u, 0x26u, 0x22u, 0x3bu, 0x43u, 0x30u, 0x00u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xddu, 0xfcu, 0xf8u, 0xbdu, 0x0fu, 0x23u, 0x2bu, 0x43u, 0x3bu, 0x43u, 0x25u, 0x22u, 0xf5u, 0xe7u, 0xc0u, 0x46u, 0x0eu, 0x00u, 0x80u, 0x00u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, + 0x28u, 0x06u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x0du, 0x00u, 0xfeu, 0xf7u, 0xd5u, 0xfeu, 0x3au, 0x00u, 0x07u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd7u, 0xfeu, 0x32u, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd2u, 0xfeu, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xcdu, 0xfeu, 0x06u, 0x9au, 0x09u, 0x21u, @@ -871,16 +871,16 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x90u, 0x08u, 0x22u, 0x00u, 0x97u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd0u, 0xfeu, 0x01u, 0x22u, 0x05u, 0x9bu, 0x13u, 0x42u, 0x0au, 0xd0u, 0x0bu, 0x23u, 0x01u, 0x93u, 0x01u, 0x3bu, 0x00u, 0x93u, 0x02u, 0x97u, 0x01u, 0x3bu, 0x07u, 0x32u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0eu, 0xfeu, 0x01u, 0x35u, 0xcdu, 0xe7u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x28u, 0x06u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0x80u, 0x22u, 0x0du, 0x4bu, 0x52u, 0x00u, 0x90u, 0x42u, 0x11u, 0xd0u, 0x07u, 0xd8u, 0x01u, 0x22u, 0xc0u, 0x28u, 0x0eu, 0xd0u, 0x02u, 0x22u, 0xe0u, 0x28u, 0x0bu, 0xd0u, 0x00u, 0x22u, 0x09u, 0xe0u, 0xc0u, 0x22u, 0x52u, 0x00u, 0x90u, 0x42u, 0x07u, 0xd0u, 0x05u, 0x4au, 0x90u, 0x42u, 0xf6u, 0xd1u, 0x05u, 0x22u, 0x00u, 0xe0u, 0x03u, 0x22u, - 0x1au, 0x70u, 0x70u, 0x47u, 0x04u, 0x22u, 0xfbu, 0xe7u, 0x1cu, 0x04u, 0x00u, 0x08u, 0x09u, 0x02u, 0x00u, 0x00u, + 0x1au, 0x70u, 0x70u, 0x47u, 0x04u, 0x22u, 0xfbu, 0xe7u, 0x14u, 0x04u, 0x00u, 0x08u, 0x09u, 0x02u, 0x00u, 0x00u, 0x01u, 0x4bu, 0x18u, 0x70u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x05u, 0x98u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2fu, 0xffu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x62u, 0xfbu, 0x13u, 0xbdu, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x93u, 0xb0u, 0x05u, 0x93u, 0x1au, 0xabu, 0x1cu, 0x78u, 0x65u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x03u, 0x91u, 0x04u, 0x92u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, - 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x43u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, + 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x59u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, 0x22u, 0x00u, 0xffu, 0x33u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0xfcu, 0xfbu, 0x04u, 0x1eu, 0x00u, 0xd0u, 0x86u, 0xe0u, 0x33u, 0x00u, 0x80u, 0x33u, 0x01u, 0x93u, 0x98u, 0x23u, 0x01u, 0x9au, 0xdbu, 0x00u, 0x77u, 0x1cu, 0xf6u, 0x50u, 0xffu, 0x37u, 0xf3u, 0x18u, 0x5au, 0x60u, 0x9fu, 0x60u, 0x19u, 0x9au, 0x09u, 0x9bu, 0x9au, 0x42u, @@ -904,10 +904,10 @@ const uint8_t cy_m0p_image[] = { 0x28u, 0x00u, 0x00u, 0xf0u, 0xa7u, 0xfbu, 0x02u, 0x9au, 0x09u, 0x9bu, 0x9bu, 0x1au, 0x19u, 0x9au, 0x9bu, 0xb2u, 0xb9u, 0x18u, 0x89u, 0xe7u, 0x02u, 0x9bu, 0x18u, 0x9au, 0x39u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x9au, 0xfbu, 0x86u, 0xe7u, 0xfau, 0x5cu, 0x01u, 0x9cu, 0x4au, 0x40u, 0xf2u, 0x54u, 0xfau, 0x5cu, 0x42u, 0x40u, 0xe2u, 0x54u, - 0x01u, 0x33u, 0x80u, 0xe7u, 0x20u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, + 0x01u, 0x33u, 0x80u, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, 0x04u, 0x92u, 0x93u, 0x22u, 0x05u, 0x93u, 0x13u, 0xaeu, 0xaeu, 0xabu, 0x1cu, 0x78u, 0x03u, 0x91u, 0x92u, 0x00u, - 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x75u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, - 0x70u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, + 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x8bu, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, + 0x86u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, 0x3bu, 0xd1u, 0x90u, 0x23u, 0x9bu, 0x00u, 0xf6u, 0x50u, 0x33u, 0xaau, 0x04u, 0x33u, 0xf2u, 0x50u, 0x0au, 0x9fu, 0x04u, 0x33u, 0x53u, 0xaau, 0xf2u, 0x50u, 0x10u, 0x9bu, 0xbeu, 0xb2u, 0x01u, 0x93u, 0x02u, 0x00u, 0x33u, 0x00u, 0x53u, 0xa9u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x6eu, 0xfcu, 0xadu, 0x9bu, 0xbbu, 0x42u, 0x2eu, 0xd9u, 0x07u, 0xa9u, @@ -937,10 +937,10 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0x43u, 0x33u, 0x60u, 0x00u, 0x2du, 0x01u, 0xd1u, 0x00u, 0x29u, 0x12u, 0xd0u, 0x80u, 0x22u, 0xa3u, 0x68u, 0x52u, 0x02u, 0xc3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd0u, 0x23u, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0x20u, 0x04u, 0x00u, 0x08u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x22u, 0x0eu, 0x21u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0du, 0x21u, 0xffu, 0xf7u, 0xdfu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0bu, 0x21u, 0xffu, 0xf7u, 0xd5u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0au, 0x21u, @@ -951,10 +951,10 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa8u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xffu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xffu, 0x03u, 0x4bu, 0x0fu, 0x21u, 0x1au, 0x68u, 0x20u, 0x00u, - 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0x24u, 0x04u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, + 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0x1cu, 0x04u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x04u, 0x4bu, 0x1fu, 0x2au, 0x00u, 0xd9u, 0x04u, 0x4bu, 0x04u, 0x4au, 0x13u, 0x60u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x44u, 0x79u, 0x00u, 0x10u, 0x98u, 0x79u, 0x00u, 0x10u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x6cu, 0x79u, 0x00u, 0x10u, 0xc0u, 0x79u, 0x00u, 0x10u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, 0x00u, 0x29u, 0x09u, 0xd1u, 0x00u, 0x2cu, 0x28u, 0xd1u, 0x13u, 0x6du, 0xc1u, 0x18u, 0x2au, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x6cu, 0x00u, 0x29u, 0x21u, 0xd0u, 0xa4u, 0x00u, 0x28u, 0x4bu, 0x65u, 0x1eu, 0x9du, 0x42u, 0x1cu, 0xd8u, 0x80u, 0x23u, 0x1bu, 0x01u, 0x9cu, 0x42u, 0x3eu, 0xd0u, 0x0du, 0xd8u, 0x80u, 0x23u, 0x9bu, 0x00u, 0x9cu, 0x42u, @@ -966,8 +966,8 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xd1u, 0x1fu, 0x2eu, 0x02u, 0xd9u, 0x10u, 0x4du, 0x1bu, 0x02u, 0x43u, 0x51u, 0x93u, 0x6bu, 0xa2u, 0x08u, 0xc3u, 0x18u, 0x19u, 0x60u, 0x0fu, 0x21u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x00u, 0x20u, 0x0bu, 0x4bu, 0x1cu, 0x60u, 0x70u, 0xbdu, 0x7cu, 0x23u, 0xe4u, 0xe7u, 0x78u, 0x23u, 0xe2u, 0xe7u, 0x60u, 0x23u, 0xe0u, 0xe7u, 0x40u, 0x23u, - 0xdeu, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x2cu, 0x06u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, - 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0x24u, 0x04u, 0x00u, 0x08u, + 0xdeu, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, + 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0x1cu, 0x04u, 0x00u, 0x08u, 0x20u, 0x4bu, 0x21u, 0x49u, 0x1bu, 0x68u, 0x09u, 0x68u, 0x9au, 0x6cu, 0x92u, 0x00u, 0x00u, 0x29u, 0x1cu, 0xd0u, 0x1eu, 0x49u, 0x09u, 0x68u, 0x00u, 0x29u, 0x18u, 0xd0u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2fu, 0xd9u, 0x1bu, 0x4bu, 0xc3u, 0x58u, 0x5bu, 0x04u, 0x5bu, 0x0eu, 0x70u, 0x2bu, 0x1du, 0xd0u, 0x08u, 0xd8u, 0x40u, 0x2bu, @@ -976,89 +976,89 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0xd0u, 0x7fu, 0x2bu, 0xf9u, 0xd1u, 0x80u, 0x22u, 0x52u, 0x00u, 0xf6u, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x01u, 0xf3u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x01u, 0xf0u, 0xe7u, 0x80u, 0x22u, 0x52u, 0x01u, 0xedu, 0xe7u, 0x80u, 0x22u, 0x12u, 0x01u, 0xeau, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x00u, 0xe7u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x00u, 0xe4u, 0xe7u, - 0x0au, 0x00u, 0xe2u, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x20u, 0x04u, 0x00u, 0x08u, 0x24u, 0x04u, 0x00u, 0x08u, + 0x0au, 0x00u, 0xe2u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x18u, 0x04u, 0x00u, 0x08u, 0x1cu, 0x04u, 0x00u, 0x08u, 0x88u, 0x14u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x17u, 0x4au, 0x18u, 0x49u, 0x13u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x17u, 0xd8u, 0x16u, 0x4bu, 0x23u, 0x60u, 0x01u, 0x20u, 0x09u, 0x68u, 0x4bu, 0x6bu, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x13u, 0x68u, 0x09u, 0x6du, 0x9au, 0x6cu, 0x61u, 0x18u, 0x92u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x23u, 0x68u, 0x0bu, 0x48u, 0x03u, 0x40u, 0x23u, 0x60u, 0x0bu, 0x68u, 0x0au, 0x48u, 0x5bu, 0x68u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x80u, 0x23u, 0x20u, 0x68u, - 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0x24u, 0x04u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, + 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0x1cu, 0x04u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, 0x01u, 0x00u, 0x02u, 0x00u, 0x03u, 0x23u, 0x03u, 0x70u, 0x00u, 0x20u, 0x70u, 0x47u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x00u, 0x23u, 0x03u, 0x60u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x20u, 0x03u, 0x4bu, - 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x24u, 0x04u, 0x00u, 0x08u, + 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x1cu, 0x04u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x01u, 0x29u, 0x0bu, 0xd9u, 0x01u, 0x22u, 0x0au, 0x40u, 0x54u, 0x42u, 0x62u, 0x41u, 0xcbu, 0x0fu, 0x5bu, 0x18u, 0x5bu, 0x10u, 0x9bu, 0x1au, 0x02u, 0x00u, 0x01u, 0x39u, 0x8bu, 0x42u, 0x00u, 0xdbu, 0x30u, 0xbdu, 0x14u, 0x78u, 0x45u, 0x5cu, 0x15u, 0x70u, 0x44u, 0x54u, 0x01u, 0x32u, 0x01u, 0x39u, 0xf5u, 0xe7u, 0x00u, 0x00u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xffu, + 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x80u, 0x21u, 0x05u, 0x4bu, 0xc9u, 0x05u, 0x1au, 0x68u, 0xd3u, 0x68u, 0xe3u, 0x18u, - 0x19u, 0x60u, 0xd3u, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x19u, 0x60u, 0xd3u, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xffu, 0x05u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, - 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, + 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0x41u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x07u, 0x4bu, 0x08u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, - 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0x02u, 0x00u, 0x42u, + 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0x02u, 0x00u, 0x42u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x03u, 0x28u, 0xfau, 0xd8u, 0x09u, 0x4bu, 0x0au, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x06u, 0x9bu, 0x23u, 0x60u, 0xf8u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, + 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x06u, 0x9bu, 0x23u, 0x60u, 0xf8u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0x32u, 0x00u, 0x43u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x80u, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x00u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0xb3u, 0x40u, 0x1cu, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x06u, 0xabu, 0x1eu, 0x78u, + 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x06u, 0xabu, 0x1eu, 0x78u, 0x38u, 0x00u, 0xffu, 0xf7u, 0x55u, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x02u, 0x21u, 0x1bu, 0x68u, 0xb1u, 0x40u, 0xd8u, 0x68u, 0x01u, 0x23u, 0xabu, 0x40u, 0x24u, 0x06u, 0x19u, 0x43u, 0x38u, 0x18u, 0x21u, 0x43u, - 0x01u, 0x60u, 0xf8u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x06u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, + 0x01u, 0x60u, 0xf8u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x06u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x3du, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x02u, 0x21u, 0x08u, 0x4bu, 0x05u, 0x9au, 0x1bu, 0x68u, 0x24u, 0x06u, 0xd8u, 0x68u, 0x04u, 0x9bu, 0x30u, 0x18u, 0x99u, 0x40u, 0x01u, 0x23u, 0xabu, 0x40u, 0x19u, 0x43u, 0x03u, 0x23u, 0x93u, 0x40u, 0x19u, 0x43u, 0x21u, 0x43u, 0x01u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x00u, 0x2bu, 0x13u, 0xd0u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x00u, 0x2bu, 0x13u, 0xd0u, 0x02u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x56u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x50u, 0x21u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, - 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x10u, 0x00u, 0x1au, 0x1eu, 0x13u, 0xd0u, 0x03u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x39u, 0xffu, 0x0cu, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x51u, 0x21u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0x13u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x13u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, 0x15u, 0xd0u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x08u, 0x23u, 0x00u, 0x22u, 0x00u, 0x93u, 0x52u, 0x21u, 0x04u, 0x3bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7eu, 0xffu, 0x10u, 0x22u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd1u, 0xc0u, 0x23u, 0x5bu, 0x00u, 0xe0u, 0x58u, 0x16u, 0xbdu, - 0x20u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0xabu, + 0x18u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0xabu, 0x1bu, 0x88u, 0x00u, 0x2bu, 0x15u, 0xd0u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xffu, 0x0cu, 0x23u, 0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u, 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x53u, 0x21u, 0xffu, 0xf7u, 0x73u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0x13u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, - 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x20u, 0x04u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x13u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, + 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u, 0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbbu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, - 0x20u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x1eu, + 0x18u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x1eu, 0x22u, 0xd0u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xb4u, 0xffu, 0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u, 0x10u, 0x24u, 0x33u, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u, 0xa4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0cu, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0du, 0x4au, 0x1bu, 0x68u, 0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8au, 0xffu, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x7cu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, - 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x08u, 0xc0u, 0x00u, 0x40u, + 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0xc0u, 0x00u, 0x40u, 0x08u, 0xc0u, 0x10u, 0x40u, 0xf8u, 0xb5u, 0x05u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x1eu, 0x1eu, 0xd0u, 0x1au, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x3cu, 0x00u, 0x0fu, 0x2cu, 0x19u, 0xd8u, 0x10u, 0x24u, 0x3bu, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u, 0xe4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0du, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x54u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0eu, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u, 0xdbu, 0x68u, 0x24u, 0x04u, 0xebu, 0x18u, 0x14u, 0x43u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0xf8u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x42u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u, - 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xa4u, 0xb2u, 0xd4u, 0xe7u, 0x20u, 0x04u, 0x00u, 0x08u, + 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xa4u, 0xb2u, 0xd4u, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, 0x00u, 0xc0u, 0x00u, 0x42u, 0x00u, 0xc0u, 0x10u, 0x42u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x14u, 0x00u, 0x1eu, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, 0x2du, 0xd0u, 0x8cu, 0x23u, 0x00u, 0x22u, 0x5bu, 0x01u, 0xeau, 0x50u, 0x28u, 0x00u, 0x0au, 0x00u, 0x33u, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x33u, 0xffu, 0x22u, 0x00u, 0x33u, 0x00u, 0x09u, 0x21u, @@ -1068,7 +1068,7 @@ const uint8_t cy_m0p_image[] = { 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x08u, 0xffu, 0x8cu, 0x23u, 0x5bu, 0x01u, 0xe8u, 0x58u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x05u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd3u, 0xe7u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x98u, 0x00u, 0x00u, 0x43u, 0x98u, 0x00u, 0x10u, 0x43u, 0xf8u, 0xb5u, 0x1fu, 0x00u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x98u, 0x00u, 0x00u, 0x43u, 0x98u, 0x00u, 0x10u, 0x43u, 0xf8u, 0xb5u, 0x1fu, 0x00u, 0x06u, 0xabu, 0x1eu, 0x88u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x00u, 0x2eu, 0x29u, 0xd0u, 0x33u, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xfeu, 0x33u, 0x00u, 0x3au, 0x00u, 0x09u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xe8u, 0xfeu, 0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x0du, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u, @@ -1077,37 +1077,37 @@ const uint8_t cy_m0p_image[] = { 0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xfeu, 0xf8u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xb0u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x98u, 0xc0u, 0x00u, 0x41u, 0x98u, 0xc0u, 0x10u, 0x41u, 0x10u, 0xb5u, 0x80u, 0x24u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x98u, 0xc0u, 0x00u, 0x41u, 0x98u, 0xc0u, 0x10u, 0x41u, 0x10u, 0xb5u, 0x80u, 0x24u, 0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u, 0x42u, 0x50u, 0x82u, 0x22u, 0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x15u, 0x00u, 0xffu, 0xf7u, 0x3fu, 0xfdu, 0x00u, 0x22u, 0x5cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfdu, 0x20u, 0x21u, 0x06u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, - 0x93u, 0x69u, 0xe4u, 0x18u, 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x93u, 0x69u, 0xe4u, 0x18u, 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x80u, 0x24u, 0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u, 0x42u, 0x50u, 0x82u, 0x22u, 0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x83u, 0x23u, 0x9bu, 0x00u, 0x10u, 0xb5u, 0xc1u, 0x50u, 0x01u, 0x21u, 0x04u, 0x33u, 0xc1u, 0x50u, 0x06u, 0x4bu, 0x19u, 0x68u, 0x0bu, 0x68u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0x8bu, 0x69u, 0xc0u, 0x18u, - 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, + 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xffu, 0xf7u, 0x05u, 0xfeu, 0x10u, 0xbdu, - 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, + 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, - 0xfau, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, + 0xfau, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xffu, 0xf7u, - 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x03u, 0x34u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xd6u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xc5u, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x09u, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x0bu, 0x43u, 0x21u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x8du, 0xfau, 0x10u, 0xbdu, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x1du, 0x00u, 0x5eu, 0x1cu, 0x01u, 0x92u, 0x0fu, 0x00u, 0x32u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xccu, 0xffu, 0x32u, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x32u, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x2au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1120,7 +1120,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x2au, 0xfau, 0x0du, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x24u, 0xfau, 0x33u, 0x00u, 0x3au, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfau, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x02u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, - 0x01u, 0x3du, 0xd9u, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, + 0x01u, 0x3du, 0xd9u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x9eu, 0x00u, 0x91u, 0x15u, 0x00u, 0x01u, 0x21u, 0x72u, 0x1cu, 0x77u, 0x00u, 0x01u, 0x93u, 0xffu, 0xf7u, 0x63u, 0xffu, 0x3au, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5eu, 0xffu, 0x3au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x59u, 0xffu, 0x32u, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, @@ -1142,7 +1142,7 @@ const uint8_t cy_m0p_image[] = { 0x7bu, 0xf9u, 0x20u, 0x00u, 0x10u, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x75u, 0xf9u, 0x00u, 0x9bu, 0x20u, 0x00u, 0x1au, 0x03u, 0x02u, 0x23u, 0x00u, 0x21u, 0x13u, 0x43u, 0x30u, 0x22u, 0xffu, 0xf7u, 0x6cu, 0xf9u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, 0x3au, 0x10u, 0x00u, 0x00u, - 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, + 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0x28u, 0x06u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, 0x10u, 0x10u, 0x00u, 0x00u, 0x21u, 0x30u, 0x00u, 0x00u, 0x23u, 0x00u, 0x30u, 0x00u, 0x28u, 0x30u, 0x00u, 0x00u, 0xf7u, 0xb5u, 0x06u, 0x00u, 0x1cu, 0x00u, 0x09u, 0x9bu, 0x01u, 0x91u, 0x5fu, 0x00u, 0x15u, 0x00u, 0x02u, 0x21u, 0x3au, 0x00u, 0xffu, 0xf7u, 0xabu, 0xfeu, 0x3au, 0x00u, 0x03u, 0x21u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xfeu, @@ -1160,7 +1160,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xf8u, 0x01u, 0x9bu, 0x30u, 0x00u, 0x1cu, 0x03u, 0x0du, 0x4bu, 0x30u, 0x22u, 0x23u, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xe2u, 0xf8u, 0xc0u, 0x23u, 0x9bu, 0x03u, 0x30u, 0x00u, 0x23u, 0x43u, 0x30u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xdau, 0xf8u, 0x30u, 0x00u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x30u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, 0x01u, 0x00u, 0x40u, 0x00u, 0xf8u, 0xb5u, 0x1du, 0x00u, 0x00u, 0x23u, 0x16u, 0x00u, 0x0fu, 0x00u, 0x10u, 0x22u, 0x19u, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xc0u, 0xf8u, 0xe0u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x11u, 0x00u, 0x3bu, 0x43u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb8u, 0xf8u, 0x90u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x33u, 0x43u, @@ -1183,8 +1183,8 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5cu, 0xfdu, 0x33u, 0x68u, 0x2cu, 0x22u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x0eu, 0x4bu, 0xa8u, 0xe7u, 0x0eu, 0x4bu, 0x25u, 0x22u, 0xeau, 0xe7u, 0xe0u, 0x21u, 0x20u, 0x00u, 0x89u, 0x01u, 0xffu, 0xf7u, 0x79u, 0xfdu, 0x00u, 0x23u, 0x11u, 0x22u, 0x19u, 0x00u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0x2cu, 0x06u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, - 0x09u, 0xc0u, 0x00u, 0x00u, 0x20u, 0x04u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0x28u, 0x06u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, + 0x09u, 0xc0u, 0x00u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, 0x0au, 0xe0u, 0x00u, 0x00u, 0xdfu, 0xd0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x06u, 0x00u, 0x0fu, 0x00u, 0x02u, 0x93u, 0x0au, 0x9du, 0x0bu, 0x98u, 0x06u, 0x2au, 0x37u, 0xd8u, 0x21u, 0x4bu, 0x91u, 0x00u, 0xc9u, 0x58u, 0x20u, 0x4cu, 0x21u, 0x4bu, 0xa4u, 0x5cu, 0x9bu, 0x5cu, 0x01u, 0x22u, 0x3au, 0x70u, 0x1au, 0x19u, 0x0bu, 0x32u, @@ -1195,7 +1195,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x12u, 0xd1u, 0x00u, 0x9au, 0xa3u, 0xb2u, 0xaau, 0x18u, 0x02u, 0x99u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb5u, 0xfcu, 0x00u, 0x28u, 0x09u, 0xd1u, 0x38u, 0x70u, 0x07u, 0xe0u, 0x00u, 0x24u, 0x23u, 0x00u, 0x21u, 0x00u, 0xcau, 0xe7u, 0x01u, 0x30u, 0x42u, 0x78u, 0xffu, 0x2au, 0xe0u, 0xd0u, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, - 0xecu, 0x79u, 0x00u, 0x10u, 0x0fu, 0x7au, 0x00u, 0x10u, 0x08u, 0x7au, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, + 0x14u, 0x7au, 0x00u, 0x10u, 0x37u, 0x7au, 0x00u, 0x10u, 0x30u, 0x7au, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, 0x09u, 0x93u, 0x8bu, 0x68u, 0x04u, 0x00u, 0x05u, 0x93u, 0xcbu, 0x68u, 0x08u, 0x92u, 0x06u, 0x93u, 0x0bu, 0x68u, 0x4fu, 0x68u, 0x07u, 0x93u, 0x0bu, 0x69u, 0x8du, 0x69u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x93u, 0xb3u, 0x4bu, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1242,10 +1242,10 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x4eu, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xfbu, 0x0du, 0x23u, 0x00u, 0x97u, 0x1au, 0x00u, 0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x44u, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfbu, 0x01u, 0x3du, 0x93u, 0xe7u, 0x0du, 0x23u, 0x05u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x39u, 0xfcu, 0x20u, 0x00u, - 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x06u, 0x60u, 0x00u, 0x00u, 0x05u, 0x50u, 0x00u, 0x00u, 0x07u, 0x70u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x09u, 0xa0u, 0x00u, 0x00u, 0x0au, 0xc0u, 0x00u, 0x00u, 0x0bu, 0x50u, 0x00u, 0x00u, 0x07u, 0xb0u, 0x00u, 0x00u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, + 0x28u, 0x06u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, 0x87u, 0xb0u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x00u, 0x04u, 0x93u, 0x8bu, 0x69u, 0x0fu, 0x68u, 0x05u, 0x93u, 0x34u, 0x4bu, 0x4du, 0x68u, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x3du, 0xffu, 0x31u, 0x00u, 0x82u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfbu, @@ -1260,13 +1260,13 @@ const uint8_t cy_m0p_image[] = { 0x0eu, 0x22u, 0x00u, 0xf0u, 0xcdu, 0xfdu, 0x2bu, 0x00u, 0x32u, 0x00u, 0x20u, 0x00u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xf9u, 0xfcu, 0x2bu, 0x00u, 0x0cu, 0x22u, 0x04u, 0x99u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xc1u, 0xfdu, 0xf0u, 0x21u, 0x20u, 0x00u, 0xc9u, 0x01u, 0xffu, 0xf7u, 0x12u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xfau, 0x00u, 0x20u, - 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x13u, 0xb5u, 0x11u, 0x00u, 0x07u, 0x22u, + 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x13u, 0xb5u, 0x11u, 0x00u, 0x07u, 0x22u, 0x04u, 0x00u, 0x58u, 0x68u, 0x02u, 0x40u, 0xc0u, 0x20u, 0x80u, 0x00u, 0x22u, 0x50u, 0x1au, 0x69u, 0x20u, 0x00u, 0x00u, 0x92u, 0x9bu, 0x69u, 0xfeu, 0xf7u, 0xdcu, 0xffu, 0x0cu, 0x23u, 0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u, 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x4cu, 0x21u, 0xffu, 0xf7u, 0x36u, 0xf8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, - 0x1au, 0x00u, 0x02u, 0xf0u, 0x4du, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, + 0x1au, 0x00u, 0x02u, 0xf0u, 0x63u, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, 0x8bu, 0x61u, 0x3cu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x2du, 0x33u, 0x40u, 0x32u, 0xffu, 0x33u, 0x0au, 0x61u, 0x08u, 0x60u, 0x48u, 0x60u, 0xcbu, 0x61u, 0x00u, 0xbdu, 0x60u, 0x33u, 0x8bu, 0x61u, 0x01u, 0x23u, 0x0bu, 0x60u, 0x4bu, 0x60u, 0x32u, 0x4bu, 0x40u, 0x32u, @@ -1282,8 +1282,8 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x24u, 0x3bu, 0xdcu, 0xe7u, 0xc0u, 0x33u, 0x8bu, 0x61u, 0x05u, 0x23u, 0x0bu, 0x60u, 0x03u, 0x3bu, 0x4bu, 0x60u, 0x0cu, 0x4bu, 0x80u, 0x32u, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x20u, 0x3bu, 0xccu, 0xe7u, 0x08u, 0x48u, - 0x96u, 0xe7u, 0xc0u, 0x46u, 0x98u, 0x7au, 0x00u, 0x10u, 0xacu, 0x7au, 0x00u, 0x10u, 0xccu, 0x7au, 0x00u, 0x10u, - 0xecu, 0x7au, 0x00u, 0x10u, 0x2cu, 0x7bu, 0x00u, 0x10u, 0x6cu, 0x7bu, 0x00u, 0x10u, 0xacu, 0x7bu, 0x00u, 0x10u, + 0x96u, 0xe7u, 0xc0u, 0x46u, 0xc0u, 0x7au, 0x00u, 0x10u, 0xd4u, 0x7au, 0x00u, 0x10u, 0xf4u, 0x7au, 0x00u, 0x10u, + 0x14u, 0x7bu, 0x00u, 0x10u, 0x54u, 0x7bu, 0x00u, 0x10u, 0x94u, 0x7bu, 0x00u, 0x10u, 0xd4u, 0x7bu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0xa0u, 0xffu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x07u, 0x00u, @@ -1313,33 +1313,33 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x20u, 0x70u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x8fu, 0xb0u, 0x01u, 0x93u, 0x14u, 0xabu, 0x1fu, 0x78u, 0x19u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x00u, 0x91u, 0x16u, 0x00u, 0x1du, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1du, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, - 0x02u, 0xf0u, 0xbfu, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, + 0x02u, 0xf0u, 0xd5u, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0cu, 0xffu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x00u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x18u, 0xffu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x00u, 0x28u, 0x03u, 0xd1u, 0x02u, 0xa9u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x0fu, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x0fu, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, - 0xfcu, 0xd1u, 0x70u, 0x47u, 0x20u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0xe0u, 0x21u, 0x07u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0fu, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb9u, 0xffu, 0x06u, 0x28u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb9u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xc8u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xcau, 0x23u, - 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, + 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xccu, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u, - 0x2cu, 0x60u, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, + 0x2cu, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, - 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, + 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0xceu, 0x21u, 0x04u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x29u, 0x43u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, - 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0x03u, 0xfeu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, + 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, + 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0x19u, 0xfeu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, 0x57u, 0x00u, 0x40u, 0x33u, 0x0bu, 0x61u, 0x69u, 0x23u, 0x4bu, 0x60u, 0x2fu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x08u, 0x60u, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x00u, 0xbdu, 0x40u, 0x33u, 0x0bu, 0x61u, 0x02u, 0x23u, 0x0bu, 0x60u, 0x68u, 0x33u, 0x4bu, 0x60u, 0x28u, 0x4bu, 0xcbu, 0x62u, 0x40u, 0x23u, @@ -1352,9 +1352,9 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x23u, 0x0bu, 0x60u, 0x66u, 0x33u, 0x4bu, 0x60u, 0x10u, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x20u, 0x3bu, 0xd4u, 0xe7u, 0x80u, 0x33u, 0x0bu, 0x61u, 0x06u, 0x23u, 0x0bu, 0x60u, 0x65u, 0x33u, 0x4bu, 0x60u, 0x0au, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, - 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0xecu, 0x7bu, 0x00u, 0x10u, 0x20u, 0x7cu, 0x00u, 0x10u, - 0x00u, 0x7cu, 0x00u, 0x10u, 0x80u, 0x7cu, 0x00u, 0x10u, 0x40u, 0x7cu, 0x00u, 0x10u, 0x00u, 0x7du, 0x00u, 0x10u, - 0xc0u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, + 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x14u, 0x7cu, 0x00u, 0x10u, 0x48u, 0x7cu, 0x00u, 0x10u, + 0x28u, 0x7cu, 0x00u, 0x10u, 0xa8u, 0x7cu, 0x00u, 0x10u, 0x68u, 0x7cu, 0x00u, 0x10u, 0x28u, 0x7du, 0x00u, 0x10u, + 0xe8u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0x40u, 0xfeu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x03u, 0x92u, 0x01u, 0x93u, 0x00u, 0xd1u, 0x95u, 0xe0u, @@ -1377,7 +1377,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x92u, 0xfeu, 0x00u, 0x27u, 0x38u, 0x00u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x02u, 0x9bu, 0x31u, 0x00u, 0x9fu, 0x1bu, 0x3au, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x99u, 0xfeu, 0x69u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x26u, 0xdbu, 0x1bu, 0x01u, 0x93u, 0xb8u, 0xe7u, 0x02u, 0x4fu, 0xeau, 0xe7u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x02u, 0x92u, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x78u, 0xe0u, 0x8bu, 0x6au, 0x0au, 0x6au, 0x00u, 0x93u, 0x53u, 0x0fu, 0x03u, 0x93u, 0x70u, 0x23u, 0xceu, 0x68u, 0xd7u, 0x00u, 0x01u, 0x93u, 0x80u, 0x2eu, 0x01u, 0xd0u, 0x38u, 0x3bu, 0x01u, 0x93u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfeu, @@ -1401,7 +1401,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0xc0u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xfdu, 0x00u, 0x20u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xbfu, 0xb0u, 0x01u, 0x93u, 0x44u, 0xabu, 0x1fu, 0x78u, 0x0du, 0x00u, 0x16u, 0x00u, 0x00u, 0x21u, 0xc0u, 0x22u, 0x0eu, 0xa8u, 0x01u, 0xf0u, - 0x00u, 0xfeu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xfbu, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, + 0x16u, 0xfeu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0x11u, 0xfeu, 0x0eu, 0xabu, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x02u, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x2au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x86u, 0xfeu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1413,7 +1413,7 @@ const uint8_t cy_m0p_image[] = { 0x60u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x5eu, 0xfbu, 0x40u, 0x21u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0xd3u, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x04u, 0x9bu, 0x1au, 0x60u, 0xa1u, 0x23u, 0x9bu, 0x00u, 0xe0u, 0x50u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x03u, 0x31u, - 0x01u, 0x00u, 0x01u, 0x00u, 0x20u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x1cu, 0x4du, + 0x01u, 0x00u, 0x01u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x1cu, 0x4du, 0x80u, 0x00u, 0x25u, 0x50u, 0x3fu, 0x25u, 0x04u, 0x30u, 0xb0u, 0x26u, 0x25u, 0x50u, 0x00u, 0x25u, 0xb6u, 0x00u, 0xa5u, 0x51u, 0x08u, 0x36u, 0xa5u, 0x51u, 0x17u, 0x4fu, 0x08u, 0x36u, 0x01u, 0x35u, 0xa5u, 0x51u, 0x10u, 0x36u, 0xa7u, 0x51u, 0x40u, 0x3eu, 0xa1u, 0x51u, 0xa9u, 0x21u, 0x89u, 0x00u, 0x62u, 0x50u, 0xa2u, 0x22u, 0x92u, 0x00u, @@ -1421,20 +1421,20 @@ const uint8_t cy_m0p_image[] = { 0x0du, 0x4bu, 0x1du, 0x68u, 0x2bu, 0x68u, 0xe1u, 0x18u, 0x03u, 0x00u, 0x08u, 0x68u, 0xe6u, 0x58u, 0x16u, 0x42u, 0x07u, 0xd0u, 0xc0u, 0x0fu, 0xf9u, 0xd1u, 0xebu, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x05u, 0x9bu, 0x1au, 0x60u, 0x00u, 0xe0u, 0x06u, 0x48u, 0xa1u, 0x23u, 0x00u, 0x22u, 0x9bu, 0x00u, 0xe2u, 0x50u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x00u, 0x00u, 0x03u, 0x31u, 0x01u, 0x00u, 0x01u, 0x00u, 0x20u, 0x04u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, + 0x00u, 0x00u, 0x03u, 0x31u, 0x01u, 0x00u, 0x01u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x07u, 0x4bu, 0x89u, 0x00u, 0x1au, 0x68u, 0x93u, 0x6bu, 0x12u, 0x69u, 0xc3u, 0x18u, 0x89u, 0x18u, 0x08u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x68u, 0x80u, 0x00u, 0x80u, 0x0cu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, + 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xfeu, 0xf7u, 0x47u, 0xfbu, 0x10u, 0xbdu, 0xfeu, 0xf7u, 0x16u, 0xfcu, 0xfbu, 0xe7u, 0xc0u, 0x46u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, + 0x28u, 0x06u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, 0x12u, 0x68u, 0x89u, 0x06u, 0x29u, 0x32u, 0x12u, 0x78u, 0x1bu, 0x0du, 0x94u, 0x42u, 0xa4u, 0x41u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa5u, 0x40u, 0x0bu, 0x43u, 0x2bu, 0x43u, 0x80u, 0x22u, 0x00u, 0x21u, 0xfeu, 0xf7u, 0x6cu, 0xf8u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xfeu, 0xf7u, 0x21u, 0xfbu, 0x10u, 0xbdu, - 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, + 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x93u, 0x0eu, 0x00u, 0x01u, 0x92u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x1bu, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2du, 0xd8u, 0x19u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xffu, 0x06u, 0x00u, 0x00u, 0x9au, 0x01u, 0x00u, @@ -1442,48 +1442,48 @@ const uint8_t cy_m0p_image[] = { 0x01u, 0x9au, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, - 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x20u, 0x04u, 0x00u, 0x08u, + 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x03u, 0x93u, 0x04u, 0x00u, 0x01u, 0x91u, 0x02u, 0x92u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x16u, 0x4eu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x23u, 0xd8u, 0x14u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x02u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, 0x03u, 0x9bu, 0x02u, 0x00u, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xffu, - 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, + 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xbbu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x03u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, - 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, + 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, 0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xa6u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3bu, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, 0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0x90u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x25u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x68u, 0x8bu, 0x00u, 0x12u, 0x69u, 0x9bu, 0x18u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x68u, 0x8bu, 0x00u, 0x12u, 0x69u, 0x9bu, 0x18u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0xffu, 0xf7u, 0xd4u, 0xfeu, 0xe1u, 0x04u, 0xc9u, 0x0cu, 0x08u, 0x31u, 0xc9u, 0x08u, - 0xfeu, 0xf7u, 0x3eu, 0xf9u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x00u, 0x28u, 0x07u, 0xdbu, + 0xfeu, 0xf7u, 0x3eu, 0xf9u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x00u, 0x28u, 0x07u, 0xdbu, 0x1fu, 0x23u, 0xc0u, 0x22u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x02u, 0x49u, 0x52u, 0x00u, 0x8bu, 0x50u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0x30u, 0xb5u, 0xf8u, 0x25u, 0x0fu, 0x4bu, 0x10u, 0x4au, 0x18u, 0x68u, 0x14u, 0x68u, 0x43u, 0x6au, 0x22u, 0x6cu, 0x6du, 0x03u, 0x9au, 0x18u, 0x11u, 0x68u, 0x29u, 0x40u, 0x10u, 0xd0u, 0x11u, 0x60u, 0x22u, 0x6cu, 0x9bu, 0x18u, 0x1bu, 0x68u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x53u, 0x1cu, 0xd9u, 0x7fu, 0x00u, 0x29u, 0x07u, 0xd1u, 0x41u, 0x6au, 0x08u, 0x6au, 0x49u, 0x6au, 0x50u, 0x62u, 0x91u, 0x62u, - 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, + 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x24u, 0x04u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, 0x0du, 0x00u, 0x0bu, 0x60u, 0x43u, 0x68u, 0x4bu, 0x60u, 0x83u, 0x69u, 0x8bu, 0x60u, 0xc3u, 0x69u, 0xcbu, 0x60u, 0x4bu, 0x1cu, 0xdau, 0x77u, 0x03u, 0x8cu, 0x0bu, 0x82u, 0x03u, 0x8du, 0x0bu, 0x83u, 0xfdu, 0xf7u, 0xceu, 0xffu, - 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0xaau, 0xfeu, + 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0xc0u, 0xfeu, 0x20u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x1au, 0x4au, 0x13u, 0x60u, 0x80u, 0x22u, 0x21u, 0x68u, 0x52u, 0x02u, 0x8au, 0x40u, 0x18u, 0x4eu, 0x61u, 0x68u, 0x33u, 0x68u, 0x49u, 0x01u, 0x1bu, 0x6au, 0x5bu, 0x18u, 0x16u, 0x49u, 0x5bu, 0x18u, 0xe1u, 0x69u, - 0x1au, 0x60u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x14u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x8au, 0xfeu, + 0x1au, 0x60u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x14u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0xa0u, 0xfeu, 0x28u, 0x23u, 0xe0u, 0x5eu, 0xffu, 0xf7u, 0x8au, 0xffu, 0x28u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x08u, 0x4au, 0x13u, 0x60u, 0x0bu, 0x4au, 0x33u, 0x68u, 0x12u, 0x68u, 0x5bu, 0x6au, 0x92u, 0x6cu, 0x00u, 0x20u, 0x9bu, 0x18u, 0xf8u, 0x22u, 0x52u, 0x03u, 0x1au, 0x60u, 0x07u, 0x4bu, 0x1du, 0x60u, 0x70u, 0xbdu, 0x25u, 0x5fu, 0x00u, 0x10u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xb9u, 0x59u, 0x00u, 0x10u, 0x20u, 0x04u, 0x00u, 0x08u, - 0x2cu, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, + 0x28u, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xb9u, 0x59u, 0x00u, 0x10u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x24u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, 0x1fu, 0x2au, 0x04u, 0xd8u, 0x05u, 0x4au, 0x1au, 0x60u, 0xffu, 0xf7u, 0x8eu, 0xffu, 0x10u, 0xbdu, 0x04u, 0x4au, - 0xf9u, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x28u, 0x04u, 0x00u, 0x08u, 0x40u, 0x7du, 0x00u, 0x10u, - 0x98u, 0x7du, 0x00u, 0x10u, 0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, + 0xf9u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x20u, 0x04u, 0x00u, 0x08u, 0x68u, 0x7du, 0x00u, 0x10u, + 0xc0u, 0x7du, 0x00u, 0x10u, 0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, 0xb2u, 0x4bu, 0xb3u, 0x4du, 0x63u, 0x60u, 0x2bu, 0x68u, 0x5fu, 0x6au, 0x23u, 0x78u, 0x01u, 0x2bu, 0x18u, 0xd1u, 0x38u, 0x00u, 0xfeu, 0xf7u, 0x1fu, 0xf8u, 0x60u, 0x60u, 0x00u, 0x23u, 0xabu, 0x4au, 0xe1u, 0x69u, 0x13u, 0x60u, 0x2bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x10u, 0x88u, 0x22u, 0x69u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, @@ -1528,9 +1528,9 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x93u, 0xd3u, 0x69u, 0x40u, 0x6au, 0x52u, 0x69u, 0xb0u, 0x47u, 0x99u, 0xe7u, 0x96u, 0x69u, 0xedu, 0xe7u, 0xd6u, 0x69u, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xedu, 0xe6u, 0xa1u, 0x6au, 0x03u, 0x91u, 0x8bu, 0x6au, 0x02u, 0x93u, 0x4bu, 0x6au, 0x01u, 0x93u, 0x0bu, 0x6au, 0x00u, 0x93u, 0xcbu, 0x69u, 0x8au, 0x69u, 0x40u, 0x6au, - 0x49u, 0x69u, 0xb0u, 0x47u, 0x84u, 0xe7u, 0xc0u, 0x46u, 0x30u, 0x04u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x20u, 0x04u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0x28u, 0x04u, 0x00u, 0x08u, - 0x2cu, 0x04u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, + 0x49u, 0x69u, 0xb0u, 0x47u, 0x84u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x18u, 0x04u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x24u, 0x04u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xc9u, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x00u, 0x93u, 0x8bu, 0x68u, 0x4au, 0x68u, 0x40u, 0x6au, 0x09u, 0x68u, 0xb0u, 0x47u, 0x65u, 0xe7u, 0x96u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xbbu, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x02u, 0x93u, 0x4bu, 0x69u, 0x01u, 0x93u, 0x0bu, 0x69u, 0x00u, 0x93u, 0x4bu, 0x68u, 0x0au, 0x68u, @@ -1554,10 +1554,10 @@ const uint8_t cy_m0p_image[] = { 0x36u, 0x0cu, 0x91u, 0x40u, 0xb1u, 0x42u, 0x13u, 0xd1u, 0x80u, 0x26u, 0x09u, 0x04u, 0x76u, 0x01u, 0x99u, 0x51u, 0xacu, 0x35u, 0x9bu, 0x59u, 0x2bu, 0x88u, 0x0au, 0x49u, 0x5au, 0x43u, 0x10u, 0x18u, 0x00u, 0xf0u, 0xe2u, 0xf8u, 0x00u, 0x28u, 0x05u, 0xd1u, 0x23u, 0x68u, 0x9bu, 0x68u, 0x00u, 0x2bu, 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcau, 0xfdu, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x0cu, 0x10u, 0x00u, 0x00u, - 0x30u, 0x04u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0x24u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x0cu, 0x10u, 0x00u, 0x00u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u, @@ -1571,41 +1571,41 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au, - 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x34u, 0x04u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x0du, 0x4bu, 0x10u, 0xb5u, 0x18u, 0x60u, 0x00u, 0x28u, 0x04u, 0xd0u, 0xfeu, 0x23u, 0x5bu, 0x42u, 0x03u, 0x80u, 0x00u, 0x23u, 0x43u, 0x80u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0x4cu, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, 0x08u, 0xd0u, 0x4du, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x02u, 0x22u, - 0x04u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xe0u, 0xf8u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x44u, 0x04u, 0x00u, 0x08u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x4du, 0x01u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, 0xffu, 0xf7u, 0xdau, 0xffu, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc0u, 0x03u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, + 0x04u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xe0u, 0xf8u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x3cu, 0x04u, 0x00u, 0x08u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x49u, 0x01u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, 0xffu, 0xf7u, 0xdau, 0xffu, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb8u, 0x03u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, - 0x18u, 0x60u, 0x70u, 0x47u, 0x48u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu, + 0x28u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, + 0x18u, 0x60u, 0x70u, 0x47u, 0x40u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1du, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x25u, 0x40u, 0x27u, 0x40u, 0x12u, 0x4cu, 0x1bu, 0x0cu, 0x26u, 0x68u, 0x07u, 0x60u, 0x34u, 0x6au, 0x45u, 0x60u, 0x83u, 0x60u, 0xacu, 0x36u, 0x36u, 0x88u, 0x77u, 0x43u, 0x3fu, 0x19u, 0x07u, 0x61u, 0x2fu, 0x00u, 0x80u, 0x37u, 0x6du, 0x01u, 0x7fu, 0x01u, 0xe7u, 0x19u, 0x64u, 0x19u, 0x0au, 0x4du, 0x47u, 0x61u, 0x1fu, 0x04u, 0x3bu, 0x43u, 0x64u, 0x19u, 0x23u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x48u, 0x04u, 0x00u, 0x08u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x40u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0xabu, 0x70u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xb5u, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xc8u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, + 0x00u, 0xf0u, 0xdeu, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, 0x1eu, 0x43u, 0x16u, 0x60u, 0xeau, 0x60u, 0x8cu, 0x61u, 0xbcu, 0x40u, 0x01u, 0x9bu, 0xa4u, 0xb2u, 0x4bu, 0x62u, - 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0x48u, 0x04u, 0x00u, 0x08u, + 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0x40u, 0x04u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, 0x07u, 0x02u, 0x8au, 0x00u, 0x2cu, 0x23u, 0x43u, 0x43u, 0x06u, 0x48u, 0x00u, 0x68u, 0xc0u, 0x18u, 0xc3u, 0x69u, 0x93u, 0x42u, 0x04u, 0xd9u, 0x03u, 0x6au, 0x00u, 0x20u, 0x92u, 0x00u, 0xd1u, 0x50u, - 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x48u, 0x04u, 0x00u, 0x08u, 0x0au, 0x02u, 0x8au, 0x00u, + 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x40u, 0x04u, 0x00u, 0x08u, 0x0au, 0x02u, 0x8au, 0x00u, 0x73u, 0xb5u, 0x00u, 0x26u, 0x42u, 0x69u, 0x04u, 0x00u, 0xd5u, 0x68u, 0x01u, 0x96u, 0x2bu, 0x0cu, 0xb3u, 0x42u, 0x21u, 0xd0u, 0x1bu, 0x04u, 0x13u, 0x60u, 0x13u, 0x68u, 0x19u, 0x4bu, 0x00u, 0x69u, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0xb3u, 0x42u, 0x15u, 0xdau, 0x01u, 0xa9u, 0xffu, 0xf7u, 0x22u, 0xffu, @@ -1614,503 +1614,505 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x69u, 0xffu, 0xf7u, 0xf1u, 0xfeu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, - 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x48u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, + 0x28u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, + 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x40u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, - 0x00u, 0xf0u, 0x2fu, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, + 0x00u, 0xf0u, 0x45u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbbu, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, - 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x4cu, 0x04u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, + 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x44u, 0x04u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, - 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, - 0x4cu, 0x04u, 0x00u, 0x08u, 0xc4u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, + 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x44u, 0x04u, 0x00u, 0x08u, 0xbcu, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xf9u, 0xf7u, 0x79u, 0xfeu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, 0x72u, 0x68u, 0xa4u, 0x00u, 0x14u, 0x19u, 0x22u, 0x68u, 0x13u, 0x42u, 0x0du, 0xd0u, 0x9au, 0x43u, 0x22u, 0x60u, 0x00u, 0x24u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x4au, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x02u, 0xd1u, 0x28u, 0x00u, 0xf9u, 0xf7u, 0x61u, 0xfeu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x03u, 0x4cu, 0xf2u, 0xe7u, 0x03u, 0x4cu, 0xf3u, 0xe7u, 0x03u, 0x4cu, 0xf7u, 0xe7u, - 0x4cu, 0x04u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, + 0x44u, 0x04u, 0x00u, 0x08u, 0x02u, 0x01u, 0x88u, 0x00u, 0x03u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x0au, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0x1au, 0x68u, 0x82u, 0x42u, 0x0du, 0xd9u, 0x59u, 0x68u, 0x1fu, 0x23u, 0x42u, 0x09u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, - 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 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0x37u, 0x4bu, 0x05u, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x3eu, 0xdau, 0x36u, 0x4au, + 0x01u, 0x21u, 0x30u, 0x00u, 0x00u, 0xf0u, 0xeeu, 0xf8u, 0x00u, 0x28u, 0x37u, 0xd1u, 0x01u, 0x98u, 0xffu, 0xf7u, + 0x8fu, 0xffu, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x3eu, 0xd0u, 0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, + 0xd9u, 0xf8u, 0x04u, 0x00u, 0x2bu, 0xe0u, 0x06u, 0x20u, 0x00u, 0xf0u, 0xe4u, 0xf8u, 0x2bu, 0x68u, 0xb0u, 0x33u, + 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x02u, 0xdau, 0x28u, 0x4cu, 0x20u, 0x00u, 0xfeu, 0xbdu, + 0x00u, 0x20u, 0x00u, 0xf0u, 0x97u, 0xf8u, 0x26u, 0x4bu, 0x98u, 0x42u, 0xf6u, 0xd0u, 0x00u, 0x23u, 0x25u, 0x4au, + 0x19u, 0x00u, 0x12u, 0x68u, 0x01u, 0x20u, 0x00u, 0xf0u, 0x9du, 0xf8u, 0x00u, 0x25u, 0xa8u, 0x42u, 0xecu, 0xd1u, + 0x00u, 0x20u, 0x00u, 0xf0u, 0x87u, 0xf8u, 0x1eu, 0x4au, 0x1fu, 0x4bu, 0x90u, 0x42u, 0x03u, 0xd0u, 0x9du, 0x42u, + 0xe3u, 0xd0u, 0x01u, 0x35u, 0xf4u, 0xe7u, 0x9du, 0x42u, 0xb9u, 0xd1u, 0xdeu, 0xe7u, 0x17u, 0x4cu, 0x03u, 0x2fu, + 0x05u, 0xd1u, 0x01u, 0x21u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x9du, 0xf8u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x28u, 0x00u, + 0x00u, 0xf0u, 0x78u, 0xf8u, 0xd2u, 0xe7u, 0x15u, 0x4cu, 0xf1u, 0xe7u, 0x00u, 0xf0u, 0x8bu, 0xf8u, 0x0eu, 0x4au, + 0x05u, 0x00u, 0x01u, 0x21u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x9du, 0xf8u, 0x00u, 0x28u, 0x09u, 0xd1u, 0x00u, 0x9bu, + 0x00u, 0x2bu, 0x08u, 0xd0u, 0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, 0x8bu, 0xf8u, 0x04u, 0x00u, + 0xe5u, 0xe7u, 0x06u, 0x4cu, 0xe3u, 0xe7u, 0x09u, 0x4cu, 0xe1u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x05u, 0x00u, 0x52u, 0x00u, + 0x01u, 0x01u, 0x88u, 0x00u, 0x3cu, 0x04u, 0x00u, 0x08u, 0xf0u, 0x49u, 0x02u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, + 0x18u, 0x4bu, 0xf7u, 0xb5u, 0x1bu, 0x68u, 0x18u, 0x4au, 0x5cu, 0x68u, 0x04u, 0x23u, 0x11u, 0x69u, 0x0bu, 0x43u, + 0x13u, 0x61u, 0x01u, 0x28u, 0x24u, 0xd0u, 0x30u, 0xbfu, 0x23u, 0x00u, 0xfcu, 0x33u, 0x1bu, 0x69u, 0x00u, 0x2bu, + 0x1du, 0xd1u, 0xa3u, 0x20u, 0x11u, 0x4bu, 0x12u, 0x49u, 0x12u, 0x4au, 0xc0u, 0x00u, 0x0fu, 0x68u, 0x1eu, 0x58u, + 0x15u, 0x68u, 0x01u, 0x95u, 0x10u, 0x4du, 0x0du, 0x60u, 0x06u, 0x25u, 0x1du, 0x50u, 0x3eu, 0x20u, 0x10u, 0x60u, + 0x0eu, 0x48u, 0x3eu, 0x35u, 0x1du, 0x50u, 0x1du, 0x58u, 0x00u, 0x2du, 0xfcu, 0xdau, 0x0cu, 0x48u, 0xfcu, 0x34u, + 0x20u, 0x61u, 0x0fu, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, 0x5eu, 0x50u, 0x01u, 0x9bu, 0x13u, 0x60u, 0xf7u, 0xbdu, + 0x20u, 0xbfu, 0xd9u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u, + 0xaau, 0xaau, 0xaau, 0xaau, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x81u, 0x64u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x23u, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x29u, 0x62u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, - 0x0du, 0x64u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xa5u, 0x6du, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x1bu, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, - 0x79u, 0x6du, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x0du, 0x64u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x55u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x0du, 0x61u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x91u, 0x5fu, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_02_cm0p_crypto.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_02_cm0p_crypto.c index f608dc4d33..96de7c86bb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_02_cm0p_crypto.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_02_cm0p_crypto.c @@ -37,19 +37,19 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xb4u, 0x03u, 0x00u, 0x08u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x63u, 0xfdu, 0x06u, 0xf0u, 0x03u, 0xfdu, 0xfeu, 0xe7u, - 0x2cu, 0x7eu, 0x00u, 0x10u, 0x44u, 0x7eu, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x06u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x75u, 0xfdu, 0x06u, 0xf0u, 0x15u, 0xfdu, 0xfeu, 0xe7u, + 0x54u, 0x7eu, 0x00u, 0x10u, 0x6cu, 0x7eu, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x06u, 0xf0u, 0xf5u, 0xfau, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, + 0x04u, 0x30u, 0x06u, 0xf0u, 0x07u, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x52u, 0x69u, 0x82u, 0x18u, 0x08u, 0x78u, 0x49u, 0x68u, 0x38u, 0x40u, 0x10u, 0x60u, 0x01u, 0x2cu, 0x00u, 0xd1u, 0x20u, 0x31u, 0x28u, 0x00u, 0x08u, 0x9au, 0x01u, 0x3cu, 0x03u, 0xf0u, 0x72u, 0xfdu, 0x0cu, 0x23u, 0x61u, 0x42u, 0x61u, 0x41u, 0x00u, 0x93u, 0x28u, 0x00u, 0x08u, 0x3bu, 0x44u, 0x31u, 0x00u, 0x22u, @@ -95,7 +95,7 @@ const uint8_t cy_m0p_image[] = { 0xd3u, 0xfeu, 0x10u, 0x23u, 0x2au, 0x00u, 0x07u, 0x99u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xcbu, 0xfcu, 0x10u, 0x3cu, 0xcfu, 0xe7u, 0x01u, 0x48u, 0xdfu, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x91u, 0xb0u, 0x19u, 0x9du, 0x04u, 0x00u, 0x06u, 0x91u, 0x0bu, 0x92u, 0x00u, 0x21u, 0x10u, 0x22u, 0x0cu, 0xa8u, 0x07u, 0x93u, - 0x06u, 0xf0u, 0x5du, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, + 0x06u, 0xf0u, 0x6fu, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, 0x10u, 0x32u, 0x04u, 0x92u, 0x05u, 0x93u, 0x07u, 0x9au, 0x10u, 0x23u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xaau, 0xfcu, 0x0fu, 0x9bu, 0x1bu, 0xbau, 0x08u, 0x93u, 0x06u, 0x9bu, 0x08u, 0x9eu, 0x1bu, 0x09u, 0x0au, 0x93u, 0x0eu, 0x9bu, 0x1fu, 0xbau, 0x08u, 0x9bu, 0x17u, 0x99u, 0xf3u, 0x1au, 0x1au, 0x01u, 0x89u, 0x18u, 0x09u, 0x91u, 0x18u, 0x99u, @@ -253,7 +253,7 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x28u, 0x00u, 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0xf0u, 0xb5u, 0x10u, 0x25u, 0x87u, 0xb0u, 0x0fu, 0x00u, 0x04u, 0x00u, 0x01u, 0x92u, 0x00u, 0x21u, 0x2au, 0x00u, - 0x02u, 0xa8u, 0x06u, 0xf0u, 0x6cu, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, + 0x02u, 0xa8u, 0x06u, 0xf0u, 0x7eu, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, 0x02u, 0xa9u, 0xeau, 0x1bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x18u, 0x4du, 0x19u, 0x4au, 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0fu, 0x2fu, 0x02u, 0xd8u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x10u, 0x22u, 0x31u, 0x00u, 0x20u, 0x00u, @@ -264,7 +264,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x08u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x1eu, 0x00u, 0xa7u, 0xb0u, 0x2cu, 0xabu, 0x0au, 0xadu, 0x1fu, 0x78u, 0x02u, 0x91u, 0x03u, 0x92u, 0x00u, 0x21u, 0x70u, 0x22u, 0x28u, 0x00u, - 0x06u, 0xf0u, 0x15u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x10u, 0xf9u, 0x3au, 0x00u, + 0x06u, 0xf0u, 0x27u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x22u, 0xf9u, 0x3au, 0x00u, 0x2eu, 0x9bu, 0x31u, 0x00u, 0x00u, 0x95u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf3u, 0xfbu, 0x2eu, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfbu, 0x06u, 0xabu, 0x04u, 0xa9u, 0x20u, 0x00u, 0x05u, 0x93u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x03u, 0x9bu, 0x02u, 0x9au, 0x04u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x60u, 0xffu, 0x20u, 0x00u, 0x2du, 0x9au, @@ -304,7 +304,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x45u, 0xfeu, 0x02u, 0x9bu, 0x04u, 0x9au, 0x28u, 0x00u, 0x01u, 0x97u, 0x00u, 0x96u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x28u, 0x00u, 0x08u, 0x23u, 0x32u, 0x00u, 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, - 0x38u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, + 0x60u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x07u, 0x93u, 0x25u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x06u, 0x91u, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x03u, 0x93u, 0x00u, 0x27u, 0x1fu, 0x4bu, 0x04u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x05u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, @@ -314,7 +314,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0xf6u, 0xfdu, 0x03u, 0x9fu, 0x03u, 0x9bu, 0x08u, 0x37u, 0x01u, 0x93u, 0x06u, 0x9au, 0x33u, 0x00u, 0x20u, 0x00u, 0x00u, 0x97u, 0x01u, 0x21u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x3au, 0x00u, 0x07u, 0x99u, 0x02u, 0xf0u, 0xe5u, 0xfdu, 0x28u, 0x00u, 0x09u, 0xb0u, 0xf0u, 0xbdu, - 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x38u, 0x71u, 0x00u, 0x10u, + 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x60u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0x86u, 0x25u, 0x6du, 0x01u, 0x44u, 0x59u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0xdcu, 0x68u, 0x05u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, 0x21u, 0x60u, @@ -335,7 +335,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x52u, 0x31u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x28u, 0x00u, - 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xb8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x27u, 0x85u, 0xb0u, 0x02u, 0x91u, 0x00u, 0x92u, 0x03u, 0x93u, 0x26u, 0x4bu, 0x00u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x01u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x00u, 0x28u, 0x04u, 0xd0u, 0x01u, 0x9bu, 0x9du, 0x42u, @@ -346,15 +346,15 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x02u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x54u, 0x31u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x3cu, 0xffu, 0x28u, 0x00u, 0x05u, 0xb0u, - 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xb8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x42u, 0x1eu, 0x03u, 0x00u, 0x00u, 0x20u, 0x04u, 0x2au, 0x03u, 0xd8u, 0x28u, 0x30u, 0x58u, 0x43u, 0x01u, 0x4bu, - 0xc0u, 0x18u, 0x70u, 0x47u, 0x38u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0xc0u, 0x18u, 0x70u, 0x47u, 0x60u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, + 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xf2u, 0xf9u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0xadu, 0xb0u, 0x04u, 0x00u, 0x04u, 0x91u, 0x05u, 0x92u, 0x03u, 0x93u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x15u, 0xe1u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x11u, 0xe1u, 0x32u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x0du, 0xe1u, 0x33u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x09u, 0xe1u, 0x32u, 0x9bu, 0x58u, 0x78u, 0xffu, 0xf7u, @@ -392,7 +392,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x00u, 0xd0u, 0x71u, 0xe7u, 0x03u, 0x9bu, 0xe9u, 0x1du, 0xc9u, 0x08u, 0x59u, 0x18u, 0x0au, 0x22u, 0x2bu, 0x00u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xc4u, 0xf8u, 0x68u, 0xe7u, 0x08u, 0x4eu, 0x6bu, 0xe7u, 0x07u, 0x4eu, 0x6eu, 0xe7u, 0x07u, 0x4eu, 0x6cu, 0xe7u, 0xc0u, 0x46u, 0x09u, 0x80u, 0x00u, 0x00u, 0x01u, 0x00u, 0x32u, 0x00u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0x0fu, 0x1eu, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0xd1u, 0x8bu, 0xe1u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x88u, 0xe1u, 0x0cu, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x84u, 0xe1u, 0x0du, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x80u, 0xe1u, 0x58u, 0x78u, 0xffu, 0xf7u, 0x78u, 0xfeu, @@ -444,11 +444,11 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x7au, 0xffu, 0x00u, 0x28u, 0x09u, 0xd0u, 0x01u, 0x23u, 0x0cu, 0x9au, 0x13u, 0x70u, 0x0eu, 0x49u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x27u, 0xfdu, 0x38u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x0cu, 0x9bu, 0x18u, 0x70u, 0xf5u, 0xe7u, 0x04u, 0x4fu, 0x09u, 0x49u, 0xf3u, 0xe7u, 0x02u, 0x4fu, 0xf4u, 0xe7u, - 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x80u, 0x80u, 0x00u, 0x00u, 0x08u, 0x60u, 0x00u, 0x00u, 0x06u, 0x80u, 0x00u, 0x00u, 0xf1u, 0x7eu, 0x00u, 0x00u, 0x30u, 0x60u, 0x00u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x85u, 0xb0u, 0x08u, 0x00u, 0x02u, 0x91u, 0x03u, 0x92u, 0x1eu, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xfcu, 0x07u, 0x1eu, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x77u, 0xe0u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x74u, 0xe0u, 0x73u, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x70u, 0xe0u, 0xb3u, 0x68u, @@ -473,24 +473,24 @@ const uint8_t cy_m0p_image[] = { 0x10u, 0xbdu, 0x00u, 0x00u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x0fu, 0xfeu, 0x10u, 0xbdu, 0x0fu, 0x23u, 0x13u, 0x43u, - 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, + 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x05u, 0xd8u, 0x05u, 0x4bu, 0x21u, 0x22u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xc0u, 0xc0u, 0x00u, 0x00u, 0xcfu, 0xc0u, 0x00u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x10u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0xeau, 0xfdu, 0x10u, 0xbdu, 0x09u, 0x03u, 0x0bu, 0x00u, 0x13u, 0x43u, 0x00u, 0x22u, 0x10u, 0xb5u, 0x11u, 0x00u, 0x01u, 0xf0u, 0xe1u, 0xfdu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, + 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, 0x07u, 0x4au, 0x15u, 0x68u, 0x24u, 0x22u, 0x29u, 0x35u, 0x2du, 0x78u, 0x1fu, 0x2du, 0x00u, 0xd9u, 0x01u, 0x3au, 0x24u, 0x01u, 0x23u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xa5u, 0xfdu, 0x70u, 0xbdu, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x23u, 0x10u, 0xb5u, 0x11u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0x95u, 0xfdu, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x1bu, 0x4du, 0xffu, 0xf7u, 0x9fu, 0xffu, 0x20u, 0x00u, 0x01u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x9cu, 0xffu, 0x2au, 0x00u, @@ -523,7 +523,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x70u, 0xfeu, 0x94u, 0x4bu, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x0bu, 0xd0u, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x00u, 0xf0u, 0x35u, 0xfdu, 0x0eu, 0x9bu, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x00u, 0xf0u, 0x24u, 0xfdu, 0x8du, 0x4bu, 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0x01u, 0xd9u, 0x00u, 0xf0u, - 0x1du, 0xfdu, 0x04u, 0xf0u, 0x27u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, + 0x1du, 0xfdu, 0x04u, 0xf0u, 0x39u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xfeu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xfeu, 0x80u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xfeu, 0xc0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9du, 0xfeu, 0xc0u, 0x22u, @@ -688,7 +688,7 @@ const uint8_t cy_m0p_image[] = { 0x8bu, 0xffu, 0x00u, 0x21u, 0x44u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x85u, 0xffu, 0xe0u, 0x21u, 0x49u, 0x00u, 0xffu, 0xf7u, 0x69u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xeau, 0xf9u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xf9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdcu, 0xf9u, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x42u, 0x4bu, - 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0xf2u, 0xf9u, 0x05u, 0x00u, 0x84u, 0x00u, + 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x04u, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, 0xd1u, 0x00u, 0xc7u, 0x01u, 0xedu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xf9u, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x73u, 0xf9u, 0x02u, 0x22u, 0x00u, 0x21u, 0xffu, 0x32u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x80u, 0x22u, 0x01u, 0x21u, @@ -715,7 +715,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xb0u, 0xfeu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x01u, 0x23u, 0xffu, 0xf7u, 0x5du, 0xf8u, 0x20u, 0x00u, 0x03u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xf8u, 0x01u, 0x23u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3eu, 0xf8u, 0x7fu, 0xe7u, 0x1cu, 0x22u, - 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0xf2u, 0xfau, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, + 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x04u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xf8u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xf8u, 0xe0u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xf8u, 0xf0u, 0x22u, 0x00u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xf8u, 0x80u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, @@ -746,7 +746,7 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x69u, 0xffu, 0x3eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xb0u, 0xfdu, 0x00u, 0x21u, 0x3eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xaau, 0xfdu, 0x23u, 0x21u, 0xffu, 0xf7u, 0x8fu, 0xf9u, 0x39u, 0x49u, 0x11u, 0x22u, 0x1cu, 0x31u, - 0x01u, 0xa8u, 0x04u, 0xf0u, 0xfbu, 0xf9u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, + 0x01u, 0xa8u, 0x04u, 0xf0u, 0x0du, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb0u, 0xffu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xabu, 0xffu, 0x31u, 0x4au, 0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xafu, 0xffu, 0xf0u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa9u, 0xffu, 0x81u, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa4u, 0xffu, @@ -760,7 +760,7 @@ const uint8_t cy_m0p_image[] = { 0x4bu, 0xfdu, 0x04u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf8u, 0xfeu, 0x4eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x3fu, 0xfdu, 0x00u, 0x21u, 0x07u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x39u, 0xfdu, 0x43u, 0x21u, 0xffu, 0xf7u, 0x1eu, 0xf9u, 0x12u, 0x10u, 0x00u, 0x00u, - 0x2du, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, + 0x55u, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0xfeu, 0xf7u, 0xdau, 0xfeu, 0x09u, 0x4bu, 0x26u, 0x01u, 0x33u, 0x43u, 0x28u, 0x00u, 0x3du, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x1fu, 0xfdu, 0x24u, 0x03u, 0x05u, 0x4bu, 0x34u, 0x43u, 0x28u, 0x00u, 0x23u, 0x43u, 0x37u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x16u, 0xfdu, 0x70u, 0xbdu, 0xc0u, 0x46u, @@ -772,7 +772,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xfcu, 0x0bu, 0x4bu, 0x2du, 0x03u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x07u, 0xd8u, 0x2bu, 0x00u, 0x26u, 0x22u, 0x3bu, 0x43u, 0x30u, 0x00u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xddu, 0xfcu, 0xf8u, 0xbdu, 0x0fu, 0x23u, 0x2bu, 0x43u, 0x3bu, 0x43u, 0x25u, 0x22u, 0xf5u, 0xe7u, 0xc0u, 0x46u, 0x0eu, 0x00u, 0x80u, 0x00u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x0du, 0x00u, 0xfeu, 0xf7u, 0xd5u, 0xfeu, 0x3au, 0x00u, 0x07u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd7u, 0xfeu, 0x32u, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd2u, 0xfeu, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xcdu, 0xfeu, 0x06u, 0x9au, 0x09u, 0x21u, @@ -867,7 +867,7 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x90u, 0x08u, 0x22u, 0x00u, 0x97u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd0u, 0xfeu, 0x01u, 0x22u, 0x05u, 0x9bu, 0x13u, 0x42u, 0x0au, 0xd0u, 0x0bu, 0x23u, 0x01u, 0x93u, 0x01u, 0x3bu, 0x00u, 0x93u, 0x02u, 0x97u, 0x01u, 0x3bu, 0x07u, 0x32u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0eu, 0xfeu, 0x01u, 0x35u, 0xcdu, 0xe7u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x80u, 0x22u, 0x0du, 0x4bu, 0x52u, 0x00u, 0x90u, 0x42u, 0x11u, 0xd0u, 0x07u, 0xd8u, 0x01u, 0x22u, 0xc0u, 0x28u, 0x0eu, 0xd0u, 0x02u, 0x22u, 0xe0u, 0x28u, 0x0bu, 0xd0u, 0x00u, 0x22u, 0x09u, 0xe0u, 0xc0u, 0x22u, 0x52u, 0x00u, 0x90u, 0x42u, 0x07u, 0xd0u, 0x05u, 0x4au, 0x90u, 0x42u, 0xf6u, 0xd1u, 0x05u, 0x22u, 0x00u, 0xe0u, 0x03u, 0x22u, @@ -876,7 +876,7 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x98u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2fu, 0xffu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x62u, 0xfbu, 0x13u, 0xbdu, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x93u, 0xb0u, 0x05u, 0x93u, 0x1au, 0xabu, 0x1cu, 0x78u, 0x65u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x03u, 0x91u, 0x04u, 0x92u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, - 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0xf1u, 0xfdu, 0x33u, 0x00u, 0x81u, 0x33u, + 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x03u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, 0x22u, 0x00u, 0xffu, 0x33u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0xfcu, 0xfbu, 0x04u, 0x1eu, 0x00u, 0xd0u, 0x86u, 0xe0u, 0x33u, 0x00u, 0x80u, 0x33u, 0x01u, 0x93u, 0x98u, 0x23u, 0x01u, 0x9au, 0xdbu, 0x00u, 0x77u, 0x1cu, 0xf6u, 0x50u, 0xffu, 0x37u, 0xf3u, 0x18u, 0x5au, 0x60u, 0x9fu, 0x60u, 0x19u, 0x9au, 0x09u, 0x9bu, 0x9au, 0x42u, @@ -902,8 +902,8 @@ const uint8_t cy_m0p_image[] = { 0x86u, 0xe7u, 0xfau, 0x5cu, 0x01u, 0x9cu, 0x4au, 0x40u, 0xf2u, 0x54u, 0xfau, 0x5cu, 0x42u, 0x40u, 0xe2u, 0x54u, 0x01u, 0x33u, 0x80u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, 0x04u, 0x92u, 0x93u, 0x22u, 0x05u, 0x93u, 0x13u, 0xaeu, 0xaeu, 0xabu, 0x1cu, 0x78u, 0x03u, 0x91u, 0x92u, 0x00u, - 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x23u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, - 0x1eu, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, + 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x35u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, + 0x30u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, 0x3bu, 0xd1u, 0x90u, 0x23u, 0x9bu, 0x00u, 0xf6u, 0x50u, 0x33u, 0xaau, 0x04u, 0x33u, 0xf2u, 0x50u, 0x0au, 0x9fu, 0x04u, 0x33u, 0x53u, 0xaau, 0xf2u, 0x50u, 0x10u, 0x9bu, 0xbeu, 0xb2u, 0x01u, 0x93u, 0x02u, 0x00u, 0x33u, 0x00u, 0x53u, 0xa9u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x6eu, 0xfcu, 0xadu, 0x9bu, 0xbbu, 0x42u, 0x2eu, 0xd9u, 0x07u, 0xa9u, @@ -934,9 +934,9 @@ const uint8_t cy_m0p_image[] = { 0x52u, 0x02u, 0xc3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd0u, 0x23u, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x22u, 0x0eu, 0x21u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0du, 0x21u, 0xffu, 0xf7u, 0xdfu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0bu, 0x21u, 0xffu, 0xf7u, 0xd5u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0au, 0x21u, @@ -949,7 +949,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xffu, 0x03u, 0x4bu, 0x0fu, 0x21u, 0x1au, 0x68u, 0x20u, 0x00u, 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0xd4u, 0x03u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x04u, 0x4bu, 0x1fu, 0x2au, 0x00u, 0xd9u, 0x04u, 0x4bu, 0x04u, 0x4au, 0x13u, 0x60u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x5cu, 0x78u, 0x00u, 0x10u, 0xb0u, 0x78u, 0x00u, 0x10u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x84u, 0x78u, 0x00u, 0x10u, 0xd8u, 0x78u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, 0x00u, 0x29u, 0x09u, 0xd1u, 0x00u, 0x2cu, 0x28u, 0xd1u, 0x13u, 0x6du, 0xc1u, 0x18u, 0x2au, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x6cu, 0x00u, 0x29u, 0x21u, 0xd0u, 0xa4u, 0x00u, 0x28u, 0x4bu, 0x65u, 0x1eu, 0x9du, 0x42u, 0x1cu, 0xd8u, @@ -962,7 +962,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xd1u, 0x1fu, 0x2eu, 0x02u, 0xd9u, 0x10u, 0x4du, 0x1bu, 0x02u, 0x43u, 0x51u, 0x93u, 0x6bu, 0xa2u, 0x08u, 0xc3u, 0x18u, 0x19u, 0x60u, 0x0fu, 0x21u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x00u, 0x20u, 0x0bu, 0x4bu, 0x1cu, 0x60u, 0x70u, 0xbdu, 0x7cu, 0x23u, 0xe4u, 0xe7u, 0x78u, 0x23u, 0xe2u, 0xe7u, 0x60u, 0x23u, 0xe0u, 0xe7u, 0x40u, 0x23u, - 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, + 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0xd4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x4bu, 0x21u, 0x49u, 0x1bu, 0x68u, 0x09u, 0x68u, 0x9au, 0x6cu, 0x92u, 0x00u, 0x00u, 0x29u, 0x1cu, 0xd0u, 0x1eu, 0x49u, 0x09u, 0x68u, 0x00u, 0x29u, 0x18u, 0xd0u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2fu, 0xd9u, @@ -972,18 +972,18 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0xd0u, 0x7fu, 0x2bu, 0xf9u, 0xd1u, 0x80u, 0x22u, 0x52u, 0x00u, 0xf6u, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x01u, 0xf3u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x01u, 0xf0u, 0xe7u, 0x80u, 0x22u, 0x52u, 0x01u, 0xedu, 0xe7u, 0x80u, 0x22u, 0x12u, 0x01u, 0xeau, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x00u, 0xe7u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x00u, 0xe4u, 0xe7u, - 0x0au, 0x00u, 0xe2u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x0au, 0x00u, 0xe2u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, 0x88u, 0x14u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x17u, 0x4au, 0x18u, 0x49u, 0x13u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x17u, 0xd8u, 0x16u, 0x4bu, 0x23u, 0x60u, 0x01u, 0x20u, 0x09u, 0x68u, 0x4bu, 0x6bu, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x13u, 0x68u, 0x09u, 0x6du, 0x9au, 0x6cu, 0x61u, 0x18u, 0x92u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x23u, 0x68u, 0x0bu, 0x48u, 0x03u, 0x40u, 0x23u, 0x60u, 0x0bu, 0x68u, 0x0au, 0x48u, 0x5bu, 0x68u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x80u, 0x23u, 0x20u, 0x68u, - 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0xd4u, 0x03u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, 0x01u, 0x00u, 0x02u, 0x00u, 0x03u, 0x23u, 0x03u, 0x70u, 0x00u, 0x20u, 0x70u, 0x47u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x00u, 0x23u, 0x03u, 0x60u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x20u, 0x03u, 0x4bu, - 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x01u, 0x29u, 0x0bu, 0xd9u, 0x01u, 0x22u, 0x0au, 0x40u, 0x54u, 0x42u, 0x62u, 0x41u, 0xcbu, 0x0fu, 0x5bu, 0x18u, 0x5bu, 0x10u, 0x9bu, 0x1au, 0x02u, 0x00u, 0x01u, 0x39u, 0x8bu, 0x42u, 0x00u, 0xdbu, 0x30u, 0xbdu, 0x14u, 0x78u, 0x45u, 0x5cu, 0x15u, 0x70u, 0x44u, 0x54u, 0x01u, 0x32u, 0x01u, 0x39u, 0xf5u, 0xe7u, 0x00u, 0x00u, @@ -1085,25 +1085,25 @@ const uint8_t cy_m0p_image[] = { 0x19u, 0x68u, 0x0bu, 0x68u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0x8bu, 0x69u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xffu, 0xf7u, 0x05u, 0xfeu, 0x10u, 0xbdu, - 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, + 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, - 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, + 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xffu, 0xf7u, - 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x03u, 0x34u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xd6u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xc5u, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x09u, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x0bu, 0x43u, 0x21u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x8du, 0xfau, 0x10u, 0xbdu, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x1du, 0x00u, 0x5eu, 0x1cu, 0x01u, 0x92u, 0x0fu, 0x00u, 0x32u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xccu, 0xffu, 0x32u, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x32u, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x2au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1116,7 +1116,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x2au, 0xfau, 0x0du, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x24u, 0xfau, 0x33u, 0x00u, 0x3au, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfau, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x02u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, - 0x01u, 0x3du, 0xd9u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, + 0x01u, 0x3du, 0xd9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x9eu, 0x00u, 0x91u, 0x15u, 0x00u, 0x01u, 0x21u, 0x72u, 0x1cu, 0x77u, 0x00u, 0x01u, 0x93u, 0xffu, 0xf7u, 0x63u, 0xffu, 0x3au, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5eu, 0xffu, 0x3au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x59u, 0xffu, 0x32u, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, @@ -1138,7 +1138,7 @@ const uint8_t cy_m0p_image[] = { 0x7bu, 0xf9u, 0x20u, 0x00u, 0x10u, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x75u, 0xf9u, 0x00u, 0x9bu, 0x20u, 0x00u, 0x1au, 0x03u, 0x02u, 0x23u, 0x00u, 0x21u, 0x13u, 0x43u, 0x30u, 0x22u, 0xffu, 0xf7u, 0x6cu, 0xf9u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, 0x3au, 0x10u, 0x00u, 0x00u, - 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, + 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, 0x10u, 0x10u, 0x00u, 0x00u, 0x21u, 0x30u, 0x00u, 0x00u, 0x23u, 0x00u, 0x30u, 0x00u, 0x28u, 0x30u, 0x00u, 0x00u, 0xf7u, 0xb5u, 0x06u, 0x00u, 0x1cu, 0x00u, 0x09u, 0x9bu, 0x01u, 0x91u, 0x5fu, 0x00u, 0x15u, 0x00u, 0x02u, 0x21u, 0x3au, 0x00u, 0xffu, 0xf7u, 0xabu, 0xfeu, 0x3au, 0x00u, 0x03u, 0x21u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xfeu, @@ -1156,7 +1156,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xf8u, 0x01u, 0x9bu, 0x30u, 0x00u, 0x1cu, 0x03u, 0x0du, 0x4bu, 0x30u, 0x22u, 0x23u, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xe2u, 0xf8u, 0xc0u, 0x23u, 0x9bu, 0x03u, 0x30u, 0x00u, 0x23u, 0x43u, 0x30u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xdau, 0xf8u, 0x30u, 0x00u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x30u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, 0x01u, 0x00u, 0x40u, 0x00u, 0xf8u, 0xb5u, 0x1du, 0x00u, 0x00u, 0x23u, 0x16u, 0x00u, 0x0fu, 0x00u, 0x10u, 0x22u, 0x19u, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xc0u, 0xf8u, 0xe0u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x11u, 0x00u, 0x3bu, 0x43u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb8u, 0xf8u, 0x90u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x33u, 0x43u, @@ -1179,7 +1179,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5cu, 0xfdu, 0x33u, 0x68u, 0x2cu, 0x22u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x0eu, 0x4bu, 0xa8u, 0xe7u, 0x0eu, 0x4bu, 0x25u, 0x22u, 0xeau, 0xe7u, 0xe0u, 0x21u, 0x20u, 0x00u, 0x89u, 0x01u, 0xffu, 0xf7u, 0x79u, 0xfdu, 0x00u, 0x23u, 0x11u, 0x22u, 0x19u, 0x00u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, 0x09u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, 0x0au, 0xe0u, 0x00u, 0x00u, 0xdfu, 0xd0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x06u, 0x00u, 0x0fu, 0x00u, 0x02u, 0x93u, 0x0au, 0x9du, 0x0bu, 0x98u, 0x06u, 0x2au, 0x37u, 0xd8u, 0x21u, 0x4bu, 0x91u, 0x00u, 0xc9u, 0x58u, @@ -1191,7 +1191,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x12u, 0xd1u, 0x00u, 0x9au, 0xa3u, 0xb2u, 0xaau, 0x18u, 0x02u, 0x99u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb5u, 0xfcu, 0x00u, 0x28u, 0x09u, 0xd1u, 0x38u, 0x70u, 0x07u, 0xe0u, 0x00u, 0x24u, 0x23u, 0x00u, 0x21u, 0x00u, 0xcau, 0xe7u, 0x01u, 0x30u, 0x42u, 0x78u, 0xffu, 0x2au, 0xe0u, 0xd0u, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, - 0x04u, 0x79u, 0x00u, 0x10u, 0x27u, 0x79u, 0x00u, 0x10u, 0x20u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, + 0x2cu, 0x79u, 0x00u, 0x10u, 0x4fu, 0x79u, 0x00u, 0x10u, 0x48u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, 0x09u, 0x93u, 0x8bu, 0x68u, 0x04u, 0x00u, 0x05u, 0x93u, 0xcbu, 0x68u, 0x08u, 0x92u, 0x06u, 0x93u, 0x0bu, 0x68u, 0x4fu, 0x68u, 0x07u, 0x93u, 0x0bu, 0x69u, 0x8du, 0x69u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x93u, 0xb3u, 0x4bu, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1241,7 +1241,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x06u, 0x60u, 0x00u, 0x00u, 0x05u, 0x50u, 0x00u, 0x00u, 0x07u, 0x70u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x09u, 0xa0u, 0x00u, 0x00u, 0x0au, 0xc0u, 0x00u, 0x00u, 0x0bu, 0x50u, 0x00u, 0x00u, 0x07u, 0xb0u, 0x00u, 0x00u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, 0x87u, 0xb0u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x00u, 0x04u, 0x93u, 0x8bu, 0x69u, 0x0fu, 0x68u, 0x05u, 0x93u, 0x34u, 0x4bu, 0x4du, 0x68u, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x3du, 0xffu, 0x31u, 0x00u, 0x82u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfbu, @@ -1262,7 +1262,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x4cu, 0x21u, 0xffu, 0xf7u, 0x36u, 0xf8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, - 0x1au, 0x00u, 0x01u, 0xf0u, 0xfbu, 0xffu, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, + 0x1au, 0x00u, 0x02u, 0xf0u, 0x0du, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, 0x8bu, 0x61u, 0x3cu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x2du, 0x33u, 0x40u, 0x32u, 0xffu, 0x33u, 0x0au, 0x61u, 0x08u, 0x60u, 0x48u, 0x60u, 0xcbu, 0x61u, 0x00u, 0xbdu, 0x60u, 0x33u, 0x8bu, 0x61u, 0x01u, 0x23u, 0x0bu, 0x60u, 0x4bu, 0x60u, 0x32u, 0x4bu, 0x40u, 0x32u, @@ -1278,8 +1278,8 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x24u, 0x3bu, 0xdcu, 0xe7u, 0xc0u, 0x33u, 0x8bu, 0x61u, 0x05u, 0x23u, 0x0bu, 0x60u, 0x03u, 0x3bu, 0x4bu, 0x60u, 0x0cu, 0x4bu, 0x80u, 0x32u, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x20u, 0x3bu, 0xccu, 0xe7u, 0x08u, 0x48u, - 0x96u, 0xe7u, 0xc0u, 0x46u, 0xb0u, 0x79u, 0x00u, 0x10u, 0xc4u, 0x79u, 0x00u, 0x10u, 0xe4u, 0x79u, 0x00u, 0x10u, - 0x04u, 0x7au, 0x00u, 0x10u, 0x44u, 0x7au, 0x00u, 0x10u, 0x84u, 0x7au, 0x00u, 0x10u, 0xc4u, 0x7au, 0x00u, 0x10u, + 0x96u, 0xe7u, 0xc0u, 0x46u, 0xd8u, 0x79u, 0x00u, 0x10u, 0xecu, 0x79u, 0x00u, 0x10u, 0x0cu, 0x7au, 0x00u, 0x10u, + 0x2cu, 0x7au, 0x00u, 0x10u, 0x6cu, 0x7au, 0x00u, 0x10u, 0xacu, 0x7au, 0x00u, 0x10u, 0xecu, 0x7au, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0xa0u, 0xffu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x07u, 0x00u, @@ -1309,7 +1309,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x20u, 0x70u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x8fu, 0xb0u, 0x01u, 0x93u, 0x14u, 0xabu, 0x1fu, 0x78u, 0x19u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x00u, 0x91u, 0x16u, 0x00u, 0x1du, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1du, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, - 0x02u, 0xf0u, 0x6du, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, + 0x02u, 0xf0u, 0x7fu, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0cu, 0xffu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x00u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x18u, 0xffu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x00u, 0x28u, 0x03u, 0xd1u, 0x02u, 0xa9u, @@ -1335,7 +1335,7 @@ const uint8_t cy_m0p_image[] = { 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0xceu, 0x21u, 0x04u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x29u, 0x43u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, - 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xb1u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, + 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xc3u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, 0x57u, 0x00u, 0x40u, 0x33u, 0x0bu, 0x61u, 0x69u, 0x23u, 0x4bu, 0x60u, 0x2fu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x08u, 0x60u, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x00u, 0xbdu, 0x40u, 0x33u, 0x0bu, 0x61u, 0x02u, 0x23u, 0x0bu, 0x60u, 0x68u, 0x33u, 0x4bu, 0x60u, 0x28u, 0x4bu, 0xcbu, 0x62u, 0x40u, 0x23u, @@ -1348,9 +1348,9 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x23u, 0x0bu, 0x60u, 0x66u, 0x33u, 0x4bu, 0x60u, 0x10u, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x20u, 0x3bu, 0xd4u, 0xe7u, 0x80u, 0x33u, 0x0bu, 0x61u, 0x06u, 0x23u, 0x0bu, 0x60u, 0x65u, 0x33u, 0x4bu, 0x60u, 0x0au, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, - 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x04u, 0x7bu, 0x00u, 0x10u, 0x38u, 0x7bu, 0x00u, 0x10u, - 0x18u, 0x7bu, 0x00u, 0x10u, 0x98u, 0x7bu, 0x00u, 0x10u, 0x58u, 0x7bu, 0x00u, 0x10u, 0x18u, 0x7cu, 0x00u, 0x10u, - 0xd8u, 0x7bu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, + 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x2cu, 0x7bu, 0x00u, 0x10u, 0x60u, 0x7bu, 0x00u, 0x10u, + 0x40u, 0x7bu, 0x00u, 0x10u, 0xc0u, 0x7bu, 0x00u, 0x10u, 0x80u, 0x7bu, 0x00u, 0x10u, 0x40u, 0x7cu, 0x00u, 0x10u, + 0x00u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0x40u, 0xfeu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x03u, 0x92u, 0x01u, 0x93u, 0x00u, 0xd1u, 0x95u, 0xe0u, @@ -1397,7 +1397,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0xc0u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xfdu, 0x00u, 0x20u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xbfu, 0xb0u, 0x01u, 0x93u, 0x44u, 0xabu, 0x1fu, 0x78u, 0x0du, 0x00u, 0x16u, 0x00u, 0x00u, 0x21u, 0xc0u, 0x22u, 0x0eu, 0xa8u, 0x01u, 0xf0u, - 0xaeu, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xa9u, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, + 0xc0u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xbbu, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x02u, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x2au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x86u, 0xfeu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1422,15 +1422,15 @@ const uint8_t cy_m0p_image[] = { 0x1bu, 0x68u, 0x00u, 0x68u, 0x80u, 0x00u, 0x80u, 0x0cu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xfeu, 0xf7u, 0x47u, 0xfbu, 0x10u, 0xbdu, 0xfeu, 0xf7u, 0x16u, 0xfcu, 0xfbu, 0xe7u, 0xc0u, 0x46u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, 0x12u, 0x68u, 0x89u, 0x06u, 0x29u, 0x32u, 0x12u, 0x78u, 0x1bu, 0x0du, 0x94u, 0x42u, 0xa4u, 0x41u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa5u, 0x40u, 0x0bu, 0x43u, 0x2bu, 0x43u, 0x80u, 0x22u, 0x00u, 0x21u, 0xfeu, 0xf7u, 0x6cu, 0xf8u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, + 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xfeu, 0xf7u, 0x21u, 0xfbu, 0x10u, 0xbdu, - 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, + 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x93u, 0x0eu, 0x00u, 0x01u, 0x92u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x1bu, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2du, 0xd8u, 0x19u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xffu, 0x06u, 0x00u, 0x00u, 0x9au, 0x01u, 0x00u, @@ -1438,14 +1438,14 @@ const uint8_t cy_m0p_image[] = { 0x01u, 0x9au, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, - 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x03u, 0x93u, 0x04u, 0x00u, 0x01u, 0x91u, 0x02u, 0x92u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x16u, 0x4eu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x23u, 0xd8u, 0x14u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x02u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, 0x03u, 0x9bu, 0x02u, 0x00u, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xffu, - 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xbbu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x03u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, @@ -1462,23 +1462,23 @@ const uint8_t cy_m0p_image[] = { 0x18u, 0x68u, 0x14u, 0x68u, 0x43u, 0x6au, 0x22u, 0x6cu, 0x6du, 0x03u, 0x9au, 0x18u, 0x11u, 0x68u, 0x29u, 0x40u, 0x10u, 0xd0u, 0x11u, 0x60u, 0x22u, 0x6cu, 0x9bu, 0x18u, 0x1bu, 0x68u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x53u, 0x1cu, 0xd9u, 0x7fu, 0x00u, 0x29u, 0x07u, 0xd1u, 0x41u, 0x6au, 0x08u, 0x6au, 0x49u, 0x6au, 0x50u, 0x62u, 0x91u, 0x62u, - 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, 0x0du, 0x00u, 0x0bu, 0x60u, 0x43u, 0x68u, 0x4bu, 0x60u, 0x83u, 0x69u, 0x8bu, 0x60u, 0xc3u, 0x69u, 0xcbu, 0x60u, 0x4bu, 0x1cu, 0xdau, 0x77u, 0x03u, 0x8cu, 0x0bu, 0x82u, 0x03u, 0x8du, 0x0bu, 0x83u, 0xfdu, 0xf7u, 0xceu, 0xffu, - 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x5cu, 0xfeu, + 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x6eu, 0xfeu, 0x20u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x1au, 0x4au, 0x13u, 0x60u, 0x1au, 0x4eu, 0x63u, 0x68u, 0x32u, 0x68u, 0x80u, 0x33u, 0x12u, 0x6au, 0x5bu, 0x01u, 0x9bu, 0x18u, 0x80u, 0x22u, 0x21u, 0x68u, 0x52u, 0x02u, 0x8au, 0x40u, 0xe1u, 0x69u, 0x9au, 0x60u, - 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x3du, 0xfeu, 0x28u, 0x23u, + 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x4fu, 0xfeu, 0x28u, 0x23u, 0xe0u, 0x5eu, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x28u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x08u, 0x4au, 0x13u, 0x60u, 0x0au, 0x4au, 0x33u, 0x68u, 0x12u, 0x68u, 0x5bu, 0x6au, 0x92u, 0x6cu, 0x00u, 0x20u, 0x9bu, 0x18u, 0xf8u, 0x22u, 0x52u, 0x03u, 0x1au, 0x60u, 0x06u, 0x4bu, 0x1du, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe1u, 0x5eu, 0x00u, 0x10u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, 0x1fu, 0x2au, 0x04u, 0xd8u, 0x05u, 0x4au, 0x1au, 0x60u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0xbdu, 0x04u, 0x4au, 0xf9u, 0xe7u, 0xc0u, 0x46u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xd8u, 0x03u, 0x00u, 0x08u, 0x58u, 0x7cu, 0x00u, 0x10u, 0xb0u, 0x7cu, 0x00u, 0x10u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xd8u, 0x03u, 0x00u, 0x08u, 0x80u, 0x7cu, 0x00u, 0x10u, 0xd8u, 0x7cu, 0x00u, 0x10u, 0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, 0xb2u, 0x4bu, 0xb3u, 0x4du, 0x63u, 0x60u, 0x2bu, 0x68u, 0x5fu, 0x6au, 0x23u, 0x78u, 0x01u, 0x2bu, 0x18u, 0xd1u, 0x38u, 0x00u, 0xfeu, 0xf7u, 0x21u, 0xf8u, 0x60u, 0x60u, 0x00u, 0x23u, 0xabu, 0x4au, 0xe1u, 0x69u, 0x13u, 0x60u, 0x2bu, 0x68u, 0x1au, 0x00u, @@ -1524,7 +1524,7 @@ const uint8_t cy_m0p_image[] = { 0x40u, 0x6au, 0x52u, 0x69u, 0xb0u, 0x47u, 0x99u, 0xe7u, 0x96u, 0x69u, 0xedu, 0xe7u, 0xd6u, 0x69u, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xedu, 0xe6u, 0xa1u, 0x6au, 0x03u, 0x91u, 0x8bu, 0x6au, 0x02u, 0x93u, 0x4bu, 0x6au, 0x01u, 0x93u, 0x0bu, 0x6au, 0x00u, 0x93u, 0xcbu, 0x69u, 0x8au, 0x69u, 0x40u, 0x6au, 0x49u, 0x69u, 0xb0u, 0x47u, - 0x84u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x84u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0xd8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xc9u, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x00u, 0x93u, 0x8bu, 0x68u, 0x4au, 0x68u, 0x40u, 0x6au, 0x09u, 0x68u, 0xb0u, 0x47u, 0x65u, 0xe7u, @@ -1549,10 +1549,10 @@ const uint8_t cy_m0p_image[] = { 0x29u, 0x6au, 0x80u, 0x33u, 0x5bu, 0x01u, 0xcbu, 0x18u, 0xdeu, 0x68u, 0x82u, 0x40u, 0x36u, 0x0cu, 0xb2u, 0x42u, 0x11u, 0xd1u, 0x12u, 0x04u, 0x1au, 0x60u, 0xacu, 0x35u, 0x1bu, 0x68u, 0x2bu, 0x88u, 0x58u, 0x43u, 0x40u, 0x18u, 0x07u, 0x49u, 0x00u, 0xf0u, 0xb5u, 0xf8u, 0x00u, 0x28u, 0x05u, 0xd1u, 0x23u, 0x68u, 0x9bu, 0x68u, 0x00u, 0x2bu, - 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xdcu, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, - 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xdcu, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u, @@ -1566,26 +1566,26 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au, - 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, - 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0xf8u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, - 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, + 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, - 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xb4u, 0xfau, + 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xc6u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, - 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, @@ -1600,20 +1600,20 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, - 0x98u, 0x47u, 0xf6u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, + 0x98u, 0x47u, 0xf6u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xf8u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, - 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x2bu, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, + 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x3du, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, - 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, + 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xf9u, 0xf7u, 0xc7u, 0xfeu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, @@ -1626,10 +1626,19 @@ const uint8_t cy_m0p_image[] = { 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, - 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, - 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, - 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0x00u, 0x00u, 0x26u, 0x40u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, + 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, + 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x04u, 0x00u, 0x08u, + 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, + 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, + 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, + 0xe7u, 0xffu, 0x02u, 0x28u, 0x1cu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x14u, 0xd0u, 0x01u, 0x28u, 0x14u, 0xd0u, + 0x00u, 0x20u, 0x11u, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x14u, 0xd0u, 0x14u, 0x23u, 0xffu, 0x33u, + 0x98u, 0x42u, 0x18u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0xf2u, 0xd1u, 0x0cu, 0x4au, 0x0cu, 0x4bu, 0xd0u, 0x58u, + 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, 0x18u, 0x68u, 0xfbu, 0xe7u, + 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, 0x18u, 0x40u, 0xf3u, 0xd0u, + 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x04u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, + 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, 0x81u, 0x80u, 0x19u, 0x00u, 0x21u, 0x40u, 0x81u, 0x72u, 0x19u, 0x09u, 0x21u, 0x40u, 0xc1u, 0x72u, 0xd9u, 0x02u, @@ -1639,463 +1648,457 @@ const uint8_t cy_m0p_image[] = { 0x3bu, 0x33u, 0x1bu, 0x78u, 0x93u, 0x42u, 0x16u, 0xd9u, 0x7fu, 0x22u, 0x1fu, 0x24u, 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, - 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xe0u, 0x22u, 0x01u, 0x21u, 0x4du, 0x4bu, 0x80u, 0x00u, - 0xc0u, 0x18u, 0x92u, 0x00u, 0x83u, 0x58u, 0xf0u, 0xb5u, 0x9bu, 0x06u, 0x9bu, 0x0fu, 0x99u, 0x40u, 0x0fu, 0x23u, - 0x84u, 0x58u, 0x89u, 0xb0u, 0x1cu, 0x40u, 0x20u, 0x00u, 0x01u, 0x91u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x03u, 0x28u, - 0x54u, 0xd0u, 0x08u, 0xd8u, 0x01u, 0x28u, 0x13u, 0xd0u, 0x62u, 0xd9u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x42u, 0x4bu, - 0x02u, 0x28u, 0x0bu, 0xd1u, 0x0du, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x50u, 0xd0u, 0x14u, 0x23u, - 0xffu, 0x33u, 0x98u, 0x42u, 0x51u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0x41u, 0xd0u, 0x00u, 0x26u, 0x01u, 0xe0u, - 0x3au, 0x4bu, 0x1eu, 0x68u, 0x00u, 0x2cu, 0x4du, 0xd1u, 0x03u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xddu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0xb0u, 0x23u, 0x31u, 0x4au, 0xdbu, 0x00u, + 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0xffu, 0xf7u, + 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x34u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, + 0x00u, 0xf0u, 0xcfu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, 0x25u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, - 0x03u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, 0x16u, 0xd0u, 0x00u, 0x23u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0xa5u, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, 0x3au, 0x00u, 0x30u, 0x00u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0x9du, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, 0x63u, 0x08u, 0x80u, 0x18u, - 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 0x73u, 0xfcu, 0x06u, 0x00u, 0x01u, 0x9bu, 0x58u, 0x08u, - 0x80u, 0x19u, 0x19u, 0x00u, 0x00u, 0xf0u, 0xe0u, 0xfbu, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x1cu, 0x4bu, 0xc0u, 0xe7u, - 0x18u, 0x4au, 0x1cu, 0x4bu, 0xd3u, 0x58u, 0x00u, 0x2bu, 0xb8u, 0xdau, 0x80u, 0x26u, 0x36u, 0x02u, 0xb9u, 0xe7u, - 0x19u, 0x4bu, 0x1bu, 0x69u, 0x5bu, 0x07u, 0xf8u, 0xd4u, 0xb0u, 0xe7u, 0x12u, 0x4au, 0x17u, 0x4bu, 0xf1u, 0xe7u, - 0x17u, 0x4eu, 0xafu, 0xe7u, 0x17u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, 0xddu, 0xd3u, - 0x03u, 0xadu, 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x89u, 0xfdu, 0x20u, 0x00u, 0x29u, 0x00u, - 0x80u, 0x34u, 0xffu, 0xf7u, 0x49u, 0xffu, 0xffu, 0x34u, 0x06u, 0x4bu, 0xa4u, 0x00u, 0xe3u, 0x58u, 0x00u, 0x24u, - 0xa3u, 0x42u, 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x2fu, 0x78u, 0x68u, 0x78u, - 0xaau, 0x78u, 0xaau, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, 0x00u, 0x04u, 0x00u, 0x08u, 0x04u, 0x04u, 0x00u, 0x08u, - 0x5cu, 0x04u, 0x00u, 0x08u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, - 0x00u, 0x12u, 0x7au, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x14u, 0x4bu, 0x30u, 0xb5u, 0x1au, 0x68u, 0x07u, 0x24u, - 0x13u, 0x00u, 0x28u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x15u, 0xd8u, 0x83u, 0x08u, 0x1du, 0x00u, 0xa5u, 0x43u, - 0x2cu, 0x1eu, 0x0fu, 0xd1u, 0x03u, 0x34u, 0x20u, 0x40u, 0xa0u, 0x40u, 0x81u, 0x40u, 0x12u, 0x68u, 0x9bu, 0x00u, - 0x20u, 0x32u, 0xd3u, 0x18u, 0x0au, 0x00u, 0xffu, 0x21u, 0x81u, 0x40u, 0x1cu, 0x68u, 0x62u, 0x40u, 0x11u, 0x40u, - 0x61u, 0x40u, 0x19u, 0x60u, 0x30u, 0xbdu, 0x80u, 0x23u, 0x20u, 0x40u, 0x1bu, 0x06u, 0x18u, 0x43u, 0x80u, 0x23u, - 0x9bu, 0x01u, 0x12u, 0x68u, 0xc9u, 0x18u, 0x89u, 0x00u, 0x88u, 0x50u, 0xf3u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, - 0x06u, 0x4bu, 0x9au, 0x68u, 0x03u, 0x00u, 0x06u, 0x48u, 0x10u, 0x33u, 0x9bu, 0x00u, 0x82u, 0x42u, 0x02u, 0xd1u, - 0x98u, 0x58u, 0x99u, 0x50u, 0x70u, 0x47u, 0x03u, 0x4au, 0xd0u, 0x58u, 0xfbu, 0xe7u, 0x00u, 0xedu, 0x00u, 0xe0u, - 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x10u, 0xf8u, 0xb5u, 0x06u, 0x00u, 0x0du, 0x00u, 0x00u, 0x28u, - 0x3au, 0xd0u, 0x00u, 0x23u, 0xc0u, 0x5eu, 0x00u, 0x28u, 0x28u, 0xdbu, 0x71u, 0x88u, 0xffu, 0xf7u, 0xb4u, 0xffu, - 0x00u, 0x24u, 0xffu, 0x22u, 0x03u, 0x27u, 0x94u, 0x46u, 0x00u, 0x23u, 0xf0u, 0x5eu, 0x71u, 0x68u, 0x83u, 0xb2u, - 0x1fu, 0x40u, 0xffu, 0x00u, 0x66u, 0x46u, 0xbau, 0x40u, 0x89u, 0x01u, 0x31u, 0x40u, 0xd2u, 0x43u, 0xb9u, 0x40u, - 0x00u, 0x28u, 0x15u, 0xdbu, 0x11u, 0x4eu, 0x83u, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u, 0xc0u, 0x26u, 0xb6u, 0x00u, - 0x9fu, 0x59u, 0x3au, 0x40u, 0x11u, 0x43u, 0x99u, 0x51u, 0x0du, 0x4bu, 0x9au, 0x68u, 0x0du, 0x4bu, 0x9au, 0x42u, - 0x02u, 0xd1u, 0x29u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu, 0x20u, 0x00u, 0xf8u, 0xbdu, 0x0au, 0x4cu, 0xd8u, 0xe7u, - 0x0fu, 0x26u, 0x33u, 0x40u, 0x08u, 0x3bu, 0x06u, 0x4eu, 0x9bu, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u, 0xdeu, 0x69u, - 0x32u, 0x40u, 0x11u, 0x43u, 0xd9u, 0x61u, 0xe7u, 0xe7u, 0x03u, 0x4cu, 0xedu, 0xe7u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, 0x01u, 0x00u, 0x56u, 0x00u, 0xfeu, 0xe7u, 0x00u, 0x00u, - 0x02u, 0x68u, 0x0au, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x60u, 0x42u, 0x68u, 0x5au, 0x60u, 0x82u, 0x68u, 0x9au, 0x60u, - 0xc2u, 0x68u, 0xdau, 0x60u, 0x02u, 0x69u, 0x1au, 0x61u, 0x42u, 0x69u, 0x5au, 0x61u, 0x82u, 0x69u, 0x9au, 0x61u, - 0xc2u, 0x69u, 0xdau, 0x61u, 0xffu, 0xf7u, 0xeau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x90u, 0x03u, 0x00u, 0x08u, - 0xb0u, 0x23u, 0x5bu, 0x05u, 0x9au, 0x89u, 0x00u, 0x2au, 0x02u, 0xd0u, 0x98u, 0x89u, 0x80u, 0xb2u, 0x70u, 0x47u, - 0x80u, 0x20u, 0x40u, 0x00u, 0xfbu, 0xe7u, 0x00u, 0x00u, 0x7fu, 0xb5u, 0x27u, 0x4bu, 0x86u, 0x00u, 0x0du, 0x00u, - 0xf4u, 0x58u, 0x04u, 0x29u, 0x01u, 0xd0u, 0x01u, 0x29u, 0x27u, 0xd1u, 0x00u, 0x20u, 0x0fu, 0xe0u, 0xa3u, 0x68u, - 0x2bu, 0x42u, 0x0bu, 0xd1u, 0xe3u, 0x68u, 0x29u, 0x00u, 0x1au, 0x68u, 0x5bu, 0x68u, 0x02u, 0x92u, 0x01u, 0x93u, - 0x03u, 0x93u, 0x02u, 0xa8u, 0x23u, 0x68u, 0x98u, 0x47u, 0x1cu, 0x4bu, 0x1cu, 0x60u, 0x64u, 0x69u, 0x00u, 0x2cu, - 0x0bu, 0xd0u, 0x1bu, 0x4bu, 0x98u, 0x42u, 0xeau, 0xd1u, 0x01u, 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0x00u, 0x41u, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, 0x1fu, 0xd0u, 0x9au, 0x68u, - 0xe0u, 0x32u, 0x12u, 0x68u, 0xd2u, 0x06u, 0x1au, 0xd5u, 0xf2u, 0x22u, 0xdbu, 0x68u, 0xd2u, 0x01u, 0x9au, 0x58u, - 0x02u, 0x60u, 0xf0u, 0x22u, 0xd2u, 0x01u, 0x9au, 0x58u, 0x42u, 0x60u, 0x0au, 0x4au, 0x9au, 0x58u, 0x82u, 0x60u, - 0x09u, 0x4au, 0x9au, 0x58u, 0xc2u, 0x60u, 0x09u, 0x4au, 0x9au, 0x58u, 0x02u, 0x61u, 0x08u, 0x4au, 0x9au, 0x58u, - 0x42u, 0x61u, 0x08u, 0x4au, 0x9au, 0x58u, 0x82u, 0x61u, 0x07u, 0x4au, 0x9bu, 0x58u, 0xc3u, 0x61u, 0x70u, 0x47u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x04u, 0x78u, 0x00u, 0x00u, 0x08u, 0x78u, 0x00u, 0x00u, 0x0cu, 0x78u, 0x00u, 0x00u, - 0x10u, 0x78u, 0x00u, 0x00u, 0x14u, 0x78u, 0x00u, 0x00u, 0x18u, 0x78u, 0x00u, 0x00u, 0x19u, 0x4bu, 0x1bu, 0x68u, - 0x1au, 0x1du, 0x19u, 0x68u, 0xd2u, 0x6fu, 0x8au, 0x18u, 0x01u, 0x6au, 0x11u, 0x60u, 0x1au, 0x00u, 0x08u, 0x32u, - 0x19u, 0x68u, 0xd2u, 0x6fu, 0x8au, 0x18u, 0x41u, 0x6au, 0x11u, 0x60u, 0x1au, 0x00u, 0x41u, 0x32u, 0x12u, 0x78u, - 0x00u, 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0x01u, 0x20u, 0x00u, 0xf0u, + 0x9du, 0xf8u, 0x00u, 0x25u, 0xa8u, 0x42u, 0xecu, 0xd1u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xafu, 0xf8u, 0x1eu, 0x4au, + 0x1fu, 0x4bu, 0x90u, 0x42u, 0x03u, 0xd0u, 0x9du, 0x42u, 0xe3u, 0xd0u, 0x01u, 0x35u, 0xf4u, 0xe7u, 0x9du, 0x42u, + 0xb9u, 0xd1u, 0xdeu, 0xe7u, 0x17u, 0x4cu, 0x03u, 0x2fu, 0x05u, 0xd1u, 0x01u, 0x21u, 0x00u, 0x20u, 0x00u, 0xf0u, + 0xadu, 0xf8u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x88u, 0xf8u, 0xd2u, 0xe7u, 0x15u, 0x4cu, + 0xf1u, 0xe7u, 0x00u, 0xf0u, 0x6bu, 0xf8u, 0x0eu, 0x4au, 0x05u, 0x00u, 0x01u, 0x21u, 0x30u, 0x00u, 0x00u, 0xf0u, + 0x6du, 0xf8u, 0x00u, 0x28u, 0x09u, 0xd1u, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x08u, 0xd0u, 0x23u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xdbu, 0x00u, 0xf0u, 0x9bu, 0xf8u, 0x04u, 0x00u, 0xe5u, 0xe7u, 0x06u, 0x4cu, 0xe3u, 0xe7u, 0x09u, 0x4cu, + 0xe1u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, + 0xe4u, 0x03u, 0x00u, 0x08u, 0x05u, 0x00u, 0x52u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u, 0xf4u, 0x03u, 0x00u, 0x08u, + 0xf0u, 0x49u, 0x02u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, 0x18u, 0x4bu, 0xf7u, 0xb5u, 0x1bu, 0x68u, 0x18u, 0x4au, + 0x5cu, 0x68u, 0x04u, 0x23u, 0x11u, 0x69u, 0x0bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x28u, 0x24u, 0xd0u, 0x30u, 0xbfu, + 0x23u, 0x00u, 0xfcu, 0x33u, 0x1bu, 0x69u, 0x00u, 0x2bu, 0x1du, 0xd1u, 0xa3u, 0x20u, 0x11u, 0x4bu, 0x12u, 0x49u, + 0x12u, 0x4au, 0xc0u, 0x00u, 0x0fu, 0x68u, 0x1eu, 0x58u, 0x15u, 0x68u, 0x01u, 0x95u, 0x10u, 0x4du, 0x0du, 0x60u, + 0x06u, 0x25u, 0x1du, 0x50u, 0x3eu, 0x20u, 0x10u, 0x60u, 0x0eu, 0x48u, 0x3eu, 0x35u, 0x1du, 0x50u, 0x1du, 0x58u, + 0x00u, 0x2du, 0xfcu, 0xdau, 0x0cu, 0x48u, 0xfcu, 0x34u, 0x20u, 0x61u, 0x0fu, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, + 0x5eu, 0x50u, 0x01u, 0x9bu, 0x13u, 0x60u, 0xf7u, 0xbdu, 0x20u, 0xbfu, 0xd9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u, + 0x1eu, 0x1fu, 0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u, 0xaau, 0xaau, 0xaau, 0xaau, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xdbu, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x69u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x75u, 0x61u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xe3u, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xbdu, 0x6cu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xa5u, 0x63u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x41u, 0x5fu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x31u, 0x63u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x05u, 0x60u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A2M) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_03_cm0p_crypto.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_03_cm0p_crypto.c index 37fdf2d4aa..271f571262 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_03_cm0p_crypto.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_03_cm0p_crypto.c @@ -37,19 +37,19 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xb4u, 0x03u, 0x00u, 0x08u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x63u, 0xfdu, 0x06u, 0xf0u, 0x03u, 0xfdu, 0xfeu, 0xe7u, - 0x2cu, 0x7eu, 0x00u, 0x10u, 0x44u, 0x7eu, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x06u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x75u, 0xfdu, 0x06u, 0xf0u, 0x15u, 0xfdu, 0xfeu, 0xe7u, + 0x54u, 0x7eu, 0x00u, 0x10u, 0x6cu, 0x7eu, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x06u, 0xf0u, 0xf5u, 0xfau, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, + 0x04u, 0x30u, 0x06u, 0xf0u, 0x07u, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x52u, 0x69u, 0x82u, 0x18u, 0x08u, 0x78u, 0x49u, 0x68u, 0x38u, 0x40u, 0x10u, 0x60u, 0x01u, 0x2cu, 0x00u, 0xd1u, 0x20u, 0x31u, 0x28u, 0x00u, 0x08u, 0x9au, 0x01u, 0x3cu, 0x03u, 0xf0u, 0x72u, 0xfdu, 0x0cu, 0x23u, 0x61u, 0x42u, 0x61u, 0x41u, 0x00u, 0x93u, 0x28u, 0x00u, 0x08u, 0x3bu, 0x44u, 0x31u, 0x00u, 0x22u, @@ -95,7 +95,7 @@ const uint8_t cy_m0p_image[] = { 0xd3u, 0xfeu, 0x10u, 0x23u, 0x2au, 0x00u, 0x07u, 0x99u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xcbu, 0xfcu, 0x10u, 0x3cu, 0xcfu, 0xe7u, 0x01u, 0x48u, 0xdfu, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x91u, 0xb0u, 0x19u, 0x9du, 0x04u, 0x00u, 0x06u, 0x91u, 0x0bu, 0x92u, 0x00u, 0x21u, 0x10u, 0x22u, 0x0cu, 0xa8u, 0x07u, 0x93u, - 0x06u, 0xf0u, 0x5du, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, + 0x06u, 0xf0u, 0x6fu, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, 0x10u, 0x32u, 0x04u, 0x92u, 0x05u, 0x93u, 0x07u, 0x9au, 0x10u, 0x23u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xaau, 0xfcu, 0x0fu, 0x9bu, 0x1bu, 0xbau, 0x08u, 0x93u, 0x06u, 0x9bu, 0x08u, 0x9eu, 0x1bu, 0x09u, 0x0au, 0x93u, 0x0eu, 0x9bu, 0x1fu, 0xbau, 0x08u, 0x9bu, 0x17u, 0x99u, 0xf3u, 0x1au, 0x1au, 0x01u, 0x89u, 0x18u, 0x09u, 0x91u, 0x18u, 0x99u, @@ -253,7 +253,7 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x28u, 0x00u, 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0xf0u, 0xb5u, 0x10u, 0x25u, 0x87u, 0xb0u, 0x0fu, 0x00u, 0x04u, 0x00u, 0x01u, 0x92u, 0x00u, 0x21u, 0x2au, 0x00u, - 0x02u, 0xa8u, 0x06u, 0xf0u, 0x6cu, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, + 0x02u, 0xa8u, 0x06u, 0xf0u, 0x7eu, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, 0x02u, 0xa9u, 0xeau, 0x1bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x18u, 0x4du, 0x19u, 0x4au, 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0fu, 0x2fu, 0x02u, 0xd8u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x10u, 0x22u, 0x31u, 0x00u, 0x20u, 0x00u, @@ -264,7 +264,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x08u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x1eu, 0x00u, 0xa7u, 0xb0u, 0x2cu, 0xabu, 0x0au, 0xadu, 0x1fu, 0x78u, 0x02u, 0x91u, 0x03u, 0x92u, 0x00u, 0x21u, 0x70u, 0x22u, 0x28u, 0x00u, - 0x06u, 0xf0u, 0x15u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x10u, 0xf9u, 0x3au, 0x00u, + 0x06u, 0xf0u, 0x27u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x22u, 0xf9u, 0x3au, 0x00u, 0x2eu, 0x9bu, 0x31u, 0x00u, 0x00u, 0x95u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf3u, 0xfbu, 0x2eu, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfbu, 0x06u, 0xabu, 0x04u, 0xa9u, 0x20u, 0x00u, 0x05u, 0x93u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x03u, 0x9bu, 0x02u, 0x9au, 0x04u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x60u, 0xffu, 0x20u, 0x00u, 0x2du, 0x9au, @@ -304,7 +304,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x45u, 0xfeu, 0x02u, 0x9bu, 0x04u, 0x9au, 0x28u, 0x00u, 0x01u, 0x97u, 0x00u, 0x96u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x28u, 0x00u, 0x08u, 0x23u, 0x32u, 0x00u, 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, - 0x38u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, + 0x60u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x07u, 0x93u, 0x25u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x06u, 0x91u, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x03u, 0x93u, 0x00u, 0x27u, 0x1fu, 0x4bu, 0x04u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x05u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, @@ -314,7 +314,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0xf6u, 0xfdu, 0x03u, 0x9fu, 0x03u, 0x9bu, 0x08u, 0x37u, 0x01u, 0x93u, 0x06u, 0x9au, 0x33u, 0x00u, 0x20u, 0x00u, 0x00u, 0x97u, 0x01u, 0x21u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x3au, 0x00u, 0x07u, 0x99u, 0x02u, 0xf0u, 0xe5u, 0xfdu, 0x28u, 0x00u, 0x09u, 0xb0u, 0xf0u, 0xbdu, - 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x38u, 0x71u, 0x00u, 0x10u, + 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x60u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0x86u, 0x25u, 0x6du, 0x01u, 0x44u, 0x59u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0xdcu, 0x68u, 0x05u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, 0x21u, 0x60u, @@ -335,7 +335,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x52u, 0x31u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x28u, 0x00u, - 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xb8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x27u, 0x85u, 0xb0u, 0x02u, 0x91u, 0x00u, 0x92u, 0x03u, 0x93u, 0x26u, 0x4bu, 0x00u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x01u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x00u, 0x28u, 0x04u, 0xd0u, 0x01u, 0x9bu, 0x9du, 0x42u, @@ -346,15 +346,15 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x02u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x54u, 0x31u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x3cu, 0xffu, 0x28u, 0x00u, 0x05u, 0xb0u, - 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xb8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x42u, 0x1eu, 0x03u, 0x00u, 0x00u, 0x20u, 0x04u, 0x2au, 0x03u, 0xd8u, 0x28u, 0x30u, 0x58u, 0x43u, 0x01u, 0x4bu, - 0xc0u, 0x18u, 0x70u, 0x47u, 0x38u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0xc0u, 0x18u, 0x70u, 0x47u, 0x60u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, + 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xf2u, 0xf9u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0xadu, 0xb0u, 0x04u, 0x00u, 0x04u, 0x91u, 0x05u, 0x92u, 0x03u, 0x93u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x15u, 0xe1u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x11u, 0xe1u, 0x32u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x0du, 0xe1u, 0x33u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x09u, 0xe1u, 0x32u, 0x9bu, 0x58u, 0x78u, 0xffu, 0xf7u, @@ -392,7 +392,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x00u, 0xd0u, 0x71u, 0xe7u, 0x03u, 0x9bu, 0xe9u, 0x1du, 0xc9u, 0x08u, 0x59u, 0x18u, 0x0au, 0x22u, 0x2bu, 0x00u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xc4u, 0xf8u, 0x68u, 0xe7u, 0x08u, 0x4eu, 0x6bu, 0xe7u, 0x07u, 0x4eu, 0x6eu, 0xe7u, 0x07u, 0x4eu, 0x6cu, 0xe7u, 0xc0u, 0x46u, 0x09u, 0x80u, 0x00u, 0x00u, 0x01u, 0x00u, 0x32u, 0x00u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0x0fu, 0x1eu, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0xd1u, 0x8bu, 0xe1u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x88u, 0xe1u, 0x0cu, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x84u, 0xe1u, 0x0du, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x80u, 0xe1u, 0x58u, 0x78u, 0xffu, 0xf7u, 0x78u, 0xfeu, @@ -444,11 +444,11 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x7au, 0xffu, 0x00u, 0x28u, 0x09u, 0xd0u, 0x01u, 0x23u, 0x0cu, 0x9au, 0x13u, 0x70u, 0x0eu, 0x49u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x27u, 0xfdu, 0x38u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x0cu, 0x9bu, 0x18u, 0x70u, 0xf5u, 0xe7u, 0x04u, 0x4fu, 0x09u, 0x49u, 0xf3u, 0xe7u, 0x02u, 0x4fu, 0xf4u, 0xe7u, - 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x80u, 0x80u, 0x00u, 0x00u, 0x08u, 0x60u, 0x00u, 0x00u, 0x06u, 0x80u, 0x00u, 0x00u, 0xf1u, 0x7eu, 0x00u, 0x00u, 0x30u, 0x60u, 0x00u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x85u, 0xb0u, 0x08u, 0x00u, 0x02u, 0x91u, 0x03u, 0x92u, 0x1eu, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xfcu, 0x07u, 0x1eu, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x77u, 0xe0u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x74u, 0xe0u, 0x73u, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x70u, 0xe0u, 0xb3u, 0x68u, @@ -473,24 +473,24 @@ const uint8_t cy_m0p_image[] = { 0x10u, 0xbdu, 0x00u, 0x00u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x0fu, 0xfeu, 0x10u, 0xbdu, 0x0fu, 0x23u, 0x13u, 0x43u, - 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, + 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x05u, 0xd8u, 0x05u, 0x4bu, 0x21u, 0x22u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xc0u, 0xc0u, 0x00u, 0x00u, 0xcfu, 0xc0u, 0x00u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x10u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0xeau, 0xfdu, 0x10u, 0xbdu, 0x09u, 0x03u, 0x0bu, 0x00u, 0x13u, 0x43u, 0x00u, 0x22u, 0x10u, 0xb5u, 0x11u, 0x00u, 0x01u, 0xf0u, 0xe1u, 0xfdu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, + 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, 0x07u, 0x4au, 0x15u, 0x68u, 0x24u, 0x22u, 0x29u, 0x35u, 0x2du, 0x78u, 0x1fu, 0x2du, 0x00u, 0xd9u, 0x01u, 0x3au, 0x24u, 0x01u, 0x23u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xa5u, 0xfdu, 0x70u, 0xbdu, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x23u, 0x10u, 0xb5u, 0x11u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0x95u, 0xfdu, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x1bu, 0x4du, 0xffu, 0xf7u, 0x9fu, 0xffu, 0x20u, 0x00u, 0x01u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x9cu, 0xffu, 0x2au, 0x00u, @@ -523,7 +523,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x70u, 0xfeu, 0x94u, 0x4bu, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x0bu, 0xd0u, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x00u, 0xf0u, 0x35u, 0xfdu, 0x0eu, 0x9bu, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x00u, 0xf0u, 0x24u, 0xfdu, 0x8du, 0x4bu, 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0x01u, 0xd9u, 0x00u, 0xf0u, - 0x1du, 0xfdu, 0x04u, 0xf0u, 0x27u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, + 0x1du, 0xfdu, 0x04u, 0xf0u, 0x39u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xfeu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xfeu, 0x80u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xfeu, 0xc0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9du, 0xfeu, 0xc0u, 0x22u, @@ -688,7 +688,7 @@ const uint8_t cy_m0p_image[] = { 0x8bu, 0xffu, 0x00u, 0x21u, 0x44u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x85u, 0xffu, 0xe0u, 0x21u, 0x49u, 0x00u, 0xffu, 0xf7u, 0x69u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xeau, 0xf9u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xf9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdcu, 0xf9u, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x42u, 0x4bu, - 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0xf2u, 0xf9u, 0x05u, 0x00u, 0x84u, 0x00u, + 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x04u, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, 0xd1u, 0x00u, 0xc7u, 0x01u, 0xedu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xf9u, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x73u, 0xf9u, 0x02u, 0x22u, 0x00u, 0x21u, 0xffu, 0x32u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x80u, 0x22u, 0x01u, 0x21u, @@ -715,7 +715,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xb0u, 0xfeu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x01u, 0x23u, 0xffu, 0xf7u, 0x5du, 0xf8u, 0x20u, 0x00u, 0x03u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xf8u, 0x01u, 0x23u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3eu, 0xf8u, 0x7fu, 0xe7u, 0x1cu, 0x22u, - 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0xf2u, 0xfau, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, + 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x04u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xf8u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xf8u, 0xe0u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xf8u, 0xf0u, 0x22u, 0x00u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xf8u, 0x80u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, @@ -746,7 +746,7 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x69u, 0xffu, 0x3eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xb0u, 0xfdu, 0x00u, 0x21u, 0x3eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xaau, 0xfdu, 0x23u, 0x21u, 0xffu, 0xf7u, 0x8fu, 0xf9u, 0x39u, 0x49u, 0x11u, 0x22u, 0x1cu, 0x31u, - 0x01u, 0xa8u, 0x04u, 0xf0u, 0xfbu, 0xf9u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, + 0x01u, 0xa8u, 0x04u, 0xf0u, 0x0du, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb0u, 0xffu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xabu, 0xffu, 0x31u, 0x4au, 0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xafu, 0xffu, 0xf0u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa9u, 0xffu, 0x81u, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa4u, 0xffu, @@ -760,7 +760,7 @@ const uint8_t cy_m0p_image[] = { 0x4bu, 0xfdu, 0x04u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf8u, 0xfeu, 0x4eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x3fu, 0xfdu, 0x00u, 0x21u, 0x07u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x39u, 0xfdu, 0x43u, 0x21u, 0xffu, 0xf7u, 0x1eu, 0xf9u, 0x12u, 0x10u, 0x00u, 0x00u, - 0x2du, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, + 0x55u, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0xfeu, 0xf7u, 0xdau, 0xfeu, 0x09u, 0x4bu, 0x26u, 0x01u, 0x33u, 0x43u, 0x28u, 0x00u, 0x3du, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x1fu, 0xfdu, 0x24u, 0x03u, 0x05u, 0x4bu, 0x34u, 0x43u, 0x28u, 0x00u, 0x23u, 0x43u, 0x37u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x16u, 0xfdu, 0x70u, 0xbdu, 0xc0u, 0x46u, @@ -772,7 +772,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xfcu, 0x0bu, 0x4bu, 0x2du, 0x03u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x07u, 0xd8u, 0x2bu, 0x00u, 0x26u, 0x22u, 0x3bu, 0x43u, 0x30u, 0x00u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xddu, 0xfcu, 0xf8u, 0xbdu, 0x0fu, 0x23u, 0x2bu, 0x43u, 0x3bu, 0x43u, 0x25u, 0x22u, 0xf5u, 0xe7u, 0xc0u, 0x46u, 0x0eu, 0x00u, 0x80u, 0x00u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x0du, 0x00u, 0xfeu, 0xf7u, 0xd5u, 0xfeu, 0x3au, 0x00u, 0x07u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd7u, 0xfeu, 0x32u, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd2u, 0xfeu, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xcdu, 0xfeu, 0x06u, 0x9au, 0x09u, 0x21u, @@ -867,7 +867,7 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x90u, 0x08u, 0x22u, 0x00u, 0x97u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd0u, 0xfeu, 0x01u, 0x22u, 0x05u, 0x9bu, 0x13u, 0x42u, 0x0au, 0xd0u, 0x0bu, 0x23u, 0x01u, 0x93u, 0x01u, 0x3bu, 0x00u, 0x93u, 0x02u, 0x97u, 0x01u, 0x3bu, 0x07u, 0x32u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0eu, 0xfeu, 0x01u, 0x35u, 0xcdu, 0xe7u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x80u, 0x22u, 0x0du, 0x4bu, 0x52u, 0x00u, 0x90u, 0x42u, 0x11u, 0xd0u, 0x07u, 0xd8u, 0x01u, 0x22u, 0xc0u, 0x28u, 0x0eu, 0xd0u, 0x02u, 0x22u, 0xe0u, 0x28u, 0x0bu, 0xd0u, 0x00u, 0x22u, 0x09u, 0xe0u, 0xc0u, 0x22u, 0x52u, 0x00u, 0x90u, 0x42u, 0x07u, 0xd0u, 0x05u, 0x4au, 0x90u, 0x42u, 0xf6u, 0xd1u, 0x05u, 0x22u, 0x00u, 0xe0u, 0x03u, 0x22u, @@ -876,7 +876,7 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x98u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2fu, 0xffu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x62u, 0xfbu, 0x13u, 0xbdu, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x93u, 0xb0u, 0x05u, 0x93u, 0x1au, 0xabu, 0x1cu, 0x78u, 0x65u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x03u, 0x91u, 0x04u, 0x92u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, - 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0xf1u, 0xfdu, 0x33u, 0x00u, 0x81u, 0x33u, + 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x03u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, 0x22u, 0x00u, 0xffu, 0x33u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0xfcu, 0xfbu, 0x04u, 0x1eu, 0x00u, 0xd0u, 0x86u, 0xe0u, 0x33u, 0x00u, 0x80u, 0x33u, 0x01u, 0x93u, 0x98u, 0x23u, 0x01u, 0x9au, 0xdbu, 0x00u, 0x77u, 0x1cu, 0xf6u, 0x50u, 0xffu, 0x37u, 0xf3u, 0x18u, 0x5au, 0x60u, 0x9fu, 0x60u, 0x19u, 0x9au, 0x09u, 0x9bu, 0x9au, 0x42u, @@ -902,8 +902,8 @@ const uint8_t cy_m0p_image[] = { 0x86u, 0xe7u, 0xfau, 0x5cu, 0x01u, 0x9cu, 0x4au, 0x40u, 0xf2u, 0x54u, 0xfau, 0x5cu, 0x42u, 0x40u, 0xe2u, 0x54u, 0x01u, 0x33u, 0x80u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, 0x04u, 0x92u, 0x93u, 0x22u, 0x05u, 0x93u, 0x13u, 0xaeu, 0xaeu, 0xabu, 0x1cu, 0x78u, 0x03u, 0x91u, 0x92u, 0x00u, - 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x23u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, - 0x1eu, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, + 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x35u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, + 0x30u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, 0x3bu, 0xd1u, 0x90u, 0x23u, 0x9bu, 0x00u, 0xf6u, 0x50u, 0x33u, 0xaau, 0x04u, 0x33u, 0xf2u, 0x50u, 0x0au, 0x9fu, 0x04u, 0x33u, 0x53u, 0xaau, 0xf2u, 0x50u, 0x10u, 0x9bu, 0xbeu, 0xb2u, 0x01u, 0x93u, 0x02u, 0x00u, 0x33u, 0x00u, 0x53u, 0xa9u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x6eu, 0xfcu, 0xadu, 0x9bu, 0xbbu, 0x42u, 0x2eu, 0xd9u, 0x07u, 0xa9u, @@ -934,9 +934,9 @@ const uint8_t cy_m0p_image[] = { 0x52u, 0x02u, 0xc3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd0u, 0x23u, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x22u, 0x0eu, 0x21u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0du, 0x21u, 0xffu, 0xf7u, 0xdfu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0bu, 0x21u, 0xffu, 0xf7u, 0xd5u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0au, 0x21u, @@ -949,7 +949,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xffu, 0x03u, 0x4bu, 0x0fu, 0x21u, 0x1au, 0x68u, 0x20u, 0x00u, 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0xd4u, 0x03u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x04u, 0x4bu, 0x1fu, 0x2au, 0x00u, 0xd9u, 0x04u, 0x4bu, 0x04u, 0x4au, 0x13u, 0x60u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x5cu, 0x78u, 0x00u, 0x10u, 0xb0u, 0x78u, 0x00u, 0x10u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x84u, 0x78u, 0x00u, 0x10u, 0xd8u, 0x78u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, 0x00u, 0x29u, 0x09u, 0xd1u, 0x00u, 0x2cu, 0x28u, 0xd1u, 0x13u, 0x6du, 0xc1u, 0x18u, 0x2au, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x6cu, 0x00u, 0x29u, 0x21u, 0xd0u, 0xa4u, 0x00u, 0x28u, 0x4bu, 0x65u, 0x1eu, 0x9du, 0x42u, 0x1cu, 0xd8u, @@ -962,7 +962,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xd1u, 0x1fu, 0x2eu, 0x02u, 0xd9u, 0x10u, 0x4du, 0x1bu, 0x02u, 0x43u, 0x51u, 0x93u, 0x6bu, 0xa2u, 0x08u, 0xc3u, 0x18u, 0x19u, 0x60u, 0x0fu, 0x21u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x00u, 0x20u, 0x0bu, 0x4bu, 0x1cu, 0x60u, 0x70u, 0xbdu, 0x7cu, 0x23u, 0xe4u, 0xe7u, 0x78u, 0x23u, 0xe2u, 0xe7u, 0x60u, 0x23u, 0xe0u, 0xe7u, 0x40u, 0x23u, - 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, + 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0xd4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x4bu, 0x21u, 0x49u, 0x1bu, 0x68u, 0x09u, 0x68u, 0x9au, 0x6cu, 0x92u, 0x00u, 0x00u, 0x29u, 0x1cu, 0xd0u, 0x1eu, 0x49u, 0x09u, 0x68u, 0x00u, 0x29u, 0x18u, 0xd0u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2fu, 0xd9u, @@ -972,18 +972,18 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0xd0u, 0x7fu, 0x2bu, 0xf9u, 0xd1u, 0x80u, 0x22u, 0x52u, 0x00u, 0xf6u, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x01u, 0xf3u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x01u, 0xf0u, 0xe7u, 0x80u, 0x22u, 0x52u, 0x01u, 0xedu, 0xe7u, 0x80u, 0x22u, 0x12u, 0x01u, 0xeau, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x00u, 0xe7u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x00u, 0xe4u, 0xe7u, - 0x0au, 0x00u, 0xe2u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x0au, 0x00u, 0xe2u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, 0x88u, 0x14u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x17u, 0x4au, 0x18u, 0x49u, 0x13u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x17u, 0xd8u, 0x16u, 0x4bu, 0x23u, 0x60u, 0x01u, 0x20u, 0x09u, 0x68u, 0x4bu, 0x6bu, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x13u, 0x68u, 0x09u, 0x6du, 0x9au, 0x6cu, 0x61u, 0x18u, 0x92u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x23u, 0x68u, 0x0bu, 0x48u, 0x03u, 0x40u, 0x23u, 0x60u, 0x0bu, 0x68u, 0x0au, 0x48u, 0x5bu, 0x68u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x80u, 0x23u, 0x20u, 0x68u, - 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0xd4u, 0x03u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, 0x01u, 0x00u, 0x02u, 0x00u, 0x03u, 0x23u, 0x03u, 0x70u, 0x00u, 0x20u, 0x70u, 0x47u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x00u, 0x23u, 0x03u, 0x60u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x20u, 0x03u, 0x4bu, - 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x01u, 0x29u, 0x0bu, 0xd9u, 0x01u, 0x22u, 0x0au, 0x40u, 0x54u, 0x42u, 0x62u, 0x41u, 0xcbu, 0x0fu, 0x5bu, 0x18u, 0x5bu, 0x10u, 0x9bu, 0x1au, 0x02u, 0x00u, 0x01u, 0x39u, 0x8bu, 0x42u, 0x00u, 0xdbu, 0x30u, 0xbdu, 0x14u, 0x78u, 0x45u, 0x5cu, 0x15u, 0x70u, 0x44u, 0x54u, 0x01u, 0x32u, 0x01u, 0x39u, 0xf5u, 0xe7u, 0x00u, 0x00u, @@ -1085,25 +1085,25 @@ const uint8_t cy_m0p_image[] = { 0x19u, 0x68u, 0x0bu, 0x68u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0x8bu, 0x69u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xffu, 0xf7u, 0x05u, 0xfeu, 0x10u, 0xbdu, - 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, + 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, - 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, + 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xffu, 0xf7u, - 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x03u, 0x34u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xd6u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xc5u, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x09u, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x0bu, 0x43u, 0x21u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x8du, 0xfau, 0x10u, 0xbdu, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x1du, 0x00u, 0x5eu, 0x1cu, 0x01u, 0x92u, 0x0fu, 0x00u, 0x32u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xccu, 0xffu, 0x32u, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x32u, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x2au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1116,7 +1116,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x2au, 0xfau, 0x0du, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x24u, 0xfau, 0x33u, 0x00u, 0x3au, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfau, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x02u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, - 0x01u, 0x3du, 0xd9u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, + 0x01u, 0x3du, 0xd9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x9eu, 0x00u, 0x91u, 0x15u, 0x00u, 0x01u, 0x21u, 0x72u, 0x1cu, 0x77u, 0x00u, 0x01u, 0x93u, 0xffu, 0xf7u, 0x63u, 0xffu, 0x3au, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5eu, 0xffu, 0x3au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x59u, 0xffu, 0x32u, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, @@ -1138,7 +1138,7 @@ const uint8_t cy_m0p_image[] = { 0x7bu, 0xf9u, 0x20u, 0x00u, 0x10u, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x75u, 0xf9u, 0x00u, 0x9bu, 0x20u, 0x00u, 0x1au, 0x03u, 0x02u, 0x23u, 0x00u, 0x21u, 0x13u, 0x43u, 0x30u, 0x22u, 0xffu, 0xf7u, 0x6cu, 0xf9u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, 0x3au, 0x10u, 0x00u, 0x00u, - 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, + 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, 0x10u, 0x10u, 0x00u, 0x00u, 0x21u, 0x30u, 0x00u, 0x00u, 0x23u, 0x00u, 0x30u, 0x00u, 0x28u, 0x30u, 0x00u, 0x00u, 0xf7u, 0xb5u, 0x06u, 0x00u, 0x1cu, 0x00u, 0x09u, 0x9bu, 0x01u, 0x91u, 0x5fu, 0x00u, 0x15u, 0x00u, 0x02u, 0x21u, 0x3au, 0x00u, 0xffu, 0xf7u, 0xabu, 0xfeu, 0x3au, 0x00u, 0x03u, 0x21u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xfeu, @@ -1156,7 +1156,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xf8u, 0x01u, 0x9bu, 0x30u, 0x00u, 0x1cu, 0x03u, 0x0du, 0x4bu, 0x30u, 0x22u, 0x23u, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xe2u, 0xf8u, 0xc0u, 0x23u, 0x9bu, 0x03u, 0x30u, 0x00u, 0x23u, 0x43u, 0x30u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xdau, 0xf8u, 0x30u, 0x00u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x30u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, 0x01u, 0x00u, 0x40u, 0x00u, 0xf8u, 0xb5u, 0x1du, 0x00u, 0x00u, 0x23u, 0x16u, 0x00u, 0x0fu, 0x00u, 0x10u, 0x22u, 0x19u, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xc0u, 0xf8u, 0xe0u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x11u, 0x00u, 0x3bu, 0x43u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb8u, 0xf8u, 0x90u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x33u, 0x43u, @@ -1179,7 +1179,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5cu, 0xfdu, 0x33u, 0x68u, 0x2cu, 0x22u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x0eu, 0x4bu, 0xa8u, 0xe7u, 0x0eu, 0x4bu, 0x25u, 0x22u, 0xeau, 0xe7u, 0xe0u, 0x21u, 0x20u, 0x00u, 0x89u, 0x01u, 0xffu, 0xf7u, 0x79u, 0xfdu, 0x00u, 0x23u, 0x11u, 0x22u, 0x19u, 0x00u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, 0x09u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, 0x0au, 0xe0u, 0x00u, 0x00u, 0xdfu, 0xd0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x06u, 0x00u, 0x0fu, 0x00u, 0x02u, 0x93u, 0x0au, 0x9du, 0x0bu, 0x98u, 0x06u, 0x2au, 0x37u, 0xd8u, 0x21u, 0x4bu, 0x91u, 0x00u, 0xc9u, 0x58u, @@ -1191,7 +1191,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x12u, 0xd1u, 0x00u, 0x9au, 0xa3u, 0xb2u, 0xaau, 0x18u, 0x02u, 0x99u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb5u, 0xfcu, 0x00u, 0x28u, 0x09u, 0xd1u, 0x38u, 0x70u, 0x07u, 0xe0u, 0x00u, 0x24u, 0x23u, 0x00u, 0x21u, 0x00u, 0xcau, 0xe7u, 0x01u, 0x30u, 0x42u, 0x78u, 0xffu, 0x2au, 0xe0u, 0xd0u, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, - 0x04u, 0x79u, 0x00u, 0x10u, 0x27u, 0x79u, 0x00u, 0x10u, 0x20u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, + 0x2cu, 0x79u, 0x00u, 0x10u, 0x4fu, 0x79u, 0x00u, 0x10u, 0x48u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, 0x09u, 0x93u, 0x8bu, 0x68u, 0x04u, 0x00u, 0x05u, 0x93u, 0xcbu, 0x68u, 0x08u, 0x92u, 0x06u, 0x93u, 0x0bu, 0x68u, 0x4fu, 0x68u, 0x07u, 0x93u, 0x0bu, 0x69u, 0x8du, 0x69u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x93u, 0xb3u, 0x4bu, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1241,7 +1241,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x06u, 0x60u, 0x00u, 0x00u, 0x05u, 0x50u, 0x00u, 0x00u, 0x07u, 0x70u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x09u, 0xa0u, 0x00u, 0x00u, 0x0au, 0xc0u, 0x00u, 0x00u, 0x0bu, 0x50u, 0x00u, 0x00u, 0x07u, 0xb0u, 0x00u, 0x00u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, 0x87u, 0xb0u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x00u, 0x04u, 0x93u, 0x8bu, 0x69u, 0x0fu, 0x68u, 0x05u, 0x93u, 0x34u, 0x4bu, 0x4du, 0x68u, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x3du, 0xffu, 0x31u, 0x00u, 0x82u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfbu, @@ -1262,7 +1262,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x4cu, 0x21u, 0xffu, 0xf7u, 0x36u, 0xf8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, - 0x1au, 0x00u, 0x01u, 0xf0u, 0xfbu, 0xffu, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, + 0x1au, 0x00u, 0x02u, 0xf0u, 0x0du, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, 0x8bu, 0x61u, 0x3cu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x2du, 0x33u, 0x40u, 0x32u, 0xffu, 0x33u, 0x0au, 0x61u, 0x08u, 0x60u, 0x48u, 0x60u, 0xcbu, 0x61u, 0x00u, 0xbdu, 0x60u, 0x33u, 0x8bu, 0x61u, 0x01u, 0x23u, 0x0bu, 0x60u, 0x4bu, 0x60u, 0x32u, 0x4bu, 0x40u, 0x32u, @@ -1278,8 +1278,8 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x24u, 0x3bu, 0xdcu, 0xe7u, 0xc0u, 0x33u, 0x8bu, 0x61u, 0x05u, 0x23u, 0x0bu, 0x60u, 0x03u, 0x3bu, 0x4bu, 0x60u, 0x0cu, 0x4bu, 0x80u, 0x32u, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x20u, 0x3bu, 0xccu, 0xe7u, 0x08u, 0x48u, - 0x96u, 0xe7u, 0xc0u, 0x46u, 0xb0u, 0x79u, 0x00u, 0x10u, 0xc4u, 0x79u, 0x00u, 0x10u, 0xe4u, 0x79u, 0x00u, 0x10u, - 0x04u, 0x7au, 0x00u, 0x10u, 0x44u, 0x7au, 0x00u, 0x10u, 0x84u, 0x7au, 0x00u, 0x10u, 0xc4u, 0x7au, 0x00u, 0x10u, + 0x96u, 0xe7u, 0xc0u, 0x46u, 0xd8u, 0x79u, 0x00u, 0x10u, 0xecu, 0x79u, 0x00u, 0x10u, 0x0cu, 0x7au, 0x00u, 0x10u, + 0x2cu, 0x7au, 0x00u, 0x10u, 0x6cu, 0x7au, 0x00u, 0x10u, 0xacu, 0x7au, 0x00u, 0x10u, 0xecu, 0x7au, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0xa0u, 0xffu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x07u, 0x00u, @@ -1309,7 +1309,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x20u, 0x70u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x8fu, 0xb0u, 0x01u, 0x93u, 0x14u, 0xabu, 0x1fu, 0x78u, 0x19u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x00u, 0x91u, 0x16u, 0x00u, 0x1du, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1du, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, - 0x02u, 0xf0u, 0x6du, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, + 0x02u, 0xf0u, 0x7fu, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0cu, 0xffu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x00u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x18u, 0xffu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x00u, 0x28u, 0x03u, 0xd1u, 0x02u, 0xa9u, @@ -1335,7 +1335,7 @@ const uint8_t cy_m0p_image[] = { 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0xceu, 0x21u, 0x04u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x29u, 0x43u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, - 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xb1u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, + 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xc3u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, 0x57u, 0x00u, 0x40u, 0x33u, 0x0bu, 0x61u, 0x69u, 0x23u, 0x4bu, 0x60u, 0x2fu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x08u, 0x60u, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x00u, 0xbdu, 0x40u, 0x33u, 0x0bu, 0x61u, 0x02u, 0x23u, 0x0bu, 0x60u, 0x68u, 0x33u, 0x4bu, 0x60u, 0x28u, 0x4bu, 0xcbu, 0x62u, 0x40u, 0x23u, @@ -1348,9 +1348,9 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x23u, 0x0bu, 0x60u, 0x66u, 0x33u, 0x4bu, 0x60u, 0x10u, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x20u, 0x3bu, 0xd4u, 0xe7u, 0x80u, 0x33u, 0x0bu, 0x61u, 0x06u, 0x23u, 0x0bu, 0x60u, 0x65u, 0x33u, 0x4bu, 0x60u, 0x0au, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, - 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x04u, 0x7bu, 0x00u, 0x10u, 0x38u, 0x7bu, 0x00u, 0x10u, - 0x18u, 0x7bu, 0x00u, 0x10u, 0x98u, 0x7bu, 0x00u, 0x10u, 0x58u, 0x7bu, 0x00u, 0x10u, 0x18u, 0x7cu, 0x00u, 0x10u, - 0xd8u, 0x7bu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, + 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x2cu, 0x7bu, 0x00u, 0x10u, 0x60u, 0x7bu, 0x00u, 0x10u, + 0x40u, 0x7bu, 0x00u, 0x10u, 0xc0u, 0x7bu, 0x00u, 0x10u, 0x80u, 0x7bu, 0x00u, 0x10u, 0x40u, 0x7cu, 0x00u, 0x10u, + 0x00u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0x40u, 0xfeu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x03u, 0x92u, 0x01u, 0x93u, 0x00u, 0xd1u, 0x95u, 0xe0u, @@ -1397,7 +1397,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0xc0u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xfdu, 0x00u, 0x20u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xbfu, 0xb0u, 0x01u, 0x93u, 0x44u, 0xabu, 0x1fu, 0x78u, 0x0du, 0x00u, 0x16u, 0x00u, 0x00u, 0x21u, 0xc0u, 0x22u, 0x0eu, 0xa8u, 0x01u, 0xf0u, - 0xaeu, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xa9u, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, + 0xc0u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xbbu, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x02u, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x2au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x86u, 0xfeu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1422,15 +1422,15 @@ const uint8_t cy_m0p_image[] = { 0x1bu, 0x68u, 0x00u, 0x68u, 0x80u, 0x00u, 0x80u, 0x0cu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xfeu, 0xf7u, 0x47u, 0xfbu, 0x10u, 0xbdu, 0xfeu, 0xf7u, 0x16u, 0xfcu, 0xfbu, 0xe7u, 0xc0u, 0x46u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, 0x12u, 0x68u, 0x89u, 0x06u, 0x29u, 0x32u, 0x12u, 0x78u, 0x1bu, 0x0du, 0x94u, 0x42u, 0xa4u, 0x41u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa5u, 0x40u, 0x0bu, 0x43u, 0x2bu, 0x43u, 0x80u, 0x22u, 0x00u, 0x21u, 0xfeu, 0xf7u, 0x6cu, 0xf8u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, + 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xfeu, 0xf7u, 0x21u, 0xfbu, 0x10u, 0xbdu, - 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, + 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x93u, 0x0eu, 0x00u, 0x01u, 0x92u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x1bu, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2du, 0xd8u, 0x19u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xffu, 0x06u, 0x00u, 0x00u, 0x9au, 0x01u, 0x00u, @@ -1438,14 +1438,14 @@ const uint8_t cy_m0p_image[] = { 0x01u, 0x9au, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, - 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x03u, 0x93u, 0x04u, 0x00u, 0x01u, 0x91u, 0x02u, 0x92u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x16u, 0x4eu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x23u, 0xd8u, 0x14u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x02u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, 0x03u, 0x9bu, 0x02u, 0x00u, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xffu, - 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xbbu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x03u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, @@ -1462,23 +1462,23 @@ const uint8_t cy_m0p_image[] = { 0x18u, 0x68u, 0x14u, 0x68u, 0x43u, 0x6au, 0x22u, 0x6cu, 0x6du, 0x03u, 0x9au, 0x18u, 0x11u, 0x68u, 0x29u, 0x40u, 0x10u, 0xd0u, 0x11u, 0x60u, 0x22u, 0x6cu, 0x9bu, 0x18u, 0x1bu, 0x68u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x53u, 0x1cu, 0xd9u, 0x7fu, 0x00u, 0x29u, 0x07u, 0xd1u, 0x41u, 0x6au, 0x08u, 0x6au, 0x49u, 0x6au, 0x50u, 0x62u, 0x91u, 0x62u, - 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, 0x0du, 0x00u, 0x0bu, 0x60u, 0x43u, 0x68u, 0x4bu, 0x60u, 0x83u, 0x69u, 0x8bu, 0x60u, 0xc3u, 0x69u, 0xcbu, 0x60u, 0x4bu, 0x1cu, 0xdau, 0x77u, 0x03u, 0x8cu, 0x0bu, 0x82u, 0x03u, 0x8du, 0x0bu, 0x83u, 0xfdu, 0xf7u, 0xceu, 0xffu, - 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x5cu, 0xfeu, + 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x6eu, 0xfeu, 0x20u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x1au, 0x4au, 0x13u, 0x60u, 0x1au, 0x4eu, 0x63u, 0x68u, 0x32u, 0x68u, 0x80u, 0x33u, 0x12u, 0x6au, 0x5bu, 0x01u, 0x9bu, 0x18u, 0x80u, 0x22u, 0x21u, 0x68u, 0x52u, 0x02u, 0x8au, 0x40u, 0xe1u, 0x69u, 0x9au, 0x60u, - 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x3du, 0xfeu, 0x28u, 0x23u, + 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x4fu, 0xfeu, 0x28u, 0x23u, 0xe0u, 0x5eu, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x28u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x08u, 0x4au, 0x13u, 0x60u, 0x0au, 0x4au, 0x33u, 0x68u, 0x12u, 0x68u, 0x5bu, 0x6au, 0x92u, 0x6cu, 0x00u, 0x20u, 0x9bu, 0x18u, 0xf8u, 0x22u, 0x52u, 0x03u, 0x1au, 0x60u, 0x06u, 0x4bu, 0x1du, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe1u, 0x5eu, 0x00u, 0x10u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, 0x1fu, 0x2au, 0x04u, 0xd8u, 0x05u, 0x4au, 0x1au, 0x60u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0xbdu, 0x04u, 0x4au, 0xf9u, 0xe7u, 0xc0u, 0x46u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xd8u, 0x03u, 0x00u, 0x08u, 0x58u, 0x7cu, 0x00u, 0x10u, 0xb0u, 0x7cu, 0x00u, 0x10u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xd8u, 0x03u, 0x00u, 0x08u, 0x80u, 0x7cu, 0x00u, 0x10u, 0xd8u, 0x7cu, 0x00u, 0x10u, 0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, 0xb2u, 0x4bu, 0xb3u, 0x4du, 0x63u, 0x60u, 0x2bu, 0x68u, 0x5fu, 0x6au, 0x23u, 0x78u, 0x01u, 0x2bu, 0x18u, 0xd1u, 0x38u, 0x00u, 0xfeu, 0xf7u, 0x21u, 0xf8u, 0x60u, 0x60u, 0x00u, 0x23u, 0xabu, 0x4au, 0xe1u, 0x69u, 0x13u, 0x60u, 0x2bu, 0x68u, 0x1au, 0x00u, @@ -1524,7 +1524,7 @@ const uint8_t cy_m0p_image[] = { 0x40u, 0x6au, 0x52u, 0x69u, 0xb0u, 0x47u, 0x99u, 0xe7u, 0x96u, 0x69u, 0xedu, 0xe7u, 0xd6u, 0x69u, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xedu, 0xe6u, 0xa1u, 0x6au, 0x03u, 0x91u, 0x8bu, 0x6au, 0x02u, 0x93u, 0x4bu, 0x6au, 0x01u, 0x93u, 0x0bu, 0x6au, 0x00u, 0x93u, 0xcbu, 0x69u, 0x8au, 0x69u, 0x40u, 0x6au, 0x49u, 0x69u, 0xb0u, 0x47u, - 0x84u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x84u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0xd8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xc9u, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x00u, 0x93u, 0x8bu, 0x68u, 0x4au, 0x68u, 0x40u, 0x6au, 0x09u, 0x68u, 0xb0u, 0x47u, 0x65u, 0xe7u, @@ -1549,10 +1549,10 @@ const uint8_t cy_m0p_image[] = { 0x29u, 0x6au, 0x80u, 0x33u, 0x5bu, 0x01u, 0xcbu, 0x18u, 0xdeu, 0x68u, 0x82u, 0x40u, 0x36u, 0x0cu, 0xb2u, 0x42u, 0x11u, 0xd1u, 0x12u, 0x04u, 0x1au, 0x60u, 0xacu, 0x35u, 0x1bu, 0x68u, 0x2bu, 0x88u, 0x58u, 0x43u, 0x40u, 0x18u, 0x07u, 0x49u, 0x00u, 0xf0u, 0xb5u, 0xf8u, 0x00u, 0x28u, 0x05u, 0xd1u, 0x23u, 0x68u, 0x9bu, 0x68u, 0x00u, 0x2bu, - 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xdcu, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, - 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xdcu, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u, @@ -1566,26 +1566,26 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au, - 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, - 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0xf8u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, - 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, + 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, - 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xb4u, 0xfau, + 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xc6u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, - 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, @@ -1600,20 +1600,20 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, - 0x98u, 0x47u, 0xf6u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, + 0x98u, 0x47u, 0xf6u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xf8u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, - 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x2bu, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, + 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x3du, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, - 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, + 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xf9u, 0xf7u, 0xc7u, 0xfeu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, @@ -1626,10 +1626,19 @@ const uint8_t cy_m0p_image[] = { 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, - 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, - 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, - 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0x00u, 0x00u, 0x26u, 0x40u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, + 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, + 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x04u, 0x00u, 0x08u, + 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, + 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, + 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, + 0xe7u, 0xffu, 0x02u, 0x28u, 0x1cu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x14u, 0xd0u, 0x01u, 0x28u, 0x14u, 0xd0u, + 0x00u, 0x20u, 0x11u, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x14u, 0xd0u, 0x14u, 0x23u, 0xffu, 0x33u, + 0x98u, 0x42u, 0x18u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0xf2u, 0xd1u, 0x0cu, 0x4au, 0x0cu, 0x4bu, 0xd0u, 0x58u, + 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, 0x18u, 0x68u, 0xfbu, 0xe7u, + 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, 0x18u, 0x40u, 0xf3u, 0xd0u, + 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x04u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, + 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, 0x81u, 0x80u, 0x19u, 0x00u, 0x21u, 0x40u, 0x81u, 0x72u, 0x19u, 0x09u, 0x21u, 0x40u, 0xc1u, 0x72u, 0xd9u, 0x02u, @@ -1639,463 +1648,457 @@ const uint8_t cy_m0p_image[] = { 0x3bu, 0x33u, 0x1bu, 0x78u, 0x93u, 0x42u, 0x16u, 0xd9u, 0x7fu, 0x22u, 0x1fu, 0x24u, 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, - 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xe0u, 0x22u, 0x01u, 0x21u, 0x4du, 0x4bu, 0x80u, 0x00u, - 0xc0u, 0x18u, 0x92u, 0x00u, 0x83u, 0x58u, 0xf0u, 0xb5u, 0x9bu, 0x06u, 0x9bu, 0x0fu, 0x99u, 0x40u, 0x0fu, 0x23u, - 0x84u, 0x58u, 0x89u, 0xb0u, 0x1cu, 0x40u, 0x20u, 0x00u, 0x01u, 0x91u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x03u, 0x28u, - 0x54u, 0xd0u, 0x08u, 0xd8u, 0x01u, 0x28u, 0x13u, 0xd0u, 0x62u, 0xd9u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x42u, 0x4bu, - 0x02u, 0x28u, 0x0bu, 0xd1u, 0x0du, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x50u, 0xd0u, 0x14u, 0x23u, - 0xffu, 0x33u, 0x98u, 0x42u, 0x51u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0x41u, 0xd0u, 0x00u, 0x26u, 0x01u, 0xe0u, - 0x3au, 0x4bu, 0x1eu, 0x68u, 0x00u, 0x2cu, 0x4du, 0xd1u, 0x03u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xddu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0xb0u, 0x23u, 0x31u, 0x4au, 0xdbu, 0x00u, + 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0xffu, 0xf7u, + 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x34u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, + 0x00u, 0xf0u, 0xcfu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, 0x25u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, - 0x03u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, 0x16u, 0xd0u, 0x00u, 0x23u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0xa5u, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, 0x3au, 0x00u, 0x30u, 0x00u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0x9du, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, 0x63u, 0x08u, 0x80u, 0x18u, - 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 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0x18u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x74u, 0x00u, + 0x02u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x05u, 0x03u, 0x60u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x06u, 0x04u, 0x60u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, + 0xbcu, 0x05u, 0x00u, 0x08u, 0x85u, 0x6bu, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0xecu, 0xf0u, 0xffu, 0x7fu, + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x00u, + 0x74u, 0x7eu, 0x00u, 0x10u, 0x80u, 0x00u, 0x00u, 0x08u, 0xf8u, 0x02u, 0x00u, 0x00u, 0xb0u, 0x03u, 0x00u, 0x08u, + 0x5cu, 0x02u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x09u, 0x3du, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, + 0x00u, 0x09u, 0x3du, 0x00u, 0x00u, 0x00u, 0xd0u, 0x07u, 0xa0u, 0x0fu, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, + 0xa9u, 0x00u, 0x00u, 0x10u, 0x81u, 0x00u, 0x00u, 0x10u, 0x80u, 0xb2u, 0x30u, 0xb5u, 0xc0u, 0x00u, 0x20u, 0xd0u, + 0x10u, 0x4bu, 0x07u, 0x22u, 0x1cu, 0x68u, 0x23u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x5au, 0x43u, 0x23u, 0x6au, + 0xd3u, 0x18u, 0x19u, 0x68u, 0x00u, 0x29u, 0xfcu, 0xdau, 0x3eu, 0x21u, 0x0bu, 0x4bu, 0x06u, 0x25u, 0x19u, 0x60u, + 0x0au, 0x4bu, 0x0bu, 0x49u, 0x19u, 0x60u, 0xa3u, 0x21u, 0x0au, 0x4bu, 0xc9u, 0x00u, 0x5du, 0x50u, 0x0au, 0x49u, + 0x58u, 0x50u, 0x58u, 0x58u, 0x20u, 0x6au, 0x12u, 0x18u, 0x00u, 0x20u, 0x50u, 0x60u, 0x5au, 0x58u, 0x00u, 0x2au, + 0xfcu, 0xdau, 0x30u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0x04u, 0x01u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, + 0x1eu, 0x1fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x43u, 0x78u, + 0xffu, 0x2bu, 0x11u, 0xd1u, 0x00u, 0xf0u, 0x2au, 0xf9u, 0x04u, 0x00u, 0x03u, 0x20u, 0x00u, 0xf0u, 0xe6u, 0xf8u, + 0xc3u, 0x68u, 0x5au, 0x68u, 0x01u, 0x23u, 0x11u, 0x68u, 0x19u, 0x43u, 0x11u, 0x60u, 0x11u, 0x68u, 0x19u, 0x42u, + 0xfcu, 0xd1u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x0au, 0xf9u, 0x10u, 0xbdu, 0xf7u, 0xb5u, 0x00u, 0x90u, 0x00u, 0x20u, + 0x01u, 0x91u, 0x00u, 0xf0u, 0xd3u, 0xf8u, 0x3fu, 0x4du, 0x06u, 0x00u, 0x2bu, 0x68u, 0x1au, 0x00u, 0x4cu, 0x33u, + 0xb0u, 0x32u, 0x14u, 0x68u, 0x1bu, 0x78u, 0x04u, 0x19u, 0x00u, 0x2bu, 0x5au, 0xd0u, 0x00u, 0xf0u, 0xe6u, 0xf8u, + 0x07u, 0x00u, 0x03u, 0x28u, 0x1bu, 0xd0u, 0x00u, 0xf0u, 0x01u, 0xf9u, 0x37u, 0x4au, 0x37u, 0x4bu, 0x05u, 0x00u, + 0xd3u, 0x58u, 0x00u, 0x2bu, 0x3eu, 0xdau, 0x36u, 0x4au, 0x01u, 0x21u, 0x30u, 0x00u, 0x00u, 0xf0u, 0xbeu, 0xf8u, + 0x00u, 0x28u, 0x37u, 0xd1u, 0x01u, 0x98u, 0xffu, 0xf7u, 0x8fu, 0xffu, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x3eu, 0xd0u, + 0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, 0xe1u, 0xf8u, 0x04u, 0x00u, 0x2bu, 0xe0u, 0x06u, 0x20u, + 0x00u, 0xf0u, 0xa4u, 0xf8u, 0x2bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x02u, 0xdau, 0x28u, 0x4cu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x00u, 0x20u, 0x00u, 0xf0u, 0xbfu, 0xf8u, 0x26u, 0x4bu, + 0x98u, 0x42u, 0xf6u, 0xd0u, 0x00u, 0x23u, 0x25u, 0x4au, 0x19u, 0x00u, 0x12u, 0x68u, 0x01u, 0x20u, 0x00u, 0xf0u, + 0x9du, 0xf8u, 0x00u, 0x25u, 0xa8u, 0x42u, 0xecu, 0xd1u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xafu, 0xf8u, 0x1eu, 0x4au, + 0x1fu, 0x4bu, 0x90u, 0x42u, 0x03u, 0xd0u, 0x9du, 0x42u, 0xe3u, 0xd0u, 0x01u, 0x35u, 0xf4u, 0xe7u, 0x9du, 0x42u, + 0xb9u, 0xd1u, 0xdeu, 0xe7u, 0x17u, 0x4cu, 0x03u, 0x2fu, 0x05u, 0xd1u, 0x01u, 0x21u, 0x00u, 0x20u, 0x00u, 0xf0u, + 0x8du, 0xf8u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xa0u, 0xf8u, 0xd2u, 0xe7u, 0x15u, 0x4cu, + 0xf1u, 0xe7u, 0x00u, 0xf0u, 0xabu, 0xf8u, 0x0eu, 0x4au, 0x05u, 0x00u, 0x01u, 0x21u, 0x30u, 0x00u, 0x00u, 0xf0u, + 0x6du, 0xf8u, 0x00u, 0x28u, 0x09u, 0xd1u, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x08u, 0xd0u, 0x23u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xdbu, 0x00u, 0xf0u, 0x93u, 0xf8u, 0x04u, 0x00u, 0xe5u, 0xe7u, 0x06u, 0x4cu, 0xe3u, 0xe7u, 0x09u, 0x4cu, + 0xe1u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, + 0xe4u, 0x03u, 0x00u, 0x08u, 0x05u, 0x00u, 0x52u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u, 0xf4u, 0x03u, 0x00u, 0x08u, + 0xf0u, 0x49u, 0x02u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, 0x18u, 0x4bu, 0xf7u, 0xb5u, 0x1bu, 0x68u, 0x18u, 0x4au, + 0x5cu, 0x68u, 0x04u, 0x23u, 0x11u, 0x69u, 0x0bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x28u, 0x24u, 0xd0u, 0x30u, 0xbfu, + 0x23u, 0x00u, 0xfcu, 0x33u, 0x1bu, 0x69u, 0x00u, 0x2bu, 0x1du, 0xd1u, 0xa3u, 0x20u, 0x11u, 0x4bu, 0x12u, 0x49u, + 0x12u, 0x4au, 0xc0u, 0x00u, 0x0fu, 0x68u, 0x1eu, 0x58u, 0x15u, 0x68u, 0x01u, 0x95u, 0x10u, 0x4du, 0x0du, 0x60u, + 0x06u, 0x25u, 0x1du, 0x50u, 0x3eu, 0x20u, 0x10u, 0x60u, 0x0eu, 0x48u, 0x3eu, 0x35u, 0x1du, 0x50u, 0x1du, 0x58u, + 0x00u, 0x2du, 0xfcu, 0xdau, 0x0cu, 0x48u, 0xfcu, 0x34u, 0x20u, 0x61u, 0x0fu, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, + 0x5eu, 0x50u, 0x01u, 0x9bu, 0x13u, 0x60u, 0xf7u, 0xbdu, 0x20u, 0xbfu, 0xd9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u, + 0x1eu, 0x1fu, 0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u, 0xaau, 0xaau, 0xaau, 0xaau, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x41u, 0x5fu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x69u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x75u, 0x61u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x31u, 0x63u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xbdu, 0x6cu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xa5u, 0x63u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xe3u, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x05u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xdbu, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A512K) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c index 7d326e39cc..e1204782e9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c @@ -41,21 +41,21 @@ const uint8_t cy_m0p_image[] = { 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xc8u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xf0u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xfcu, 0x03u, 0x00u, 0x08u, 0xc8u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xfcu, 0x03u, 0x00u, 0x08u, 0xf0u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0xb9u, 0xfeu, 0x00u, 0xf0u, 0x63u, 0xfeu, 0xfeu, 0xe7u, - 0xd4u, 0x14u, 0x00u, 0x10u, 0xecu, 0x14u, 0x00u, 0x10u, 0xf8u, 0x03u, 0x00u, 0x08u, 0x10u, 0x06u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0xcfu, 0xfeu, 0x00u, 0xf0u, 0x79u, 0xfeu, 0xfeu, 0xe7u, + 0xfcu, 0x14u, 0x00u, 0x10u, 0x14u, 0x15u, 0x00u, 0x10u, 0xf8u, 0x03u, 0x00u, 0x08u, 0x14u, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x00u, 0xf0u, 0x55u, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0x0cu, 0x06u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, - 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, + 0x04u, 0x30u, 0x00u, 0xf0u, 0x6bu, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, + 0x10u, 0x06u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, + 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x10u, 0x06u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, @@ -69,33 +69,33 @@ const uint8_t cy_m0p_image[] = { 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, - 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x0cu, 0x06u, 0x00u, 0x08u, + 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, 0x14u, 0x04u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x0du, 0x4bu, 0x10u, 0xb5u, 0x18u, 0x60u, 0x00u, 0x28u, 0x04u, 0xd0u, 0xfeu, 0x23u, 0x5bu, 0x42u, 0x03u, 0x80u, 0x00u, 0x23u, 0x43u, 0x80u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0x4cu, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, 0x08u, 0xd0u, 0x4du, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x02u, 0x22u, 0x04u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xe0u, 0xf8u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x24u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x49u, 0x01u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, + 0x24u, 0x04u, 0x00u, 0x08u, 0x10u, 0x06u, 0x00u, 0x08u, 0x45u, 0x01u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb8u, 0x03u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, - 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, + 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0x28u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1du, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x25u, 0x40u, 0x27u, 0x40u, 0x12u, 0x4cu, 0x1bu, 0x0cu, 0x26u, 0x68u, 0x07u, 0x60u, 0x34u, 0x6au, 0x45u, 0x60u, 0x83u, 0x60u, 0xacu, 0x36u, 0x36u, 0x88u, 0x77u, 0x43u, 0x3fu, 0x19u, 0x07u, 0x61u, 0x2fu, 0x00u, 0x80u, 0x37u, 0x6du, 0x01u, 0x7fu, 0x01u, 0xe7u, 0x19u, 0x64u, 0x19u, 0x0au, 0x4du, 0x47u, 0x61u, 0x1fu, 0x04u, 0x3bu, 0x43u, 0x64u, 0x19u, 0x23u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, - 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x06u, 0x00u, 0x08u, + 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0xabu, 0x70u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xb5u, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xffu, - 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xc8u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, + 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xdeu, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x10u, 0x06u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, @@ -112,20 +112,20 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0xf1u, 0xfeu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, - 0x98u, 0x47u, 0xf6u, 0xe7u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, + 0x98u, 0x47u, 0xf6u, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, - 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0xfeu, 0xfeu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xfeu, + 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x14u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbbu, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, - 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, + 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x10u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, - 0x0cu, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, 0xbcu, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, + 0x10u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, 0xbcu, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xffu, 0xf7u, 0x67u, 0xfdu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, @@ -138,279 +138,282 @@ const uint8_t cy_m0p_image[] = { 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, - 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, - 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, - 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0x00u, 0x00u, 0x26u, 0x40u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, - 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, - 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, - 0x81u, 0x80u, 0x19u, 0x00u, 0x21u, 0x40u, 0x81u, 0x72u, 0x19u, 0x09u, 0x21u, 0x40u, 0xc1u, 0x72u, 0xd9u, 0x02u, - 0x9bu, 0x00u, 0x9bu, 0x0fu, 0x83u, 0x73u, 0x07u, 0x4bu, 0xc9u, 0x0cu, 0xd3u, 0x58u, 0x81u, 0x81u, 0x5au, 0x05u, - 0xdbu, 0x01u, 0x52u, 0x0fu, 0xdbu, 0x0du, 0x82u, 0x71u, 0x03u, 0x82u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u, - 0x84u, 0x05u, 0x00u, 0x00u, 0x8cu, 0x05u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x10u, 0x4bu, 0x42u, 0x1eu, 0x1bu, 0x68u, - 0x3bu, 0x33u, 0x1bu, 0x78u, 0x93u, 0x42u, 0x16u, 0xd9u, 0x7fu, 0x22u, 0x1fu, 0x24u, 0x80u, 0x30u, 0xffu, 0x30u, - 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, - 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, - 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0cu, 0x06u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xe0u, 0x22u, 0x01u, 0x21u, 0x4du, 0x4bu, 0x80u, 0x00u, - 0xc0u, 0x18u, 0x92u, 0x00u, 0x83u, 0x58u, 0xf0u, 0xb5u, 0x9bu, 0x06u, 0x9bu, 0x0fu, 0x99u, 0x40u, 0x0fu, 0x23u, - 0x84u, 0x58u, 0x89u, 0xb0u, 0x1cu, 0x40u, 0x20u, 0x00u, 0x01u, 0x91u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x03u, 0x28u, - 0x54u, 0xd0u, 0x08u, 0xd8u, 0x01u, 0x28u, 0x13u, 0xd0u, 0x62u, 0xd9u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x42u, 0x4bu, - 0x02u, 0x28u, 0x0bu, 0xd1u, 0x0du, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x50u, 0xd0u, 0x14u, 0x23u, - 0xffu, 0x33u, 0x98u, 0x42u, 0x51u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0x41u, 0xd0u, 0x00u, 0x26u, 0x01u, 0xe0u, - 0x3au, 0x4bu, 0x1eu, 0x68u, 0x00u, 0x2cu, 0x4du, 0xd1u, 0x03u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xb0u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0xb0u, 0x23u, 0x31u, 0x4au, 0xdbu, 0x00u, - 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, - 0x03u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, 0x16u, 0xd0u, 0x00u, 0x23u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0x81u, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, 0x3au, 0x00u, 0x30u, 0x00u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0x79u, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, 0x63u, 0x08u, 0x80u, 0x18u, - 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 0x4fu, 0xfcu, 0x06u, 0x00u, 0x01u, 0x9bu, 0x58u, 0x08u, - 0x80u, 0x19u, 0x19u, 0x00u, 0x00u, 0xf0u, 0xbcu, 0xfbu, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x1cu, 0x4bu, 0xc0u, 0xe7u, - 0x18u, 0x4au, 0x1cu, 0x4bu, 0xd3u, 0x58u, 0x00u, 0x2bu, 0xb8u, 0xdau, 0x80u, 0x26u, 0x36u, 0x02u, 0xb9u, 0xe7u, - 0x19u, 0x4bu, 0x1bu, 0x69u, 0x5bu, 0x07u, 0xf8u, 0xd4u, 0xb0u, 0xe7u, 0x12u, 0x4au, 0x17u, 0x4bu, 0xf1u, 0xe7u, - 0x17u, 0x4eu, 0xafu, 0xe7u, 0x17u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, 0xddu, 0xd3u, - 0x03u, 0xadu, 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x5cu, 0xfdu, 0x20u, 0x00u, 0x29u, 0x00u, - 0x80u, 0x34u, 0xffu, 0xf7u, 0x49u, 0xffu, 0xffu, 0x34u, 0x06u, 0x4bu, 0xa4u, 0x00u, 0xe3u, 0x58u, 0x00u, 0x24u, - 0xa3u, 0x42u, 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x2fu, 0x78u, 0x68u, 0x78u, - 0xaau, 0x78u, 0xaau, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, 0x30u, 0x04u, 0x00u, 0x08u, 0x34u, 0x04u, 0x00u, 0x08u, - 0xc4u, 0x00u, 0x00u, 0x08u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, - 0x00u, 0x12u, 0x7au, 0x00u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x14u, 0x4bu, 0x30u, 0xb5u, 0x1au, 0x68u, 0x07u, 0x24u, - 0x13u, 0x00u, 0x28u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x15u, 0xd8u, 0x83u, 0x08u, 0x1du, 0x00u, 0xa5u, 0x43u, - 0x2cu, 0x1eu, 0x0fu, 0xd1u, 0x03u, 0x34u, 0x20u, 0x40u, 0xa0u, 0x40u, 0x81u, 0x40u, 0x12u, 0x68u, 0x9bu, 0x00u, - 0x20u, 0x32u, 0xd3u, 0x18u, 0x0au, 0x00u, 0xffu, 0x21u, 0x81u, 0x40u, 0x1cu, 0x68u, 0x62u, 0x40u, 0x11u, 0x40u, - 0x61u, 0x40u, 0x19u, 0x60u, 0x30u, 0xbdu, 0x80u, 0x23u, 0x20u, 0x40u, 0x1bu, 0x06u, 0x18u, 0x43u, 0x80u, 0x23u, - 0x9bu, 0x01u, 0x12u, 0x68u, 0xc9u, 0x18u, 0x89u, 0x00u, 0x88u, 0x50u, 0xf3u, 0xe7u, 0x0cu, 0x06u, 0x00u, 0x08u, - 0x06u, 0x4bu, 0x9au, 0x68u, 0x03u, 0x00u, 0x06u, 0x48u, 0x10u, 0x33u, 0x9bu, 0x00u, 0x82u, 0x42u, 0x02u, 0xd1u, - 0x98u, 0x58u, 0x99u, 0x50u, 0x70u, 0x47u, 0x03u, 0x4au, 0xd0u, 0x58u, 0xfbu, 0xe7u, 0x00u, 0xedu, 0x00u, 0xe0u, - 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x10u, 0xf8u, 0xb5u, 0x06u, 0x00u, 0x0du, 0x00u, 0x00u, 0x28u, - 0x3au, 0xd0u, 0x00u, 0x23u, 0xc0u, 0x5eu, 0x00u, 0x28u, 0x28u, 0xdbu, 0xb1u, 0x78u, 0xffu, 0xf7u, 0xb4u, 0xffu, - 0x00u, 0x24u, 0xffu, 0x22u, 0x03u, 0x27u, 0x94u, 0x46u, 0x00u, 0x23u, 0xf0u, 0x5eu, 0x71u, 0x68u, 0x83u, 0xb2u, - 0x1fu, 0x40u, 0xffu, 0x00u, 0x66u, 0x46u, 0xbau, 0x40u, 0x89u, 0x01u, 0x31u, 0x40u, 0xd2u, 0x43u, 0xb9u, 0x40u, - 0x00u, 0x28u, 0x15u, 0xdbu, 0x11u, 0x4eu, 0x83u, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u, 0xc0u, 0x26u, 0xb6u, 0x00u, - 0x9fu, 0x59u, 0x3au, 0x40u, 0x11u, 0x43u, 0x99u, 0x51u, 0x0du, 0x4bu, 0x9au, 0x68u, 0x0du, 0x4bu, 0x9au, 0x42u, - 0x02u, 0xd1u, 0x29u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu, 0x20u, 0x00u, 0xf8u, 0xbdu, 0x0au, 0x4cu, 0xd8u, 0xe7u, - 0x0fu, 0x26u, 0x33u, 0x40u, 0x08u, 0x3bu, 0x06u, 0x4eu, 0x9bu, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u, 0xdeu, 0x69u, - 0x32u, 0x40u, 0x11u, 0x43u, 0xd9u, 0x61u, 0xe7u, 0xe7u, 0x03u, 0x4cu, 0xedu, 0xe7u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x00u, 0x08u, 0x01u, 0x00u, 0x56u, 0x00u, 0xfeu, 0xe7u, 0x00u, 0x00u, - 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0x79u, 0x02u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x31u, 0x03u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xb5u, 0x01u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + }; #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c index 81e1bd68aa..5ab97070c6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c @@ -37,21 +37,21 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xf0u, 0x13u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x18u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0xf0u, 0x13u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xb4u, 0x03u, 0x00u, 0x08u, 0x18u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x73u, 0xfeu, 0x00u, 0xf0u, 0x1du, 0xfeu, 0xfeu, 0xe7u, - 0xfcu, 0x13u, 0x00u, 0x10u, 0x14u, 0x14u, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0xccu, 0x05u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x85u, 0xfeu, 0x00u, 0xf0u, 0x2fu, 0xfeu, 0xfeu, 0xe7u, + 0x24u, 0x14u, 0x00u, 0x10u, 0x3cu, 0x14u, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x00u, 0xf0u, 0x0fu, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, - 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, + 0x04u, 0x30u, 0x00u, 0xf0u, 0x21u, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, + 0xc4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, + 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, @@ -65,27 +65,27 @@ const uint8_t cy_m0p_image[] = { 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, - 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xccu, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, + 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, - 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xb4u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, + 0x00u, 0xf0u, 0xc6u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, + 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, @@ -99,20 +99,20 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x2bu, 0x00u, 0xd0u, 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, - 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, + 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, - 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0xfau, 0xfeu, 0x29u, 0x00u, 0x20u, 0x00u, + 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x0cu, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, - 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, - 0x03u, 0x48u, 0xf3u, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, + 0x03u, 0x48u, 0xf3u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xffu, 0xf7u, 0xadu, 0xfdu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, @@ -125,10 +125,19 @@ const uint8_t cy_m0p_image[] = { 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, - 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x09u, 0x4au, 0x83u, 0x00u, - 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, - 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, + 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, + 0xefu, 0xffu, 0x00u, 0x23u, 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, + 0xe8u, 0x03u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, + 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, + 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x10u, 0xb5u, 0xffu, 0xf7u, 0xe7u, 0xffu, 0x02u, 0x28u, 0x1cu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x14u, 0xd0u, + 0x01u, 0x28u, 0x14u, 0xd0u, 0x00u, 0x20u, 0x11u, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x14u, 0xd0u, + 0x14u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x18u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0xf2u, 0xd1u, 0x0cu, 0x4au, + 0x0cu, 0x4bu, 0xd0u, 0x58u, 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, + 0x18u, 0x68u, 0xfbu, 0xe7u, 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, + 0x18u, 0x40u, 0xf3u, 0xd0u, 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0xecu, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, 0x81u, 0x80u, 0x19u, 0x00u, 0x21u, 0x40u, 0x81u, 0x72u, 0x19u, 0x09u, 0x21u, 0x40u, @@ -139,264 +148,258 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xe0u, 0x22u, 0x01u, 0x21u, - 0x4du, 0x4bu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x92u, 0x00u, 0x83u, 0x58u, 0xf0u, 0xb5u, 0x9bu, 0x06u, 0x9bu, 0x0fu, - 0x99u, 0x40u, 0x0fu, 0x23u, 0x84u, 0x58u, 0x89u, 0xb0u, 0x1cu, 0x40u, 0x20u, 0x00u, 0x01u, 0x91u, 0xffu, 0xf7u, - 0x7du, 0xffu, 0x03u, 0x28u, 0x54u, 0xd0u, 0x08u, 0xd8u, 0x01u, 0x28u, 0x13u, 0xd0u, 0x62u, 0xd9u, 0xffu, 0xf7u, - 0x67u, 0xffu, 0x42u, 0x4bu, 0x02u, 0x28u, 0x0bu, 0xd1u, 0x0du, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, - 0x50u, 0xd0u, 0x14u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x51u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0x41u, 0xd0u, - 0x00u, 0x26u, 0x01u, 0xe0u, 0x3au, 0x4bu, 0x1eu, 0x68u, 0x00u, 0x2cu, 0x4du, 0xd1u, 0x03u, 0xadu, 0x14u, 0x22u, - 0x21u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xacu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0xb0u, 0x23u, - 0x31u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, - 0x9cu, 0x41u, 0xeau, 0x79u, 0x03u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, - 0x16u, 0xd0u, 0x00u, 0x23u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x7du, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, - 0x3au, 0x00u, 0x30u, 0x00u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x75u, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, - 0x63u, 0x08u, 0x80u, 0x18u, 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 0x4bu, 0xfcu, 0x06u, 0x00u, - 0x01u, 0x9bu, 0x58u, 0x08u, 0x80u, 0x19u, 0x19u, 0x00u, 0x00u, 0xf0u, 0xb8u, 0xfbu, 0x09u, 0xb0u, 0xf0u, 0xbdu, - 0x1cu, 0x4bu, 0xc0u, 0xe7u, 0x18u, 0x4au, 0x1cu, 0x4bu, 0xd3u, 0x58u, 0x00u, 0x2bu, 0xb8u, 0xdau, 0x80u, 0x26u, - 0x36u, 0x02u, 0xb9u, 0xe7u, 0x19u, 0x4bu, 0x1bu, 0x69u, 0x5bu, 0x07u, 0xf8u, 0xd4u, 0xb0u, 0xe7u, 0x12u, 0x4au, - 0x17u, 0x4bu, 0xf1u, 0xe7u, 0x17u, 0x4eu, 0xafu, 0xe7u, 0x17u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, - 0xa3u, 0x42u, 0xddu, 0xd3u, 0x03u, 0xadu, 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x58u, 0xfdu, - 0x20u, 0x00u, 0x29u, 0x00u, 0x80u, 0x34u, 0xffu, 0xf7u, 0x49u, 0xffu, 0xffu, 0x34u, 0x06u, 0x4bu, 0xa4u, 0x00u, - 0xe3u, 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0x04u, 0x23u, + 0x11u, 0x69u, 0x0bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x28u, 0x24u, 0xd0u, 0x30u, 0xbfu, 0x23u, 0x00u, 0xfcu, 0x33u, + 0x1bu, 0x69u, 0x00u, 0x2bu, 0x1du, 0xd1u, 0xa3u, 0x20u, 0x11u, 0x4bu, 0x12u, 0x49u, 0x12u, 0x4au, 0xc0u, 0x00u, + 0x0fu, 0x68u, 0x1eu, 0x58u, 0x15u, 0x68u, 0x01u, 0x95u, 0x10u, 0x4du, 0x0du, 0x60u, 0x06u, 0x25u, 0x1du, 0x50u, + 0x3eu, 0x20u, 0x10u, 0x60u, 0x0eu, 0x48u, 0x3eu, 0x35u, 0x1du, 0x50u, 0x1du, 0x58u, 0x00u, 0x2du, 0xfcu, 0xdau, + 0x0cu, 0x48u, 0xfcu, 0x34u, 0x20u, 0x61u, 0x0fu, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, 0x5eu, 0x50u, 0x01u, 0x9bu, + 0x13u, 0x60u, 0xf7u, 0xbdu, 0x20u, 0xbfu, 0xd9u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xedu, 0x00u, 0xe0u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, + 0x1cu, 0x05u, 0x00u, 0x00u, 0xaau, 0xaau, 0xaau, 0xaau, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xdbu, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x9du, 0x02u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xa9u, 0x03u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xe3u, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xddu, 0x0eu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xd9u, 0x05u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x75u, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x65u, 0x05u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x39u, 0x02u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A2M) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c index 532d233722..de4c30d0ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c @@ -37,21 +37,21 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xf0u, 0x13u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x18u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0xf0u, 0x13u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xb4u, 0x03u, 0x00u, 0x08u, 0x18u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x73u, 0xfeu, 0x00u, 0xf0u, 0x1du, 0xfeu, 0xfeu, 0xe7u, - 0xfcu, 0x13u, 0x00u, 0x10u, 0x14u, 0x14u, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0xccu, 0x05u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x85u, 0xfeu, 0x00u, 0xf0u, 0x2fu, 0xfeu, 0xfeu, 0xe7u, + 0x24u, 0x14u, 0x00u, 0x10u, 0x3cu, 0x14u, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x00u, 0xf0u, 0x0fu, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, - 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, + 0x04u, 0x30u, 0x00u, 0xf0u, 0x21u, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, + 0xc4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, + 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, @@ -65,27 +65,27 @@ const uint8_t cy_m0p_image[] = { 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, - 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xccu, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, + 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, - 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xb4u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, + 0x00u, 0xf0u, 0xc6u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, + 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, @@ -99,20 +99,20 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x2bu, 0x00u, 0xd0u, 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, - 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, + 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, - 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0xfau, 0xfeu, 0x29u, 0x00u, 0x20u, 0x00u, + 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x0cu, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, - 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, - 0x03u, 0x48u, 0xf3u, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, + 0x03u, 0x48u, 0xf3u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xffu, 0xf7u, 0xadu, 0xfdu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, @@ -125,10 +125,19 @@ const uint8_t cy_m0p_image[] = { 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, - 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x09u, 0x4au, 0x83u, 0x00u, - 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, - 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, + 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, + 0xefu, 0xffu, 0x00u, 0x23u, 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, + 0xe8u, 0x03u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, + 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, + 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x10u, 0xb5u, 0xffu, 0xf7u, 0xe7u, 0xffu, 0x02u, 0x28u, 0x1cu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x14u, 0xd0u, + 0x01u, 0x28u, 0x14u, 0xd0u, 0x00u, 0x20u, 0x11u, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x14u, 0xd0u, + 0x14u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x18u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0xf2u, 0xd1u, 0x0cu, 0x4au, + 0x0cu, 0x4bu, 0xd0u, 0x58u, 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, + 0x18u, 0x68u, 0xfbu, 0xe7u, 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, + 0x18u, 0x40u, 0xf3u, 0xd0u, 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0xecu, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, 0x81u, 0x80u, 0x19u, 0x00u, 0x21u, 0x40u, 0x81u, 0x72u, 0x19u, 0x09u, 0x21u, 0x40u, @@ -139,264 +148,258 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xe0u, 0x22u, 0x01u, 0x21u, - 0x4du, 0x4bu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x92u, 0x00u, 0x83u, 0x58u, 0xf0u, 0xb5u, 0x9bu, 0x06u, 0x9bu, 0x0fu, - 0x99u, 0x40u, 0x0fu, 0x23u, 0x84u, 0x58u, 0x89u, 0xb0u, 0x1cu, 0x40u, 0x20u, 0x00u, 0x01u, 0x91u, 0xffu, 0xf7u, - 0x7du, 0xffu, 0x03u, 0x28u, 0x54u, 0xd0u, 0x08u, 0xd8u, 0x01u, 0x28u, 0x13u, 0xd0u, 0x62u, 0xd9u, 0xffu, 0xf7u, - 0x67u, 0xffu, 0x42u, 0x4bu, 0x02u, 0x28u, 0x0bu, 0xd1u, 0x0du, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, - 0x50u, 0xd0u, 0x14u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x51u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0x41u, 0xd0u, - 0x00u, 0x26u, 0x01u, 0xe0u, 0x3au, 0x4bu, 0x1eu, 0x68u, 0x00u, 0x2cu, 0x4du, 0xd1u, 0x03u, 0xadu, 0x14u, 0x22u, - 0x21u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0xacu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0xb0u, 0x23u, - 0x31u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, - 0x9cu, 0x41u, 0xeau, 0x79u, 0x03u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, - 0x16u, 0xd0u, 0x00u, 0x23u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x7du, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, - 0x3au, 0x00u, 0x30u, 0x00u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x75u, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, - 0x63u, 0x08u, 0x80u, 0x18u, 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 0x4bu, 0xfcu, 0x06u, 0x00u, - 0x01u, 0x9bu, 0x58u, 0x08u, 0x80u, 0x19u, 0x19u, 0x00u, 0x00u, 0xf0u, 0xb8u, 0xfbu, 0x09u, 0xb0u, 0xf0u, 0xbdu, - 0x1cu, 0x4bu, 0xc0u, 0xe7u, 0x18u, 0x4au, 0x1cu, 0x4bu, 0xd3u, 0x58u, 0x00u, 0x2bu, 0xb8u, 0xdau, 0x80u, 0x26u, - 0x36u, 0x02u, 0xb9u, 0xe7u, 0x19u, 0x4bu, 0x1bu, 0x69u, 0x5bu, 0x07u, 0xf8u, 0xd4u, 0xb0u, 0xe7u, 0x12u, 0x4au, - 0x17u, 0x4bu, 0xf1u, 0xe7u, 0x17u, 0x4eu, 0xafu, 0xe7u, 0x17u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, - 0xa3u, 0x42u, 0xddu, 0xd3u, 0x03u, 0xadu, 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x58u, 0xfdu, - 0x20u, 0x00u, 0x29u, 0x00u, 0x80u, 0x34u, 0xffu, 0xf7u, 0x49u, 0xffu, 0xffu, 0x34u, 0x06u, 0x4bu, 0xa4u, 0x00u, - 0xe3u, 0x58u, 0x00u, 0x24u, 0xa3u, 0x42u, 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, - 0x2fu, 0x78u, 0x68u, 0x78u, 0xaau, 0x78u, 0xaau, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, 0xe8u, 0x03u, 0x00u, 0x08u, - 0xecu, 0x03u, 0x00u, 0x08u, 0x44u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x27u, 0x40u, - 0x3cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x14u, 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0x00u, 0xbfu, 0xddu, 0x0eu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xd9u, 0x05u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xe3u, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x39u, 0x02u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xdbu, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A512K) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/README.md index 0df7feed0b..6f8d7eef8f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/README.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/README.md @@ -6,6 +6,11 @@ Prebuilt application images are executed on the Cortex M0+ core of the PSoC 6 du The images are provided as C arrays ready to be compiled as part of the Cortex M4 application. The Cortex M0+ application code is placed to internal flash by the Cortex M4 linker script. +Note: Each application image has a variant based on the hardware die (e.g. +psoc6_01, psoc6_02, psoc6_03, ...) it is supported on. An #ifdef at the top of +each .c file automatically controls which version is used so there is no need +to specify a particular image. + ### Images * [COMPONENT_CM0P_SLEEP](./COMPONENT_CM0P_SLEEP/README.md) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/version.xml index 39a7566b36..0f08fc2b23 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/version.xml @@ -1 +1 @@ -1.1.0.56 +1.1.1.63 From 4e6692b529a8814c0974ad2e23354b8b32c333ac Mon Sep 17 00:00:00 2001 From: Dustin Crossman Date: Mon, 2 Mar 2020 15:03:41 -0800 Subject: [PATCH 36/49] Backport #12603: Add CYSBSYSKIT_01 --- .../qspi/flash_configs/flash_configs.h | 3 +- .../interface/SclSTAInterface.cpp | 328 +++++ .../COMPONENT_SCL/interface/SclSTAInterface.h | 165 +++ .../interface/default_wifi_interface.cpp | 35 + .../COMPONENT_SCL/interface/scl_emac.cpp | 203 +++ .../COMPONENT_SCL/interface/scl_emac.h | 189 +++ features/netsocket/ppp/mbed_lib.json | 3 + .../COMPONENT_SCL/generated_mac_address.txt | 9 + .../COMPONENT_SCL/inc/scl_common.h | 211 +++ .../TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h | 120 ++ .../COMPONENT_SCL/inc/scl_types.h | 115 ++ .../COMPONENT_SCL/inc/scl_wifi_api.h | 151 ++ .../COMPONENT_SCL/src/IPC/scl_ipc.c | 293 ++++ .../src/include/scl_buffer_api.h | 113 ++ .../COMPONENT_SCL/src/scl_buffer_api.c | 82 ++ .../COMPONENT_SCL/src/scl_wifi_api.c | 160 +++ .../GeneratedSource/cycfg.c | 33 + .../GeneratedSource/cycfg.h | 47 + .../GeneratedSource/cycfg.timestamp | 26 + .../GeneratedSource/cycfg_notices.h | 32 + .../GeneratedSource/cycfg_pins.c | 177 +++ .../GeneratedSource/cycfg_pins.h | 190 +++ .../GeneratedSource/cycfg_qspi_memslot.c | 266 ++++ .../GeneratedSource/cycfg_qspi_memslot.h | 51 + .../GeneratedSource/cycfg_routing.c | 31 + .../GeneratedSource/cycfg_routing.h | 46 + .../GeneratedSource/cycfg_system.c | 28 + .../GeneratedSource/cycfg_system.h | 43 + .../GeneratedSource/qspi_config.cfg | 2 + .../cyreservedresources.list | 99 ++ .../design.cycapsense | 71 + .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 63 + .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 106 ++ .../TARGET_CYSBSYSKIT_01/PeripheralPins.c | 427 ++++++ .../TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c | 115 ++ .../TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h | 76 + .../TARGET_CYSBSYSKIT_01/cybsp_types.h | 194 +++ .../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 298 ++++ .../TOOLCHAIN_ARM/startup_psoc6_02_cm4.S | 703 +++++++++ .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld | 448 ++++++ .../TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S | 673 +++++++++ .../TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf | 274 ++++ .../TOOLCHAIN_IAR/startup_psoc6_02_cm4.S | 1263 +++++++++++++++++ .../device/COMPONENT_CM4/system_psoc6_cm4.c | 552 +++++++ .../device/system_psoc6.h | 680 +++++++++ targets/targets.json | 49 + 46 files changed, 9242 insertions(+), 1 deletion(-) create mode 100644 features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp create mode 100644 features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h create mode 100644 features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp create mode 100644 features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.cpp create mode 100644 features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/generated_mac_address.txt create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/include/scl_buffer_api.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_buffer_api.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h diff --git a/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h b/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h index 180a3d3bd7..215c75caf7 100644 --- a/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h +++ b/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h @@ -69,7 +69,8 @@ defined(TARGET_CY8CPROTO_062S2_43012) || \ defined(TARGET_CY8CPROTO_062S3_4343W) || \ defined(TARGET_CYW943012P6EVB_01) || \ - defined(TARGET_CYW9P62S1_43438EVB_01)) + defined(TARGET_CYW9P62S1_43438EVB_01) || \ + defined(TARGET_CYSBSYSKIT_01)) #include "S25FL512S_config.h" #elif defined(TARGET_CYW9P62S1_43012EVB_01) diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp new file mode 100644 index 0000000000..5a17077efb --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp @@ -0,0 +1,328 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include "SclSTAInterface.h" +#include "nsapi.h" +#include "lwipopts.h" +#include "lwip/etharp.h" +#include "lwip/ethip6.h" +#include "rtos.h" +#include "scl_emac.h" +#include "scl_ipc.h" +#include "mbed_wait_api.h" + + +/** @file + * Provides SCL interface functions to be used with WiFiInterface or NetworkInterface Objects + */ + +struct scl_tx_nw_credentials { + nsapi_security_t network_security_type; + int ssid_len; + int pass_len; + const char *network_ssid; + const char *network_passphrase; +} scl_tx_nw_credentials_t; + +network_params_t network_parameter; + +int scl_toerror(scl_result_t res) +{ + switch (res) { + case SCL_SUCCESS: + return NSAPI_ERROR_OK; + case SCL_UNSUPPORTED: + return NSAPI_ERROR_UNSUPPORTED; + case SCL_BADARG: + return NSAPI_ERROR_PARAMETER; + case SCL_INVALID_JOIN_STATUS: + return NSAPI_ERROR_NO_CONNECTION; + case SCL_BUFFER_UNAVAILABLE_PERMANENT: + case SCL_BUFFER_UNAVAILABLE_TEMPORARY: + case SCL_RX_BUFFER_ALLOC_FAIL: + case SCL_BUFFER_ALLOC_FAIL: + case SCL_MALLOC_FAILURE: + return NSAPI_ERROR_NO_MEMORY; + case SCL_ACCESS_POINT_NOT_FOUND: + case SCL_NETWORK_NOT_FOUND: + return NSAPI_ERROR_NO_SSID; + case SCL_NOT_AUTHENTICATED: + case SCL_INVALID_KEY: + case SCL_NOT_KEYED: + return NSAPI_ERROR_AUTH_FAILURE; + case SCL_PENDING: + case SCL_JOIN_IN_PROGRESS: + return NSAPI_ERROR_IN_PROGRESS; + case SCL_CONNECTION_LOST: + return NSAPI_ERROR_CONNECTION_LOST; + case SCL_TIMEOUT: + case SCL_EAPOL_KEY_PACKET_M1_TIMEOUT: + case SCL_EAPOL_KEY_PACKET_M3_TIMEOUT: + case SCL_EAPOL_KEY_PACKET_G1_TIMEOUT: + return NSAPI_ERROR_CONNECTION_TIMEOUT; + default: + return -res; + } +} + +nsapi_security_t scl_tosecurity(scl_security_t sec) +{ + switch (sec) { + case SCL_SECURITY_OPEN: + return NSAPI_SECURITY_NONE; + case SCL_SECURITY_WEP_PSK: + case SCL_SECURITY_WEP_SHARED: + return NSAPI_SECURITY_WEP; + case SCL_SECURITY_WPA_TKIP_PSK: + case SCL_SECURITY_WPA_TKIP_ENT: + return NSAPI_SECURITY_WPA; + case SCL_SECURITY_WPA2_MIXED_PSK: + return NSAPI_SECURITY_WPA_WPA2; + case SCL_SECURITY_WPA2_AES_PSK: + case SCL_SECURITY_WPA2_AES_ENT: + case SCL_SECURITY_WPA2_FBT_PSK: + case SCL_SECURITY_WPA2_FBT_ENT: + return NSAPI_SECURITY_WPA2; + default: + return NSAPI_SECURITY_UNKNOWN; + } +} + +scl_security_t scl_fromsecurity(nsapi_security_t sec) +{ + switch (sec) { + case NSAPI_SECURITY_NONE: + return SCL_SECURITY_OPEN; + case NSAPI_SECURITY_WEP: + return SCL_SECURITY_WEP_PSK; + case NSAPI_SECURITY_WPA: + return SCL_SECURITY_WPA_MIXED_PSK; + case NSAPI_SECURITY_WPA2: + return SCL_SECURITY_WPA2_AES_PSK; + case NSAPI_SECURITY_WPA_WPA2: + return SCL_SECURITY_WPA2_MIXED_PSK; + default: + return SCL_SECURITY_UNKNOWN; + } +} + +SclSTAInterface::SclSTAInterface(SCL_EMAC &emac, OnboardNetworkStack &stack) + : EMACInterface(emac, stack), + _ssid("\0"), + _pass("\0"), + _security(NSAPI_SECURITY_NONE), + _scl_emac(emac) +{ +} + +nsapi_error_t SclSTAInterface::connect(const char *ssid, const char *pass, nsapi_security_t security, uint8_t channel) +{ + int err = set_channel(channel); + if (err) { + return err; + } + + err = set_credentials(ssid, pass, security); + if (err) { + return err; + } + + return connect(); +} + +nsapi_error_t SclSTAInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) +{ + if ((ssid == NULL) || + (strlen(ssid) == 0) || + (pass == NULL && (security != NSAPI_SECURITY_NONE)) || + (strlen(pass) == 0 && (security != NSAPI_SECURITY_NONE)) || + (strlen(pass) > 63 && (security == NSAPI_SECURITY_WPA2 || security == NSAPI_SECURITY_WPA || security == NSAPI_SECURITY_WPA_WPA2)) + ) { + return NSAPI_ERROR_PARAMETER; + } + + memset(_ssid, 0, sizeof(_ssid)); + strncpy(_ssid, ssid, sizeof(_ssid)); + + memset(_pass, 0, sizeof(_pass)); + strncpy(_pass, pass, sizeof(_pass)); + + _security = security; + + return NSAPI_ERROR_OK; +} + +nsapi_error_t SclSTAInterface::connect() +{ + + uint32_t delay_timeout = 0; + scl_result_t ret_val; + nsapi_error_t interface_status; + uint32_t connection_status = 0; + + scl_tx_nw_credentials_t.network_ssid = _ssid; + if (strlen(_ssid) < MAX_SSID_LENGTH) { + scl_tx_nw_credentials_t.ssid_len = strlen(_ssid); + } + scl_tx_nw_credentials_t.network_passphrase = _pass; + if (strlen(_pass) < MAX_PASSWORD_LENGTH) { + scl_tx_nw_credentials_t.pass_len = strlen(_pass); + } + scl_tx_nw_credentials_t.network_security_type = _security; + + ret_val = scl_send_data(SCL_TX_CONNECT, (char *)&scl_tx_nw_credentials_t, TIMER_DEFAULT_VALUE); + + if (ret_val == SCL_SUCCESS) { + SCL_LOG(("wifi provisioning in progress")); + } + + network_parameter.connection_status = NSAPI_STATUS_DISCONNECTED; + + + //Get the network parameter from NP + while ((network_parameter.connection_status != NSAPI_STATUS_GLOBAL_UP) && delay_timeout < NW_CONNECT_TIMEOUT) { + ret_val = scl_get_nw_parameters(&network_parameter); + wait_us(NW_DELAY_TIME_US); + delay_timeout++; + } + + if (delay_timeout >= NW_CONNECT_TIMEOUT || ret_val != SCL_SUCCESS) { + return NSAPI_ERROR_NO_CONNECTION; + } + + if (!_scl_emac.powered_up) { + _scl_emac.power_up(); + } + + if (!_interface) { + nsapi_error_t err = _stack.add_ethernet_interface(_emac, true, &_interface); + if (err != NSAPI_ERROR_OK) { + _interface = NULL; + return err; + } + _interface->attach(_connection_status_cb); + } + + if (!scl_wifi_is_ready_to_transceive()) { + scl_emac_wifi_link_state_changed(true); + } + + interface_status = _interface->bringup(false, + network_parameter.ip_address, + network_parameter.netmask, + network_parameter.gateway, + DEFAULT_STACK); + + scl_send_data(SCL_TX_CONNECTION_STATUS, (char *)&connection_status, TIMER_DEFAULT_VALUE); + + return interface_status; +} + +void SclSTAInterface::wifi_on() +{ + if (!_scl_emac.powered_up) { + _scl_emac.power_up(); + } +} + +nsapi_error_t SclSTAInterface::disconnect() +{ + scl_result_t ret_val; + nsapi_error_t disconnect_status; + ret_val = scl_send_data(SCL_TX_DISCONNECT, (char *)&disconnect_status, TIMER_DEFAULT_VALUE); + + if (ret_val == SCL_ERROR) { + return NSAPI_ERROR_TIMEOUT; + } + + if (!_interface) { + return NSAPI_STATUS_DISCONNECTED; + } + + // bring down + int err = _interface->bringdown(); + if (err) { + return err; + } + + scl_emac_wifi_link_state_changed(false); + + return NSAPI_ERROR_OK; +} + +int SclSTAInterface::scan(WiFiAccessPoint *res, unsigned count) +{ + /* To Do */ + return NSAPI_ERROR_UNSUPPORTED; +} + +int8_t SclSTAInterface::get_rssi() +{ + int32_t rssi; + scl_result_t res; + + if (!_scl_emac.powered_up) { + _scl_emac.power_up(); + } + + res = (scl_result_t) scl_wifi_get_rssi(&rssi); + if (res == SCL_ERROR) { + return SCL_ERROR; + } + + return (int8_t)rssi; +} + +int SclSTAInterface::is_interface_connected(void) +{ + if (scl_wifi_is_ready_to_transceive() == SCL_SUCCESS) { + return SCL_SUCCESS; + } else { + return SCL_CONNECTION_LOST; + } +} + +int SclSTAInterface::get_bssid(uint8_t *bssid) +{ + scl_mac_t ap_mac; + scl_result_t res = SCL_SUCCESS; + + if (bssid == NULL) { + return SCL_BADARG; + } + + memset(&ap_mac, 0, sizeof(ap_mac)); + if (scl_wifi_is_ready_to_transceive() == SCL_SUCCESS) { + res = (scl_result_t) scl_wifi_get_bssid(&ap_mac); + if (res == SCL_SUCCESS) { + memcpy(bssid, ap_mac.octet, sizeof(ap_mac.octet)); + } + } else { + return SCL_CONNECTION_LOST; + } + return res; +} + +int SclSTAInterface::wifi_set_up(void) +{ + int res = SCL_SUCCESS; + res = scl_wifi_set_up(); + return res; +} diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h new file mode 100644 index 0000000000..801a9a5dfc --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h @@ -0,0 +1,165 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SCL_STA_INTERFACE_H +#define SCL_STA_INTERFACE_H + + +/** @file + * Provides SCL interface functions to be used with WiFiInterface or NetworkInterface Objects + */ + +#include "netsocket/WiFiInterface.h" +#include "netsocket/EMACInterface.h" +#include "netsocket/OnboardNetworkStack.h" +#include "scl_emac.h" +#include "scl_wifi_api.h" +#include "scl_types.h" +#define MAX_SSID_LENGTH (33) /**< Maximum ssid length */ +#define MAX_PASSWORD_LENGTH (64) /**< Maximum password length */ + +/** SclSTAInterface class + * Implementation of the Network Stack for the SCL + */ +class SclSTAInterface : public WiFiInterface, public EMACInterface { +public: + + SclSTAInterface( + SCL_EMAC &emac = SCL_EMAC::get_instance(), + OnboardNetworkStack &stack = OnboardNetworkStack::get_default_instance()); + + /** Gets the current instance of the SclSTAInterface + * + * @return Pointer to the object of class SclSTAInterface. + */ + static SclSTAInterface *get_default_instance(); + + /** Turns on the Wi-Fi device + * + * @return void + */ + void wifi_on(); + + /** Starts the interface + * + * Attempts to connect to a Wi-Fi network. Requires ssid and passphrase to be set. + * If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned. + * + * @return 0 on success, negative error code on failure. + */ + nsapi_error_t connect(); + + /** Starts the interface + * + * Attempts to connect to a Wi-Fi network. + * + * @param ssid Name of the network to connect to. + * @param pass Security passphrase to connect to the network. + * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE). + * @param channel This parameter is not supported, setting it to a value other than 0 will result in NSAPI_ERROR_UNSUPPORTED. + * @return 0 on success, negative error code on failure. + */ + nsapi_error_t connect(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE, uint8_t channel = 0); + + /** Disconnects the interface + * + * @return 0 on success, negative error code on failure. + */ + nsapi_error_t disconnect(); + + /** Set the Wi-Fi network credentials + * + * @param ssid Name of the network to connect to. + * @param pass Security passphrase to connect to the network. + * @param security Type of encryption for connection. + * (defaults to NSAPI_SECURITY_NONE) + * @return 0 on success, negative error code on failure. + */ + nsapi_error_t set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE); + + /** Sets the Wi-Fi network channel - NOT SUPPORTED + * + * This function is not supported and will return NSAPI_ERROR_UNSUPPORTED. + * + * @param channel Channel on which the connection is to be made (Default: 0). + * @return Not supported, returns NSAPI_ERROR_UNSUPPORTED. + */ + nsapi_error_t set_channel(uint8_t channel) + { + if (channel != 0) { + return NSAPI_ERROR_UNSUPPORTED; + } + return 0; + } + + /** Set blocking status of interface. + * Nonblocking mode is not supported. + * + * @param blocking True if connect is blocking + * @return 0 on success, negative error code on failure + */ + nsapi_error_t set_blocking(bool blocking) + { + if (blocking) { + _blocking = blocking; + return NSAPI_ERROR_OK; + } else { + return NSAPI_ERROR_UNSUPPORTED; + } + } + /** Gets the current radio signal strength for active connection + * + * @return Connection strength in dBm (negative value). + */ + int8_t get_rssi(); + + /** Scans for available networks - NOT SUPPORTED + * + * @return NSAPI_ERROR_UNSUPPORTED + */ + int scan(WiFiAccessPoint *res, unsigned count); + + /** This function is used to indicate if the device is connected to the network. + * + * @return SCL_SUCCESS if device is connected. + */ + int is_interface_connected(); + + /** Gets the BSSID (MAC address of device connected to). + * + * @param bssid Pointer to the BSSID value. + * @return SCL_SUCCESS if BSSID is obtained successfully. + * @return SCL_BADARG if input parameter is NULL. + * @return SCL_ERROR if unable to fetch BSSID. + */ + int get_bssid(uint8_t *bssid); + + /** This function is used to set up the Wi-Fi interface. + * This function should be used after the wifi_on. + * + * @return SCL_SUCCESS if the Wi-Fi interface is set up successfully. + */ + int wifi_set_up(void); + +private: + + char _ssid[MAX_SSID_LENGTH]; /**< The longest possible name (defined in 802.11) +1 for the \0 */ + char _pass[MAX_PASSWORD_LENGTH]; /**< The longest allowed passphrase + 1 */ + nsapi_security_t _security; /**< Security type */ + SCL_EMAC &_scl_emac; /**< SCL_EMAC object */ +}; +#endif /* ifndef SCL_STA_INTERFACE_H */ diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp new file mode 100644 index 0000000000..59cb5ef0ab --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp @@ -0,0 +1,35 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "SclSTAInterface.h" + +/** @file +* Provides function definition to override get_target_default_intance of WiFiInterface and NetworkInterface classes +*/ + +/** + * Returns the WiFiInterface Object + * This function can be called using WiFiInterface or NetworkInterface objects + * + * @return pointer to WiFiInterface object. + */ + +WiFiInterface *WiFiInterface::get_target_default_instance() +{ + static SclSTAInterface wifi; + return &wifi; +} diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.cpp b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.cpp new file mode 100644 index 0000000000..d7a276858e --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.cpp @@ -0,0 +1,203 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include + +#include "cmsis_os.h" +#include "scl_emac.h" +#include "lwip/etharp.h" +#include "lwip/ethip6.h" +#include "mbed_shared_queues.h" +#include "scl_buffer_api.h" +#include "cy_result.h" +#include "cy_pdl.h" +#include "scl_ipc.h" + +/** @file + * Provides EMAC interface functions to be used with the SCL_EMAC object + */ + +SCL_EMAC::SCL_EMAC(scl_interface_role_t role) + : interface_type(role) +{ +} + +SCL_EMAC::SCL_EMAC() + : interface_type(SCL_STA_ROLE) +{ +} + +SCL_EMAC &SCL_EMAC::get_instance() +{ + return get_instance(SCL_STA_ROLE); +} + +SCL_EMAC &SCL_EMAC::get_instance(scl_interface_role_t role) +{ + static SCL_EMAC emac_sta(SCL_STA_ROLE); + static SCL_EMAC emac_ap(SCL_AP_ROLE); + return role == SCL_AP_ROLE ? emac_ap : emac_sta; +} + +uint32_t SCL_EMAC::get_mtu_size() const +{ + return SCL_PAYLOAD_MTU; +} + +uint32_t SCL_EMAC::get_align_preference() const +{ + return 0; +} + +void SCL_EMAC::add_multicast_group(const uint8_t *addr) +{ + memcpy(multicast_addr.octet, addr, sizeof(multicast_addr.octet)); + scl_wifi_register_multicast_address(&multicast_addr); +} + +void SCL_EMAC::remove_multicast_group(const uint8_t *address) +{ + /* To Do */ +} +void SCL_EMAC::set_all_multicast(bool all) +{ + /* No-op at this stage */ +} + +void SCL_EMAC::power_down() +{ + /* No-op at this stage */ +} + +bool SCL_EMAC::power_up() +{ + if (!powered_up) { + if (scl_wifi_on() != true) { + SCL_LOG(("returning False in scl_wifi_on()\n")); + return false; + } + powered_up = true; + if (link_state && emac_link_state_cb) { + emac_link_state_cb(link_state); + } + } + return true; +} + +bool SCL_EMAC::get_hwaddr(uint8_t *addr) const +{ + scl_mac_t mac; + scl_result_t res = scl_wifi_get_mac_address(&mac); + if (res == SCL_SUCCESS) { + memcpy(addr, mac.octet, sizeof(mac.octet)); + return true; + } else { + SCL_LOG(("return False in SCL_EMAC::gethwaddr\n")); + return false; + } + +} + +void SCL_EMAC::set_hwaddr(const uint8_t *addr) +{ + /* No-op at this stage */ +} + +uint8_t SCL_EMAC::get_hwaddr_size() const +{ + scl_mac_t mac; + return sizeof(mac.octet); +} + +void SCL_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb) +{ + emac_link_input_cb = input_cb; +} + +void SCL_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb) +{ + emac_link_state_cb = state_cb; +} + +void SCL_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr) +{ + memory_manager = &mem_mngr; +} + +bool SCL_EMAC::link_out(emac_mem_buf_t *buf) +{ + scl_result_t retval; + scl_tx_buf_t scl_tx_data; + scl_tx_data.size = memory_manager->get_total_len(buf); + scl_tx_data.buffer = buf; + if (buf == NULL) { + return false; + } + retval = scl_network_send_ethernet_data(scl_tx_data); + if (retval != SCL_SUCCESS) { + return false; + } + memory_manager->free(buf); + return true; +} + +void SCL_EMAC::get_ifname(char *name, uint8_t size) const +{ + if (name != NULL) { + memcpy(name, "scl", size); + } +} + +void SCL_EMAC::set_activity_cb(mbed::Callback cb) +{ + activity_cb = cb; +} + +extern "C" +{ + void scl_network_process_ethernet_data(scl_buffer_t buffer) + { + emac_mem_buf_t *mem_buf = NULL; + + SCL_EMAC &emac = SCL_EMAC::get_instance(SCL_STA_ROLE); + + if (!emac.powered_up && !emac.emac_link_input_cb) { + scl_buffer_release(buffer, SCL_NETWORK_RX); + return; + } + mem_buf = buffer; + if (emac.activity_cb) { + emac.activity_cb(false); + } + emac.emac_link_input_cb(mem_buf); + } + + void scl_emac_wifi_link_state_changed(bool state_up) + { + SCL_EMAC &emac = SCL_EMAC::get_instance(SCL_STA_ROLE); + + emac.link_state = state_up; + if (emac.emac_link_state_cb) { + emac.emac_link_state_cb(state_up); + } + } +} // extern "C" + + diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.h b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.h new file mode 100644 index 0000000000..e6e3ecd8a9 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.h @@ -0,0 +1,189 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SCL_EMAC_H_ +#define SCL_EMAC_H_ + +/** @file + * Provides EMAC interface functions to be used with the SCL_EMAC object + * + */ +#include "EMAC.h" +#include "EMACInterface.h" +#include "WiFiInterface.h" +#include "scl_common.h" +#include "rtos/Semaphore.h" +#include "rtos/Mutex.h" +#include "scl_wifi_api.h" +class SCL_EMAC : public EMAC { +public: + SCL_EMAC(); + SCL_EMAC(scl_interface_role_t itype); + + /** + * Get the EMAC instance + * + * @return Reference to SCL_EMAC object. + */ + static SCL_EMAC &get_instance(); + + /** + * Get the EMAC instance + * + * @param role Interface type. + * + * @return Reference to SCL_EMAC object. + */ + static SCL_EMAC &get_instance(scl_interface_role_t role); + + /** + * Returns the maximum transmission unit + * + * @return MTU in bytes. + */ + virtual uint32_t get_mtu_size() const; + + /** + * Gets the memory buffer alignment preference + * + * Gets the preferred memory buffer alignment of the EMAC device. IP stack may or may not + * align with the link out memory buffer chains using the alignment. + * + * @return Memory alignment requirement in bytes. + */ + virtual uint32_t get_align_preference() const; + + /** + * Returns the interface name + * + * @param name Pointer to the location where the name should be written. + * @param size Maximum number of characters to copy. + */ + virtual void get_ifname(char *name, uint8_t size) const; + + /** + * Returns the size of the underlying interface HW address size. + * + * @return HW address size in bytes. + */ + virtual uint8_t get_hwaddr_size() const; + + /** + * Returns the interface supplied HW address + * Copies the HW address to the provided memory + * @param addr HW address of the underlying interface. It must be of correct size. See @a get_hwaddr_size. + * @return True if HW address is available. + */ + virtual bool get_hwaddr(uint8_t *addr) const; + + /** + * Set HW address for the interface + * + * Provided address must be of correct size. See @a get_hwaddr_size. + * + * Called to set the MAC address to be used - if @a get_hwaddr is provided + * the stack would normally use that, but it could be overridden for test + * purposes. + * + * @param addr Address to be set + */ + virtual void set_hwaddr(const uint8_t *addr); + + /** + * Sends the packet over the link + * + * This cannot be called from an interrupt context. + * + * @param buf Packet to be sent. + * @return True if the packet was sent successfully. False otherwise. + */ + virtual bool link_out(emac_mem_buf_t *buf); + + /** + * Initializes the HW + * + * @return True on success. False in case of an error. + */ + virtual bool power_up(); + + /** + * De-initializes the HW + */ + virtual void power_down(); + + /** + * Sets a callback that is called for packets received for a given interface + * + * @param input_cb Function to be registered as a callback. + */ + virtual void set_link_input_cb(emac_link_input_cb_t input_cb); + + /** + * Sets a callback that is called on changes in the link status for a given interface + * + * @param state_cb Function to be registered as a callback. + */ + virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb); + + /** Adds a device to a multicast group + * + * @param address A multicast group hardware address. + */ + virtual void add_multicast_group(const uint8_t *address); + + /** Removes a device from a multicast group + * + * @param address A multicast group hardware address. + */ + virtual void remove_multicast_group(const uint8_t *address); + + /** Requests reception of all multicast packets + * + * @param all True to receive all multicasts. + * False to receive only multicasts addressed to specified groups. + */ + virtual void set_all_multicast(bool all); + + /** Sets memory manager used to handle memory buffers + * + * @param mem_mngr Pointer to memory manager. + */ + virtual void set_memory_manager(EMACMemoryManager &mem_mngr); + + /** Sets callback to receive EMAC activity events + * + * @param activity_cb The callback for activity events. + */ + virtual void set_activity_cb(mbed::Callback activity_cb); + + emac_link_input_cb_t emac_link_input_cb = NULL; /**< Callback for incoming data */ + emac_link_state_change_cb_t emac_link_state_cb = NULL; /**< Callback for network connection status */ + EMACMemoryManager *memory_manager; /**< Pointer to hold memory manager object */ + bool powered_up = false; /**< Flag for Wi-Fi power on status */ + bool link_state = false; /**< Flag for network connection status */ + scl_interface_role_t interface_type; /**< Type of the interface */ + scl_mac_t multicast_addr; /**< Multicast address */ + mbed::Callback activity_cb; /**< Callback for activity on network */ + +}; +/** Sends the change in network connection state to network stack +* +* @param state_up Connection status. +*/ +extern "C" void scl_emac_wifi_link_state_changed(bool state_up); + +#endif /* SCL_EMAC_H_ */ diff --git a/features/netsocket/ppp/mbed_lib.json b/features/netsocket/ppp/mbed_lib.json index 33bdb3df99..a95bfd25bb 100644 --- a/features/netsocket/ppp/mbed_lib.json +++ b/features/netsocket/ppp/mbed_lib.json @@ -47,6 +47,9 @@ }, "CY8CKIT_062S2_43012": { "thread-stacksize": 896 + }, + "CYSBSYSKIT_01": { + "thread-stacksize": 896 } } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/generated_mac_address.txt b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/generated_mac_address.txt new file mode 100644 index 0000000000..cba1ab8625 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/generated_mac_address.txt @@ -0,0 +1,9 @@ +/* + * This file is used to set the MAC address in NVRAM. + * The MAC address of the Wi-Fi device may be configured in OTP and/or in NVRAM. + * If both OTP and NVRAM contains the MAC address then OTP programmed MAC address will be used. + * PSOC boards are usually programmed with OTP MAC address. + * MAC address is printed during SCL power up + */ + +#define NVRAM_GENERATED_MAC_ADDRESS "macaddr=00:A0:50:45:2e:c8" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h new file mode 100644 index 0000000000..42e0b1c02d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h @@ -0,0 +1,211 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file scl_common.h + * Defines common data types used in SCL + */ + +#include +#include "cy_result.h" + +#ifndef INCLUDED_SCL_COMMON_H_ +#define INCLUDED_SCL_COMMON_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/****************************************************** +* Constants +******************************************************/ + +#define SCL_LOG_ENABLE false /**< Flag to enable SCL debug logs */ +#define SCL_LOG(x) if (SCL_LOG_ENABLE) \ + { printf x; } /**< SCL log interface */ +#define CHECK_BUFFER_NULL(buf) if (buf == NULL)\ + { SCL_LOG(("Buffer pointer is null\n")); \ + return SCL_BADARG; } /**< Helper macro to check if the input buffer pointer is null */ + +#define MODULE_BASE_CODE (0x0080U) /**< Base code for the SCL error status */ +#define SCL_RESULT_TYPE (0) /**< SCL Result type */ + +/* + * scl_result_t Error code format + * |31-18 (14 bit) for module id|17-16 (2 bit) for result type|15-0 for SCL Error code| + * for example, for Error code 1026, the result of SCL_RESULT_CREATE is 33555458. + */ +#define SCL_RESULT_CREATE(x) CY_RSLT_CREATE(SCL_RESULT_TYPE, MODULE_BASE_CODE, (x) ) /**< Create a result value from the specified type, module, and result code */ + +#define SCL_SUCCESS (0) /**< IPC success */ +#define SCL_ERROR (100) /**< IPC error */ +#define SCL_PENDING SCL_RESULT_CREATE(1) /**< IPC Pending */ +#define SCL_TIMEOUT SCL_RESULT_CREATE(2) /**< Timeout */ +#define SCL_BADARG SCL_RESULT_CREATE(5) /**< Bad Arguments */ +#define SCL_UNFINISHED SCL_RESULT_CREATE(10) /**< Operation not finished yet (maybe aborted) */ +#define SCL_PARTIAL_RESULTS SCL_RESULT_CREATE(1003) /**< Partial results */ +#define SCL_INVALID_KEY SCL_RESULT_CREATE(1004) /**< Invalid key */ +#define SCL_DOES_NOT_EXIST SCL_RESULT_CREATE(1005) /**< Does not exist */ +#define SCL_NOT_AUTHENTICATED SCL_RESULT_CREATE(1006) /**< Not authenticated */ +#define SCL_NOT_KEYED SCL_RESULT_CREATE(1007) /**< Not keyed */ +#define SCL_IOCTL_FAIL SCL_RESULT_CREATE(1008) /**< IOCTL fail */ +#define SCL_BUFFER_UNAVAILABLE_TEMPORARY SCL_RESULT_CREATE(1009) /**< Buffer unavailable temporarily */ +#define SCL_BUFFER_UNAVAILABLE_PERMANENT SCL_RESULT_CREATE(1010) /**< Buffer unavailable permanently */ +#define SCL_CONNECTION_LOST SCL_RESULT_CREATE(1012) /**< Connection lost */ +#define SCL_OUT_OF_EVENT_HANDLER_SPACE SCL_RESULT_CREATE(1013) /**< Cannot add extra event handler */ +#define SCL_SEMAPHORE_ERROR SCL_RESULT_CREATE(1014) /**< Error manipulating a semaphore */ +#define SCL_FLOW_CONTROLLED SCL_RESULT_CREATE(1015) /**< Packet retrieval cancelled due to flow control */ +#define SCL_NO_CREDITS SCL_RESULT_CREATE(1016) /**< Packet retrieval cancelled due to lack of bus credits */ +#define SCL_NO_PACKET_TO_SEND SCL_RESULT_CREATE(1017) /**< Packet retrieval cancelled due to no pending packets */ +#define SCL_CORE_CLOCK_NOT_ENABLED SCL_RESULT_CREATE(1018) /**< Core disabled due to no clock */ +#define SCL_CORE_IN_RESET SCL_RESULT_CREATE(1019) /**< Core disabled - in reset */ +#define SCL_UNSUPPORTED SCL_RESULT_CREATE(1020) /**< Unsupported function */ +#define SCL_BUS_WRITE_REGISTER_ERROR SCL_RESULT_CREATE(1021) /**< Error writing to WLAN register */ +#define SCL_SDIO_BUS_UP_FAIL SCL_RESULT_CREATE(1022) /**< SDIO bus failed to come up */ +#define SCL_JOIN_IN_PROGRESS SCL_RESULT_CREATE(1023) /**< Join not finished yet */ +#define SCL_NETWORK_NOT_FOUND SCL_RESULT_CREATE(1024) /**< Specified network was not found */ +#define SCL_INVALID_JOIN_STATUS SCL_RESULT_CREATE(1025) /**< Join status error */ +#define SCL_UNKNOWN_INTERFACE SCL_RESULT_CREATE(1026) /**< Unknown interface specified */ +#define SCL_SDIO_RX_FAIL SCL_RESULT_CREATE(1027) /**< Error during SDIO receive */ +#define SCL_HWTAG_MISMATCH SCL_RESULT_CREATE(1028) /**< Hardware tag header corrupt */ +#define SCL_RX_BUFFER_ALLOC_FAIL SCL_RESULT_CREATE(1029) /**< Failed to allocate a buffer to receive into */ +#define SCL_BUS_READ_REGISTER_ERROR SCL_RESULT_CREATE(1030) /**< Error reading a bus hardware register */ +#define SCL_THREAD_CREATE_FAILED SCL_RESULT_CREATE(1031) /**< Failed to create a new thread */ +#define SCL_QUEUE_ERROR SCL_RESULT_CREATE(1032) /**< Error manipulating a queue */ +#define SCL_BUFFER_POINTER_MOVE_ERROR SCL_RESULT_CREATE(1033) /**< Error moving the current pointer of a packet buffer */ +#define SCL_BUFFER_SIZE_SET_ERROR SCL_RESULT_CREATE(1034) /**< Error setting size of packet buffer */ +#define SCL_THREAD_STACK_NULL SCL_RESULT_CREATE(1035) /**< Null stack pointer passed when non null was required */ +#define SCL_THREAD_DELETE_FAIL SCL_RESULT_CREATE(1036) /**< Error deleting a thread */ +#define SCL_SLEEP_ERROR SCL_RESULT_CREATE(1037) /**< Error sleeping a thread */ +#define SCL_BUFFER_ALLOC_FAIL SCL_RESULT_CREATE(1038) /**< Failed to allocate a packet buffer */ +#define SCL_NO_PACKET_TO_RECEIVE SCL_RESULT_CREATE(1039) /**< No Packets waiting to be received */ +#define SCL_INTERFACE_NOT_UP SCL_RESULT_CREATE(1040) /**< Requested interface is not active */ +#define SCL_DELAY_TOO_LONG SCL_RESULT_CREATE(1041) /**< Requested delay is too long */ +#define SCL_INVALID_DUTY_CYCLE SCL_RESULT_CREATE(1042) /**< Duty cycle is outside limit 0 to 100 */ +#define SCL_PMK_WRONG_LENGTH SCL_RESULT_CREATE(1043) /**< Returned pmk was the wrong length */ +#define SCL_UNKNOWN_SECURITY_TYPE SCL_RESULT_CREATE(1044) /**< AP security type was unknown */ +#define SCL_WEP_NOT_ALLOWED SCL_RESULT_CREATE(1045) /**< AP not allowed to use WEP - it is not secure - use Open instead */ +#define SCL_WPA_KEYLEN_BAD SCL_RESULT_CREATE(1046) /**< WPA / WPA2 key length must be between 8 & 64 bytes */ +#define SCL_FILTER_NOT_FOUND SCL_RESULT_CREATE(1047) /**< Specified filter id not found */ +#define SCL_SPI_ID_READ_FAIL SCL_RESULT_CREATE(1048) /**< Failed to read 0xfeedbead SPI id from chip */ +#define SCL_SPI_SIZE_MISMATCH SCL_RESULT_CREATE(1049) /**< Mismatch in sizes between SPI header and SDPCM header */ +#define SCL_ADDRESS_ALREADY_REGISTERED SCL_RESULT_CREATE(1050) /**< Attempt to register a multicast address twice */ +#define SCL_SDIO_RETRIES_EXCEEDED SCL_RESULT_CREATE(1051) /**< SDIO transfer failed too many times. */ +#define SCL_NULL_PTR_ARG SCL_RESULT_CREATE(1052) /**< Null Pointer argument passed to function. */ +#define SCL_THREAD_FINISH_FAIL SCL_RESULT_CREATE(1053) /**< Error deleting a thread */ +#define SCL_WAIT_ABORTED SCL_RESULT_CREATE(1054) /**< Semaphore/mutex wait has been aborted */ +#define SCL_SET_BLOCK_ACK_WINDOW_FAIL SCL_RESULT_CREATE(1055) /**< Failed to set block ack window */ +#define SCL_DELAY_TOO_SHORT SCL_RESULT_CREATE(1056) /**< Requested delay is too short */ +#define SCL_INVALID_INTERFACE SCL_RESULT_CREATE(1057) /**< Invalid interface provided */ +#define SCL_WEP_KEYLEN_BAD SCL_RESULT_CREATE(1058) /**< WEP / WEP_SHARED key length must be 5 or 13 bytes */ +#define SCL_HANDLER_ALREADY_REGISTERED SCL_RESULT_CREATE(1059) /**< EAPOL handler already registered */ +#define SCL_AP_ALREADY_UP SCL_RESULT_CREATE(1060) /**< Soft AP or P2P group owner already up */ +#define SCL_EAPOL_KEY_PACKET_M1_TIMEOUT SCL_RESULT_CREATE(1061) /**< Timeout occurred while waiting for EAPOL packet M1 from AP */ +#define SCL_EAPOL_KEY_PACKET_M3_TIMEOUT SCL_RESULT_CREATE(1062) /**< Timeout occurred while waiting for EAPOL packet M3 from AP which may indicate incorrect WPA2/WPA passphrase */ +#define SCL_EAPOL_KEY_PACKET_G1_TIMEOUT SCL_RESULT_CREATE(1063) /**< Timeout occurred while waiting for EAPOL packet G1 from AP */ +#define SCL_EAPOL_KEY_FAILURE SCL_RESULT_CREATE(1064) /**< Unknown failure occurred during the EAPOL key handshake */ +#define SCL_MALLOC_FAILURE SCL_RESULT_CREATE(1065) /**< Memory allocation failure */ +#define SCL_ACCESS_POINT_NOT_FOUND SCL_RESULT_CREATE(1066) /**< Access point not found */ +#define SCL_RTOS_ERROR SCL_RESULT_CREATE(1067) /**< RTOS operation failed */ +#define SCL_CLM_BLOB_DLOAD_ERROR SCL_RESULT_CREATE(1068) /**< CLM blob download failed */ +#define SCL_HAL_ERROR SCL_RESULT_CREATE(1069) /**< SCL HAL Error */ +#define SCL_RTOS_STATIC_MEM_LIMIT SCL_RESULT_CREATE(1070) /**< Exceeding the RTOS static objects memory */ + +/* Application uses the following constants to allocate the buffer pool: */ + +#define BDC_HEADER_WITH_PAD 6 /**< BDC Header with padding 4 + 2 */ + +#define SCL_PAYLOAD_MTU (1500) /**< The maximum size, in bytes, of the data part of an Ethernet frame */ + +/****************************************************** +* Type Definitions +******************************************************/ +/** + * Typedef for SCL buffer pointer + */ +typedef void *scl_buffer_t; + +/** + * Typedef for SCL result + */ +typedef uint32_t scl_result_t; + +/****************************************************** +* Structures and Enumerations +******************************************************/ + +/** + * Typedef for SCL boolean flags + */ +typedef enum { + SCL_FALSE = 0, /**< Boolean False */ + SCL_TRUE = 1 /**< Boolean True */ +} scl_bool_t; + +/** + * Typedef for SCL interface roles + */ +typedef enum { + SCL_INVALID_ROLE = 0, /**< Invalid role */ + SCL_STA_ROLE = 1, /**< STA or Client Interface */ + SCL_AP_ROLE = 2, /**< softAP Interface */ + SCL_P2P_ROLE = 3 /**< P2P Interface */ +} scl_interface_role_t; + +/** + * Typedef for SCL IPC receive index + */ +typedef enum { + SCL_RX_DATA = 0, /**< Received buffer */ + SCL_RX_TEST_MSG = 1, /**< Test message */ + SCL_RX_GET_BUFFER = 2, /**< Get the buffer */ + SCL_RX_GET_CONNECTION_STATUS = 3 /**< Get the connection status */ +} scl_ipc_rx_t; + +/** + * Typedef for SCL IPC transmit index + */ +typedef enum { + SCL_TX_TEST_MSG = 1, /**< Test Message */ + SCL_TX_WIFI_INIT = 2, /**< Initialize Wi-Fi */ + SCL_TX_CONFIG_PARAMETERS = 3, /**< Configuration parameters */ + SCL_TX_GET_MAC = 4, /**< Get MAC address */ + SCL_TX_REGISTER_MULTICAST_ADDRESS = 5, /**< Register multicast address */ + SCL_TX_SEND_OUT = 6, /**< Transmit buffer */ + SCL_TX_TRANSCEIVE_READY = 7, /**< Wi-Fi transmit/receive ready */ + SCL_TX_WIFI_ON = 8, /**< Wi-Fi on */ + SCL_TX_WIFI_SET_UP = 9, /**< Wi-Fi setup */ + SCL_TX_WIFI_NW_PARAM = 10, /**< Get network parameters */ + SCL_TX_WIFI_GET_RSSI = 11, /**< Get RSSI */ + SCL_TX_WIFI_GET_BSSID = 12, /**< Get BSSID */ + SCL_TX_CONNECT = 13, /**< Wi-Fi connect */ + SCL_TX_DISCONNECT = 14, /**< Wi-Fi disconnect */ + SCL_TX_CONNECTION_STATUS = 15 /**< Transmit connection status */ +} scl_ipc_tx_t; + + +/** + * Structure for storing a MAC address (Wi-Fi Media Access Control address). + */ +typedef struct { + uint8_t octet[6]; /**< Unique 6-byte MAC address */ +} scl_mac_t; + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_SCL_COMMON_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h new file mode 100644 index 0000000000..a9d3e23700 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h @@ -0,0 +1,120 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides SCL functionality to communicate with Network Processor + */ + +#include "scl_common.h" +#include "cy_device.h" +#include "cy_sysint.h" +#include "cy_ipc_drv.h" +#include "scl_wifi_api.h" +#include "ip4_addr.h" + +#ifndef INCLUDED_SCL_IPC_H +#define INCLUDED_SCL_IPC_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/****************************************************** + * Macros + ******************************************************/ +/** + * Hardware address of IPC_DATA0 register + */ +#define REG_IPC_STRUCT_DATA0(base) (((IPC_STRUCT_V2_Type*)(base))->DATA0) +/** + * Default timeout value (in ms) for SCL operations + */ +#define TIMER_DEFAULT_VALUE (100) +/** + * Default timeout value (in ms) for Wi-Fi on + */ +#define WIFI_ON_TIMEOUT (5000) +/** + * Default timeout value (in seconds) for Wi-Fi connection + */ +#define NW_CONNECT_TIMEOUT (30) +/** + * Default interval (in micro seconds) for polling the Network Processor + */ +#define NW_DELAY_TIME_US (3000000) +/** + * Default parameter length + */ +#define PARAM_LEN (20) + +/****************************************************** +* Variables +******************************************************/ +/** + * Network parameters structure. + */ +typedef struct network_params { + char ip_address[PARAM_LEN]; /**< IP address */ + char netmask[PARAM_LEN]; /**< Netmask */ + char gateway[PARAM_LEN]; /**< Gateway */ + int connection_status; /**< Connection status */ +} network_params_t; + +/****************************************************** +* Function Declarations +******************************************************/ + +/** @addtogroup communication SCL communication API + * APIs for communicating with Network Processor + * @{ + */ + +/** Initializes the SCL thread and necessary artifacts + * + * @return SCL_SUCCESS on successful initialization or SCL_ERROR otherwise + */ +extern scl_result_t scl_init(void); + +/** Sends the SCL data and respective command to Network Processor + * + * @param index Index of the command. + * @param buffer Data to be sent. + * @param timeout The maximum time (in ms) to wait for the Network Processor to release IPC channel. + * + * @return SCL_SUCCESS on successful communication within SCL timeout duration or SCL_ERROR + */ +extern scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout); + +/** Terminates the SCL thread and disables the interrupts + * + * @return SCL_SUCCESS on successful termination of SCL thread and disabling of interrupts or SCL_ERROR on timeout + */ +extern scl_result_t scl_end(void); + +/** Gets the network parameters like IP Address, Netmask, and Gateway from Network Processor + * + * @param nw_param structure pointer of type @a network_params_t + * + * @return SCL_SUCCESS on successful communication or SCL_ERROR + */ +extern scl_result_t scl_get_nw_parameters(network_params_t *nw_param); + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_SCL_IPC_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h new file mode 100644 index 0000000000..bda316cb79 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h @@ -0,0 +1,115 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file scl_types.h + * Defines common data types used in SCL + * + */ + +#include +#include "cy_result.h" + +#ifndef INCLUDED_SCL_TYPES_H_ +#define INCLUDED_SCL_TYPES_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif +/****************************************************** +* Macros +******************************************************/ +#define SSID_NAME_SIZE (32) /**< SSID Length */ + +#define WEP_ENABLED 0x0001 /**< Flag to enable WEP Security */ +#define TKIP_ENABLED 0x0002 /**< Flag to enable TKIP Encryption */ +#define AES_ENABLED 0x0004 /**< Flag to enable AES Encryption */ +#define SHARED_ENABLED 0x00008000 /**< Flag to enable Shared key Security */ +#define WPA_SECURITY 0x00200000 /**< Flag to enable WPA Security */ +#define WPA2_SECURITY 0x00400000 /**< Flag to enable WPA2 Security */ +#define WPA3_SECURITY 0x01000000 /**< Flag to enable WPA3 PSK Security */ + +#define ENTERPRISE_ENABLED 0x02000000 /**< Flag to enable Enterprise Security */ +#define WPS_ENABLED 0x10000000 /**< Flag to enable WPS Security */ +#define IBSS_ENABLED 0x20000000 /**< Flag to enable IBSS mode */ +#define FBT_ENABLED 0x40000000 /**< Flag to enable FBT */ + +#define NO_POWERSAVE_MODE (0) /**< No Power save mode */ +#define PM1_POWERSAVE_MODE (1) /**< Power save mode on specified interface without regard for throughput reduction */ +#define PM2_POWERSAVE_MODE (2) /**< Power save mode on specified interface with High throughput */ + +/** + * Suppresses unused parameter warning + */ +#define UNUSED_PARAMETER(x) ( (void)(x) ) + +/** + * Suppresses unused variable warning + */ +#define UNUSED_VARIABLE(x) ( (void)(x) ) + +/** + * Suppresses unused variable warning that occurs due to an assert being disabled in release mode + */ +#define REFERENCE_DEBUG_ONLY_VARIABLE(x) ( (void)(x) ) + +/****************************************************** +* Constants +******************************************************/ + +/****************************************************** +* Structures and Enumerations +******************************************************/ + +/** + * Enumeration of Wi-Fi security modes + */ +typedef enum { + SCL_SECURITY_OPEN = 0, /**< Open security */ + SCL_SECURITY_WEP_PSK = WEP_ENABLED, /**< WEP PSK Security with open authentication */ + SCL_SECURITY_WEP_SHARED = (WEP_ENABLED | SHARED_ENABLED), /**< WEP PSK Security with shared authentication */ + SCL_SECURITY_WPA_TKIP_PSK = (WPA_SECURITY | TKIP_ENABLED), /**< WPA PSK Security with TKIP */ + SCL_SECURITY_WPA_AES_PSK = (WPA_SECURITY | AES_ENABLED), /**< WPA PSK Security with AES */ + SCL_SECURITY_WPA_MIXED_PSK = (WPA_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA PSK Security with AES & TKIP */ + SCL_SECURITY_WPA2_AES_PSK = (WPA2_SECURITY | AES_ENABLED), /**< WPA2 PSK Security with AES */ + SCL_SECURITY_WPA2_TKIP_PSK = (WPA2_SECURITY | TKIP_ENABLED), /**< WPA2 PSK Security with TKIP */ + SCL_SECURITY_WPA2_MIXED_PSK = (WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA2 PSK Security with AES & TKIP */ + SCL_SECURITY_WPA2_FBT_PSK = (WPA2_SECURITY | AES_ENABLED | FBT_ENABLED), /**< WPA2 FBT PSK Security with AES & TKIP */ + SCL_SECURITY_WPA3_SAE = (WPA3_SECURITY | AES_ENABLED), /**< WPA3 Security with AES */ + SCL_SECURITY_WPA3_WPA2_PSK = (WPA3_SECURITY | WPA2_SECURITY | AES_ENABLED), /**< WPA3 WPA2 PSK Security with AES */ + + SCL_SECURITY_WPA_TKIP_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | TKIP_ENABLED), /**< WPA Enterprise Security with TKIP */ + SCL_SECURITY_WPA_AES_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | AES_ENABLED), /**< WPA Enterprise Security with AES */ + SCL_SECURITY_WPA_MIXED_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA Enterprise Security with AES & TKIP */ + SCL_SECURITY_WPA2_TKIP_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | TKIP_ENABLED), /**< WPA2 Enterprise Security with TKIP */ + SCL_SECURITY_WPA2_AES_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | AES_ENABLED), /**< WPA2 Enterprise Security with AES */ + SCL_SECURITY_WPA2_MIXED_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA2 Enterprise Security with AES & TKIP */ + SCL_SECURITY_WPA2_FBT_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | AES_ENABLED | FBT_ENABLED), /**< WPA2 Enterprise Security with AES & FBT */ + + SCL_SECURITY_IBSS_OPEN = (IBSS_ENABLED), /**< Open security on IBSS ad-hoc network */ + SCL_SECURITY_WPS_OPEN = (WPS_ENABLED), /**< WPS with open security */ + SCL_SECURITY_WPS_SECURE = (WPS_ENABLED | AES_ENABLED), /**< WPS with AES security */ + + SCL_SECURITY_UNKNOWN = -1, /**< Returned by scan function if security is unknown. Do not pass this to the join function! */ + + SCL_SECURITY_FORCE_32_BIT = 0x7fffffff /**< Exists only to force scl_security_t type to 32 bits */ +} scl_security_t; + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_SCL_TYPES_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h new file mode 100644 index 0000000000..f880559a52 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h @@ -0,0 +1,151 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Prototypes of functions for controlling the Wi-Fi system + * + * This file provides prototypes for end-user functions, which allow + * actions such as scanning for Wi-Fi networks, joining Wi-Fi + * networks, getting the MAC address, and so on. + * + */ + +#include +#include "scl_common.h" +#ifndef INCLUDED_SCL_WIFI_API_H +#define INCLUDED_SCL_WIFI_API_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * SCL transmit buffer structure + */ +typedef struct scl_tx_buf { + scl_buffer_t buffer; /**< pointer to the buffer */ + uint32_t size; /**< size of the buffer */ +} scl_tx_buf_t; + +/****************************************************** +* Function Declarations +******************************************************/ + +/** @addtogroup wifi SCL Wi-Fi API + * APIs for controlling the Wi-Fi system + * @{ + */ + +/** Turn on the Wi-Fi device + * + * @note This API should be called before using any SCL Wi-Fi API. + * + * @return True if initialization is successful, False otherwise. + */ +extern bool scl_wifi_on(void); + +/** Brings up the Wi-Fi core + * + * @return SCL_SUCCESS or Error code. + */ +extern scl_result_t scl_wifi_set_up(void); + +/** Retrieves the current Media Access Control (MAC) address + * (or Ethernet hardware address) of the 802.11 device + * + * @param mac Pointer to a variable to which the current MAC address will be written. + * + * @return SCL_SUCCESS or Error code. + */ +extern scl_result_t scl_wifi_get_mac_address(scl_mac_t *mac); + +/** Gets the BSSID of the interface + * + * @note This API should be used after the device is connected to a network. + * + * @param bssid Returns the BSSID address (mac address), if associated. + * + * @return SCL_SUCCESS or Error code. + */ +extern scl_result_t scl_wifi_get_bssid(scl_mac_t *bssid); + +/** Registers interest in a multicast address + * + * Once a multicast address has been registered, all packets detected on the + * medium destined for that address are forwarded to the host. + * Otherwise, the packets are ignored. + * + * @param mac Ethernet MAC address. + * + * @return SCL_SUCCESS If the address was registered successfully or Error code. + */ +extern scl_result_t scl_wifi_register_multicast_address(scl_mac_t *mac); + +/** Determines if an interface is ready to transmit/receive ethernet packets. + * + * @note This function must be called after the connection is established; otherwise, it returns Error code. + * + * @return SCL_SUCCESS If the interface is ready to transmit/receive ethernet packets. + * SCL_NOTFOUND If no AP with a matching SSID was found. + * SCL_NOT_AUTHENTICATED If matching AP was found, but it does not let you authenticate. + * @note This can occur if the device is in the blocklist of the AP. + * SCL_NOT_KEYED If the device has authenticated and associated but has not completed the key exchange. + * @note This can occur if the passphrase is incorrect. + * Error code If the interface is not ready to transmit/receive ethernet packets. + */ +extern scl_result_t scl_wifi_is_ready_to_transceive(void); + +/** Sends an ethernet frame to SCL (called by the Network Stack) + * + * This function takes ethernet data from the network stack and transmits over the wireless network. + * This function returns immediately after the packet has been queued for transmission, + * NOT after it has been transmitted. Packet buffers passed to the SCL + * are released inside the SCL once they have been transmitted. + * + * @param buffer Handle of the packet buffer to be sent. + * + * @return SCL_SUCCESS or Error code. + */ +extern scl_result_t scl_network_send_ethernet_data(scl_tx_buf_t buffer); + +/** Retrieves the latest RSSI value + * + * @note This API must be called after the device is connected to a network. + * + * @param rssi Location where the RSSI value will be stored. + * + * @return SCL_SUCCESS If the RSSI was successfully retrieved or Error code. + */ +extern scl_result_t scl_wifi_get_rssi(int32_t *rssi); + +/** Retrieves the RX data packet + * + * @param buffer Pointer to RX buffer. + */ +extern void scl_network_process_ethernet_data(scl_buffer_t buffer); + +/** Notifies network stack about the change in network connection state + * + * @param state_up Connection state. + */ +extern void scl_emac_wifi_link_state_changed(bool state_up); + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_SCL_WIFI_API_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c new file mode 100644 index 0000000000..f3d462f558 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c @@ -0,0 +1,293 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides SCL functionality to communicate with Network Processor + */ +#include "scl_ipc.h" +#include "scl_buffer_api.h" +#include "cyabs_rtos.h" +#include "mbed_wait_api.h" +#include "string.h" +#include "nsapi_types.h" +/****************************************************** + ** Macros + *******************************************************/ +#define SCL_THREAD_STACK_SIZE (1000) +#define SCL_THREAD_PRIORITY (CY_RTOS_PRIORITY_HIGH) +#define SCL_INTR_SRC (cpuss_interrupts_ipc_4_IRQn) +#define SCL_INTR_PRI (1) +#define SCL_RX_CHANNEL (4) +#define SCL_CHANNEL_NOTIFY_INTR ((1 << SCL_RX_CHANNEL) << 16) +#define SCL_NOTIFY (1 << SCL_TX_CHANNEL) +#define SCL_LOCK_ACQUIRE_STATUS (0x80000000) +#define SCL_TX_CHANNEL (3) +#define SCL_RELEASE (0) +#define DELAY_TIME (1000) +#define SEMAPHORE_MAXCOUNT (1) +#define SEMAPHORE_INITCOUNT (0) +/****************************************************** + ** Function Declarations + *******************************************************/ +static void scl_isr(void); +static void scl_config(void); +static void scl_rx_handler(void); +static scl_result_t scl_thread_init(void); +scl_result_t scl_get_nw_parameters(network_params_t *nw_param); +scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout); +scl_result_t scl_end(void); +scl_result_t scl_init(void); +/****************************************************** + * Variables Definitions + *****************************************************/ +/* Structure of SCL thread info + * scl_thread_quit_flag: flag used to determine if thread is to be quit + * scl_inited: flag used to determine if thread is started + * scl_thread: variable for thread handle + * scl_thread_stack_start: pointer to start of thread stack + * scl_thread_stack_size: size of thread stack + * scl_thread_priority: priority of thread + * scl_rx_ready: semaphore for blocking the thread + */ +struct scl_thread_info_t { + volatile scl_bool_t scl_inited; + volatile scl_bool_t scl_thread_quit_flag; + void *scl_thread_stack_start; + cy_thread_t scl_thread; + cy_semaphore_t scl_rx_ready; + uint32_t scl_thread_stack_size; + cy_thread_priority_t scl_thread_priority; +}; +struct scl_thread_info_t g_scl_thread_info; + +/****************************************************** + * Function Definitions + ******************************************************/ + +/** ISR for the IPC receiver channel interrupt + */ +static void scl_isr(void) +{ + IPC_INTR_STRUCT_Type *scl_rx_intr = NULL; + scl_rx_intr = Cy_IPC_Drv_GetIntrBaseAddr(SCL_RX_CHANNEL); + + if (REG_IPC_INTR_STRUCT_INTR_MASKED(scl_rx_intr) & SCL_CHANNEL_NOTIFY_INTR) { + REG_IPC_INTR_STRUCT_INTR(scl_rx_intr) |= SCL_CHANNEL_NOTIFY_INTR; + if (g_scl_thread_info.scl_inited == SCL_TRUE) { + cy_rtos_set_semaphore(&g_scl_thread_info.scl_rx_ready, true); + } + } +} +/** Configures the IPC interrupt channel + */ +static void scl_config(void) +{ + IPC_INTR_STRUCT_Type *scl_rx_intr = NULL; + cy_stc_sysint_t intrCfg = { + .intrSrc = SCL_INTR_SRC, + .intrPriority = SCL_INTR_PRI + }; + + scl_rx_intr = Cy_IPC_Drv_GetIntrBaseAddr(SCL_RX_CHANNEL); + REG_IPC_INTR_STRUCT_INTR_MASK(scl_rx_intr) |= SCL_CHANNEL_NOTIFY_INTR; + Cy_SysInt_Init(&intrCfg, &scl_isr); + NVIC_EnableIRQ(intrCfg.intrSrc); +} +/** Create the SCL thread and initialize the semaphore for handling the events from Network Processor + * + * @return SCL_SUCCESS on successful initialization of thread or SCL_ERROR on failure + */ +static scl_result_t scl_thread_init(void) +{ + cy_rslt_t retval, tmp = 0; + memset(&g_scl_thread_info, 0, sizeof(g_scl_thread_info)); + g_scl_thread_info.scl_thread_stack_start = (uint8_t *) malloc(SCL_THREAD_STACK_SIZE);; + g_scl_thread_info.scl_thread_stack_size = (uint32_t) SCL_THREAD_STACK_SIZE; + g_scl_thread_info.scl_thread_priority = (cy_thread_priority_t) SCL_THREAD_PRIORITY; + + if (g_scl_thread_info.scl_inited != SCL_TRUE) { + retval = cy_rtos_init_semaphore(&g_scl_thread_info.scl_rx_ready, SEMAPHORE_MAXCOUNT, SEMAPHORE_INITCOUNT); + if (retval != SCL_SUCCESS) { + return SCL_ERROR; + } + retval = cy_rtos_create_thread(&g_scl_thread_info.scl_thread, (cy_thread_entry_fn_t) scl_rx_handler, + "SCL_thread", g_scl_thread_info.scl_thread_stack_start, + g_scl_thread_info.scl_thread_stack_size, + g_scl_thread_info.scl_thread_priority, (uint32_t) tmp); + if (retval != SCL_SUCCESS) { + return SCL_ERROR; + } + g_scl_thread_info.scl_inited = SCL_TRUE; + } else { + return SCL_ERROR; + } + return SCL_SUCCESS; +} + +scl_result_t scl_init(void) +{ + scl_result_t retval = SCL_SUCCESS; + uint32_t configuration_parameters = 0; +#ifdef MBED_CONF_TARGET_NP_CLOUD_DISABLE + configuration_parameters = (MBED_CONF_TARGET_NP_CLOUD_DISABLE << 1); +#else + configuration_parameters = (false << 1); +#endif +#ifdef MBED_CONF_TARGET_NP_WIFI_ENABLE + configuration_parameters |= MBED_CONF_TARGET_NP_WIFI_ENABLE; +#else + configuration_parameters |= false; +#endif + //SCL_LOG("configuration_parameters = %lu\n", configuration_parameters); + scl_config(); + if (g_scl_thread_info.scl_inited != SCL_TRUE) { + retval = scl_thread_init(); + if (retval != SCL_SUCCESS) { + SCL_LOG(("Thread init failed\n")); + return SCL_ERROR; + } else { + retval = scl_send_data(SCL_TX_CONFIG_PARAMETERS, (char *) &configuration_parameters, TIMER_DEFAULT_VALUE); + return retval; + } + } + return SCL_SUCCESS; +} + +scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout) +{ + uint32_t acquire_state; + IPC_STRUCT_Type *scl_send = NULL; + uint32_t delay_timeout; + + SCL_LOG(("scl_send_data index = %d\n", index)); + scl_send = Cy_IPC_Drv_GetIpcBaseAddress(SCL_TX_CHANNEL); + CHECK_BUFFER_NULL(buffer); + if (!(REG_IPC_STRUCT_LOCK_STATUS(scl_send) & SCL_LOCK_ACQUIRE_STATUS)) { + acquire_state = REG_IPC_STRUCT_ACQUIRE(scl_send); + if (!(acquire_state & SCL_LOCK_ACQUIRE_STATUS)) { + SCL_LOG(("IPC Channel 3 Acquired Failed\r\n")); + return SCL_ERROR; + } + REG_IPC_STRUCT_DATA0(scl_send) = index; + REG_IPC_STRUCT_DATA1(scl_send) = (uint32_t) buffer; + REG_IPC_STRUCT_NOTIFY(scl_send) = SCL_NOTIFY; + delay_timeout = 0; + while ((REG_IPC_STRUCT_LOCK_STATUS(scl_send) & SCL_LOCK_ACQUIRE_STATUS) && delay_timeout <= timeout) { + wait_us(DELAY_TIME); + delay_timeout++; + } + if (delay_timeout > timeout) { + REG_IPC_STRUCT_RELEASE(scl_send) = SCL_RELEASE; + delay_timeout = 0; + return SCL_ERROR; + } else { + return SCL_SUCCESS; + } + } else { + SCL_LOG(("unable to acquire lock\n")); + return SCL_ERROR; + } +} + +scl_result_t scl_end(void) +{ + scl_result_t retval = SCL_SUCCESS; + if (g_scl_thread_info.scl_inited == SCL_TRUE) { + retval = (scl_result_t) cy_rtos_terminate_thread(&g_scl_thread_info.scl_thread); + if (retval == SCL_SUCCESS) { + retval = (scl_result_t) cy_rtos_join_thread(&g_scl_thread_info.scl_thread); + if (retval == SCL_SUCCESS) { + retval = (scl_result_t) cy_rtos_deinit_semaphore(&g_scl_thread_info.scl_rx_ready); + if (retval == SCL_SUCCESS) { + g_scl_thread_info.scl_inited = SCL_FALSE; + } + } + } + } + return retval; +} + +/** Thread to handle the received buffer + */ +static void scl_rx_handler(void) +{ + char *buffer = NULL; + nsapi_connection_status_t connection_status; + uint32_t index; + IPC_STRUCT_Type *scl_receive = NULL; + scl_buffer_t cp_buffer; + scl_buffer_t scl_buffer; + uint32_t rx_ipc_size; + struct rx_ipc_info { + uint32_t size; + int *buf_alloc; + }*rx_cp = NULL; + + SCL_LOG(("Starting CP Rx thread\r\n")); + scl_receive = Cy_IPC_Drv_GetIpcBaseAddress(SCL_RX_CHANNEL); + + while (SCL_TRUE) { + cy_rtos_get_semaphore(&g_scl_thread_info.scl_rx_ready, CY_RTOS_NEVER_TIMEOUT, SCL_FALSE); + index = (uint32_t)REG_IPC_STRUCT_DATA0(scl_receive); + SCL_LOG(("scl_rx_handler index = %lu\n", index)); + switch (index) { + case SCL_RX_DATA: { + rx_cp = (struct rx_ipc_info *) REG_IPC_STRUCT_DATA1(scl_receive); + scl_buffer = rx_cp->buf_alloc; + REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; + SCL_LOG(("scl_buffer = %p\n", scl_buffer)); + scl_network_process_ethernet_data(scl_buffer); + break; + } + case SCL_RX_TEST_MSG: { + buffer = (char *) REG_IPC_STRUCT_DATA1(scl_receive); + SCL_LOG(("%s\r\n", (char *) buffer)); + REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; + break; + } + case SCL_RX_GET_BUFFER: { + rx_ipc_size = (uint32_t) REG_IPC_STRUCT_DATA1(scl_receive); + scl_host_buffer_get(&cp_buffer, SCL_NETWORK_RX, rx_ipc_size, SCL_FALSE); + REG_IPC_STRUCT_DATA1(scl_receive) = (uint32_t)cp_buffer; + REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; + break; + } + case SCL_RX_GET_CONNECTION_STATUS: { + connection_status = (nsapi_connection_status_t) REG_IPC_STRUCT_DATA1(scl_receive); + if (connection_status == NSAPI_STATUS_GLOBAL_UP) { + scl_emac_wifi_link_state_changed(true); + } else { + scl_emac_wifi_link_state_changed(false); + } + SCL_LOG(("connection status = %d\n", connection_status)); + break; + } + default: { + SCL_LOG(("incorrect IPC from Network Processor\n")); + REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; + break; + } + } + } +} + +scl_result_t scl_get_nw_parameters(network_params_t *nw_param) +{ + scl_result_t status = SCL_ERROR; + status = scl_send_data(SCL_TX_WIFI_NW_PARAM, (char *)nw_param, TIMER_DEFAULT_VALUE); + return status; +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/include/scl_buffer_api.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/include/scl_buffer_api.h new file mode 100644 index 0000000000..7a188ce9d2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/include/scl_buffer_api.h @@ -0,0 +1,113 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides declarations for buffer management functionality + */ +#ifndef _SCL_INTERNAL_BUFFER_API_H_ +#define _SCL_INTERNAL_BUFFER_API_H_ + +#include "scl_types.h" +#include "scl_common.h" +#include +#include "cy_utils.h" +#include "memp.h" +#include "pbuf.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/****************************************************** +* Constants +******************************************************/ +/** + * Size of the SDIO block + */ +#define SDIO_BLOCK_SIZE (64U) + +/****************************************************** +* Macros +******************************************************/ + +/****************************************************** +* Structures and Enumerations +******************************************************/ +/** + * Indicates the transmit/receive direction that the buffer has + * been used for. This is needed if transmit/receive pools are separate. + */ +typedef enum { + SCL_NETWORK_TX = 0, /**< Transmit direction */ + SCL_NETWORK_RX = 1 /**< Receive direction */ +} scl_buffer_dir_t; + +/****************************************************** +* Function Prototypes +******************************************************/ +/** Allocates the SCL buffer. + * + * Attempts to allocate a buffer of the requested size. A buffer + * is either allocated from a static pool of memory or allocated dynamically. + * + * @param buffer A pointer which receives the allocated buffer. + * @param direction Indicates transmit/receive direction that the buffer is + * used for. This may be needed if transmit/receive pools are separate. + * @param size The number of bytes to allocate. + * @param wait Time to wait for a buffer to be available in milli-seconds. + * + * @return SCL_SUCCESS or Error code + * + */ +scl_result_t scl_host_buffer_get(scl_buffer_t *buffer, scl_buffer_dir_t direction, + uint16_t size, uint32_t wait); + +/** Releases the SCL buffer. + * + * This function is used by SCL to indicate that it no longer requires + * the buffer. The buffer can then be released back into a pool for + * reuse or the dynamically allocated memory can be freed. + * + * @param buffer The buffer to be released. + * @param direction Indicates the transmit/receive direction that the buffer has + * been used for. This might be needed if transmit/receive pools are separate. + * + */ +void scl_buffer_release(scl_buffer_t buffer, scl_buffer_dir_t direction); + +/** Retrieves the pointer to the payload of the buffer. + * + * @param buffer The buffer whose payload pointer is to be retrieved. + * + * @return Pointer to the payload. + */ +uint8_t *scl_buffer_get_current_piece_data_pointer(scl_buffer_t buffer); + +/** Retrieves the size of the buffer. + * + * @param buffer The buffer whose size is to be retrieved. + * + * @return The size of the buffer. + */ +uint16_t scl_buffer_get_current_piece_size(scl_buffer_t buffer); + +#ifdef __cplusplus +} /*extern "C" */ +#endif + +#endif /* ifndef _SCL_INTERNAL_BUFFER_API_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_buffer_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_buffer_api.c new file mode 100644 index 0000000000..ec4d33a412 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_buffer_api.c @@ -0,0 +1,82 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "scl_buffer_api.h" + +/****************************************************** +** @cond Constants +*******************************************************/ + +/****************************************************** +** Enumerations +*******************************************************/ + +/****************************************************** +** Function Declarations +*******************************************************/ + +/****************************************************** + * Variables Definitions + *****************************************************/ + +/****************************************************** +* Function Definitions +******************************************************/ + +scl_result_t scl_host_buffer_get(scl_buffer_t *buffer, scl_buffer_dir_t direction, + uint16_t size, uint32_t wait) +{ + UNUSED_PARAMETER(direction); + struct pbuf *p = NULL; + if ((direction == SCL_NETWORK_TX) && (size <= PBUF_POOL_BUFSIZE)) { + p = pbuf_alloc(PBUF_RAW, size, PBUF_POOL); + } else { + p = pbuf_alloc(PBUF_RAW, size + SDIO_BLOCK_SIZE, PBUF_RAM); + if (p != NULL) { + p->len = size; + p->tot_len -= SDIO_BLOCK_SIZE; + } + } + if (p != NULL) { + *buffer = p; + return SCL_SUCCESS; + } else { + return SCL_BUFFER_ALLOC_FAIL; + } + +} + +void scl_buffer_release(scl_buffer_t buffer, scl_buffer_dir_t direction) +{ + UNUSED_PARAMETER(direction); + (void) pbuf_free((struct pbuf *)buffer); +} + +uint8_t *scl_buffer_get_current_piece_data_pointer(scl_buffer_t buffer) +{ + CY_ASSERT(buffer != NULL); + struct pbuf *pbuffer = (struct pbuf *) buffer; + return (uint8_t *) pbuffer->payload; +} + +uint16_t scl_buffer_get_current_piece_size(scl_buffer_t buffer) +{ + CY_ASSERT(buffer != NULL); + struct pbuf *pbuffer = (struct pbuf *) buffer; + return (uint16_t) pbuffer->len; +} + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c new file mode 100644 index 0000000000..92b7e43d8d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c @@ -0,0 +1,160 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "scl_wifi_api.h" +#include "scl_ipc.h" + +/****************************************************** + * Variables Definitions + *****************************************************/ + +typedef struct { + scl_mac_t *mac; + uint32_t retval; +} scl_mac; + +/****************************************************** + * Function Definitions + ******************************************************/ + +scl_result_t scl_wifi_is_ready_to_transceive(void) +{ + scl_result_t result = SCL_SUCCESS; + scl_result_t retval = SCL_SUCCESS; + + result = scl_send_data(SCL_TX_TRANSCEIVE_READY, (char *)&retval, TIMER_DEFAULT_VALUE); + if (result == SCL_ERROR) { + SCL_LOG(("Ready to tranceive error\n")); + return SCL_ERROR; + } else { + return retval; + } +} + +bool scl_wifi_on(void) +{ + bool retval = false; + scl_result_t result = SCL_SUCCESS; + result = scl_send_data(SCL_TX_WIFI_ON, (char *)&retval, WIFI_ON_TIMEOUT); + if (result == SCL_ERROR) { + SCL_LOG(("wifi_on Error\n")); + return false; + } else { + return retval; + } +} + +scl_result_t scl_wifi_set_up(void) +{ + scl_result_t retval = SCL_SUCCESS; + scl_result_t result = SCL_SUCCESS; + result = scl_send_data(SCL_TX_WIFI_SET_UP, (char *)&retval, TIMER_DEFAULT_VALUE); + if (result == SCL_SUCCESS) { + return retval; + } else { + SCL_LOG(("Wifi set up error\n")); + return SCL_ERROR; + } +} + +scl_result_t scl_wifi_get_mac_address(scl_mac_t *mac) +{ + scl_mac scl_mac_data; + scl_result_t scl_retval = SCL_SUCCESS; + scl_mac_data.mac = mac; + scl_mac_data.retval = SCL_SUCCESS; + + if (mac == NULL) { + return SCL_BADARG; + } + scl_retval = scl_send_data(SCL_TX_GET_MAC, (char *)&scl_mac_data, TIMER_DEFAULT_VALUE); + if (scl_retval == SCL_SUCCESS) { + return scl_mac_data.retval; + } else { + SCL_LOG(("Get MAC address error\n")); + return SCL_ERROR; + } +} + +scl_result_t scl_wifi_get_bssid(scl_mac_t *bssid) +{ + struct scl_bssid { + scl_mac_t *bssid; + uint32_t retval; + } scl_bssid_t; + scl_result_t scl_retval = SCL_SUCCESS; + scl_bssid_t.bssid = bssid; + scl_bssid_t.retval = 0; + if (bssid == NULL) { + return SCL_BADARG; + } + scl_retval = scl_send_data(SCL_TX_WIFI_GET_BSSID, (char *)&scl_bssid_t, TIMER_DEFAULT_VALUE); + if (scl_retval == SCL_SUCCESS) { + return scl_bssid_t.retval; + } else { + SCL_LOG(("get bssid error\n")); + return SCL_ERROR; + } +} + +scl_result_t scl_wifi_register_multicast_address(scl_mac_t *mac) +{ + scl_mac scl_mac_t; + scl_mac_t.mac = mac; + scl_mac_t.retval = 0; + scl_result_t scl_retval = SCL_SUCCESS; + if (mac == NULL) { + return SCL_BADARG; + } + scl_retval = scl_send_data(SCL_TX_REGISTER_MULTICAST_ADDRESS, (char *)&scl_mac_t, TIMER_DEFAULT_VALUE); + if (scl_retval != SCL_SUCCESS) { + SCL_LOG(("Register Multicast Address IPC Error")); + return SCL_ERROR; + } + return (scl_mac_t.retval); +} + +scl_result_t scl_network_send_ethernet_data(scl_tx_buf_t scl_buffer) +{ + scl_result_t retval = SCL_SUCCESS; + if (scl_buffer.buffer == NULL) { + return SCL_BADARG; + } + retval = scl_send_data(SCL_TX_SEND_OUT, (char *)&scl_buffer, TIMER_DEFAULT_VALUE); + return retval; +} + +scl_result_t scl_wifi_get_rssi(int32_t *rssi) +{ + struct tx_param { + uint32_t retval; + int32_t *get_rssi; + } tx_param_t; + scl_result_t scl_retval = SCL_SUCCESS; + + if (rssi == NULL) { + return SCL_BADARG; + } + tx_param_t.get_rssi = rssi; + scl_retval = scl_send_data(SCL_TX_WIFI_GET_RSSI, (char *) &tx_param_t, TIMER_DEFAULT_VALUE); + if (scl_retval == SCL_SUCCESS) { + return tx_param_t.retval; + } else { + SCL_LOG(("get rssi error\n")); + return SCL_ERROR; + } +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c new file mode 100644 index 0000000000..54662185ad --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -0,0 +1,33 @@ +/******************************************************************************* +* File Name: cycfg.c +* +* Description: +* Wrapper function to initialize all generated code. +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg.h" + +void init_cycfg_all(void) +{ + init_cycfg_routing(); + init_cycfg_pins(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h new file mode 100644 index 0000000000..6ceb622e4f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -0,0 +1,47 @@ +/******************************************************************************* +* File Name: cycfg.h +* +* Description: +* Simple wrapper header containing all generated files. +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_H) +#define CYCFG_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +#include "cycfg_system.h" +#include "cycfg_routing.h" +#include "cycfg_pins.h" + +void init_cycfg_all(void); + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp new file mode 100644 index 0000000000..8619de1542 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -0,0 +1,26 @@ +/******************************************************************************* +* File Name: cycfg.timestamp +* +* Description: +* Sentinel file for determining if generated source is up to date. +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h new file mode 100644 index 0000000000..3587d0e5f0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: cycfg_notices.h +* +* Description: +* Contains warnings and errors that occurred while generating code for the +* design. +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + + +#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c new file mode 100644 index 0000000000..41daa132b4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -0,0 +1,177 @@ +/******************************************************************************* +* File Name: cycfg_pins.c +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_pins.h" + +const cy_stc_gpio_pin_config_t CYBSP_SW1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_SW1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SW1_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SW1_PORT_NUM, + .channel_num = CYBSP_SW1_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_LED1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_LED1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_LED1_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_LED1_PORT_NUM, + .channel_num = CYBSP_LED1_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_SWO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWO_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWO_PORT_NUM, + .channel_num = CYBSP_SWO_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = CYBSP_SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWDIO_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWDIO_PORT_NUM, + .channel_num = CYBSP_SWDIO_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = CYBSP_SWDCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWDCK_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWDCK_PORT_NUM, + .channel_num = CYBSP_SWDCK_PIN, + }; +#endif //defined (CY_USING_HAL) + + +void init_cycfg_pins(void) +{ + Cy_GPIO_Pin_Init(CYBSP_SW1_PORT, CYBSP_SW1_PIN, &CYBSP_SW1_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SW1_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_LED1_PORT, CYBSP_LED1_PIN, &CYBSP_LED1_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_LED1_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h new file mode 100644 index 0000000000..4aacaaa8d3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -0,0 +1,190 @@ +/******************************************************************************* +* File Name: cycfg_pins.h +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_gpio.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) +#include "cycfg_routing.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYBSP_SW1_ENABLED 1U +#define CYBSP_SW1_PORT GPIO_PRT0 +#define CYBSP_SW1_PORT_NUM 0U +#define CYBSP_SW1_PIN 4U +#define CYBSP_SW1_NUM 4U +#define CYBSP_SW1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_SW1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_4_HSIOM + #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SW1_HSIOM ioss_0_port_0_pin_4_HSIOM +#define CYBSP_SW1_IRQ ioss_interrupts_gpio_0_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SW1_HAL_PORT_PIN P0_4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SW1_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SW1_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SW1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_LED1_ENABLED 1U +#define CYBSP_LED1_PORT GPIO_PRT11 +#define CYBSP_LED1_PORT_NUM 11U +#define CYBSP_LED1_PIN 1U +#define CYBSP_LED1_NUM 1U +#define CYBSP_LED1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_LED1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_1_HSIOM + #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_LED1_HSIOM ioss_0_port_11_pin_1_HSIOM +#define CYBSP_LED1_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_LED1_HAL_PORT_PIN P11_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED1_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED1_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_SWO_ENABLED 1U +#define CYBSP_SWO_PORT GPIO_PRT6 +#define CYBSP_SWO_PORT_NUM 6U +#define CYBSP_SWO_PIN 4U +#define CYBSP_SWO_NUM 4U +#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SWO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_4_HSIOM + #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM +#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_PORT_PIN P6_4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_SWDIO_ENABLED 1U +#define CYBSP_SWDIO_PORT GPIO_PRT6 +#define CYBSP_SWDIO_PORT_NUM 6U +#define CYBSP_SWDIO_PIN 6U +#define CYBSP_SWDIO_NUM 6U +#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP +#define CYBSP_SWDIO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_6_HSIOM + #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM +#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_PORT_PIN P6_6 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP +#endif //defined (CY_USING_HAL) +#define CYBSP_SWDCK_ENABLED 1U +#define CYBSP_SWDCK_PORT GPIO_PRT6 +#define CYBSP_SWDCK_PORT_NUM 6U +#define CYBSP_SWDCK_PIN 7U +#define CYBSP_SWDCK_NUM 7U +#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN +#define CYBSP_SWDCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_7_HSIOM + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM +#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_PORT_PIN P6_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN +#endif //defined (CY_USING_HAL) + +extern const cy_stc_gpio_pin_config_t CYBSP_SW1_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SW1_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_LED1_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_LED1_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWO_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWDIO_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWDCK_obj; +#endif //defined (CY_USING_HAL) + +void init_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c new file mode 100644 index 0000000000..92d57a03ff --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -0,0 +1,266 @@ +/******************************************************************************* +* File Name: cycfg_qspi_memslot.c +* +* Description: +* Provides definitions of the SMIF-driver memory configuration. +* This file was automatically generated and should not be modified. +* QSPI Configurator: 2.0.0.1483 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_qspi_memslot.h" + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xEBU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_QUAD, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0x01U, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 4U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x06U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x04U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xD8U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x60U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x38U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x35U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x05U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x01U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 = +{ + /* Specifies the number of address bytes used by the memory slave device. */ + .numOfAddrBytes = 0x03U, + /* The size of the memory. */ + .memSize = 0x04000000U, + /* Specifies the Read command. */ + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd, + /* Specifies the Write Enable command. */ + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd, + /* Specifies the Write Disable command. */ + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd, + /* Specifies the Erase command. */ + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd, + /* Specifies the sector size of each erase. */ + .eraseSize = 0x00040000U, + /* Specifies the Chip Erase command. */ + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd, + /* Specifies the Program command. */ + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd, + /* Specifies the page size for programming. */ + .programSize = 0x00000200U, + /* Specifies the command to read the QE-containing status register. */ + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd, + /* Specifies the command to read the WIP-containing status register. */ + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd, + /* Specifies the command to write into the QE-containing status register. */ + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd, + /* The mask for the status register. */ + .stsRegBusyMask = 0x01U, + /* The mask for the status register. */ + .stsRegQuadEnableMask = 0x02U, + /* The max time for the erase type-1 cycle-time in ms. */ + .eraseTime = 2600U, + /* The max time for the chip-erase cycle-time in ms. */ + .chipEraseTime = 460000U, + /* The max time for the page-program cycle-time in us. */ + .programTime = 1300U +}; + +const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 = +{ + /* Determines the slot number where the memory device is placed. */ + .slaveSelect = CY_SMIF_SLAVE_SELECT_0, + /* Flags. */ + .flags = CY_SMIF_FLAG_WR_EN, + /* The data-line selection options for a slave device. */ + .dataSelect = CY_SMIF_DATA_SEL0, + /* The base address the memory slave is mapped to in the PSoC memory map. + Valid when the memory-mapped mode is enabled. */ + .baseAddress = 0x18000000U, + /* The size allocated in the PSoC memory map, for the memory slave device. + The size is allocated from the base address. Valid when the memory mapped mode is enabled. */ + .memMappedSize = 0x10000U, + /* If this memory device is one of the devices in the dual quad SPI configuration. + Valid when the memory mapped mode is enabled. */ + .dualQuadSlots = 0, + /* The configuration of the device. */ + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0 +}; + +const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { + &S25FL512S_SlaveSlot_0 +}; + +const cy_stc_smif_block_config_t smifBlockConfig = +{ + /* The number of SMIF memories defined. */ + .memCount = CY_SMIF_DEVICE_NUM, + /* The pointer to the array of memory config structures of size memCount. */ + .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs, + /* The version of the SMIF driver. */ + .majorVersion = CY_SMIF_DRV_VERSION_MAJOR, + /* The version of the SMIF driver. */ + .minorVersion = CY_SMIF_DRV_VERSION_MINOR +}; + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h new file mode 100644 index 0000000000..c313452c10 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -0,0 +1,51 @@ +/******************************************************************************* +* File Name: cycfg_qspi_memslot.h +* +* Description: +* Provides declarations of the SMIF-driver memory configuration. +* This file was automatically generated and should not be modified. +* QSPI Configurator: 2.0.0.1483 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#ifndef CYCFG_QSPI_MEMSLOT_H +#define CYCFG_QSPI_MEMSLOT_H +#include "cy_smif_memslot.h" + +#define CY_SMIF_DEVICE_NUM 1 + +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd; + +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0; + +extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0; +extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; + +extern const cy_stc_smif_block_config_t smifBlockConfig; + + +#endif /*CY_SMIF_MEMCONFIG_H*/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c new file mode 100644 index 0000000000..a8de1e3d5f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -0,0 +1,31 @@ +/******************************************************************************* +* File Name: cycfg_routing.c +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_routing.h" + +void init_cycfg_routing(void) +{ +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h new file mode 100644 index 0000000000..645fc6902d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -0,0 +1,46 @@ +/******************************************************************************* +* File Name: cycfg_routing.h +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +void init_cycfg_routing(void); +#define init_cycfg_connectivity() init_cycfg_routing() +#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO +#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS +#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c new file mode 100644 index 0000000000..d06a4b5f86 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -0,0 +1,28 @@ +/******************************************************************************* +* File Name: cycfg_system.c +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_system.h" + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h new file mode 100644 index 0000000000..106e61a459 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -0,0 +1,43 @@ +/******************************************************************************* +* File Name: cycfg_system.h +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_SYSTEM_H) +#define CYCFG_SYSTEM_H + +#include "cycfg_notices.h" +#if defined(__cplusplus) +extern "C" { +#endif + +#define cpuss_0_dap_0_ENABLED 1U + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_SYSTEM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg new file mode 100644 index 0000000000..a561643dcf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg @@ -0,0 +1,2 @@ +set SMIF_BANKS { +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list new file mode 100644 index 0000000000..edb189b2e2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -0,0 +1,99 @@ +[Device=CY8C624AFNI-D43] + +[Blocks] +# WIFI +# CYBSP_WIFI_SDIO +sdhc[0] +# CYBSP_WIFI_SDIO_D0 +ioss[0].port[2].pin[0] +# CYBSP_WIFI_SDIO_D1 +ioss[0].port[2].pin[1] +# CYBSP_WIFI_SDIO_D2 +ioss[0].port[2].pin[2] +# CYBSP_WIFI_SDIO_D3 +ioss[0].port[2].pin[3] +# CYBSP_WIFI_SDIO_CMD +ioss[0].port[2].pin[4] +# CYBSP_WIFI_SDIO_CLK +ioss[0].port[2].pin[5] +# CYBSP_WIFI_WL_REG_ON +ioss[0].port[2].pin[6] +# CYBSP_WIFI_DEVICE_WAKE +ioss[0].port[2].pin[7] +# CYBSP_WIFI_HOST_WAKE +ioss[0].port[1].pin[4] + +# BT UART +# CYBSP_BT_UART +scb[12] +# CYBSP_BT_POWER +ioss[0].port[12].pin[0] +# CYBSP_BT_DEVICE_WAKE +ioss[0].port[12].pin[2] +# CYBSP_BT_HOST_WAKE +ioss[0].port[12].pin[3] +# CYBSP_BT_UART_RX +ioss[0].port[13].pin[4] +# CYBSP_BT_UART_TX +ioss[0].port[13].pin[5] +# CYBSP_BT_UART_RTS +ioss[0].port[13].pin[6] +# CYBSP_BT_UART_CTS +ioss[0].port[13].pin[7] +# CYBSP_BT_UART_CLK_DIV +peri[0].div_16[1] + +# UART +# CYBSP_DEBUG_UART +scb[10] +# CYBSP_DEBUG_UART_RX +ioss[0].port[5].pin[4] +# CYBSP_DEBUG_UART_TX +ioss[0].port[5].pin[5] +# CYBSP_DEBUG_UART_CLK_DIV +peri[0].div_16[0] + +# POWER +srss[0].power[0] + +# SYSTEM CLOCK +srss[0].clock[0] +# CLK_ALT_SYS_TICK +srss[0].clock[0].altsystickclk[0] +# CLK_BAK +srss[0].clock[0].bakclk[0] +# CLK_FAST +srss[0].clock[0].fastclk[0] +# CLK_HF0 +srss[0].clock[0].hfclk[0] +# CLK_HF2 +srss[0].clock[0].hfclk[2] +# CLK_HF4 +srss[0].clock[0].hfclk[4] +# CLK_ILO +srss[0].clock[0].ilo[0] +# CLK_IMO +srss[0].clock[0].imo[0] +# CLK_LF +srss[0].clock[0].lfclk[0] +# PATH_MUX0 +srss[0].clock[0].pathmux[0] +# PATH_MUX1 +srss[0].clock[0].pathmux[1] +# CLK_PERI +srss[0].clock[0].periclk[0] +# CLK_PLL0 +srss[0].clock[0].pll[0] +# CLK_SLOW +srss[0].clock[0].slowclk[0] +# CLK_TIMER +srss[0].clock[0].timerclk[0] + +# RTC +srss[0].rtc[0] + +# CM0(NP) I2C +# CYBSP_I2C_SCL +ioss[0].port[8].pin[0] +# CYBSP_I2C_SDA +ioss[0].port[8].pin[1] diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense new file mode 100644 index 0000000000..a31d15e293 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -0,0 +1,71 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi new file mode 100644 index 0000000000..f0610e1067 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -0,0 +1,63 @@ + + + + PSoC 6.xml + + + 0 + S25FL512S + false + None + 0x18000000 + 0x10000 + 0x1800FFFF + true + false + QUAD_SPI_DATA_0_3 + S25FL512S + true + + + 1 + Not used + false + None + 0x18010000 + 0x10000 + 0x1801FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 2 + Not used + false + None + 0x18020000 + 0x10000 + 0x1802FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 3 + Not used + false + None + 0x18030000 + 0x10000 + 0x1803FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus new file mode 100644 index 0000000000..120837b1b1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -0,0 +1,106 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c new file mode 100644 index 0000000000..57eb8a28a6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c @@ -0,0 +1,427 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralNames.h" +#include "PeripheralPins.h" +#include "pinmap.h" + +#if DEVICE_SERIAL +//*** SERIAL *** +const PinMap PinMap_UART_RX[] = { + {P0_2, UART_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)}, + {P1_0, UART_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)}, + {P2_0, UART_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_UART_RX)}, + {P2_4, UART_9, CYHAL_PIN_IN_FUNCTION(P2_4_SCB9_UART_RX)}, + {P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)}, + {P5_4, UART_10, CYHAL_PIN_IN_FUNCTION(P5_4_SCB10_UART_RX)}, + {P6_0, UART_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)}, + {P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)}, + {P7_0, UART_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)}, + {P8_0, UART_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)}, + {P8_4, UART_11, CYHAL_PIN_IN_FUNCTION(P8_4_SCB11_UART_RX)}, + {P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)}, + {P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)}, + {P11_0, UART_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)}, + {P12_0, UART_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)}, + {P13_0, UART_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)}, + {P13_4, UART_12, CYHAL_PIN_IN_FUNCTION(P13_4_SCB12_UART_RX)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_TX[] = { + {P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)}, + {P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)}, + {P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_UART_TX)}, + {P2_5, UART_9, CYHAL_PIN_OUT_FUNCTION(P2_5_SCB9_UART_TX)}, + {P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)}, + {P5_5, UART_10, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB10_UART_TX)}, + {P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)}, + {P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)}, + {P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)}, + {P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)}, + {P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)}, + {P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)}, + {P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)}, + {P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)}, + {P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)}, + {P13_5, UART_12, CYHAL_PIN_OUT_FUNCTION(P13_5_SCB12_UART_TX)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_RTS[] = { + {P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)}, + {P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_UART_RTS)}, + {P2_6, UART_9, CYHAL_PIN_OUT_FUNCTION(P2_6_SCB9_UART_RTS)}, + {P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)}, + {P5_6, UART_10, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB10_UART_RTS)}, + {P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)}, + {P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)}, + {P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)}, + {P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)}, + {P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)}, + {P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)}, + {P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)}, + {P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)}, + {P13_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_UART_RTS)}, + {P13_6, UART_12, CYHAL_PIN_OUT_FUNCTION(P13_6_SCB12_UART_RTS)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_CTS[] = { + {P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)}, + {P2_3, UART_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_UART_CTS)}, + {P2_7, UART_9, CYHAL_PIN_IN_FUNCTION(P2_7_SCB9_UART_CTS)}, + {P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)}, + {P5_7, UART_10, CYHAL_PIN_IN_FUNCTION(P5_7_SCB10_UART_CTS)}, + {P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)}, + {P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)}, + {P7_3, UART_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)}, + {P8_3, UART_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)}, + {P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)}, + {P10_3, UART_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)}, + {P11_3, UART_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)}, + {P12_3, UART_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)}, + {P13_3, UART_6, CYHAL_PIN_IN_FUNCTION(P13_3_SCB6_UART_CTS)}, + {P13_7, UART_12, CYHAL_PIN_IN_FUNCTION(P13_7_SCB12_UART_CTS)}, + {NC, NC, 0} +}; +#endif // DEVICE_SERIAL + + +#if DEVICE_I2C +//*** I2C *** +const PinMap PinMap_I2C_SCL[] = { + {P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)}, + {P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)}, + {P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_0_SCB1_I2C_SCL)}, + {P2_4, I2C_9, CYHAL_PIN_OD_FUNCTION(P2_4_SCB9_I2C_SCL)}, + {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)}, + {P5_4, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_4_SCB10_I2C_SCL)}, + {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)}, + {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)}, + {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)}, + {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)}, + {P8_4, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_4_SCB11_I2C_SCL)}, + {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)}, + {P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)}, + {P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)}, + {P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)}, + {P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)}, + {P13_4, I2C_12, CYHAL_PIN_OD_FUNCTION(P13_4_SCB12_I2C_SCL)}, + {NC, NC, 0} +}; +const PinMap PinMap_I2C_SDA[] = { + {P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)}, + {P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)}, + {P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_1_SCB1_I2C_SDA)}, + {P2_5, I2C_9, CYHAL_PIN_OD_FUNCTION(P2_5_SCB9_I2C_SDA)}, + {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)}, + {P5_5, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_5_SCB10_I2C_SDA)}, + {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)}, + {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)}, + {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)}, + {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)}, + {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)}, + {P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)}, + {P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)}, + {P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)}, + {P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)}, + {P13_5, I2C_12, CYHAL_PIN_OD_FUNCTION(P13_5_SCB12_I2C_SDA)}, + {NC, NC, 0} +}; +#endif // DEVICE_I2C + +#if DEVICE_SPI +//*** SPI *** +const PinMap PinMap_SPI_MOSI[] = { + {P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)}, + {P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)}, + {P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_0_SCB1_SPI_MOSI)}, + {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)}, + {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)}, + {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)}, + {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)}, + {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)}, + {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)}, + {P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)}, + {P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)}, + {P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)}, + {P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_MISO[] = { + {P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)}, + {P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)}, + {P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P2_1_SCB1_SPI_MISO)}, + {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)}, + {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)}, + {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)}, + {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)}, + {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)}, + {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)}, + {P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)}, + {P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)}, + {P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)}, + {P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SCLK[] = { + {P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)}, + {P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_SPI_CLK)}, + {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)}, + {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)}, + {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)}, + {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)}, + {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)}, + {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)}, + {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)}, + {P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)}, + {P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)}, + {P13_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_SPI_CLK)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SSEL[] = { + {P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)}, + {P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_3_SCB1_SPI_SELECT0)}, + {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)}, + {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)}, + {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)}, + {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)}, + {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)}, + {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)}, + {P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)}, + {P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)}, + {P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)}, + {P13_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_3_SCB6_SPI_SELECT0)}, + {NC, NC, 0} +}; +#endif // DEVICE_SPI + +#if DEVICE_PWMOUT +//*** PWM *** +const PinMap PinMap_PWM_OUT[] = { + // 16-bit PWM outputs + {P0_0, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)}, + {P0_2, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)}, + {P0_4, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)}, + {P1_0, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)}, + {P1_4, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)}, + {P2_0, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM1_LINE15)}, + {P2_2, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM1_LINE16)}, + {P2_4, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM1_LINE17)}, + {P2_6, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM1_LINE18)}, + {P5_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)}, + {P5_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)}, + {P5_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)}, + {P5_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)}, + {P6_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)}, + {P6_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)}, + {P6_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)}, + {P6_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)}, + {P7_0, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)}, + {P7_2, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)}, + {P8_0, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)}, + {P8_2, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)}, + {P8_4, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)}, + {P9_0, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)}, + {P9_2, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)}, + {P9_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)}, + {P10_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)}, + {P10_2, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)}, + {P10_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)}, + {P10_6, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)}, + {P11_0, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)}, + {P11_2, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)}, + {P11_4, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)}, + {P12_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)}, + {P12_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)}, + {P12_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)}, + {P12_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)}, + {P13_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)}, + {P13_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9)}, + {P13_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10)}, + {P13_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)}, + // 16-bit PWM inverted outputs + {P0_1, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)}, + {P0_3, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)}, + {P0_5, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)}, + {P1_1, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)}, + {P1_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)}, + {P2_1, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM1_LINE_COMPL15)}, + {P2_3, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM1_LINE_COMPL16)}, + {P2_5, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM1_LINE_COMPL17)}, + {P2_7, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM1_LINE_COMPL18)}, + {P5_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)}, + {P5_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)}, + {P5_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)}, + {P5_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)}, + {P6_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)}, + {P6_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)}, + {P6_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)}, + {P6_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)}, + {P7_1, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)}, + {P7_3, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)}, + {P7_7, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)}, + {P8_1, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)}, + {P8_3, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)}, + {P9_1, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)}, + {P9_3, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)}, + {P9_7, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)}, + {P10_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)}, + {P10_3, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)}, + {P10_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)}, + {P10_7, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)}, + {P11_1, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)}, + {P11_3, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)}, + {P11_5, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)}, + {P12_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)}, + {P12_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)}, + {P12_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)}, + {P12_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)}, + {P13_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)}, + {P13_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9)}, + {P13_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10)}, + {P13_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)}, + // 32-bit PWM outputs + {P0_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, + {P0_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)}, + {P0_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)}, + {P1_0, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)}, + {P1_4, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)}, + {P2_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM0_LINE6)}, + {P2_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM0_LINE7)}, + {P2_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM0_LINE0)}, + {P2_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM0_LINE1)}, + {P5_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)}, + {P5_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)}, + {P5_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)}, + {P5_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)}, + {P6_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)}, + {P6_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)}, + {P6_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)}, + {P6_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)}, + {P7_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)}, + {P7_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)}, + {P8_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)}, + {P8_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)}, + {P8_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)}, + {P9_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)}, + {P9_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)}, + {P9_4, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)}, + {P10_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)}, + {P10_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)}, + {P10_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)}, + {P10_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)}, + {P11_0, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)}, + {P11_2, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)}, + {P11_4, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)}, + {P12_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)}, + {P12_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)}, + {P12_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)}, + {P12_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)}, + {P13_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)}, + {P13_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1)}, + {P13_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2)}, + {P13_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)}, + // 32-bit PWM inverted outputs + {P0_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)}, + {P0_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)}, + {P0_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)}, + {P1_1, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)}, + {P1_5, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)}, + {P2_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM0_LINE_COMPL6)}, + {P2_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM0_LINE_COMPL7)}, + {P2_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM0_LINE_COMPL0)}, + {P2_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM0_LINE_COMPL1)}, + {P5_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)}, + {P5_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)}, + {P5_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)}, + {P5_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)}, + {P6_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)}, + {P6_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)}, + {P6_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)}, + {P6_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)}, + {P7_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)}, + {P7_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)}, + {P7_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)}, + {P8_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)}, + {P8_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)}, + {P9_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)}, + {P9_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)}, + {P9_7, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)}, + {P10_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)}, + {P10_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)}, + {P10_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)}, + {P10_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)}, + {P11_1, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)}, + {P11_3, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)}, + {P11_5, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)}, + {P12_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)}, + {P12_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)}, + {P12_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)}, + {P12_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)}, + {P13_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)}, + {P13_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1)}, + {P13_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2)}, + {P13_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)}, + {NC, NC, 0} +}; +#endif // DEVICE_PWMOUT + +#if DEVICE_ANALOGIN +const PinMap PinMap_ADC[] = { + {P9_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_0 pin through the AMUXA bus + {P9_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_1 pin through the AMUXA bus + {P9_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_2 pin through the AMUXA bus + {P9_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_4 pin through the AMUXA bus + {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_0 pin + {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_1 pin + {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_2 pin + {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_3 pin + {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_4 pin + {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_5 pin + {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_6 pin + {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_7 pin + {NC, NC, 0} +}; +#endif // DEVICE_ANALOGIN + +#if DEVICE_QSPI +const PinMap PinMap_QSPI_SCLK[] = { + {P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_SSEL[] = { + {P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA0[] = { + {P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA1[] = { + {P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA2[] = { + {P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA3[] = { + {P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +#endif // DEVICE_QSPI diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c new file mode 100644 index 0000000000..a935ed999b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c @@ -0,0 +1,115 @@ +/***************************************************************************//** +* \file cybsp.c +* +* Description: +* Provides initialization code for starting up the hardware contained on the +* Cypress board. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cy_syspm.h" +#include "cy_sysclk.h" +#include "cybsp.h" +#if defined(CY_USING_HAL) +#include "cyhal_hwmgr.h" +#endif + +#if !defined (CY_CFG_PWR_SYS_IDLE_MODE) +#include "mbed_power_mgmt.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/* The sysclk deep sleep callback is recommended to be the last callback that +* is executed before entry into deep sleep mode and the first one upon +* exit the deep sleep mode. +* Doing so minimizes the time spent on low power mode entry and exit. +*/ +#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) +#endif + +#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) +static cyhal_sdio_t sdio_obj; + +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) +{ + return &sdio_obj; +} +#endif + +/** + * Registers a power management callback that prepares the clock system + * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. + * NOTE: This is called automatically as part of \ref cybsp_init + */ +static cy_rslt_t cybsp_register_sysclk_pm_callback(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, + .callbackParams = &cybsp_sysclk_pm_callback_param, + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + }; + + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { + result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; + } + return result; +} + +cy_rslt_t cybsp_init(void) +{ + /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ +#if defined(CY_USING_HAL) + cy_rslt_t result = cyhal_hwmgr_init(); +#else + cy_rslt_t result = CY_RSLT_SUCCESS; +#endif + +#if defined(COMPONENT_BSP_DESIGN_MODUS) + init_cycfg_all(); +#endif + + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_register_sysclk_pm_callback(); + } + +#if !defined(CY_CFG_PWR_SYS_IDLE_MODE) + /* Disable deep-sleep. */ + sleep_manager_lock_deep_sleep(); +#endif + + /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by + * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list + * (cyreservedresources.list) to make sure no resources are reserved by both. + */ + return result; +} + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h new file mode 100644 index 0000000000..7d15280e71 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h @@ -0,0 +1,76 @@ +/***************************************************************************//** +* \file cybsp.h +* +* \brief +* Basic API for setting up boards containing a Cypress MCU. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cy_result.h" +#include "cybsp_types.h" +#if defined(COMPONENT_BSP_DESIGN_MODUS) +#include "cycfg.h" +#endif +#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) +#include "cyhal_sdio.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_macros Macros +* \{ +*/ + +/** Failed to configure sysclk power management callback */ +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) + +/** \} group_bsp_macros */ + +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +/** + * \brief Initialize all hardware on the board + * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * a problem initializing any hardware it returns an error code specific + * to the hardware module that had a problem. + */ +cy_rslt_t cybsp_init(void); + +#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + +/** \} group_bsp_functions */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h new file mode 100644 index 0000000000..64ef452d65 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h @@ -0,0 +1,194 @@ +/***************************************************************************//** +* \file CYSBSYSKIT_01/cybsp_types.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CYSBSYSKIT_01 kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#if defined(CY_USING_HAL) +#include "cyhal_pin_package.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +#ifndef CY_CFG_SYSCLK_CLKLF_FREQ_HZ +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ (32000U) +#endif + +/** +* \addtogroup group_bsp_settings BSP Settings +* \{ +* +*
Peripheral Default HAL Settings:
+* | Resource | Parameter | Value | Remarks | +* | :------: | :-------: | :---: | :------ | +* | ADC | VREF | 1.2 V | | +* | ^ | Measurement type | Single Ended | | +* | ^ | Input voltage range | 0 to 2.4 V (0 to 2*VREF) | | +* | ^ | Output range | 0x000 to 0x7FF | | +* | DAC | Reference source | VDDA | | +* | ^ | Input range | 0x000 to 0xFFF | | +* | ^ | Output range | 0 to VDDA | | +* | ^ | Output type | Unbuffered output | | +* | I2C | Role | Master | Configurable to slave mode through HAL function | +* | ^ | Data rate | 100 kbps | Configurable through HAL function | +* | ^ | Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required | +* | LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter. 1 count = 1/32768 second or 32768 counts = 1 second. ||| +* | SPI | Data rate | 100 kpbs | Configurable through HAL function | +* | ^ | Slave select polarity | Active low | | +* | UART | Flow control | No flow control | Configurable through HAL function | +* | ^ | Data format | 8N1 | Configurable through HAL function | +* | ^ | Baud rate | 115200 | Configurable through HAL function | +*/ +/** \} group_bsp_settings */ + +/** +* \addtogroup group_bsp_pin_state Pin States +* \{ +*/ + +/** Pin state for the LED on. */ +#define CYBSP_LED_STATE_ON (0U) +/** Pin state for the LED off. */ +#define CYBSP_LED_STATE_OFF (1U) + +/** Pin state for when a button is pressed. */ +#define CYBSP_BTN_PRESSED (0U) +/** Pin state for when a button is released. */ +#define CYBSP_BTN_OFF (1U) + +/** \} group_bsp_pin_state */ + +#if defined(CY_USING_HAL) + +/** +* \addtogroup group_bsp_pins Pin Mappings +* \{ +*/ + +/** +* \addtogroup group_bsp_pins_led LED Pins +* \{ +*/ + +/** BSP user LED1 reference designator to pin mapping */ +#define CYBSP_USER_LED1 (P11_1) + +/** \} group_bsp_pins_led */ + +/** +* \addtogroup group_bsp_pins_btn Button Pins +* \{ +*/ + +/** BSP user button reference designator to pin mapping */ +#define CYBSP_USER_BTN (P0_4) + +/** \} group_bsp_pins_btn */ + +/** +* \addtogroup group_bsp_pins_comm Communication Pins +* \{ +*/ + +/** Pin: WIFI SDIO D0 */ +#define CYBSP_WIFI_SDIO_D0 (P2_0) +/** Pin: WIFI SDIO D1 */ +#define CYBSP_WIFI_SDIO_D1 (P2_1) +/** Pin: WIFI SDIO D2 */ +#define CYBSP_WIFI_SDIO_D2 (P2_2) +/** Pin: WIFI SDIO D3 */ +#define CYBSP_WIFI_SDIO_D3 (P2_3) +/** Pin: WIFI SDIO CMD */ +#define CYBSP_WIFI_SDIO_CMD (P2_4) +/** Pin: WIFI SDIO CLK */ +#define CYBSP_WIFI_SDIO_CLK (P2_5) +/** Pin: WIFI ON */ +#define CYBSP_WIFI_WL_REG_ON (P2_6) +/** Pin: WIFI Host Wakeup */ +#define CYBSP_WIFI_HOST_WAKE (P1_4) + +/** Host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) +/** Host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) +/** Pin: BT UART RX */ +#define CYBSP_BT_UART_RX (P13_4) +/** Pin: BT UART TX */ +#define CYBSP_BT_UART_TX (P13_5) +/** Pin: BT UART RTS */ +#define CYBSP_BT_UART_RTS (P13_6) +/** Pin: BT UART CTS */ +#define CYBSP_BT_UART_CTS (P13_7) + +/** Pin: BT Power */ +#define CYBSP_BT_POWER (P12_0) +/** Pin: BT Host Wakeup */ +#define CYBSP_BT_HOST_WAKE (P12_3) +/** Pin: BT Device Wakeup */ +#define CYBSP_BT_DEVICE_WAKE (P12_2) + +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RX (P5_4) +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_TX (P5_5) + +/** Pin: SWO */ +#define CYBSP_SWO (P6_4) +/** Pin: SWDIO */ +#define CYBSP_SWDIO (P6_6) +/** Pin: SWDCK */ +#define CYBSP_SWDCK (P6_7) + +/** Pin: QUAD SPI SS */ +#define CYBSP_QSPI_SS (P11_2) +/** Pin: QUAD SPI D3 */ +#define CYBSP_QSPI_D3 (P11_3) +/** Pin: QUAD SPI D2 */ +#define CYBSP_QSPI_D2 (P11_4) +/** Pin: QUAD SPI D1 */ +#define CYBSP_QSPI_D1 (P11_5) +/** Pin: QUAD SPI D0 */ +#define CYBSP_QSPI_D0 (P11_6) +/** Pin: QUAD SPI SCK */ +#define CYBSP_QSPI_SCK (P11_7) + +/** Pin: I2C SCL */ +#define CYBSP_I2C_SCL (P6_0) +/** Pin: I2C SDA */ +#define CYBSP_I2C_SDA (P6_1) + +/** \} group_bsp_pins_comm */ + +/** \} group_bsp_pins */ + + + + +#endif /* defined(CY_USING_HAL) */ + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct new file mode 100644 index 0000000000..ea1cfaefe9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -0,0 +1,298 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm4_dual.sct +;* \version 2.60 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10180000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08080000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x7F800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; Size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S new file mode 100644 index 0000000000..88eb1f471d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S @@ -0,0 +1,703 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 + DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 + DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 + DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 + DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt + DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt + DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used + DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT scb_9_interrupt_IRQHandler [WEAK] + EXPORT scb_10_interrupt_IRQHandler [WEAK] + EXPORT scb_11_interrupt_IRQHandler [WEAK] + EXPORT scb_12_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_0_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_0_interrupt_pdm_IRQHandler [WEAK] + EXPORT audioss_1_interrupt_i2s_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK] + EXPORT sdhc_1_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_1_interrupt_general_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +scb_9_interrupt_IRQHandler +scb_10_interrupt_IRQHandler +scb_11_interrupt_IRQHandler +scb_12_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dmac_0_IRQHandler +cpuss_interrupts_dmac_1_IRQHandler +cpuss_interrupts_dmac_2_IRQHandler +cpuss_interrupts_dmac_3_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw0_16_IRQHandler +cpuss_interrupts_dw0_17_IRQHandler +cpuss_interrupts_dw0_18_IRQHandler +cpuss_interrupts_dw0_19_IRQHandler +cpuss_interrupts_dw0_20_IRQHandler +cpuss_interrupts_dw0_21_IRQHandler +cpuss_interrupts_dw0_22_IRQHandler +cpuss_interrupts_dw0_23_IRQHandler +cpuss_interrupts_dw0_24_IRQHandler +cpuss_interrupts_dw0_25_IRQHandler +cpuss_interrupts_dw0_26_IRQHandler +cpuss_interrupts_dw0_27_IRQHandler +cpuss_interrupts_dw0_28_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_dw1_16_IRQHandler +cpuss_interrupts_dw1_17_IRQHandler +cpuss_interrupts_dw1_18_IRQHandler +cpuss_interrupts_dw1_19_IRQHandler +cpuss_interrupts_dw1_20_IRQHandler +cpuss_interrupts_dw1_21_IRQHandler +cpuss_interrupts_dw1_22_IRQHandler +cpuss_interrupts_dw1_23_IRQHandler +cpuss_interrupts_dw1_24_IRQHandler +cpuss_interrupts_dw1_25_IRQHandler +cpuss_interrupts_dw1_26_IRQHandler +cpuss_interrupts_dw1_27_IRQHandler +cpuss_interrupts_dw1_28_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm4_fp_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_0_interrupt_i2s_IRQHandler +audioss_0_interrupt_pdm_IRQHandler +audioss_1_interrupt_i2s_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +sdhc_0_interrupt_wakeup_IRQHandler +sdhc_0_interrupt_general_IRQHandler +sdhc_1_interrupt_wakeup_IRQHandler +sdhc_1_interrupt_general_IRQHandler + + B . + ENDP + + ALIGN + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld new file mode 100644 index 0000000000..8f5a345f18 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -0,0 +1,448 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm4_dual.ld +* \version 2.60 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10180000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08080000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x7F800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* Size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00200000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S new file mode 100644 index 0000000000..1ebcac39f8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S @@ -0,0 +1,673 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf new file mode 100644 index 0000000000..019967a0c1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -0,0 +1,274 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm4_dual.icf +* \version 2.60 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10180000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08080000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x7F800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S new file mode 100644 index 0000000000..3257b6f20c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S @@ -0,0 +1,1263 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 + DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 + DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 + DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 + DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt + DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt + DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used + DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK scb_9_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_9_interrupt_IRQHandler + B scb_9_interrupt_IRQHandler + + PUBWEAK scb_10_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_10_interrupt_IRQHandler + B scb_10_interrupt_IRQHandler + + PUBWEAK scb_11_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_11_interrupt_IRQHandler + B scb_11_interrupt_IRQHandler + + PUBWEAK scb_12_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_12_interrupt_IRQHandler + B scb_12_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_0_IRQHandler + B cpuss_interrupts_dmac_0_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_1_IRQHandler + B cpuss_interrupts_dmac_1_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_2_IRQHandler + B cpuss_interrupts_dmac_2_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_3_IRQHandler + B cpuss_interrupts_dmac_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_16_IRQHandler + B cpuss_interrupts_dw0_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_17_IRQHandler + B cpuss_interrupts_dw0_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_18_IRQHandler + B cpuss_interrupts_dw0_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_19_IRQHandler + B cpuss_interrupts_dw0_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_20_IRQHandler + B cpuss_interrupts_dw0_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_21_IRQHandler + B cpuss_interrupts_dw0_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_22_IRQHandler + B cpuss_interrupts_dw0_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_23_IRQHandler + B cpuss_interrupts_dw0_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_24_IRQHandler + B cpuss_interrupts_dw0_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_25_IRQHandler + B cpuss_interrupts_dw0_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_26_IRQHandler + B cpuss_interrupts_dw0_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_27_IRQHandler + B cpuss_interrupts_dw0_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_28_IRQHandler + B cpuss_interrupts_dw0_28_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_16_IRQHandler + B cpuss_interrupts_dw1_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_17_IRQHandler + B cpuss_interrupts_dw1_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_18_IRQHandler + B cpuss_interrupts_dw1_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_19_IRQHandler + B cpuss_interrupts_dw1_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_20_IRQHandler + B cpuss_interrupts_dw1_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_21_IRQHandler + B cpuss_interrupts_dw1_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_22_IRQHandler + B cpuss_interrupts_dw1_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_23_IRQHandler + B cpuss_interrupts_dw1_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_24_IRQHandler + B cpuss_interrupts_dw1_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_25_IRQHandler + B cpuss_interrupts_dw1_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_26_IRQHandler + B cpuss_interrupts_dw1_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_27_IRQHandler + B cpuss_interrupts_dw1_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_28_IRQHandler + B cpuss_interrupts_dw1_28_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_fp_IRQHandler + B cpuss_interrupts_cm4_fp_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_0_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_0_interrupt_i2s_IRQHandler + B audioss_0_interrupt_i2s_IRQHandler + + PUBWEAK audioss_0_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_0_interrupt_pdm_IRQHandler + B audioss_0_interrupt_pdm_IRQHandler + + PUBWEAK audioss_1_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_1_interrupt_i2s_IRQHandler + B audioss_1_interrupt_i2s_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK sdhc_0_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_wakeup_IRQHandler + B sdhc_0_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_0_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_general_IRQHandler + B sdhc_0_interrupt_general_IRQHandler + + PUBWEAK sdhc_1_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_1_interrupt_wakeup_IRQHandler + B sdhc_1_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_1_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_1_interrupt_general_IRQHandler + B sdhc_1_interrupt_general_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c new file mode 100644 index 0000000000..0a18f50a4d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -0,0 +1,552 @@ +/***************************************************************************//** +* \file system_psoc6_cm4.c +* \version 2.60 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + #else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); + #endif /* (__CM0P_PRESENT) */ +#else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#endif /* __CM0P_PRESENT */ + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t fastClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if ((rootPath == 1UL) || (rootPath == 2UL)) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Fast Clock Divider */ + fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + cy_PeriClkFreqHz = pathFreqHz / periClkDiv; + + pathFreqHz = pathFreqHz / fastClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_SysLib_ExitCriticalSection(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm4 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm4(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h new file mode 100644 index 0000000000..423361f58a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h @@ -0,0 +1,680 @@ +/***************************************************************************//** +* \file system_psoc6.h +* \version 2.60 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6_H_ +#define _SYSTEM_PSOC6_H_ + +/** +* \addtogroup group_system_config +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_merge_apps +* - \ref group_system_config_default_handlers +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's +* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this +* by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* ARM MDK\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00024000 +* \endcode +* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10080000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08024000 +* #define RAM_SIZE 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value in the 'xx_cm4_dual.scat' file, +* where 'xx' is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' +* is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the compiler:\n +* \code -D __STACK_SIZE=0x000000400 \endcode +* \code -D __HEAP_SIZE=0x000000100 \endcode +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the assembler:\n +* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode +* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables +* The CM0+ project and linker script build the CM0+ application image. Similarly, +* the CM4 linker script builds the CM4 application image. Each specifies +* locations, sizes, and contents of sections in memory. See +* \ref group_system_config_device_memory_definition for the symbols and default +* values. +* +* The cymcuelftool is invoked by a post-build command. The precise project +* setting is IDE-specific. +* +* The cymcuelftool combines the two executables. The tool examines the +* executables to ensure that memory regions either do not overlap, or contain +* identical bytes (shared). If there are no problems, it creates a new ELF file +* with the merged image, without changing any of the addresses or data. +* +* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is \_IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* The code in these files copies the vector table from Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM MDK +* The linker script file is 'xx_yy.scat', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and +* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_more_information More Information +* Refer to the PDL User Guide for the +* more details. +* +* \section group_system_config_MISRA MISRA Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + +#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) + #include "cyfitter.h" +#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ + + + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + +#if defined (CYDEV_CLK_EXTCLK__HZ) + #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) +#else + /***************************************************************************//** + * External Clock Frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_EXTCLK__HZ) */ + + +#if defined (CYDEV_CLK_ECO__HZ) + #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) +#else + /***************************************************************************//** + * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled + * within PSoC Creator and the clock is enabled in the DWR, the value from DWR + * used. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_ECO__HZ) */ + + +#if defined (CYDEV_CLK_ALTHF__HZ) + #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) +#else + /***************************************************************************//** + * \brief Alternate high frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ +#endif /* (CYDEV_CLK_ALTHF__HZ) */ + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#if !defined (CY_CORTEX_M4_APPL_ADDR) + #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ +#endif /* (CY_CORTEX_M4_APPL_ADDR) */ + + +/***************************************************************************//** +* \brief IPC Semaphores allocation ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ + + +/***************************************************************************//** +* \brief IPC Pipe definitions ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +extern void SystemInit(void); + +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); + +void Cy_SysIpcPipeIsrCm0(void); +void Cy_SysIpcPipeIsrCm4(void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + + +/******************************************************************************* +* IPC Configuration +* ========================= +*******************************************************************************/ +/* IPC CY_PIPE default configuration */ +#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) + +#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ + +#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) + + +/******************************************************************************/ +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) + +#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) + +/******************************************************************************/ + + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + + + +/** \cond INTERNAL */ +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ + +/* BWC defines for functions related to enter/exit critical section */ +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) +#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) + +/** \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC6_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/targets.json b/targets/targets.json index 031ae43f93..02ebdeb554 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9371,6 +9371,55 @@ "network-default-interface-type": "WIFI" } }, + "CYSBSYSKIT_01": { + "inherits": [ + "MCU_PSOC6_M4" + ], + "components_add": [ + "SCL", + "43012", + "CYW43XXX" + ], + "device_has_remove": [ + "ANALOGOUT" + ], + "components_remove": [ + "CM0P_SLEEP" + ], + "extra_labels_add": [ + "PSOC6_02", + "MXCRYPTO_02" + ], + "macros_add": [ + "CY8C624AFNI_D43", + "CYBSP_WIFI_CAPABLE" + ], + "overrides": { + "network-default-interface-type": "WIFI", + "deep-sleep-latency": 0 + }, + "detect_code": [ + "1912" + ], + "macros_remove": [ + "CYBSP_WIFI_CAPABLE", + "MBED_TICKLESS" + ], + "config": { + "np_cloud_disable": { + "help": "Value: Tells the np to connect to cloud or not", + "value": false + }, + "np_wifi_enable": { + "help": "Value: Tells the np to connect to wifi with its network credentials or wait till cp provides network credentials to it", + "value": false + } + }, + "forced_reset_timeout": 5, + "post_binary_hook": { + "function": "PSOC6Code.complete" + } + }, "FUTURE_SEQUANA_M0": { "inherits": ["MCU_PSOC6_M0"], "supported_form_factors": ["ARDUINO"], From fa6bfb26eb4e9741a87f3689bba7eebf5e59b79a Mon Sep 17 00:00:00 2001 From: Ryan Morse Date: Fri, 20 Mar 2020 02:37:01 +0100 Subject: [PATCH 37/49] Backport #12701: Custom BT Firmware for CYW9P62S1_43012EVB_01 --- .../w_bt_firmware_controller.c | 2 + .../w_bt_firmware_controller.c | 4222 +++++++++++++++++ 2 files changed, 4224 insertions(+) create mode 100644 features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/TARGET_CYW9P62S1_43012EVB_01/w_bt_firmware_controller.c diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/COMPONENT_43012/w_bt_firmware_controller.c b/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/COMPONENT_43012/w_bt_firmware_controller.c index 621771321d..577a49f78c 100644 --- a/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/COMPONENT_43012/w_bt_firmware_controller.c +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/COMPONENT_43012/w_bt_firmware_controller.c @@ -2,6 +2,7 @@ /* labelling: appname-(chipname)(stepping)-frequency-(headset GIT SHA)-(generating SDK version)- * Wiced-release.hcd */ +#ifndef TARGET_CYW9P62S1_43012EVB_01 const char brcm_patch_version[] = "CYW43012C0_003.001.015.0128.0000_Generic_UART_37_4MHz_wlcsp_ref3_sLNA"; const uint8_t brcm_patchram_format = 0x01; /* Configuration Data Records (Write_RAM) */ @@ -4061,3 +4062,4 @@ const uint8_t brcm_patchram_buf[] = { }; const int brcm_patch_ram_length = sizeof(brcm_patchram_buf); +#endif diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/TARGET_CYW9P62S1_43012EVB_01/w_bt_firmware_controller.c b/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/TARGET_CYW9P62S1_43012EVB_01/w_bt_firmware_controller.c new file mode 100644 index 0000000000..cfddd7f547 --- /dev/null +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/TARGET_CYW9P62S1_43012EVB_01/w_bt_firmware_controller.c @@ -0,0 +1,4222 @@ +#include + +/* labelling: appname-(chipname)(stepping)-frequency-(headset GIT SHA)-(generating SDK version)- + * Wiced-release.hcd */ +const char brcm_patch_version[] = " CYW43012C0_003.001.015.0144.0000_Generic_UART_37_4MHz_wlbga_ref3_sLNA_USI"; +const uint8_t brcm_patchram_format = 0x01; +/* Configuration Data Records (Write_RAM) */ +const uint8_t brcm_patchram_buf[71349] = { + 76, 252, 70, 0, 0, 34, 0, 66, 82, 67, 77, 99, 102, 103, 83, 0, 0, 0, + 0, 50, 0, 0, 0, 1, 1, 4, 24, 146, 0, 0, 0, 3, 6, 172, 31, 0, 44, 1, + 67, 0, 1, 28, 66, 0, 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 254, 0, 0, 76, 252, 204, 66, 0, 34, 0, + 66, 82, 67, 77, 99, 102, 103, 68, 0, 0, 0, 0, 230, 12, 1, 0, 3, 3, 31, + 67, 89, 87, 52, 51, 48, 49, 50, 67, 48, 32, 85, 65, 82, 84, 32, 87, + 76, 66, 71, 65, 32, 115, 76, 78, 65, 32, 85, 83, 73, 0, 22, 3, 2, 144, + 0, 3, 1, 8, 112, 158, 32, 0, 0, 0, 0, 0, 3, 1, 5, 52, 210, 33, 0, 0, + 3, 1, 5, 208, 196, 32, 0, 1, 3, 1, 5, 209, 196, 32, 0, 1, 0, 7, 4, 31, + 0, 0, 0, 1, 7, 158, 4, 0, 6, 10, 35, 60, 90, 110, 125, 5, 101, 3, 134, + 3, 162, 3, 182, 3, 177, 3, 196, 3, 233, 3, 2, 4, 52, 4, 16, 4, 232, + 3, 242, 3, 21, 4, 71, 4, 26, 4, 66, 4, 94, 4, 112, 4, 124, 4, 117, 4, + 165, 4, 202, 4, 213, 4, 3, 5, 4, 5, 228, 4, 254, 4, 227, 4, 61, 5, 23, + 5, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 100, 4, 17, + 4, 151, 5, 198, 4, 201, 4, 15, 5, 9, 5, 82, 5, 64, 5, 76, 252, 204, + 10, 1, 34, 0, 91, 5, 65, 5, 55, 5, 130, 5, 170, 5, 150, 5, 175, 5, 182, + 5, 236, 5, 234, 5, 29, 6, 185, 5, 192, 5, 236, 5, 4, 6, 40, 6, 190, + 5, 187, 5, 251, 5, 10, 6, 45, 6, 20, 255, 20, 255, 20, 255, 20, 255, + 20, 255, 20, 255, 7, 1, 0, 0, 96, 0, 5, 156, 2, 255, 160, 2, 255, 164, + 2, 255, 168, 2, 255, 172, 2, 255, 0, 0, 96, 0, 5, 200, 2, 255, 204, + 2, 255, 208, 2, 255, 212, 2, 255, 216, 2, 255, 0, 0, 96, 0, 5, 188, + 4, 255, 192, 4, 255, 196, 4, 255, 200, 4, 255, 204, 4, 255, 0, 0, 96, + 0, 5, 132, 11, 255, 120, 8, 255, 72, 11, 255, 248, 4, 255, 252, 4, 255, + 0, 0, 96, 0, 5, 0, 5, 255, 4, 5, 255, 8, 5, 255, 12, 5, 255, 16, 5, + 255, 0, 0, 96, 0, 5, 20, 5, 255, 24, 5, 255, 28, 5, 255, 224, 9, 255, + 128, 10, 255, 0, 0, 96, 0, 5, 228, 4, 255, 232, 4, 255, 236, 4, 255, + 240, 4, 255, 244, 4, 255, 0, 0, 65, 0, 76, 252, 204, 210, 1, 34, 0, + 2, 128, 3, 255, 255, 136, 4, 255, 255, 78, 76, 78, 85, 86, 76, 74, 75, + 80, 83, 124, 124, 124, 124, 124, 0, 10, 34, 101, 101, 101, 101, 101, + 105, 105, 105, 105, 105, 165, 68, 89, 89, 89, 89, 89, 96, 92, 95, 103, + 105, 95, 92, 93, 99, 103, 124, 124, 124, 124, 124, 0, 9, 34, 101, 101, + 101, 101, 101, 87, 87, 87, 87, 87, 165, 68, 90, 90, 90, 90, 90, 118, + 114, 117, 127, 129, 115, 112, 113, 120, 125, 124, 124, 124, 124, 124, + 0, 8, 34, 101, 101, 101, 101, 101, 87, 87, 87, 87, 87, 165, 68, 90, + 90, 90, 90, 90, 143, 138, 142, 154, 156, 142, 139, 140, 149, 155, 124, + 124, 124, 124, 124, 0, 8, 34, 101, 101, 101, 101, 101, 87, 87, 87, 87, + 87, 165, 68, 90, 90, 90, 90, 90, 165, 159, 163, 177, 180, 163, 159, + 160, 170, 177, 124, 124, 124, 124, 124, 0, 7, 34, 101, 101, 101, 101, + 101, 87, 87, 87, 87, 87, 165, 68, 90, 90, 90, 90, 90, 193, 186, 191, + 207, 210, 189, 184, 186, 197, 205, 124, 124, 124, 124, 124, 7, 76, 252, + 204, 154, 2, 34, 0, 6, 82, 105, 105, 105, 105, 105, 105, 105, 105, 105, + 105, 165, 68, 90, 90, 90, 90, 90, 219, 19, 0, 4, 222, 19, 0, 4, 222, + 19, 0, 4, 222, 19, 0, 4, 222, 19, 0, 4, 222, 19, 0, 4, 2, 7, 127, 2, + 6, 5, 197, 3, 192, 3, 202, 3, 217, 3, 222, 3, 46, 4, 41, 4, 46, 4, 91, + 4, 66, 4, 86, 4, 51, 4, 66, 4, 111, 4, 76, 4, 186, 4, 166, 4, 161, 4, + 166, 4, 171, 4, 40, 5, 25, 5, 10, 5, 50, 5, 65, 5, 110, 5, 80, 5, 25, + 5, 110, 5, 85, 5, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, + 1, 0, 0, 0, 96, 0, 5, 156, 2, 255, 160, 2, 255, 164, 2, 255, 168, 2, + 255, 172, 2, 255, 30, 30, 31, 31, 33, 49, 50, 51, 51, 56, 134, 134, + 134, 134, 134, 100, 100, 99, 103, 113, 154, 149, 151, 161, 181, 200, + 197, 202, 219, 218, 2, 7, 127, 0, 6, 5, 197, 3, 192, 3, 202, 3, 217, + 3, 222, 3, 46, 4, 41, 4, 46, 4, 91, 4, 66, 4, 86, 76, 252, 204, 98, + 3, 34, 0, 4, 51, 4, 66, 4, 111, 4, 76, 4, 186, 4, 166, 4, 161, 4, 166, + 4, 171, 4, 40, 5, 25, 5, 10, 5, 50, 5, 65, 5, 110, 5, 80, 5, 25, 5, + 110, 5, 85, 5, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, + 1, 0, 0, 0, 96, 0, 5, 156, 2, 255, 160, 2, 255, 164, 2, 255, 168, 2, + 255, 172, 2, 255, 78, 76, 78, 85, 86, 96, 92, 95, 103, 105, 118, 114, + 117, 127, 129, 143, 138, 142, 154, 156, 165, 159, 163, 177, 180, 193, + 186, 191, 207, 210, 2, 1, 160, 23, 12, 0, 65, 0, 255, 255, 255, 255, + 84, 64, 0, 0, 24, 0, 65, 0, 255, 255, 255, 255, 7, 126, 0, 0, 136, 0, + 65, 0, 255, 255, 255, 255, 0, 0, 0, 0, 192, 0, 65, 0, 255, 255, 255, + 255, 129, 1, 0, 0, 60, 1, 65, 0, 255, 255, 255, 255, 42, 5, 0, 0, 68, + 1, 65, 0, 255, 255, 255, 255, 12, 9, 0, 0, 72, 1, 65, 0, 255, 255, 255, + 255, 46, 3, 0, 0, 96, 1, 65, 0, 255, 255, 255, 255, 10, 76, 252, 204, + 42, 4, 34, 0, 9, 0, 0, 112, 1, 65, 0, 255, 255, 255, 255, 222, 23, 0, + 0, 124, 1, 65, 0, 255, 255, 255, 255, 42, 5, 0, 0, 128, 3, 65, 0, 255, + 255, 255, 255, 222, 19, 0, 0, 132, 3, 65, 0, 255, 255, 255, 255, 215, + 206, 0, 0, 136, 3, 65, 0, 255, 255, 255, 255, 249, 63, 0, 0, 140, 3, + 65, 0, 255, 255, 255, 255, 133, 172, 0, 0, 144, 3, 65, 0, 255, 255, + 255, 255, 93, 28, 0, 0, 232, 3, 65, 0, 255, 255, 255, 255, 28, 0, 0, + 0, 148, 4, 65, 0, 255, 255, 255, 255, 108, 2, 0, 0, 192, 4, 65, 0, 255, + 255, 255, 255, 0, 128, 0, 0, 28, 6, 65, 0, 255, 255, 255, 255, 47, 64, + 0, 0, 32, 6, 65, 0, 255, 255, 255, 255, 37, 64, 0, 0, 36, 6, 65, 0, + 255, 255, 255, 255, 20, 64, 0, 0, 40, 6, 65, 0, 255, 255, 255, 255, + 163, 67, 0, 0, 44, 6, 65, 0, 255, 255, 255, 255, 82, 64, 0, 0, 52, 7, + 65, 0, 255, 255, 255, 255, 33, 98, 0, 0, 240, 7, 65, 0, 255, 76, 252, + 204, 242, 4, 34, 0, 255, 255, 255, 49, 128, 0, 0, 160, 8, 65, 0, 255, + 255, 255, 255, 49, 1, 0, 0, 168, 8, 65, 0, 255, 255, 255, 255, 80, 3, + 0, 0, 164, 8, 65, 0, 255, 255, 255, 255, 83, 1, 0, 0, 160, 8, 65, 0, + 255, 255, 255, 255, 55, 1, 0, 0, 156, 8, 65, 0, 255, 255, 255, 255, + 0, 1, 0, 0, 8, 0, 96, 0, 255, 255, 255, 255, 5, 0, 0, 0, 52, 0, 96, + 0, 255, 255, 255, 255, 15, 0, 0, 0, 36, 1, 96, 0, 255, 255, 255, 255, + 57, 0, 0, 0, 40, 1, 96, 0, 255, 255, 255, 255, 63, 0, 0, 0, 44, 1, 96, + 0, 255, 255, 255, 255, 86, 0, 0, 0, 48, 1, 96, 0, 255, 255, 255, 255, + 32, 0, 0, 0, 80, 1, 96, 0, 255, 255, 255, 255, 1, 0, 0, 0, 52, 1, 96, + 0, 255, 255, 255, 255, 9, 0, 0, 0, 88, 1, 96, 0, 255, 255, 255, 255, + 33, 0, 0, 0, 220, 1, 96, 0, 255, 255, 255, 255, 133, 0, 0, 0, 224, 1, + 96, 0, 255, 255, 255, 255, 37, 0, 0, 0, 228, 76, 252, 204, 186, 5, 34, + 0, 1, 96, 0, 255, 255, 255, 255, 62, 0, 0, 0, 232, 1, 96, 0, 255, 255, + 255, 255, 38, 0, 0, 0, 236, 1, 96, 0, 255, 255, 255, 255, 100, 0, 0, + 0, 244, 1, 96, 0, 255, 255, 255, 255, 156, 0, 0, 0, 156, 2, 96, 0, 255, + 255, 255, 255, 80, 0, 0, 0, 160, 2, 96, 0, 255, 255, 255, 255, 80, 0, + 0, 0, 164, 2, 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 168, 2, 96, 0, + 255, 255, 255, 255, 80, 0, 0, 0, 172, 2, 96, 0, 255, 255, 255, 255, + 80, 0, 0, 0, 200, 2, 96, 0, 255, 255, 255, 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13, 1, 195, 166, 19, 0, 205, 22, 13, 1, 215, 166, 19, 0, + 233, 22, 13, 1, 233, 166, 19, 0, 5, 23, 13, 1, 9, 167, 19, 0, 89, 23, + 13, 1, 43, 167, 19, 0, 117, 23, 13, 1, 75, 167, 19, 0, 29, 64, 4, 2, + 249, 9, 19, 0, 3, 1, 216, 11, 92, 163, 33, 0, 1, 0, 0, 0, 0, 0, 4, 0, + 48, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 76, 252, 204, 138, 7, 35, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 8, 0, 0, 245, 18, 5, 0, 229, 76, 19, 0, 143, 77, 19, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 53, 175, 8, 0, 75, 175, 8, 0, 157, 175, 8, 0, 177, 175, + 8, 0, 201, 175, 8, 0, 169, 176, 8, 0, 241, 176, 8, 0, 31, 177, 8, 0, + 165, 178, 8, 0, 45, 180, 8, 0, 47, 180, 8, 0, 99, 239, 5, 0, 13, 82, + 19, 0, 141, 239, 5, 0, 169, 239, 5, 0, 31, 85, 19, 0, 221, 240, 5, 0, + 29, 241, 5, 0, 99, 242, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 211, 129, 8, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 76, + 252, 204, 82, 8, 35, 0, 0, 0, 17, 79, 19, 0, 188, 188, 188, 188, 67, + 67, 67, 67, 0, 0, 0, 0, 152, 4, 96, 0, 29, 0, 0, 0, 255, 0, 0, 0, 0, + 0, 0, 0, 156, 4, 96, 0, 255, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 175, + 126, 8, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 180, 11, + 96, 0, 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 88, 1, 96, 0, 50, 0, 0, + 0, 255, 0, 0, 0, 0, 0, 0, 0, 84, 1, 96, 0, 4, 0, 0, 0, 255, 0, 0, 0, + 0, 0, 0, 0, 232, 4, 65, 0, 0, 192, 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, + 221, 126, 8, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 11, + 127, 8, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 55, 127, + 8, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 48, 4, 65, 0, + 128, 0, 0, 0, 128, 0, 0, 0, 0, 0, 0, 0, 52, 6, 65, 0, 0, 72, 76, 252, + 204, 26, 9, 35, 0, 0, 0, 255, 255, 0, 0, 0, 0, 0, 0, 195, 125, 8, 0, + 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 188, 1, 65, 0, 0, 3, + 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 252, 2, 96, 0, 13, 0, 0, 0, 255, 0, 0, + 0, 0, 0, 0, 0, 188, 1, 96, 0, 1, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, + 12, 1, 96, 0, 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 147, 127, 8, 0, + 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 199, 127, 8, 0, 188, + 188, 188, 188, 67, 67, 67, 67, 0, 0, 0, 0, 1, 128, 8, 0, 188, 188, 188, + 188, 67, 67, 67, 67, 0, 0, 0, 0, 168, 1, 65, 0, 24, 2, 0, 0, 255, 255, + 0, 0, 0, 0, 0, 0, 217, 124, 8, 0, 188, 188, 188, 188, 67, 67, 67, 67, + 0, 0, 0, 0, 105, 129, 8, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, + 0, 0, 59, 80, 19, 0, 188, 188, 188, 188, 67, 67, 67, 67, 0, 0, 76, 252, + 204, 226, 9, 35, 0, 0, 0, 19, 81, 19, 0, 188, 188, 188, 188, 67, 67, + 67, 67, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 1, 16, 39, 136, 19, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 9, 8, 8, 7, 6, 18, + 17, 4, 189, 10, 23, 16, 4, 191, 9, 28, 14, 4, 194, 8, 33, 12, 4, 198, + 7, 38, 11, 4, 203, 6, 43, 9, 4, 208, 5, 48, 8, 4, 214, 4, 53, 6, 4, + 221, 3, 58, 5, 4, 229, 2, 63, 3, 4, 237, 1, 68, 2, 4, 246, 0, 73, 0, + 4, 0, 0, 78, 254, 3, 11, 255, 83, 253, 3, 22, 254, 88, 251, 3, 34, 253, + 93, 250, 3, 47, 252, 98, 248, 3, 60, 251, 103, 247, 3, 75, 250, 108, + 245, 3, 90, 249, 113, 244, 3, 105, 248, 118, 242, 3, 122, 247, 123, + 241, 3, 139, 246, 128, 239, 3, 157, 245, 133, 238, 3, 175, 244, 25, + 0, 255, 0, 76, 252, 204, 170, 10, 35, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, + 0, 16, 39, 0, 0, 109, 57, 19, 0, 4, 0, 6, 0, 225, 62, 19, 0, 3, 0, 70, + 0, 239, 59, 19, 0, 28, 0, 0, 0, 217, 59, 19, 0, 11, 0, 6, 0, 65, 64, + 19, 0, 3, 0, 8, 0, 187, 61, 19, 0, 67, 0, 0, 0, 253, 61, 19, 0, 9, 0, + 6, 0, 63, 62, 19, 0, 5, 0, 0, 0, 135, 58, 19, 0, 6, 0, 6, 0, 253, 56, + 19, 0, 10, 0, 6, 0, 161, 59, 19, 0, 5, 0, 6, 0, 175, 59, 19, 0, 13, + 0, 6, 0, 225, 113, 19, 0, 5, 0, 6, 0, 25, 114, 19, 0, 3, 0, 8, 0, 107, + 114, 19, 0, 12, 0, 6, 0, 201, 114, 19, 0, 3, 0, 15, 0, 0, 1, 0, 0, 0, + 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 1, 0, 0, 0, 2, 0, 76, 252, 204, 114, 11, 35, 0, 0, 0, 3, 0, 0, + 0, 4, 0, 0, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7, 0, 0, 0, 8, 0, 0, 0, 9, 0, + 0, 0, 10, 0, 0, 0, 11, 0, 0, 0, 12, 0, 0, 0, 13, 0, 0, 0, 14, 0, 0, + 0, 15, 0, 0, 0, 123, 139, 19, 0, 133, 139, 19, 0, 145, 139, 19, 0, 157, + 139, 19, 0, 169, 139, 19, 0, 181, 139, 19, 0, 193, 139, 19, 0, 205, + 139, 19, 0, 217, 139, 19, 0, 229, 139, 19, 0, 241, 139, 19, 0, 253, + 139, 19, 0, 9, 140, 19, 0, 21, 140, 19, 0, 33, 140, 19, 0, 45, 140, + 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 3, 0, 0, 255, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 255, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 136, 19, 0, 0, + 0, 0, 0, 0, 128, 195, 201, 1, 0, 48, 48, 0, 0, 16, 1, 0, 0, 0, 76, 252, + 204, 58, 12, 35, 0, 0, 0, 0, 0, 0, 0, 254, 0, 0, 0, 254, 0, 0, 0, 1, + 0, 4, 25, 4, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 194, 1, 0, 13, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 2, 2, 0, 0, 0, 0, 15, 0, 1, 0, 0, 0, 39, 63, 181, 129, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 100, 7, 0, 36, 67, 0, 0, 0, 0, 0, 0, 0, 1, 6, 10, 0, 4, + 62, 0, 0, 124, 0, 0, 0, 20, 14, 8, 0, 176, 4, 0, 0, 102, 73, 170, 27, + 210, 16, 0, 5, 240, 0, 0, 0, 0, 0, 16, 0, 11, 0, 0, 0, 144, 9, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 76, 252, 58, 2, 13, 35, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 3, 1, 8, 48, 169, 33, 0, 15, 0, 0, 0, 6, 1, 4, 125, 68, 19, + 0, 6, 1, 4, 41, 112, 19, 0, 254, 0, 0, 78, 252, 4, 255, 255, 255, 255 +}; + +const int brcm_patch_ram_length = sizeof(brcm_patchram_buf); From ec898fb1fa079acb9f5e4dbeee2867a671de6d19 Mon Sep 17 00:00:00 2001 From: Jaeden Amero Date: Tue, 7 Apr 2020 09:57:37 +0100 Subject: [PATCH 38/49] tls: Upgrade to Mbed TLS 2.20.0 --- features/mbedtls/VERSION.txt | 2 +- features/mbedtls/importer/Makefile | 4 +- features/mbedtls/inc/mbedtls/check_config.h | 24 + features/mbedtls/inc/mbedtls/config.h | 31 +- features/mbedtls/inc/mbedtls/error.h | 8 +- features/mbedtls/inc/mbedtls/pkcs11.h | 121 +- features/mbedtls/inc/mbedtls/ssl_internal.h | 45 +- features/mbedtls/inc/mbedtls/version.h | 10 +- features/mbedtls/src/Makefile | 12 +- features/mbedtls/src/debug.c | 3 +- features/mbedtls/src/error.c | 14 +- features/mbedtls/src/net_sockets.c | 13 +- features/mbedtls/src/ssl_cli.c | 44 +- features/mbedtls/src/ssl_cookie.c | 5 +- features/mbedtls/src/ssl_msg.c | 5691 ++++++++++++++++++ features/mbedtls/src/ssl_srv.c | 37 +- features/mbedtls/src/ssl_ticket.c | 9 +- features/mbedtls/src/ssl_tls.c | 5732 +------------------ features/mbedtls/src/x509.c | 33 +- features/mbedtls/src/x509_create.c | 11 +- features/mbedtls/src/x509_crl.c | 19 +- features/mbedtls/src/x509_crt.c | 55 +- features/mbedtls/src/x509_csr.c | 11 +- features/mbedtls/src/x509write_crt.c | 35 +- features/mbedtls/src/x509write_csr.c | 32 +- 25 files changed, 6125 insertions(+), 5876 deletions(-) create mode 100644 features/mbedtls/src/ssl_msg.c diff --git a/features/mbedtls/VERSION.txt b/features/mbedtls/VERSION.txt index 25ccba53c2..ac08791e86 100644 --- a/features/mbedtls/VERSION.txt +++ b/features/mbedtls/VERSION.txt @@ -1 +1 @@ -mbedtls-2.20.0d0 +mbedtls-2.21.0 diff --git a/features/mbedtls/importer/Makefile b/features/mbedtls/importer/Makefile index b737e5bb97..eb7cf9372e 100644 --- a/features/mbedtls/importer/Makefile +++ b/features/mbedtls/importer/Makefile @@ -27,8 +27,8 @@ # # Set the mbed TLS release to import (this can/should be edited before import) -MBED_TLS_RELEASE ?= mbedtls-2.20.0d0 -MBED_TLS_REPO_URL ?= git@github.com:ARMmbed/mbedtls-restricted.git +MBED_TLS_RELEASE ?= mbedtls-2.21.0 +MBED_TLS_REPO_URL ?= git@github.com:ARMmbed/mbedtls.git # Translate between mbed TLS namespace and mbed namespace TARGET_PREFIX:=../ diff --git a/features/mbedtls/inc/mbedtls/check_config.h b/features/mbedtls/inc/mbedtls/check_config.h index 7e0e3575c8..46d9117f1e 100644 --- a/features/mbedtls/inc/mbedtls/check_config.h +++ b/features/mbedtls/inc/mbedtls/check_config.h @@ -342,6 +342,14 @@ #error "MBEDTLS_PKCS11_C defined, but not all prerequisites" #endif +#if defined(MBEDTLS_PKCS11_C) +#if defined(MBEDTLS_DEPRECATED_REMOVED) +#error "MBEDTLS_PKCS11_C is deprecated and will be removed in a future version of Mbed TLS" +#elif defined(MBEDTLS_DEPRECATED_WARNING) +#warning "MBEDTLS_PKCS11_C is deprecated and will be removed in a future version of Mbed TLS" +#endif +#endif /* MBEDTLS_PKCS11_C */ + #if defined(MBEDTLS_PLATFORM_EXIT_ALT) && !defined(MBEDTLS_PLATFORM_C) #error "MBEDTLS_PLATFORM_EXIT_ALT defined, but not all prerequisites" #endif @@ -769,6 +777,22 @@ #error "MBEDTLS_HAVE_INT32/MBEDTLS_HAVE_INT64 and MBEDTLS_HAVE_ASM cannot be defined simultaneously" #endif /* (MBEDTLS_HAVE_INT32 || MBEDTLS_HAVE_INT64) && MBEDTLS_HAVE_ASM */ +#if defined(MBEDTLS_SSL_PROTO_SSL3) +#if defined(MBEDTLS_DEPRECATED_REMOVED) +#error "MBEDTLS_SSL_PROTO_SSL3 is deprecated and will be removed in a future version of Mbed TLS" +#elif defined(MBEDTLS_DEPRECATED_WARNING) +#warning "MBEDTLS_SSL_PROTO_SSL3 is deprecated and will be removed in a future version of Mbed TLS" +#endif +#endif /* MBEDTLS_SSL_PROTO_SSL3 */ + +#if defined(MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO) +#if defined(MBEDTLS_DEPRECATED_REMOVED) +#error "MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO is deprecated and will be removed in a future version of Mbed TLS" +#elif defined(MBEDTLS_DEPRECATED_WARNING) +#warning "MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO is deprecated and will be removed in a future version of Mbed TLS" +#endif +#endif /* MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO */ + /* * Avoid warning from -pedantic. This is a convenient place for this * workaround since this is included by every single file before the diff --git a/features/mbedtls/inc/mbedtls/config.h b/features/mbedtls/inc/mbedtls/config.h index e6b459dc11..4a913cfae8 100644 --- a/features/mbedtls/inc/mbedtls/config.h +++ b/features/mbedtls/inc/mbedtls/config.h @@ -249,27 +249,27 @@ /** * \def MBEDTLS_DEPRECATED_WARNING * - * Mark deprecated functions so that they generate a warning if used. - * Functions deprecated in one version will usually be removed in the next - * version. You can enable this to help you prepare the transition to a new - * major version by making sure your code is not using these functions. + * Mark deprecated functions and features so that they generate a warning if + * used. Functionality deprecated in one version will usually be removed in the + * next version. You can enable this to help you prepare the transition to a + * new major version by making sure your code is not using this functionality. * * This only works with GCC and Clang. With other compilers, you may want to * use MBEDTLS_DEPRECATED_REMOVED * - * Uncomment to get warnings on using deprecated functions. + * Uncomment to get warnings on using deprecated functions and features. */ //#define MBEDTLS_DEPRECATED_WARNING /** * \def MBEDTLS_DEPRECATED_REMOVED * - * Remove deprecated functions so that they generate an error if used. - * Functions deprecated in one version will usually be removed in the next - * version. You can enable this to help you prepare the transition to a new - * major version by making sure your code is not using these functions. + * Remove deprecated functions and features so that they generate an error if + * used. Functionality deprecated in one version will usually be removed in the + * next version. You can enable this to help you prepare the transition to a + * new major version by making sure your code is not using this functionality. * - * Uncomment to get errors on using deprecated functions. + * Uncomment to get errors on using deprecated functions and features. */ //#define MBEDTLS_DEPRECATED_REMOVED @@ -1587,6 +1587,9 @@ * Enable support for receiving and parsing SSLv2 Client Hello messages for the * SSL Server module (MBEDTLS_SSL_SRV_C). * + * \deprecated This option is deprecated and will be removed in a future + * version of Mbed TLS. + * * Uncomment this macro to enable support for SSLv2 Client Hello messages. */ //#define MBEDTLS_SSL_SRV_SUPPORT_SSLV2_CLIENT_HELLO @@ -1618,6 +1621,9 @@ * Requires: MBEDTLS_MD5_C * MBEDTLS_SHA1_C * + * \deprecated This option is deprecated and will be removed in a future + * version of Mbed TLS. + * * Comment this macro to disable support for SSL 3.0 */ //#define MBEDTLS_SSL_PROTO_SSL3 @@ -2828,7 +2834,10 @@ /** * \def MBEDTLS_PKCS11_C * - * Enable wrapper for PKCS#11 smartcard support. + * Enable wrapper for PKCS#11 smartcard support via the pkcs11-helper library. + * + * \deprecated This option is deprecated and will be removed in a future + * version of Mbed TLS. * * Module: library/pkcs11.c * Caller: library/pk.c diff --git a/features/mbedtls/inc/mbedtls/error.h b/features/mbedtls/inc/mbedtls/error.h index 06bb1c9cac..82b018813e 100644 --- a/features/mbedtls/inc/mbedtls/error.h +++ b/features/mbedtls/inc/mbedtls/error.h @@ -52,9 +52,10 @@ * For historical reasons, low-level error codes are divided in even and odd, * even codes were assigned first, and -1 is reserved for other errors. * - * Low-level module errors (0x0002-0x007E, 0x0003-0x007F) + * Low-level module errors (0x0002-0x007E, 0x0001-0x007F) * * Module Nr Codes assigned + * ERROR 2 0x006E 0x0001 * MPI 7 0x0002-0x0010 * GCM 3 0x0012-0x0014 0x0013-0x0013 * BLOWFISH 3 0x0016-0x0018 0x0017-0x0017 @@ -86,7 +87,7 @@ * CHACHA20 3 0x0051-0x0055 * POLY1305 3 0x0057-0x005B * CHACHAPOLY 2 0x0054-0x0056 - * PLATFORM 1 0x0070-0x0072 + * PLATFORM 2 0x0070-0x0072 * * High-level module nr (3 bits - 0x0...-0x7...) * Name ID Nr of Errors @@ -112,6 +113,9 @@ extern "C" { #endif +#define MBEDTLS_ERR_ERROR_GENERIC_ERROR -0x0001 /**< Generic error */ +#define MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED -0x006E /**< This is a bug in the library */ + /** * \brief Translate a mbed TLS error code into a string representation, * Result is truncated if necessary and always includes a terminating diff --git a/features/mbedtls/inc/mbedtls/pkcs11.h b/features/mbedtls/inc/mbedtls/pkcs11.h index d9f45db676..cf8d8c4297 100644 --- a/features/mbedtls/inc/mbedtls/pkcs11.h +++ b/features/mbedtls/inc/mbedtls/pkcs11.h @@ -47,6 +47,8 @@ extern "C" { #endif +#if defined(MBEDTLS_DEPRECATED_REMOVED) + /** * Context for PKCS #11 private keys. */ @@ -56,47 +58,71 @@ typedef struct mbedtls_pkcs11_context int len; } mbedtls_pkcs11_context; +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif + /** * Initialize a mbedtls_pkcs11_context. * (Just making memory references valid.) + * + * \deprecated This function is deprecated and will be removed in a + * future version of the library. */ -void mbedtls_pkcs11_init( mbedtls_pkcs11_context *ctx ); +MBEDTLS_DEPRECATED void mbedtls_pkcs11_init( mbedtls_pkcs11_context *ctx ); /** * Fill in a mbed TLS certificate, based on the given PKCS11 helper certificate. * + * \deprecated This function is deprecated and will be removed in a + * future version of the library. + * * \param cert X.509 certificate to fill * \param pkcs11h_cert PKCS #11 helper certificate * * \return 0 on success. */ -int mbedtls_pkcs11_x509_cert_bind( mbedtls_x509_crt *cert, pkcs11h_certificate_t pkcs11h_cert ); +MBEDTLS_DEPRECATED int mbedtls_pkcs11_x509_cert_bind( mbedtls_x509_crt *cert, + pkcs11h_certificate_t pkcs11h_cert ); /** * Set up a mbedtls_pkcs11_context storing the given certificate. Note that the * mbedtls_pkcs11_context will take over control of the certificate, freeing it when * done. * + * \deprecated This function is deprecated and will be removed in a + * future version of the library. + * * \param priv_key Private key structure to fill. * \param pkcs11_cert PKCS #11 helper certificate * * \return 0 on success */ -int mbedtls_pkcs11_priv_key_bind( mbedtls_pkcs11_context *priv_key, - pkcs11h_certificate_t pkcs11_cert ); +MBEDTLS_DEPRECATED int mbedtls_pkcs11_priv_key_bind( + mbedtls_pkcs11_context *priv_key, + pkcs11h_certificate_t pkcs11_cert ); /** * Free the contents of the given private key context. Note that the structure * itself is not freed. * + * \deprecated This function is deprecated and will be removed in a + * future version of the library. + * * \param priv_key Private key structure to cleanup */ -void mbedtls_pkcs11_priv_key_free( mbedtls_pkcs11_context *priv_key ); +MBEDTLS_DEPRECATED void mbedtls_pkcs11_priv_key_free( + mbedtls_pkcs11_context *priv_key ); /** * \brief Do an RSA private key decrypt, then remove the message * padding * + * \deprecated This function is deprecated and will be removed in a future + * version of the library. + * * \param ctx PKCS #11 context * \param mode must be MBEDTLS_RSA_PRIVATE, for compatibility with rsa.c's signature * \param input buffer holding the encrypted data @@ -110,15 +136,18 @@ void mbedtls_pkcs11_priv_key_free( mbedtls_pkcs11_context *priv_key ); * of ctx->N (eg. 128 bytes if RSA-1024 is used) otherwise * an error is thrown. */ -int mbedtls_pkcs11_decrypt( mbedtls_pkcs11_context *ctx, - int mode, size_t *olen, - const unsigned char *input, - unsigned char *output, - size_t output_max_len ); +MBEDTLS_DEPRECATED int mbedtls_pkcs11_decrypt( mbedtls_pkcs11_context *ctx, + int mode, size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len ); /** * \brief Do a private RSA to sign a message digest * + * \deprecated This function is deprecated and will be removed in a future + * version of the library. + * * \param ctx PKCS #11 context * \param mode must be MBEDTLS_RSA_PRIVATE, for compatibility with rsa.c's signature * \param md_alg a MBEDTLS_MD_XXX (use MBEDTLS_MD_NONE for signing raw data) @@ -132,28 +161,58 @@ int mbedtls_pkcs11_decrypt( mbedtls_pkcs11_context *ctx, * \note The "sig" buffer must be as large as the size * of ctx->N (eg. 128 bytes if RSA-1024 is used). */ -int mbedtls_pkcs11_sign( mbedtls_pkcs11_context *ctx, - int mode, - mbedtls_md_type_t md_alg, - unsigned int hashlen, - const unsigned char *hash, - unsigned char *sig ); +MBEDTLS_DEPRECATED int mbedtls_pkcs11_sign( mbedtls_pkcs11_context *ctx, + int mode, + mbedtls_md_type_t md_alg, + unsigned int hashlen, + const unsigned char *hash, + unsigned char *sig ); /** * SSL/TLS wrappers for PKCS#11 functions + * + * \deprecated This function is deprecated and will be removed in a future + * version of the library. */ -static inline int mbedtls_ssl_pkcs11_decrypt( void *ctx, int mode, size_t *olen, - const unsigned char *input, unsigned char *output, - size_t output_max_len ) +MBEDTLS_DEPRECATED static inline int mbedtls_ssl_pkcs11_decrypt( void *ctx, + int mode, size_t *olen, + const unsigned char *input, unsigned char *output, + size_t output_max_len ) { return mbedtls_pkcs11_decrypt( (mbedtls_pkcs11_context *) ctx, mode, olen, input, output, output_max_len ); } -static inline int mbedtls_ssl_pkcs11_sign( void *ctx, - int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, - int mode, mbedtls_md_type_t md_alg, unsigned int hashlen, - const unsigned char *hash, unsigned char *sig ) +/** + * \brief This function signs a message digest using RSA. + * + * \deprecated This function is deprecated and will be removed in a future + * version of the library. + * + * \param ctx The PKCS #11 context. + * \param f_rng The RNG function. This parameter is unused. + * \param p_rng The RNG context. This parameter is unused. + * \param mode The operation to run. This must be set to + * MBEDTLS_RSA_PRIVATE, for compatibility with rsa.c's + * signature. + * \param md_alg The message digest algorithm. One of the MBEDTLS_MD_XXX + * must be passed to this function and MBEDTLS_MD_NONE can be + * used for signing raw data. + * \param hashlen The message digest length (for MBEDTLS_MD_NONE only). + * \param hash The buffer holding the message digest. + * \param sig The buffer that will hold the ciphertext. + * + * \return \c 0 if the signing operation was successful. + * \return A non-zero error code on failure. + * + * \note The \p sig buffer must be as large as the size of + * ctx->N. For example, 128 bytes if RSA-1024 is + * used. + */ +MBEDTLS_DEPRECATED static inline int mbedtls_ssl_pkcs11_sign( void *ctx, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + int mode, mbedtls_md_type_t md_alg, unsigned int hashlen, + const unsigned char *hash, unsigned char *sig ) { ((void) f_rng); ((void) p_rng); @@ -161,11 +220,25 @@ static inline int mbedtls_ssl_pkcs11_sign( void *ctx, hashlen, hash, sig ); } -static inline size_t mbedtls_ssl_pkcs11_key_len( void *ctx ) +/** + * This function gets the length of the private key. + * + * \deprecated This function is deprecated and will be removed in a future + * version of the library. + * + * \param ctx The PKCS #11 context. + * + * \return The length of the private key. + */ +MBEDTLS_DEPRECATED static inline size_t mbedtls_ssl_pkcs11_key_len( void *ctx ) { return ( (mbedtls_pkcs11_context *) ctx )->len; } +#undef MBEDTLS_DEPRECATED + +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + #ifdef __cplusplus } #endif diff --git a/features/mbedtls/inc/mbedtls/ssl_internal.h b/features/mbedtls/inc/mbedtls/ssl_internal.h index f703da99b4..6332d148f6 100644 --- a/features/mbedtls/inc/mbedtls/ssl_internal.h +++ b/features/mbedtls/inc/mbedtls/ssl_internal.h @@ -319,7 +319,8 @@ struct mbedtls_ssl_handshake_params mbedtls_ecdh_context ecdh_ctx; /*!< ECDH key exchange */ #if defined(MBEDTLS_USE_PSA_CRYPTO) - psa_ecc_curve_t ecdh_psa_curve; + psa_key_type_t ecdh_psa_type; + uint16_t ecdh_bits; psa_key_handle_t ecdh_psa_privkey; unsigned char ecdh_psa_peerkey[MBEDTLS_PSA_MAX_EC_PUBKEY_LENGTH]; size_t ecdh_psa_peerkey_len; @@ -1062,4 +1063,46 @@ int mbedtls_ssl_decrypt_buf( mbedtls_ssl_context const *ssl, mbedtls_ssl_transform *transform, mbedtls_record *rec ); +/* Length of the "epoch" field in the record header */ +static inline size_t mbedtls_ssl_ep_len( const mbedtls_ssl_context *ssl ) +{ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + return( 2 ); +#else + ((void) ssl); +#endif + return( 0 ); +} + +#if defined(MBEDTLS_SSL_PROTO_DTLS) +int mbedtls_ssl_resend_hello_request( mbedtls_ssl_context *ssl ); +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +void mbedtls_ssl_set_timer( mbedtls_ssl_context *ssl, uint32_t millisecs ); +int mbedtls_ssl_check_timer( mbedtls_ssl_context *ssl ); + +void mbedtls_ssl_reset_in_out_pointers( mbedtls_ssl_context *ssl ); +void mbedtls_ssl_update_out_pointers( mbedtls_ssl_context *ssl, + mbedtls_ssl_transform *transform ); +void mbedtls_ssl_update_in_pointers( mbedtls_ssl_context *ssl ); + +int mbedtls_ssl_session_reset_int( mbedtls_ssl_context *ssl, int partial ); + +#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) +void mbedtls_ssl_dtls_replay_reset( mbedtls_ssl_context *ssl ); +#endif + +void mbedtls_ssl_handshake_wrapup_free_hs_transform( mbedtls_ssl_context *ssl ); + +#if defined(MBEDTLS_SSL_RENEGOTIATION) +int mbedtls_ssl_start_renegotiation( mbedtls_ssl_context *ssl ); +#endif /* MBEDTLS_SSL_RENEGOTIATION */ + +#if defined(MBEDTLS_SSL_PROTO_DTLS) +size_t mbedtls_ssl_get_current_mtu( const mbedtls_ssl_context *ssl ); +void mbedtls_ssl_buffering_free( mbedtls_ssl_context *ssl ); +void mbedtls_ssl_flight_free( mbedtls_ssl_flight_item *flight ); +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + #endif /* ssl_internal.h */ diff --git a/features/mbedtls/inc/mbedtls/version.h b/features/mbedtls/inc/mbedtls/version.h index ae694eeda2..35af4cc432 100644 --- a/features/mbedtls/inc/mbedtls/version.h +++ b/features/mbedtls/inc/mbedtls/version.h @@ -39,17 +39,17 @@ * Major, Minor, Patchlevel */ #define MBEDTLS_VERSION_MAJOR 2 -#define MBEDTLS_VERSION_MINOR 19 -#define MBEDTLS_VERSION_PATCH 1 +#define MBEDTLS_VERSION_MINOR 21 +#define MBEDTLS_VERSION_PATCH 0 /** * The single version number has the following structure: * MMNNPP00 * Major version | Minor version | Patch version */ -#define MBEDTLS_VERSION_NUMBER 0x02130100 -#define MBEDTLS_VERSION_STRING "2.19.1" -#define MBEDTLS_VERSION_STRING_FULL "mbed TLS 2.19.1" +#define MBEDTLS_VERSION_NUMBER 0x02150000 +#define MBEDTLS_VERSION_STRING "2.21.0" +#define MBEDTLS_VERSION_STRING_FULL "mbed TLS 2.21.0" #if defined(MBEDTLS_VERSION_C) diff --git a/features/mbedtls/src/Makefile b/features/mbedtls/src/Makefile index 501421fb64..6debdfd93d 100644 --- a/features/mbedtls/src/Makefile +++ b/features/mbedtls/src/Makefile @@ -37,7 +37,7 @@ endif SOEXT_TLS=so.13 SOEXT_X509=so.1 -SOEXT_CRYPTO=so.3 +SOEXT_CRYPTO=so.4 # Set AR_DASH= (empty string) to use an ar implementation that does not accept # the - prefix for command line options (e.g. llvm-ar) @@ -77,6 +77,7 @@ OBJS_X509= certs.o pkcs11.o x509.o \ OBJS_TLS= debug.o net_sockets.o \ ssl_cache.o ssl_ciphersuites.o \ ssl_cli.o ssl_cookie.o \ + ssl_msg.o \ ssl_srv.o ssl_ticket.o \ ssl_tls.o @@ -146,17 +147,22 @@ libmbedx509.so: libmbedx509.$(SOEXT_X509) echo " LN $@ -> $<" ln -sf $< $@ -libmbedx509.dylib: $(OBJS_X509) libmbedcrypto.dylib +libmbedx509.dylib: $(OBJS_X509) $(CRYPTO)libmbedcrypto.dylib echo " LD $@" $(CC) -dynamiclib -L. -lmbedcrypto $(LOCAL_LDFLAGS) $(LDFLAGS) -o $@ $(OBJS_X509) -libmbedx509.dll: $(OBJS_X509) libmbedcrypto.dll +libmbedx509.dll: $(OBJS_X509) $(CRYPTO)libmbedcrypto.dll echo " LD $@" $(CC) -shared -Wl,-soname,$@ -Wl,--out-implib,$@.a -o $@ $(OBJS_X509) -lws2_32 -lwinmm -lgdi32 -L. -lmbedcrypto -static-libgcc $(LOCAL_LDFLAGS) $(LDFLAGS) libmbedcrypto.%: $(MAKE) CRYPTO_INCLUDES:="-I../../include -I../include" -C ../crypto/library $@ +libmbedcrypto.$(DLEXT): $(CRYPTO)libmbedcrypto.$(DLEXT) + +$(CRYPTO)libmbedcrypto.$(DLEXT): | libmbedcrypto.a + $(MAKE) CRYPTO_INCLUDES:="-I../../include -I../include" -C ../crypto/library libmbedcrypto.$(DLEXT) + .c.o: echo " CC $<" $(CC) $(LOCAL_CFLAGS) $(CFLAGS) -o $@ -c $< diff --git a/features/mbedtls/src/debug.c b/features/mbedtls/src/debug.c index 0c46c0690d..ae78a697a4 100644 --- a/features/mbedtls/src/debug.c +++ b/features/mbedtls/src/debug.c @@ -39,6 +39,7 @@ #endif #include "mbedtls/debug.h" +#include "mbedtls/error.h" #include #include @@ -85,7 +86,7 @@ void mbedtls_debug_print_msg( const mbedtls_ssl_context *ssl, int level, { va_list argp; char str[DEBUG_BUF_SIZE]; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( NULL == ssl || NULL == ssl->conf || diff --git a/features/mbedtls/src/error.c b/features/mbedtls/src/error.c index d8b5780483..c451f4ddff 100644 --- a/features/mbedtls/src/error.c +++ b/features/mbedtls/src/error.c @@ -25,8 +25,7 @@ #include MBEDTLS_CONFIG_FILE #endif -#if defined(MBEDTLS_ERROR_C) || defined(MBEDTLS_ERROR_STRERROR_DUMMY) -#include "mbedtls/error.h" +#if defined(MBEDTLS_ERROR_STRERROR_DUMMY) #include #endif @@ -109,6 +108,10 @@ #include "mbedtls/entropy.h" #endif +#if defined(MBEDTLS_ERROR_C) +#include "mbedtls/error.h" +#endif + #if defined(MBEDTLS_GCM_C) #include "mbedtls/gcm.h" #endif @@ -754,6 +757,13 @@ void mbedtls_strerror( int ret, char *buf, size_t buflen ) mbedtls_snprintf( buf, buflen, "ENTROPY - Read/write error in file" ); #endif /* MBEDTLS_ENTROPY_C */ +#if defined(MBEDTLS_ERROR_C) + if( use_ret == -(MBEDTLS_ERR_ERROR_GENERIC_ERROR) ) + mbedtls_snprintf( buf, buflen, "ERROR - Generic error" ); + if( use_ret == -(MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED) ) + mbedtls_snprintf( buf, buflen, "ERROR - This is a bug in the library" ); +#endif /* MBEDTLS_ERROR_C */ + #if defined(MBEDTLS_GCM_C) if( use_ret == -(MBEDTLS_ERR_GCM_AUTH_FAILED) ) mbedtls_snprintf( buf, buflen, "GCM - Authenticated decryption failed" ); diff --git a/features/mbedtls/src/net_sockets.c b/features/mbedtls/src/net_sockets.c index c7b358d057..dbde510db8 100644 --- a/features/mbedtls/src/net_sockets.c +++ b/features/mbedtls/src/net_sockets.c @@ -45,6 +45,7 @@ #endif #include "mbedtls/net_sockets.h" +#include "mbedtls/error.h" #include @@ -147,7 +148,7 @@ void mbedtls_net_init( mbedtls_net_context *ctx ) int mbedtls_net_connect( mbedtls_net_context *ctx, const char *host, const char *port, int proto ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; struct addrinfo hints, *addr_list, *cur; if( ( ret = net_prepare() ) != 0 ) @@ -313,7 +314,7 @@ int mbedtls_net_accept( mbedtls_net_context *bind_ctx, mbedtls_net_context *client_ctx, void *client_ip, size_t buf_size, size_t *ip_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; int type; struct sockaddr_storage client_addr; @@ -455,7 +456,7 @@ int mbedtls_net_set_nonblock( mbedtls_net_context *ctx ) int mbedtls_net_poll( mbedtls_net_context *ctx, uint32_t rw, uint32_t timeout ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; struct timeval tv; fd_set read_fds; @@ -540,7 +541,7 @@ void mbedtls_net_usleep( unsigned long usec ) */ int mbedtls_net_recv( void *ctx, unsigned char *buf, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; int fd = ((mbedtls_net_context *) ctx)->fd; if( fd < 0 ) @@ -577,7 +578,7 @@ int mbedtls_net_recv( void *ctx, unsigned char *buf, size_t len ) int mbedtls_net_recv_timeout( void *ctx, unsigned char *buf, size_t len, uint32_t timeout ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; struct timeval tv; fd_set read_fds; int fd = ((mbedtls_net_context *) ctx)->fd; @@ -620,7 +621,7 @@ int mbedtls_net_recv_timeout( void *ctx, unsigned char *buf, */ int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; int fd = ((mbedtls_net_context *) ctx)->fd; if( fd < 0 ) diff --git a/features/mbedtls/src/ssl_cli.c b/features/mbedtls/src/ssl_cli.c index 57e5d8ab97..0f6a26b184 100644 --- a/features/mbedtls/src/ssl_cli.c +++ b/features/mbedtls/src/ssl_cli.c @@ -35,9 +35,10 @@ #define mbedtls_free free #endif -#include "mbedtls/debug.h" #include "mbedtls/ssl.h" #include "mbedtls/ssl_internal.h" +#include "mbedtls/debug.h" +#include "mbedtls/error.h" #if defined(MBEDTLS_USE_PSA_CRYPTO) #include "mbedtls/psa_util.h" @@ -402,7 +403,7 @@ static void ssl_write_ecjpake_kkpp_ext( mbedtls_ssl_context *ssl, unsigned char *buf, size_t *olen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *p = buf; const unsigned char *end = ssl->out_msg + MBEDTLS_SSL_OUT_CONTENT_LEN; size_t kkpp_len; @@ -766,7 +767,7 @@ static void ssl_write_alpn_ext( mbedtls_ssl_context *ssl, */ static int ssl_generate_random( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *p = ssl->handshake->randbytes; #if defined(MBEDTLS_HAVE_TIME) mbedtls_time_t t; @@ -858,7 +859,7 @@ static int ssl_validate_ciphersuite( const mbedtls_ssl_ciphersuite_t * suite_inf static int ssl_write_client_hello( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i, n, olen, ext_len = 0; unsigned char *buf; unsigned char *p, *q; @@ -1470,7 +1471,7 @@ static int ssl_parse_ecjpake_kkpp( mbedtls_ssl_context *ssl, const unsigned char *buf, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ssl->handshake->ciphersuite_info->key_exchange != MBEDTLS_KEY_EXCHANGE_ECJPAKE ) @@ -2243,6 +2244,7 @@ static int ssl_parse_server_ecdh_params_psa( mbedtls_ssl_context *ssl, unsigned char *end ) { uint16_t tls_id; + size_t ecdh_bits = 0; uint8_t ecpoint_len; mbedtls_ssl_handshake_params *handshake = ssl->handshake; @@ -2263,11 +2265,14 @@ static int ssl_parse_server_ecdh_params_psa( mbedtls_ssl_context *ssl, tls_id |= *(*p)++; /* Convert EC group to PSA key type. */ - if( ( handshake->ecdh_psa_curve = - mbedtls_psa_parse_tls_ecc_group( tls_id ) ) == 0 ) + if( ( handshake->ecdh_psa_type = + mbedtls_psa_parse_tls_ecc_group( tls_id, &ecdh_bits ) ) == 0 ) { return( MBEDTLS_ERR_SSL_BAD_HS_SERVER_KEY_EXCHANGE ); } + if( ecdh_bits > 0xffff ) + return( MBEDTLS_ERR_SSL_BAD_HS_SERVER_KEY_EXCHANGE ); + handshake->ecdh_bits = (uint16_t) ecdh_bits; /* * Put peer's ECDH public key in the format understood by PSA. @@ -2277,7 +2282,7 @@ static int ssl_parse_server_ecdh_params_psa( mbedtls_ssl_context *ssl, if( (size_t)( end - *p ) < ecpoint_len ) return( MBEDTLS_ERR_SSL_BAD_HS_SERVER_KEY_EXCHANGE ); - if( mbedtls_psa_tls_ecpoint_to_psa_ec( handshake->ecdh_psa_curve, + if( mbedtls_psa_tls_ecpoint_to_psa_ec( *p, ecpoint_len, handshake->ecdh_psa_peerkey, sizeof( handshake->ecdh_psa_peerkey ), @@ -2384,7 +2389,7 @@ static int ssl_write_encrypted_pms( mbedtls_ssl_context *ssl, size_t offset, size_t *olen, size_t pms_offset ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len_bytes = ssl->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 ? 0 : 2; unsigned char *p = ssl->handshake->premaster + pms_offset; mbedtls_pk_context * peer_pk; @@ -2531,7 +2536,7 @@ static int ssl_parse_signature_algorithm( mbedtls_ssl_context *ssl, defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) static int ssl_get_ecdh_params_from_cert( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const mbedtls_ecp_keypair *peer_key; mbedtls_pk_context * peer_pk; @@ -2582,7 +2587,7 @@ static int ssl_get_ecdh_params_from_cert( mbedtls_ssl_context *ssl ) static int ssl_parse_server_key_exchange( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const mbedtls_ssl_ciphersuite_t *ciphersuite_info = ssl->handshake->ciphersuite_info; unsigned char *p = NULL, *end = NULL; @@ -2971,7 +2976,7 @@ static int ssl_parse_certificate_request( mbedtls_ssl_context *ssl ) #else /* MBEDTLS_KEY_EXCHANGE__CERT_REQ_ALLOWED__ENABLED */ static int ssl_parse_certificate_request( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *buf; size_t n = 0; size_t cert_type_len = 0, dn_len = 0; @@ -3135,7 +3140,7 @@ exit: static int ssl_parse_server_hello_done( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> parse server hello done" ) ); @@ -3174,7 +3179,7 @@ static int ssl_parse_server_hello_done( mbedtls_ssl_context *ssl ) static int ssl_write_client_key_exchange( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t header_len; size_t content_len; @@ -3256,11 +3261,8 @@ static int ssl_write_client_key_exchange( mbedtls_ssl_context *ssl ) key_attributes = psa_key_attributes_init(); psa_set_key_usage_flags( &key_attributes, PSA_KEY_USAGE_DERIVE ); psa_set_key_algorithm( &key_attributes, PSA_ALG_ECDH ); - psa_set_key_type( &key_attributes, - PSA_KEY_TYPE_ECC_KEY_PAIR( handshake->ecdh_psa_curve ) - ); - psa_set_key_bits( &key_attributes, - PSA_ECC_CURVE_BITS( handshake->ecdh_psa_curve ) ); + psa_set_key_type( &key_attributes, handshake->ecdh_psa_type ); + psa_set_key_bits( &key_attributes, handshake->ecdh_bits ); /* Generate ECDH private key. */ status = psa_generate_key( &key_attributes, @@ -3595,7 +3597,7 @@ static int ssl_write_certificate_verify( mbedtls_ssl_context *ssl ) { const mbedtls_ssl_ciphersuite_t *ciphersuite_info = ssl->handshake->ciphersuite_info; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write certificate verify" ) ); @@ -3790,7 +3792,7 @@ sign: #if defined(MBEDTLS_SSL_SESSION_TICKETS) static int ssl_parse_new_session_ticket( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; uint32_t lifetime; size_t ticket_len; unsigned char *ticket; diff --git a/features/mbedtls/src/ssl_cookie.c b/features/mbedtls/src/ssl_cookie.c index 56e9bdd2bf..4bf9058af4 100644 --- a/features/mbedtls/src/ssl_cookie.c +++ b/features/mbedtls/src/ssl_cookie.c @@ -40,6 +40,7 @@ #include "mbedtls/ssl_cookie.h" #include "mbedtls/ssl_internal.h" +#include "mbedtls/error.h" #include "mbedtls/platform_util.h" #include @@ -104,7 +105,7 @@ int mbedtls_ssl_cookie_setup( mbedtls_ssl_cookie_ctx *ctx, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char key[COOKIE_MD_OUTLEN]; if( ( ret = f_rng( p_rng, key, sizeof( key ) ) ) != 0 ) @@ -157,7 +158,7 @@ int mbedtls_ssl_cookie_write( void *p_ctx, unsigned char **p, unsigned char *end, const unsigned char *cli_id, size_t cli_id_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ssl_cookie_ctx *ctx = (mbedtls_ssl_cookie_ctx *) p_ctx; unsigned long t; diff --git a/features/mbedtls/src/ssl_msg.c b/features/mbedtls/src/ssl_msg.c new file mode 100644 index 0000000000..9c2d615095 --- /dev/null +++ b/features/mbedtls/src/ssl_msg.c @@ -0,0 +1,5691 @@ +/* + * Generic SSL/TLS messaging layer functions + * (record layer + retransmission state machine) + * + * Copyright (C) 2006-2020, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ +/* + * The SSL 3.0 specification was drafted by Netscape in 1996, + * and became an IETF standard in 1999. + * + * http://wp.netscape.com/eng/ssl3/ + * http://www.ietf.org/rfc/rfc2246.txt + * http://www.ietf.org/rfc/rfc4346.txt + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_SSL_TLS_C) + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#include "mbedtls/ssl.h" +#include "mbedtls/ssl_internal.h" +#include "mbedtls/debug.h" +#include "mbedtls/error.h" +#include "mbedtls/platform_util.h" +#include "mbedtls/version.h" + +#include + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +#include "mbedtls/psa_util.h" +#include "psa/crypto.h" +#endif + +#if defined(MBEDTLS_X509_CRT_PARSE_C) +#include "mbedtls/oid.h" +#endif + +static uint32_t ssl_get_hs_total_len( mbedtls_ssl_context const *ssl ); + +/* + * Start a timer. + * Passing millisecs = 0 cancels a running timer. + */ +void mbedtls_ssl_set_timer( mbedtls_ssl_context *ssl, uint32_t millisecs ) +{ + if( ssl->f_set_timer == NULL ) + return; + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "set_timer to %d ms", (int) millisecs ) ); + ssl->f_set_timer( ssl->p_timer, millisecs / 4, millisecs ); +} + +/* + * Return -1 is timer is expired, 0 if it isn't. + */ +int mbedtls_ssl_check_timer( mbedtls_ssl_context *ssl ) +{ + if( ssl->f_get_timer == NULL ) + return( 0 ); + + if( ssl->f_get_timer( ssl->p_timer ) == 2 ) + { + MBEDTLS_SSL_DEBUG_MSG( 3, ( "timer expired" ) ); + return( -1 ); + } + + return( 0 ); +} + +#if defined(MBEDTLS_SSL_RECORD_CHECKING) +static int ssl_parse_record_header( mbedtls_ssl_context const *ssl, + unsigned char *buf, + size_t len, + mbedtls_record *rec ); + +int mbedtls_ssl_check_record( mbedtls_ssl_context const *ssl, + unsigned char *buf, + size_t buflen ) +{ + int ret = 0; + MBEDTLS_SSL_DEBUG_MSG( 1, ( "=> mbedtls_ssl_check_record" ) ); + MBEDTLS_SSL_DEBUG_BUF( 3, "record buffer", buf, buflen ); + + /* We don't support record checking in TLS because + * (a) there doesn't seem to be a usecase for it, and + * (b) In SSLv3 and TLS 1.0, CBC record decryption has state + * and we'd need to backup the transform here. + */ + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_STREAM ) + { + ret = MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE; + goto exit; + } +#if defined(MBEDTLS_SSL_PROTO_DTLS) + else + { + mbedtls_record rec; + + ret = ssl_parse_record_header( ssl, buf, buflen, &rec ); + if( ret != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 3, "ssl_parse_record_header", ret ); + goto exit; + } + + if( ssl->transform_in != NULL ) + { + ret = mbedtls_ssl_decrypt_buf( ssl, ssl->transform_in, &rec ); + if( ret != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 3, "mbedtls_ssl_decrypt_buf", ret ); + goto exit; + } + } + } +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +exit: + /* On success, we have decrypted the buffer in-place, so make + * sure we don't leak any plaintext data. */ + mbedtls_platform_zeroize( buf, buflen ); + + /* For the purpose of this API, treat messages with unexpected CID + * as well as such from future epochs as unexpected. */ + if( ret == MBEDTLS_ERR_SSL_UNEXPECTED_CID || + ret == MBEDTLS_ERR_SSL_EARLY_MESSAGE ) + { + ret = MBEDTLS_ERR_SSL_UNEXPECTED_RECORD; + } + + MBEDTLS_SSL_DEBUG_MSG( 1, ( "<= mbedtls_ssl_check_record" ) ); + return( ret ); +} +#endif /* MBEDTLS_SSL_RECORD_CHECKING */ + +#define SSL_DONT_FORCE_FLUSH 0 +#define SSL_FORCE_FLUSH 1 + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + +/* Forward declarations for functions related to message buffering. */ +static void ssl_buffering_free_slot( mbedtls_ssl_context *ssl, + uint8_t slot ); +static void ssl_free_buffered_record( mbedtls_ssl_context *ssl ); +static int ssl_load_buffered_message( mbedtls_ssl_context *ssl ); +static int ssl_load_buffered_record( mbedtls_ssl_context *ssl ); +static int ssl_buffer_message( mbedtls_ssl_context *ssl ); +static int ssl_buffer_future_record( mbedtls_ssl_context *ssl, + mbedtls_record const *rec ); +static int ssl_next_record_is_in_datagram( mbedtls_ssl_context *ssl ); + +static size_t ssl_get_maximum_datagram_size( mbedtls_ssl_context const *ssl ) +{ + size_t mtu = mbedtls_ssl_get_current_mtu( ssl ); + + if( mtu != 0 && mtu < MBEDTLS_SSL_OUT_BUFFER_LEN ) + return( mtu ); + + return( MBEDTLS_SSL_OUT_BUFFER_LEN ); +} + +static int ssl_get_remaining_space_in_datagram( mbedtls_ssl_context const *ssl ) +{ + size_t const bytes_written = ssl->out_left; + size_t const mtu = ssl_get_maximum_datagram_size( ssl ); + + /* Double-check that the write-index hasn't gone + * past what we can transmit in a single datagram. */ + if( bytes_written > mtu ) + { + /* Should never happen... */ + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + return( (int) ( mtu - bytes_written ) ); +} + +static int ssl_get_remaining_payload_in_datagram( mbedtls_ssl_context const *ssl ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t remaining, expansion; + size_t max_len = MBEDTLS_SSL_OUT_CONTENT_LEN; + +#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) + const size_t mfl = mbedtls_ssl_get_max_frag_len( ssl ); + + if( max_len > mfl ) + max_len = mfl; + + /* By the standard (RFC 6066 Sect. 4), the MFL extension + * only limits the maximum record payload size, so in theory + * we would be allowed to pack multiple records of payload size + * MFL into a single datagram. However, this would mean that there's + * no way to explicitly communicate MTU restrictions to the peer. + * + * The following reduction of max_len makes sure that we never + * write datagrams larger than MFL + Record Expansion Overhead. + */ + if( max_len <= ssl->out_left ) + return( 0 ); + + max_len -= ssl->out_left; +#endif + + ret = ssl_get_remaining_space_in_datagram( ssl ); + if( ret < 0 ) + return( ret ); + remaining = (size_t) ret; + + ret = mbedtls_ssl_get_record_expansion( ssl ); + if( ret < 0 ) + return( ret ); + expansion = (size_t) ret; + + if( remaining <= expansion ) + return( 0 ); + + remaining -= expansion; + if( remaining >= max_len ) + remaining = max_len; + + return( (int) remaining ); +} + +/* + * Double the retransmit timeout value, within the allowed range, + * returning -1 if the maximum value has already been reached. + */ +static int ssl_double_retransmit_timeout( mbedtls_ssl_context *ssl ) +{ + uint32_t new_timeout; + + if( ssl->handshake->retransmit_timeout >= ssl->conf->hs_timeout_max ) + return( -1 ); + + /* Implement the final paragraph of RFC 6347 section 4.1.1.1 + * in the following way: after the initial transmission and a first + * retransmission, back off to a temporary estimated MTU of 508 bytes. + * This value is guaranteed to be deliverable (if not guaranteed to be + * delivered) of any compliant IPv4 (and IPv6) network, and should work + * on most non-IP stacks too. */ + if( ssl->handshake->retransmit_timeout != ssl->conf->hs_timeout_min ) + { + ssl->handshake->mtu = 508; + MBEDTLS_SSL_DEBUG_MSG( 2, ( "mtu autoreduction to %d bytes", ssl->handshake->mtu ) ); + } + + new_timeout = 2 * ssl->handshake->retransmit_timeout; + + /* Avoid arithmetic overflow and range overflow */ + if( new_timeout < ssl->handshake->retransmit_timeout || + new_timeout > ssl->conf->hs_timeout_max ) + { + new_timeout = ssl->conf->hs_timeout_max; + } + + ssl->handshake->retransmit_timeout = new_timeout; + MBEDTLS_SSL_DEBUG_MSG( 3, ( "update timeout value to %d millisecs", + ssl->handshake->retransmit_timeout ) ); + + return( 0 ); +} + +static void ssl_reset_retransmit_timeout( mbedtls_ssl_context *ssl ) +{ + ssl->handshake->retransmit_timeout = ssl->conf->hs_timeout_min; + MBEDTLS_SSL_DEBUG_MSG( 3, ( "update timeout value to %d millisecs", + ssl->handshake->retransmit_timeout ) ); +} +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL) +int (*mbedtls_ssl_hw_record_init)( mbedtls_ssl_context *ssl, + const unsigned char *key_enc, const unsigned char *key_dec, + size_t keylen, + const unsigned char *iv_enc, const unsigned char *iv_dec, + size_t ivlen, + const unsigned char *mac_enc, const unsigned char *mac_dec, + size_t maclen ) = NULL; +int (*mbedtls_ssl_hw_record_activate)( mbedtls_ssl_context *ssl, int direction) = NULL; +int (*mbedtls_ssl_hw_record_reset)( mbedtls_ssl_context *ssl ) = NULL; +int (*mbedtls_ssl_hw_record_write)( mbedtls_ssl_context *ssl ) = NULL; +int (*mbedtls_ssl_hw_record_read)( mbedtls_ssl_context *ssl ) = NULL; +int (*mbedtls_ssl_hw_record_finish)( mbedtls_ssl_context *ssl ) = NULL; +#endif /* MBEDTLS_SSL_HW_RECORD_ACCEL */ + +/* The function below is only used in the Lucky 13 counter-measure in + * mbedtls_ssl_decrypt_buf(). These are the defines that guard the call site. */ +#if defined(MBEDTLS_SSL_SOME_MODES_USE_MAC) && \ + ( defined(MBEDTLS_SSL_PROTO_TLS1) || \ + defined(MBEDTLS_SSL_PROTO_TLS1_1) || \ + defined(MBEDTLS_SSL_PROTO_TLS1_2) ) +/* This function makes sure every byte in the memory region is accessed + * (in ascending addresses order) */ +static void ssl_read_memory( unsigned char *p, size_t len ) +{ + unsigned char acc = 0; + volatile unsigned char force; + + for( ; len != 0; p++, len-- ) + acc ^= *p; + + force = acc; + (void) force; +} +#endif /* SSL_SOME_MODES_USE_MAC && ( TLS1 || TLS1_1 || TLS1_2 ) */ + +/* + * Encryption/decryption functions + */ + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) +/* This functions transforms a DTLS plaintext fragment and a record content + * type into an instance of the DTLSInnerPlaintext structure: + * + * struct { + * opaque content[DTLSPlaintext.length]; + * ContentType real_type; + * uint8 zeros[length_of_padding]; + * } DTLSInnerPlaintext; + * + * Input: + * - `content`: The beginning of the buffer holding the + * plaintext to be wrapped. + * - `*content_size`: The length of the plaintext in Bytes. + * - `max_len`: The number of Bytes available starting from + * `content`. This must be `>= *content_size`. + * - `rec_type`: The desired record content type. + * + * Output: + * - `content`: The beginning of the resulting DTLSInnerPlaintext structure. + * - `*content_size`: The length of the resulting DTLSInnerPlaintext structure. + * + * Returns: + * - `0` on success. + * - A negative error code if `max_len` didn't offer enough space + * for the expansion. + */ +static int ssl_cid_build_inner_plaintext( unsigned char *content, + size_t *content_size, + size_t remaining, + uint8_t rec_type ) +{ + size_t len = *content_size; + size_t pad = ( MBEDTLS_SSL_CID_PADDING_GRANULARITY - + ( len + 1 ) % MBEDTLS_SSL_CID_PADDING_GRANULARITY ) % + MBEDTLS_SSL_CID_PADDING_GRANULARITY; + + /* Write real content type */ + if( remaining == 0 ) + return( -1 ); + content[ len ] = rec_type; + len++; + remaining--; + + if( remaining < pad ) + return( -1 ); + memset( content + len, 0, pad ); + len += pad; + remaining -= pad; + + *content_size = len; + return( 0 ); +} + +/* This function parses a DTLSInnerPlaintext structure. + * See ssl_cid_build_inner_plaintext() for details. */ +static int ssl_cid_parse_inner_plaintext( unsigned char const *content, + size_t *content_size, + uint8_t *rec_type ) +{ + size_t remaining = *content_size; + + /* Determine length of padding by skipping zeroes from the back. */ + do + { + if( remaining == 0 ) + return( -1 ); + remaining--; + } while( content[ remaining ] == 0 ); + + *content_size = remaining; + *rec_type = content[ remaining ]; + + return( 0 ); +} +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + +/* `add_data` must have size 13 Bytes if the CID extension is disabled, + * and 13 + 1 + CID-length Bytes if the CID extension is enabled. */ +static void ssl_extract_add_data_from_record( unsigned char* add_data, + size_t *add_data_len, + mbedtls_record *rec ) +{ + /* Quoting RFC 5246 (TLS 1.2): + * + * additional_data = seq_num + TLSCompressed.type + + * TLSCompressed.version + TLSCompressed.length; + * + * For the CID extension, this is extended as follows + * (quoting draft-ietf-tls-dtls-connection-id-05, + * https://tools.ietf.org/html/draft-ietf-tls-dtls-connection-id-05): + * + * additional_data = seq_num + DTLSPlaintext.type + + * DTLSPlaintext.version + + * cid + + * cid_length + + * length_of_DTLSInnerPlaintext; + */ + + memcpy( add_data, rec->ctr, sizeof( rec->ctr ) ); + add_data[8] = rec->type; + memcpy( add_data + 9, rec->ver, sizeof( rec->ver ) ); + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + if( rec->cid_len != 0 ) + { + memcpy( add_data + 11, rec->cid, rec->cid_len ); + add_data[11 + rec->cid_len + 0] = rec->cid_len; + add_data[11 + rec->cid_len + 1] = ( rec->data_len >> 8 ) & 0xFF; + add_data[11 + rec->cid_len + 2] = ( rec->data_len >> 0 ) & 0xFF; + *add_data_len = 13 + 1 + rec->cid_len; + } + else +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + { + add_data[11 + 0] = ( rec->data_len >> 8 ) & 0xFF; + add_data[11 + 1] = ( rec->data_len >> 0 ) & 0xFF; + *add_data_len = 13; + } +} + +#if defined(MBEDTLS_SSL_PROTO_SSL3) + +#define SSL3_MAC_MAX_BYTES 20 /* MD-5 or SHA-1 */ + +/* + * SSLv3.0 MAC functions + */ +static void ssl_mac( mbedtls_md_context_t *md_ctx, + const unsigned char *secret, + const unsigned char *buf, size_t len, + const unsigned char *ctr, int type, + unsigned char out[SSL3_MAC_MAX_BYTES] ) +{ + unsigned char header[11]; + unsigned char padding[48]; + int padlen; + int md_size = mbedtls_md_get_size( md_ctx->md_info ); + int md_type = mbedtls_md_get_type( md_ctx->md_info ); + + /* Only MD5 and SHA-1 supported */ + if( md_type == MBEDTLS_MD_MD5 ) + padlen = 48; + else + padlen = 40; + + memcpy( header, ctr, 8 ); + header[ 8] = (unsigned char) type; + header[ 9] = (unsigned char)( len >> 8 ); + header[10] = (unsigned char)( len ); + + memset( padding, 0x36, padlen ); + mbedtls_md_starts( md_ctx ); + mbedtls_md_update( md_ctx, secret, md_size ); + mbedtls_md_update( md_ctx, padding, padlen ); + mbedtls_md_update( md_ctx, header, 11 ); + mbedtls_md_update( md_ctx, buf, len ); + mbedtls_md_finish( md_ctx, out ); + + memset( padding, 0x5C, padlen ); + mbedtls_md_starts( md_ctx ); + mbedtls_md_update( md_ctx, secret, md_size ); + mbedtls_md_update( md_ctx, padding, padlen ); + mbedtls_md_update( md_ctx, out, md_size ); + mbedtls_md_finish( md_ctx, out ); +} +#endif /* MBEDTLS_SSL_PROTO_SSL3 */ + +int mbedtls_ssl_encrypt_buf( mbedtls_ssl_context *ssl, + mbedtls_ssl_transform *transform, + mbedtls_record *rec, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + mbedtls_cipher_mode_t mode; + int auth_done = 0; + unsigned char * data; + unsigned char add_data[13 + 1 + MBEDTLS_SSL_CID_OUT_LEN_MAX ]; + size_t add_data_len; + size_t post_avail; + + /* The SSL context is only used for debugging purposes! */ +#if !defined(MBEDTLS_DEBUG_C) + ssl = NULL; /* make sure we don't use it except for debug */ + ((void) ssl); +#endif + + /* The PRNG is used for dynamic IV generation that's used + * for CBC transformations in TLS 1.1 and TLS 1.2. */ +#if !( defined(MBEDTLS_CIPHER_MODE_CBC) && \ + ( defined(MBEDTLS_AES_C) || \ + defined(MBEDTLS_ARIA_C) || \ + defined(MBEDTLS_CAMELLIA_C) ) && \ + ( defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2) ) ) + ((void) f_rng); + ((void) p_rng); +#endif + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> encrypt buf" ) ); + + if( transform == NULL ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "no transform provided to encrypt_buf" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + if( rec == NULL + || rec->buf == NULL + || rec->buf_len < rec->data_offset + || rec->buf_len - rec->data_offset < rec->data_len +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + || rec->cid_len != 0 +#endif + ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad record structure provided to encrypt_buf" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + data = rec->buf + rec->data_offset; + post_avail = rec->buf_len - ( rec->data_len + rec->data_offset ); + MBEDTLS_SSL_DEBUG_BUF( 4, "before encrypt: output payload", + data, rec->data_len ); + + mode = mbedtls_cipher_get_cipher_mode( &transform->cipher_ctx_enc ); + + if( rec->data_len > MBEDTLS_SSL_OUT_CONTENT_LEN ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "Record content %u too large, maximum %d", + (unsigned) rec->data_len, + MBEDTLS_SSL_OUT_CONTENT_LEN ) ); + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + } + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + /* + * Add CID information + */ + rec->cid_len = transform->out_cid_len; + memcpy( rec->cid, transform->out_cid, transform->out_cid_len ); + MBEDTLS_SSL_DEBUG_BUF( 3, "CID", rec->cid, rec->cid_len ); + + if( rec->cid_len != 0 ) + { + /* + * Wrap plaintext into DTLSInnerPlaintext structure. + * See ssl_cid_build_inner_plaintext() for more information. + * + * Note that this changes `rec->data_len`, and hence + * `post_avail` needs to be recalculated afterwards. + */ + if( ssl_cid_build_inner_plaintext( data, + &rec->data_len, + post_avail, + rec->type ) != 0 ) + { + return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); + } + + rec->type = MBEDTLS_SSL_MSG_CID; + } +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + + post_avail = rec->buf_len - ( rec->data_len + rec->data_offset ); + + /* + * Add MAC before if needed + */ +#if defined(MBEDTLS_SSL_SOME_MODES_USE_MAC) + if( mode == MBEDTLS_MODE_STREAM || + ( mode == MBEDTLS_MODE_CBC +#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) + && transform->encrypt_then_mac == MBEDTLS_SSL_ETM_DISABLED +#endif + ) ) + { + if( post_avail < transform->maclen ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "Buffer provided for encrypted record not large enough" ) ); + return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); + } + +#if defined(MBEDTLS_SSL_PROTO_SSL3) + if( transform->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 ) + { + unsigned char mac[SSL3_MAC_MAX_BYTES]; + ssl_mac( &transform->md_ctx_enc, transform->mac_enc, + data, rec->data_len, rec->ctr, rec->type, mac ); + memcpy( data + rec->data_len, mac, transform->maclen ); + } + else +#endif +#if defined(MBEDTLS_SSL_PROTO_TLS1) || defined(MBEDTLS_SSL_PROTO_TLS1_1) || \ + defined(MBEDTLS_SSL_PROTO_TLS1_2) + if( transform->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_1 ) + { + unsigned char mac[MBEDTLS_SSL_MAC_ADD]; + + ssl_extract_add_data_from_record( add_data, &add_data_len, rec ); + + mbedtls_md_hmac_update( &transform->md_ctx_enc, add_data, + add_data_len ); + mbedtls_md_hmac_update( &transform->md_ctx_enc, + data, rec->data_len ); + mbedtls_md_hmac_finish( &transform->md_ctx_enc, mac ); + mbedtls_md_hmac_reset( &transform->md_ctx_enc ); + + memcpy( data + rec->data_len, mac, transform->maclen ); + } + else +#endif + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + MBEDTLS_SSL_DEBUG_BUF( 4, "computed mac", data + rec->data_len, + transform->maclen ); + + rec->data_len += transform->maclen; + post_avail -= transform->maclen; + auth_done++; + } +#endif /* MBEDTLS_SSL_SOME_MODES_USE_MAC */ + + /* + * Encrypt + */ +#if defined(MBEDTLS_ARC4_C) || defined(MBEDTLS_CIPHER_NULL_CIPHER) + if( mode == MBEDTLS_MODE_STREAM ) + { + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t olen; + MBEDTLS_SSL_DEBUG_MSG( 3, ( "before encrypt: msglen = %d, " + "including %d bytes of padding", + rec->data_len, 0 ) ); + + if( ( ret = mbedtls_cipher_crypt( &transform->cipher_ctx_enc, + transform->iv_enc, transform->ivlen, + data, rec->data_len, + data, &olen ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_crypt", ret ); + return( ret ); + } + + if( rec->data_len != olen ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + } + else +#endif /* MBEDTLS_ARC4_C || MBEDTLS_CIPHER_NULL_CIPHER */ + +#if defined(MBEDTLS_GCM_C) || \ + defined(MBEDTLS_CCM_C) || \ + defined(MBEDTLS_CHACHAPOLY_C) + if( mode == MBEDTLS_MODE_GCM || + mode == MBEDTLS_MODE_CCM || + mode == MBEDTLS_MODE_CHACHAPOLY ) + { + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char iv[12]; + size_t explicit_iv_len = transform->ivlen - transform->fixed_ivlen; + + /* Check that there's space for both the authentication tag + * and the explicit IV before and after the record content. */ + if( post_avail < transform->taglen || + rec->data_offset < explicit_iv_len ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "Buffer provided for encrypted record not large enough" ) ); + return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); + } + + /* + * Generate IV + */ + if( transform->ivlen == 12 && transform->fixed_ivlen == 4 ) + { + /* GCM and CCM: fixed || explicit (=seqnum) */ + memcpy( iv, transform->iv_enc, transform->fixed_ivlen ); + memcpy( iv + transform->fixed_ivlen, rec->ctr, + explicit_iv_len ); + /* Prefix record content with explicit IV. */ + memcpy( data - explicit_iv_len, rec->ctr, explicit_iv_len ); + } + else if( transform->ivlen == 12 && transform->fixed_ivlen == 12 ) + { + /* ChachaPoly: fixed XOR sequence number */ + unsigned char i; + + memcpy( iv, transform->iv_enc, transform->fixed_ivlen ); + + for( i = 0; i < 8; i++ ) + iv[i+4] ^= rec->ctr[i]; + } + else + { + /* Reminder if we ever add an AEAD mode with a different size */ + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + ssl_extract_add_data_from_record( add_data, &add_data_len, rec ); + + MBEDTLS_SSL_DEBUG_BUF( 4, "IV used (internal)", + iv, transform->ivlen ); + MBEDTLS_SSL_DEBUG_BUF( 4, "IV used (transmitted)", + data - explicit_iv_len, explicit_iv_len ); + MBEDTLS_SSL_DEBUG_BUF( 4, "additional data used for AEAD", + add_data, add_data_len ); + MBEDTLS_SSL_DEBUG_MSG( 3, ( "before encrypt: msglen = %d, " + "including 0 bytes of padding", + rec->data_len ) ); + + /* + * Encrypt and authenticate + */ + + if( ( ret = mbedtls_cipher_auth_encrypt( &transform->cipher_ctx_enc, + iv, transform->ivlen, + add_data, add_data_len, /* add data */ + data, rec->data_len, /* source */ + data, &rec->data_len, /* destination */ + data + rec->data_len, transform->taglen ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_auth_encrypt", ret ); + return( ret ); + } + + MBEDTLS_SSL_DEBUG_BUF( 4, "after encrypt: tag", + data + rec->data_len, transform->taglen ); + + rec->data_len += transform->taglen + explicit_iv_len; + rec->data_offset -= explicit_iv_len; + post_avail -= transform->taglen; + auth_done++; + } + else +#endif /* MBEDTLS_GCM_C || MBEDTLS_CCM_C */ +#if defined(MBEDTLS_CIPHER_MODE_CBC) && \ + ( defined(MBEDTLS_AES_C) || defined(MBEDTLS_CAMELLIA_C) || defined(MBEDTLS_ARIA_C) ) + if( mode == MBEDTLS_MODE_CBC ) + { + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t padlen, i; + size_t olen; + + /* Currently we're always using minimal padding + * (up to 255 bytes would be allowed). */ + padlen = transform->ivlen - ( rec->data_len + 1 ) % transform->ivlen; + if( padlen == transform->ivlen ) + padlen = 0; + + /* Check there's enough space in the buffer for the padding. */ + if( post_avail < padlen + 1 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "Buffer provided for encrypted record not large enough" ) ); + return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); + } + + for( i = 0; i <= padlen; i++ ) + data[rec->data_len + i] = (unsigned char) padlen; + + rec->data_len += padlen + 1; + post_avail -= padlen + 1; + +#if defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2) + /* + * Prepend per-record IV for block cipher in TLS v1.1 and up as per + * Method 1 (6.2.3.2. in RFC4346 and RFC5246) + */ + if( transform->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_2 ) + { + if( f_rng == NULL ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "No PRNG provided to encrypt_record routine" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + if( rec->data_offset < transform->ivlen ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "Buffer provided for encrypted record not large enough" ) ); + return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); + } + + /* + * Generate IV + */ + ret = f_rng( p_rng, transform->iv_enc, transform->ivlen ); + if( ret != 0 ) + return( ret ); + + memcpy( data - transform->ivlen, transform->iv_enc, + transform->ivlen ); + + } +#endif /* MBEDTLS_SSL_PROTO_TLS1_1 || MBEDTLS_SSL_PROTO_TLS1_2 */ + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "before encrypt: msglen = %d, " + "including %d bytes of IV and %d bytes of padding", + rec->data_len, transform->ivlen, + padlen + 1 ) ); + + if( ( ret = mbedtls_cipher_crypt( &transform->cipher_ctx_enc, + transform->iv_enc, + transform->ivlen, + data, rec->data_len, + data, &olen ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_crypt", ret ); + return( ret ); + } + + if( rec->data_len != olen ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + +#if defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1) + if( transform->minor_ver < MBEDTLS_SSL_MINOR_VERSION_2 ) + { + /* + * Save IV in SSL3 and TLS1 + */ + memcpy( transform->iv_enc, transform->cipher_ctx_enc.iv, + transform->ivlen ); + } + else +#endif + { + data -= transform->ivlen; + rec->data_offset -= transform->ivlen; + rec->data_len += transform->ivlen; + } + +#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) + if( auth_done == 0 ) + { + unsigned char mac[MBEDTLS_SSL_MAC_ADD]; + + /* + * MAC(MAC_write_key, seq_num + + * TLSCipherText.type + + * TLSCipherText.version + + * length_of( (IV +) ENC(...) ) + + * IV + // except for TLS 1.0 + * ENC(content + padding + padding_length)); + */ + + if( post_avail < transform->maclen) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "Buffer provided for encrypted record not large enough" ) ); + return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); + } + + ssl_extract_add_data_from_record( add_data, &add_data_len, rec ); + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "using encrypt then mac" ) ); + MBEDTLS_SSL_DEBUG_BUF( 4, "MAC'd meta-data", add_data, + add_data_len ); + + mbedtls_md_hmac_update( &transform->md_ctx_enc, add_data, + add_data_len ); + mbedtls_md_hmac_update( &transform->md_ctx_enc, + data, rec->data_len ); + mbedtls_md_hmac_finish( &transform->md_ctx_enc, mac ); + mbedtls_md_hmac_reset( &transform->md_ctx_enc ); + + memcpy( data + rec->data_len, mac, transform->maclen ); + + rec->data_len += transform->maclen; + post_avail -= transform->maclen; + auth_done++; + } +#endif /* MBEDTLS_SSL_ENCRYPT_THEN_MAC */ + } + else +#endif /* MBEDTLS_CIPHER_MODE_CBC && + ( MBEDTLS_AES_C || MBEDTLS_CAMELLIA_C || MBEDTLS_ARIA_C ) */ + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + /* Make extra sure authentication was performed, exactly once */ + if( auth_done != 1 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= encrypt buf" ) ); + + return( 0 ); +} + +int mbedtls_ssl_decrypt_buf( mbedtls_ssl_context const *ssl, + mbedtls_ssl_transform *transform, + mbedtls_record *rec ) +{ + size_t olen; + mbedtls_cipher_mode_t mode; + int ret, auth_done = 0; +#if defined(MBEDTLS_SSL_SOME_MODES_USE_MAC) + size_t padlen = 0, correct = 1; +#endif + unsigned char* data; + unsigned char add_data[13 + 1 + MBEDTLS_SSL_CID_IN_LEN_MAX ]; + size_t add_data_len; + +#if !defined(MBEDTLS_DEBUG_C) + ssl = NULL; /* make sure we don't use it except for debug */ + ((void) ssl); +#endif + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> decrypt buf" ) ); + if( rec == NULL || + rec->buf == NULL || + rec->buf_len < rec->data_offset || + rec->buf_len - rec->data_offset < rec->data_len ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad record structure provided to decrypt_buf" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + data = rec->buf + rec->data_offset; + mode = mbedtls_cipher_get_cipher_mode( &transform->cipher_ctx_dec ); + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + /* + * Match record's CID with incoming CID. + */ + if( rec->cid_len != transform->in_cid_len || + memcmp( rec->cid, transform->in_cid, rec->cid_len ) != 0 ) + { + return( MBEDTLS_ERR_SSL_UNEXPECTED_CID ); + } +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + +#if defined(MBEDTLS_ARC4_C) || defined(MBEDTLS_CIPHER_NULL_CIPHER) + if( mode == MBEDTLS_MODE_STREAM ) + { + padlen = 0; + if( ( ret = mbedtls_cipher_crypt( &transform->cipher_ctx_dec, + transform->iv_dec, + transform->ivlen, + data, rec->data_len, + data, &olen ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_crypt", ret ); + return( ret ); + } + + if( rec->data_len != olen ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + } + else +#endif /* MBEDTLS_ARC4_C || MBEDTLS_CIPHER_NULL_CIPHER */ +#if defined(MBEDTLS_GCM_C) || \ + defined(MBEDTLS_CCM_C) || \ + defined(MBEDTLS_CHACHAPOLY_C) + if( mode == MBEDTLS_MODE_GCM || + mode == MBEDTLS_MODE_CCM || + mode == MBEDTLS_MODE_CHACHAPOLY ) + { + unsigned char iv[12]; + size_t explicit_iv_len = transform->ivlen - transform->fixed_ivlen; + + /* + * Prepare IV from explicit and implicit data. + */ + + /* Check that there's enough space for the explicit IV + * (at the beginning of the record) and the MAC (at the + * end of the record). */ + if( rec->data_len < explicit_iv_len + transform->taglen ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "msglen (%d) < explicit_iv_len (%d) " + "+ taglen (%d)", rec->data_len, + explicit_iv_len, transform->taglen ) ); + return( MBEDTLS_ERR_SSL_INVALID_MAC ); + } + +#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CCM_C) + if( transform->ivlen == 12 && transform->fixed_ivlen == 4 ) + { + /* GCM and CCM: fixed || explicit */ + + /* Fixed */ + memcpy( iv, transform->iv_dec, transform->fixed_ivlen ); + /* Explicit */ + memcpy( iv + transform->fixed_ivlen, data, 8 ); + } + else +#endif /* MBEDTLS_GCM_C || MBEDTLS_CCM_C */ +#if defined(MBEDTLS_CHACHAPOLY_C) + if( transform->ivlen == 12 && transform->fixed_ivlen == 12 ) + { + /* ChachaPoly: fixed XOR sequence number */ + unsigned char i; + + memcpy( iv, transform->iv_dec, transform->fixed_ivlen ); + + for( i = 0; i < 8; i++ ) + iv[i+4] ^= rec->ctr[i]; + } + else +#endif /* MBEDTLS_CHACHAPOLY_C */ + { + /* Reminder if we ever add an AEAD mode with a different size */ + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + /* Group changes to data, data_len, and add_data, because + * add_data depends on data_len. */ + data += explicit_iv_len; + rec->data_offset += explicit_iv_len; + rec->data_len -= explicit_iv_len + transform->taglen; + + ssl_extract_add_data_from_record( add_data, &add_data_len, rec ); + MBEDTLS_SSL_DEBUG_BUF( 4, "additional data used for AEAD", + add_data, add_data_len ); + + /* Because of the check above, we know that there are + * explicit_iv_len Bytes preceeding data, and taglen + * bytes following data + data_len. This justifies + * the debug message and the invocation of + * mbedtls_cipher_auth_decrypt() below. */ + + MBEDTLS_SSL_DEBUG_BUF( 4, "IV used", iv, transform->ivlen ); + MBEDTLS_SSL_DEBUG_BUF( 4, "TAG used", data + rec->data_len, + transform->taglen ); + + /* + * Decrypt and authenticate + */ + if( ( ret = mbedtls_cipher_auth_decrypt( &transform->cipher_ctx_dec, + iv, transform->ivlen, + add_data, add_data_len, + data, rec->data_len, + data, &olen, + data + rec->data_len, + transform->taglen ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_auth_decrypt", ret ); + + if( ret == MBEDTLS_ERR_CIPHER_AUTH_FAILED ) + return( MBEDTLS_ERR_SSL_INVALID_MAC ); + + return( ret ); + } + auth_done++; + + /* Double-check that AEAD decryption doesn't change content length. */ + if( olen != rec->data_len ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + } + else +#endif /* MBEDTLS_GCM_C || MBEDTLS_CCM_C */ +#if defined(MBEDTLS_CIPHER_MODE_CBC) && \ + ( defined(MBEDTLS_AES_C) || defined(MBEDTLS_CAMELLIA_C) || defined(MBEDTLS_ARIA_C) ) + if( mode == MBEDTLS_MODE_CBC ) + { + size_t minlen = 0; + + /* + * Check immediate ciphertext sanity + */ +#if defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2) + if( transform->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_2 ) + { + /* The ciphertext is prefixed with the CBC IV. */ + minlen += transform->ivlen; + } +#endif + + /* Size considerations: + * + * - The CBC cipher text must not be empty and hence + * at least of size transform->ivlen. + * + * Together with the potential IV-prefix, this explains + * the first of the two checks below. + * + * - The record must contain a MAC, either in plain or + * encrypted, depending on whether Encrypt-then-MAC + * is used or not. + * - If it is, the message contains the IV-prefix, + * the CBC ciphertext, and the MAC. + * - If it is not, the padded plaintext, and hence + * the CBC ciphertext, has at least length maclen + 1 + * because there is at least the padding length byte. + * + * As the CBC ciphertext is not empty, both cases give the + * lower bound minlen + maclen + 1 on the record size, which + * we test for in the second check below. + */ + if( rec->data_len < minlen + transform->ivlen || + rec->data_len < minlen + transform->maclen + 1 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "msglen (%d) < max( ivlen(%d), maclen (%d) " + "+ 1 ) ( + expl IV )", rec->data_len, + transform->ivlen, + transform->maclen ) ); + return( MBEDTLS_ERR_SSL_INVALID_MAC ); + } + + /* + * Authenticate before decrypt if enabled + */ +#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) + if( transform->encrypt_then_mac == MBEDTLS_SSL_ETM_ENABLED ) + { + unsigned char mac_expect[MBEDTLS_SSL_MAC_ADD]; + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "using encrypt then mac" ) ); + + /* Update data_len in tandem with add_data. + * + * The subtraction is safe because of the previous check + * data_len >= minlen + maclen + 1. + * + * Afterwards, we know that data + data_len is followed by at + * least maclen Bytes, which justifies the call to + * mbedtls_ssl_safer_memcmp() below. + * + * Further, we still know that data_len > minlen */ + rec->data_len -= transform->maclen; + ssl_extract_add_data_from_record( add_data, &add_data_len, rec ); + + /* Calculate expected MAC. */ + MBEDTLS_SSL_DEBUG_BUF( 4, "MAC'd meta-data", add_data, + add_data_len ); + mbedtls_md_hmac_update( &transform->md_ctx_dec, add_data, + add_data_len ); + mbedtls_md_hmac_update( &transform->md_ctx_dec, + data, rec->data_len ); + mbedtls_md_hmac_finish( &transform->md_ctx_dec, mac_expect ); + mbedtls_md_hmac_reset( &transform->md_ctx_dec ); + + MBEDTLS_SSL_DEBUG_BUF( 4, "message mac", data + rec->data_len, + transform->maclen ); + MBEDTLS_SSL_DEBUG_BUF( 4, "expected mac", mac_expect, + transform->maclen ); + + /* Compare expected MAC with MAC at the end of the record. */ + if( mbedtls_ssl_safer_memcmp( data + rec->data_len, mac_expect, + transform->maclen ) != 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "message mac does not match" ) ); + return( MBEDTLS_ERR_SSL_INVALID_MAC ); + } + auth_done++; + } +#endif /* MBEDTLS_SSL_ENCRYPT_THEN_MAC */ + + /* + * Check length sanity + */ + + /* We know from above that data_len > minlen >= 0, + * so the following check in particular implies that + * data_len >= minlen + ivlen ( = minlen or 2 * minlen ). */ + if( rec->data_len % transform->ivlen != 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "msglen (%d) %% ivlen (%d) != 0", + rec->data_len, transform->ivlen ) ); + return( MBEDTLS_ERR_SSL_INVALID_MAC ); + } + +#if defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2) + /* + * Initialize for prepended IV for block cipher in TLS v1.1 and up + */ + if( transform->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_2 ) + { + /* Safe because data_len >= minlen + ivlen = 2 * ivlen. */ + memcpy( transform->iv_dec, data, transform->ivlen ); + + data += transform->ivlen; + rec->data_offset += transform->ivlen; + rec->data_len -= transform->ivlen; + } +#endif /* MBEDTLS_SSL_PROTO_TLS1_1 || MBEDTLS_SSL_PROTO_TLS1_2 */ + + /* We still have data_len % ivlen == 0 and data_len >= ivlen here. */ + + if( ( ret = mbedtls_cipher_crypt( &transform->cipher_ctx_dec, + transform->iv_dec, transform->ivlen, + data, rec->data_len, data, &olen ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_crypt", ret ); + return( ret ); + } + + /* Double-check that length hasn't changed during decryption. */ + if( rec->data_len != olen ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + +#if defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1) + if( transform->minor_ver < MBEDTLS_SSL_MINOR_VERSION_2 ) + { + /* + * Save IV in SSL3 and TLS1, where CBC decryption of consecutive + * records is equivalent to CBC decryption of the concatenation + * of the records; in other words, IVs are maintained across + * record decryptions. + */ + memcpy( transform->iv_dec, transform->cipher_ctx_dec.iv, + transform->ivlen ); + } +#endif + + /* Safe since data_len >= minlen + maclen + 1, so after having + * subtracted at most minlen and maclen up to this point, + * data_len > 0 (because of data_len % ivlen == 0, it's actually + * >= ivlen ). */ + padlen = data[rec->data_len - 1]; + + if( auth_done == 1 ) + { + correct *= ( rec->data_len >= padlen + 1 ); + padlen *= ( rec->data_len >= padlen + 1 ); + } + else + { +#if defined(MBEDTLS_SSL_DEBUG_ALL) + if( rec->data_len < transform->maclen + padlen + 1 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "msglen (%d) < maclen (%d) + padlen (%d)", + rec->data_len, + transform->maclen, + padlen + 1 ) ); + } +#endif + + correct *= ( rec->data_len >= transform->maclen + padlen + 1 ); + padlen *= ( rec->data_len >= transform->maclen + padlen + 1 ); + } + + padlen++; + + /* Regardless of the validity of the padding, + * we have data_len >= padlen here. */ + +#if defined(MBEDTLS_SSL_PROTO_SSL3) + if( transform->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 ) + { + if( padlen > transform->ivlen ) + { +#if defined(MBEDTLS_SSL_DEBUG_ALL) + MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad padding length: is %d, " + "should be no more than %d", + padlen, transform->ivlen ) ); +#endif + correct = 0; + } + } + else +#endif /* MBEDTLS_SSL_PROTO_SSL3 */ +#if defined(MBEDTLS_SSL_PROTO_TLS1) || defined(MBEDTLS_SSL_PROTO_TLS1_1) || \ + defined(MBEDTLS_SSL_PROTO_TLS1_2) + if( transform->minor_ver > MBEDTLS_SSL_MINOR_VERSION_0 ) + { + /* The padding check involves a series of up to 256 + * consecutive memory reads at the end of the record + * plaintext buffer. In order to hide the length and + * validity of the padding, always perform exactly + * `min(256,plaintext_len)` reads (but take into account + * only the last `padlen` bytes for the padding check). */ + size_t pad_count = 0; + size_t real_count = 0; + volatile unsigned char* const check = data; + + /* Index of first padding byte; it has been ensured above + * that the subtraction is safe. */ + size_t const padding_idx = rec->data_len - padlen; + size_t const num_checks = rec->data_len <= 256 ? rec->data_len : 256; + size_t const start_idx = rec->data_len - num_checks; + size_t idx; + + for( idx = start_idx; idx < rec->data_len; idx++ ) + { + real_count |= ( idx >= padding_idx ); + pad_count += real_count * ( check[idx] == padlen - 1 ); + } + correct &= ( pad_count == padlen ); + +#if defined(MBEDTLS_SSL_DEBUG_ALL) + if( padlen > 0 && correct == 0 ) + MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad padding byte detected" ) ); +#endif + padlen &= correct * 0x1FF; + } + else +#endif /* MBEDTLS_SSL_PROTO_TLS1 || MBEDTLS_SSL_PROTO_TLS1_1 || \ + MBEDTLS_SSL_PROTO_TLS1_2 */ + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + /* If the padding was found to be invalid, padlen == 0 + * and the subtraction is safe. If the padding was found valid, + * padlen hasn't been changed and the previous assertion + * data_len >= padlen still holds. */ + rec->data_len -= padlen; + } + else +#endif /* MBEDTLS_CIPHER_MODE_CBC && + ( MBEDTLS_AES_C || MBEDTLS_CAMELLIA_C || MBEDTLS_ARIA_C ) */ + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + +#if defined(MBEDTLS_SSL_DEBUG_ALL) + MBEDTLS_SSL_DEBUG_BUF( 4, "raw buffer after decryption", + data, rec->data_len ); +#endif + + /* + * Authenticate if not done yet. + * Compute the MAC regardless of the padding result (RFC4346, CBCTIME). + */ +#if defined(MBEDTLS_SSL_SOME_MODES_USE_MAC) + if( auth_done == 0 ) + { + unsigned char mac_expect[MBEDTLS_SSL_MAC_ADD]; + + /* If the initial value of padlen was such that + * data_len < maclen + padlen + 1, then padlen + * got reset to 1, and the initial check + * data_len >= minlen + maclen + 1 + * guarantees that at this point we still + * have at least data_len >= maclen. + * + * If the initial value of padlen was such that + * data_len >= maclen + padlen + 1, then we have + * subtracted either padlen + 1 (if the padding was correct) + * or 0 (if the padding was incorrect) since then, + * hence data_len >= maclen in any case. + */ + rec->data_len -= transform->maclen; + ssl_extract_add_data_from_record( add_data, &add_data_len, rec ); + +#if defined(MBEDTLS_SSL_PROTO_SSL3) + if( transform->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 ) + { + ssl_mac( &transform->md_ctx_dec, + transform->mac_dec, + data, rec->data_len, + rec->ctr, rec->type, + mac_expect ); + } + else +#endif /* MBEDTLS_SSL_PROTO_SSL3 */ +#if defined(MBEDTLS_SSL_PROTO_TLS1) || defined(MBEDTLS_SSL_PROTO_TLS1_1) || \ + defined(MBEDTLS_SSL_PROTO_TLS1_2) + if( transform->minor_ver > MBEDTLS_SSL_MINOR_VERSION_0 ) + { + /* + * Process MAC and always update for padlen afterwards to make + * total time independent of padlen. + * + * Known timing attacks: + * - Lucky Thirteen (http://www.isg.rhul.ac.uk/tls/TLStiming.pdf) + * + * To compensate for different timings for the MAC calculation + * depending on how much padding was removed (which is determined + * by padlen), process extra_run more blocks through the hash + * function. + * + * The formula in the paper is + * extra_run = ceil( (L1-55) / 64 ) - ceil( (L2-55) / 64 ) + * where L1 is the size of the header plus the decrypted message + * plus CBC padding and L2 is the size of the header plus the + * decrypted message. This is for an underlying hash function + * with 64-byte blocks. + * We use ( (Lx+8) / 64 ) to handle 'negative Lx' values + * correctly. We round down instead of up, so -56 is the correct + * value for our calculations instead of -55. + * + * Repeat the formula rather than defining a block_size variable. + * This avoids requiring division by a variable at runtime + * (which would be marginally less efficient and would require + * linking an extra division function in some builds). + */ + size_t j, extra_run = 0; + unsigned char tmp[MBEDTLS_MD_MAX_BLOCK_SIZE]; + + /* + * The next two sizes are the minimum and maximum values of + * in_msglen over all padlen values. + * + * They're independent of padlen, since we previously did + * data_len -= padlen. + * + * Note that max_len + maclen is never more than the buffer + * length, as we previously did in_msglen -= maclen too. + */ + const size_t max_len = rec->data_len + padlen; + const size_t min_len = ( max_len > 256 ) ? max_len - 256 : 0; + + memset( tmp, 0, sizeof( tmp ) ); + + switch( mbedtls_md_get_type( transform->md_ctx_dec.md_info ) ) + { +#if defined(MBEDTLS_MD5_C) || defined(MBEDTLS_SHA1_C) || \ + defined(MBEDTLS_SHA256_C) + case MBEDTLS_MD_MD5: + case MBEDTLS_MD_SHA1: + case MBEDTLS_MD_SHA256: + /* 8 bytes of message size, 64-byte compression blocks */ + extra_run = + ( add_data_len + rec->data_len + padlen + 8 ) / 64 - + ( add_data_len + rec->data_len + 8 ) / 64; + break; +#endif +#if defined(MBEDTLS_SHA512_C) + case MBEDTLS_MD_SHA384: + /* 16 bytes of message size, 128-byte compression blocks */ + extra_run = + ( add_data_len + rec->data_len + padlen + 16 ) / 128 - + ( add_data_len + rec->data_len + 16 ) / 128; + break; +#endif + default: + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + extra_run &= correct * 0xFF; + + mbedtls_md_hmac_update( &transform->md_ctx_dec, add_data, + add_data_len ); + mbedtls_md_hmac_update( &transform->md_ctx_dec, data, + rec->data_len ); + /* Make sure we access everything even when padlen > 0. This + * makes the synchronisation requirements for just-in-time + * Prime+Probe attacks much tighter and hopefully impractical. */ + ssl_read_memory( data + rec->data_len, padlen ); + mbedtls_md_hmac_finish( &transform->md_ctx_dec, mac_expect ); + + /* Call mbedtls_md_process at least once due to cache attacks + * that observe whether md_process() was called of not */ + for( j = 0; j < extra_run + 1; j++ ) + mbedtls_md_process( &transform->md_ctx_dec, tmp ); + + mbedtls_md_hmac_reset( &transform->md_ctx_dec ); + + /* Make sure we access all the memory that could contain the MAC, + * before we check it in the next code block. This makes the + * synchronisation requirements for just-in-time Prime+Probe + * attacks much tighter and hopefully impractical. */ + ssl_read_memory( data + min_len, + max_len - min_len + transform->maclen ); + } + else +#endif /* MBEDTLS_SSL_PROTO_TLS1 || MBEDTLS_SSL_PROTO_TLS1_1 || \ + MBEDTLS_SSL_PROTO_TLS1_2 */ + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + +#if defined(MBEDTLS_SSL_DEBUG_ALL) + MBEDTLS_SSL_DEBUG_BUF( 4, "expected mac", mac_expect, transform->maclen ); + MBEDTLS_SSL_DEBUG_BUF( 4, "message mac", data + rec->data_len, transform->maclen ); +#endif + + if( mbedtls_ssl_safer_memcmp( data + rec->data_len, mac_expect, + transform->maclen ) != 0 ) + { +#if defined(MBEDTLS_SSL_DEBUG_ALL) + MBEDTLS_SSL_DEBUG_MSG( 1, ( "message mac does not match" ) ); +#endif + correct = 0; + } + auth_done++; + } + + /* + * Finally check the correct flag + */ + if( correct == 0 ) + return( MBEDTLS_ERR_SSL_INVALID_MAC ); +#endif /* MBEDTLS_SSL_SOME_MODES_USE_MAC */ + + /* Make extra sure authentication was performed, exactly once */ + if( auth_done != 1 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + if( rec->cid_len != 0 ) + { + ret = ssl_cid_parse_inner_plaintext( data, &rec->data_len, + &rec->type ); + if( ret != 0 ) + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= decrypt buf" ) ); + + return( 0 ); +} + +#undef MAC_NONE +#undef MAC_PLAINTEXT +#undef MAC_CIPHERTEXT + +#if defined(MBEDTLS_ZLIB_SUPPORT) +/* + * Compression/decompression functions + */ +static int ssl_compress_buf( mbedtls_ssl_context *ssl ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char *msg_post = ssl->out_msg; + ptrdiff_t bytes_written = ssl->out_msg - ssl->out_buf; + size_t len_pre = ssl->out_msglen; + unsigned char *msg_pre = ssl->compress_buf; + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> compress buf" ) ); + + if( len_pre == 0 ) + return( 0 ); + + memcpy( msg_pre, ssl->out_msg, len_pre ); + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "before compression: msglen = %d, ", + ssl->out_msglen ) ); + + MBEDTLS_SSL_DEBUG_BUF( 4, "before compression: output payload", + ssl->out_msg, ssl->out_msglen ); + + ssl->transform_out->ctx_deflate.next_in = msg_pre; + ssl->transform_out->ctx_deflate.avail_in = len_pre; + ssl->transform_out->ctx_deflate.next_out = msg_post; + ssl->transform_out->ctx_deflate.avail_out = MBEDTLS_SSL_OUT_BUFFER_LEN - bytes_written; + + ret = deflate( &ssl->transform_out->ctx_deflate, Z_SYNC_FLUSH ); + if( ret != Z_OK ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "failed to perform compression (%d)", ret ) ); + return( MBEDTLS_ERR_SSL_COMPRESSION_FAILED ); + } + + ssl->out_msglen = MBEDTLS_SSL_OUT_BUFFER_LEN - + ssl->transform_out->ctx_deflate.avail_out - bytes_written; + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "after compression: msglen = %d, ", + ssl->out_msglen ) ); + + MBEDTLS_SSL_DEBUG_BUF( 4, "after compression: output payload", + ssl->out_msg, ssl->out_msglen ); + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= compress buf" ) ); + + return( 0 ); +} + +static int ssl_decompress_buf( mbedtls_ssl_context *ssl ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char *msg_post = ssl->in_msg; + ptrdiff_t header_bytes = ssl->in_msg - ssl->in_buf; + size_t len_pre = ssl->in_msglen; + unsigned char *msg_pre = ssl->compress_buf; + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> decompress buf" ) ); + + if( len_pre == 0 ) + return( 0 ); + + memcpy( msg_pre, ssl->in_msg, len_pre ); + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "before decompression: msglen = %d, ", + ssl->in_msglen ) ); + + MBEDTLS_SSL_DEBUG_BUF( 4, "before decompression: input payload", + ssl->in_msg, ssl->in_msglen ); + + ssl->transform_in->ctx_inflate.next_in = msg_pre; + ssl->transform_in->ctx_inflate.avail_in = len_pre; + ssl->transform_in->ctx_inflate.next_out = msg_post; + ssl->transform_in->ctx_inflate.avail_out = MBEDTLS_SSL_IN_BUFFER_LEN - + header_bytes; + + ret = inflate( &ssl->transform_in->ctx_inflate, Z_SYNC_FLUSH ); + if( ret != Z_OK ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "failed to perform decompression (%d)", ret ) ); + return( MBEDTLS_ERR_SSL_COMPRESSION_FAILED ); + } + + ssl->in_msglen = MBEDTLS_SSL_IN_BUFFER_LEN - + ssl->transform_in->ctx_inflate.avail_out - header_bytes; + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "after decompression: msglen = %d, ", + ssl->in_msglen ) ); + + MBEDTLS_SSL_DEBUG_BUF( 4, "after decompression: input payload", + ssl->in_msg, ssl->in_msglen ); + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= decompress buf" ) ); + + return( 0 ); +} +#endif /* MBEDTLS_ZLIB_SUPPORT */ + +/* + * Fill the input message buffer by appending data to it. + * The amount of data already fetched is in ssl->in_left. + * + * If we return 0, is it guaranteed that (at least) nb_want bytes are + * available (from this read and/or a previous one). Otherwise, an error code + * is returned (possibly EOF or WANT_READ). + * + * With stream transport (TLS) on success ssl->in_left == nb_want, but + * with datagram transport (DTLS) on success ssl->in_left >= nb_want, + * since we always read a whole datagram at once. + * + * For DTLS, it is up to the caller to set ssl->next_record_offset when + * they're done reading a record. + */ +int mbedtls_ssl_fetch_input( mbedtls_ssl_context *ssl, size_t nb_want ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t len; + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> fetch input" ) ); + + if( ssl->f_recv == NULL && ssl->f_recv_timeout == NULL ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "Bad usage of mbedtls_ssl_set_bio() " + "or mbedtls_ssl_set_bio()" ) ); + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + } + + if( nb_want > MBEDTLS_SSL_IN_BUFFER_LEN - (size_t)( ssl->in_hdr - ssl->in_buf ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "requesting more data than fits" ) ); + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + } + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + uint32_t timeout; + + /* Just to be sure */ + if( ssl->f_set_timer == NULL || ssl->f_get_timer == NULL ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "You must use " + "mbedtls_ssl_set_timer_cb() for DTLS" ) ); + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + } + + /* + * The point is, we need to always read a full datagram at once, so we + * sometimes read more then requested, and handle the additional data. + * It could be the rest of the current record (while fetching the + * header) and/or some other records in the same datagram. + */ + + /* + * Move to the next record in the already read datagram if applicable + */ + if( ssl->next_record_offset != 0 ) + { + if( ssl->in_left < ssl->next_record_offset ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + ssl->in_left -= ssl->next_record_offset; + + if( ssl->in_left != 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "next record in same datagram, offset: %d", + ssl->next_record_offset ) ); + memmove( ssl->in_hdr, + ssl->in_hdr + ssl->next_record_offset, + ssl->in_left ); + } + + ssl->next_record_offset = 0; + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "in_left: %d, nb_want: %d", + ssl->in_left, nb_want ) ); + + /* + * Done if we already have enough data. + */ + if( nb_want <= ssl->in_left) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= fetch input" ) ); + return( 0 ); + } + + /* + * A record can't be split across datagrams. If we need to read but + * are not at the beginning of a new record, the caller did something + * wrong. + */ + if( ssl->in_left != 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + /* + * Don't even try to read if time's out already. + * This avoids by-passing the timer when repeatedly receiving messages + * that will end up being dropped. + */ + if( mbedtls_ssl_check_timer( ssl ) != 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "timer has expired" ) ); + ret = MBEDTLS_ERR_SSL_TIMEOUT; + } + else + { + len = MBEDTLS_SSL_IN_BUFFER_LEN - ( ssl->in_hdr - ssl->in_buf ); + + if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER ) + timeout = ssl->handshake->retransmit_timeout; + else + timeout = ssl->conf->read_timeout; + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "f_recv_timeout: %u ms", timeout ) ); + + if( ssl->f_recv_timeout != NULL ) + ret = ssl->f_recv_timeout( ssl->p_bio, ssl->in_hdr, len, + timeout ); + else + ret = ssl->f_recv( ssl->p_bio, ssl->in_hdr, len ); + + MBEDTLS_SSL_DEBUG_RET( 2, "ssl->f_recv(_timeout)", ret ); + + if( ret == 0 ) + return( MBEDTLS_ERR_SSL_CONN_EOF ); + } + + if( ret == MBEDTLS_ERR_SSL_TIMEOUT ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "timeout" ) ); + mbedtls_ssl_set_timer( ssl, 0 ); + + if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER ) + { + if( ssl_double_retransmit_timeout( ssl ) != 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "handshake timeout" ) ); + return( MBEDTLS_ERR_SSL_TIMEOUT ); + } + + if( ( ret = mbedtls_ssl_resend( ssl ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_resend", ret ); + return( ret ); + } + + return( MBEDTLS_ERR_SSL_WANT_READ ); + } +#if defined(MBEDTLS_SSL_SRV_C) && defined(MBEDTLS_SSL_RENEGOTIATION) + else if( ssl->conf->endpoint == MBEDTLS_SSL_IS_SERVER && + ssl->renego_status == MBEDTLS_SSL_RENEGOTIATION_PENDING ) + { + if( ( ret = mbedtls_ssl_resend_hello_request( ssl ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_resend_hello_request", + ret ); + return( ret ); + } + + return( MBEDTLS_ERR_SSL_WANT_READ ); + } +#endif /* MBEDTLS_SSL_SRV_C && MBEDTLS_SSL_RENEGOTIATION */ + } + + if( ret < 0 ) + return( ret ); + + ssl->in_left = ret; + } + else +#endif + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "in_left: %d, nb_want: %d", + ssl->in_left, nb_want ) ); + + while( ssl->in_left < nb_want ) + { + len = nb_want - ssl->in_left; + + if( mbedtls_ssl_check_timer( ssl ) != 0 ) + ret = MBEDTLS_ERR_SSL_TIMEOUT; + else + { + if( ssl->f_recv_timeout != NULL ) + { + ret = ssl->f_recv_timeout( ssl->p_bio, + ssl->in_hdr + ssl->in_left, len, + ssl->conf->read_timeout ); + } + else + { + ret = ssl->f_recv( ssl->p_bio, + ssl->in_hdr + ssl->in_left, len ); + } + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "in_left: %d, nb_want: %d", + ssl->in_left, nb_want ) ); + MBEDTLS_SSL_DEBUG_RET( 2, "ssl->f_recv(_timeout)", ret ); + + if( ret == 0 ) + return( MBEDTLS_ERR_SSL_CONN_EOF ); + + if( ret < 0 ) + return( ret ); + + if ( (size_t)ret > len || ( INT_MAX > SIZE_MAX && ret > SIZE_MAX ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, + ( "f_recv returned %d bytes but only %lu were requested", + ret, (unsigned long)len ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + ssl->in_left += ret; + } + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= fetch input" ) ); + + return( 0 ); +} + +/* + * Flush any data not yet written + */ +int mbedtls_ssl_flush_output( mbedtls_ssl_context *ssl ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char *buf; + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> flush output" ) ); + + if( ssl->f_send == NULL ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "Bad usage of mbedtls_ssl_set_bio() " + "or mbedtls_ssl_set_bio()" ) ); + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + } + + /* Avoid incrementing counter if data is flushed */ + if( ssl->out_left == 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= flush output" ) ); + return( 0 ); + } + + while( ssl->out_left > 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "message length: %d, out_left: %d", + mbedtls_ssl_out_hdr_len( ssl ) + ssl->out_msglen, ssl->out_left ) ); + + buf = ssl->out_hdr - ssl->out_left; + ret = ssl->f_send( ssl->p_bio, buf, ssl->out_left ); + + MBEDTLS_SSL_DEBUG_RET( 2, "ssl->f_send", ret ); + + if( ret <= 0 ) + return( ret ); + + if( (size_t)ret > ssl->out_left || ( INT_MAX > SIZE_MAX && ret > SIZE_MAX ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, + ( "f_send returned %d bytes but only %lu bytes were sent", + ret, (unsigned long)ssl->out_left ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + ssl->out_left -= ret; + } + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + ssl->out_hdr = ssl->out_buf; + } + else +#endif + { + ssl->out_hdr = ssl->out_buf + 8; + } + mbedtls_ssl_update_out_pointers( ssl, ssl->transform_out ); + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= flush output" ) ); + + return( 0 ); +} + +/* + * Functions to handle the DTLS retransmission state machine + */ +#if defined(MBEDTLS_SSL_PROTO_DTLS) +/* + * Append current handshake message to current outgoing flight + */ +static int ssl_flight_append( mbedtls_ssl_context *ssl ) +{ + mbedtls_ssl_flight_item *msg; + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> ssl_flight_append" ) ); + MBEDTLS_SSL_DEBUG_BUF( 4, "message appended to flight", + ssl->out_msg, ssl->out_msglen ); + + /* Allocate space for current message */ + if( ( msg = mbedtls_calloc( 1, sizeof( mbedtls_ssl_flight_item ) ) ) == NULL ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "alloc %d bytes failed", + sizeof( mbedtls_ssl_flight_item ) ) ); + return( MBEDTLS_ERR_SSL_ALLOC_FAILED ); + } + + if( ( msg->p = mbedtls_calloc( 1, ssl->out_msglen ) ) == NULL ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "alloc %d bytes failed", ssl->out_msglen ) ); + mbedtls_free( msg ); + return( MBEDTLS_ERR_SSL_ALLOC_FAILED ); + } + + /* Copy current handshake message with headers */ + memcpy( msg->p, ssl->out_msg, ssl->out_msglen ); + msg->len = ssl->out_msglen; + msg->type = ssl->out_msgtype; + msg->next = NULL; + + /* Append to the current flight */ + if( ssl->handshake->flight == NULL ) + ssl->handshake->flight = msg; + else + { + mbedtls_ssl_flight_item *cur = ssl->handshake->flight; + while( cur->next != NULL ) + cur = cur->next; + cur->next = msg; + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= ssl_flight_append" ) ); + return( 0 ); +} + +/* + * Free the current flight of handshake messages + */ +void mbedtls_ssl_flight_free( mbedtls_ssl_flight_item *flight ) +{ + mbedtls_ssl_flight_item *cur = flight; + mbedtls_ssl_flight_item *next; + + while( cur != NULL ) + { + next = cur->next; + + mbedtls_free( cur->p ); + mbedtls_free( cur ); + + cur = next; + } +} + +/* + * Swap transform_out and out_ctr with the alternative ones + */ +static void ssl_swap_epochs( mbedtls_ssl_context *ssl ) +{ + mbedtls_ssl_transform *tmp_transform; + unsigned char tmp_out_ctr[8]; + + if( ssl->transform_out == ssl->handshake->alt_transform_out ) + { + MBEDTLS_SSL_DEBUG_MSG( 3, ( "skip swap epochs" ) ); + return; + } + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "swap epochs" ) ); + + /* Swap transforms */ + tmp_transform = ssl->transform_out; + ssl->transform_out = ssl->handshake->alt_transform_out; + ssl->handshake->alt_transform_out = tmp_transform; + + /* Swap epoch + sequence_number */ + memcpy( tmp_out_ctr, ssl->cur_out_ctr, 8 ); + memcpy( ssl->cur_out_ctr, ssl->handshake->alt_out_ctr, 8 ); + memcpy( ssl->handshake->alt_out_ctr, tmp_out_ctr, 8 ); + + /* Adjust to the newly activated transform */ + mbedtls_ssl_update_out_pointers( ssl, ssl->transform_out ); + +#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL) + if( mbedtls_ssl_hw_record_activate != NULL ) + { + if( ( ret = mbedtls_ssl_hw_record_activate( ssl, MBEDTLS_SSL_CHANNEL_OUTBOUND ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_hw_record_activate", ret ); + return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); + } + } +#endif +} + +/* + * Retransmit the current flight of messages. + */ +int mbedtls_ssl_resend( mbedtls_ssl_context *ssl ) +{ + int ret = 0; + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> mbedtls_ssl_resend" ) ); + + ret = mbedtls_ssl_flight_transmit( ssl ); + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= mbedtls_ssl_resend" ) ); + + return( ret ); +} + +/* + * Transmit or retransmit the current flight of messages. + * + * Need to remember the current message in case flush_output returns + * WANT_WRITE, causing us to exit this function and come back later. + * This function must be called until state is no longer SENDING. + */ +int mbedtls_ssl_flight_transmit( mbedtls_ssl_context *ssl ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> mbedtls_ssl_flight_transmit" ) ); + + if( ssl->handshake->retransmit_state != MBEDTLS_SSL_RETRANS_SENDING ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "initialise flight transmission" ) ); + + ssl->handshake->cur_msg = ssl->handshake->flight; + ssl->handshake->cur_msg_p = ssl->handshake->flight->p + 12; + ssl_swap_epochs( ssl ); + + ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_SENDING; + } + + while( ssl->handshake->cur_msg != NULL ) + { + size_t max_frag_len; + const mbedtls_ssl_flight_item * const cur = ssl->handshake->cur_msg; + + int const is_finished = + ( cur->type == MBEDTLS_SSL_MSG_HANDSHAKE && + cur->p[0] == MBEDTLS_SSL_HS_FINISHED ); + + uint8_t const force_flush = ssl->disable_datagram_packing == 1 ? + SSL_FORCE_FLUSH : SSL_DONT_FORCE_FLUSH; + + /* Swap epochs before sending Finished: we can't do it after + * sending ChangeCipherSpec, in case write returns WANT_READ. + * Must be done before copying, may change out_msg pointer */ + if( is_finished && ssl->handshake->cur_msg_p == ( cur->p + 12 ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "swap epochs to send finished message" ) ); + ssl_swap_epochs( ssl ); + } + + ret = ssl_get_remaining_payload_in_datagram( ssl ); + if( ret < 0 ) + return( ret ); + max_frag_len = (size_t) ret; + + /* CCS is copied as is, while HS messages may need fragmentation */ + if( cur->type == MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC ) + { + if( max_frag_len == 0 ) + { + if( ( ret = mbedtls_ssl_flush_output( ssl ) ) != 0 ) + return( ret ); + + continue; + } + + memcpy( ssl->out_msg, cur->p, cur->len ); + ssl->out_msglen = cur->len; + ssl->out_msgtype = cur->type; + + /* Update position inside current message */ + ssl->handshake->cur_msg_p += cur->len; + } + else + { + const unsigned char * const p = ssl->handshake->cur_msg_p; + const size_t hs_len = cur->len - 12; + const size_t frag_off = p - ( cur->p + 12 ); + const size_t rem_len = hs_len - frag_off; + size_t cur_hs_frag_len, max_hs_frag_len; + + if( ( max_frag_len < 12 ) || ( max_frag_len == 12 && hs_len != 0 ) ) + { + if( is_finished ) + ssl_swap_epochs( ssl ); + + if( ( ret = mbedtls_ssl_flush_output( ssl ) ) != 0 ) + return( ret ); + + continue; + } + max_hs_frag_len = max_frag_len - 12; + + cur_hs_frag_len = rem_len > max_hs_frag_len ? + max_hs_frag_len : rem_len; + + if( frag_off == 0 && cur_hs_frag_len != hs_len ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "fragmenting handshake message (%u > %u)", + (unsigned) cur_hs_frag_len, + (unsigned) max_hs_frag_len ) ); + } + + /* Messages are stored with handshake headers as if not fragmented, + * copy beginning of headers then fill fragmentation fields. + * Handshake headers: type(1) len(3) seq(2) f_off(3) f_len(3) */ + memcpy( ssl->out_msg, cur->p, 6 ); + + ssl->out_msg[6] = ( ( frag_off >> 16 ) & 0xff ); + ssl->out_msg[7] = ( ( frag_off >> 8 ) & 0xff ); + ssl->out_msg[8] = ( ( frag_off ) & 0xff ); + + ssl->out_msg[ 9] = ( ( cur_hs_frag_len >> 16 ) & 0xff ); + ssl->out_msg[10] = ( ( cur_hs_frag_len >> 8 ) & 0xff ); + ssl->out_msg[11] = ( ( cur_hs_frag_len ) & 0xff ); + + MBEDTLS_SSL_DEBUG_BUF( 3, "handshake header", ssl->out_msg, 12 ); + + /* Copy the handshake message content and set records fields */ + memcpy( ssl->out_msg + 12, p, cur_hs_frag_len ); + ssl->out_msglen = cur_hs_frag_len + 12; + ssl->out_msgtype = cur->type; + + /* Update position inside current message */ + ssl->handshake->cur_msg_p += cur_hs_frag_len; + } + + /* If done with the current message move to the next one if any */ + if( ssl->handshake->cur_msg_p >= cur->p + cur->len ) + { + if( cur->next != NULL ) + { + ssl->handshake->cur_msg = cur->next; + ssl->handshake->cur_msg_p = cur->next->p + 12; + } + else + { + ssl->handshake->cur_msg = NULL; + ssl->handshake->cur_msg_p = NULL; + } + } + + /* Actually send the message out */ + if( ( ret = mbedtls_ssl_write_record( ssl, force_flush ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_write_record", ret ); + return( ret ); + } + } + + if( ( ret = mbedtls_ssl_flush_output( ssl ) ) != 0 ) + return( ret ); + + /* Update state and set timer */ + if( ssl->state == MBEDTLS_SSL_HANDSHAKE_OVER ) + ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_FINISHED; + else + { + ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_WAITING; + mbedtls_ssl_set_timer( ssl, ssl->handshake->retransmit_timeout ); + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= mbedtls_ssl_flight_transmit" ) ); + + return( 0 ); +} + +/* + * To be called when the last message of an incoming flight is received. + */ +void mbedtls_ssl_recv_flight_completed( mbedtls_ssl_context *ssl ) +{ + /* We won't need to resend that one any more */ + mbedtls_ssl_flight_free( ssl->handshake->flight ); + ssl->handshake->flight = NULL; + ssl->handshake->cur_msg = NULL; + + /* The next incoming flight will start with this msg_seq */ + ssl->handshake->in_flight_start_seq = ssl->handshake->in_msg_seq; + + /* We don't want to remember CCS's across flight boundaries. */ + ssl->handshake->buffering.seen_ccs = 0; + + /* Clear future message buffering structure. */ + mbedtls_ssl_buffering_free( ssl ); + + /* Cancel timer */ + mbedtls_ssl_set_timer( ssl, 0 ); + + if( ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE && + ssl->in_msg[0] == MBEDTLS_SSL_HS_FINISHED ) + { + ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_FINISHED; + } + else + ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_PREPARING; +} + +/* + * To be called when the last message of an outgoing flight is send. + */ +void mbedtls_ssl_send_flight_completed( mbedtls_ssl_context *ssl ) +{ + ssl_reset_retransmit_timeout( ssl ); + mbedtls_ssl_set_timer( ssl, ssl->handshake->retransmit_timeout ); + + if( ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE && + ssl->in_msg[0] == MBEDTLS_SSL_HS_FINISHED ) + { + ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_FINISHED; + } + else + ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_WAITING; +} +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +/* + * Handshake layer functions + */ + +/* + * Write (DTLS: or queue) current handshake (including CCS) message. + * + * - fill in handshake headers + * - update handshake checksum + * - DTLS: save message for resending + * - then pass to the record layer + * + * DTLS: except for HelloRequest, messages are only queued, and will only be + * actually sent when calling flight_transmit() or resend(). + * + * Inputs: + * - ssl->out_msglen: 4 + actual handshake message len + * (4 is the size of handshake headers for TLS) + * - ssl->out_msg[0]: the handshake type (ClientHello, ServerHello, etc) + * - ssl->out_msg + 4: the handshake message body + * + * Outputs, ie state before passing to flight_append() or write_record(): + * - ssl->out_msglen: the length of the record contents + * (including handshake headers but excluding record headers) + * - ssl->out_msg: the record contents (handshake headers + content) + */ +int mbedtls_ssl_write_handshake_msg( mbedtls_ssl_context *ssl ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + const size_t hs_len = ssl->out_msglen - 4; + const unsigned char hs_type = ssl->out_msg[0]; + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write handshake message" ) ); + + /* + * Sanity checks + */ + if( ssl->out_msgtype != MBEDTLS_SSL_MSG_HANDSHAKE && + ssl->out_msgtype != MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC ) + { + /* In SSLv3, the client might send a NoCertificate alert. */ +#if defined(MBEDTLS_SSL_PROTO_SSL3) && defined(MBEDTLS_SSL_CLI_C) + if( ! ( ssl->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 && + ssl->out_msgtype == MBEDTLS_SSL_MSG_ALERT && + ssl->conf->endpoint == MBEDTLS_SSL_IS_CLIENT ) ) +#endif /* MBEDTLS_SSL_PROTO_SSL3 && MBEDTLS_SSL_SRV_C */ + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + } + + /* Whenever we send anything different from a + * HelloRequest we should be in a handshake - double check. */ + if( ! ( ssl->out_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE && + hs_type == MBEDTLS_SSL_HS_HELLO_REQUEST ) && + ssl->handshake == NULL ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && + ssl->handshake != NULL && + ssl->handshake->retransmit_state == MBEDTLS_SSL_RETRANS_SENDING ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } +#endif + + /* Double-check that we did not exceed the bounds + * of the outgoing record buffer. + * This should never fail as the various message + * writing functions must obey the bounds of the + * outgoing record buffer, but better be safe. + * + * Note: We deliberately do not check for the MTU or MFL here. + */ + if( ssl->out_msglen > MBEDTLS_SSL_OUT_CONTENT_LEN ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "Record too large: " + "size %u, maximum %u", + (unsigned) ssl->out_msglen, + (unsigned) MBEDTLS_SSL_OUT_CONTENT_LEN ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + /* + * Fill handshake headers + */ + if( ssl->out_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE ) + { + ssl->out_msg[1] = (unsigned char)( hs_len >> 16 ); + ssl->out_msg[2] = (unsigned char)( hs_len >> 8 ); + ssl->out_msg[3] = (unsigned char)( hs_len ); + + /* + * DTLS has additional fields in the Handshake layer, + * between the length field and the actual payload: + * uint16 message_seq; + * uint24 fragment_offset; + * uint24 fragment_length; + */ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + /* Make room for the additional DTLS fields */ + if( MBEDTLS_SSL_OUT_CONTENT_LEN - ssl->out_msglen < 8 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "DTLS handshake message too large: " + "size %u, maximum %u", + (unsigned) ( hs_len ), + (unsigned) ( MBEDTLS_SSL_OUT_CONTENT_LEN - 12 ) ) ); + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + } + + memmove( ssl->out_msg + 12, ssl->out_msg + 4, hs_len ); + ssl->out_msglen += 8; + + /* Write message_seq and update it, except for HelloRequest */ + if( hs_type != MBEDTLS_SSL_HS_HELLO_REQUEST ) + { + ssl->out_msg[4] = ( ssl->handshake->out_msg_seq >> 8 ) & 0xFF; + ssl->out_msg[5] = ( ssl->handshake->out_msg_seq ) & 0xFF; + ++( ssl->handshake->out_msg_seq ); + } + else + { + ssl->out_msg[4] = 0; + ssl->out_msg[5] = 0; + } + + /* Handshake hashes are computed without fragmentation, + * so set frag_offset = 0 and frag_len = hs_len for now */ + memset( ssl->out_msg + 6, 0x00, 3 ); + memcpy( ssl->out_msg + 9, ssl->out_msg + 1, 3 ); + } +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + + /* Update running hashes of handshake messages seen */ + if( hs_type != MBEDTLS_SSL_HS_HELLO_REQUEST ) + ssl->handshake->update_checksum( ssl, ssl->out_msg, ssl->out_msglen ); + } + + /* Either send now, or just save to be sent (and resent) later */ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && + ! ( ssl->out_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE && + hs_type == MBEDTLS_SSL_HS_HELLO_REQUEST ) ) + { + if( ( ret = ssl_flight_append( ssl ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "ssl_flight_append", ret ); + return( ret ); + } + } + else +#endif + { + if( ( ret = mbedtls_ssl_write_record( ssl, SSL_FORCE_FLUSH ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "ssl_write_record", ret ); + return( ret ); + } + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= write handshake message" ) ); + + return( 0 ); +} + +/* + * Record layer functions + */ + +/* + * Write current record. + * + * Uses: + * - ssl->out_msgtype: type of the message (AppData, Handshake, Alert, CCS) + * - ssl->out_msglen: length of the record content (excl headers) + * - ssl->out_msg: record content + */ +int mbedtls_ssl_write_record( mbedtls_ssl_context *ssl, uint8_t force_flush ) +{ + int ret, done = 0; + size_t len = ssl->out_msglen; + uint8_t flush = force_flush; + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write record" ) ); + +#if defined(MBEDTLS_ZLIB_SUPPORT) + if( ssl->transform_out != NULL && + ssl->session_out->compression == MBEDTLS_SSL_COMPRESS_DEFLATE ) + { + if( ( ret = ssl_compress_buf( ssl ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "ssl_compress_buf", ret ); + return( ret ); + } + + len = ssl->out_msglen; + } +#endif /*MBEDTLS_ZLIB_SUPPORT */ + +#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL) + if( mbedtls_ssl_hw_record_write != NULL ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "going for mbedtls_ssl_hw_record_write()" ) ); + + ret = mbedtls_ssl_hw_record_write( ssl ); + if( ret != 0 && ret != MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_hw_record_write", ret ); + return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); + } + + if( ret == 0 ) + done = 1; + } +#endif /* MBEDTLS_SSL_HW_RECORD_ACCEL */ + if( !done ) + { + unsigned i; + size_t protected_record_size; + + /* Skip writing the record content type to after the encryption, + * as it may change when using the CID extension. */ + + mbedtls_ssl_write_version( ssl->major_ver, ssl->minor_ver, + ssl->conf->transport, ssl->out_hdr + 1 ); + + memcpy( ssl->out_ctr, ssl->cur_out_ctr, 8 ); + ssl->out_len[0] = (unsigned char)( len >> 8 ); + ssl->out_len[1] = (unsigned char)( len ); + + if( ssl->transform_out != NULL ) + { + mbedtls_record rec; + + rec.buf = ssl->out_iv; + rec.buf_len = MBEDTLS_SSL_OUT_BUFFER_LEN - + ( ssl->out_iv - ssl->out_buf ); + rec.data_len = ssl->out_msglen; + rec.data_offset = ssl->out_msg - rec.buf; + + memcpy( &rec.ctr[0], ssl->out_ctr, 8 ); + mbedtls_ssl_write_version( ssl->major_ver, ssl->minor_ver, + ssl->conf->transport, rec.ver ); + rec.type = ssl->out_msgtype; + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + /* The CID is set by mbedtls_ssl_encrypt_buf(). */ + rec.cid_len = 0; +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + + if( ( ret = mbedtls_ssl_encrypt_buf( ssl, ssl->transform_out, &rec, + ssl->conf->f_rng, ssl->conf->p_rng ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "ssl_encrypt_buf", ret ); + return( ret ); + } + + if( rec.data_offset != 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + /* Update the record content type and CID. */ + ssl->out_msgtype = rec.type; +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID ) + memcpy( ssl->out_cid, rec.cid, rec.cid_len ); +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + ssl->out_msglen = len = rec.data_len; + ssl->out_len[0] = (unsigned char)( rec.data_len >> 8 ); + ssl->out_len[1] = (unsigned char)( rec.data_len ); + } + + protected_record_size = len + mbedtls_ssl_out_hdr_len( ssl ); + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + /* In case of DTLS, double-check that we don't exceed + * the remaining space in the datagram. */ + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + ret = ssl_get_remaining_space_in_datagram( ssl ); + if( ret < 0 ) + return( ret ); + + if( protected_record_size > (size_t) ret ) + { + /* Should never happen */ + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + } +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + + /* Now write the potentially updated record content type. */ + ssl->out_hdr[0] = (unsigned char) ssl->out_msgtype; + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "output record: msgtype = %d, " + "version = [%d:%d], msglen = %d", + ssl->out_hdr[0], ssl->out_hdr[1], + ssl->out_hdr[2], len ) ); + + MBEDTLS_SSL_DEBUG_BUF( 4, "output record sent to network", + ssl->out_hdr, protected_record_size ); + + ssl->out_left += protected_record_size; + ssl->out_hdr += protected_record_size; + mbedtls_ssl_update_out_pointers( ssl, ssl->transform_out ); + + for( i = 8; i > mbedtls_ssl_ep_len( ssl ); i-- ) + if( ++ssl->cur_out_ctr[i - 1] != 0 ) + break; + + /* The loop goes to its end iff the counter is wrapping */ + if( i == mbedtls_ssl_ep_len( ssl ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "outgoing message counter would wrap" ) ); + return( MBEDTLS_ERR_SSL_COUNTER_WRAPPING ); + } + } + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && + flush == SSL_DONT_FORCE_FLUSH ) + { + size_t remaining; + ret = ssl_get_remaining_payload_in_datagram( ssl ); + if( ret < 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "ssl_get_remaining_payload_in_datagram", + ret ); + return( ret ); + } + + remaining = (size_t) ret; + if( remaining == 0 ) + { + flush = SSL_FORCE_FLUSH; + } + else + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Still %u bytes available in current datagram", (unsigned) remaining ) ); + } + } +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + + if( ( flush == SSL_FORCE_FLUSH ) && + ( ret = mbedtls_ssl_flush_output( ssl ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_flush_output", ret ); + return( ret ); + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= write record" ) ); + + return( 0 ); +} + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + +static int ssl_hs_is_proper_fragment( mbedtls_ssl_context *ssl ) +{ + if( ssl->in_msglen < ssl->in_hslen || + memcmp( ssl->in_msg + 6, "\0\0\0", 3 ) != 0 || + memcmp( ssl->in_msg + 9, ssl->in_msg + 1, 3 ) != 0 ) + { + return( 1 ); + } + return( 0 ); +} + +static uint32_t ssl_get_hs_frag_len( mbedtls_ssl_context const *ssl ) +{ + return( ( ssl->in_msg[9] << 16 ) | + ( ssl->in_msg[10] << 8 ) | + ssl->in_msg[11] ); +} + +static uint32_t ssl_get_hs_frag_off( mbedtls_ssl_context const *ssl ) +{ + return( ( ssl->in_msg[6] << 16 ) | + ( ssl->in_msg[7] << 8 ) | + ssl->in_msg[8] ); +} + +static int ssl_check_hs_header( mbedtls_ssl_context const *ssl ) +{ + uint32_t msg_len, frag_off, frag_len; + + msg_len = ssl_get_hs_total_len( ssl ); + frag_off = ssl_get_hs_frag_off( ssl ); + frag_len = ssl_get_hs_frag_len( ssl ); + + if( frag_off > msg_len ) + return( -1 ); + + if( frag_len > msg_len - frag_off ) + return( -1 ); + + if( frag_len + 12 > ssl->in_msglen ) + return( -1 ); + + return( 0 ); +} + +/* + * Mark bits in bitmask (used for DTLS HS reassembly) + */ +static void ssl_bitmask_set( unsigned char *mask, size_t offset, size_t len ) +{ + unsigned int start_bits, end_bits; + + start_bits = 8 - ( offset % 8 ); + if( start_bits != 8 ) + { + size_t first_byte_idx = offset / 8; + + /* Special case */ + if( len <= start_bits ) + { + for( ; len != 0; len-- ) + mask[first_byte_idx] |= 1 << ( start_bits - len ); + + /* Avoid potential issues with offset or len becoming invalid */ + return; + } + + offset += start_bits; /* Now offset % 8 == 0 */ + len -= start_bits; + + for( ; start_bits != 0; start_bits-- ) + mask[first_byte_idx] |= 1 << ( start_bits - 1 ); + } + + end_bits = len % 8; + if( end_bits != 0 ) + { + size_t last_byte_idx = ( offset + len ) / 8; + + len -= end_bits; /* Now len % 8 == 0 */ + + for( ; end_bits != 0; end_bits-- ) + mask[last_byte_idx] |= 1 << ( 8 - end_bits ); + } + + memset( mask + offset / 8, 0xFF, len / 8 ); +} + +/* + * Check that bitmask is full + */ +static int ssl_bitmask_check( unsigned char *mask, size_t len ) +{ + size_t i; + + for( i = 0; i < len / 8; i++ ) + if( mask[i] != 0xFF ) + return( -1 ); + + for( i = 0; i < len % 8; i++ ) + if( ( mask[len / 8] & ( 1 << ( 7 - i ) ) ) == 0 ) + return( -1 ); + + return( 0 ); +} + +/* msg_len does not include the handshake header */ +static size_t ssl_get_reassembly_buffer_size( size_t msg_len, + unsigned add_bitmap ) +{ + size_t alloc_len; + + alloc_len = 12; /* Handshake header */ + alloc_len += msg_len; /* Content buffer */ + + if( add_bitmap ) + alloc_len += msg_len / 8 + ( msg_len % 8 != 0 ); /* Bitmap */ + + return( alloc_len ); +} + +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +static uint32_t ssl_get_hs_total_len( mbedtls_ssl_context const *ssl ) +{ + return( ( ssl->in_msg[1] << 16 ) | + ( ssl->in_msg[2] << 8 ) | + ssl->in_msg[3] ); +} + +int mbedtls_ssl_prepare_handshake_record( mbedtls_ssl_context *ssl ) +{ + if( ssl->in_msglen < mbedtls_ssl_hs_hdr_len( ssl ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "handshake message too short: %d", + ssl->in_msglen ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + + ssl->in_hslen = mbedtls_ssl_hs_hdr_len( ssl ) + ssl_get_hs_total_len( ssl ); + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "handshake message: msglen =" + " %d, type = %d, hslen = %d", + ssl->in_msglen, ssl->in_msg[0], ssl->in_hslen ) ); + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned int recv_msg_seq = ( ssl->in_msg[4] << 8 ) | ssl->in_msg[5]; + + if( ssl_check_hs_header( ssl ) != 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "invalid handshake header" ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + + if( ssl->handshake != NULL && + ( ( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER && + recv_msg_seq != ssl->handshake->in_msg_seq ) || + ( ssl->state == MBEDTLS_SSL_HANDSHAKE_OVER && + ssl->in_msg[0] != MBEDTLS_SSL_HS_CLIENT_HELLO ) ) ) + { + if( recv_msg_seq > ssl->handshake->in_msg_seq ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "received future handshake message of sequence number %u (next %u)", + recv_msg_seq, + ssl->handshake->in_msg_seq ) ); + return( MBEDTLS_ERR_SSL_EARLY_MESSAGE ); + } + + /* Retransmit only on last message from previous flight, to avoid + * too many retransmissions. + * Besides, No sane server ever retransmits HelloVerifyRequest */ + if( recv_msg_seq == ssl->handshake->in_flight_start_seq - 1 && + ssl->in_msg[0] != MBEDTLS_SSL_HS_HELLO_VERIFY_REQUEST ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "received message from last flight, " + "message_seq = %d, start_of_flight = %d", + recv_msg_seq, + ssl->handshake->in_flight_start_seq ) ); + + if( ( ret = mbedtls_ssl_resend( ssl ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_resend", ret ); + return( ret ); + } + } + else + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "dropping out-of-sequence message: " + "message_seq = %d, expected = %d", + recv_msg_seq, + ssl->handshake->in_msg_seq ) ); + } + + return( MBEDTLS_ERR_SSL_CONTINUE_PROCESSING ); + } + /* Wait until message completion to increment in_msg_seq */ + + /* Message reassembly is handled alongside buffering of future + * messages; the commonality is that both handshake fragments and + * future messages cannot be forwarded immediately to the + * handshake logic layer. */ + if( ssl_hs_is_proper_fragment( ssl ) == 1 ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "found fragmented DTLS handshake message" ) ); + return( MBEDTLS_ERR_SSL_EARLY_MESSAGE ); + } + } + else +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + /* With TLS we don't handle fragmentation (for now) */ + if( ssl->in_msglen < ssl->in_hslen ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "TLS handshake fragmentation not supported" ) ); + return( MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE ); + } + + return( 0 ); +} + +void mbedtls_ssl_update_handshake_status( mbedtls_ssl_context *ssl ) +{ + mbedtls_ssl_handshake_params * const hs = ssl->handshake; + + if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER && hs != NULL ) + { + ssl->handshake->update_checksum( ssl, ssl->in_msg, ssl->in_hslen ); + } + + /* Handshake message is complete, increment counter */ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && + ssl->handshake != NULL ) + { + unsigned offset; + mbedtls_ssl_hs_buffer *hs_buf; + + /* Increment handshake sequence number */ + hs->in_msg_seq++; + + /* + * Clear up handshake buffering and reassembly structure. + */ + + /* Free first entry */ + ssl_buffering_free_slot( ssl, 0 ); + + /* Shift all other entries */ + for( offset = 0, hs_buf = &hs->buffering.hs[0]; + offset + 1 < MBEDTLS_SSL_MAX_BUFFERED_HS; + offset++, hs_buf++ ) + { + *hs_buf = *(hs_buf + 1); + } + + /* Create a fresh last entry */ + memset( hs_buf, 0, sizeof( mbedtls_ssl_hs_buffer ) ); + } +#endif +} + +/* + * DTLS anti-replay: RFC 6347 4.1.2.6 + * + * in_window is a field of bits numbered from 0 (lsb) to 63 (msb). + * Bit n is set iff record number in_window_top - n has been seen. + * + * Usually, in_window_top is the last record number seen and the lsb of + * in_window is set. The only exception is the initial state (record number 0 + * not seen yet). + */ +#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) +void mbedtls_ssl_dtls_replay_reset( mbedtls_ssl_context *ssl ) +{ + ssl->in_window_top = 0; + ssl->in_window = 0; +} + +static inline uint64_t ssl_load_six_bytes( unsigned char *buf ) +{ + return( ( (uint64_t) buf[0] << 40 ) | + ( (uint64_t) buf[1] << 32 ) | + ( (uint64_t) buf[2] << 24 ) | + ( (uint64_t) buf[3] << 16 ) | + ( (uint64_t) buf[4] << 8 ) | + ( (uint64_t) buf[5] ) ); +} + +static int mbedtls_ssl_dtls_record_replay_check( mbedtls_ssl_context *ssl, uint8_t *record_in_ctr ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char *original_in_ctr; + + // save original in_ctr + original_in_ctr = ssl->in_ctr; + + // use counter from record + ssl->in_ctr = record_in_ctr; + + ret = mbedtls_ssl_dtls_replay_check( (mbedtls_ssl_context const *) ssl ); + + // restore the counter + ssl->in_ctr = original_in_ctr; + + return ret; +} + +/* + * Return 0 if sequence number is acceptable, -1 otherwise + */ +int mbedtls_ssl_dtls_replay_check( mbedtls_ssl_context const *ssl ) +{ + uint64_t rec_seqnum = ssl_load_six_bytes( ssl->in_ctr + 2 ); + uint64_t bit; + + if( ssl->conf->anti_replay == MBEDTLS_SSL_ANTI_REPLAY_DISABLED ) + return( 0 ); + + if( rec_seqnum > ssl->in_window_top ) + return( 0 ); + + bit = ssl->in_window_top - rec_seqnum; + + if( bit >= 64 ) + return( -1 ); + + if( ( ssl->in_window & ( (uint64_t) 1 << bit ) ) != 0 ) + return( -1 ); + + return( 0 ); +} + +/* + * Update replay window on new validated record + */ +void mbedtls_ssl_dtls_replay_update( mbedtls_ssl_context *ssl ) +{ + uint64_t rec_seqnum = ssl_load_six_bytes( ssl->in_ctr + 2 ); + + if( ssl->conf->anti_replay == MBEDTLS_SSL_ANTI_REPLAY_DISABLED ) + return; + + if( rec_seqnum > ssl->in_window_top ) + { + /* Update window_top and the contents of the window */ + uint64_t shift = rec_seqnum - ssl->in_window_top; + + if( shift >= 64 ) + ssl->in_window = 1; + else + { + ssl->in_window <<= shift; + ssl->in_window |= 1; + } + + ssl->in_window_top = rec_seqnum; + } + else + { + /* Mark that number as seen in the current window */ + uint64_t bit = ssl->in_window_top - rec_seqnum; + + if( bit < 64 ) /* Always true, but be extra sure */ + ssl->in_window |= (uint64_t) 1 << bit; + } +} +#endif /* MBEDTLS_SSL_DTLS_ANTI_REPLAY */ + +#if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) && defined(MBEDTLS_SSL_SRV_C) +/* + * Without any SSL context, check if a datagram looks like a ClientHello with + * a valid cookie, and if it doesn't, generate a HelloVerifyRequest message. + * Both input and output include full DTLS headers. + * + * - if cookie is valid, return 0 + * - if ClientHello looks superficially valid but cookie is not, + * fill obuf and set olen, then + * return MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED + * - otherwise return a specific error code + */ +static int ssl_check_dtls_clihlo_cookie( + mbedtls_ssl_cookie_write_t *f_cookie_write, + mbedtls_ssl_cookie_check_t *f_cookie_check, + void *p_cookie, + const unsigned char *cli_id, size_t cli_id_len, + const unsigned char *in, size_t in_len, + unsigned char *obuf, size_t buf_len, size_t *olen ) +{ + size_t sid_len, cookie_len; + unsigned char *p; + + /* + * Structure of ClientHello with record and handshake headers, + * and expected values. We don't need to check a lot, more checks will be + * done when actually parsing the ClientHello - skipping those checks + * avoids code duplication and does not make cookie forging any easier. + * + * 0-0 ContentType type; copied, must be handshake + * 1-2 ProtocolVersion version; copied + * 3-4 uint16 epoch; copied, must be 0 + * 5-10 uint48 sequence_number; copied + * 11-12 uint16 length; (ignored) + * + * 13-13 HandshakeType msg_type; (ignored) + * 14-16 uint24 length; (ignored) + * 17-18 uint16 message_seq; copied + * 19-21 uint24 fragment_offset; copied, must be 0 + * 22-24 uint24 fragment_length; (ignored) + * + * 25-26 ProtocolVersion client_version; (ignored) + * 27-58 Random random; (ignored) + * 59-xx SessionID session_id; 1 byte len + sid_len content + * 60+ opaque cookie<0..2^8-1>; 1 byte len + content + * ... + * + * Minimum length is 61 bytes. + */ + if( in_len < 61 || + in[0] != MBEDTLS_SSL_MSG_HANDSHAKE || + in[3] != 0 || in[4] != 0 || + in[19] != 0 || in[20] != 0 || in[21] != 0 ) + { + return( MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO ); + } + + sid_len = in[59]; + if( sid_len > in_len - 61 ) + return( MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO ); + + cookie_len = in[60 + sid_len]; + if( cookie_len > in_len - 60 ) + return( MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO ); + + if( f_cookie_check( p_cookie, in + sid_len + 61, cookie_len, + cli_id, cli_id_len ) == 0 ) + { + /* Valid cookie */ + return( 0 ); + } + + /* + * If we get here, we've got an invalid cookie, let's prepare HVR. + * + * 0-0 ContentType type; copied + * 1-2 ProtocolVersion version; copied + * 3-4 uint16 epoch; copied + * 5-10 uint48 sequence_number; copied + * 11-12 uint16 length; olen - 13 + * + * 13-13 HandshakeType msg_type; hello_verify_request + * 14-16 uint24 length; olen - 25 + * 17-18 uint16 message_seq; copied + * 19-21 uint24 fragment_offset; copied + * 22-24 uint24 fragment_length; olen - 25 + * + * 25-26 ProtocolVersion server_version; 0xfe 0xff + * 27-27 opaque cookie<0..2^8-1>; cookie_len = olen - 27, cookie + * + * Minimum length is 28. + */ + if( buf_len < 28 ) + return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); + + /* Copy most fields and adapt others */ + memcpy( obuf, in, 25 ); + obuf[13] = MBEDTLS_SSL_HS_HELLO_VERIFY_REQUEST; + obuf[25] = 0xfe; + obuf[26] = 0xff; + + /* Generate and write actual cookie */ + p = obuf + 28; + if( f_cookie_write( p_cookie, + &p, obuf + buf_len, cli_id, cli_id_len ) != 0 ) + { + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + *olen = p - obuf; + + /* Go back and fill length fields */ + obuf[27] = (unsigned char)( *olen - 28 ); + + obuf[14] = obuf[22] = (unsigned char)( ( *olen - 25 ) >> 16 ); + obuf[15] = obuf[23] = (unsigned char)( ( *olen - 25 ) >> 8 ); + obuf[16] = obuf[24] = (unsigned char)( ( *olen - 25 ) ); + + obuf[11] = (unsigned char)( ( *olen - 13 ) >> 8 ); + obuf[12] = (unsigned char)( ( *olen - 13 ) ); + + return( MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED ); +} + +/* + * Handle possible client reconnect with the same UDP quadruplet + * (RFC 6347 Section 4.2.8). + * + * Called by ssl_parse_record_header() in case we receive an epoch 0 record + * that looks like a ClientHello. + * + * - if the input looks like a ClientHello without cookies, + * send back HelloVerifyRequest, then + * return MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED + * - if the input looks like a ClientHello with a valid cookie, + * reset the session of the current context, and + * return MBEDTLS_ERR_SSL_CLIENT_RECONNECT + * - if anything goes wrong, return a specific error code + * + * mbedtls_ssl_read_record() will ignore the record if anything else than + * MBEDTLS_ERR_SSL_CLIENT_RECONNECT or 0 is returned, although this function + * cannot not return 0. + */ +static int ssl_handle_possible_reconnect( mbedtls_ssl_context *ssl ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t len; + + if( ssl->conf->f_cookie_write == NULL || + ssl->conf->f_cookie_check == NULL ) + { + /* If we can't use cookies to verify reachability of the peer, + * drop the record. */ + return( 0 ); + } + + ret = ssl_check_dtls_clihlo_cookie( + ssl->conf->f_cookie_write, + ssl->conf->f_cookie_check, + ssl->conf->p_cookie, + ssl->cli_id, ssl->cli_id_len, + ssl->in_buf, ssl->in_left, + ssl->out_buf, MBEDTLS_SSL_OUT_CONTENT_LEN, &len ); + + MBEDTLS_SSL_DEBUG_RET( 2, "ssl_check_dtls_clihlo_cookie", ret ); + + if( ret == MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED ) + { + /* Don't check write errors as we can't do anything here. + * If the error is permanent we'll catch it later, + * if it's not, then hopefully it'll work next time. */ + (void) ssl->f_send( ssl->p_bio, ssl->out_buf, len ); + ret = 0; + } + + if( ret == 0 ) + { + /* Got a valid cookie, partially reset context */ + if( ( ret = mbedtls_ssl_session_reset_int( ssl, 1 ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "reset", ret ); + return( ret ); + } + + return( MBEDTLS_ERR_SSL_CLIENT_RECONNECT ); + } + + return( ret ); +} +#endif /* MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE && MBEDTLS_SSL_SRV_C */ + +static int ssl_check_record_type( uint8_t record_type ) +{ + if( record_type != MBEDTLS_SSL_MSG_HANDSHAKE && + record_type != MBEDTLS_SSL_MSG_ALERT && + record_type != MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC && + record_type != MBEDTLS_SSL_MSG_APPLICATION_DATA ) + { + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + + return( 0 ); +} + +/* + * ContentType type; + * ProtocolVersion version; + * uint16 epoch; // DTLS only + * uint48 sequence_number; // DTLS only + * uint16 length; + * + * Return 0 if header looks sane (and, for DTLS, the record is expected) + * MBEDTLS_ERR_SSL_INVALID_RECORD if the header looks bad, + * MBEDTLS_ERR_SSL_UNEXPECTED_RECORD (DTLS only) if sane but unexpected. + * + * With DTLS, mbedtls_ssl_read_record() will: + * 1. proceed with the record if this function returns 0 + * 2. drop only the current record if this function returns UNEXPECTED_RECORD + * 3. return CLIENT_RECONNECT if this function return that value + * 4. drop the whole datagram if this function returns anything else. + * Point 2 is needed when the peer is resending, and we have already received + * the first record from a datagram but are still waiting for the others. + */ +static int ssl_parse_record_header( mbedtls_ssl_context const *ssl, + unsigned char *buf, + size_t len, + mbedtls_record *rec ) +{ + int major_ver, minor_ver; + + size_t const rec_hdr_type_offset = 0; + size_t const rec_hdr_type_len = 1; + + size_t const rec_hdr_version_offset = rec_hdr_type_offset + + rec_hdr_type_len; + size_t const rec_hdr_version_len = 2; + + size_t const rec_hdr_ctr_len = 8; +#if defined(MBEDTLS_SSL_PROTO_DTLS) + uint32_t rec_epoch; + size_t const rec_hdr_ctr_offset = rec_hdr_version_offset + + rec_hdr_version_len; + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + size_t const rec_hdr_cid_offset = rec_hdr_ctr_offset + + rec_hdr_ctr_len; + size_t rec_hdr_cid_len = 0; +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + + size_t rec_hdr_len_offset; /* To be determined */ + size_t const rec_hdr_len_len = 2; + + /* + * Check minimum lengths for record header. + */ + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + rec_hdr_len_offset = rec_hdr_ctr_offset + rec_hdr_ctr_len; + } + else +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + { + rec_hdr_len_offset = rec_hdr_version_offset + rec_hdr_version_len; + } + + if( len < rec_hdr_len_offset + rec_hdr_len_len ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "datagram of length %u too small to hold DTLS record header of length %u", + (unsigned) len, + (unsigned)( rec_hdr_len_len + rec_hdr_len_len ) ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + + /* + * Parse and validate record content type + */ + + rec->type = buf[ rec_hdr_type_offset ]; + + /* Check record content type */ +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + rec->cid_len = 0; + + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && + ssl->conf->cid_len != 0 && + rec->type == MBEDTLS_SSL_MSG_CID ) + { + /* Shift pointers to account for record header including CID + * struct { + * ContentType special_type = tls12_cid; + * ProtocolVersion version; + * uint16 epoch; + * uint48 sequence_number; + * opaque cid[cid_length]; // Additional field compared to + * // default DTLS record format + * uint16 length; + * opaque enc_content[DTLSCiphertext.length]; + * } DTLSCiphertext; + */ + + /* So far, we only support static CID lengths + * fixed in the configuration. */ + rec_hdr_cid_len = ssl->conf->cid_len; + rec_hdr_len_offset += rec_hdr_cid_len; + + if( len < rec_hdr_len_offset + rec_hdr_len_len ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "datagram of length %u too small to hold DTLS record header including CID, length %u", + (unsigned) len, + (unsigned)( rec_hdr_len_offset + rec_hdr_len_len ) ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + + /* configured CID len is guaranteed at most 255, see + * MBEDTLS_SSL_CID_OUT_LEN_MAX in check_config.h */ + rec->cid_len = (uint8_t) rec_hdr_cid_len; + memcpy( rec->cid, buf + rec_hdr_cid_offset, rec_hdr_cid_len ); + } + else +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + { + if( ssl_check_record_type( rec->type ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "unknown record type %u", + (unsigned) rec->type ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + } + + /* + * Parse and validate record version + */ + + rec->ver[0] = buf[ rec_hdr_version_offset + 0 ]; + rec->ver[1] = buf[ rec_hdr_version_offset + 1 ]; + mbedtls_ssl_read_version( &major_ver, &minor_ver, + ssl->conf->transport, + &rec->ver[0] ); + + if( major_ver != ssl->major_ver ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "major version mismatch" ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + + if( minor_ver > ssl->conf->max_minor_ver ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "minor version mismatch" ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + + /* + * Parse/Copy record sequence number. + */ + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + /* Copy explicit record sequence number from input buffer. */ + memcpy( &rec->ctr[0], buf + rec_hdr_ctr_offset, + rec_hdr_ctr_len ); + } + else +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + { + /* Copy implicit record sequence number from SSL context structure. */ + memcpy( &rec->ctr[0], ssl->in_ctr, rec_hdr_ctr_len ); + } + + /* + * Parse record length. + */ + + rec->data_offset = rec_hdr_len_offset + rec_hdr_len_len; + rec->data_len = ( (size_t) buf[ rec_hdr_len_offset + 0 ] << 8 ) | + ( (size_t) buf[ rec_hdr_len_offset + 1 ] << 0 ); + MBEDTLS_SSL_DEBUG_BUF( 4, "input record header", buf, rec->data_offset ); + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "input record: msgtype = %d, " + "version = [%d:%d], msglen = %d", + rec->type, + major_ver, minor_ver, rec->data_len ) ); + + rec->buf = buf; + rec->buf_len = rec->data_offset + rec->data_len; + + if( rec->data_len == 0 ) + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + + /* + * DTLS-related tests. + * Check epoch before checking length constraint because + * the latter varies with the epoch. E.g., if a ChangeCipherSpec + * message gets duplicated before the corresponding Finished message, + * the second ChangeCipherSpec should be discarded because it belongs + * to an old epoch, but not because its length is shorter than + * the minimum record length for packets using the new record transform. + * Note that these two kinds of failures are handled differently, + * as an unexpected record is silently skipped but an invalid + * record leads to the entire datagram being dropped. + */ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + rec_epoch = ( rec->ctr[0] << 8 ) | rec->ctr[1]; + + /* Check that the datagram is large enough to contain a record + * of the advertised length. */ + if( len < rec->data_offset + rec->data_len ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "Datagram of length %u too small to contain record of advertised length %u.", + (unsigned) len, + (unsigned)( rec->data_offset + rec->data_len ) ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + + /* Records from other, non-matching epochs are silently discarded. + * (The case of same-port Client reconnects must be considered in + * the caller). */ + if( rec_epoch != ssl->in_epoch ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "record from another epoch: " + "expected %d, received %d", + ssl->in_epoch, rec_epoch ) ); + + /* Records from the next epoch are considered for buffering + * (concretely: early Finished messages). */ + if( rec_epoch == (unsigned) ssl->in_epoch + 1 ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Consider record for buffering" ) ); + return( MBEDTLS_ERR_SSL_EARLY_MESSAGE ); + } + + return( MBEDTLS_ERR_SSL_UNEXPECTED_RECORD ); + } +#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) + /* For records from the correct epoch, check whether their + * sequence number has been seen before. */ + else if( mbedtls_ssl_dtls_record_replay_check( (mbedtls_ssl_context *) ssl, + &rec->ctr[0] ) != 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "replayed record" ) ); + return( MBEDTLS_ERR_SSL_UNEXPECTED_RECORD ); + } +#endif + } +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + + return( 0 ); +} + + +#if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) && defined(MBEDTLS_SSL_SRV_C) +static int ssl_check_client_reconnect( mbedtls_ssl_context *ssl ) +{ + unsigned int rec_epoch = ( ssl->in_ctr[0] << 8 ) | ssl->in_ctr[1]; + + /* + * Check for an epoch 0 ClientHello. We can't use in_msg here to + * access the first byte of record content (handshake type), as we + * have an active transform (possibly iv_len != 0), so use the + * fact that the record header len is 13 instead. + */ + if( rec_epoch == 0 && + ssl->conf->endpoint == MBEDTLS_SSL_IS_SERVER && + ssl->state == MBEDTLS_SSL_HANDSHAKE_OVER && + ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE && + ssl->in_left > 13 && + ssl->in_buf[13] == MBEDTLS_SSL_HS_CLIENT_HELLO ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "possible client reconnect " + "from the same port" ) ); + return( ssl_handle_possible_reconnect( ssl ) ); + } + + return( 0 ); +} +#endif /* MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE && MBEDTLS_SSL_SRV_C */ + +/* + * If applicable, decrypt record content + */ +static int ssl_prepare_record_content( mbedtls_ssl_context *ssl, + mbedtls_record *rec ) +{ + int ret, done = 0; + + MBEDTLS_SSL_DEBUG_BUF( 4, "input record from network", + rec->buf, rec->buf_len ); + +#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL) + if( mbedtls_ssl_hw_record_read != NULL ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "going for mbedtls_ssl_hw_record_read()" ) ); + + ret = mbedtls_ssl_hw_record_read( ssl ); + if( ret != 0 && ret != MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_hw_record_read", ret ); + return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); + } + + if( ret == 0 ) + done = 1; + } +#endif /* MBEDTLS_SSL_HW_RECORD_ACCEL */ + if( !done && ssl->transform_in != NULL ) + { + unsigned char const old_msg_type = rec->type; + + if( ( ret = mbedtls_ssl_decrypt_buf( ssl, ssl->transform_in, + rec ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "ssl_decrypt_buf", ret ); + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + if( ret == MBEDTLS_ERR_SSL_UNEXPECTED_CID && + ssl->conf->ignore_unexpected_cid + == MBEDTLS_SSL_UNEXPECTED_CID_IGNORE ) + { + MBEDTLS_SSL_DEBUG_MSG( 3, ( "ignoring unexpected CID" ) ); + ret = MBEDTLS_ERR_SSL_CONTINUE_PROCESSING; + } +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + + return( ret ); + } + + if( old_msg_type != rec->type ) + { + MBEDTLS_SSL_DEBUG_MSG( 4, ( "record type after decrypt (before %d): %d", + old_msg_type, rec->type ) ); + } + + MBEDTLS_SSL_DEBUG_BUF( 4, "input payload after decrypt", + rec->buf + rec->data_offset, rec->data_len ); + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + /* We have already checked the record content type + * in ssl_parse_record_header(), failing or silently + * dropping the record in the case of an unknown type. + * + * Since with the use of CIDs, the record content type + * might change during decryption, re-check the record + * content type, but treat a failure as fatal this time. */ + if( ssl_check_record_type( rec->type ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "unknown record type" ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + + if( rec->data_len == 0 ) + { +#if defined(MBEDTLS_SSL_PROTO_TLS1_2) + if( ssl->minor_ver == MBEDTLS_SSL_MINOR_VERSION_3 + && rec->type != MBEDTLS_SSL_MSG_APPLICATION_DATA ) + { + /* TLS v1.2 explicitly disallows zero-length messages which are not application data */ + MBEDTLS_SSL_DEBUG_MSG( 1, ( "invalid zero-length message type: %d", ssl->in_msgtype ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } +#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ + + ssl->nb_zero++; + + /* + * Three or more empty messages may be a DoS attack + * (excessive CPU consumption). + */ + if( ssl->nb_zero > 3 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "received four consecutive empty " + "messages, possible DoS attack" ) ); + /* Treat the records as if they were not properly authenticated, + * thereby failing the connection if we see more than allowed + * by the configured bad MAC threshold. */ + return( MBEDTLS_ERR_SSL_INVALID_MAC ); + } + } + else + ssl->nb_zero = 0; + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + ; /* in_ctr read from peer, not maintained internally */ + } + else +#endif + { + unsigned i; + for( i = 8; i > mbedtls_ssl_ep_len( ssl ); i-- ) + if( ++ssl->in_ctr[i - 1] != 0 ) + break; + + /* The loop goes to its end iff the counter is wrapping */ + if( i == mbedtls_ssl_ep_len( ssl ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "incoming message counter would wrap" ) ); + return( MBEDTLS_ERR_SSL_COUNTER_WRAPPING ); + } + } + + } + +#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + mbedtls_ssl_dtls_replay_update( ssl ); + } +#endif + + /* Check actual (decrypted) record content length against + * configured maximum. */ + if( ssl->in_msglen > MBEDTLS_SSL_IN_CONTENT_LEN ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad message length" ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + + return( 0 ); +} + +/* + * Read a record. + * + * Silently ignore non-fatal alert (and for DTLS, invalid records as well, + * RFC 6347 4.1.2.7) and continue reading until a valid record is found. + * + */ + +/* Helper functions for mbedtls_ssl_read_record(). */ +static int ssl_consume_current_message( mbedtls_ssl_context *ssl ); +static int ssl_get_next_record( mbedtls_ssl_context *ssl ); +static int ssl_record_is_in_progress( mbedtls_ssl_context *ssl ); + +int mbedtls_ssl_read_record( mbedtls_ssl_context *ssl, + unsigned update_hs_digest ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> read record" ) ); + + if( ssl->keep_current_message == 0 ) + { + do { + + ret = ssl_consume_current_message( ssl ); + if( ret != 0 ) + return( ret ); + + if( ssl_record_is_in_progress( ssl ) == 0 ) + { +#if defined(MBEDTLS_SSL_PROTO_DTLS) + int have_buffered = 0; + + /* We only check for buffered messages if the + * current datagram is fully consumed. */ + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && + ssl_next_record_is_in_datagram( ssl ) == 0 ) + { + if( ssl_load_buffered_message( ssl ) == 0 ) + have_buffered = 1; + } + + if( have_buffered == 0 ) +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + { + ret = ssl_get_next_record( ssl ); + if( ret == MBEDTLS_ERR_SSL_CONTINUE_PROCESSING ) + continue; + + if( ret != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, ( "ssl_get_next_record" ), ret ); + return( ret ); + } + } + } + + ret = mbedtls_ssl_handle_message_type( ssl ); + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ret == MBEDTLS_ERR_SSL_EARLY_MESSAGE ) + { + /* Buffer future message */ + ret = ssl_buffer_message( ssl ); + if( ret != 0 ) + return( ret ); + + ret = MBEDTLS_ERR_SSL_CONTINUE_PROCESSING; + } +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + + } while( MBEDTLS_ERR_SSL_NON_FATAL == ret || + MBEDTLS_ERR_SSL_CONTINUE_PROCESSING == ret ); + + if( 0 != ret ) + { + MBEDTLS_SSL_DEBUG_RET( 1, ( "mbedtls_ssl_handle_message_type" ), ret ); + return( ret ); + } + + if( ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE && + update_hs_digest == 1 ) + { + mbedtls_ssl_update_handshake_status( ssl ); + } + } + else + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "reuse previously read message" ) ); + ssl->keep_current_message = 0; + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= read record" ) ); + + return( 0 ); +} + +#if defined(MBEDTLS_SSL_PROTO_DTLS) +static int ssl_next_record_is_in_datagram( mbedtls_ssl_context *ssl ) +{ + if( ssl->in_left > ssl->next_record_offset ) + return( 1 ); + + return( 0 ); +} + +static int ssl_load_buffered_message( mbedtls_ssl_context *ssl ) +{ + mbedtls_ssl_handshake_params * const hs = ssl->handshake; + mbedtls_ssl_hs_buffer * hs_buf; + int ret = 0; + + if( hs == NULL ) + return( -1 ); + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> ssl_load_buffered_messsage" ) ); + + if( ssl->state == MBEDTLS_SSL_CLIENT_CHANGE_CIPHER_SPEC || + ssl->state == MBEDTLS_SSL_SERVER_CHANGE_CIPHER_SPEC ) + { + /* Check if we have seen a ChangeCipherSpec before. + * If yes, synthesize a CCS record. */ + if( !hs->buffering.seen_ccs ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "CCS not seen in the current flight" ) ); + ret = -1; + goto exit; + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Injecting buffered CCS message" ) ); + ssl->in_msgtype = MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC; + ssl->in_msglen = 1; + ssl->in_msg[0] = 1; + + /* As long as they are equal, the exact value doesn't matter. */ + ssl->in_left = 0; + ssl->next_record_offset = 0; + + hs->buffering.seen_ccs = 0; + goto exit; + } + +#if defined(MBEDTLS_DEBUG_C) + /* Debug only */ + { + unsigned offset; + for( offset = 1; offset < MBEDTLS_SSL_MAX_BUFFERED_HS; offset++ ) + { + hs_buf = &hs->buffering.hs[offset]; + if( hs_buf->is_valid == 1 ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Future message with sequence number %u %s buffered.", + hs->in_msg_seq + offset, + hs_buf->is_complete ? "fully" : "partially" ) ); + } + } + } +#endif /* MBEDTLS_DEBUG_C */ + + /* Check if we have buffered and/or fully reassembled the + * next handshake message. */ + hs_buf = &hs->buffering.hs[0]; + if( ( hs_buf->is_valid == 1 ) && ( hs_buf->is_complete == 1 ) ) + { + /* Synthesize a record containing the buffered HS message. */ + size_t msg_len = ( hs_buf->data[1] << 16 ) | + ( hs_buf->data[2] << 8 ) | + hs_buf->data[3]; + + /* Double-check that we haven't accidentally buffered + * a message that doesn't fit into the input buffer. */ + if( msg_len + 12 > MBEDTLS_SSL_IN_CONTENT_LEN ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Next handshake message has been buffered - load" ) ); + MBEDTLS_SSL_DEBUG_BUF( 3, "Buffered handshake message (incl. header)", + hs_buf->data, msg_len + 12 ); + + ssl->in_msgtype = MBEDTLS_SSL_MSG_HANDSHAKE; + ssl->in_hslen = msg_len + 12; + ssl->in_msglen = msg_len + 12; + memcpy( ssl->in_msg, hs_buf->data, ssl->in_hslen ); + + ret = 0; + goto exit; + } + else + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Next handshake message %u not or only partially bufffered", + hs->in_msg_seq ) ); + } + + ret = -1; + +exit: + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= ssl_load_buffered_message" ) ); + return( ret ); +} + +static int ssl_buffer_make_space( mbedtls_ssl_context *ssl, + size_t desired ) +{ + int offset; + mbedtls_ssl_handshake_params * const hs = ssl->handshake; + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Attempt to free buffered messages to have %u bytes available", + (unsigned) desired ) ); + + /* Get rid of future records epoch first, if such exist. */ + ssl_free_buffered_record( ssl ); + + /* Check if we have enough space available now. */ + if( desired <= ( MBEDTLS_SSL_DTLS_MAX_BUFFERING - + hs->buffering.total_bytes_buffered ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Enough space available after freeing future epoch record" ) ); + return( 0 ); + } + + /* We don't have enough space to buffer the next expected handshake + * message. Remove buffers used for future messages to gain space, + * starting with the most distant one. */ + for( offset = MBEDTLS_SSL_MAX_BUFFERED_HS - 1; + offset >= 0; offset-- ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Free buffering slot %d to make space for reassembly of next handshake message", + offset ) ); + + ssl_buffering_free_slot( ssl, (uint8_t) offset ); + + /* Check if we have enough space available now. */ + if( desired <= ( MBEDTLS_SSL_DTLS_MAX_BUFFERING - + hs->buffering.total_bytes_buffered ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Enough space available after freeing buffered HS messages" ) ); + return( 0 ); + } + } + + return( -1 ); +} + +static int ssl_buffer_message( mbedtls_ssl_context *ssl ) +{ + int ret = 0; + mbedtls_ssl_handshake_params * const hs = ssl->handshake; + + if( hs == NULL ) + return( 0 ); + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> ssl_buffer_message" ) ); + + switch( ssl->in_msgtype ) + { + case MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC: + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Remember CCS message" ) ); + + hs->buffering.seen_ccs = 1; + break; + + case MBEDTLS_SSL_MSG_HANDSHAKE: + { + unsigned recv_msg_seq_offset; + unsigned recv_msg_seq = ( ssl->in_msg[4] << 8 ) | ssl->in_msg[5]; + mbedtls_ssl_hs_buffer *hs_buf; + size_t msg_len = ssl->in_hslen - 12; + + /* We should never receive an old handshake + * message - double-check nonetheless. */ + if( recv_msg_seq < ssl->handshake->in_msg_seq ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + recv_msg_seq_offset = recv_msg_seq - ssl->handshake->in_msg_seq; + if( recv_msg_seq_offset >= MBEDTLS_SSL_MAX_BUFFERED_HS ) + { + /* Silently ignore -- message too far in the future */ + MBEDTLS_SSL_DEBUG_MSG( 2, + ( "Ignore future HS message with sequence number %u, " + "buffering window %u - %u", + recv_msg_seq, ssl->handshake->in_msg_seq, + ssl->handshake->in_msg_seq + MBEDTLS_SSL_MAX_BUFFERED_HS - 1 ) ); + + goto exit; + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Buffering HS message with sequence number %u, offset %u ", + recv_msg_seq, recv_msg_seq_offset ) ); + + hs_buf = &hs->buffering.hs[ recv_msg_seq_offset ]; + + /* Check if the buffering for this seq nr has already commenced. */ + if( !hs_buf->is_valid ) + { + size_t reassembly_buf_sz; + + hs_buf->is_fragmented = + ( ssl_hs_is_proper_fragment( ssl ) == 1 ); + + /* We copy the message back into the input buffer + * after reassembly, so check that it's not too large. + * This is an implementation-specific limitation + * and not one from the standard, hence it is not + * checked in ssl_check_hs_header(). */ + if( msg_len + 12 > MBEDTLS_SSL_IN_CONTENT_LEN ) + { + /* Ignore message */ + goto exit; + } + + /* Check if we have enough space to buffer the message. */ + if( hs->buffering.total_bytes_buffered > + MBEDTLS_SSL_DTLS_MAX_BUFFERING ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + reassembly_buf_sz = ssl_get_reassembly_buffer_size( msg_len, + hs_buf->is_fragmented ); + + if( reassembly_buf_sz > ( MBEDTLS_SSL_DTLS_MAX_BUFFERING - + hs->buffering.total_bytes_buffered ) ) + { + if( recv_msg_seq_offset > 0 ) + { + /* If we can't buffer a future message because + * of space limitations -- ignore. */ + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Buffering of future message of size %u would exceed the compile-time limit %u (already %u bytes buffered) -- ignore\n", + (unsigned) msg_len, MBEDTLS_SSL_DTLS_MAX_BUFFERING, + (unsigned) hs->buffering.total_bytes_buffered ) ); + goto exit; + } + else + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Buffering of future message of size %u would exceed the compile-time limit %u (already %u bytes buffered) -- attempt to make space by freeing buffered future messages\n", + (unsigned) msg_len, MBEDTLS_SSL_DTLS_MAX_BUFFERING, + (unsigned) hs->buffering.total_bytes_buffered ) ); + } + + if( ssl_buffer_make_space( ssl, reassembly_buf_sz ) != 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Reassembly of next message of size %u (%u with bitmap) would exceed the compile-time limit %u (already %u bytes buffered) -- fail\n", + (unsigned) msg_len, + (unsigned) reassembly_buf_sz, + MBEDTLS_SSL_DTLS_MAX_BUFFERING, + (unsigned) hs->buffering.total_bytes_buffered ) ); + ret = MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL; + goto exit; + } + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "initialize reassembly, total length = %d", + msg_len ) ); + + hs_buf->data = mbedtls_calloc( 1, reassembly_buf_sz ); + if( hs_buf->data == NULL ) + { + ret = MBEDTLS_ERR_SSL_ALLOC_FAILED; + goto exit; + } + hs_buf->data_len = reassembly_buf_sz; + + /* Prepare final header: copy msg_type, length and message_seq, + * then add standardised fragment_offset and fragment_length */ + memcpy( hs_buf->data, ssl->in_msg, 6 ); + memset( hs_buf->data + 6, 0, 3 ); + memcpy( hs_buf->data + 9, hs_buf->data + 1, 3 ); + + hs_buf->is_valid = 1; + + hs->buffering.total_bytes_buffered += reassembly_buf_sz; + } + else + { + /* Make sure msg_type and length are consistent */ + if( memcmp( hs_buf->data, ssl->in_msg, 4 ) != 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "Fragment header mismatch - ignore" ) ); + /* Ignore */ + goto exit; + } + } + + if( !hs_buf->is_complete ) + { + size_t frag_len, frag_off; + unsigned char * const msg = hs_buf->data + 12; + + /* + * Check and copy current fragment + */ + + /* Validation of header fields already done in + * mbedtls_ssl_prepare_handshake_record(). */ + frag_off = ssl_get_hs_frag_off( ssl ); + frag_len = ssl_get_hs_frag_len( ssl ); + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "adding fragment, offset = %d, length = %d", + frag_off, frag_len ) ); + memcpy( msg + frag_off, ssl->in_msg + 12, frag_len ); + + if( hs_buf->is_fragmented ) + { + unsigned char * const bitmask = msg + msg_len; + ssl_bitmask_set( bitmask, frag_off, frag_len ); + hs_buf->is_complete = ( ssl_bitmask_check( bitmask, + msg_len ) == 0 ); + } + else + { + hs_buf->is_complete = 1; + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "message %scomplete", + hs_buf->is_complete ? "" : "not yet " ) ); + } + + break; + } + + default: + /* We don't buffer other types of messages. */ + break; + } + +exit: + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= ssl_buffer_message" ) ); + return( ret ); +} +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +static int ssl_consume_current_message( mbedtls_ssl_context *ssl ) +{ + /* + * Consume last content-layer message and potentially + * update in_msglen which keeps track of the contents' + * consumption state. + * + * (1) Handshake messages: + * Remove last handshake message, move content + * and adapt in_msglen. + * + * (2) Alert messages: + * Consume whole record content, in_msglen = 0. + * + * (3) Change cipher spec: + * Consume whole record content, in_msglen = 0. + * + * (4) Application data: + * Don't do anything - the record layer provides + * the application data as a stream transport + * and consumes through mbedtls_ssl_read only. + * + */ + + /* Case (1): Handshake messages */ + if( ssl->in_hslen != 0 ) + { + /* Hard assertion to be sure that no application data + * is in flight, as corrupting ssl->in_msglen during + * ssl->in_offt != NULL is fatal. */ + if( ssl->in_offt != NULL ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + /* + * Get next Handshake message in the current record + */ + + /* Notes: + * (1) in_hslen is not necessarily the size of the + * current handshake content: If DTLS handshake + * fragmentation is used, that's the fragment + * size instead. Using the total handshake message + * size here is faulty and should be changed at + * some point. + * (2) While it doesn't seem to cause problems, one + * has to be very careful not to assume that in_hslen + * is always <= in_msglen in a sensible communication. + * Again, it's wrong for DTLS handshake fragmentation. + * The following check is therefore mandatory, and + * should not be treated as a silently corrected assertion. + * Additionally, ssl->in_hslen might be arbitrarily out of + * bounds after handling a DTLS message with an unexpected + * sequence number, see mbedtls_ssl_prepare_handshake_record. + */ + if( ssl->in_hslen < ssl->in_msglen ) + { + ssl->in_msglen -= ssl->in_hslen; + memmove( ssl->in_msg, ssl->in_msg + ssl->in_hslen, + ssl->in_msglen ); + + MBEDTLS_SSL_DEBUG_BUF( 4, "remaining content in record", + ssl->in_msg, ssl->in_msglen ); + } + else + { + ssl->in_msglen = 0; + } + + ssl->in_hslen = 0; + } + /* Case (4): Application data */ + else if( ssl->in_offt != NULL ) + { + return( 0 ); + } + /* Everything else (CCS & Alerts) */ + else + { + ssl->in_msglen = 0; + } + + return( 0 ); +} + +static int ssl_record_is_in_progress( mbedtls_ssl_context *ssl ) +{ + if( ssl->in_msglen > 0 ) + return( 1 ); + + return( 0 ); +} + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + +static void ssl_free_buffered_record( mbedtls_ssl_context *ssl ) +{ + mbedtls_ssl_handshake_params * const hs = ssl->handshake; + if( hs == NULL ) + return; + + if( hs->buffering.future_record.data != NULL ) + { + hs->buffering.total_bytes_buffered -= + hs->buffering.future_record.len; + + mbedtls_free( hs->buffering.future_record.data ); + hs->buffering.future_record.data = NULL; + } +} + +static int ssl_load_buffered_record( mbedtls_ssl_context *ssl ) +{ + mbedtls_ssl_handshake_params * const hs = ssl->handshake; + unsigned char * rec; + size_t rec_len; + unsigned rec_epoch; + + if( ssl->conf->transport != MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + return( 0 ); + + if( hs == NULL ) + return( 0 ); + + rec = hs->buffering.future_record.data; + rec_len = hs->buffering.future_record.len; + rec_epoch = hs->buffering.future_record.epoch; + + if( rec == NULL ) + return( 0 ); + + /* Only consider loading future records if the + * input buffer is empty. */ + if( ssl_next_record_is_in_datagram( ssl ) == 1 ) + return( 0 ); + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> ssl_load_buffered_record" ) ); + + if( rec_epoch != ssl->in_epoch ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Buffered record not from current epoch." ) ); + goto exit; + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Found buffered record from current epoch - load" ) ); + + /* Double-check that the record is not too large */ + if( rec_len > MBEDTLS_SSL_IN_BUFFER_LEN - + (size_t)( ssl->in_hdr - ssl->in_buf ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + memcpy( ssl->in_hdr, rec, rec_len ); + ssl->in_left = rec_len; + ssl->next_record_offset = 0; + + ssl_free_buffered_record( ssl ); + +exit: + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= ssl_load_buffered_record" ) ); + return( 0 ); +} + +static int ssl_buffer_future_record( mbedtls_ssl_context *ssl, + mbedtls_record const *rec ) +{ + mbedtls_ssl_handshake_params * const hs = ssl->handshake; + + /* Don't buffer future records outside handshakes. */ + if( hs == NULL ) + return( 0 ); + + /* Only buffer handshake records (we are only interested + * in Finished messages). */ + if( rec->type != MBEDTLS_SSL_MSG_HANDSHAKE ) + return( 0 ); + + /* Don't buffer more than one future epoch record. */ + if( hs->buffering.future_record.data != NULL ) + return( 0 ); + + /* Don't buffer record if there's not enough buffering space remaining. */ + if( rec->buf_len > ( MBEDTLS_SSL_DTLS_MAX_BUFFERING - + hs->buffering.total_bytes_buffered ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Buffering of future epoch record of size %u would exceed the compile-time limit %u (already %u bytes buffered) -- ignore\n", + (unsigned) rec->buf_len, MBEDTLS_SSL_DTLS_MAX_BUFFERING, + (unsigned) hs->buffering.total_bytes_buffered ) ); + return( 0 ); + } + + /* Buffer record */ + MBEDTLS_SSL_DEBUG_MSG( 2, ( "Buffer record from epoch %u", + ssl->in_epoch + 1 ) ); + MBEDTLS_SSL_DEBUG_BUF( 3, "Buffered record", rec->buf, rec->buf_len ); + + /* ssl_parse_record_header() only considers records + * of the next epoch as candidates for buffering. */ + hs->buffering.future_record.epoch = ssl->in_epoch + 1; + hs->buffering.future_record.len = rec->buf_len; + + hs->buffering.future_record.data = + mbedtls_calloc( 1, hs->buffering.future_record.len ); + if( hs->buffering.future_record.data == NULL ) + { + /* If we run out of RAM trying to buffer a + * record from the next epoch, just ignore. */ + return( 0 ); + } + + memcpy( hs->buffering.future_record.data, rec->buf, rec->buf_len ); + + hs->buffering.total_bytes_buffered += rec->buf_len; + return( 0 ); +} + +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +static int ssl_get_next_record( mbedtls_ssl_context *ssl ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + mbedtls_record rec; + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + /* We might have buffered a future record; if so, + * and if the epoch matches now, load it. + * On success, this call will set ssl->in_left to + * the length of the buffered record, so that + * the calls to ssl_fetch_input() below will + * essentially be no-ops. */ + ret = ssl_load_buffered_record( ssl ); + if( ret != 0 ) + return( ret ); +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + + /* Ensure that we have enough space available for the default form + * of TLS / DTLS record headers (5 Bytes for TLS, 13 Bytes for DTLS, + * with no space for CIDs counted in). */ + ret = mbedtls_ssl_fetch_input( ssl, mbedtls_ssl_in_hdr_len( ssl ) ); + if( ret != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_fetch_input", ret ); + return( ret ); + } + + ret = ssl_parse_record_header( ssl, ssl->in_hdr, ssl->in_left, &rec ); + if( ret != 0 ) + { +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + if( ret == MBEDTLS_ERR_SSL_EARLY_MESSAGE ) + { + ret = ssl_buffer_future_record( ssl, &rec ); + if( ret != 0 ) + return( ret ); + + /* Fall through to handling of unexpected records */ + ret = MBEDTLS_ERR_SSL_UNEXPECTED_RECORD; + } + + if( ret == MBEDTLS_ERR_SSL_UNEXPECTED_RECORD ) + { +#if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) && defined(MBEDTLS_SSL_SRV_C) + /* Reset in pointers to default state for TLS/DTLS records, + * assuming no CID and no offset between record content and + * record plaintext. */ + mbedtls_ssl_update_in_pointers( ssl ); + + /* Setup internal message pointers from record structure. */ + ssl->in_msgtype = rec.type; +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + ssl->in_len = ssl->in_cid + rec.cid_len; +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + ssl->in_iv = ssl->in_msg = ssl->in_len + 2; + ssl->in_msglen = rec.data_len; + + ret = ssl_check_client_reconnect( ssl ); + if( ret != 0 ) + return( ret ); +#endif + + /* Skip unexpected record (but not whole datagram) */ + ssl->next_record_offset = rec.buf_len; + + MBEDTLS_SSL_DEBUG_MSG( 1, ( "discarding unexpected record " + "(header)" ) ); + } + else + { + /* Skip invalid record and the rest of the datagram */ + ssl->next_record_offset = 0; + ssl->in_left = 0; + + MBEDTLS_SSL_DEBUG_MSG( 1, ( "discarding invalid record " + "(header)" ) ); + } + + /* Get next record */ + return( MBEDTLS_ERR_SSL_CONTINUE_PROCESSING ); + } + else +#endif + { + return( ret ); + } + } + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + /* Remember offset of next record within datagram. */ + ssl->next_record_offset = rec.buf_len; + if( ssl->next_record_offset < ssl->in_left ) + { + MBEDTLS_SSL_DEBUG_MSG( 3, ( "more than one record within datagram" ) ); + } + } + else +#endif + { + /* + * Fetch record contents from underlying transport. + */ + ret = mbedtls_ssl_fetch_input( ssl, rec.buf_len ); + if( ret != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_fetch_input", ret ); + return( ret ); + } + + ssl->in_left = 0; + } + + /* + * Decrypt record contents. + */ + + if( ( ret = ssl_prepare_record_content( ssl, &rec ) ) != 0 ) + { +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + /* Silently discard invalid records */ + if( ret == MBEDTLS_ERR_SSL_INVALID_MAC ) + { + /* Except when waiting for Finished as a bad mac here + * probably means something went wrong in the handshake + * (eg wrong psk used, mitm downgrade attempt, etc.) */ + if( ssl->state == MBEDTLS_SSL_CLIENT_FINISHED || + ssl->state == MBEDTLS_SSL_SERVER_FINISHED ) + { +#if defined(MBEDTLS_SSL_ALL_ALERT_MESSAGES) + if( ret == MBEDTLS_ERR_SSL_INVALID_MAC ) + { + mbedtls_ssl_send_alert_message( ssl, + MBEDTLS_SSL_ALERT_LEVEL_FATAL, + MBEDTLS_SSL_ALERT_MSG_BAD_RECORD_MAC ); + } +#endif + return( ret ); + } + +#if defined(MBEDTLS_SSL_DTLS_BADMAC_LIMIT) + if( ssl->conf->badmac_limit != 0 && + ++ssl->badmac_seen >= ssl->conf->badmac_limit ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "too many records with bad MAC" ) ); + return( MBEDTLS_ERR_SSL_INVALID_MAC ); + } +#endif + + /* As above, invalid records cause + * dismissal of the whole datagram. */ + + ssl->next_record_offset = 0; + ssl->in_left = 0; + + MBEDTLS_SSL_DEBUG_MSG( 1, ( "discarding invalid record (mac)" ) ); + return( MBEDTLS_ERR_SSL_CONTINUE_PROCESSING ); + } + + return( ret ); + } + else +#endif + { + /* Error out (and send alert) on invalid records */ +#if defined(MBEDTLS_SSL_ALL_ALERT_MESSAGES) + if( ret == MBEDTLS_ERR_SSL_INVALID_MAC ) + { + mbedtls_ssl_send_alert_message( ssl, + MBEDTLS_SSL_ALERT_LEVEL_FATAL, + MBEDTLS_SSL_ALERT_MSG_BAD_RECORD_MAC ); + } +#endif + return( ret ); + } + } + + + /* Reset in pointers to default state for TLS/DTLS records, + * assuming no CID and no offset between record content and + * record plaintext. */ + mbedtls_ssl_update_in_pointers( ssl ); +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + ssl->in_len = ssl->in_cid + rec.cid_len; +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + ssl->in_iv = ssl->in_len + 2; + + /* The record content type may change during decryption, + * so re-read it. */ + ssl->in_msgtype = rec.type; + /* Also update the input buffer, because unfortunately + * the server-side ssl_parse_client_hello() reparses the + * record header when receiving a ClientHello initiating + * a renegotiation. */ + ssl->in_hdr[0] = rec.type; + ssl->in_msg = rec.buf + rec.data_offset; + ssl->in_msglen = rec.data_len; + ssl->in_len[0] = (unsigned char)( rec.data_len >> 8 ); + ssl->in_len[1] = (unsigned char)( rec.data_len ); + +#if defined(MBEDTLS_ZLIB_SUPPORT) + if( ssl->transform_in != NULL && + ssl->session_in->compression == MBEDTLS_SSL_COMPRESS_DEFLATE ) + { + if( ( ret = ssl_decompress_buf( ssl ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "ssl_decompress_buf", ret ); + return( ret ); + } + + /* Check actual (decompress) record content length against + * configured maximum. */ + if( ssl->in_msglen > MBEDTLS_SSL_IN_CONTENT_LEN ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad message length" ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + } +#endif /* MBEDTLS_ZLIB_SUPPORT */ + + return( 0 ); +} + +int mbedtls_ssl_handle_message_type( mbedtls_ssl_context *ssl ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + /* + * Handle particular types of records + */ + if( ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE ) + { + if( ( ret = mbedtls_ssl_prepare_handshake_record( ssl ) ) != 0 ) + { + return( ret ); + } + } + + if( ssl->in_msgtype == MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC ) + { + if( ssl->in_msglen != 1 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "invalid CCS message, len: %d", + ssl->in_msglen ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + + if( ssl->in_msg[0] != 1 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "invalid CCS message, content: %02x", + ssl->in_msg[0] ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && + ssl->state != MBEDTLS_SSL_CLIENT_CHANGE_CIPHER_SPEC && + ssl->state != MBEDTLS_SSL_SERVER_CHANGE_CIPHER_SPEC ) + { + if( ssl->handshake == NULL ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "dropping ChangeCipherSpec outside handshake" ) ); + return( MBEDTLS_ERR_SSL_UNEXPECTED_RECORD ); + } + + MBEDTLS_SSL_DEBUG_MSG( 1, ( "received out-of-order ChangeCipherSpec - remember" ) ); + return( MBEDTLS_ERR_SSL_EARLY_MESSAGE ); + } +#endif + } + + if( ssl->in_msgtype == MBEDTLS_SSL_MSG_ALERT ) + { + if( ssl->in_msglen != 2 ) + { + /* Note: Standard allows for more than one 2 byte alert + to be packed in a single message, but Mbed TLS doesn't + currently support this. */ + MBEDTLS_SSL_DEBUG_MSG( 1, ( "invalid alert message, len: %d", + ssl->in_msglen ) ); + return( MBEDTLS_ERR_SSL_INVALID_RECORD ); + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "got an alert message, type: [%d:%d]", + ssl->in_msg[0], ssl->in_msg[1] ) ); + + /* + * Ignore non-fatal alerts, except close_notify and no_renegotiation + */ + if( ssl->in_msg[0] == MBEDTLS_SSL_ALERT_LEVEL_FATAL ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "is a fatal alert message (msg %d)", + ssl->in_msg[1] ) ); + return( MBEDTLS_ERR_SSL_FATAL_ALERT_MESSAGE ); + } + + if( ssl->in_msg[0] == MBEDTLS_SSL_ALERT_LEVEL_WARNING && + ssl->in_msg[1] == MBEDTLS_SSL_ALERT_MSG_CLOSE_NOTIFY ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "is a close notify message" ) ); + return( MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY ); + } + +#if defined(MBEDTLS_SSL_RENEGOTIATION_ENABLED) + if( ssl->in_msg[0] == MBEDTLS_SSL_ALERT_LEVEL_WARNING && + ssl->in_msg[1] == MBEDTLS_SSL_ALERT_MSG_NO_RENEGOTIATION ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "is a SSLv3 no renegotiation alert" ) ); + /* Will be handled when trying to parse ServerHello */ + return( 0 ); + } +#endif + +#if defined(MBEDTLS_SSL_PROTO_SSL3) && defined(MBEDTLS_SSL_SRV_C) + if( ssl->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 && + ssl->conf->endpoint == MBEDTLS_SSL_IS_SERVER && + ssl->in_msg[0] == MBEDTLS_SSL_ALERT_LEVEL_WARNING && + ssl->in_msg[1] == MBEDTLS_SSL_ALERT_MSG_NO_CERT ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "is a SSLv3 no_cert" ) ); + /* Will be handled in mbedtls_ssl_parse_certificate() */ + return( 0 ); + } +#endif /* MBEDTLS_SSL_PROTO_SSL3 && MBEDTLS_SSL_SRV_C */ + + /* Silently ignore: fetch new message */ + return MBEDTLS_ERR_SSL_NON_FATAL; + } + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + /* Drop unexpected ApplicationData records, + * except at the beginning of renegotiations */ + if( ssl->in_msgtype == MBEDTLS_SSL_MSG_APPLICATION_DATA && + ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER +#if defined(MBEDTLS_SSL_RENEGOTIATION) + && ! ( ssl->renego_status == MBEDTLS_SSL_RENEGOTIATION_IN_PROGRESS && + ssl->state == MBEDTLS_SSL_SERVER_HELLO ) +#endif + ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "dropping unexpected ApplicationData" ) ); + return( MBEDTLS_ERR_SSL_NON_FATAL ); + } + + if( ssl->handshake != NULL && + ssl->state == MBEDTLS_SSL_HANDSHAKE_OVER ) + { + mbedtls_ssl_handshake_wrapup_free_hs_transform( ssl ); + } + } +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + + return( 0 ); +} + +int mbedtls_ssl_send_fatal_handshake_failure( mbedtls_ssl_context *ssl ) +{ + return( mbedtls_ssl_send_alert_message( ssl, + MBEDTLS_SSL_ALERT_LEVEL_FATAL, + MBEDTLS_SSL_ALERT_MSG_HANDSHAKE_FAILURE ) ); +} + +int mbedtls_ssl_send_alert_message( mbedtls_ssl_context *ssl, + unsigned char level, + unsigned char message ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + if( ssl == NULL || ssl->conf == NULL ) + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> send alert message" ) ); + MBEDTLS_SSL_DEBUG_MSG( 3, ( "send alert level=%u message=%u", level, message )); + + ssl->out_msgtype = MBEDTLS_SSL_MSG_ALERT; + ssl->out_msglen = 2; + ssl->out_msg[0] = level; + ssl->out_msg[1] = message; + + if( ( ret = mbedtls_ssl_write_record( ssl, SSL_FORCE_FLUSH ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_write_record", ret ); + return( ret ); + } + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= send alert message" ) ); + + return( 0 ); +} + +int mbedtls_ssl_write_change_cipher_spec( mbedtls_ssl_context *ssl ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write change cipher spec" ) ); + + ssl->out_msgtype = MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC; + ssl->out_msglen = 1; + ssl->out_msg[0] = 1; + + ssl->state++; + + if( ( ret = mbedtls_ssl_write_handshake_msg( ssl ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_write_handshake_msg", ret ); + return( ret ); + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= write change cipher spec" ) ); + + return( 0 ); +} + +int mbedtls_ssl_parse_change_cipher_spec( mbedtls_ssl_context *ssl ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> parse change cipher spec" ) ); + + if( ( ret = mbedtls_ssl_read_record( ssl, 1 ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_read_record", ret ); + return( ret ); + } + + if( ssl->in_msgtype != MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad change cipher spec message" ) ); + mbedtls_ssl_send_alert_message( ssl, MBEDTLS_SSL_ALERT_LEVEL_FATAL, + MBEDTLS_SSL_ALERT_MSG_UNEXPECTED_MESSAGE ); + return( MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE ); + } + + /* CCS records are only accepted if they have length 1 and content '1', + * so we don't need to check this here. */ + + /* + * Switch to our negotiated transform and session parameters for inbound + * data. + */ + MBEDTLS_SSL_DEBUG_MSG( 3, ( "switching to new transform spec for inbound data" ) ); + ssl->transform_in = ssl->transform_negotiate; + ssl->session_in = ssl->session_negotiate; + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { +#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) + mbedtls_ssl_dtls_replay_reset( ssl ); +#endif + + /* Increment epoch */ + if( ++ssl->in_epoch == 0 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "DTLS epoch would wrap" ) ); + /* This is highly unlikely to happen for legitimate reasons, so + treat it as an attack and don't send an alert. */ + return( MBEDTLS_ERR_SSL_COUNTER_WRAPPING ); + } + } + else +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + memset( ssl->in_ctr, 0, 8 ); + + mbedtls_ssl_update_in_pointers( ssl ); + +#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL) + if( mbedtls_ssl_hw_record_activate != NULL ) + { + if( ( ret = mbedtls_ssl_hw_record_activate( ssl, MBEDTLS_SSL_CHANNEL_INBOUND ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_hw_record_activate", ret ); + mbedtls_ssl_send_alert_message( ssl, MBEDTLS_SSL_ALERT_LEVEL_FATAL, + MBEDTLS_SSL_ALERT_MSG_INTERNAL_ERROR ); + return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); + } + } +#endif + + ssl->state++; + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= parse change cipher spec" ) ); + + return( 0 ); +} + +/* Once ssl->out_hdr as the address of the beginning of the + * next outgoing record is set, deduce the other pointers. + * + * Note: For TLS, we save the implicit record sequence number + * (entering MAC computation) in the 8 bytes before ssl->out_hdr, + * and the caller has to make sure there's space for this. + */ + +void mbedtls_ssl_update_out_pointers( mbedtls_ssl_context *ssl, + mbedtls_ssl_transform *transform ) +{ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + ssl->out_ctr = ssl->out_hdr + 3; +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + ssl->out_cid = ssl->out_ctr + 8; + ssl->out_len = ssl->out_cid; + if( transform != NULL ) + ssl->out_len += transform->out_cid_len; +#else /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + ssl->out_len = ssl->out_ctr + 8; +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + ssl->out_iv = ssl->out_len + 2; + } + else +#endif + { + ssl->out_ctr = ssl->out_hdr - 8; + ssl->out_len = ssl->out_hdr + 3; +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + ssl->out_cid = ssl->out_len; +#endif + ssl->out_iv = ssl->out_hdr + 5; + } + + /* Adjust out_msg to make space for explicit IV, if used. */ + if( transform != NULL && + ssl->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_2 ) + { + ssl->out_msg = ssl->out_iv + transform->ivlen - transform->fixed_ivlen; + } + else + ssl->out_msg = ssl->out_iv; +} + +/* Once ssl->in_hdr as the address of the beginning of the + * next incoming record is set, deduce the other pointers. + * + * Note: For TLS, we save the implicit record sequence number + * (entering MAC computation) in the 8 bytes before ssl->in_hdr, + * and the caller has to make sure there's space for this. + */ + +void mbedtls_ssl_update_in_pointers( mbedtls_ssl_context *ssl ) +{ + /* This function sets the pointers to match the case + * of unprotected TLS/DTLS records, with both ssl->in_iv + * and ssl->in_msg pointing to the beginning of the record + * content. + * + * When decrypting a protected record, ssl->in_msg + * will be shifted to point to the beginning of the + * record plaintext. + */ + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + /* This sets the header pointers to match records + * without CID. When we receive a record containing + * a CID, the fields are shifted accordingly in + * ssl_parse_record_header(). */ + ssl->in_ctr = ssl->in_hdr + 3; +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + ssl->in_cid = ssl->in_ctr + 8; + ssl->in_len = ssl->in_cid; /* Default: no CID */ +#else /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + ssl->in_len = ssl->in_ctr + 8; +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + ssl->in_iv = ssl->in_len + 2; + } + else +#endif + { + ssl->in_ctr = ssl->in_hdr - 8; + ssl->in_len = ssl->in_hdr + 3; +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + ssl->in_cid = ssl->in_len; +#endif + ssl->in_iv = ssl->in_hdr + 5; + } + + /* This will be adjusted at record decryption time. */ + ssl->in_msg = ssl->in_iv; +} + +/* + * Setup an SSL context + */ + +void mbedtls_ssl_reset_in_out_pointers( mbedtls_ssl_context *ssl ) +{ + /* Set the incoming and outgoing record pointers. */ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + ssl->out_hdr = ssl->out_buf; + ssl->in_hdr = ssl->in_buf; + } + else +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + { + ssl->out_hdr = ssl->out_buf + 8; + ssl->in_hdr = ssl->in_buf + 8; + } + + /* Derive other internal pointers. */ + mbedtls_ssl_update_out_pointers( ssl, NULL /* no transform enabled */ ); + mbedtls_ssl_update_in_pointers ( ssl ); +} + +/* + * SSL get accessors + */ +size_t mbedtls_ssl_get_bytes_avail( const mbedtls_ssl_context *ssl ) +{ + return( ssl->in_offt == NULL ? 0 : ssl->in_msglen ); +} + +int mbedtls_ssl_check_pending( const mbedtls_ssl_context *ssl ) +{ + /* + * Case A: We're currently holding back + * a message for further processing. + */ + + if( ssl->keep_current_message == 1 ) + { + MBEDTLS_SSL_DEBUG_MSG( 3, ( "ssl_check_pending: record held back for processing" ) ); + return( 1 ); + } + + /* + * Case B: Further records are pending in the current datagram. + */ + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && + ssl->in_left > ssl->next_record_offset ) + { + MBEDTLS_SSL_DEBUG_MSG( 3, ( "ssl_check_pending: more records within current datagram" ) ); + return( 1 ); + } +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + + /* + * Case C: A handshake message is being processed. + */ + + if( ssl->in_hslen > 0 && ssl->in_hslen < ssl->in_msglen ) + { + MBEDTLS_SSL_DEBUG_MSG( 3, ( "ssl_check_pending: more handshake messages within current record" ) ); + return( 1 ); + } + + /* + * Case D: An application data message is being processed + */ + if( ssl->in_offt != NULL ) + { + MBEDTLS_SSL_DEBUG_MSG( 3, ( "ssl_check_pending: application data record is being processed" ) ); + return( 1 ); + } + + /* + * In all other cases, the rest of the message can be dropped. + * As in ssl_get_next_record, this needs to be adapted if + * we implement support for multiple alerts in single records. + */ + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "ssl_check_pending: nothing pending" ) ); + return( 0 ); +} + + +int mbedtls_ssl_get_record_expansion( const mbedtls_ssl_context *ssl ) +{ + size_t transform_expansion = 0; + const mbedtls_ssl_transform *transform = ssl->transform_out; + unsigned block_size; + + size_t out_hdr_len = mbedtls_ssl_out_hdr_len( ssl ); + + if( transform == NULL ) + return( (int) out_hdr_len ); + +#if defined(MBEDTLS_ZLIB_SUPPORT) + if( ssl->session_out->compression != MBEDTLS_SSL_COMPRESS_NULL ) + return( MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE ); +#endif + + switch( mbedtls_cipher_get_cipher_mode( &transform->cipher_ctx_enc ) ) + { + case MBEDTLS_MODE_GCM: + case MBEDTLS_MODE_CCM: + case MBEDTLS_MODE_CHACHAPOLY: + case MBEDTLS_MODE_STREAM: + transform_expansion = transform->minlen; + break; + + case MBEDTLS_MODE_CBC: + + block_size = mbedtls_cipher_get_block_size( + &transform->cipher_ctx_enc ); + + /* Expansion due to the addition of the MAC. */ + transform_expansion += transform->maclen; + + /* Expansion due to the addition of CBC padding; + * Theoretically up to 256 bytes, but we never use + * more than the block size of the underlying cipher. */ + transform_expansion += block_size; + + /* For TLS 1.1 or higher, an explicit IV is added + * after the record header. */ +#if defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2) + if( ssl->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_2 ) + transform_expansion += block_size; +#endif /* MBEDTLS_SSL_PROTO_TLS1_1 || MBEDTLS_SSL_PROTO_TLS1_2 */ + + break; + + default: + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + +#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) + if( transform->out_cid_len != 0 ) + transform_expansion += MBEDTLS_SSL_MAX_CID_EXPANSION; +#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ + + return( (int)( out_hdr_len + transform_expansion ) ); +} + +#if defined(MBEDTLS_SSL_RENEGOTIATION) +/* + * Check record counters and renegotiate if they're above the limit. + */ +static int ssl_check_ctr_renegotiate( mbedtls_ssl_context *ssl ) +{ + size_t ep_len = mbedtls_ssl_ep_len( ssl ); + int in_ctr_cmp; + int out_ctr_cmp; + + if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER || + ssl->renego_status == MBEDTLS_SSL_RENEGOTIATION_PENDING || + ssl->conf->disable_renegotiation == MBEDTLS_SSL_RENEGOTIATION_DISABLED ) + { + return( 0 ); + } + + in_ctr_cmp = memcmp( ssl->in_ctr + ep_len, + ssl->conf->renego_period + ep_len, 8 - ep_len ); + out_ctr_cmp = memcmp( ssl->cur_out_ctr + ep_len, + ssl->conf->renego_period + ep_len, 8 - ep_len ); + + if( in_ctr_cmp <= 0 && out_ctr_cmp <= 0 ) + { + return( 0 ); + } + + MBEDTLS_SSL_DEBUG_MSG( 1, ( "record counter limit reached: renegotiate" ) ); + return( mbedtls_ssl_renegotiate( ssl ) ); +} +#endif /* MBEDTLS_SSL_RENEGOTIATION */ + +/* + * Receive application data decrypted from the SSL layer + */ +int mbedtls_ssl_read( mbedtls_ssl_context *ssl, unsigned char *buf, size_t len ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t n; + + if( ssl == NULL || ssl->conf == NULL ) + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> read" ) ); + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + if( ( ret = mbedtls_ssl_flush_output( ssl ) ) != 0 ) + return( ret ); + + if( ssl->handshake != NULL && + ssl->handshake->retransmit_state == MBEDTLS_SSL_RETRANS_SENDING ) + { + if( ( ret = mbedtls_ssl_flight_transmit( ssl ) ) != 0 ) + return( ret ); + } + } +#endif + + /* + * Check if renegotiation is necessary and/or handshake is + * in process. If yes, perform/continue, and fall through + * if an unexpected packet is received while the client + * is waiting for the ServerHello. + * + * (There is no equivalent to the last condition on + * the server-side as it is not treated as within + * a handshake while waiting for the ClientHello + * after a renegotiation request.) + */ + +#if defined(MBEDTLS_SSL_RENEGOTIATION) + ret = ssl_check_ctr_renegotiate( ssl ); + if( ret != MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO && + ret != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "ssl_check_ctr_renegotiate", ret ); + return( ret ); + } +#endif + + if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER ) + { + ret = mbedtls_ssl_handshake( ssl ); + if( ret != MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO && + ret != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_handshake", ret ); + return( ret ); + } + } + + /* Loop as long as no application data record is available */ + while( ssl->in_offt == NULL ) + { + /* Start timer if not already running */ + if( ssl->f_get_timer != NULL && + ssl->f_get_timer( ssl->p_timer ) == -1 ) + { + mbedtls_ssl_set_timer( ssl, ssl->conf->read_timeout ); + } + + if( ( ret = mbedtls_ssl_read_record( ssl, 1 ) ) != 0 ) + { + if( ret == MBEDTLS_ERR_SSL_CONN_EOF ) + return( 0 ); + + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_read_record", ret ); + return( ret ); + } + + if( ssl->in_msglen == 0 && + ssl->in_msgtype == MBEDTLS_SSL_MSG_APPLICATION_DATA ) + { + /* + * OpenSSL sends empty messages to randomize the IV + */ + if( ( ret = mbedtls_ssl_read_record( ssl, 1 ) ) != 0 ) + { + if( ret == MBEDTLS_ERR_SSL_CONN_EOF ) + return( 0 ); + + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_read_record", ret ); + return( ret ); + } + } + + if( ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "received handshake message" ) ); + + /* + * - For client-side, expect SERVER_HELLO_REQUEST. + * - For server-side, expect CLIENT_HELLO. + * - Fail (TLS) or silently drop record (DTLS) in other cases. + */ + +#if defined(MBEDTLS_SSL_CLI_C) + if( ssl->conf->endpoint == MBEDTLS_SSL_IS_CLIENT && + ( ssl->in_msg[0] != MBEDTLS_SSL_HS_HELLO_REQUEST || + ssl->in_hslen != mbedtls_ssl_hs_hdr_len( ssl ) ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "handshake received (not HelloRequest)" ) ); + + /* With DTLS, drop the packet (probably from last handshake) */ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + continue; + } +#endif + return( MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE ); + } +#endif /* MBEDTLS_SSL_CLI_C */ + +#if defined(MBEDTLS_SSL_SRV_C) + if( ssl->conf->endpoint == MBEDTLS_SSL_IS_SERVER && + ssl->in_msg[0] != MBEDTLS_SSL_HS_CLIENT_HELLO ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "handshake received (not ClientHello)" ) ); + + /* With DTLS, drop the packet (probably from last handshake) */ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + continue; + } +#endif + return( MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE ); + } +#endif /* MBEDTLS_SSL_SRV_C */ + +#if defined(MBEDTLS_SSL_RENEGOTIATION) + /* Determine whether renegotiation attempt should be accepted */ + if( ! ( ssl->conf->disable_renegotiation == MBEDTLS_SSL_RENEGOTIATION_DISABLED || + ( ssl->secure_renegotiation == MBEDTLS_SSL_LEGACY_RENEGOTIATION && + ssl->conf->allow_legacy_renegotiation == + MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION ) ) ) + { + /* + * Accept renegotiation request + */ + + /* DTLS clients need to know renego is server-initiated */ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && + ssl->conf->endpoint == MBEDTLS_SSL_IS_CLIENT ) + { + ssl->renego_status = MBEDTLS_SSL_RENEGOTIATION_PENDING; + } +#endif + ret = mbedtls_ssl_start_renegotiation( ssl ); + if( ret != MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO && + ret != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_start_renegotiation", + ret ); + return( ret ); + } + } + else +#endif /* MBEDTLS_SSL_RENEGOTIATION */ + { + /* + * Refuse renegotiation + */ + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "refusing renegotiation, sending alert" ) ); + +#if defined(MBEDTLS_SSL_PROTO_SSL3) + if( ssl->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 ) + { + /* SSLv3 does not have a "no_renegotiation" warning, so + we send a fatal alert and abort the connection. */ + mbedtls_ssl_send_alert_message( ssl, MBEDTLS_SSL_ALERT_LEVEL_FATAL, + MBEDTLS_SSL_ALERT_MSG_UNEXPECTED_MESSAGE ); + return( MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE ); + } + else +#endif /* MBEDTLS_SSL_PROTO_SSL3 */ +#if defined(MBEDTLS_SSL_PROTO_TLS1) || defined(MBEDTLS_SSL_PROTO_TLS1_1) || \ + defined(MBEDTLS_SSL_PROTO_TLS1_2) + if( ssl->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_1 ) + { + if( ( ret = mbedtls_ssl_send_alert_message( ssl, + MBEDTLS_SSL_ALERT_LEVEL_WARNING, + MBEDTLS_SSL_ALERT_MSG_NO_RENEGOTIATION ) ) != 0 ) + { + return( ret ); + } + } + else +#endif /* MBEDTLS_SSL_PROTO_TLS1 || MBEDTLS_SSL_PROTO_TLS1_1 || + MBEDTLS_SSL_PROTO_TLS1_2 */ + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + } + + /* At this point, we don't know whether the renegotiation has been + * completed or not. The cases to consider are the following: + * 1) The renegotiation is complete. In this case, no new record + * has been read yet. + * 2) The renegotiation is incomplete because the client received + * an application data record while awaiting the ServerHello. + * 3) The renegotiation is incomplete because the client received + * a non-handshake, non-application data message while awaiting + * the ServerHello. + * In each of these case, looping will be the proper action: + * - For 1), the next iteration will read a new record and check + * if it's application data. + * - For 2), the loop condition isn't satisfied as application data + * is present, hence continue is the same as break + * - For 3), the loop condition is satisfied and read_record + * will re-deliver the message that was held back by the client + * when expecting the ServerHello. + */ + continue; + } +#if defined(MBEDTLS_SSL_RENEGOTIATION) + else if( ssl->renego_status == MBEDTLS_SSL_RENEGOTIATION_PENDING ) + { + if( ssl->conf->renego_max_records >= 0 ) + { + if( ++ssl->renego_records_seen > ssl->conf->renego_max_records ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "renegotiation requested, " + "but not honored by client" ) ); + return( MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE ); + } + } + } +#endif /* MBEDTLS_SSL_RENEGOTIATION */ + + /* Fatal and closure alerts handled by mbedtls_ssl_read_record() */ + if( ssl->in_msgtype == MBEDTLS_SSL_MSG_ALERT ) + { + MBEDTLS_SSL_DEBUG_MSG( 2, ( "ignoring non-fatal non-closure alert" ) ); + return( MBEDTLS_ERR_SSL_WANT_READ ); + } + + if( ssl->in_msgtype != MBEDTLS_SSL_MSG_APPLICATION_DATA ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad application data message" ) ); + return( MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE ); + } + + ssl->in_offt = ssl->in_msg; + + /* We're going to return something now, cancel timer, + * except if handshake (renegotiation) is in progress */ + if( ssl->state == MBEDTLS_SSL_HANDSHAKE_OVER ) + mbedtls_ssl_set_timer( ssl, 0 ); + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + /* If we requested renego but received AppData, resend HelloRequest. + * Do it now, after setting in_offt, to avoid taking this branch + * again if ssl_write_hello_request() returns WANT_WRITE */ +#if defined(MBEDTLS_SSL_SRV_C) && defined(MBEDTLS_SSL_RENEGOTIATION) + if( ssl->conf->endpoint == MBEDTLS_SSL_IS_SERVER && + ssl->renego_status == MBEDTLS_SSL_RENEGOTIATION_PENDING ) + { + if( ( ret = mbedtls_ssl_resend_hello_request( ssl ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_resend_hello_request", + ret ); + return( ret ); + } + } +#endif /* MBEDTLS_SSL_SRV_C && MBEDTLS_SSL_RENEGOTIATION */ +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + } + + n = ( len < ssl->in_msglen ) + ? len : ssl->in_msglen; + + memcpy( buf, ssl->in_offt, n ); + ssl->in_msglen -= n; + + if( ssl->in_msglen == 0 ) + { + /* all bytes consumed */ + ssl->in_offt = NULL; + ssl->keep_current_message = 0; + } + else + { + /* more data available */ + ssl->in_offt += n; + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= read" ) ); + + return( (int) n ); +} + +/* + * Send application data to be encrypted by the SSL layer, taking care of max + * fragment length and buffer size. + * + * According to RFC 5246 Section 6.2.1: + * + * Zero-length fragments of Application data MAY be sent as they are + * potentially useful as a traffic analysis countermeasure. + * + * Therefore, it is possible that the input message length is 0 and the + * corresponding return code is 0 on success. + */ +static int ssl_write_real( mbedtls_ssl_context *ssl, + const unsigned char *buf, size_t len ) +{ + int ret = mbedtls_ssl_get_max_out_record_payload( ssl ); + const size_t max_len = (size_t) ret; + + if( ret < 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_get_max_out_record_payload", ret ); + return( ret ); + } + + if( len > max_len ) + { +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "fragment larger than the (negotiated) " + "maximum fragment length: %d > %d", + len, max_len ) ); + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + } + else +#endif + len = max_len; + } + + if( ssl->out_left != 0 ) + { + /* + * The user has previously tried to send the data and + * MBEDTLS_ERR_SSL_WANT_WRITE or the message was only partially + * written. In this case, we expect the high-level write function + * (e.g. mbedtls_ssl_write()) to be called with the same parameters + */ + if( ( ret = mbedtls_ssl_flush_output( ssl ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_flush_output", ret ); + return( ret ); + } + } + else + { + /* + * The user is trying to send a message the first time, so we need to + * copy the data into the internal buffers and setup the data structure + * to keep track of partial writes + */ + ssl->out_msglen = len; + ssl->out_msgtype = MBEDTLS_SSL_MSG_APPLICATION_DATA; + memcpy( ssl->out_msg, buf, len ); + + if( ( ret = mbedtls_ssl_write_record( ssl, SSL_FORCE_FLUSH ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_write_record", ret ); + return( ret ); + } + } + + return( (int) len ); +} + +/* + * Write application data, doing 1/n-1 splitting if necessary. + * + * With non-blocking I/O, ssl_write_real() may return WANT_WRITE, + * then the caller will call us again with the same arguments, so + * remember whether we already did the split or not. + */ +#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING) +static int ssl_write_split( mbedtls_ssl_context *ssl, + const unsigned char *buf, size_t len ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + if( ssl->conf->cbc_record_splitting == + MBEDTLS_SSL_CBC_RECORD_SPLITTING_DISABLED || + len <= 1 || + ssl->minor_ver > MBEDTLS_SSL_MINOR_VERSION_1 || + mbedtls_cipher_get_cipher_mode( &ssl->transform_out->cipher_ctx_enc ) + != MBEDTLS_MODE_CBC ) + { + return( ssl_write_real( ssl, buf, len ) ); + } + + if( ssl->split_done == 0 ) + { + if( ( ret = ssl_write_real( ssl, buf, 1 ) ) <= 0 ) + return( ret ); + ssl->split_done = 1; + } + + if( ( ret = ssl_write_real( ssl, buf + 1, len - 1 ) ) <= 0 ) + return( ret ); + ssl->split_done = 0; + + return( ret + 1 ); +} +#endif /* MBEDTLS_SSL_CBC_RECORD_SPLITTING */ + +/* + * Write application data (public-facing wrapper) + */ +int mbedtls_ssl_write( mbedtls_ssl_context *ssl, const unsigned char *buf, size_t len ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write" ) ); + + if( ssl == NULL || ssl->conf == NULL ) + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + +#if defined(MBEDTLS_SSL_RENEGOTIATION) + if( ( ret = ssl_check_ctr_renegotiate( ssl ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "ssl_check_ctr_renegotiate", ret ); + return( ret ); + } +#endif + + if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER ) + { + if( ( ret = mbedtls_ssl_handshake( ssl ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_handshake", ret ); + return( ret ); + } + } + +#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING) + ret = ssl_write_split( ssl, buf, len ); +#else + ret = ssl_write_real( ssl, buf, len ); +#endif + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= write" ) ); + + return( ret ); +} + +/* + * Notify the peer that the connection is being closed + */ +int mbedtls_ssl_close_notify( mbedtls_ssl_context *ssl ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + + if( ssl == NULL || ssl->conf == NULL ) + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write close notify" ) ); + + if( ssl->out_left != 0 ) + return( mbedtls_ssl_flush_output( ssl ) ); + + if( ssl->state == MBEDTLS_SSL_HANDSHAKE_OVER ) + { + if( ( ret = mbedtls_ssl_send_alert_message( ssl, + MBEDTLS_SSL_ALERT_LEVEL_WARNING, + MBEDTLS_SSL_ALERT_MSG_CLOSE_NOTIFY ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_send_alert_message", ret ); + return( ret ); + } + } + + MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= write close notify" ) ); + + return( 0 ); +} + +void mbedtls_ssl_transform_free( mbedtls_ssl_transform *transform ) +{ + if( transform == NULL ) + return; + +#if defined(MBEDTLS_ZLIB_SUPPORT) + deflateEnd( &transform->ctx_deflate ); + inflateEnd( &transform->ctx_inflate ); +#endif + + mbedtls_cipher_free( &transform->cipher_ctx_enc ); + mbedtls_cipher_free( &transform->cipher_ctx_dec ); + +#if defined(MBEDTLS_SSL_SOME_MODES_USE_MAC) + mbedtls_md_free( &transform->md_ctx_enc ); + mbedtls_md_free( &transform->md_ctx_dec ); +#endif + + mbedtls_platform_zeroize( transform, sizeof( mbedtls_ssl_transform ) ); +} + +#if defined(MBEDTLS_SSL_PROTO_DTLS) + +void mbedtls_ssl_buffering_free( mbedtls_ssl_context *ssl ) +{ + unsigned offset; + mbedtls_ssl_handshake_params * const hs = ssl->handshake; + + if( hs == NULL ) + return; + + ssl_free_buffered_record( ssl ); + + for( offset = 0; offset < MBEDTLS_SSL_MAX_BUFFERED_HS; offset++ ) + ssl_buffering_free_slot( ssl, offset ); +} + +static void ssl_buffering_free_slot( mbedtls_ssl_context *ssl, + uint8_t slot ) +{ + mbedtls_ssl_handshake_params * const hs = ssl->handshake; + mbedtls_ssl_hs_buffer * const hs_buf = &hs->buffering.hs[slot]; + + if( slot >= MBEDTLS_SSL_MAX_BUFFERED_HS ) + return; + + if( hs_buf->is_valid == 1 ) + { + hs->buffering.total_bytes_buffered -= hs_buf->data_len; + mbedtls_platform_zeroize( hs_buf->data, hs_buf->data_len ); + mbedtls_free( hs_buf->data ); + memset( hs_buf, 0, sizeof( mbedtls_ssl_hs_buffer ) ); + } +} + +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + +/* + * Convert version numbers to/from wire format + * and, for DTLS, to/from TLS equivalent. + * + * For TLS this is the identity. + * For DTLS, use 1's complement (v -> 255 - v, and then map as follows: + * 1.0 <-> 3.2 (DTLS 1.0 is based on TLS 1.1) + * 1.x <-> 3.x+1 for x != 0 (DTLS 1.2 based on TLS 1.2) + */ +void mbedtls_ssl_write_version( int major, int minor, int transport, + unsigned char ver[2] ) +{ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + if( minor == MBEDTLS_SSL_MINOR_VERSION_2 ) + --minor; /* DTLS 1.0 stored as TLS 1.1 internally */ + + ver[0] = (unsigned char)( 255 - ( major - 2 ) ); + ver[1] = (unsigned char)( 255 - ( minor - 1 ) ); + } + else +#else + ((void) transport); +#endif + { + ver[0] = (unsigned char) major; + ver[1] = (unsigned char) minor; + } +} + +void mbedtls_ssl_read_version( int *major, int *minor, int transport, + const unsigned char ver[2] ) +{ +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) + { + *major = 255 - ver[0] + 2; + *minor = 255 - ver[1] + 1; + + if( *minor == MBEDTLS_SSL_MINOR_VERSION_1 ) + ++*minor; /* DTLS 1.0 stored as TLS 1.1 internally */ + } + else +#else + ((void) transport); +#endif + { + *major = ver[0]; + *minor = ver[1]; + } +} + +#endif /* MBEDTLS_SSL_TLS_C */ diff --git a/features/mbedtls/src/ssl_srv.c b/features/mbedtls/src/ssl_srv.c index b1da073ece..b0b09cd97f 100644 --- a/features/mbedtls/src/ssl_srv.c +++ b/features/mbedtls/src/ssl_srv.c @@ -35,9 +35,10 @@ #define mbedtls_free free #endif -#include "mbedtls/debug.h" #include "mbedtls/ssl.h" #include "mbedtls/ssl_internal.h" +#include "mbedtls/debug.h" +#include "mbedtls/error.h" #include "mbedtls/platform_util.h" #include @@ -85,7 +86,7 @@ static int ssl_parse_servername_ext( mbedtls_ssl_context *ssl, const unsigned char *buf, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t servername_list_size, hostname_len; const unsigned char *p; @@ -432,7 +433,7 @@ static int ssl_parse_ecjpake_kkpp( mbedtls_ssl_context *ssl, const unsigned char *buf, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( mbedtls_ecjpake_check( &ssl->handshake->ecjpake_ctx ) != 0 ) { @@ -624,7 +625,7 @@ static int ssl_parse_session_ticket_ext( mbedtls_ssl_context *ssl, unsigned char *buf, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ssl_session session; mbedtls_ssl_session_init( &session ); @@ -2428,7 +2429,7 @@ static void ssl_write_ecjpake_kkpp_ext( mbedtls_ssl_context *ssl, unsigned char *buf, size_t *olen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *p = buf; const unsigned char *end = ssl->out_msg + MBEDTLS_SSL_OUT_CONTENT_LEN; size_t kkpp_len; @@ -2506,7 +2507,7 @@ static void ssl_write_alpn_ext( mbedtls_ssl_context *ssl, #if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) static int ssl_write_hello_verify_request( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *p = ssl->out_msg + 4; unsigned char *cookie_len_byte; @@ -2580,7 +2581,7 @@ static int ssl_write_server_hello( mbedtls_ssl_context *ssl ) #if defined(MBEDTLS_HAVE_TIME) mbedtls_time_t t; #endif - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t olen, ext_len = 0, n; unsigned char *buf, *p; @@ -3007,7 +3008,7 @@ static int ssl_write_certificate_request( mbedtls_ssl_context *ssl ) defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) static int ssl_get_ecdh_params_from_cert( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ! mbedtls_pk_can_do( mbedtls_ssl_own_key( ssl ), MBEDTLS_PK_ECKEY ) ) { @@ -3088,7 +3089,7 @@ static int ssl_prepare_server_key_exchange( mbedtls_ssl_context *ssl, #if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) if( ciphersuite_info->key_exchange == MBEDTLS_KEY_EXCHANGE_ECJPAKE ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; ret = mbedtls_ecjpake_write_round_two( @@ -3128,7 +3129,7 @@ static int ssl_prepare_server_key_exchange( mbedtls_ssl_context *ssl, #if defined(MBEDTLS_KEY_EXCHANGE__SOME__DHE_ENABLED) if( mbedtls_ssl_ciphersuite_uses_dhe( ciphersuite_info ) ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; if( ssl->conf->dhm_P.p == NULL || ssl->conf->dhm_G.p == NULL ) @@ -3193,7 +3194,7 @@ static int ssl_prepare_server_key_exchange( mbedtls_ssl_context *ssl, */ const mbedtls_ecp_curve_info **curve = NULL; const mbedtls_ecp_group_id *gid; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; /* Match our preference list against the offered curves */ @@ -3251,7 +3252,7 @@ curve_matching_done: size_t dig_signed_len = ssl->out_msg + ssl->out_msglen - dig_signed; size_t hashlen = 0; unsigned char hash[MBEDTLS_MD_MAX_SIZE]; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* * 2.1: Choose hash algorithm: @@ -3424,7 +3425,7 @@ curve_matching_done: * machine. */ static int ssl_write_server_key_exchange( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t signature_len = 0; #if defined(MBEDTLS_KEY_EXCHANGE__SOME_NON_PFS__ENABLED) const mbedtls_ssl_ciphersuite_t *ciphersuite_info = @@ -3521,7 +3522,7 @@ static int ssl_write_server_key_exchange( mbedtls_ssl_context *ssl ) static int ssl_write_server_hello_done( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write server hello done" ) ); @@ -3625,7 +3626,7 @@ static int ssl_decrypt_encrypted_pms( mbedtls_ssl_context *ssl, size_t *peer_pmslen, size_t peer_pmssize ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_pk_context *private_key = mbedtls_ssl_own_key( ssl ); mbedtls_pk_context *public_key = &mbedtls_ssl_own_cert( ssl )->pk; size_t len = mbedtls_pk_get_len( public_key ); @@ -3714,7 +3715,7 @@ static int ssl_parse_encrypted_pms( mbedtls_ssl_context *ssl, const unsigned char *end, size_t pms_offset ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *pms = ssl->handshake->premaster + pms_offset; unsigned char ver[2]; unsigned char fake_pms[48], peer_pms[48]; @@ -3868,7 +3869,7 @@ static int ssl_parse_client_psk_identity( mbedtls_ssl_context *ssl, unsigned cha static int ssl_parse_client_key_exchange( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const mbedtls_ssl_ciphersuite_t *ciphersuite_info; unsigned char *p, *end; @@ -4385,7 +4386,7 @@ static int ssl_parse_certificate_verify( mbedtls_ssl_context *ssl ) #if defined(MBEDTLS_SSL_SESSION_TICKETS) static int ssl_write_new_session_ticket( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t tlen; uint32_t lifetime; diff --git a/features/mbedtls/src/ssl_ticket.c b/features/mbedtls/src/ssl_ticket.c index 6dad5d1b29..8a76b42b6b 100644 --- a/features/mbedtls/src/ssl_ticket.c +++ b/features/mbedtls/src/ssl_ticket.c @@ -36,6 +36,7 @@ #endif #include "mbedtls/ssl_ticket.h" +#include "mbedtls/error.h" #include "mbedtls/platform_util.h" #include @@ -73,7 +74,7 @@ void mbedtls_ssl_ticket_init( mbedtls_ssl_ticket_context *ctx ) static int ssl_ticket_gen_key( mbedtls_ssl_ticket_context *ctx, unsigned char index ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char buf[MAX_KEY_BYTES]; mbedtls_ssl_ticket_key *key = ctx->keys + index; @@ -133,7 +134,7 @@ int mbedtls_ssl_ticket_setup( mbedtls_ssl_ticket_context *ctx, mbedtls_cipher_type_t cipher, uint32_t lifetime ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const mbedtls_cipher_info_t *cipher_info; ctx->f_rng = f_rng; @@ -206,7 +207,7 @@ int mbedtls_ssl_ticket_write( void *p_ticket, size_t *tlen, uint32_t *ticket_lifetime ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ssl_ticket_context *ctx = p_ticket; mbedtls_ssl_ticket_key *key; unsigned char *key_name = start; @@ -306,7 +307,7 @@ int mbedtls_ssl_ticket_parse( void *p_ticket, unsigned char *buf, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ssl_ticket_context *ctx = p_ticket; mbedtls_ssl_ticket_key *key; unsigned char *key_name = buf; diff --git a/features/mbedtls/src/ssl_tls.c b/features/mbedtls/src/ssl_tls.c index 4e7c01bc9e..63bc5c850c 100644 --- a/features/mbedtls/src/ssl_tls.c +++ b/features/mbedtls/src/ssl_tls.c @@ -43,9 +43,10 @@ #define mbedtls_free free #endif -#include "mbedtls/debug.h" #include "mbedtls/ssl.h" #include "mbedtls/ssl_internal.h" +#include "mbedtls/debug.h" +#include "mbedtls/error.h" #include "mbedtls/platform_util.h" #include "mbedtls/version.h" @@ -60,123 +61,6 @@ #include "mbedtls/oid.h" #endif -static void ssl_reset_in_out_pointers( mbedtls_ssl_context *ssl ); -static uint32_t ssl_get_hs_total_len( mbedtls_ssl_context const *ssl ); - -/* Length of the "epoch" field in the record header */ -static inline size_t ssl_ep_len( const mbedtls_ssl_context *ssl ) -{ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - return( 2 ); -#else - ((void) ssl); -#endif - return( 0 ); -} - -/* - * Start a timer. - * Passing millisecs = 0 cancels a running timer. - */ -static void ssl_set_timer( mbedtls_ssl_context *ssl, uint32_t millisecs ) -{ - if( ssl->f_set_timer == NULL ) - return; - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "set_timer to %d ms", (int) millisecs ) ); - ssl->f_set_timer( ssl->p_timer, millisecs / 4, millisecs ); -} - -/* - * Return -1 is timer is expired, 0 if it isn't. - */ -static int ssl_check_timer( mbedtls_ssl_context *ssl ) -{ - if( ssl->f_get_timer == NULL ) - return( 0 ); - - if( ssl->f_get_timer( ssl->p_timer ) == 2 ) - { - MBEDTLS_SSL_DEBUG_MSG( 3, ( "timer expired" ) ); - return( -1 ); - } - - return( 0 ); -} - -static void ssl_update_out_pointers( mbedtls_ssl_context *ssl, - mbedtls_ssl_transform *transform ); -static void ssl_update_in_pointers( mbedtls_ssl_context *ssl ); - -#if defined(MBEDTLS_SSL_RECORD_CHECKING) -static int ssl_parse_record_header( mbedtls_ssl_context const *ssl, - unsigned char *buf, - size_t len, - mbedtls_record *rec ); - -int mbedtls_ssl_check_record( mbedtls_ssl_context const *ssl, - unsigned char *buf, - size_t buflen ) -{ - int ret = 0; - mbedtls_record rec; - MBEDTLS_SSL_DEBUG_MSG( 1, ( "=> mbedtls_ssl_check_record" ) ); - MBEDTLS_SSL_DEBUG_BUF( 3, "record buffer", buf, buflen ); - - /* We don't support record checking in TLS because - * (a) there doesn't seem to be a usecase for it, and - * (b) In SSLv3 and TLS 1.0, CBC record decryption has state - * and we'd need to backup the transform here. - */ - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_STREAM ) - { - ret = MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE; - goto exit; - } -#if defined(MBEDTLS_SSL_PROTO_DTLS) - else - { - ret = ssl_parse_record_header( ssl, buf, buflen, &rec ); - if( ret != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 3, "ssl_parse_record_header", ret ); - goto exit; - } - - if( ssl->transform_in != NULL ) - { - ret = mbedtls_ssl_decrypt_buf( ssl, ssl->transform_in, &rec ); - if( ret != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 3, "mbedtls_ssl_decrypt_buf", ret ); - goto exit; - } - } - } -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - -exit: - /* On success, we have decrypted the buffer in-place, so make - * sure we don't leak any plaintext data. */ - mbedtls_platform_zeroize( buf, buflen ); - - /* For the purpose of this API, treat messages with unexpected CID - * as well as such from future epochs as unexpected. */ - if( ret == MBEDTLS_ERR_SSL_UNEXPECTED_CID || - ret == MBEDTLS_ERR_SSL_EARLY_MESSAGE ) - { - ret = MBEDTLS_ERR_SSL_UNEXPECTED_RECORD; - } - - MBEDTLS_SSL_DEBUG_MSG( 1, ( "<= mbedtls_ssl_check_record" ) ); - return( ret ); -} -#endif /* MBEDTLS_SSL_RECORD_CHECKING */ - -#define SSL_DONT_FORCE_FLUSH 0 -#define SSL_FORCE_FLUSH 1 - #if defined(MBEDTLS_SSL_PROTO_DTLS) #if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) @@ -272,137 +156,6 @@ int mbedtls_ssl_get_peer_cid( mbedtls_ssl_context *ssl, } #endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ -/* Forward declarations for functions related to message buffering. */ -static void ssl_buffering_free( mbedtls_ssl_context *ssl ); -static void ssl_buffering_free_slot( mbedtls_ssl_context *ssl, - uint8_t slot ); -static void ssl_free_buffered_record( mbedtls_ssl_context *ssl ); -static int ssl_load_buffered_message( mbedtls_ssl_context *ssl ); -static int ssl_load_buffered_record( mbedtls_ssl_context *ssl ); -static int ssl_buffer_message( mbedtls_ssl_context *ssl ); -static int ssl_buffer_future_record( mbedtls_ssl_context *ssl, - mbedtls_record const *rec ); -static int ssl_next_record_is_in_datagram( mbedtls_ssl_context *ssl ); - -static size_t ssl_get_current_mtu( const mbedtls_ssl_context *ssl ); -static size_t ssl_get_maximum_datagram_size( mbedtls_ssl_context const *ssl ) -{ - size_t mtu = ssl_get_current_mtu( ssl ); - - if( mtu != 0 && mtu < MBEDTLS_SSL_OUT_BUFFER_LEN ) - return( mtu ); - - return( MBEDTLS_SSL_OUT_BUFFER_LEN ); -} - -static int ssl_get_remaining_space_in_datagram( mbedtls_ssl_context const *ssl ) -{ - size_t const bytes_written = ssl->out_left; - size_t const mtu = ssl_get_maximum_datagram_size( ssl ); - - /* Double-check that the write-index hasn't gone - * past what we can transmit in a single datagram. */ - if( bytes_written > mtu ) - { - /* Should never happen... */ - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - return( (int) ( mtu - bytes_written ) ); -} - -static int ssl_get_remaining_payload_in_datagram( mbedtls_ssl_context const *ssl ) -{ - int ret; - size_t remaining, expansion; - size_t max_len = MBEDTLS_SSL_OUT_CONTENT_LEN; - -#if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) - const size_t mfl = mbedtls_ssl_get_max_frag_len( ssl ); - - if( max_len > mfl ) - max_len = mfl; - - /* By the standard (RFC 6066 Sect. 4), the MFL extension - * only limits the maximum record payload size, so in theory - * we would be allowed to pack multiple records of payload size - * MFL into a single datagram. However, this would mean that there's - * no way to explicitly communicate MTU restrictions to the peer. - * - * The following reduction of max_len makes sure that we never - * write datagrams larger than MFL + Record Expansion Overhead. - */ - if( max_len <= ssl->out_left ) - return( 0 ); - - max_len -= ssl->out_left; -#endif - - ret = ssl_get_remaining_space_in_datagram( ssl ); - if( ret < 0 ) - return( ret ); - remaining = (size_t) ret; - - ret = mbedtls_ssl_get_record_expansion( ssl ); - if( ret < 0 ) - return( ret ); - expansion = (size_t) ret; - - if( remaining <= expansion ) - return( 0 ); - - remaining -= expansion; - if( remaining >= max_len ) - remaining = max_len; - - return( (int) remaining ); -} - -/* - * Double the retransmit timeout value, within the allowed range, - * returning -1 if the maximum value has already been reached. - */ -static int ssl_double_retransmit_timeout( mbedtls_ssl_context *ssl ) -{ - uint32_t new_timeout; - - if( ssl->handshake->retransmit_timeout >= ssl->conf->hs_timeout_max ) - return( -1 ); - - /* Implement the final paragraph of RFC 6347 section 4.1.1.1 - * in the following way: after the initial transmission and a first - * retransmission, back off to a temporary estimated MTU of 508 bytes. - * This value is guaranteed to be deliverable (if not guaranteed to be - * delivered) of any compliant IPv4 (and IPv6) network, and should work - * on most non-IP stacks too. */ - if( ssl->handshake->retransmit_timeout != ssl->conf->hs_timeout_min ) - { - ssl->handshake->mtu = 508; - MBEDTLS_SSL_DEBUG_MSG( 2, ( "mtu autoreduction to %d bytes", ssl->handshake->mtu ) ); - } - - new_timeout = 2 * ssl->handshake->retransmit_timeout; - - /* Avoid arithmetic overflow and range overflow */ - if( new_timeout < ssl->handshake->retransmit_timeout || - new_timeout > ssl->conf->hs_timeout_max ) - { - new_timeout = ssl->conf->hs_timeout_max; - } - - ssl->handshake->retransmit_timeout = new_timeout; - MBEDTLS_SSL_DEBUG_MSG( 3, ( "update timeout value to %d millisecs", - ssl->handshake->retransmit_timeout ) ); - - return( 0 ); -} - -static void ssl_reset_retransmit_timeout( mbedtls_ssl_context *ssl ) -{ - ssl->handshake->retransmit_timeout = ssl->conf->hs_timeout_min; - MBEDTLS_SSL_DEBUG_MSG( 3, ( "update timeout value to %d millisecs", - ssl->handshake->retransmit_timeout ) ); -} #endif /* MBEDTLS_SSL_PROTO_DTLS */ #if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) @@ -445,7 +198,7 @@ int mbedtls_ssl_session_copy( mbedtls_ssl_session *dst, #if defined(MBEDTLS_SSL_KEEP_PEER_CERTIFICATE) if( src->peer_cert != NULL ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; dst->peer_cert = mbedtls_calloc( 1, sizeof(mbedtls_x509_crt) ); if( dst->peer_cert == NULL ) @@ -492,21 +245,6 @@ int mbedtls_ssl_session_copy( mbedtls_ssl_session *dst, return( 0 ); } -#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL) -int (*mbedtls_ssl_hw_record_init)( mbedtls_ssl_context *ssl, - const unsigned char *key_enc, const unsigned char *key_dec, - size_t keylen, - const unsigned char *iv_enc, const unsigned char *iv_dec, - size_t ivlen, - const unsigned char *mac_enc, const unsigned char *mac_dec, - size_t maclen ) = NULL; -int (*mbedtls_ssl_hw_record_activate)( mbedtls_ssl_context *ssl, int direction) = NULL; -int (*mbedtls_ssl_hw_record_reset)( mbedtls_ssl_context *ssl ) = NULL; -int (*mbedtls_ssl_hw_record_write)( mbedtls_ssl_context *ssl ) = NULL; -int (*mbedtls_ssl_hw_record_read)( mbedtls_ssl_context *ssl ) = NULL; -int (*mbedtls_ssl_hw_record_finish)( mbedtls_ssl_context *ssl ) = NULL; -#endif /* MBEDTLS_SSL_HW_RECORD_ACCEL */ - /* * Key material generation */ @@ -585,7 +323,7 @@ static int tls1_prf( const unsigned char *secret, size_t slen, unsigned char h_i[20]; const mbedtls_md_info_t *md_info; mbedtls_md_context_t md_ctx; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_md_init( &md_ctx ); @@ -831,7 +569,7 @@ static int tls_prf_generic( mbedtls_md_type_t md_type, unsigned char h_i[MBEDTLS_MD_MAX_SIZE]; const mbedtls_md_info_t *md_info; mbedtls_md_context_t md_ctx; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_md_init( &md_ctx ); @@ -1682,7 +1420,7 @@ static int ssl_compute_master( mbedtls_ssl_handshake_params *handshake, unsigned char *master, const mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* cf. RFC 5246, Section 8.1: * "The master secret is always exactly 48 bytes in length." */ @@ -1809,7 +1547,7 @@ static int ssl_compute_master( mbedtls_ssl_handshake_params *handshake, int mbedtls_ssl_derive_keys( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const mbedtls_ssl_ciphersuite_t * const ciphersuite_info = ssl->handshake->ciphersuite_info; @@ -1878,7 +1616,7 @@ int mbedtls_ssl_derive_keys( mbedtls_ssl_context *ssl ) /* Allocate compression buffer */ #if defined(MBEDTLS_ZLIB_SUPPORT) - if( session->compression == MBEDTLS_SSL_COMPRESS_DEFLATE && + if( ssl->session_negotiate->compression == MBEDTLS_SSL_COMPRESS_DEFLATE && ssl->compress_buf == NULL ) { MBEDTLS_SSL_DEBUG_MSG( 3, ( "Allocating compression buffer" ) ); @@ -2139,7 +1877,7 @@ int mbedtls_ssl_psk_derive_premaster( mbedtls_ssl_context *ssl, mbedtls_key_exch #if defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) if( key_ex == MBEDTLS_KEY_EXCHANGE_DHE_PSK ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; /* Write length only when we know the actual value */ @@ -2161,7 +1899,7 @@ int mbedtls_ssl_psk_derive_premaster( mbedtls_ssl_context *ssl, mbedtls_key_exch #if defined(MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED) if( key_ex == MBEDTLS_KEY_EXCHANGE_ECDHE_PSK ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t zlen; if( ( ret = mbedtls_ecdh_calc_secret( &ssl->handshake->ecdh_ctx, &zlen, @@ -2205,1361 +1943,11 @@ int mbedtls_ssl_psk_derive_premaster( mbedtls_ssl_context *ssl, mbedtls_key_exch } #endif /* MBEDTLS_KEY_EXCHANGE__SOME__PSK_ENABLED */ -#if defined(MBEDTLS_SSL_PROTO_SSL3) -/* - * SSLv3.0 MAC functions - */ -#define SSL_MAC_MAX_BYTES 20 /* MD-5 or SHA-1 */ -static void ssl_mac( mbedtls_md_context_t *md_ctx, - const unsigned char *secret, - const unsigned char *buf, size_t len, - const unsigned char *ctr, int type, - unsigned char out[SSL_MAC_MAX_BYTES] ) -{ - unsigned char header[11]; - unsigned char padding[48]; - int padlen; - int md_size = mbedtls_md_get_size( md_ctx->md_info ); - int md_type = mbedtls_md_get_type( md_ctx->md_info ); - - /* Only MD5 and SHA-1 supported */ - if( md_type == MBEDTLS_MD_MD5 ) - padlen = 48; - else - padlen = 40; - - memcpy( header, ctr, 8 ); - header[ 8] = (unsigned char) type; - header[ 9] = (unsigned char)( len >> 8 ); - header[10] = (unsigned char)( len ); - - memset( padding, 0x36, padlen ); - mbedtls_md_starts( md_ctx ); - mbedtls_md_update( md_ctx, secret, md_size ); - mbedtls_md_update( md_ctx, padding, padlen ); - mbedtls_md_update( md_ctx, header, 11 ); - mbedtls_md_update( md_ctx, buf, len ); - mbedtls_md_finish( md_ctx, out ); - - memset( padding, 0x5C, padlen ); - mbedtls_md_starts( md_ctx ); - mbedtls_md_update( md_ctx, secret, md_size ); - mbedtls_md_update( md_ctx, padding, padlen ); - mbedtls_md_update( md_ctx, out, md_size ); - mbedtls_md_finish( md_ctx, out ); -} -#endif /* MBEDTLS_SSL_PROTO_SSL3 */ - -/* The function below is only used in the Lucky 13 counter-measure in - * mbedtls_ssl_decrypt_buf(). These are the defines that guard the call site. */ -#if defined(MBEDTLS_SSL_SOME_MODES_USE_MAC) && \ - ( defined(MBEDTLS_SSL_PROTO_TLS1) || \ - defined(MBEDTLS_SSL_PROTO_TLS1_1) || \ - defined(MBEDTLS_SSL_PROTO_TLS1_2) ) -/* This function makes sure every byte in the memory region is accessed - * (in ascending addresses order) */ -static void ssl_read_memory( unsigned char *p, size_t len ) -{ - unsigned char acc = 0; - volatile unsigned char force; - - for( ; len != 0; p++, len-- ) - acc ^= *p; - - force = acc; - (void) force; -} -#endif /* SSL_SOME_MODES_USE_MAC && ( TLS1 || TLS1_1 || TLS1_2 ) */ - -/* - * Encryption/decryption functions - */ - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) -/* This functions transforms a DTLS plaintext fragment and a record content - * type into an instance of the DTLSInnerPlaintext structure: - * - * struct { - * opaque content[DTLSPlaintext.length]; - * ContentType real_type; - * uint8 zeros[length_of_padding]; - * } DTLSInnerPlaintext; - * - * Input: - * - `content`: The beginning of the buffer holding the - * plaintext to be wrapped. - * - `*content_size`: The length of the plaintext in Bytes. - * - `max_len`: The number of Bytes available starting from - * `content`. This must be `>= *content_size`. - * - `rec_type`: The desired record content type. - * - * Output: - * - `content`: The beginning of the resulting DTLSInnerPlaintext structure. - * - `*content_size`: The length of the resulting DTLSInnerPlaintext structure. - * - * Returns: - * - `0` on success. - * - A negative error code if `max_len` didn't offer enough space - * for the expansion. - */ -static int ssl_cid_build_inner_plaintext( unsigned char *content, - size_t *content_size, - size_t remaining, - uint8_t rec_type ) -{ - size_t len = *content_size; - size_t pad = ( MBEDTLS_SSL_CID_PADDING_GRANULARITY - - ( len + 1 ) % MBEDTLS_SSL_CID_PADDING_GRANULARITY ) % - MBEDTLS_SSL_CID_PADDING_GRANULARITY; - - /* Write real content type */ - if( remaining == 0 ) - return( -1 ); - content[ len ] = rec_type; - len++; - remaining--; - - if( remaining < pad ) - return( -1 ); - memset( content + len, 0, pad ); - len += pad; - remaining -= pad; - - *content_size = len; - return( 0 ); -} - -/* This function parses a DTLSInnerPlaintext structure. - * See ssl_cid_build_inner_plaintext() for details. */ -static int ssl_cid_parse_inner_plaintext( unsigned char const *content, - size_t *content_size, - uint8_t *rec_type ) -{ - size_t remaining = *content_size; - - /* Determine length of padding by skipping zeroes from the back. */ - do - { - if( remaining == 0 ) - return( -1 ); - remaining--; - } while( content[ remaining ] == 0 ); - - *content_size = remaining; - *rec_type = content[ remaining ]; - - return( 0 ); -} -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - -/* `add_data` must have size 13 Bytes if the CID extension is disabled, - * and 13 + 1 + CID-length Bytes if the CID extension is enabled. */ -static void ssl_extract_add_data_from_record( unsigned char* add_data, - size_t *add_data_len, - mbedtls_record *rec ) -{ - /* Quoting RFC 5246 (TLS 1.2): - * - * additional_data = seq_num + TLSCompressed.type + - * TLSCompressed.version + TLSCompressed.length; - * - * For the CID extension, this is extended as follows - * (quoting draft-ietf-tls-dtls-connection-id-05, - * https://tools.ietf.org/html/draft-ietf-tls-dtls-connection-id-05): - * - * additional_data = seq_num + DTLSPlaintext.type + - * DTLSPlaintext.version + - * cid + - * cid_length + - * length_of_DTLSInnerPlaintext; - */ - - memcpy( add_data, rec->ctr, sizeof( rec->ctr ) ); - add_data[8] = rec->type; - memcpy( add_data + 9, rec->ver, sizeof( rec->ver ) ); - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - if( rec->cid_len != 0 ) - { - memcpy( add_data + 11, rec->cid, rec->cid_len ); - add_data[11 + rec->cid_len + 0] = rec->cid_len; - add_data[11 + rec->cid_len + 1] = ( rec->data_len >> 8 ) & 0xFF; - add_data[11 + rec->cid_len + 2] = ( rec->data_len >> 0 ) & 0xFF; - *add_data_len = 13 + 1 + rec->cid_len; - } - else -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - { - add_data[11 + 0] = ( rec->data_len >> 8 ) & 0xFF; - add_data[11 + 1] = ( rec->data_len >> 0 ) & 0xFF; - *add_data_len = 13; - } -} - -int mbedtls_ssl_encrypt_buf( mbedtls_ssl_context *ssl, - mbedtls_ssl_transform *transform, - mbedtls_record *rec, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng ) -{ - mbedtls_cipher_mode_t mode; - int auth_done = 0; - unsigned char * data; - unsigned char add_data[13 + 1 + MBEDTLS_SSL_CID_OUT_LEN_MAX ]; - size_t add_data_len; - size_t post_avail; - - /* The SSL context is only used for debugging purposes! */ -#if !defined(MBEDTLS_DEBUG_C) - ssl = NULL; /* make sure we don't use it except for debug */ - ((void) ssl); -#endif - - /* The PRNG is used for dynamic IV generation that's used - * for CBC transformations in TLS 1.1 and TLS 1.2. */ -#if !( defined(MBEDTLS_CIPHER_MODE_CBC) && \ - ( defined(MBEDTLS_AES_C) || \ - defined(MBEDTLS_ARIA_C) || \ - defined(MBEDTLS_CAMELLIA_C) ) && \ - ( defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2) ) ) - ((void) f_rng); - ((void) p_rng); -#endif - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> encrypt buf" ) ); - - if( transform == NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "no transform provided to encrypt_buf" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - if( rec == NULL - || rec->buf == NULL - || rec->buf_len < rec->data_offset - || rec->buf_len - rec->data_offset < rec->data_len -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - || rec->cid_len != 0 -#endif - ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad record structure provided to encrypt_buf" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - data = rec->buf + rec->data_offset; - post_avail = rec->buf_len - ( rec->data_len + rec->data_offset ); - MBEDTLS_SSL_DEBUG_BUF( 4, "before encrypt: output payload", - data, rec->data_len ); - - mode = mbedtls_cipher_get_cipher_mode( &transform->cipher_ctx_enc ); - - if( rec->data_len > MBEDTLS_SSL_OUT_CONTENT_LEN ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "Record content %u too large, maximum %d", - (unsigned) rec->data_len, - MBEDTLS_SSL_OUT_CONTENT_LEN ) ); - return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - } - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - /* - * Add CID information - */ - rec->cid_len = transform->out_cid_len; - memcpy( rec->cid, transform->out_cid, transform->out_cid_len ); - MBEDTLS_SSL_DEBUG_BUF( 3, "CID", rec->cid, rec->cid_len ); - - if( rec->cid_len != 0 ) - { - /* - * Wrap plaintext into DTLSInnerPlaintext structure. - * See ssl_cid_build_inner_plaintext() for more information. - * - * Note that this changes `rec->data_len`, and hence - * `post_avail` needs to be recalculated afterwards. - */ - if( ssl_cid_build_inner_plaintext( data, - &rec->data_len, - post_avail, - rec->type ) != 0 ) - { - return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); - } - - rec->type = MBEDTLS_SSL_MSG_CID; - } -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - - post_avail = rec->buf_len - ( rec->data_len + rec->data_offset ); - - /* - * Add MAC before if needed - */ -#if defined(MBEDTLS_SSL_SOME_MODES_USE_MAC) - if( mode == MBEDTLS_MODE_STREAM || - ( mode == MBEDTLS_MODE_CBC -#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) - && transform->encrypt_then_mac == MBEDTLS_SSL_ETM_DISABLED -#endif - ) ) - { - if( post_avail < transform->maclen ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "Buffer provided for encrypted record not large enough" ) ); - return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); - } - -#if defined(MBEDTLS_SSL_PROTO_SSL3) - if( transform->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 ) - { - unsigned char mac[SSL_MAC_MAX_BYTES]; - ssl_mac( &transform->md_ctx_enc, transform->mac_enc, - data, rec->data_len, rec->ctr, rec->type, mac ); - memcpy( data + rec->data_len, mac, transform->maclen ); - } - else -#endif -#if defined(MBEDTLS_SSL_PROTO_TLS1) || defined(MBEDTLS_SSL_PROTO_TLS1_1) || \ - defined(MBEDTLS_SSL_PROTO_TLS1_2) - if( transform->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_1 ) - { - unsigned char mac[MBEDTLS_SSL_MAC_ADD]; - - ssl_extract_add_data_from_record( add_data, &add_data_len, rec ); - - mbedtls_md_hmac_update( &transform->md_ctx_enc, add_data, - add_data_len ); - mbedtls_md_hmac_update( &transform->md_ctx_enc, - data, rec->data_len ); - mbedtls_md_hmac_finish( &transform->md_ctx_enc, mac ); - mbedtls_md_hmac_reset( &transform->md_ctx_enc ); - - memcpy( data + rec->data_len, mac, transform->maclen ); - } - else -#endif - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - MBEDTLS_SSL_DEBUG_BUF( 4, "computed mac", data + rec->data_len, - transform->maclen ); - - rec->data_len += transform->maclen; - post_avail -= transform->maclen; - auth_done++; - } -#endif /* MBEDTLS_SSL_SOME_MODES_USE_MAC */ - - /* - * Encrypt - */ -#if defined(MBEDTLS_ARC4_C) || defined(MBEDTLS_CIPHER_NULL_CIPHER) - if( mode == MBEDTLS_MODE_STREAM ) - { - int ret; - size_t olen; - MBEDTLS_SSL_DEBUG_MSG( 3, ( "before encrypt: msglen = %d, " - "including %d bytes of padding", - rec->data_len, 0 ) ); - - if( ( ret = mbedtls_cipher_crypt( &transform->cipher_ctx_enc, - transform->iv_enc, transform->ivlen, - data, rec->data_len, - data, &olen ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_crypt", ret ); - return( ret ); - } - - if( rec->data_len != olen ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - } - else -#endif /* MBEDTLS_ARC4_C || MBEDTLS_CIPHER_NULL_CIPHER */ - -#if defined(MBEDTLS_GCM_C) || \ - defined(MBEDTLS_CCM_C) || \ - defined(MBEDTLS_CHACHAPOLY_C) - if( mode == MBEDTLS_MODE_GCM || - mode == MBEDTLS_MODE_CCM || - mode == MBEDTLS_MODE_CHACHAPOLY ) - { - int ret; - unsigned char iv[12]; - size_t explicit_iv_len = transform->ivlen - transform->fixed_ivlen; - - /* Check that there's space for both the authentication tag - * and the explicit IV before and after the record content. */ - if( post_avail < transform->taglen || - rec->data_offset < explicit_iv_len ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "Buffer provided for encrypted record not large enough" ) ); - return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); - } - - /* - * Generate IV - */ - if( transform->ivlen == 12 && transform->fixed_ivlen == 4 ) - { - /* GCM and CCM: fixed || explicit (=seqnum) */ - memcpy( iv, transform->iv_enc, transform->fixed_ivlen ); - memcpy( iv + transform->fixed_ivlen, rec->ctr, - explicit_iv_len ); - /* Prefix record content with explicit IV. */ - memcpy( data - explicit_iv_len, rec->ctr, explicit_iv_len ); - } - else if( transform->ivlen == 12 && transform->fixed_ivlen == 12 ) - { - /* ChachaPoly: fixed XOR sequence number */ - unsigned char i; - - memcpy( iv, transform->iv_enc, transform->fixed_ivlen ); - - for( i = 0; i < 8; i++ ) - iv[i+4] ^= rec->ctr[i]; - } - else - { - /* Reminder if we ever add an AEAD mode with a different size */ - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - ssl_extract_add_data_from_record( add_data, &add_data_len, rec ); - - MBEDTLS_SSL_DEBUG_BUF( 4, "IV used (internal)", - iv, transform->ivlen ); - MBEDTLS_SSL_DEBUG_BUF( 4, "IV used (transmitted)", - data - explicit_iv_len, explicit_iv_len ); - MBEDTLS_SSL_DEBUG_BUF( 4, "additional data used for AEAD", - add_data, add_data_len ); - MBEDTLS_SSL_DEBUG_MSG( 3, ( "before encrypt: msglen = %d, " - "including 0 bytes of padding", - rec->data_len ) ); - - /* - * Encrypt and authenticate - */ - - if( ( ret = mbedtls_cipher_auth_encrypt( &transform->cipher_ctx_enc, - iv, transform->ivlen, - add_data, add_data_len, /* add data */ - data, rec->data_len, /* source */ - data, &rec->data_len, /* destination */ - data + rec->data_len, transform->taglen ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_auth_encrypt", ret ); - return( ret ); - } - - MBEDTLS_SSL_DEBUG_BUF( 4, "after encrypt: tag", - data + rec->data_len, transform->taglen ); - - rec->data_len += transform->taglen + explicit_iv_len; - rec->data_offset -= explicit_iv_len; - post_avail -= transform->taglen; - auth_done++; - } - else -#endif /* MBEDTLS_GCM_C || MBEDTLS_CCM_C */ -#if defined(MBEDTLS_CIPHER_MODE_CBC) && \ - ( defined(MBEDTLS_AES_C) || defined(MBEDTLS_CAMELLIA_C) || defined(MBEDTLS_ARIA_C) ) - if( mode == MBEDTLS_MODE_CBC ) - { - int ret; - size_t padlen, i; - size_t olen; - - /* Currently we're always using minimal padding - * (up to 255 bytes would be allowed). */ - padlen = transform->ivlen - ( rec->data_len + 1 ) % transform->ivlen; - if( padlen == transform->ivlen ) - padlen = 0; - - /* Check there's enough space in the buffer for the padding. */ - if( post_avail < padlen + 1 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "Buffer provided for encrypted record not large enough" ) ); - return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); - } - - for( i = 0; i <= padlen; i++ ) - data[rec->data_len + i] = (unsigned char) padlen; - - rec->data_len += padlen + 1; - post_avail -= padlen + 1; - -#if defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2) - /* - * Prepend per-record IV for block cipher in TLS v1.1 and up as per - * Method 1 (6.2.3.2. in RFC4346 and RFC5246) - */ - if( transform->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_2 ) - { - if( f_rng == NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "No PRNG provided to encrypt_record routine" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - if( rec->data_offset < transform->ivlen ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "Buffer provided for encrypted record not large enough" ) ); - return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); - } - - /* - * Generate IV - */ - ret = f_rng( p_rng, transform->iv_enc, transform->ivlen ); - if( ret != 0 ) - return( ret ); - - memcpy( data - transform->ivlen, transform->iv_enc, - transform->ivlen ); - - } -#endif /* MBEDTLS_SSL_PROTO_TLS1_1 || MBEDTLS_SSL_PROTO_TLS1_2 */ - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "before encrypt: msglen = %d, " - "including %d bytes of IV and %d bytes of padding", - rec->data_len, transform->ivlen, - padlen + 1 ) ); - - if( ( ret = mbedtls_cipher_crypt( &transform->cipher_ctx_enc, - transform->iv_enc, - transform->ivlen, - data, rec->data_len, - data, &olen ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_crypt", ret ); - return( ret ); - } - - if( rec->data_len != olen ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - -#if defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1) - if( transform->minor_ver < MBEDTLS_SSL_MINOR_VERSION_2 ) - { - /* - * Save IV in SSL3 and TLS1 - */ - memcpy( transform->iv_enc, transform->cipher_ctx_enc.iv, - transform->ivlen ); - } - else -#endif - { - data -= transform->ivlen; - rec->data_offset -= transform->ivlen; - rec->data_len += transform->ivlen; - } - -#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) - if( auth_done == 0 ) - { - unsigned char mac[MBEDTLS_SSL_MAC_ADD]; - - /* - * MAC(MAC_write_key, seq_num + - * TLSCipherText.type + - * TLSCipherText.version + - * length_of( (IV +) ENC(...) ) + - * IV + // except for TLS 1.0 - * ENC(content + padding + padding_length)); - */ - - if( post_avail < transform->maclen) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "Buffer provided for encrypted record not large enough" ) ); - return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); - } - - ssl_extract_add_data_from_record( add_data, &add_data_len, rec ); - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "using encrypt then mac" ) ); - MBEDTLS_SSL_DEBUG_BUF( 4, "MAC'd meta-data", add_data, - add_data_len ); - - mbedtls_md_hmac_update( &transform->md_ctx_enc, add_data, - add_data_len ); - mbedtls_md_hmac_update( &transform->md_ctx_enc, - data, rec->data_len ); - mbedtls_md_hmac_finish( &transform->md_ctx_enc, mac ); - mbedtls_md_hmac_reset( &transform->md_ctx_enc ); - - memcpy( data + rec->data_len, mac, transform->maclen ); - - rec->data_len += transform->maclen; - post_avail -= transform->maclen; - auth_done++; - } -#endif /* MBEDTLS_SSL_ENCRYPT_THEN_MAC */ - } - else -#endif /* MBEDTLS_CIPHER_MODE_CBC && - ( MBEDTLS_AES_C || MBEDTLS_CAMELLIA_C || MBEDTLS_ARIA_C ) */ - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - /* Make extra sure authentication was performed, exactly once */ - if( auth_done != 1 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= encrypt buf" ) ); - - return( 0 ); -} - -int mbedtls_ssl_decrypt_buf( mbedtls_ssl_context const *ssl, - mbedtls_ssl_transform *transform, - mbedtls_record *rec ) -{ - size_t olen; - mbedtls_cipher_mode_t mode; - int ret, auth_done = 0; -#if defined(MBEDTLS_SSL_SOME_MODES_USE_MAC) - size_t padlen = 0, correct = 1; -#endif - unsigned char* data; - unsigned char add_data[13 + 1 + MBEDTLS_SSL_CID_IN_LEN_MAX ]; - size_t add_data_len; - -#if !defined(MBEDTLS_DEBUG_C) - ssl = NULL; /* make sure we don't use it except for debug */ - ((void) ssl); -#endif - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> decrypt buf" ) ); - if( rec == NULL || - rec->buf == NULL || - rec->buf_len < rec->data_offset || - rec->buf_len - rec->data_offset < rec->data_len ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad record structure provided to decrypt_buf" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - data = rec->buf + rec->data_offset; - mode = mbedtls_cipher_get_cipher_mode( &transform->cipher_ctx_dec ); - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - /* - * Match record's CID with incoming CID. - */ - if( rec->cid_len != transform->in_cid_len || - memcmp( rec->cid, transform->in_cid, rec->cid_len ) != 0 ) - { - return( MBEDTLS_ERR_SSL_UNEXPECTED_CID ); - } -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - -#if defined(MBEDTLS_ARC4_C) || defined(MBEDTLS_CIPHER_NULL_CIPHER) - if( mode == MBEDTLS_MODE_STREAM ) - { - padlen = 0; - if( ( ret = mbedtls_cipher_crypt( &transform->cipher_ctx_dec, - transform->iv_dec, - transform->ivlen, - data, rec->data_len, - data, &olen ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_crypt", ret ); - return( ret ); - } - - if( rec->data_len != olen ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - } - else -#endif /* MBEDTLS_ARC4_C || MBEDTLS_CIPHER_NULL_CIPHER */ -#if defined(MBEDTLS_GCM_C) || \ - defined(MBEDTLS_CCM_C) || \ - defined(MBEDTLS_CHACHAPOLY_C) - if( mode == MBEDTLS_MODE_GCM || - mode == MBEDTLS_MODE_CCM || - mode == MBEDTLS_MODE_CHACHAPOLY ) - { - unsigned char iv[12]; - size_t explicit_iv_len = transform->ivlen - transform->fixed_ivlen; - - /* - * Prepare IV from explicit and implicit data. - */ - - /* Check that there's enough space for the explicit IV - * (at the beginning of the record) and the MAC (at the - * end of the record). */ - if( rec->data_len < explicit_iv_len + transform->taglen ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "msglen (%d) < explicit_iv_len (%d) " - "+ taglen (%d)", rec->data_len, - explicit_iv_len, transform->taglen ) ); - return( MBEDTLS_ERR_SSL_INVALID_MAC ); - } - -#if defined(MBEDTLS_GCM_C) || defined(MBEDTLS_CCM_C) - if( transform->ivlen == 12 && transform->fixed_ivlen == 4 ) - { - /* GCM and CCM: fixed || explicit */ - - /* Fixed */ - memcpy( iv, transform->iv_dec, transform->fixed_ivlen ); - /* Explicit */ - memcpy( iv + transform->fixed_ivlen, data, 8 ); - } - else -#endif /* MBEDTLS_GCM_C || MBEDTLS_CCM_C */ -#if defined(MBEDTLS_CHACHAPOLY_C) - if( transform->ivlen == 12 && transform->fixed_ivlen == 12 ) - { - /* ChachaPoly: fixed XOR sequence number */ - unsigned char i; - - memcpy( iv, transform->iv_dec, transform->fixed_ivlen ); - - for( i = 0; i < 8; i++ ) - iv[i+4] ^= rec->ctr[i]; - } - else -#endif /* MBEDTLS_CHACHAPOLY_C */ - { - /* Reminder if we ever add an AEAD mode with a different size */ - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - /* Group changes to data, data_len, and add_data, because - * add_data depends on data_len. */ - data += explicit_iv_len; - rec->data_offset += explicit_iv_len; - rec->data_len -= explicit_iv_len + transform->taglen; - - ssl_extract_add_data_from_record( add_data, &add_data_len, rec ); - MBEDTLS_SSL_DEBUG_BUF( 4, "additional data used for AEAD", - add_data, add_data_len ); - - /* Because of the check above, we know that there are - * explicit_iv_len Bytes preceeding data, and taglen - * bytes following data + data_len. This justifies - * the debug message and the invocation of - * mbedtls_cipher_auth_decrypt() below. */ - - MBEDTLS_SSL_DEBUG_BUF( 4, "IV used", iv, transform->ivlen ); - MBEDTLS_SSL_DEBUG_BUF( 4, "TAG used", data + rec->data_len, - transform->taglen ); - - /* - * Decrypt and authenticate - */ - if( ( ret = mbedtls_cipher_auth_decrypt( &transform->cipher_ctx_dec, - iv, transform->ivlen, - add_data, add_data_len, - data, rec->data_len, - data, &olen, - data + rec->data_len, - transform->taglen ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_auth_decrypt", ret ); - - if( ret == MBEDTLS_ERR_CIPHER_AUTH_FAILED ) - return( MBEDTLS_ERR_SSL_INVALID_MAC ); - - return( ret ); - } - auth_done++; - - /* Double-check that AEAD decryption doesn't change content length. */ - if( olen != rec->data_len ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - } - else -#endif /* MBEDTLS_GCM_C || MBEDTLS_CCM_C */ -#if defined(MBEDTLS_CIPHER_MODE_CBC) && \ - ( defined(MBEDTLS_AES_C) || defined(MBEDTLS_CAMELLIA_C) || defined(MBEDTLS_ARIA_C) ) - if( mode == MBEDTLS_MODE_CBC ) - { - size_t minlen = 0; - - /* - * Check immediate ciphertext sanity - */ -#if defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2) - if( transform->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_2 ) - { - /* The ciphertext is prefixed with the CBC IV. */ - minlen += transform->ivlen; - } -#endif - - /* Size considerations: - * - * - The CBC cipher text must not be empty and hence - * at least of size transform->ivlen. - * - * Together with the potential IV-prefix, this explains - * the first of the two checks below. - * - * - The record must contain a MAC, either in plain or - * encrypted, depending on whether Encrypt-then-MAC - * is used or not. - * - If it is, the message contains the IV-prefix, - * the CBC ciphertext, and the MAC. - * - If it is not, the padded plaintext, and hence - * the CBC ciphertext, has at least length maclen + 1 - * because there is at least the padding length byte. - * - * As the CBC ciphertext is not empty, both cases give the - * lower bound minlen + maclen + 1 on the record size, which - * we test for in the second check below. - */ - if( rec->data_len < minlen + transform->ivlen || - rec->data_len < minlen + transform->maclen + 1 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "msglen (%d) < max( ivlen(%d), maclen (%d) " - "+ 1 ) ( + expl IV )", rec->data_len, - transform->ivlen, - transform->maclen ) ); - return( MBEDTLS_ERR_SSL_INVALID_MAC ); - } - - /* - * Authenticate before decrypt if enabled - */ -#if defined(MBEDTLS_SSL_ENCRYPT_THEN_MAC) - if( transform->encrypt_then_mac == MBEDTLS_SSL_ETM_ENABLED ) - { - unsigned char mac_expect[MBEDTLS_SSL_MAC_ADD]; - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "using encrypt then mac" ) ); - - /* Update data_len in tandem with add_data. - * - * The subtraction is safe because of the previous check - * data_len >= minlen + maclen + 1. - * - * Afterwards, we know that data + data_len is followed by at - * least maclen Bytes, which justifies the call to - * mbedtls_ssl_safer_memcmp() below. - * - * Further, we still know that data_len > minlen */ - rec->data_len -= transform->maclen; - ssl_extract_add_data_from_record( add_data, &add_data_len, rec ); - - /* Calculate expected MAC. */ - MBEDTLS_SSL_DEBUG_BUF( 4, "MAC'd meta-data", add_data, - add_data_len ); - mbedtls_md_hmac_update( &transform->md_ctx_dec, add_data, - add_data_len ); - mbedtls_md_hmac_update( &transform->md_ctx_dec, - data, rec->data_len ); - mbedtls_md_hmac_finish( &transform->md_ctx_dec, mac_expect ); - mbedtls_md_hmac_reset( &transform->md_ctx_dec ); - - MBEDTLS_SSL_DEBUG_BUF( 4, "message mac", data + rec->data_len, - transform->maclen ); - MBEDTLS_SSL_DEBUG_BUF( 4, "expected mac", mac_expect, - transform->maclen ); - - /* Compare expected MAC with MAC at the end of the record. */ - if( mbedtls_ssl_safer_memcmp( data + rec->data_len, mac_expect, - transform->maclen ) != 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "message mac does not match" ) ); - return( MBEDTLS_ERR_SSL_INVALID_MAC ); - } - auth_done++; - } -#endif /* MBEDTLS_SSL_ENCRYPT_THEN_MAC */ - - /* - * Check length sanity - */ - - /* We know from above that data_len > minlen >= 0, - * so the following check in particular implies that - * data_len >= minlen + ivlen ( = minlen or 2 * minlen ). */ - if( rec->data_len % transform->ivlen != 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "msglen (%d) %% ivlen (%d) != 0", - rec->data_len, transform->ivlen ) ); - return( MBEDTLS_ERR_SSL_INVALID_MAC ); - } - -#if defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2) - /* - * Initialize for prepended IV for block cipher in TLS v1.1 and up - */ - if( transform->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_2 ) - { - /* Safe because data_len >= minlen + ivlen = 2 * ivlen. */ - memcpy( transform->iv_dec, data, transform->ivlen ); - - data += transform->ivlen; - rec->data_offset += transform->ivlen; - rec->data_len -= transform->ivlen; - } -#endif /* MBEDTLS_SSL_PROTO_TLS1_1 || MBEDTLS_SSL_PROTO_TLS1_2 */ - - /* We still have data_len % ivlen == 0 and data_len >= ivlen here. */ - - if( ( ret = mbedtls_cipher_crypt( &transform->cipher_ctx_dec, - transform->iv_dec, transform->ivlen, - data, rec->data_len, data, &olen ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_crypt", ret ); - return( ret ); - } - - /* Double-check that length hasn't changed during decryption. */ - if( rec->data_len != olen ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - -#if defined(MBEDTLS_SSL_PROTO_SSL3) || defined(MBEDTLS_SSL_PROTO_TLS1) - if( transform->minor_ver < MBEDTLS_SSL_MINOR_VERSION_2 ) - { - /* - * Save IV in SSL3 and TLS1, where CBC decryption of consecutive - * records is equivalent to CBC decryption of the concatenation - * of the records; in other words, IVs are maintained across - * record decryptions. - */ - memcpy( transform->iv_dec, transform->cipher_ctx_dec.iv, - transform->ivlen ); - } -#endif - - /* Safe since data_len >= minlen + maclen + 1, so after having - * subtracted at most minlen and maclen up to this point, - * data_len > 0 (because of data_len % ivlen == 0, it's actually - * >= ivlen ). */ - padlen = data[rec->data_len - 1]; - - if( auth_done == 1 ) - { - correct *= ( rec->data_len >= padlen + 1 ); - padlen *= ( rec->data_len >= padlen + 1 ); - } - else - { -#if defined(MBEDTLS_SSL_DEBUG_ALL) - if( rec->data_len < transform->maclen + padlen + 1 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "msglen (%d) < maclen (%d) + padlen (%d)", - rec->data_len, - transform->maclen, - padlen + 1 ) ); - } -#endif - - correct *= ( rec->data_len >= transform->maclen + padlen + 1 ); - padlen *= ( rec->data_len >= transform->maclen + padlen + 1 ); - } - - padlen++; - - /* Regardless of the validity of the padding, - * we have data_len >= padlen here. */ - -#if defined(MBEDTLS_SSL_PROTO_SSL3) - if( transform->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 ) - { - if( padlen > transform->ivlen ) - { -#if defined(MBEDTLS_SSL_DEBUG_ALL) - MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad padding length: is %d, " - "should be no more than %d", - padlen, transform->ivlen ) ); -#endif - correct = 0; - } - } - else -#endif /* MBEDTLS_SSL_PROTO_SSL3 */ -#if defined(MBEDTLS_SSL_PROTO_TLS1) || defined(MBEDTLS_SSL_PROTO_TLS1_1) || \ - defined(MBEDTLS_SSL_PROTO_TLS1_2) - if( transform->minor_ver > MBEDTLS_SSL_MINOR_VERSION_0 ) - { - /* The padding check involves a series of up to 256 - * consecutive memory reads at the end of the record - * plaintext buffer. In order to hide the length and - * validity of the padding, always perform exactly - * `min(256,plaintext_len)` reads (but take into account - * only the last `padlen` bytes for the padding check). */ - size_t pad_count = 0; - size_t real_count = 0; - volatile unsigned char* const check = data; - - /* Index of first padding byte; it has been ensured above - * that the subtraction is safe. */ - size_t const padding_idx = rec->data_len - padlen; - size_t const num_checks = rec->data_len <= 256 ? rec->data_len : 256; - size_t const start_idx = rec->data_len - num_checks; - size_t idx; - - for( idx = start_idx; idx < rec->data_len; idx++ ) - { - real_count |= ( idx >= padding_idx ); - pad_count += real_count * ( check[idx] == padlen - 1 ); - } - correct &= ( pad_count == padlen ); - -#if defined(MBEDTLS_SSL_DEBUG_ALL) - if( padlen > 0 && correct == 0 ) - MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad padding byte detected" ) ); -#endif - padlen &= correct * 0x1FF; - } - else -#endif /* MBEDTLS_SSL_PROTO_TLS1 || MBEDTLS_SSL_PROTO_TLS1_1 || \ - MBEDTLS_SSL_PROTO_TLS1_2 */ - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - /* If the padding was found to be invalid, padlen == 0 - * and the subtraction is safe. If the padding was found valid, - * padlen hasn't been changed and the previous assertion - * data_len >= padlen still holds. */ - rec->data_len -= padlen; - } - else -#endif /* MBEDTLS_CIPHER_MODE_CBC && - ( MBEDTLS_AES_C || MBEDTLS_CAMELLIA_C || MBEDTLS_ARIA_C ) */ - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - -#if defined(MBEDTLS_SSL_DEBUG_ALL) - MBEDTLS_SSL_DEBUG_BUF( 4, "raw buffer after decryption", - data, rec->data_len ); -#endif - - /* - * Authenticate if not done yet. - * Compute the MAC regardless of the padding result (RFC4346, CBCTIME). - */ -#if defined(MBEDTLS_SSL_SOME_MODES_USE_MAC) - if( auth_done == 0 ) - { - unsigned char mac_expect[MBEDTLS_SSL_MAC_ADD]; - - /* If the initial value of padlen was such that - * data_len < maclen + padlen + 1, then padlen - * got reset to 1, and the initial check - * data_len >= minlen + maclen + 1 - * guarantees that at this point we still - * have at least data_len >= maclen. - * - * If the initial value of padlen was such that - * data_len >= maclen + padlen + 1, then we have - * subtracted either padlen + 1 (if the padding was correct) - * or 0 (if the padding was incorrect) since then, - * hence data_len >= maclen in any case. - */ - rec->data_len -= transform->maclen; - ssl_extract_add_data_from_record( add_data, &add_data_len, rec ); - -#if defined(MBEDTLS_SSL_PROTO_SSL3) - if( transform->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 ) - { - ssl_mac( &transform->md_ctx_dec, - transform->mac_dec, - data, rec->data_len, - rec->ctr, rec->type, - mac_expect ); - } - else -#endif /* MBEDTLS_SSL_PROTO_SSL3 */ -#if defined(MBEDTLS_SSL_PROTO_TLS1) || defined(MBEDTLS_SSL_PROTO_TLS1_1) || \ - defined(MBEDTLS_SSL_PROTO_TLS1_2) - if( transform->minor_ver > MBEDTLS_SSL_MINOR_VERSION_0 ) - { - /* - * Process MAC and always update for padlen afterwards to make - * total time independent of padlen. - * - * Known timing attacks: - * - Lucky Thirteen (http://www.isg.rhul.ac.uk/tls/TLStiming.pdf) - * - * To compensate for different timings for the MAC calculation - * depending on how much padding was removed (which is determined - * by padlen), process extra_run more blocks through the hash - * function. - * - * The formula in the paper is - * extra_run = ceil( (L1-55) / 64 ) - ceil( (L2-55) / 64 ) - * where L1 is the size of the header plus the decrypted message - * plus CBC padding and L2 is the size of the header plus the - * decrypted message. This is for an underlying hash function - * with 64-byte blocks. - * We use ( (Lx+8) / 64 ) to handle 'negative Lx' values - * correctly. We round down instead of up, so -56 is the correct - * value for our calculations instead of -55. - * - * Repeat the formula rather than defining a block_size variable. - * This avoids requiring division by a variable at runtime - * (which would be marginally less efficient and would require - * linking an extra division function in some builds). - */ - size_t j, extra_run = 0; - unsigned char tmp[MBEDTLS_MD_MAX_BLOCK_SIZE]; - - /* - * The next two sizes are the minimum and maximum values of - * in_msglen over all padlen values. - * - * They're independent of padlen, since we previously did - * data_len -= padlen. - * - * Note that max_len + maclen is never more than the buffer - * length, as we previously did in_msglen -= maclen too. - */ - const size_t max_len = rec->data_len + padlen; - const size_t min_len = ( max_len > 256 ) ? max_len - 256 : 0; - - memset( tmp, 0, sizeof( tmp ) ); - - switch( mbedtls_md_get_type( transform->md_ctx_dec.md_info ) ) - { -#if defined(MBEDTLS_MD5_C) || defined(MBEDTLS_SHA1_C) || \ - defined(MBEDTLS_SHA256_C) - case MBEDTLS_MD_MD5: - case MBEDTLS_MD_SHA1: - case MBEDTLS_MD_SHA256: - /* 8 bytes of message size, 64-byte compression blocks */ - extra_run = - ( add_data_len + rec->data_len + padlen + 8 ) / 64 - - ( add_data_len + rec->data_len + 8 ) / 64; - break; -#endif -#if defined(MBEDTLS_SHA512_C) - case MBEDTLS_MD_SHA384: - /* 16 bytes of message size, 128-byte compression blocks */ - extra_run = - ( add_data_len + rec->data_len + padlen + 16 ) / 128 - - ( add_data_len + rec->data_len + 16 ) / 128; - break; -#endif - default: - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - extra_run &= correct * 0xFF; - - mbedtls_md_hmac_update( &transform->md_ctx_dec, add_data, - add_data_len ); - mbedtls_md_hmac_update( &transform->md_ctx_dec, data, - rec->data_len ); - /* Make sure we access everything even when padlen > 0. This - * makes the synchronisation requirements for just-in-time - * Prime+Probe attacks much tighter and hopefully impractical. */ - ssl_read_memory( data + rec->data_len, padlen ); - mbedtls_md_hmac_finish( &transform->md_ctx_dec, mac_expect ); - - /* Call mbedtls_md_process at least once due to cache attacks - * that observe whether md_process() was called of not */ - for( j = 0; j < extra_run + 1; j++ ) - mbedtls_md_process( &transform->md_ctx_dec, tmp ); - - mbedtls_md_hmac_reset( &transform->md_ctx_dec ); - - /* Make sure we access all the memory that could contain the MAC, - * before we check it in the next code block. This makes the - * synchronisation requirements for just-in-time Prime+Probe - * attacks much tighter and hopefully impractical. */ - ssl_read_memory( data + min_len, - max_len - min_len + transform->maclen ); - } - else -#endif /* MBEDTLS_SSL_PROTO_TLS1 || MBEDTLS_SSL_PROTO_TLS1_1 || \ - MBEDTLS_SSL_PROTO_TLS1_2 */ - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - -#if defined(MBEDTLS_SSL_DEBUG_ALL) - MBEDTLS_SSL_DEBUG_BUF( 4, "expected mac", mac_expect, transform->maclen ); - MBEDTLS_SSL_DEBUG_BUF( 4, "message mac", data + rec->data_len, transform->maclen ); -#endif - - if( mbedtls_ssl_safer_memcmp( data + rec->data_len, mac_expect, - transform->maclen ) != 0 ) - { -#if defined(MBEDTLS_SSL_DEBUG_ALL) - MBEDTLS_SSL_DEBUG_MSG( 1, ( "message mac does not match" ) ); -#endif - correct = 0; - } - auth_done++; - } - - /* - * Finally check the correct flag - */ - if( correct == 0 ) - return( MBEDTLS_ERR_SSL_INVALID_MAC ); -#endif /* MBEDTLS_SSL_SOME_MODES_USE_MAC */ - - /* Make extra sure authentication was performed, exactly once */ - if( auth_done != 1 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - if( rec->cid_len != 0 ) - { - ret = ssl_cid_parse_inner_plaintext( data, &rec->data_len, - &rec->type ); - if( ret != 0 ) - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= decrypt buf" ) ); - - return( 0 ); -} - -#undef MAC_NONE -#undef MAC_PLAINTEXT -#undef MAC_CIPHERTEXT - -#if defined(MBEDTLS_ZLIB_SUPPORT) -/* - * Compression/decompression functions - */ -static int ssl_compress_buf( mbedtls_ssl_context *ssl ) -{ - int ret; - unsigned char *msg_post = ssl->out_msg; - ptrdiff_t bytes_written = ssl->out_msg - ssl->out_buf; - size_t len_pre = ssl->out_msglen; - unsigned char *msg_pre = ssl->compress_buf; - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> compress buf" ) ); - - if( len_pre == 0 ) - return( 0 ); - - memcpy( msg_pre, ssl->out_msg, len_pre ); - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "before compression: msglen = %d, ", - ssl->out_msglen ) ); - - MBEDTLS_SSL_DEBUG_BUF( 4, "before compression: output payload", - ssl->out_msg, ssl->out_msglen ); - - ssl->transform_out->ctx_deflate.next_in = msg_pre; - ssl->transform_out->ctx_deflate.avail_in = len_pre; - ssl->transform_out->ctx_deflate.next_out = msg_post; - ssl->transform_out->ctx_deflate.avail_out = MBEDTLS_SSL_OUT_BUFFER_LEN - bytes_written; - - ret = deflate( &ssl->transform_out->ctx_deflate, Z_SYNC_FLUSH ); - if( ret != Z_OK ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "failed to perform compression (%d)", ret ) ); - return( MBEDTLS_ERR_SSL_COMPRESSION_FAILED ); - } - - ssl->out_msglen = MBEDTLS_SSL_OUT_BUFFER_LEN - - ssl->transform_out->ctx_deflate.avail_out - bytes_written; - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "after compression: msglen = %d, ", - ssl->out_msglen ) ); - - MBEDTLS_SSL_DEBUG_BUF( 4, "after compression: output payload", - ssl->out_msg, ssl->out_msglen ); - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= compress buf" ) ); - - return( 0 ); -} - -static int ssl_decompress_buf( mbedtls_ssl_context *ssl ) -{ - int ret; - unsigned char *msg_post = ssl->in_msg; - ptrdiff_t header_bytes = ssl->in_msg - ssl->in_buf; - size_t len_pre = ssl->in_msglen; - unsigned char *msg_pre = ssl->compress_buf; - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> decompress buf" ) ); - - if( len_pre == 0 ) - return( 0 ); - - memcpy( msg_pre, ssl->in_msg, len_pre ); - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "before decompression: msglen = %d, ", - ssl->in_msglen ) ); - - MBEDTLS_SSL_DEBUG_BUF( 4, "before decompression: input payload", - ssl->in_msg, ssl->in_msglen ); - - ssl->transform_in->ctx_inflate.next_in = msg_pre; - ssl->transform_in->ctx_inflate.avail_in = len_pre; - ssl->transform_in->ctx_inflate.next_out = msg_post; - ssl->transform_in->ctx_inflate.avail_out = MBEDTLS_SSL_IN_BUFFER_LEN - - header_bytes; - - ret = inflate( &ssl->transform_in->ctx_inflate, Z_SYNC_FLUSH ); - if( ret != Z_OK ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "failed to perform decompression (%d)", ret ) ); - return( MBEDTLS_ERR_SSL_COMPRESSION_FAILED ); - } - - ssl->in_msglen = MBEDTLS_SSL_IN_BUFFER_LEN - - ssl->transform_in->ctx_inflate.avail_out - header_bytes; - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "after decompression: msglen = %d, ", - ssl->in_msglen ) ); - - MBEDTLS_SSL_DEBUG_BUF( 4, "after decompression: input payload", - ssl->in_msg, ssl->in_msglen ); - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= decompress buf" ) ); - - return( 0 ); -} -#endif /* MBEDTLS_ZLIB_SUPPORT */ - #if defined(MBEDTLS_SSL_SRV_C) && defined(MBEDTLS_SSL_RENEGOTIATION) static int ssl_write_hello_request( mbedtls_ssl_context *ssl ); #if defined(MBEDTLS_SSL_PROTO_DTLS) -static int ssl_resend_hello_request( mbedtls_ssl_context *ssl ) +int mbedtls_ssl_resend_hello_request( mbedtls_ssl_context *ssl ) { /* If renegotiation is not enforced, retransmit until we would reach max * timeout if we were using the usual handshake doubling scheme */ @@ -3586,3045 +1974,6 @@ static int ssl_resend_hello_request( mbedtls_ssl_context *ssl ) #endif #endif /* MBEDTLS_SSL_SRV_C && MBEDTLS_SSL_RENEGOTIATION */ -/* - * Fill the input message buffer by appending data to it. - * The amount of data already fetched is in ssl->in_left. - * - * If we return 0, is it guaranteed that (at least) nb_want bytes are - * available (from this read and/or a previous one). Otherwise, an error code - * is returned (possibly EOF or WANT_READ). - * - * With stream transport (TLS) on success ssl->in_left == nb_want, but - * with datagram transport (DTLS) on success ssl->in_left >= nb_want, - * since we always read a whole datagram at once. - * - * For DTLS, it is up to the caller to set ssl->next_record_offset when - * they're done reading a record. - */ -int mbedtls_ssl_fetch_input( mbedtls_ssl_context *ssl, size_t nb_want ) -{ - int ret; - size_t len; - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> fetch input" ) ); - - if( ssl->f_recv == NULL && ssl->f_recv_timeout == NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "Bad usage of mbedtls_ssl_set_bio() " - "or mbedtls_ssl_set_bio()" ) ); - return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - } - - if( nb_want > MBEDTLS_SSL_IN_BUFFER_LEN - (size_t)( ssl->in_hdr - ssl->in_buf ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "requesting more data than fits" ) ); - return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - } - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - uint32_t timeout; - - /* Just to be sure */ - if( ssl->f_set_timer == NULL || ssl->f_get_timer == NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "You must use " - "mbedtls_ssl_set_timer_cb() for DTLS" ) ); - return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - } - - /* - * The point is, we need to always read a full datagram at once, so we - * sometimes read more then requested, and handle the additional data. - * It could be the rest of the current record (while fetching the - * header) and/or some other records in the same datagram. - */ - - /* - * Move to the next record in the already read datagram if applicable - */ - if( ssl->next_record_offset != 0 ) - { - if( ssl->in_left < ssl->next_record_offset ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - ssl->in_left -= ssl->next_record_offset; - - if( ssl->in_left != 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "next record in same datagram, offset: %d", - ssl->next_record_offset ) ); - memmove( ssl->in_hdr, - ssl->in_hdr + ssl->next_record_offset, - ssl->in_left ); - } - - ssl->next_record_offset = 0; - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "in_left: %d, nb_want: %d", - ssl->in_left, nb_want ) ); - - /* - * Done if we already have enough data. - */ - if( nb_want <= ssl->in_left) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= fetch input" ) ); - return( 0 ); - } - - /* - * A record can't be split across datagrams. If we need to read but - * are not at the beginning of a new record, the caller did something - * wrong. - */ - if( ssl->in_left != 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - /* - * Don't even try to read if time's out already. - * This avoids by-passing the timer when repeatedly receiving messages - * that will end up being dropped. - */ - if( ssl_check_timer( ssl ) != 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "timer has expired" ) ); - ret = MBEDTLS_ERR_SSL_TIMEOUT; - } - else - { - len = MBEDTLS_SSL_IN_BUFFER_LEN - ( ssl->in_hdr - ssl->in_buf ); - - if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER ) - timeout = ssl->handshake->retransmit_timeout; - else - timeout = ssl->conf->read_timeout; - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "f_recv_timeout: %u ms", timeout ) ); - - if( ssl->f_recv_timeout != NULL ) - ret = ssl->f_recv_timeout( ssl->p_bio, ssl->in_hdr, len, - timeout ); - else - ret = ssl->f_recv( ssl->p_bio, ssl->in_hdr, len ); - - MBEDTLS_SSL_DEBUG_RET( 2, "ssl->f_recv(_timeout)", ret ); - - if( ret == 0 ) - return( MBEDTLS_ERR_SSL_CONN_EOF ); - } - - if( ret == MBEDTLS_ERR_SSL_TIMEOUT ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "timeout" ) ); - ssl_set_timer( ssl, 0 ); - - if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER ) - { - if( ssl_double_retransmit_timeout( ssl ) != 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "handshake timeout" ) ); - return( MBEDTLS_ERR_SSL_TIMEOUT ); - } - - if( ( ret = mbedtls_ssl_resend( ssl ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_resend", ret ); - return( ret ); - } - - return( MBEDTLS_ERR_SSL_WANT_READ ); - } -#if defined(MBEDTLS_SSL_SRV_C) && defined(MBEDTLS_SSL_RENEGOTIATION) - else if( ssl->conf->endpoint == MBEDTLS_SSL_IS_SERVER && - ssl->renego_status == MBEDTLS_SSL_RENEGOTIATION_PENDING ) - { - if( ( ret = ssl_resend_hello_request( ssl ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "ssl_resend_hello_request", ret ); - return( ret ); - } - - return( MBEDTLS_ERR_SSL_WANT_READ ); - } -#endif /* MBEDTLS_SSL_SRV_C && MBEDTLS_SSL_RENEGOTIATION */ - } - - if( ret < 0 ) - return( ret ); - - ssl->in_left = ret; - } - else -#endif - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "in_left: %d, nb_want: %d", - ssl->in_left, nb_want ) ); - - while( ssl->in_left < nb_want ) - { - len = nb_want - ssl->in_left; - - if( ssl_check_timer( ssl ) != 0 ) - ret = MBEDTLS_ERR_SSL_TIMEOUT; - else - { - if( ssl->f_recv_timeout != NULL ) - { - ret = ssl->f_recv_timeout( ssl->p_bio, - ssl->in_hdr + ssl->in_left, len, - ssl->conf->read_timeout ); - } - else - { - ret = ssl->f_recv( ssl->p_bio, - ssl->in_hdr + ssl->in_left, len ); - } - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "in_left: %d, nb_want: %d", - ssl->in_left, nb_want ) ); - MBEDTLS_SSL_DEBUG_RET( 2, "ssl->f_recv(_timeout)", ret ); - - if( ret == 0 ) - return( MBEDTLS_ERR_SSL_CONN_EOF ); - - if( ret < 0 ) - return( ret ); - - if ( (size_t)ret > len || ( INT_MAX > SIZE_MAX && ret > SIZE_MAX ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, - ( "f_recv returned %d bytes but only %lu were requested", - ret, (unsigned long)len ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - ssl->in_left += ret; - } - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= fetch input" ) ); - - return( 0 ); -} - -/* - * Flush any data not yet written - */ -int mbedtls_ssl_flush_output( mbedtls_ssl_context *ssl ) -{ - int ret; - unsigned char *buf; - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> flush output" ) ); - - if( ssl->f_send == NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "Bad usage of mbedtls_ssl_set_bio() " - "or mbedtls_ssl_set_bio()" ) ); - return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - } - - /* Avoid incrementing counter if data is flushed */ - if( ssl->out_left == 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= flush output" ) ); - return( 0 ); - } - - while( ssl->out_left > 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "message length: %d, out_left: %d", - mbedtls_ssl_out_hdr_len( ssl ) + ssl->out_msglen, ssl->out_left ) ); - - buf = ssl->out_hdr - ssl->out_left; - ret = ssl->f_send( ssl->p_bio, buf, ssl->out_left ); - - MBEDTLS_SSL_DEBUG_RET( 2, "ssl->f_send", ret ); - - if( ret <= 0 ) - return( ret ); - - if( (size_t)ret > ssl->out_left || ( INT_MAX > SIZE_MAX && ret > SIZE_MAX ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, - ( "f_send returned %d bytes but only %lu bytes were sent", - ret, (unsigned long)ssl->out_left ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - ssl->out_left -= ret; - } - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - ssl->out_hdr = ssl->out_buf; - } - else -#endif - { - ssl->out_hdr = ssl->out_buf + 8; - } - ssl_update_out_pointers( ssl, ssl->transform_out ); - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= flush output" ) ); - - return( 0 ); -} - -/* - * Functions to handle the DTLS retransmission state machine - */ -#if defined(MBEDTLS_SSL_PROTO_DTLS) -/* - * Append current handshake message to current outgoing flight - */ -static int ssl_flight_append( mbedtls_ssl_context *ssl ) -{ - mbedtls_ssl_flight_item *msg; - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> ssl_flight_append" ) ); - MBEDTLS_SSL_DEBUG_BUF( 4, "message appended to flight", - ssl->out_msg, ssl->out_msglen ); - - /* Allocate space for current message */ - if( ( msg = mbedtls_calloc( 1, sizeof( mbedtls_ssl_flight_item ) ) ) == NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "alloc %d bytes failed", - sizeof( mbedtls_ssl_flight_item ) ) ); - return( MBEDTLS_ERR_SSL_ALLOC_FAILED ); - } - - if( ( msg->p = mbedtls_calloc( 1, ssl->out_msglen ) ) == NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "alloc %d bytes failed", ssl->out_msglen ) ); - mbedtls_free( msg ); - return( MBEDTLS_ERR_SSL_ALLOC_FAILED ); - } - - /* Copy current handshake message with headers */ - memcpy( msg->p, ssl->out_msg, ssl->out_msglen ); - msg->len = ssl->out_msglen; - msg->type = ssl->out_msgtype; - msg->next = NULL; - - /* Append to the current flight */ - if( ssl->handshake->flight == NULL ) - ssl->handshake->flight = msg; - else - { - mbedtls_ssl_flight_item *cur = ssl->handshake->flight; - while( cur->next != NULL ) - cur = cur->next; - cur->next = msg; - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= ssl_flight_append" ) ); - return( 0 ); -} - -/* - * Free the current flight of handshake messages - */ -static void ssl_flight_free( mbedtls_ssl_flight_item *flight ) -{ - mbedtls_ssl_flight_item *cur = flight; - mbedtls_ssl_flight_item *next; - - while( cur != NULL ) - { - next = cur->next; - - mbedtls_free( cur->p ); - mbedtls_free( cur ); - - cur = next; - } -} - -#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) -static void ssl_dtls_replay_reset( mbedtls_ssl_context *ssl ); -#endif - -/* - * Swap transform_out and out_ctr with the alternative ones - */ -static void ssl_swap_epochs( mbedtls_ssl_context *ssl ) -{ - mbedtls_ssl_transform *tmp_transform; - unsigned char tmp_out_ctr[8]; - - if( ssl->transform_out == ssl->handshake->alt_transform_out ) - { - MBEDTLS_SSL_DEBUG_MSG( 3, ( "skip swap epochs" ) ); - return; - } - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "swap epochs" ) ); - - /* Swap transforms */ - tmp_transform = ssl->transform_out; - ssl->transform_out = ssl->handshake->alt_transform_out; - ssl->handshake->alt_transform_out = tmp_transform; - - /* Swap epoch + sequence_number */ - memcpy( tmp_out_ctr, ssl->cur_out_ctr, 8 ); - memcpy( ssl->cur_out_ctr, ssl->handshake->alt_out_ctr, 8 ); - memcpy( ssl->handshake->alt_out_ctr, tmp_out_ctr, 8 ); - - /* Adjust to the newly activated transform */ - ssl_update_out_pointers( ssl, ssl->transform_out ); - -#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL) - if( mbedtls_ssl_hw_record_activate != NULL ) - { - if( ( ret = mbedtls_ssl_hw_record_activate( ssl, MBEDTLS_SSL_CHANNEL_OUTBOUND ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_hw_record_activate", ret ); - return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); - } - } -#endif -} - -/* - * Retransmit the current flight of messages. - */ -int mbedtls_ssl_resend( mbedtls_ssl_context *ssl ) -{ - int ret = 0; - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> mbedtls_ssl_resend" ) ); - - ret = mbedtls_ssl_flight_transmit( ssl ); - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= mbedtls_ssl_resend" ) ); - - return( ret ); -} - -/* - * Transmit or retransmit the current flight of messages. - * - * Need to remember the current message in case flush_output returns - * WANT_WRITE, causing us to exit this function and come back later. - * This function must be called until state is no longer SENDING. - */ -int mbedtls_ssl_flight_transmit( mbedtls_ssl_context *ssl ) -{ - int ret; - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> mbedtls_ssl_flight_transmit" ) ); - - if( ssl->handshake->retransmit_state != MBEDTLS_SSL_RETRANS_SENDING ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "initialise flight transmission" ) ); - - ssl->handshake->cur_msg = ssl->handshake->flight; - ssl->handshake->cur_msg_p = ssl->handshake->flight->p + 12; - ssl_swap_epochs( ssl ); - - ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_SENDING; - } - - while( ssl->handshake->cur_msg != NULL ) - { - size_t max_frag_len; - const mbedtls_ssl_flight_item * const cur = ssl->handshake->cur_msg; - - int const is_finished = - ( cur->type == MBEDTLS_SSL_MSG_HANDSHAKE && - cur->p[0] == MBEDTLS_SSL_HS_FINISHED ); - - uint8_t const force_flush = ssl->disable_datagram_packing == 1 ? - SSL_FORCE_FLUSH : SSL_DONT_FORCE_FLUSH; - - /* Swap epochs before sending Finished: we can't do it after - * sending ChangeCipherSpec, in case write returns WANT_READ. - * Must be done before copying, may change out_msg pointer */ - if( is_finished && ssl->handshake->cur_msg_p == ( cur->p + 12 ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "swap epochs to send finished message" ) ); - ssl_swap_epochs( ssl ); - } - - ret = ssl_get_remaining_payload_in_datagram( ssl ); - if( ret < 0 ) - return( ret ); - max_frag_len = (size_t) ret; - - /* CCS is copied as is, while HS messages may need fragmentation */ - if( cur->type == MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC ) - { - if( max_frag_len == 0 ) - { - if( ( ret = mbedtls_ssl_flush_output( ssl ) ) != 0 ) - return( ret ); - - continue; - } - - memcpy( ssl->out_msg, cur->p, cur->len ); - ssl->out_msglen = cur->len; - ssl->out_msgtype = cur->type; - - /* Update position inside current message */ - ssl->handshake->cur_msg_p += cur->len; - } - else - { - const unsigned char * const p = ssl->handshake->cur_msg_p; - const size_t hs_len = cur->len - 12; - const size_t frag_off = p - ( cur->p + 12 ); - const size_t rem_len = hs_len - frag_off; - size_t cur_hs_frag_len, max_hs_frag_len; - - if( ( max_frag_len < 12 ) || ( max_frag_len == 12 && hs_len != 0 ) ) - { - if( is_finished ) - ssl_swap_epochs( ssl ); - - if( ( ret = mbedtls_ssl_flush_output( ssl ) ) != 0 ) - return( ret ); - - continue; - } - max_hs_frag_len = max_frag_len - 12; - - cur_hs_frag_len = rem_len > max_hs_frag_len ? - max_hs_frag_len : rem_len; - - if( frag_off == 0 && cur_hs_frag_len != hs_len ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "fragmenting handshake message (%u > %u)", - (unsigned) cur_hs_frag_len, - (unsigned) max_hs_frag_len ) ); - } - - /* Messages are stored with handshake headers as if not fragmented, - * copy beginning of headers then fill fragmentation fields. - * Handshake headers: type(1) len(3) seq(2) f_off(3) f_len(3) */ - memcpy( ssl->out_msg, cur->p, 6 ); - - ssl->out_msg[6] = ( ( frag_off >> 16 ) & 0xff ); - ssl->out_msg[7] = ( ( frag_off >> 8 ) & 0xff ); - ssl->out_msg[8] = ( ( frag_off ) & 0xff ); - - ssl->out_msg[ 9] = ( ( cur_hs_frag_len >> 16 ) & 0xff ); - ssl->out_msg[10] = ( ( cur_hs_frag_len >> 8 ) & 0xff ); - ssl->out_msg[11] = ( ( cur_hs_frag_len ) & 0xff ); - - MBEDTLS_SSL_DEBUG_BUF( 3, "handshake header", ssl->out_msg, 12 ); - - /* Copy the handshake message content and set records fields */ - memcpy( ssl->out_msg + 12, p, cur_hs_frag_len ); - ssl->out_msglen = cur_hs_frag_len + 12; - ssl->out_msgtype = cur->type; - - /* Update position inside current message */ - ssl->handshake->cur_msg_p += cur_hs_frag_len; - } - - /* If done with the current message move to the next one if any */ - if( ssl->handshake->cur_msg_p >= cur->p + cur->len ) - { - if( cur->next != NULL ) - { - ssl->handshake->cur_msg = cur->next; - ssl->handshake->cur_msg_p = cur->next->p + 12; - } - else - { - ssl->handshake->cur_msg = NULL; - ssl->handshake->cur_msg_p = NULL; - } - } - - /* Actually send the message out */ - if( ( ret = mbedtls_ssl_write_record( ssl, force_flush ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_write_record", ret ); - return( ret ); - } - } - - if( ( ret = mbedtls_ssl_flush_output( ssl ) ) != 0 ) - return( ret ); - - /* Update state and set timer */ - if( ssl->state == MBEDTLS_SSL_HANDSHAKE_OVER ) - ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_FINISHED; - else - { - ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_WAITING; - ssl_set_timer( ssl, ssl->handshake->retransmit_timeout ); - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= mbedtls_ssl_flight_transmit" ) ); - - return( 0 ); -} - -/* - * To be called when the last message of an incoming flight is received. - */ -void mbedtls_ssl_recv_flight_completed( mbedtls_ssl_context *ssl ) -{ - /* We won't need to resend that one any more */ - ssl_flight_free( ssl->handshake->flight ); - ssl->handshake->flight = NULL; - ssl->handshake->cur_msg = NULL; - - /* The next incoming flight will start with this msg_seq */ - ssl->handshake->in_flight_start_seq = ssl->handshake->in_msg_seq; - - /* We don't want to remember CCS's across flight boundaries. */ - ssl->handshake->buffering.seen_ccs = 0; - - /* Clear future message buffering structure. */ - ssl_buffering_free( ssl ); - - /* Cancel timer */ - ssl_set_timer( ssl, 0 ); - - if( ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE && - ssl->in_msg[0] == MBEDTLS_SSL_HS_FINISHED ) - { - ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_FINISHED; - } - else - ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_PREPARING; -} - -/* - * To be called when the last message of an outgoing flight is send. - */ -void mbedtls_ssl_send_flight_completed( mbedtls_ssl_context *ssl ) -{ - ssl_reset_retransmit_timeout( ssl ); - ssl_set_timer( ssl, ssl->handshake->retransmit_timeout ); - - if( ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE && - ssl->in_msg[0] == MBEDTLS_SSL_HS_FINISHED ) - { - ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_FINISHED; - } - else - ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_WAITING; -} -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - -/* - * Handshake layer functions - */ - -/* - * Write (DTLS: or queue) current handshake (including CCS) message. - * - * - fill in handshake headers - * - update handshake checksum - * - DTLS: save message for resending - * - then pass to the record layer - * - * DTLS: except for HelloRequest, messages are only queued, and will only be - * actually sent when calling flight_transmit() or resend(). - * - * Inputs: - * - ssl->out_msglen: 4 + actual handshake message len - * (4 is the size of handshake headers for TLS) - * - ssl->out_msg[0]: the handshake type (ClientHello, ServerHello, etc) - * - ssl->out_msg + 4: the handshake message body - * - * Outputs, ie state before passing to flight_append() or write_record(): - * - ssl->out_msglen: the length of the record contents - * (including handshake headers but excluding record headers) - * - ssl->out_msg: the record contents (handshake headers + content) - */ -int mbedtls_ssl_write_handshake_msg( mbedtls_ssl_context *ssl ) -{ - int ret; - const size_t hs_len = ssl->out_msglen - 4; - const unsigned char hs_type = ssl->out_msg[0]; - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write handshake message" ) ); - - /* - * Sanity checks - */ - if( ssl->out_msgtype != MBEDTLS_SSL_MSG_HANDSHAKE && - ssl->out_msgtype != MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC ) - { - /* In SSLv3, the client might send a NoCertificate alert. */ -#if defined(MBEDTLS_SSL_PROTO_SSL3) && defined(MBEDTLS_SSL_CLI_C) - if( ! ( ssl->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 && - ssl->out_msgtype == MBEDTLS_SSL_MSG_ALERT && - ssl->conf->endpoint == MBEDTLS_SSL_IS_CLIENT ) ) -#endif /* MBEDTLS_SSL_PROTO_SSL3 && MBEDTLS_SSL_SRV_C */ - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - } - - /* Whenever we send anything different from a - * HelloRequest we should be in a handshake - double check. */ - if( ! ( ssl->out_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE && - hs_type == MBEDTLS_SSL_HS_HELLO_REQUEST ) && - ssl->handshake == NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && - ssl->handshake != NULL && - ssl->handshake->retransmit_state == MBEDTLS_SSL_RETRANS_SENDING ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } -#endif - - /* Double-check that we did not exceed the bounds - * of the outgoing record buffer. - * This should never fail as the various message - * writing functions must obey the bounds of the - * outgoing record buffer, but better be safe. - * - * Note: We deliberately do not check for the MTU or MFL here. - */ - if( ssl->out_msglen > MBEDTLS_SSL_OUT_CONTENT_LEN ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "Record too large: " - "size %u, maximum %u", - (unsigned) ssl->out_msglen, - (unsigned) MBEDTLS_SSL_OUT_CONTENT_LEN ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - /* - * Fill handshake headers - */ - if( ssl->out_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE ) - { - ssl->out_msg[1] = (unsigned char)( hs_len >> 16 ); - ssl->out_msg[2] = (unsigned char)( hs_len >> 8 ); - ssl->out_msg[3] = (unsigned char)( hs_len ); - - /* - * DTLS has additional fields in the Handshake layer, - * between the length field and the actual payload: - * uint16 message_seq; - * uint24 fragment_offset; - * uint24 fragment_length; - */ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - /* Make room for the additional DTLS fields */ - if( MBEDTLS_SSL_OUT_CONTENT_LEN - ssl->out_msglen < 8 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "DTLS handshake message too large: " - "size %u, maximum %u", - (unsigned) ( hs_len ), - (unsigned) ( MBEDTLS_SSL_OUT_CONTENT_LEN - 12 ) ) ); - return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - } - - memmove( ssl->out_msg + 12, ssl->out_msg + 4, hs_len ); - ssl->out_msglen += 8; - - /* Write message_seq and update it, except for HelloRequest */ - if( hs_type != MBEDTLS_SSL_HS_HELLO_REQUEST ) - { - ssl->out_msg[4] = ( ssl->handshake->out_msg_seq >> 8 ) & 0xFF; - ssl->out_msg[5] = ( ssl->handshake->out_msg_seq ) & 0xFF; - ++( ssl->handshake->out_msg_seq ); - } - else - { - ssl->out_msg[4] = 0; - ssl->out_msg[5] = 0; - } - - /* Handshake hashes are computed without fragmentation, - * so set frag_offset = 0 and frag_len = hs_len for now */ - memset( ssl->out_msg + 6, 0x00, 3 ); - memcpy( ssl->out_msg + 9, ssl->out_msg + 1, 3 ); - } -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - - /* Update running hashes of handshake messages seen */ - if( hs_type != MBEDTLS_SSL_HS_HELLO_REQUEST ) - ssl->handshake->update_checksum( ssl, ssl->out_msg, ssl->out_msglen ); - } - - /* Either send now, or just save to be sent (and resent) later */ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && - ! ( ssl->out_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE && - hs_type == MBEDTLS_SSL_HS_HELLO_REQUEST ) ) - { - if( ( ret = ssl_flight_append( ssl ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "ssl_flight_append", ret ); - return( ret ); - } - } - else -#endif - { - if( ( ret = mbedtls_ssl_write_record( ssl, SSL_FORCE_FLUSH ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "ssl_write_record", ret ); - return( ret ); - } - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= write handshake message" ) ); - - return( 0 ); -} - -/* - * Record layer functions - */ - -/* - * Write current record. - * - * Uses: - * - ssl->out_msgtype: type of the message (AppData, Handshake, Alert, CCS) - * - ssl->out_msglen: length of the record content (excl headers) - * - ssl->out_msg: record content - */ -int mbedtls_ssl_write_record( mbedtls_ssl_context *ssl, uint8_t force_flush ) -{ - int ret, done = 0; - size_t len = ssl->out_msglen; - uint8_t flush = force_flush; - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write record" ) ); - -#if defined(MBEDTLS_ZLIB_SUPPORT) - if( ssl->transform_out != NULL && - ssl->session_out->compression == MBEDTLS_SSL_COMPRESS_DEFLATE ) - { - if( ( ret = ssl_compress_buf( ssl ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "ssl_compress_buf", ret ); - return( ret ); - } - - len = ssl->out_msglen; - } -#endif /*MBEDTLS_ZLIB_SUPPORT */ - -#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL) - if( mbedtls_ssl_hw_record_write != NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "going for mbedtls_ssl_hw_record_write()" ) ); - - ret = mbedtls_ssl_hw_record_write( ssl ); - if( ret != 0 && ret != MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_hw_record_write", ret ); - return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); - } - - if( ret == 0 ) - done = 1; - } -#endif /* MBEDTLS_SSL_HW_RECORD_ACCEL */ - if( !done ) - { - unsigned i; - size_t protected_record_size; - - /* Skip writing the record content type to after the encryption, - * as it may change when using the CID extension. */ - - mbedtls_ssl_write_version( ssl->major_ver, ssl->minor_ver, - ssl->conf->transport, ssl->out_hdr + 1 ); - - memcpy( ssl->out_ctr, ssl->cur_out_ctr, 8 ); - ssl->out_len[0] = (unsigned char)( len >> 8 ); - ssl->out_len[1] = (unsigned char)( len ); - - if( ssl->transform_out != NULL ) - { - mbedtls_record rec; - - rec.buf = ssl->out_iv; - rec.buf_len = MBEDTLS_SSL_OUT_BUFFER_LEN - - ( ssl->out_iv - ssl->out_buf ); - rec.data_len = ssl->out_msglen; - rec.data_offset = ssl->out_msg - rec.buf; - - memcpy( &rec.ctr[0], ssl->out_ctr, 8 ); - mbedtls_ssl_write_version( ssl->major_ver, ssl->minor_ver, - ssl->conf->transport, rec.ver ); - rec.type = ssl->out_msgtype; - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - /* The CID is set by mbedtls_ssl_encrypt_buf(). */ - rec.cid_len = 0; -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - - if( ( ret = mbedtls_ssl_encrypt_buf( ssl, ssl->transform_out, &rec, - ssl->conf->f_rng, ssl->conf->p_rng ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "ssl_encrypt_buf", ret ); - return( ret ); - } - - if( rec.data_offset != 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - /* Update the record content type and CID. */ - ssl->out_msgtype = rec.type; -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID ) - memcpy( ssl->out_cid, rec.cid, rec.cid_len ); -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - ssl->out_msglen = len = rec.data_len; - ssl->out_len[0] = (unsigned char)( rec.data_len >> 8 ); - ssl->out_len[1] = (unsigned char)( rec.data_len ); - } - - protected_record_size = len + mbedtls_ssl_out_hdr_len( ssl ); - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - /* In case of DTLS, double-check that we don't exceed - * the remaining space in the datagram. */ - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - ret = ssl_get_remaining_space_in_datagram( ssl ); - if( ret < 0 ) - return( ret ); - - if( protected_record_size > (size_t) ret ) - { - /* Should never happen */ - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - } -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - - /* Now write the potentially updated record content type. */ - ssl->out_hdr[0] = (unsigned char) ssl->out_msgtype; - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "output record: msgtype = %d, " - "version = [%d:%d], msglen = %d", - ssl->out_hdr[0], ssl->out_hdr[1], - ssl->out_hdr[2], len ) ); - - MBEDTLS_SSL_DEBUG_BUF( 4, "output record sent to network", - ssl->out_hdr, protected_record_size ); - - ssl->out_left += protected_record_size; - ssl->out_hdr += protected_record_size; - ssl_update_out_pointers( ssl, ssl->transform_out ); - - for( i = 8; i > ssl_ep_len( ssl ); i-- ) - if( ++ssl->cur_out_ctr[i - 1] != 0 ) - break; - - /* The loop goes to its end iff the counter is wrapping */ - if( i == ssl_ep_len( ssl ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "outgoing message counter would wrap" ) ); - return( MBEDTLS_ERR_SSL_COUNTER_WRAPPING ); - } - } - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && - flush == SSL_DONT_FORCE_FLUSH ) - { - size_t remaining; - ret = ssl_get_remaining_payload_in_datagram( ssl ); - if( ret < 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "ssl_get_remaining_payload_in_datagram", - ret ); - return( ret ); - } - - remaining = (size_t) ret; - if( remaining == 0 ) - { - flush = SSL_FORCE_FLUSH; - } - else - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Still %u bytes available in current datagram", (unsigned) remaining ) ); - } - } -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - - if( ( flush == SSL_FORCE_FLUSH ) && - ( ret = mbedtls_ssl_flush_output( ssl ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_flush_output", ret ); - return( ret ); - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= write record" ) ); - - return( 0 ); -} - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - -static int ssl_hs_is_proper_fragment( mbedtls_ssl_context *ssl ) -{ - if( ssl->in_msglen < ssl->in_hslen || - memcmp( ssl->in_msg + 6, "\0\0\0", 3 ) != 0 || - memcmp( ssl->in_msg + 9, ssl->in_msg + 1, 3 ) != 0 ) - { - return( 1 ); - } - return( 0 ); -} - -static uint32_t ssl_get_hs_frag_len( mbedtls_ssl_context const *ssl ) -{ - return( ( ssl->in_msg[9] << 16 ) | - ( ssl->in_msg[10] << 8 ) | - ssl->in_msg[11] ); -} - -static uint32_t ssl_get_hs_frag_off( mbedtls_ssl_context const *ssl ) -{ - return( ( ssl->in_msg[6] << 16 ) | - ( ssl->in_msg[7] << 8 ) | - ssl->in_msg[8] ); -} - -static int ssl_check_hs_header( mbedtls_ssl_context const *ssl ) -{ - uint32_t msg_len, frag_off, frag_len; - - msg_len = ssl_get_hs_total_len( ssl ); - frag_off = ssl_get_hs_frag_off( ssl ); - frag_len = ssl_get_hs_frag_len( ssl ); - - if( frag_off > msg_len ) - return( -1 ); - - if( frag_len > msg_len - frag_off ) - return( -1 ); - - if( frag_len + 12 > ssl->in_msglen ) - return( -1 ); - - return( 0 ); -} - -/* - * Mark bits in bitmask (used for DTLS HS reassembly) - */ -static void ssl_bitmask_set( unsigned char *mask, size_t offset, size_t len ) -{ - unsigned int start_bits, end_bits; - - start_bits = 8 - ( offset % 8 ); - if( start_bits != 8 ) - { - size_t first_byte_idx = offset / 8; - - /* Special case */ - if( len <= start_bits ) - { - for( ; len != 0; len-- ) - mask[first_byte_idx] |= 1 << ( start_bits - len ); - - /* Avoid potential issues with offset or len becoming invalid */ - return; - } - - offset += start_bits; /* Now offset % 8 == 0 */ - len -= start_bits; - - for( ; start_bits != 0; start_bits-- ) - mask[first_byte_idx] |= 1 << ( start_bits - 1 ); - } - - end_bits = len % 8; - if( end_bits != 0 ) - { - size_t last_byte_idx = ( offset + len ) / 8; - - len -= end_bits; /* Now len % 8 == 0 */ - - for( ; end_bits != 0; end_bits-- ) - mask[last_byte_idx] |= 1 << ( 8 - end_bits ); - } - - memset( mask + offset / 8, 0xFF, len / 8 ); -} - -/* - * Check that bitmask is full - */ -static int ssl_bitmask_check( unsigned char *mask, size_t len ) -{ - size_t i; - - for( i = 0; i < len / 8; i++ ) - if( mask[i] != 0xFF ) - return( -1 ); - - for( i = 0; i < len % 8; i++ ) - if( ( mask[len / 8] & ( 1 << ( 7 - i ) ) ) == 0 ) - return( -1 ); - - return( 0 ); -} - -/* msg_len does not include the handshake header */ -static size_t ssl_get_reassembly_buffer_size( size_t msg_len, - unsigned add_bitmap ) -{ - size_t alloc_len; - - alloc_len = 12; /* Handshake header */ - alloc_len += msg_len; /* Content buffer */ - - if( add_bitmap ) - alloc_len += msg_len / 8 + ( msg_len % 8 != 0 ); /* Bitmap */ - - return( alloc_len ); -} - -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - -static uint32_t ssl_get_hs_total_len( mbedtls_ssl_context const *ssl ) -{ - return( ( ssl->in_msg[1] << 16 ) | - ( ssl->in_msg[2] << 8 ) | - ssl->in_msg[3] ); -} - -int mbedtls_ssl_prepare_handshake_record( mbedtls_ssl_context *ssl ) -{ - if( ssl->in_msglen < mbedtls_ssl_hs_hdr_len( ssl ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "handshake message too short: %d", - ssl->in_msglen ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } - - ssl->in_hslen = mbedtls_ssl_hs_hdr_len( ssl ) + ssl_get_hs_total_len( ssl ); - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "handshake message: msglen =" - " %d, type = %d, hslen = %d", - ssl->in_msglen, ssl->in_msg[0], ssl->in_hslen ) ); - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - int ret; - unsigned int recv_msg_seq = ( ssl->in_msg[4] << 8 ) | ssl->in_msg[5]; - - if( ssl_check_hs_header( ssl ) != 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "invalid handshake header" ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } - - if( ssl->handshake != NULL && - ( ( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER && - recv_msg_seq != ssl->handshake->in_msg_seq ) || - ( ssl->state == MBEDTLS_SSL_HANDSHAKE_OVER && - ssl->in_msg[0] != MBEDTLS_SSL_HS_CLIENT_HELLO ) ) ) - { - if( recv_msg_seq > ssl->handshake->in_msg_seq ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "received future handshake message of sequence number %u (next %u)", - recv_msg_seq, - ssl->handshake->in_msg_seq ) ); - return( MBEDTLS_ERR_SSL_EARLY_MESSAGE ); - } - - /* Retransmit only on last message from previous flight, to avoid - * too many retransmissions. - * Besides, No sane server ever retransmits HelloVerifyRequest */ - if( recv_msg_seq == ssl->handshake->in_flight_start_seq - 1 && - ssl->in_msg[0] != MBEDTLS_SSL_HS_HELLO_VERIFY_REQUEST ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "received message from last flight, " - "message_seq = %d, start_of_flight = %d", - recv_msg_seq, - ssl->handshake->in_flight_start_seq ) ); - - if( ( ret = mbedtls_ssl_resend( ssl ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_resend", ret ); - return( ret ); - } - } - else - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "dropping out-of-sequence message: " - "message_seq = %d, expected = %d", - recv_msg_seq, - ssl->handshake->in_msg_seq ) ); - } - - return( MBEDTLS_ERR_SSL_CONTINUE_PROCESSING ); - } - /* Wait until message completion to increment in_msg_seq */ - - /* Message reassembly is handled alongside buffering of future - * messages; the commonality is that both handshake fragments and - * future messages cannot be forwarded immediately to the - * handshake logic layer. */ - if( ssl_hs_is_proper_fragment( ssl ) == 1 ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "found fragmented DTLS handshake message" ) ); - return( MBEDTLS_ERR_SSL_EARLY_MESSAGE ); - } - } - else -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - /* With TLS we don't handle fragmentation (for now) */ - if( ssl->in_msglen < ssl->in_hslen ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "TLS handshake fragmentation not supported" ) ); - return( MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE ); - } - - return( 0 ); -} - -void mbedtls_ssl_update_handshake_status( mbedtls_ssl_context *ssl ) -{ - mbedtls_ssl_handshake_params * const hs = ssl->handshake; - - if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER && hs != NULL ) - { - ssl->handshake->update_checksum( ssl, ssl->in_msg, ssl->in_hslen ); - } - - /* Handshake message is complete, increment counter */ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && - ssl->handshake != NULL ) - { - unsigned offset; - mbedtls_ssl_hs_buffer *hs_buf; - - /* Increment handshake sequence number */ - hs->in_msg_seq++; - - /* - * Clear up handshake buffering and reassembly structure. - */ - - /* Free first entry */ - ssl_buffering_free_slot( ssl, 0 ); - - /* Shift all other entries */ - for( offset = 0, hs_buf = &hs->buffering.hs[0]; - offset + 1 < MBEDTLS_SSL_MAX_BUFFERED_HS; - offset++, hs_buf++ ) - { - *hs_buf = *(hs_buf + 1); - } - - /* Create a fresh last entry */ - memset( hs_buf, 0, sizeof( mbedtls_ssl_hs_buffer ) ); - } -#endif -} - -/* - * DTLS anti-replay: RFC 6347 4.1.2.6 - * - * in_window is a field of bits numbered from 0 (lsb) to 63 (msb). - * Bit n is set iff record number in_window_top - n has been seen. - * - * Usually, in_window_top is the last record number seen and the lsb of - * in_window is set. The only exception is the initial state (record number 0 - * not seen yet). - */ -#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) -static void ssl_dtls_replay_reset( mbedtls_ssl_context *ssl ) -{ - ssl->in_window_top = 0; - ssl->in_window = 0; -} - -static inline uint64_t ssl_load_six_bytes( unsigned char *buf ) -{ - return( ( (uint64_t) buf[0] << 40 ) | - ( (uint64_t) buf[1] << 32 ) | - ( (uint64_t) buf[2] << 24 ) | - ( (uint64_t) buf[3] << 16 ) | - ( (uint64_t) buf[4] << 8 ) | - ( (uint64_t) buf[5] ) ); -} - -/* - * Return 0 if sequence number is acceptable, -1 otherwise - */ -int mbedtls_ssl_dtls_replay_check( mbedtls_ssl_context const *ssl ) -{ - uint64_t rec_seqnum = ssl_load_six_bytes( ssl->in_ctr + 2 ); - uint64_t bit; - - if( ssl->conf->anti_replay == MBEDTLS_SSL_ANTI_REPLAY_DISABLED ) - return( 0 ); - - if( rec_seqnum > ssl->in_window_top ) - return( 0 ); - - bit = ssl->in_window_top - rec_seqnum; - - if( bit >= 64 ) - return( -1 ); - - if( ( ssl->in_window & ( (uint64_t) 1 << bit ) ) != 0 ) - return( -1 ); - - return( 0 ); -} - -/* - * Update replay window on new validated record - */ -void mbedtls_ssl_dtls_replay_update( mbedtls_ssl_context *ssl ) -{ - uint64_t rec_seqnum = ssl_load_six_bytes( ssl->in_ctr + 2 ); - - if( ssl->conf->anti_replay == MBEDTLS_SSL_ANTI_REPLAY_DISABLED ) - return; - - if( rec_seqnum > ssl->in_window_top ) - { - /* Update window_top and the contents of the window */ - uint64_t shift = rec_seqnum - ssl->in_window_top; - - if( shift >= 64 ) - ssl->in_window = 1; - else - { - ssl->in_window <<= shift; - ssl->in_window |= 1; - } - - ssl->in_window_top = rec_seqnum; - } - else - { - /* Mark that number as seen in the current window */ - uint64_t bit = ssl->in_window_top - rec_seqnum; - - if( bit < 64 ) /* Always true, but be extra sure */ - ssl->in_window |= (uint64_t) 1 << bit; - } -} -#endif /* MBEDTLS_SSL_DTLS_ANTI_REPLAY */ - -#if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) && defined(MBEDTLS_SSL_SRV_C) -/* Forward declaration */ -static int ssl_session_reset_int( mbedtls_ssl_context *ssl, int partial ); - -/* - * Without any SSL context, check if a datagram looks like a ClientHello with - * a valid cookie, and if it doesn't, generate a HelloVerifyRequest message. - * Both input and output include full DTLS headers. - * - * - if cookie is valid, return 0 - * - if ClientHello looks superficially valid but cookie is not, - * fill obuf and set olen, then - * return MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED - * - otherwise return a specific error code - */ -static int ssl_check_dtls_clihlo_cookie( - mbedtls_ssl_cookie_write_t *f_cookie_write, - mbedtls_ssl_cookie_check_t *f_cookie_check, - void *p_cookie, - const unsigned char *cli_id, size_t cli_id_len, - const unsigned char *in, size_t in_len, - unsigned char *obuf, size_t buf_len, size_t *olen ) -{ - size_t sid_len, cookie_len; - unsigned char *p; - - /* - * Structure of ClientHello with record and handshake headers, - * and expected values. We don't need to check a lot, more checks will be - * done when actually parsing the ClientHello - skipping those checks - * avoids code duplication and does not make cookie forging any easier. - * - * 0-0 ContentType type; copied, must be handshake - * 1-2 ProtocolVersion version; copied - * 3-4 uint16 epoch; copied, must be 0 - * 5-10 uint48 sequence_number; copied - * 11-12 uint16 length; (ignored) - * - * 13-13 HandshakeType msg_type; (ignored) - * 14-16 uint24 length; (ignored) - * 17-18 uint16 message_seq; copied - * 19-21 uint24 fragment_offset; copied, must be 0 - * 22-24 uint24 fragment_length; (ignored) - * - * 25-26 ProtocolVersion client_version; (ignored) - * 27-58 Random random; (ignored) - * 59-xx SessionID session_id; 1 byte len + sid_len content - * 60+ opaque cookie<0..2^8-1>; 1 byte len + content - * ... - * - * Minimum length is 61 bytes. - */ - if( in_len < 61 || - in[0] != MBEDTLS_SSL_MSG_HANDSHAKE || - in[3] != 0 || in[4] != 0 || - in[19] != 0 || in[20] != 0 || in[21] != 0 ) - { - return( MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO ); - } - - sid_len = in[59]; - if( sid_len > in_len - 61 ) - return( MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO ); - - cookie_len = in[60 + sid_len]; - if( cookie_len > in_len - 60 ) - return( MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO ); - - if( f_cookie_check( p_cookie, in + sid_len + 61, cookie_len, - cli_id, cli_id_len ) == 0 ) - { - /* Valid cookie */ - return( 0 ); - } - - /* - * If we get here, we've got an invalid cookie, let's prepare HVR. - * - * 0-0 ContentType type; copied - * 1-2 ProtocolVersion version; copied - * 3-4 uint16 epoch; copied - * 5-10 uint48 sequence_number; copied - * 11-12 uint16 length; olen - 13 - * - * 13-13 HandshakeType msg_type; hello_verify_request - * 14-16 uint24 length; olen - 25 - * 17-18 uint16 message_seq; copied - * 19-21 uint24 fragment_offset; copied - * 22-24 uint24 fragment_length; olen - 25 - * - * 25-26 ProtocolVersion server_version; 0xfe 0xff - * 27-27 opaque cookie<0..2^8-1>; cookie_len = olen - 27, cookie - * - * Minimum length is 28. - */ - if( buf_len < 28 ) - return( MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL ); - - /* Copy most fields and adapt others */ - memcpy( obuf, in, 25 ); - obuf[13] = MBEDTLS_SSL_HS_HELLO_VERIFY_REQUEST; - obuf[25] = 0xfe; - obuf[26] = 0xff; - - /* Generate and write actual cookie */ - p = obuf + 28; - if( f_cookie_write( p_cookie, - &p, obuf + buf_len, cli_id, cli_id_len ) != 0 ) - { - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - *olen = p - obuf; - - /* Go back and fill length fields */ - obuf[27] = (unsigned char)( *olen - 28 ); - - obuf[14] = obuf[22] = (unsigned char)( ( *olen - 25 ) >> 16 ); - obuf[15] = obuf[23] = (unsigned char)( ( *olen - 25 ) >> 8 ); - obuf[16] = obuf[24] = (unsigned char)( ( *olen - 25 ) ); - - obuf[11] = (unsigned char)( ( *olen - 13 ) >> 8 ); - obuf[12] = (unsigned char)( ( *olen - 13 ) ); - - return( MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED ); -} - -/* - * Handle possible client reconnect with the same UDP quadruplet - * (RFC 6347 Section 4.2.8). - * - * Called by ssl_parse_record_header() in case we receive an epoch 0 record - * that looks like a ClientHello. - * - * - if the input looks like a ClientHello without cookies, - * send back HelloVerifyRequest, then - * return MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED - * - if the input looks like a ClientHello with a valid cookie, - * reset the session of the current context, and - * return MBEDTLS_ERR_SSL_CLIENT_RECONNECT - * - if anything goes wrong, return a specific error code - * - * mbedtls_ssl_read_record() will ignore the record if anything else than - * MBEDTLS_ERR_SSL_CLIENT_RECONNECT or 0 is returned, although this function - * cannot not return 0. - */ -static int ssl_handle_possible_reconnect( mbedtls_ssl_context *ssl ) -{ - int ret; - size_t len; - - if( ssl->conf->f_cookie_write == NULL || - ssl->conf->f_cookie_check == NULL ) - { - /* If we can't use cookies to verify reachability of the peer, - * drop the record. */ - return( 0 ); - } - - ret = ssl_check_dtls_clihlo_cookie( - ssl->conf->f_cookie_write, - ssl->conf->f_cookie_check, - ssl->conf->p_cookie, - ssl->cli_id, ssl->cli_id_len, - ssl->in_buf, ssl->in_left, - ssl->out_buf, MBEDTLS_SSL_OUT_CONTENT_LEN, &len ); - - MBEDTLS_SSL_DEBUG_RET( 2, "ssl_check_dtls_clihlo_cookie", ret ); - - if( ret == MBEDTLS_ERR_SSL_HELLO_VERIFY_REQUIRED ) - { - /* Don't check write errors as we can't do anything here. - * If the error is permanent we'll catch it later, - * if it's not, then hopefully it'll work next time. */ - (void) ssl->f_send( ssl->p_bio, ssl->out_buf, len ); - ret = 0; - } - - if( ret == 0 ) - { - /* Got a valid cookie, partially reset context */ - if( ( ret = ssl_session_reset_int( ssl, 1 ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "reset", ret ); - return( ret ); - } - - return( MBEDTLS_ERR_SSL_CLIENT_RECONNECT ); - } - - return( ret ); -} -#endif /* MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE && MBEDTLS_SSL_SRV_C */ - -static int ssl_check_record_type( uint8_t record_type ) -{ - if( record_type != MBEDTLS_SSL_MSG_HANDSHAKE && - record_type != MBEDTLS_SSL_MSG_ALERT && - record_type != MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC && - record_type != MBEDTLS_SSL_MSG_APPLICATION_DATA ) - { - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } - - return( 0 ); -} - -/* - * ContentType type; - * ProtocolVersion version; - * uint16 epoch; // DTLS only - * uint48 sequence_number; // DTLS only - * uint16 length; - * - * Return 0 if header looks sane (and, for DTLS, the record is expected) - * MBEDTLS_ERR_SSL_INVALID_RECORD if the header looks bad, - * MBEDTLS_ERR_SSL_UNEXPECTED_RECORD (DTLS only) if sane but unexpected. - * - * With DTLS, mbedtls_ssl_read_record() will: - * 1. proceed with the record if this function returns 0 - * 2. drop only the current record if this function returns UNEXPECTED_RECORD - * 3. return CLIENT_RECONNECT if this function return that value - * 4. drop the whole datagram if this function returns anything else. - * Point 2 is needed when the peer is resending, and we have already received - * the first record from a datagram but are still waiting for the others. - */ -static int ssl_parse_record_header( mbedtls_ssl_context const *ssl, - unsigned char *buf, - size_t len, - mbedtls_record *rec ) -{ - int major_ver, minor_ver; - - size_t const rec_hdr_type_offset = 0; - size_t const rec_hdr_type_len = 1; - - size_t const rec_hdr_version_offset = rec_hdr_type_offset + - rec_hdr_type_len; - size_t const rec_hdr_version_len = 2; - - size_t const rec_hdr_ctr_len = 8; -#if defined(MBEDTLS_SSL_PROTO_DTLS) - uint32_t rec_epoch; - size_t const rec_hdr_ctr_offset = rec_hdr_version_offset + - rec_hdr_version_len; - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - size_t const rec_hdr_cid_offset = rec_hdr_ctr_offset + - rec_hdr_ctr_len; - size_t rec_hdr_cid_len = 0; -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - - size_t rec_hdr_len_offset; /* To be determined */ - size_t const rec_hdr_len_len = 2; - - /* - * Check minimum lengths for record header. - */ - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - rec_hdr_len_offset = rec_hdr_ctr_offset + rec_hdr_ctr_len; - } - else -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - { - rec_hdr_len_offset = rec_hdr_version_offset + rec_hdr_version_len; - } - - if( len < rec_hdr_len_offset + rec_hdr_len_len ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "datagram of length %u too small to hold DTLS record header of length %u", - (unsigned) len, - (unsigned)( rec_hdr_len_len + rec_hdr_len_len ) ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } - - /* - * Parse and validate record content type - */ - - rec->type = buf[ rec_hdr_type_offset ]; - - /* Check record content type */ -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - rec->cid_len = 0; - - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && - ssl->conf->cid_len != 0 && - rec->type == MBEDTLS_SSL_MSG_CID ) - { - /* Shift pointers to account for record header including CID - * struct { - * ContentType special_type = tls12_cid; - * ProtocolVersion version; - * uint16 epoch; - * uint48 sequence_number; - * opaque cid[cid_length]; // Additional field compared to - * // default DTLS record format - * uint16 length; - * opaque enc_content[DTLSCiphertext.length]; - * } DTLSCiphertext; - */ - - /* So far, we only support static CID lengths - * fixed in the configuration. */ - rec_hdr_cid_len = ssl->conf->cid_len; - rec_hdr_len_offset += rec_hdr_cid_len; - - if( len < rec_hdr_len_offset + rec_hdr_len_len ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "datagram of length %u too small to hold DTLS record header including CID, length %u", - (unsigned) len, - (unsigned)( rec_hdr_len_offset + rec_hdr_len_len ) ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } - - /* configured CID len is guaranteed at most 255, see - * MBEDTLS_SSL_CID_OUT_LEN_MAX in check_config.h */ - rec->cid_len = (uint8_t) rec_hdr_cid_len; - memcpy( rec->cid, buf + rec_hdr_cid_offset, rec_hdr_cid_len ); - } - else -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - { - if( ssl_check_record_type( rec->type ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "unknown record type %u", - (unsigned) rec->type ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } - } - - /* - * Parse and validate record version - */ - - rec->ver[0] = buf[ rec_hdr_version_offset + 0 ]; - rec->ver[1] = buf[ rec_hdr_version_offset + 1 ]; - mbedtls_ssl_read_version( &major_ver, &minor_ver, - ssl->conf->transport, - &rec->ver[0] ); - - if( major_ver != ssl->major_ver ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "major version mismatch" ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } - - if( minor_ver > ssl->conf->max_minor_ver ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "minor version mismatch" ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } - - /* - * Parse/Copy record sequence number. - */ - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - /* Copy explicit record sequence number from input buffer. */ - memcpy( &rec->ctr[0], buf + rec_hdr_ctr_offset, - rec_hdr_ctr_len ); - } - else -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - { - /* Copy implicit record sequence number from SSL context structure. */ - memcpy( &rec->ctr[0], ssl->in_ctr, rec_hdr_ctr_len ); - } - - /* - * Parse record length. - */ - - rec->data_offset = rec_hdr_len_offset + rec_hdr_len_len; - rec->data_len = ( (size_t) buf[ rec_hdr_len_offset + 0 ] << 8 ) | - ( (size_t) buf[ rec_hdr_len_offset + 1 ] << 0 ); - MBEDTLS_SSL_DEBUG_BUF( 4, "input record header", buf, rec->data_offset ); - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "input record: msgtype = %d, " - "version = [%d:%d], msglen = %d", - rec->type, - major_ver, minor_ver, rec->data_len ) ); - - rec->buf = buf; - rec->buf_len = rec->data_offset + rec->data_len; - - if( rec->data_len == 0 ) - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - - /* - * DTLS-related tests. - * Check epoch before checking length constraint because - * the latter varies with the epoch. E.g., if a ChangeCipherSpec - * message gets duplicated before the corresponding Finished message, - * the second ChangeCipherSpec should be discarded because it belongs - * to an old epoch, but not because its length is shorter than - * the minimum record length for packets using the new record transform. - * Note that these two kinds of failures are handled differently, - * as an unexpected record is silently skipped but an invalid - * record leads to the entire datagram being dropped. - */ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - rec_epoch = ( rec->ctr[0] << 8 ) | rec->ctr[1]; - - /* Check that the datagram is large enough to contain a record - * of the advertised length. */ - if( len < rec->data_offset + rec->data_len ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "Datagram of length %u too small to contain record of advertised length %u.", - (unsigned) len, - (unsigned)( rec->data_offset + rec->data_len ) ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } - - /* Records from other, non-matching epochs are silently discarded. - * (The case of same-port Client reconnects must be considered in - * the caller). */ - if( rec_epoch != ssl->in_epoch ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "record from another epoch: " - "expected %d, received %d", - ssl->in_epoch, rec_epoch ) ); - - /* Records from the next epoch are considered for buffering - * (concretely: early Finished messages). */ - if( rec_epoch == (unsigned) ssl->in_epoch + 1 ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Consider record for buffering" ) ); - return( MBEDTLS_ERR_SSL_EARLY_MESSAGE ); - } - - return( MBEDTLS_ERR_SSL_UNEXPECTED_RECORD ); - } -#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) - /* For records from the correct epoch, check whether their - * sequence number has been seen before. */ - else if( mbedtls_ssl_dtls_replay_check( ssl ) != 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "replayed record" ) ); - return( MBEDTLS_ERR_SSL_UNEXPECTED_RECORD ); - } -#endif - } -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - - return( 0 ); -} - - -#if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) && defined(MBEDTLS_SSL_SRV_C) -static int ssl_check_client_reconnect( mbedtls_ssl_context *ssl ) -{ - unsigned int rec_epoch = ( ssl->in_ctr[0] << 8 ) | ssl->in_ctr[1]; - - /* - * Check for an epoch 0 ClientHello. We can't use in_msg here to - * access the first byte of record content (handshake type), as we - * have an active transform (possibly iv_len != 0), so use the - * fact that the record header len is 13 instead. - */ - if( rec_epoch == 0 && - ssl->conf->endpoint == MBEDTLS_SSL_IS_SERVER && - ssl->state == MBEDTLS_SSL_HANDSHAKE_OVER && - ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE && - ssl->in_left > 13 && - ssl->in_buf[13] == MBEDTLS_SSL_HS_CLIENT_HELLO ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "possible client reconnect " - "from the same port" ) ); - return( ssl_handle_possible_reconnect( ssl ) ); - } - - return( 0 ); -} -#endif /* MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE && MBEDTLS_SSL_SRV_C */ - -/* - * If applicable, decrypt (and decompress) record content - */ -static int ssl_prepare_record_content( mbedtls_ssl_context *ssl, - mbedtls_record *rec ) -{ - int ret, done = 0; - - MBEDTLS_SSL_DEBUG_BUF( 4, "input record from network", - rec->buf, rec->buf_len ); - -#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL) - if( mbedtls_ssl_hw_record_read != NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "going for mbedtls_ssl_hw_record_read()" ) ); - - ret = mbedtls_ssl_hw_record_read( ssl ); - if( ret != 0 && ret != MBEDTLS_ERR_SSL_HW_ACCEL_FALLTHROUGH ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_hw_record_read", ret ); - return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); - } - - if( ret == 0 ) - done = 1; - } -#endif /* MBEDTLS_SSL_HW_RECORD_ACCEL */ - if( !done && ssl->transform_in != NULL ) - { - unsigned char const old_msg_type = rec->type; - - if( ( ret = mbedtls_ssl_decrypt_buf( ssl, ssl->transform_in, - rec ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "ssl_decrypt_buf", ret ); - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - if( ret == MBEDTLS_ERR_SSL_UNEXPECTED_CID && - ssl->conf->ignore_unexpected_cid - == MBEDTLS_SSL_UNEXPECTED_CID_IGNORE ) - { - MBEDTLS_SSL_DEBUG_MSG( 3, ( "ignoring unexpected CID" ) ); - ret = MBEDTLS_ERR_SSL_CONTINUE_PROCESSING; - } -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - - return( ret ); - } - - if( old_msg_type != rec->type ) - { - MBEDTLS_SSL_DEBUG_MSG( 4, ( "record type after decrypt (before %d): %d", - old_msg_type, rec->type ) ); - } - - MBEDTLS_SSL_DEBUG_BUF( 4, "input payload after decrypt", - rec->buf + rec->data_offset, rec->data_len ); - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - /* We have already checked the record content type - * in ssl_parse_record_header(), failing or silently - * dropping the record in the case of an unknown type. - * - * Since with the use of CIDs, the record content type - * might change during decryption, re-check the record - * content type, but treat a failure as fatal this time. */ - if( ssl_check_record_type( rec->type ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "unknown record type" ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - - if( rec->data_len == 0 ) - { -#if defined(MBEDTLS_SSL_PROTO_TLS1_2) - if( ssl->minor_ver == MBEDTLS_SSL_MINOR_VERSION_3 - && rec->type != MBEDTLS_SSL_MSG_APPLICATION_DATA ) - { - /* TLS v1.2 explicitly disallows zero-length messages which are not application data */ - MBEDTLS_SSL_DEBUG_MSG( 1, ( "invalid zero-length message type: %d", ssl->in_msgtype ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } -#endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ - - ssl->nb_zero++; - - /* - * Three or more empty messages may be a DoS attack - * (excessive CPU consumption). - */ - if( ssl->nb_zero > 3 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "received four consecutive empty " - "messages, possible DoS attack" ) ); - /* Treat the records as if they were not properly authenticated, - * thereby failing the connection if we see more than allowed - * by the configured bad MAC threshold. */ - return( MBEDTLS_ERR_SSL_INVALID_MAC ); - } - } - else - ssl->nb_zero = 0; - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - ; /* in_ctr read from peer, not maintained internally */ - } - else -#endif - { - unsigned i; - for( i = 8; i > ssl_ep_len( ssl ); i-- ) - if( ++ssl->in_ctr[i - 1] != 0 ) - break; - - /* The loop goes to its end iff the counter is wrapping */ - if( i == ssl_ep_len( ssl ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "incoming message counter would wrap" ) ); - return( MBEDTLS_ERR_SSL_COUNTER_WRAPPING ); - } - } - - } - -#if defined(MBEDTLS_ZLIB_SUPPORT) - if( ssl->transform_in != NULL && - ssl->session_in->compression == MBEDTLS_SSL_COMPRESS_DEFLATE ) - { - if( ( ret = ssl_decompress_buf( ssl ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "ssl_decompress_buf", ret ); - return( ret ); - } - } -#endif /* MBEDTLS_ZLIB_SUPPORT */ - -#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - mbedtls_ssl_dtls_replay_update( ssl ); - } -#endif - - /* Check actual (decrypted) record content length against - * configured maximum. */ - if( ssl->in_msglen > MBEDTLS_SSL_IN_CONTENT_LEN ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad message length" ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } - - return( 0 ); -} - -static void ssl_handshake_wrapup_free_hs_transform( mbedtls_ssl_context *ssl ); - -/* - * Read a record. - * - * Silently ignore non-fatal alert (and for DTLS, invalid records as well, - * RFC 6347 4.1.2.7) and continue reading until a valid record is found. - * - */ - -/* Helper functions for mbedtls_ssl_read_record(). */ -static int ssl_consume_current_message( mbedtls_ssl_context *ssl ); -static int ssl_get_next_record( mbedtls_ssl_context *ssl ); -static int ssl_record_is_in_progress( mbedtls_ssl_context *ssl ); - -int mbedtls_ssl_read_record( mbedtls_ssl_context *ssl, - unsigned update_hs_digest ) -{ - int ret; - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> read record" ) ); - - if( ssl->keep_current_message == 0 ) - { - do { - - ret = ssl_consume_current_message( ssl ); - if( ret != 0 ) - return( ret ); - - if( ssl_record_is_in_progress( ssl ) == 0 ) - { -#if defined(MBEDTLS_SSL_PROTO_DTLS) - int have_buffered = 0; - - /* We only check for buffered messages if the - * current datagram is fully consumed. */ - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && - ssl_next_record_is_in_datagram( ssl ) == 0 ) - { - if( ssl_load_buffered_message( ssl ) == 0 ) - have_buffered = 1; - } - - if( have_buffered == 0 ) -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - { - ret = ssl_get_next_record( ssl ); - if( ret == MBEDTLS_ERR_SSL_CONTINUE_PROCESSING ) - continue; - - if( ret != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, ( "ssl_get_next_record" ), ret ); - return( ret ); - } - } - } - - ret = mbedtls_ssl_handle_message_type( ssl ); - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ret == MBEDTLS_ERR_SSL_EARLY_MESSAGE ) - { - /* Buffer future message */ - ret = ssl_buffer_message( ssl ); - if( ret != 0 ) - return( ret ); - - ret = MBEDTLS_ERR_SSL_CONTINUE_PROCESSING; - } -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - - } while( MBEDTLS_ERR_SSL_NON_FATAL == ret || - MBEDTLS_ERR_SSL_CONTINUE_PROCESSING == ret ); - - if( 0 != ret ) - { - MBEDTLS_SSL_DEBUG_RET( 1, ( "mbedtls_ssl_handle_message_type" ), ret ); - return( ret ); - } - - if( ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE && - update_hs_digest == 1 ) - { - mbedtls_ssl_update_handshake_status( ssl ); - } - } - else - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "reuse previously read message" ) ); - ssl->keep_current_message = 0; - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= read record" ) ); - - return( 0 ); -} - -#if defined(MBEDTLS_SSL_PROTO_DTLS) -static int ssl_next_record_is_in_datagram( mbedtls_ssl_context *ssl ) -{ - if( ssl->in_left > ssl->next_record_offset ) - return( 1 ); - - return( 0 ); -} - -static int ssl_load_buffered_message( mbedtls_ssl_context *ssl ) -{ - mbedtls_ssl_handshake_params * const hs = ssl->handshake; - mbedtls_ssl_hs_buffer * hs_buf; - int ret = 0; - - if( hs == NULL ) - return( -1 ); - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> ssl_load_buffered_messsage" ) ); - - if( ssl->state == MBEDTLS_SSL_CLIENT_CHANGE_CIPHER_SPEC || - ssl->state == MBEDTLS_SSL_SERVER_CHANGE_CIPHER_SPEC ) - { - /* Check if we have seen a ChangeCipherSpec before. - * If yes, synthesize a CCS record. */ - if( !hs->buffering.seen_ccs ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "CCS not seen in the current flight" ) ); - ret = -1; - goto exit; - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Injecting buffered CCS message" ) ); - ssl->in_msgtype = MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC; - ssl->in_msglen = 1; - ssl->in_msg[0] = 1; - - /* As long as they are equal, the exact value doesn't matter. */ - ssl->in_left = 0; - ssl->next_record_offset = 0; - - hs->buffering.seen_ccs = 0; - goto exit; - } - -#if defined(MBEDTLS_DEBUG_C) - /* Debug only */ - { - unsigned offset; - for( offset = 1; offset < MBEDTLS_SSL_MAX_BUFFERED_HS; offset++ ) - { - hs_buf = &hs->buffering.hs[offset]; - if( hs_buf->is_valid == 1 ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Future message with sequence number %u %s buffered.", - hs->in_msg_seq + offset, - hs_buf->is_complete ? "fully" : "partially" ) ); - } - } - } -#endif /* MBEDTLS_DEBUG_C */ - - /* Check if we have buffered and/or fully reassembled the - * next handshake message. */ - hs_buf = &hs->buffering.hs[0]; - if( ( hs_buf->is_valid == 1 ) && ( hs_buf->is_complete == 1 ) ) - { - /* Synthesize a record containing the buffered HS message. */ - size_t msg_len = ( hs_buf->data[1] << 16 ) | - ( hs_buf->data[2] << 8 ) | - hs_buf->data[3]; - - /* Double-check that we haven't accidentally buffered - * a message that doesn't fit into the input buffer. */ - if( msg_len + 12 > MBEDTLS_SSL_IN_CONTENT_LEN ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Next handshake message has been buffered - load" ) ); - MBEDTLS_SSL_DEBUG_BUF( 3, "Buffered handshake message (incl. header)", - hs_buf->data, msg_len + 12 ); - - ssl->in_msgtype = MBEDTLS_SSL_MSG_HANDSHAKE; - ssl->in_hslen = msg_len + 12; - ssl->in_msglen = msg_len + 12; - memcpy( ssl->in_msg, hs_buf->data, ssl->in_hslen ); - - ret = 0; - goto exit; - } - else - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Next handshake message %u not or only partially bufffered", - hs->in_msg_seq ) ); - } - - ret = -1; - -exit: - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= ssl_load_buffered_message" ) ); - return( ret ); -} - -static int ssl_buffer_make_space( mbedtls_ssl_context *ssl, - size_t desired ) -{ - int offset; - mbedtls_ssl_handshake_params * const hs = ssl->handshake; - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Attempt to free buffered messages to have %u bytes available", - (unsigned) desired ) ); - - /* Get rid of future records epoch first, if such exist. */ - ssl_free_buffered_record( ssl ); - - /* Check if we have enough space available now. */ - if( desired <= ( MBEDTLS_SSL_DTLS_MAX_BUFFERING - - hs->buffering.total_bytes_buffered ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Enough space available after freeing future epoch record" ) ); - return( 0 ); - } - - /* We don't have enough space to buffer the next expected handshake - * message. Remove buffers used for future messages to gain space, - * starting with the most distant one. */ - for( offset = MBEDTLS_SSL_MAX_BUFFERED_HS - 1; - offset >= 0; offset-- ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Free buffering slot %d to make space for reassembly of next handshake message", - offset ) ); - - ssl_buffering_free_slot( ssl, (uint8_t) offset ); - - /* Check if we have enough space available now. */ - if( desired <= ( MBEDTLS_SSL_DTLS_MAX_BUFFERING - - hs->buffering.total_bytes_buffered ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Enough space available after freeing buffered HS messages" ) ); - return( 0 ); - } - } - - return( -1 ); -} - -static int ssl_buffer_message( mbedtls_ssl_context *ssl ) -{ - int ret = 0; - mbedtls_ssl_handshake_params * const hs = ssl->handshake; - - if( hs == NULL ) - return( 0 ); - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> ssl_buffer_message" ) ); - - switch( ssl->in_msgtype ) - { - case MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC: - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Remember CCS message" ) ); - - hs->buffering.seen_ccs = 1; - break; - - case MBEDTLS_SSL_MSG_HANDSHAKE: - { - unsigned recv_msg_seq_offset; - unsigned recv_msg_seq = ( ssl->in_msg[4] << 8 ) | ssl->in_msg[5]; - mbedtls_ssl_hs_buffer *hs_buf; - size_t msg_len = ssl->in_hslen - 12; - - /* We should never receive an old handshake - * message - double-check nonetheless. */ - if( recv_msg_seq < ssl->handshake->in_msg_seq ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - recv_msg_seq_offset = recv_msg_seq - ssl->handshake->in_msg_seq; - if( recv_msg_seq_offset >= MBEDTLS_SSL_MAX_BUFFERED_HS ) - { - /* Silently ignore -- message too far in the future */ - MBEDTLS_SSL_DEBUG_MSG( 2, - ( "Ignore future HS message with sequence number %u, " - "buffering window %u - %u", - recv_msg_seq, ssl->handshake->in_msg_seq, - ssl->handshake->in_msg_seq + MBEDTLS_SSL_MAX_BUFFERED_HS - 1 ) ); - - goto exit; - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Buffering HS message with sequence number %u, offset %u ", - recv_msg_seq, recv_msg_seq_offset ) ); - - hs_buf = &hs->buffering.hs[ recv_msg_seq_offset ]; - - /* Check if the buffering for this seq nr has already commenced. */ - if( !hs_buf->is_valid ) - { - size_t reassembly_buf_sz; - - hs_buf->is_fragmented = - ( ssl_hs_is_proper_fragment( ssl ) == 1 ); - - /* We copy the message back into the input buffer - * after reassembly, so check that it's not too large. - * This is an implementation-specific limitation - * and not one from the standard, hence it is not - * checked in ssl_check_hs_header(). */ - if( msg_len + 12 > MBEDTLS_SSL_IN_CONTENT_LEN ) - { - /* Ignore message */ - goto exit; - } - - /* Check if we have enough space to buffer the message. */ - if( hs->buffering.total_bytes_buffered > - MBEDTLS_SSL_DTLS_MAX_BUFFERING ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - reassembly_buf_sz = ssl_get_reassembly_buffer_size( msg_len, - hs_buf->is_fragmented ); - - if( reassembly_buf_sz > ( MBEDTLS_SSL_DTLS_MAX_BUFFERING - - hs->buffering.total_bytes_buffered ) ) - { - if( recv_msg_seq_offset > 0 ) - { - /* If we can't buffer a future message because - * of space limitations -- ignore. */ - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Buffering of future message of size %u would exceed the compile-time limit %u (already %u bytes buffered) -- ignore\n", - (unsigned) msg_len, MBEDTLS_SSL_DTLS_MAX_BUFFERING, - (unsigned) hs->buffering.total_bytes_buffered ) ); - goto exit; - } - else - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Buffering of future message of size %u would exceed the compile-time limit %u (already %u bytes buffered) -- attempt to make space by freeing buffered future messages\n", - (unsigned) msg_len, MBEDTLS_SSL_DTLS_MAX_BUFFERING, - (unsigned) hs->buffering.total_bytes_buffered ) ); - } - - if( ssl_buffer_make_space( ssl, reassembly_buf_sz ) != 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Reassembly of next message of size %u (%u with bitmap) would exceed the compile-time limit %u (already %u bytes buffered) -- fail\n", - (unsigned) msg_len, - (unsigned) reassembly_buf_sz, - MBEDTLS_SSL_DTLS_MAX_BUFFERING, - (unsigned) hs->buffering.total_bytes_buffered ) ); - ret = MBEDTLS_ERR_SSL_BUFFER_TOO_SMALL; - goto exit; - } - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "initialize reassembly, total length = %d", - msg_len ) ); - - hs_buf->data = mbedtls_calloc( 1, reassembly_buf_sz ); - if( hs_buf->data == NULL ) - { - ret = MBEDTLS_ERR_SSL_ALLOC_FAILED; - goto exit; - } - hs_buf->data_len = reassembly_buf_sz; - - /* Prepare final header: copy msg_type, length and message_seq, - * then add standardised fragment_offset and fragment_length */ - memcpy( hs_buf->data, ssl->in_msg, 6 ); - memset( hs_buf->data + 6, 0, 3 ); - memcpy( hs_buf->data + 9, hs_buf->data + 1, 3 ); - - hs_buf->is_valid = 1; - - hs->buffering.total_bytes_buffered += reassembly_buf_sz; - } - else - { - /* Make sure msg_type and length are consistent */ - if( memcmp( hs_buf->data, ssl->in_msg, 4 ) != 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "Fragment header mismatch - ignore" ) ); - /* Ignore */ - goto exit; - } - } - - if( !hs_buf->is_complete ) - { - size_t frag_len, frag_off; - unsigned char * const msg = hs_buf->data + 12; - - /* - * Check and copy current fragment - */ - - /* Validation of header fields already done in - * mbedtls_ssl_prepare_handshake_record(). */ - frag_off = ssl_get_hs_frag_off( ssl ); - frag_len = ssl_get_hs_frag_len( ssl ); - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "adding fragment, offset = %d, length = %d", - frag_off, frag_len ) ); - memcpy( msg + frag_off, ssl->in_msg + 12, frag_len ); - - if( hs_buf->is_fragmented ) - { - unsigned char * const bitmask = msg + msg_len; - ssl_bitmask_set( bitmask, frag_off, frag_len ); - hs_buf->is_complete = ( ssl_bitmask_check( bitmask, - msg_len ) == 0 ); - } - else - { - hs_buf->is_complete = 1; - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "message %scomplete", - hs_buf->is_complete ? "" : "not yet " ) ); - } - - break; - } - - default: - /* We don't buffer other types of messages. */ - break; - } - -exit: - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= ssl_buffer_message" ) ); - return( ret ); -} -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - -static int ssl_consume_current_message( mbedtls_ssl_context *ssl ) -{ - /* - * Consume last content-layer message and potentially - * update in_msglen which keeps track of the contents' - * consumption state. - * - * (1) Handshake messages: - * Remove last handshake message, move content - * and adapt in_msglen. - * - * (2) Alert messages: - * Consume whole record content, in_msglen = 0. - * - * (3) Change cipher spec: - * Consume whole record content, in_msglen = 0. - * - * (4) Application data: - * Don't do anything - the record layer provides - * the application data as a stream transport - * and consumes through mbedtls_ssl_read only. - * - */ - - /* Case (1): Handshake messages */ - if( ssl->in_hslen != 0 ) - { - /* Hard assertion to be sure that no application data - * is in flight, as corrupting ssl->in_msglen during - * ssl->in_offt != NULL is fatal. */ - if( ssl->in_offt != NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - /* - * Get next Handshake message in the current record - */ - - /* Notes: - * (1) in_hslen is not necessarily the size of the - * current handshake content: If DTLS handshake - * fragmentation is used, that's the fragment - * size instead. Using the total handshake message - * size here is faulty and should be changed at - * some point. - * (2) While it doesn't seem to cause problems, one - * has to be very careful not to assume that in_hslen - * is always <= in_msglen in a sensible communication. - * Again, it's wrong for DTLS handshake fragmentation. - * The following check is therefore mandatory, and - * should not be treated as a silently corrected assertion. - * Additionally, ssl->in_hslen might be arbitrarily out of - * bounds after handling a DTLS message with an unexpected - * sequence number, see mbedtls_ssl_prepare_handshake_record. - */ - if( ssl->in_hslen < ssl->in_msglen ) - { - ssl->in_msglen -= ssl->in_hslen; - memmove( ssl->in_msg, ssl->in_msg + ssl->in_hslen, - ssl->in_msglen ); - - MBEDTLS_SSL_DEBUG_BUF( 4, "remaining content in record", - ssl->in_msg, ssl->in_msglen ); - } - else - { - ssl->in_msglen = 0; - } - - ssl->in_hslen = 0; - } - /* Case (4): Application data */ - else if( ssl->in_offt != NULL ) - { - return( 0 ); - } - /* Everything else (CCS & Alerts) */ - else - { - ssl->in_msglen = 0; - } - - return( 0 ); -} - -static int ssl_record_is_in_progress( mbedtls_ssl_context *ssl ) -{ - if( ssl->in_msglen > 0 ) - return( 1 ); - - return( 0 ); -} - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - -static void ssl_free_buffered_record( mbedtls_ssl_context *ssl ) -{ - mbedtls_ssl_handshake_params * const hs = ssl->handshake; - if( hs == NULL ) - return; - - if( hs->buffering.future_record.data != NULL ) - { - hs->buffering.total_bytes_buffered -= - hs->buffering.future_record.len; - - mbedtls_free( hs->buffering.future_record.data ); - hs->buffering.future_record.data = NULL; - } -} - -static int ssl_load_buffered_record( mbedtls_ssl_context *ssl ) -{ - mbedtls_ssl_handshake_params * const hs = ssl->handshake; - unsigned char * rec; - size_t rec_len; - unsigned rec_epoch; - - if( ssl->conf->transport != MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - return( 0 ); - - if( hs == NULL ) - return( 0 ); - - rec = hs->buffering.future_record.data; - rec_len = hs->buffering.future_record.len; - rec_epoch = hs->buffering.future_record.epoch; - - if( rec == NULL ) - return( 0 ); - - /* Only consider loading future records if the - * input buffer is empty. */ - if( ssl_next_record_is_in_datagram( ssl ) == 1 ) - return( 0 ); - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> ssl_load_buffered_record" ) ); - - if( rec_epoch != ssl->in_epoch ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Buffered record not from current epoch." ) ); - goto exit; - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Found buffered record from current epoch - load" ) ); - - /* Double-check that the record is not too large */ - if( rec_len > MBEDTLS_SSL_IN_BUFFER_LEN - - (size_t)( ssl->in_hdr - ssl->in_buf ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - - memcpy( ssl->in_hdr, rec, rec_len ); - ssl->in_left = rec_len; - ssl->next_record_offset = 0; - - ssl_free_buffered_record( ssl ); - -exit: - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= ssl_load_buffered_record" ) ); - return( 0 ); -} - -static int ssl_buffer_future_record( mbedtls_ssl_context *ssl, - mbedtls_record const *rec ) -{ - mbedtls_ssl_handshake_params * const hs = ssl->handshake; - - /* Don't buffer future records outside handshakes. */ - if( hs == NULL ) - return( 0 ); - - /* Only buffer handshake records (we are only interested - * in Finished messages). */ - if( rec->type != MBEDTLS_SSL_MSG_HANDSHAKE ) - return( 0 ); - - /* Don't buffer more than one future epoch record. */ - if( hs->buffering.future_record.data != NULL ) - return( 0 ); - - /* Don't buffer record if there's not enough buffering space remaining. */ - if( rec->buf_len > ( MBEDTLS_SSL_DTLS_MAX_BUFFERING - - hs->buffering.total_bytes_buffered ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Buffering of future epoch record of size %u would exceed the compile-time limit %u (already %u bytes buffered) -- ignore\n", - (unsigned) rec->buf_len, MBEDTLS_SSL_DTLS_MAX_BUFFERING, - (unsigned) hs->buffering.total_bytes_buffered ) ); - return( 0 ); - } - - /* Buffer record */ - MBEDTLS_SSL_DEBUG_MSG( 2, ( "Buffer record from epoch %u", - ssl->in_epoch + 1 ) ); - MBEDTLS_SSL_DEBUG_BUF( 3, "Buffered record", rec->buf, rec->buf_len ); - - /* ssl_parse_record_header() only considers records - * of the next epoch as candidates for buffering. */ - hs->buffering.future_record.epoch = ssl->in_epoch + 1; - hs->buffering.future_record.len = rec->buf_len; - - hs->buffering.future_record.data = - mbedtls_calloc( 1, hs->buffering.future_record.len ); - if( hs->buffering.future_record.data == NULL ) - { - /* If we run out of RAM trying to buffer a - * record from the next epoch, just ignore. */ - return( 0 ); - } - - memcpy( hs->buffering.future_record.data, rec->buf, rec->buf_len ); - - hs->buffering.total_bytes_buffered += rec->buf_len; - return( 0 ); -} - -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - -static int ssl_get_next_record( mbedtls_ssl_context *ssl ) -{ - int ret; - mbedtls_record rec; - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - /* We might have buffered a future record; if so, - * and if the epoch matches now, load it. - * On success, this call will set ssl->in_left to - * the length of the buffered record, so that - * the calls to ssl_fetch_input() below will - * essentially be no-ops. */ - ret = ssl_load_buffered_record( ssl ); - if( ret != 0 ) - return( ret ); -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - - /* Ensure that we have enough space available for the default form - * of TLS / DTLS record headers (5 Bytes for TLS, 13 Bytes for DTLS, - * with no space for CIDs counted in). */ - ret = mbedtls_ssl_fetch_input( ssl, mbedtls_ssl_in_hdr_len( ssl ) ); - if( ret != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_fetch_input", ret ); - return( ret ); - } - - ret = ssl_parse_record_header( ssl, ssl->in_hdr, ssl->in_left, &rec ); - if( ret != 0 ) - { -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - if( ret == MBEDTLS_ERR_SSL_EARLY_MESSAGE ) - { - ret = ssl_buffer_future_record( ssl, &rec ); - if( ret != 0 ) - return( ret ); - - /* Fall through to handling of unexpected records */ - ret = MBEDTLS_ERR_SSL_UNEXPECTED_RECORD; - } - - if( ret == MBEDTLS_ERR_SSL_UNEXPECTED_RECORD ) - { -#if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) && defined(MBEDTLS_SSL_SRV_C) - /* Reset in pointers to default state for TLS/DTLS records, - * assuming no CID and no offset between record content and - * record plaintext. */ - ssl_update_in_pointers( ssl ); - - /* Setup internal message pointers from record structure. */ - ssl->in_msgtype = rec.type; -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - ssl->in_len = ssl->in_cid + rec.cid_len; -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - ssl->in_iv = ssl->in_msg = ssl->in_len + 2; - ssl->in_msglen = rec.data_len; - - ret = ssl_check_client_reconnect( ssl ); - if( ret != 0 ) - return( ret ); -#endif - - /* Skip unexpected record (but not whole datagram) */ - ssl->next_record_offset = rec.buf_len; - - MBEDTLS_SSL_DEBUG_MSG( 1, ( "discarding unexpected record " - "(header)" ) ); - } - else - { - /* Skip invalid record and the rest of the datagram */ - ssl->next_record_offset = 0; - ssl->in_left = 0; - - MBEDTLS_SSL_DEBUG_MSG( 1, ( "discarding invalid record " - "(header)" ) ); - } - - /* Get next record */ - return( MBEDTLS_ERR_SSL_CONTINUE_PROCESSING ); - } - else -#endif - { - return( ret ); - } - } - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - /* Remember offset of next record within datagram. */ - ssl->next_record_offset = rec.buf_len; - if( ssl->next_record_offset < ssl->in_left ) - { - MBEDTLS_SSL_DEBUG_MSG( 3, ( "more than one record within datagram" ) ); - } - } - else -#endif - { - /* - * Fetch record contents from underlying transport. - */ - ret = mbedtls_ssl_fetch_input( ssl, rec.buf_len ); - if( ret != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_fetch_input", ret ); - return( ret ); - } - - ssl->in_left = 0; - } - - /* - * Decrypt record contents. - */ - - if( ( ret = ssl_prepare_record_content( ssl, &rec ) ) != 0 ) - { -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - /* Silently discard invalid records */ - if( ret == MBEDTLS_ERR_SSL_INVALID_MAC ) - { - /* Except when waiting for Finished as a bad mac here - * probably means something went wrong in the handshake - * (eg wrong psk used, mitm downgrade attempt, etc.) */ - if( ssl->state == MBEDTLS_SSL_CLIENT_FINISHED || - ssl->state == MBEDTLS_SSL_SERVER_FINISHED ) - { -#if defined(MBEDTLS_SSL_ALL_ALERT_MESSAGES) - if( ret == MBEDTLS_ERR_SSL_INVALID_MAC ) - { - mbedtls_ssl_send_alert_message( ssl, - MBEDTLS_SSL_ALERT_LEVEL_FATAL, - MBEDTLS_SSL_ALERT_MSG_BAD_RECORD_MAC ); - } -#endif - return( ret ); - } - -#if defined(MBEDTLS_SSL_DTLS_BADMAC_LIMIT) - if( ssl->conf->badmac_limit != 0 && - ++ssl->badmac_seen >= ssl->conf->badmac_limit ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "too many records with bad MAC" ) ); - return( MBEDTLS_ERR_SSL_INVALID_MAC ); - } -#endif - - /* As above, invalid records cause - * dismissal of the whole datagram. */ - - ssl->next_record_offset = 0; - ssl->in_left = 0; - - MBEDTLS_SSL_DEBUG_MSG( 1, ( "discarding invalid record (mac)" ) ); - return( MBEDTLS_ERR_SSL_CONTINUE_PROCESSING ); - } - - return( ret ); - } - else -#endif - { - /* Error out (and send alert) on invalid records */ -#if defined(MBEDTLS_SSL_ALL_ALERT_MESSAGES) - if( ret == MBEDTLS_ERR_SSL_INVALID_MAC ) - { - mbedtls_ssl_send_alert_message( ssl, - MBEDTLS_SSL_ALERT_LEVEL_FATAL, - MBEDTLS_SSL_ALERT_MSG_BAD_RECORD_MAC ); - } -#endif - return( ret ); - } - } - - - /* Reset in pointers to default state for TLS/DTLS records, - * assuming no CID and no offset between record content and - * record plaintext. */ - ssl_update_in_pointers( ssl ); -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - ssl->in_len = ssl->in_cid + rec.cid_len; -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - ssl->in_iv = ssl->in_msg = ssl->in_len + 2; - - /* The record content type may change during decryption, - * so re-read it. */ - ssl->in_msgtype = rec.type; - /* Also update the input buffer, because unfortunately - * the server-side ssl_parse_client_hello() reparses the - * record header when receiving a ClientHello initiating - * a renegotiation. */ - ssl->in_hdr[0] = rec.type; - ssl->in_msg = rec.buf + rec.data_offset; - ssl->in_msglen = rec.data_len; - ssl->in_len[0] = (unsigned char)( rec.data_len >> 8 ); - ssl->in_len[1] = (unsigned char)( rec.data_len ); - - return( 0 ); -} - -int mbedtls_ssl_handle_message_type( mbedtls_ssl_context *ssl ) -{ - int ret; - - /* - * Handle particular types of records - */ - if( ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE ) - { - if( ( ret = mbedtls_ssl_prepare_handshake_record( ssl ) ) != 0 ) - { - return( ret ); - } - } - - if( ssl->in_msgtype == MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC ) - { - if( ssl->in_msglen != 1 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "invalid CCS message, len: %d", - ssl->in_msglen ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } - - if( ssl->in_msg[0] != 1 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "invalid CCS message, content: %02x", - ssl->in_msg[0] ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && - ssl->state != MBEDTLS_SSL_CLIENT_CHANGE_CIPHER_SPEC && - ssl->state != MBEDTLS_SSL_SERVER_CHANGE_CIPHER_SPEC ) - { - if( ssl->handshake == NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "dropping ChangeCipherSpec outside handshake" ) ); - return( MBEDTLS_ERR_SSL_UNEXPECTED_RECORD ); - } - - MBEDTLS_SSL_DEBUG_MSG( 1, ( "received out-of-order ChangeCipherSpec - remember" ) ); - return( MBEDTLS_ERR_SSL_EARLY_MESSAGE ); - } -#endif - } - - if( ssl->in_msgtype == MBEDTLS_SSL_MSG_ALERT ) - { - if( ssl->in_msglen != 2 ) - { - /* Note: Standard allows for more than one 2 byte alert - to be packed in a single message, but Mbed TLS doesn't - currently support this. */ - MBEDTLS_SSL_DEBUG_MSG( 1, ( "invalid alert message, len: %d", - ssl->in_msglen ) ); - return( MBEDTLS_ERR_SSL_INVALID_RECORD ); - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "got an alert message, type: [%d:%d]", - ssl->in_msg[0], ssl->in_msg[1] ) ); - - /* - * Ignore non-fatal alerts, except close_notify and no_renegotiation - */ - if( ssl->in_msg[0] == MBEDTLS_SSL_ALERT_LEVEL_FATAL ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "is a fatal alert message (msg %d)", - ssl->in_msg[1] ) ); - return( MBEDTLS_ERR_SSL_FATAL_ALERT_MESSAGE ); - } - - if( ssl->in_msg[0] == MBEDTLS_SSL_ALERT_LEVEL_WARNING && - ssl->in_msg[1] == MBEDTLS_SSL_ALERT_MSG_CLOSE_NOTIFY ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "is a close notify message" ) ); - return( MBEDTLS_ERR_SSL_PEER_CLOSE_NOTIFY ); - } - -#if defined(MBEDTLS_SSL_RENEGOTIATION_ENABLED) - if( ssl->in_msg[0] == MBEDTLS_SSL_ALERT_LEVEL_WARNING && - ssl->in_msg[1] == MBEDTLS_SSL_ALERT_MSG_NO_RENEGOTIATION ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "is a SSLv3 no renegotiation alert" ) ); - /* Will be handled when trying to parse ServerHello */ - return( 0 ); - } -#endif - -#if defined(MBEDTLS_SSL_PROTO_SSL3) && defined(MBEDTLS_SSL_SRV_C) - if( ssl->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 && - ssl->conf->endpoint == MBEDTLS_SSL_IS_SERVER && - ssl->in_msg[0] == MBEDTLS_SSL_ALERT_LEVEL_WARNING && - ssl->in_msg[1] == MBEDTLS_SSL_ALERT_MSG_NO_CERT ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "is a SSLv3 no_cert" ) ); - /* Will be handled in mbedtls_ssl_parse_certificate() */ - return( 0 ); - } -#endif /* MBEDTLS_SSL_PROTO_SSL3 && MBEDTLS_SSL_SRV_C */ - - /* Silently ignore: fetch new message */ - return MBEDTLS_ERR_SSL_NON_FATAL; - } - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - /* Drop unexpected ApplicationData records, - * except at the beginning of renegotiations */ - if( ssl->in_msgtype == MBEDTLS_SSL_MSG_APPLICATION_DATA && - ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER -#if defined(MBEDTLS_SSL_RENEGOTIATION) - && ! ( ssl->renego_status == MBEDTLS_SSL_RENEGOTIATION_IN_PROGRESS && - ssl->state == MBEDTLS_SSL_SERVER_HELLO ) -#endif - ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "dropping unexpected ApplicationData" ) ); - return( MBEDTLS_ERR_SSL_NON_FATAL ); - } - - if( ssl->handshake != NULL && - ssl->state == MBEDTLS_SSL_HANDSHAKE_OVER ) - { - ssl_handshake_wrapup_free_hs_transform( ssl ); - } - } -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - - return( 0 ); -} - -int mbedtls_ssl_send_fatal_handshake_failure( mbedtls_ssl_context *ssl ) -{ - int ret; - - if( ( ret = mbedtls_ssl_send_alert_message( ssl, - MBEDTLS_SSL_ALERT_LEVEL_FATAL, - MBEDTLS_SSL_ALERT_MSG_HANDSHAKE_FAILURE ) ) != 0 ) - { - return( ret ); - } - - return( 0 ); -} - -int mbedtls_ssl_send_alert_message( mbedtls_ssl_context *ssl, - unsigned char level, - unsigned char message ) -{ - int ret; - - if( ssl == NULL || ssl->conf == NULL ) - return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> send alert message" ) ); - MBEDTLS_SSL_DEBUG_MSG( 3, ( "send alert level=%u message=%u", level, message )); - - ssl->out_msgtype = MBEDTLS_SSL_MSG_ALERT; - ssl->out_msglen = 2; - ssl->out_msg[0] = level; - ssl->out_msg[1] = message; - - if( ( ret = mbedtls_ssl_write_record( ssl, SSL_FORCE_FLUSH ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_write_record", ret ); - return( ret ); - } - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= send alert message" ) ); - - return( 0 ); -} - #if defined(MBEDTLS_X509_CRT_PARSE_C) static void ssl_clear_peer_cert( mbedtls_ssl_session *session ) { @@ -6821,14 +2170,14 @@ static int ssl_check_peer_crt_unchanged( mbedtls_ssl_context *ssl, if( peer_crt->raw.len != crt_buf_len ) return( -1 ); - return( memcmp( peer_crt->raw.p, crt_buf, crt_buf_len ) ); + return( memcmp( peer_crt->raw.p, crt_buf, peer_crt->raw.len ) ); } #else /* MBEDTLS_SSL_KEEP_PEER_CERTIFICATE */ static int ssl_check_peer_crt_unchanged( mbedtls_ssl_context *ssl, unsigned char *crt_buf, size_t crt_buf_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char const * const peer_cert_digest = ssl->session->peer_cert_digest; mbedtls_md_type_t const peer_cert_digest_type = @@ -6861,7 +2210,7 @@ static int ssl_check_peer_crt_unchanged( mbedtls_ssl_context *ssl, static int ssl_parse_certificate_chain( mbedtls_ssl_context *ssl, mbedtls_x509_crt *chain ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; #if defined(MBEDTLS_SSL_RENEGOTIATION) && defined(MBEDTLS_SSL_CLI_C) int crt_cnt=0; #endif @@ -7276,14 +2625,14 @@ static int ssl_parse_certificate_verify( mbedtls_ssl_context *ssl, static int ssl_remember_peer_crt_digest( mbedtls_ssl_context *ssl, unsigned char *start, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* Remember digest of the peer's end-CRT. */ ssl->session_negotiate->peer_cert_digest = mbedtls_calloc( 1, MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_LEN ); if( ssl->session_negotiate->peer_cert_digest == NULL ) { MBEDTLS_SSL_DEBUG_MSG( 1, ( "alloc(%d bytes) failed", - sizeof( MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_LEN ) ) ); + MBEDTLS_SSL_PEER_CERT_DIGEST_DFL_LEN ) ); mbedtls_ssl_send_alert_message( ssl, MBEDTLS_SSL_ALERT_LEVEL_FATAL, MBEDTLS_SSL_ALERT_MSG_INTERNAL_ERROR ); @@ -7308,7 +2657,7 @@ static int ssl_remember_peer_pubkey( mbedtls_ssl_context *ssl, unsigned char *start, size_t len ) { unsigned char *end = start + len; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* Make a copy of the peer's raw public key. */ mbedtls_pk_init( &ssl->handshake->peer_pubkey ); @@ -7476,102 +2825,6 @@ exit: } #endif /* MBEDTLS_KEY_EXCHANGE__WITH_CERT__ENABLED */ -int mbedtls_ssl_write_change_cipher_spec( mbedtls_ssl_context *ssl ) -{ - int ret; - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write change cipher spec" ) ); - - ssl->out_msgtype = MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC; - ssl->out_msglen = 1; - ssl->out_msg[0] = 1; - - ssl->state++; - - if( ( ret = mbedtls_ssl_write_handshake_msg( ssl ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_write_handshake_msg", ret ); - return( ret ); - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= write change cipher spec" ) ); - - return( 0 ); -} - -int mbedtls_ssl_parse_change_cipher_spec( mbedtls_ssl_context *ssl ) -{ - int ret; - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> parse change cipher spec" ) ); - - if( ( ret = mbedtls_ssl_read_record( ssl, 1 ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_read_record", ret ); - return( ret ); - } - - if( ssl->in_msgtype != MBEDTLS_SSL_MSG_CHANGE_CIPHER_SPEC ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad change cipher spec message" ) ); - mbedtls_ssl_send_alert_message( ssl, MBEDTLS_SSL_ALERT_LEVEL_FATAL, - MBEDTLS_SSL_ALERT_MSG_UNEXPECTED_MESSAGE ); - return( MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE ); - } - - /* CCS records are only accepted if they have length 1 and content '1', - * so we don't need to check this here. */ - - /* - * Switch to our negotiated transform and session parameters for inbound - * data. - */ - MBEDTLS_SSL_DEBUG_MSG( 3, ( "switching to new transform spec for inbound data" ) ); - ssl->transform_in = ssl->transform_negotiate; - ssl->session_in = ssl->session_negotiate; - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { -#if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) - ssl_dtls_replay_reset( ssl ); -#endif - - /* Increment epoch */ - if( ++ssl->in_epoch == 0 ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "DTLS epoch would wrap" ) ); - /* This is highly unlikely to happen for legitimate reasons, so - treat it as an attack and don't send an alert. */ - return( MBEDTLS_ERR_SSL_COUNTER_WRAPPING ); - } - } - else -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - memset( ssl->in_ctr, 0, 8 ); - - ssl_update_in_pointers( ssl ); - -#if defined(MBEDTLS_SSL_HW_RECORD_ACCEL) - if( mbedtls_ssl_hw_record_activate != NULL ) - { - if( ( ret = mbedtls_ssl_hw_record_activate( ssl, MBEDTLS_SSL_CHANNEL_INBOUND ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_hw_record_activate", ret ); - mbedtls_ssl_send_alert_message( ssl, MBEDTLS_SSL_ALERT_LEVEL_FATAL, - MBEDTLS_SSL_ALERT_MSG_INTERNAL_ERROR ); - return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); - } - } -#endif - - ssl->state++; - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= parse change cipher spec" ) ); - - return( 0 ); -} - void mbedtls_ssl_optimize_checksum( mbedtls_ssl_context *ssl, const mbedtls_ssl_ciphersuite_t *ciphersuite_info ) { @@ -7987,7 +3240,7 @@ static void ssl_calc_finished_tls_sha384( #endif /* MBEDTLS_SHA512_C */ #endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ -static void ssl_handshake_wrapup_free_hs_transform( mbedtls_ssl_context *ssl ) +void mbedtls_ssl_handshake_wrapup_free_hs_transform( mbedtls_ssl_context *ssl ) { MBEDTLS_SSL_DEBUG_MSG( 3, ( "=> handshake wrapup: final free" ) ); @@ -8059,7 +3312,7 @@ void mbedtls_ssl_handshake_wrapup( mbedtls_ssl_context *ssl ) ssl->handshake->flight != NULL ) { /* Cancel handshake timer */ - ssl_set_timer( ssl, 0 ); + mbedtls_ssl_set_timer( ssl, 0 ); /* Keep last flight around in case we need to resend it: * we need the handshake and transform structures for that */ @@ -8067,7 +3320,7 @@ void mbedtls_ssl_handshake_wrapup( mbedtls_ssl_context *ssl ) } else #endif - ssl_handshake_wrapup_free_hs_transform( ssl ); + mbedtls_ssl_handshake_wrapup_free_hs_transform( ssl ); ssl->state++; @@ -8080,7 +3333,7 @@ int mbedtls_ssl_write_finished( mbedtls_ssl_context *ssl ) MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write finished" ) ); - ssl_update_out_pointers( ssl, ssl->transform_negotiate ); + mbedtls_ssl_update_out_pointers( ssl, ssl->transform_negotiate ); ssl->handshake->calc_finished( ssl, ssl->out_msg + 4, ssl->conf->endpoint ); @@ -8200,7 +3453,7 @@ int mbedtls_ssl_write_finished( mbedtls_ssl_context *ssl ) int mbedtls_ssl_parse_finished( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned int hash_len; unsigned char buf[SSL_MAX_HASH_LEN]; @@ -8424,7 +3677,7 @@ static int ssl_handshake_init( mbedtls_ssl_context *ssl ) else ssl->handshake->retransmit_state = MBEDTLS_SSL_RETRANS_WAITING; - ssl_set_timer( ssl, 0 ); + mbedtls_ssl_set_timer( ssl, 0 ); } #endif @@ -8460,103 +3713,6 @@ static int ssl_cookie_check_dummy( void *ctx, } #endif /* MBEDTLS_SSL_DTLS_HELLO_VERIFY && MBEDTLS_SSL_SRV_C */ -/* Once ssl->out_hdr as the address of the beginning of the - * next outgoing record is set, deduce the other pointers. - * - * Note: For TLS, we save the implicit record sequence number - * (entering MAC computation) in the 8 bytes before ssl->out_hdr, - * and the caller has to make sure there's space for this. - */ - -static void ssl_update_out_pointers( mbedtls_ssl_context *ssl, - mbedtls_ssl_transform *transform ) -{ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - ssl->out_ctr = ssl->out_hdr + 3; -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - ssl->out_cid = ssl->out_ctr + 8; - ssl->out_len = ssl->out_cid; - if( transform != NULL ) - ssl->out_len += transform->out_cid_len; -#else /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - ssl->out_len = ssl->out_ctr + 8; -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - ssl->out_iv = ssl->out_len + 2; - } - else -#endif - { - ssl->out_ctr = ssl->out_hdr - 8; - ssl->out_len = ssl->out_hdr + 3; -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - ssl->out_cid = ssl->out_len; -#endif - ssl->out_iv = ssl->out_hdr + 5; - } - - /* Adjust out_msg to make space for explicit IV, if used. */ - if( transform != NULL && - ssl->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_2 ) - { - ssl->out_msg = ssl->out_iv + transform->ivlen - transform->fixed_ivlen; - } - else - ssl->out_msg = ssl->out_iv; -} - -/* Once ssl->in_hdr as the address of the beginning of the - * next incoming record is set, deduce the other pointers. - * - * Note: For TLS, we save the implicit record sequence number - * (entering MAC computation) in the 8 bytes before ssl->in_hdr, - * and the caller has to make sure there's space for this. - */ - -static void ssl_update_in_pointers( mbedtls_ssl_context *ssl ) -{ - /* This function sets the pointers to match the case - * of unprotected TLS/DTLS records, with both ssl->in_iv - * and ssl->in_msg pointing to the beginning of the record - * content. - * - * When decrypting a protected record, ssl->in_msg - * will be shifted to point to the beginning of the - * record plaintext. - */ - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - /* This sets the header pointers to match records - * without CID. When we receive a record containing - * a CID, the fields are shifted accordingly in - * ssl_parse_record_header(). */ - ssl->in_ctr = ssl->in_hdr + 3; -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - ssl->in_cid = ssl->in_ctr + 8; - ssl->in_len = ssl->in_cid; /* Default: no CID */ -#else /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - ssl->in_len = ssl->in_ctr + 8; -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - ssl->in_iv = ssl->in_len + 2; - } - else -#endif - { - ssl->in_ctr = ssl->in_hdr - 8; - ssl->in_len = ssl->in_hdr + 3; -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - ssl->in_cid = ssl->in_len; -#endif - ssl->in_iv = ssl->in_hdr + 5; - } - - /* This will be adjusted at record decryption time. */ - ssl->in_msg = ssl->in_iv; -} - /* * Initialize an SSL context */ @@ -8569,31 +3725,10 @@ void mbedtls_ssl_init( mbedtls_ssl_context *ssl ) * Setup an SSL context */ -static void ssl_reset_in_out_pointers( mbedtls_ssl_context *ssl ) -{ - /* Set the incoming and outgoing record pointers. */ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - ssl->out_hdr = ssl->out_buf; - ssl->in_hdr = ssl->in_buf; - } - else -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - { - ssl->out_hdr = ssl->out_buf + 8; - ssl->in_hdr = ssl->in_buf + 8; - } - - /* Derive other internal pointers. */ - ssl_update_out_pointers( ssl, NULL /* no transform enabled */ ); - ssl_update_in_pointers ( ssl ); -} - int mbedtls_ssl_setup( mbedtls_ssl_context *ssl, const mbedtls_ssl_config *conf ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ssl->conf = conf; @@ -8620,7 +3755,7 @@ int mbedtls_ssl_setup( mbedtls_ssl_context *ssl, goto error; } - ssl_reset_in_out_pointers( ssl ); + mbedtls_ssl_reset_in_out_pointers( ssl ); if( ( ret = ssl_handshake_init( ssl ) ) != 0 ) goto error; @@ -8658,9 +3793,9 @@ error: * If partial is non-zero, keep data in the input buffer and client ID. * (Use when a DTLS client reconnects from the same port.) */ -static int ssl_session_reset_int( mbedtls_ssl_context *ssl, int partial ) +int mbedtls_ssl_session_reset_int( mbedtls_ssl_context *ssl, int partial ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; #if !defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) || \ !defined(MBEDTLS_SSL_SRV_C) @@ -8670,7 +3805,7 @@ static int ssl_session_reset_int( mbedtls_ssl_context *ssl, int partial ) ssl->state = MBEDTLS_SSL_HELLO_REQUEST; /* Cancel any possibly running timer */ - ssl_set_timer( ssl, 0 ); + mbedtls_ssl_set_timer( ssl, 0 ); #if defined(MBEDTLS_SSL_RENEGOTIATION) ssl->renego_status = MBEDTLS_SSL_INITIAL_HANDSHAKE; @@ -8683,7 +3818,7 @@ static int ssl_session_reset_int( mbedtls_ssl_context *ssl, int partial ) ssl->secure_renegotiation = MBEDTLS_SSL_LEGACY_RENEGOTIATION; ssl->in_offt = NULL; - ssl_reset_in_out_pointers( ssl ); + mbedtls_ssl_reset_in_out_pointers( ssl ); ssl->in_msgtype = 0; ssl->in_msglen = 0; @@ -8692,7 +3827,7 @@ static int ssl_session_reset_int( mbedtls_ssl_context *ssl, int partial ) ssl->in_epoch = 0; #endif #if defined(MBEDTLS_SSL_DTLS_ANTI_REPLAY) - ssl_dtls_replay_reset( ssl ); + mbedtls_ssl_dtls_replay_reset( ssl ); #endif ssl->in_hslen = 0; @@ -8779,7 +3914,7 @@ static int ssl_session_reset_int( mbedtls_ssl_context *ssl, int partial ) */ int mbedtls_ssl_session_reset( mbedtls_ssl_context *ssl ) { - return( ssl_session_reset_int( ssl, 0 ) ); + return( mbedtls_ssl_session_reset_int( ssl, 0 ) ); } /* @@ -8890,7 +4025,7 @@ void mbedtls_ssl_set_timer_cb( mbedtls_ssl_context *ssl, ssl->f_get_timer = f_get_timer; /* Make sure we start with no timer running */ - ssl_set_timer( ssl, 0 ); + mbedtls_ssl_set_timer( ssl, 0 ); } #if defined(MBEDTLS_SSL_SRV_C) @@ -8908,7 +4043,7 @@ void mbedtls_ssl_conf_session_cache( mbedtls_ssl_config *conf, #if defined(MBEDTLS_SSL_CLI_C) int mbedtls_ssl_set_session( mbedtls_ssl_context *ssl, const mbedtls_ssl_session *session ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ssl == NULL || session == NULL || @@ -9152,13 +4287,18 @@ int mbedtls_ssl_conf_psk( mbedtls_ssl_config *conf, const unsigned char *psk, size_t psk_len, const unsigned char *psk_identity, size_t psk_identity_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* Remove opaque/raw PSK + PSK Identity */ ssl_conf_remove_psk( conf ); /* Check and set raw PSK */ - if( psk == NULL || psk_len > MBEDTLS_PSK_MAX_LEN ) + if( psk == NULL ) return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + if( psk_len == 0 ) + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + if( psk_len > MBEDTLS_PSK_MAX_LEN ) + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + if( ( conf->psk = mbedtls_calloc( 1, psk_len ) ) == NULL ) return( MBEDTLS_ERR_SSL_ALLOC_FAILED ); conf->psk_len = psk_len; @@ -9216,7 +4356,7 @@ int mbedtls_ssl_conf_psk_opaque( mbedtls_ssl_config *conf, const unsigned char *psk_identity, size_t psk_identity_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* Clear opaque/raw PSK + PSK Identity, if present. */ ssl_conf_remove_psk( conf ); @@ -9261,7 +4401,7 @@ void mbedtls_ssl_conf_psk_cb( mbedtls_ssl_config *conf, #if !defined(MBEDTLS_DEPRECATED_REMOVED) int mbedtls_ssl_conf_dh_param( mbedtls_ssl_config *conf, const char *dhm_P, const char *dhm_G ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = mbedtls_mpi_read_string( &conf->dhm_P, 16, dhm_P ) ) != 0 || ( ret = mbedtls_mpi_read_string( &conf->dhm_G, 16, dhm_G ) ) != 0 ) @@ -9279,7 +4419,7 @@ int mbedtls_ssl_conf_dh_param_bin( mbedtls_ssl_config *conf, const unsigned char *dhm_P, size_t P_len, const unsigned char *dhm_G, size_t G_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = mbedtls_mpi_read_binary( &conf->dhm_P, dhm_P, P_len ) ) != 0 || ( ret = mbedtls_mpi_read_binary( &conf->dhm_G, dhm_G, G_len ) ) != 0 ) @@ -9294,7 +4434,7 @@ int mbedtls_ssl_conf_dh_param_bin( mbedtls_ssl_config *conf, int mbedtls_ssl_conf_dh_param_ctx( mbedtls_ssl_config *conf, mbedtls_dhm_context *dhm_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = mbedtls_mpi_copy( &conf->dhm_P, &dhm_ctx->P ) ) != 0 || ( ret = mbedtls_mpi_copy( &conf->dhm_G, &dhm_ctx->G ) ) != 0 ) @@ -9609,66 +4749,6 @@ void mbedtls_ssl_set_async_operation_data( mbedtls_ssl_context *ssl, /* * SSL get accessors */ -size_t mbedtls_ssl_get_bytes_avail( const mbedtls_ssl_context *ssl ) -{ - return( ssl->in_offt == NULL ? 0 : ssl->in_msglen ); -} - -int mbedtls_ssl_check_pending( const mbedtls_ssl_context *ssl ) -{ - /* - * Case A: We're currently holding back - * a message for further processing. - */ - - if( ssl->keep_current_message == 1 ) - { - MBEDTLS_SSL_DEBUG_MSG( 3, ( "ssl_check_pending: record held back for processing" ) ); - return( 1 ); - } - - /* - * Case B: Further records are pending in the current datagram. - */ - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && - ssl->in_left > ssl->next_record_offset ) - { - MBEDTLS_SSL_DEBUG_MSG( 3, ( "ssl_check_pending: more records within current datagram" ) ); - return( 1 ); - } -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - - /* - * Case C: A handshake message is being processed. - */ - - if( ssl->in_hslen > 0 && ssl->in_hslen < ssl->in_msglen ) - { - MBEDTLS_SSL_DEBUG_MSG( 3, ( "ssl_check_pending: more handshake messages within current record" ) ); - return( 1 ); - } - - /* - * Case D: An application data message is being processed - */ - if( ssl->in_offt != NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 3, ( "ssl_check_pending: application data record is being processed" ) ); - return( 1 ); - } - - /* - * In all other cases, the rest of the message can be dropped. - * As in ssl_get_next_record, this needs to be adapted if - * we implement support for multiple alerts in single records. - */ - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "ssl_check_pending: nothing pending" ) ); - return( 0 ); -} - uint32_t mbedtls_ssl_get_verify_result( const mbedtls_ssl_context *ssl ) { if( ssl->session != NULL ) @@ -9726,66 +4806,6 @@ const char *mbedtls_ssl_get_version( const mbedtls_ssl_context *ssl ) } } -int mbedtls_ssl_get_record_expansion( const mbedtls_ssl_context *ssl ) -{ - size_t transform_expansion = 0; - const mbedtls_ssl_transform *transform = ssl->transform_out; - unsigned block_size; - - size_t out_hdr_len = mbedtls_ssl_out_hdr_len( ssl ); - - if( transform == NULL ) - return( (int) out_hdr_len ); - -#if defined(MBEDTLS_ZLIB_SUPPORT) - if( ssl->session_out->compression != MBEDTLS_SSL_COMPRESS_NULL ) - return( MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE ); -#endif - - switch( mbedtls_cipher_get_cipher_mode( &transform->cipher_ctx_enc ) ) - { - case MBEDTLS_MODE_GCM: - case MBEDTLS_MODE_CCM: - case MBEDTLS_MODE_CHACHAPOLY: - case MBEDTLS_MODE_STREAM: - transform_expansion = transform->minlen; - break; - - case MBEDTLS_MODE_CBC: - - block_size = mbedtls_cipher_get_block_size( - &transform->cipher_ctx_enc ); - - /* Expansion due to the addition of the MAC. */ - transform_expansion += transform->maclen; - - /* Expansion due to the addition of CBC padding; - * Theoretically up to 256 bytes, but we never use - * more than the block size of the underlying cipher. */ - transform_expansion += block_size; - - /* For TLS 1.1 or higher, an explicit IV is added - * after the record header. */ -#if defined(MBEDTLS_SSL_PROTO_TLS1_1) || defined(MBEDTLS_SSL_PROTO_TLS1_2) - if( ssl->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_2 ) - transform_expansion += block_size; -#endif /* MBEDTLS_SSL_PROTO_TLS1_1 || MBEDTLS_SSL_PROTO_TLS1_2 */ - - break; - - default: - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - -#if defined(MBEDTLS_SSL_DTLS_CONNECTION_ID) - if( transform->out_cid_len != 0 ) - transform_expansion += MBEDTLS_SSL_MAX_CID_EXPANSION; -#endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ - - return( (int)( out_hdr_len + transform_expansion ) ); -} - #if defined(MBEDTLS_SSL_MAX_FRAGMENT_LENGTH) size_t mbedtls_ssl_get_max_frag_len( const mbedtls_ssl_context *ssl ) { @@ -9815,7 +4835,7 @@ size_t mbedtls_ssl_get_max_frag_len( const mbedtls_ssl_context *ssl ) #endif /* MBEDTLS_SSL_MAX_FRAGMENT_LENGTH */ #if defined(MBEDTLS_SSL_PROTO_DTLS) -static size_t ssl_get_current_mtu( const mbedtls_ssl_context *ssl ) +size_t mbedtls_ssl_get_current_mtu( const mbedtls_ssl_context *ssl ) { /* Return unlimited mtu for client hello messages to avoid fragmentation. */ if( ssl->conf->endpoint == MBEDTLS_SSL_IS_CLIENT && @@ -9851,9 +4871,9 @@ int mbedtls_ssl_get_max_out_record_payload( const mbedtls_ssl_context *ssl ) #endif #if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl_get_current_mtu( ssl ) != 0 ) + if( mbedtls_ssl_get_current_mtu( ssl ) != 0 ) { - const size_t mtu = ssl_get_current_mtu( ssl ); + const size_t mtu = mbedtls_ssl_get_current_mtu( ssl ); const int ret = mbedtls_ssl_get_record_expansion( ssl ); const size_t overhead = (size_t) ret; @@ -10342,7 +5362,7 @@ static int ssl_session_load( mbedtls_ssl_session *session, if( cert_len != 0 ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( cert_len > (size_t)( end - p ) ) return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); @@ -10530,7 +5550,7 @@ int mbedtls_ssl_handshake( mbedtls_ssl_context *ssl ) */ static int ssl_write_hello_request( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write hello request" ) ); @@ -10559,9 +5579,9 @@ static int ssl_write_hello_request( mbedtls_ssl_context *ssl ) * If the handshake doesn't complete due to waiting for I/O, it will continue * during the next calls to mbedtls_ssl_renegotiate() or mbedtls_ssl_read() respectively. */ -static int ssl_start_renegotiation( mbedtls_ssl_context *ssl ) +int mbedtls_ssl_start_renegotiation( mbedtls_ssl_context *ssl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> renegotiate" ) ); @@ -10633,9 +5653,9 @@ int mbedtls_ssl_renegotiate( mbedtls_ssl_context *ssl ) if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER ) return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - if( ( ret = ssl_start_renegotiation( ssl ) ) != 0 ) + if( ( ret = mbedtls_ssl_start_renegotiation( ssl ) ) != 0 ) { - MBEDTLS_SSL_DEBUG_RET( 1, "ssl_start_renegotiation", ret ); + MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_start_renegotiation", ret ); return( ret ); } } @@ -10651,546 +5671,8 @@ int mbedtls_ssl_renegotiate( mbedtls_ssl_context *ssl ) return( ret ); } - -/* - * Check record counters and renegotiate if they're above the limit. - */ -static int ssl_check_ctr_renegotiate( mbedtls_ssl_context *ssl ) -{ - size_t ep_len = ssl_ep_len( ssl ); - int in_ctr_cmp; - int out_ctr_cmp; - - if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER || - ssl->renego_status == MBEDTLS_SSL_RENEGOTIATION_PENDING || - ssl->conf->disable_renegotiation == MBEDTLS_SSL_RENEGOTIATION_DISABLED ) - { - return( 0 ); - } - - in_ctr_cmp = memcmp( ssl->in_ctr + ep_len, - ssl->conf->renego_period + ep_len, 8 - ep_len ); - out_ctr_cmp = memcmp( ssl->cur_out_ctr + ep_len, - ssl->conf->renego_period + ep_len, 8 - ep_len ); - - if( in_ctr_cmp <= 0 && out_ctr_cmp <= 0 ) - { - return( 0 ); - } - - MBEDTLS_SSL_DEBUG_MSG( 1, ( "record counter limit reached: renegotiate" ) ); - return( mbedtls_ssl_renegotiate( ssl ) ); -} #endif /* MBEDTLS_SSL_RENEGOTIATION */ -/* - * Receive application data decrypted from the SSL layer - */ -int mbedtls_ssl_read( mbedtls_ssl_context *ssl, unsigned char *buf, size_t len ) -{ - int ret; - size_t n; - - if( ssl == NULL || ssl->conf == NULL ) - return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> read" ) ); - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - if( ( ret = mbedtls_ssl_flush_output( ssl ) ) != 0 ) - return( ret ); - - if( ssl->handshake != NULL && - ssl->handshake->retransmit_state == MBEDTLS_SSL_RETRANS_SENDING ) - { - if( ( ret = mbedtls_ssl_flight_transmit( ssl ) ) != 0 ) - return( ret ); - } - } -#endif - - /* - * Check if renegotiation is necessary and/or handshake is - * in process. If yes, perform/continue, and fall through - * if an unexpected packet is received while the client - * is waiting for the ServerHello. - * - * (There is no equivalent to the last condition on - * the server-side as it is not treated as within - * a handshake while waiting for the ClientHello - * after a renegotiation request.) - */ - -#if defined(MBEDTLS_SSL_RENEGOTIATION) - ret = ssl_check_ctr_renegotiate( ssl ); - if( ret != MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO && - ret != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "ssl_check_ctr_renegotiate", ret ); - return( ret ); - } -#endif - - if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER ) - { - ret = mbedtls_ssl_handshake( ssl ); - if( ret != MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO && - ret != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_handshake", ret ); - return( ret ); - } - } - - /* Loop as long as no application data record is available */ - while( ssl->in_offt == NULL ) - { - /* Start timer if not already running */ - if( ssl->f_get_timer != NULL && - ssl->f_get_timer( ssl->p_timer ) == -1 ) - { - ssl_set_timer( ssl, ssl->conf->read_timeout ); - } - - if( ( ret = mbedtls_ssl_read_record( ssl, 1 ) ) != 0 ) - { - if( ret == MBEDTLS_ERR_SSL_CONN_EOF ) - return( 0 ); - - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_read_record", ret ); - return( ret ); - } - - if( ssl->in_msglen == 0 && - ssl->in_msgtype == MBEDTLS_SSL_MSG_APPLICATION_DATA ) - { - /* - * OpenSSL sends empty messages to randomize the IV - */ - if( ( ret = mbedtls_ssl_read_record( ssl, 1 ) ) != 0 ) - { - if( ret == MBEDTLS_ERR_SSL_CONN_EOF ) - return( 0 ); - - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_read_record", ret ); - return( ret ); - } - } - - if( ssl->in_msgtype == MBEDTLS_SSL_MSG_HANDSHAKE ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "received handshake message" ) ); - - /* - * - For client-side, expect SERVER_HELLO_REQUEST. - * - For server-side, expect CLIENT_HELLO. - * - Fail (TLS) or silently drop record (DTLS) in other cases. - */ - -#if defined(MBEDTLS_SSL_CLI_C) - if( ssl->conf->endpoint == MBEDTLS_SSL_IS_CLIENT && - ( ssl->in_msg[0] != MBEDTLS_SSL_HS_HELLO_REQUEST || - ssl->in_hslen != mbedtls_ssl_hs_hdr_len( ssl ) ) ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "handshake received (not HelloRequest)" ) ); - - /* With DTLS, drop the packet (probably from last handshake) */ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - continue; - } -#endif - return( MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE ); - } -#endif /* MBEDTLS_SSL_CLI_C */ - -#if defined(MBEDTLS_SSL_SRV_C) - if( ssl->conf->endpoint == MBEDTLS_SSL_IS_SERVER && - ssl->in_msg[0] != MBEDTLS_SSL_HS_CLIENT_HELLO ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "handshake received (not ClientHello)" ) ); - - /* With DTLS, drop the packet (probably from last handshake) */ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - continue; - } -#endif - return( MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE ); - } -#endif /* MBEDTLS_SSL_SRV_C */ - -#if defined(MBEDTLS_SSL_RENEGOTIATION) - /* Determine whether renegotiation attempt should be accepted */ - if( ! ( ssl->conf->disable_renegotiation == MBEDTLS_SSL_RENEGOTIATION_DISABLED || - ( ssl->secure_renegotiation == MBEDTLS_SSL_LEGACY_RENEGOTIATION && - ssl->conf->allow_legacy_renegotiation == - MBEDTLS_SSL_LEGACY_NO_RENEGOTIATION ) ) ) - { - /* - * Accept renegotiation request - */ - - /* DTLS clients need to know renego is server-initiated */ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && - ssl->conf->endpoint == MBEDTLS_SSL_IS_CLIENT ) - { - ssl->renego_status = MBEDTLS_SSL_RENEGOTIATION_PENDING; - } -#endif - ret = ssl_start_renegotiation( ssl ); - if( ret != MBEDTLS_ERR_SSL_WAITING_SERVER_HELLO_RENEGO && - ret != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "ssl_start_renegotiation", ret ); - return( ret ); - } - } - else -#endif /* MBEDTLS_SSL_RENEGOTIATION */ - { - /* - * Refuse renegotiation - */ - - MBEDTLS_SSL_DEBUG_MSG( 3, ( "refusing renegotiation, sending alert" ) ); - -#if defined(MBEDTLS_SSL_PROTO_SSL3) - if( ssl->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 ) - { - /* SSLv3 does not have a "no_renegotiation" warning, so - we send a fatal alert and abort the connection. */ - mbedtls_ssl_send_alert_message( ssl, MBEDTLS_SSL_ALERT_LEVEL_FATAL, - MBEDTLS_SSL_ALERT_MSG_UNEXPECTED_MESSAGE ); - return( MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE ); - } - else -#endif /* MBEDTLS_SSL_PROTO_SSL3 */ -#if defined(MBEDTLS_SSL_PROTO_TLS1) || defined(MBEDTLS_SSL_PROTO_TLS1_1) || \ - defined(MBEDTLS_SSL_PROTO_TLS1_2) - if( ssl->minor_ver >= MBEDTLS_SSL_MINOR_VERSION_1 ) - { - if( ( ret = mbedtls_ssl_send_alert_message( ssl, - MBEDTLS_SSL_ALERT_LEVEL_WARNING, - MBEDTLS_SSL_ALERT_MSG_NO_RENEGOTIATION ) ) != 0 ) - { - return( ret ); - } - } - else -#endif /* MBEDTLS_SSL_PROTO_TLS1 || MBEDTLS_SSL_PROTO_TLS1_1 || - MBEDTLS_SSL_PROTO_TLS1_2 */ - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "should never happen" ) ); - return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); - } - } - - /* At this point, we don't know whether the renegotiation has been - * completed or not. The cases to consider are the following: - * 1) The renegotiation is complete. In this case, no new record - * has been read yet. - * 2) The renegotiation is incomplete because the client received - * an application data record while awaiting the ServerHello. - * 3) The renegotiation is incomplete because the client received - * a non-handshake, non-application data message while awaiting - * the ServerHello. - * In each of these case, looping will be the proper action: - * - For 1), the next iteration will read a new record and check - * if it's application data. - * - For 2), the loop condition isn't satisfied as application data - * is present, hence continue is the same as break - * - For 3), the loop condition is satisfied and read_record - * will re-deliver the message that was held back by the client - * when expecting the ServerHello. - */ - continue; - } -#if defined(MBEDTLS_SSL_RENEGOTIATION) - else if( ssl->renego_status == MBEDTLS_SSL_RENEGOTIATION_PENDING ) - { - if( ssl->conf->renego_max_records >= 0 ) - { - if( ++ssl->renego_records_seen > ssl->conf->renego_max_records ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "renegotiation requested, " - "but not honored by client" ) ); - return( MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE ); - } - } - } -#endif /* MBEDTLS_SSL_RENEGOTIATION */ - - /* Fatal and closure alerts handled by mbedtls_ssl_read_record() */ - if( ssl->in_msgtype == MBEDTLS_SSL_MSG_ALERT ) - { - MBEDTLS_SSL_DEBUG_MSG( 2, ( "ignoring non-fatal non-closure alert" ) ); - return( MBEDTLS_ERR_SSL_WANT_READ ); - } - - if( ssl->in_msgtype != MBEDTLS_SSL_MSG_APPLICATION_DATA ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad application data message" ) ); - return( MBEDTLS_ERR_SSL_UNEXPECTED_MESSAGE ); - } - - ssl->in_offt = ssl->in_msg; - - /* We're going to return something now, cancel timer, - * except if handshake (renegotiation) is in progress */ - if( ssl->state == MBEDTLS_SSL_HANDSHAKE_OVER ) - ssl_set_timer( ssl, 0 ); - -#if defined(MBEDTLS_SSL_PROTO_DTLS) - /* If we requested renego but received AppData, resend HelloRequest. - * Do it now, after setting in_offt, to avoid taking this branch - * again if ssl_write_hello_request() returns WANT_WRITE */ -#if defined(MBEDTLS_SSL_SRV_C) && defined(MBEDTLS_SSL_RENEGOTIATION) - if( ssl->conf->endpoint == MBEDTLS_SSL_IS_SERVER && - ssl->renego_status == MBEDTLS_SSL_RENEGOTIATION_PENDING ) - { - if( ( ret = ssl_resend_hello_request( ssl ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "ssl_resend_hello_request", ret ); - return( ret ); - } - } -#endif /* MBEDTLS_SSL_SRV_C && MBEDTLS_SSL_RENEGOTIATION */ -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - } - - n = ( len < ssl->in_msglen ) - ? len : ssl->in_msglen; - - memcpy( buf, ssl->in_offt, n ); - ssl->in_msglen -= n; - - if( ssl->in_msglen == 0 ) - { - /* all bytes consumed */ - ssl->in_offt = NULL; - ssl->keep_current_message = 0; - } - else - { - /* more data available */ - ssl->in_offt += n; - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= read" ) ); - - return( (int) n ); -} - -/* - * Send application data to be encrypted by the SSL layer, taking care of max - * fragment length and buffer size. - * - * According to RFC 5246 Section 6.2.1: - * - * Zero-length fragments of Application data MAY be sent as they are - * potentially useful as a traffic analysis countermeasure. - * - * Therefore, it is possible that the input message length is 0 and the - * corresponding return code is 0 on success. - */ -static int ssl_write_real( mbedtls_ssl_context *ssl, - const unsigned char *buf, size_t len ) -{ - int ret = mbedtls_ssl_get_max_out_record_payload( ssl ); - const size_t max_len = (size_t) ret; - - if( ret < 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_get_max_out_record_payload", ret ); - return( ret ); - } - - if( len > max_len ) - { -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "fragment larger than the (negotiated) " - "maximum fragment length: %d > %d", - len, max_len ) ); - return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - } - else -#endif - len = max_len; - } - - if( ssl->out_left != 0 ) - { - /* - * The user has previously tried to send the data and - * MBEDTLS_ERR_SSL_WANT_WRITE or the message was only partially - * written. In this case, we expect the high-level write function - * (e.g. mbedtls_ssl_write()) to be called with the same parameters - */ - if( ( ret = mbedtls_ssl_flush_output( ssl ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_flush_output", ret ); - return( ret ); - } - } - else - { - /* - * The user is trying to send a message the first time, so we need to - * copy the data into the internal buffers and setup the data structure - * to keep track of partial writes - */ - ssl->out_msglen = len; - ssl->out_msgtype = MBEDTLS_SSL_MSG_APPLICATION_DATA; - memcpy( ssl->out_msg, buf, len ); - - if( ( ret = mbedtls_ssl_write_record( ssl, SSL_FORCE_FLUSH ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_write_record", ret ); - return( ret ); - } - } - - return( (int) len ); -} - -/* - * Write application data, doing 1/n-1 splitting if necessary. - * - * With non-blocking I/O, ssl_write_real() may return WANT_WRITE, - * then the caller will call us again with the same arguments, so - * remember whether we already did the split or not. - */ -#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING) -static int ssl_write_split( mbedtls_ssl_context *ssl, - const unsigned char *buf, size_t len ) -{ - int ret; - - if( ssl->conf->cbc_record_splitting == - MBEDTLS_SSL_CBC_RECORD_SPLITTING_DISABLED || - len <= 1 || - ssl->minor_ver > MBEDTLS_SSL_MINOR_VERSION_1 || - mbedtls_cipher_get_cipher_mode( &ssl->transform_out->cipher_ctx_enc ) - != MBEDTLS_MODE_CBC ) - { - return( ssl_write_real( ssl, buf, len ) ); - } - - if( ssl->split_done == 0 ) - { - if( ( ret = ssl_write_real( ssl, buf, 1 ) ) <= 0 ) - return( ret ); - ssl->split_done = 1; - } - - if( ( ret = ssl_write_real( ssl, buf + 1, len - 1 ) ) <= 0 ) - return( ret ); - ssl->split_done = 0; - - return( ret + 1 ); -} -#endif /* MBEDTLS_SSL_CBC_RECORD_SPLITTING */ - -/* - * Write application data (public-facing wrapper) - */ -int mbedtls_ssl_write( mbedtls_ssl_context *ssl, const unsigned char *buf, size_t len ) -{ - int ret; - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write" ) ); - - if( ssl == NULL || ssl->conf == NULL ) - return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - -#if defined(MBEDTLS_SSL_RENEGOTIATION) - if( ( ret = ssl_check_ctr_renegotiate( ssl ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "ssl_check_ctr_renegotiate", ret ); - return( ret ); - } -#endif - - if( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER ) - { - if( ( ret = mbedtls_ssl_handshake( ssl ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_handshake", ret ); - return( ret ); - } - } - -#if defined(MBEDTLS_SSL_CBC_RECORD_SPLITTING) - ret = ssl_write_split( ssl, buf, len ); -#else - ret = ssl_write_real( ssl, buf, len ); -#endif - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= write" ) ); - - return( ret ); -} - -/* - * Notify the peer that the connection is being closed - */ -int mbedtls_ssl_close_notify( mbedtls_ssl_context *ssl ) -{ - int ret; - - if( ssl == NULL || ssl->conf == NULL ) - return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> write close notify" ) ); - - if( ssl->out_left != 0 ) - return( mbedtls_ssl_flush_output( ssl ) ); - - if( ssl->state == MBEDTLS_SSL_HANDSHAKE_OVER ) - { - if( ( ret = mbedtls_ssl_send_alert_message( ssl, - MBEDTLS_SSL_ALERT_LEVEL_WARNING, - MBEDTLS_SSL_ALERT_MSG_CLOSE_NOTIFY ) ) != 0 ) - { - MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_ssl_send_alert_message", ret ); - return( ret ); - } - } - - MBEDTLS_SSL_DEBUG_MSG( 2, ( "<= write close notify" ) ); - - return( 0 ); -} - -void mbedtls_ssl_transform_free( mbedtls_ssl_transform *transform ) -{ - if( transform == NULL ) - return; - -#if defined(MBEDTLS_ZLIB_SUPPORT) - deflateEnd( &transform->ctx_deflate ); - inflateEnd( &transform->ctx_inflate ); -#endif - - mbedtls_cipher_free( &transform->cipher_ctx_enc ); - mbedtls_cipher_free( &transform->cipher_ctx_dec ); - -#if defined(MBEDTLS_SSL_SOME_MODES_USE_MAC) - mbedtls_md_free( &transform->md_ctx_enc ); - mbedtls_md_free( &transform->md_ctx_dec ); -#endif - - mbedtls_platform_zeroize( transform, sizeof( mbedtls_ssl_transform ) ); -} - #if defined(MBEDTLS_X509_CRT_PARSE_C) static void ssl_key_cert_free( mbedtls_ssl_key_cert *key_cert ) { @@ -11205,42 +5687,6 @@ static void ssl_key_cert_free( mbedtls_ssl_key_cert *key_cert ) } #endif /* MBEDTLS_X509_CRT_PARSE_C */ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - -static void ssl_buffering_free( mbedtls_ssl_context *ssl ) -{ - unsigned offset; - mbedtls_ssl_handshake_params * const hs = ssl->handshake; - - if( hs == NULL ) - return; - - ssl_free_buffered_record( ssl ); - - for( offset = 0; offset < MBEDTLS_SSL_MAX_BUFFERED_HS; offset++ ) - ssl_buffering_free_slot( ssl, offset ); -} - -static void ssl_buffering_free_slot( mbedtls_ssl_context *ssl, - uint8_t slot ) -{ - mbedtls_ssl_handshake_params * const hs = ssl->handshake; - mbedtls_ssl_hs_buffer * const hs_buf = &hs->buffering.hs[slot]; - - if( slot >= MBEDTLS_SSL_MAX_BUFFERED_HS ) - return; - - if( hs_buf->is_valid == 1 ) - { - hs->buffering.total_bytes_buffered -= hs_buf->data_len; - mbedtls_platform_zeroize( hs_buf->data, hs_buf->data_len ); - mbedtls_free( hs_buf->data ); - memset( hs_buf, 0, sizeof( mbedtls_ssl_hs_buffer ) ); - } -} - -#endif /* MBEDTLS_SSL_PROTO_DTLS */ - void mbedtls_ssl_handshake_free( mbedtls_ssl_context *ssl ) { mbedtls_ssl_handshake_params *handshake = ssl->handshake; @@ -11342,8 +5788,8 @@ void mbedtls_ssl_handshake_free( mbedtls_ssl_context *ssl ) #if defined(MBEDTLS_SSL_PROTO_DTLS) mbedtls_free( handshake->verify_cookie ); - ssl_flight_free( handshake->flight ); - ssl_buffering_free( ssl ); + mbedtls_ssl_flight_free( handshake->flight ); + mbedtls_ssl_buffering_free( ssl ); #endif #if defined(MBEDTLS_ECDH_C) && \ @@ -11689,7 +6135,7 @@ int mbedtls_ssl_context_save( mbedtls_ssl_context *ssl, MBEDTLS_SSL_DEBUG_BUF( 4, "saved context", buf, used ); - return( ssl_session_reset_int( ssl, 0 ) ); + return( mbedtls_ssl_session_reset_int( ssl, 0 ) ); } /* @@ -11727,7 +6173,7 @@ static int ssl_context_load( mbedtls_ssl_context *ssl, const unsigned char *p = buf; const unsigned char * const end = buf + len; size_t session_len; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* * The context should have been freshly setup or reset. @@ -11786,7 +6232,7 @@ static int ssl_context_load( mbedtls_ssl_context *ssl, p += 4; /* This has been allocated by ssl_handshake_init(), called by - * by either ssl_session_reset_int() or mbedtls_ssl_setup(). */ + * by either mbedtls_ssl_session_reset_int() or mbedtls_ssl_setup(). */ ssl->session = ssl->session_negotiate; ssl->session_in = ssl->session; ssl->session_out = ssl->session; @@ -11809,7 +6255,7 @@ static int ssl_context_load( mbedtls_ssl_context *ssl, */ /* This has been allocated by ssl_handshake_init(), called by - * by either ssl_session_reset_int() or mbedtls_ssl_setup(). */ + * by either mbedtls_ssl_session_reset_int() or mbedtls_ssl_setup(). */ ssl->transform = ssl->transform_negotiate; ssl->transform_in = ssl->transform; ssl->transform_out = ssl->transform; @@ -11970,7 +6416,7 @@ static int ssl_context_load( mbedtls_ssl_context *ssl, /* Adjust pointers for header fields of outgoing records to * the given transform, accounting for explicit IV and CID. */ - ssl_update_out_pointers( ssl, ssl->transform ); + mbedtls_ssl_update_out_pointers( ssl, ssl->transform ); #if defined(MBEDTLS_SSL_PROTO_DTLS) ssl->in_epoch = 1; @@ -11978,7 +6424,8 @@ static int ssl_context_load( mbedtls_ssl_context *ssl, /* mbedtls_ssl_reset() leaves the handshake sub-structure allocated, * which we don't want - otherwise we'd end up freeing the wrong transform - * by calling ssl_handshake_wrapup_free_hs_transform() inappropriately. */ + * by calling mbedtls_ssl_handshake_wrapup_free_hs_transform() + * inappropriately. */ if( ssl->handshake != NULL ) { mbedtls_ssl_handshake_free( ssl ); @@ -12148,7 +6595,7 @@ int mbedtls_ssl_config_defaults( mbedtls_ssl_config *conf, int endpoint, int transport, int preset ) { #if defined(MBEDTLS_DHM_C) && defined(MBEDTLS_SSL_SRV_C) - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; #endif /* Use the functions here so that they are covered in tests, @@ -12636,59 +7083,6 @@ int mbedtls_ssl_check_cert_usage( const mbedtls_x509_crt *cert, } #endif /* MBEDTLS_X509_CRT_PARSE_C */ -/* - * Convert version numbers to/from wire format - * and, for DTLS, to/from TLS equivalent. - * - * For TLS this is the identity. - * For DTLS, use 1's complement (v -> 255 - v, and then map as follows: - * 1.0 <-> 3.2 (DTLS 1.0 is based on TLS 1.1) - * 1.x <-> 3.x+1 for x != 0 (DTLS 1.2 based on TLS 1.2) - */ -void mbedtls_ssl_write_version( int major, int minor, int transport, - unsigned char ver[2] ) -{ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - if( minor == MBEDTLS_SSL_MINOR_VERSION_2 ) - --minor; /* DTLS 1.0 stored as TLS 1.1 internally */ - - ver[0] = (unsigned char)( 255 - ( major - 2 ) ); - ver[1] = (unsigned char)( 255 - ( minor - 1 ) ); - } - else -#else - ((void) transport); -#endif - { - ver[0] = (unsigned char) major; - ver[1] = (unsigned char) minor; - } -} - -void mbedtls_ssl_read_version( int *major, int *minor, int transport, - const unsigned char ver[2] ) -{ -#if defined(MBEDTLS_SSL_PROTO_DTLS) - if( transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM ) - { - *major = 255 - ver[0] + 2; - *minor = 255 - ver[1] + 1; - - if( *minor == MBEDTLS_SSL_MINOR_VERSION_1 ) - ++*minor; /* DTLS 1.0 stored as TLS 1.1 internally */ - } - else -#else - ((void) transport); -#endif - { - *major = ver[0]; - *minor = ver[1]; - } -} - int mbedtls_ssl_set_calc_verify_md( mbedtls_ssl_context *ssl, int md ) { #if defined(MBEDTLS_SSL_PROTO_TLS1_2) diff --git a/features/mbedtls/src/x509.c b/features/mbedtls/src/x509.c index 2e0b0e8f6c..7f8181be27 100644 --- a/features/mbedtls/src/x509.c +++ b/features/mbedtls/src/x509.c @@ -39,6 +39,7 @@ #include "mbedtls/x509.h" #include "mbedtls/asn1.h" +#include "mbedtls/error.h" #include "mbedtls/oid.h" #include @@ -83,7 +84,7 @@ int mbedtls_x509_get_serial( unsigned char **p, const unsigned char *end, mbedtls_x509_buf *serial ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( end - *p ) < 1 ) return( MBEDTLS_ERR_X509_INVALID_SERIAL + @@ -114,7 +115,7 @@ int mbedtls_x509_get_serial( unsigned char **p, const unsigned char *end, int mbedtls_x509_get_alg_null( unsigned char **p, const unsigned char *end, mbedtls_x509_buf *alg ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = mbedtls_asn1_get_alg_null( p, end, alg ) ) != 0 ) return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); @@ -128,7 +129,7 @@ int mbedtls_x509_get_alg_null( unsigned char **p, const unsigned char *end, int mbedtls_x509_get_alg( unsigned char **p, const unsigned char *end, mbedtls_x509_buf *alg, mbedtls_x509_buf *params ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = mbedtls_asn1_get_alg( p, end, alg, params ) ) != 0 ) return( MBEDTLS_ERR_X509_INVALID_ALG + ret ); @@ -148,7 +149,7 @@ int mbedtls_x509_get_alg( unsigned char **p, const unsigned char *end, */ static int x509_get_hash_alg( const mbedtls_x509_buf *alg, mbedtls_md_type_t *md_alg ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *p; const unsigned char *end; mbedtls_x509_buf md_oid; @@ -209,7 +210,7 @@ int mbedtls_x509_get_rsassa_pss_params( const mbedtls_x509_buf *params, mbedtls_md_type_t *md_alg, mbedtls_md_type_t *mgf_md, int *salt_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *p; const unsigned char *end, *end2; size_t len; @@ -352,7 +353,7 @@ static int x509_get_attr_type_value( unsigned char **p, const unsigned char *end, mbedtls_x509_name *cur ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; mbedtls_x509_buf *oid; mbedtls_x509_buf *val; @@ -433,7 +434,7 @@ static int x509_get_attr_type_value( unsigned char **p, int mbedtls_x509_get_name( unsigned char **p, const unsigned char *end, mbedtls_x509_name *cur ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t set_len; const unsigned char *end_set; @@ -539,7 +540,7 @@ static int x509_date_is_valid(const mbedtls_x509_time *t ) static int x509_parse_time( unsigned char **p, size_t len, size_t yearlen, mbedtls_x509_time *tm ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* * Minimum length is 10 or 12 depending on yearlen @@ -604,7 +605,7 @@ static int x509_parse_time( unsigned char **p, size_t len, size_t yearlen, int mbedtls_x509_get_time( unsigned char **p, const unsigned char *end, mbedtls_x509_time *tm ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len, year_len; unsigned char tag; @@ -633,7 +634,7 @@ int mbedtls_x509_get_time( unsigned char **p, const unsigned char *end, int mbedtls_x509_get_sig( unsigned char **p, const unsigned char *end, mbedtls_x509_buf *sig ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; int tag_type; @@ -662,7 +663,7 @@ int mbedtls_x509_get_sig_alg( const mbedtls_x509_buf *sig_oid, const mbedtls_x50 mbedtls_md_type_t *md_alg, mbedtls_pk_type_t *pk_alg, void **sig_opts ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( *sig_opts != NULL ) return( MBEDTLS_ERR_X509_BAD_INPUT_DATA ); @@ -710,7 +711,7 @@ int mbedtls_x509_get_sig_alg( const mbedtls_x509_buf *sig_oid, const mbedtls_x50 int mbedtls_x509_get_ext( unsigned char **p, const unsigned char *end, mbedtls_x509_buf *ext, int tag ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; /* Extension structure use EXPLICIT tagging. That is, the actual @@ -745,7 +746,7 @@ int mbedtls_x509_get_ext( unsigned char **p, const unsigned char *end, */ int mbedtls_x509_dn_gets( char *buf, size_t size, const mbedtls_x509_name *dn ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i, n; unsigned char c, merge = 0; const mbedtls_x509_name *name; @@ -807,7 +808,7 @@ int mbedtls_x509_dn_gets( char *buf, size_t size, const mbedtls_x509_name *dn ) */ int mbedtls_x509_serial_gets( char *buf, size_t size, const mbedtls_x509_buf *serial ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i, n, nr; char *p; @@ -843,7 +844,7 @@ int mbedtls_x509_sig_alg_gets( char *buf, size_t size, const mbedtls_x509_buf *s mbedtls_pk_type_t pk_alg, mbedtls_md_type_t md_alg, const void *sig_opts ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; char *p = buf; size_t n = size; const char *desc = NULL; @@ -888,7 +889,7 @@ int mbedtls_x509_key_size_helper( char *buf, size_t buf_size, const char *name ) { char *p = buf; size_t n = buf_size; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ret = mbedtls_snprintf( p, n, "%s key size", name ); MBEDTLS_X509_SAFE_SNPRINTF; diff --git a/features/mbedtls/src/x509_create.c b/features/mbedtls/src/x509_create.c index 546e8fa1a9..7df2f0ed56 100644 --- a/features/mbedtls/src/x509_create.c +++ b/features/mbedtls/src/x509_create.c @@ -29,6 +29,7 @@ #include "mbedtls/x509.h" #include "mbedtls/asn1write.h" +#include "mbedtls/error.h" #include "mbedtls/oid.h" #include @@ -241,7 +242,7 @@ int mbedtls_x509_set_extension( mbedtls_asn1_named_data **head, const char *oid, */ static int x509_write_name( unsigned char **p, unsigned char *start, mbedtls_asn1_named_data* cur_name) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; const char *oid = (const char*)cur_name->oid.p; size_t oid_len = cur_name->oid.len; @@ -274,7 +275,7 @@ static int x509_write_name( unsigned char **p, unsigned char *start, mbedtls_asn int mbedtls_x509_write_names( unsigned char **p, unsigned char *start, mbedtls_asn1_named_data *first ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; mbedtls_asn1_named_data *cur = first; @@ -295,7 +296,7 @@ int mbedtls_x509_write_sig( unsigned char **p, unsigned char *start, const char *oid, size_t oid_len, unsigned char *sig, size_t size ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; if( *p < start || (size_t)( *p - start ) < size ) @@ -325,7 +326,7 @@ int mbedtls_x509_write_sig( unsigned char **p, unsigned char *start, static int x509_write_extension( unsigned char **p, unsigned char *start, mbedtls_asn1_named_data *ext ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_raw_buffer( p, start, ext->val.p + 1, @@ -363,7 +364,7 @@ static int x509_write_extension( unsigned char **p, unsigned char *start, int mbedtls_x509_write_extensions( unsigned char **p, unsigned char *start, mbedtls_asn1_named_data *first ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; mbedtls_asn1_named_data *cur_ext = first; diff --git a/features/mbedtls/src/x509_crl.c b/features/mbedtls/src/x509_crl.c index 00f8545d7c..371c446be5 100644 --- a/features/mbedtls/src/x509_crl.c +++ b/features/mbedtls/src/x509_crl.c @@ -38,6 +38,7 @@ #if defined(MBEDTLS_X509_CRL_PARSE_C) #include "mbedtls/x509_crl.h" +#include "mbedtls/error.h" #include "mbedtls/oid.h" #include "mbedtls/platform_util.h" @@ -74,7 +75,7 @@ static int x509_crl_get_version( unsigned char **p, const unsigned char *end, int *ver ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = mbedtls_asn1_get_int( p, end, ver ) ) != 0 ) { @@ -101,7 +102,7 @@ static int x509_get_crl_ext( unsigned char **p, const unsigned char *end, mbedtls_x509_buf *ext ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( *p == end ) return( 0 ); @@ -181,7 +182,7 @@ static int x509_get_crl_entry_ext( unsigned char **p, const unsigned char *end, mbedtls_x509_buf *ext ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; /* OPTIONAL */ @@ -235,7 +236,7 @@ static int x509_get_entries( unsigned char **p, const unsigned char *end, mbedtls_x509_crl_entry *entry ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t entry_len; mbedtls_x509_crl_entry *cur_entry = entry; @@ -300,7 +301,7 @@ static int x509_get_entries( unsigned char **p, int mbedtls_x509_crl_parse_der( mbedtls_x509_crl *chain, const unsigned char *buf, size_t buflen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; unsigned char *p = NULL, *end = NULL; mbedtls_x509_buf sig_params1, sig_params2, sig_oid2; @@ -539,8 +540,8 @@ int mbedtls_x509_crl_parse_der( mbedtls_x509_crl *chain, int mbedtls_x509_crl_parse( mbedtls_x509_crl *chain, const unsigned char *buf, size_t buflen ) { #if defined(MBEDTLS_PEM_PARSE_C) - int ret; - size_t use_len; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t use_len = 0; mbedtls_pem_context pem; int is_pem = 0; @@ -603,7 +604,7 @@ int mbedtls_x509_crl_parse( mbedtls_x509_crl *chain, const unsigned char *buf, s */ int mbedtls_x509_crl_parse_file( mbedtls_x509_crl *chain, const char *path ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n; unsigned char *buf; @@ -630,7 +631,7 @@ int mbedtls_x509_crl_parse_file( mbedtls_x509_crl *chain, const char *path ) int mbedtls_x509_crl_info( char *buf, size_t size, const char *prefix, const mbedtls_x509_crl *crl ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n; char *p; const mbedtls_x509_crl_entry *entry; diff --git a/features/mbedtls/src/x509_crt.c b/features/mbedtls/src/x509_crt.c index 48f244e2e8..1e472303b1 100644 --- a/features/mbedtls/src/x509_crt.c +++ b/features/mbedtls/src/x509_crt.c @@ -40,6 +40,7 @@ #if defined(MBEDTLS_X509_CRT_PARSE_C) #include "mbedtls/x509_crt.h" +#include "mbedtls/error.h" #include "mbedtls/oid.h" #include "mbedtls/platform_util.h" @@ -390,7 +391,7 @@ static int x509_get_version( unsigned char **p, const unsigned char *end, int *ver ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; if( ( ret = mbedtls_asn1_get_tag( p, end, &len, @@ -427,7 +428,7 @@ static int x509_get_dates( unsigned char **p, mbedtls_x509_time *from, mbedtls_x509_time *to ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; if( ( ret = mbedtls_asn1_get_tag( p, end, &len, @@ -456,7 +457,7 @@ static int x509_get_uid( unsigned char **p, const unsigned char *end, mbedtls_x509_buf *uid, int n ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( *p == end ) return( 0 ); @@ -483,7 +484,7 @@ static int x509_get_basic_constraints( unsigned char **p, int *ca_istrue, int *max_pathlen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; /* @@ -532,7 +533,7 @@ static int x509_get_ns_cert_type( unsigned char **p, const unsigned char *end, unsigned char *ns_cert_type) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_x509_bitstring bs = { 0, 0, NULL }; if( ( ret = mbedtls_asn1_get_bitstring( p, end, &bs ) ) != 0 ) @@ -551,7 +552,7 @@ static int x509_get_key_usage( unsigned char **p, const unsigned char *end, unsigned int *key_usage) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i; mbedtls_x509_bitstring bs = { 0, 0, NULL }; @@ -581,7 +582,7 @@ static int x509_get_ext_key_usage( unsigned char **p, const unsigned char *end, mbedtls_x509_sequence *ext_key_usage) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = mbedtls_asn1_get_sequence_of( p, end, ext_key_usage, MBEDTLS_ASN1_OID ) ) != 0 ) return( MBEDTLS_ERR_X509_INVALID_EXTENSIONS + ret ); @@ -625,7 +626,7 @@ static int x509_get_subject_alt_name( unsigned char **p, const unsigned char *end, mbedtls_x509_sequence *subject_alt_name ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len, tag_len; mbedtls_asn1_buf *buf; unsigned char tag; @@ -887,7 +888,7 @@ static int x509_get_crt_ext( unsigned char **p, const unsigned char *end, mbedtls_x509_crt *crt ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; unsigned char *end_ext_data, *end_ext_octet; @@ -1056,7 +1057,7 @@ static int x509_crt_parse_der_core( mbedtls_x509_crt *crt, size_t buflen, int make_copy ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; unsigned char *p, *end, *crt_end; mbedtls_x509_buf sig_params1, sig_params2, sig_oid2; @@ -1318,7 +1319,7 @@ static int mbedtls_x509_crt_parse_der_internal( mbedtls_x509_crt *chain, size_t buflen, int make_copy ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_x509_crt *crt = chain, *prev = NULL; /* @@ -1415,7 +1416,7 @@ int mbedtls_x509_crt_parse( mbedtls_x509_crt *chain, #if defined(MBEDTLS_PEM_PARSE_C) if( buf_format == MBEDTLS_X509_FORMAT_PEM ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_pem_context pem; /* 1 rather than 0 since the terminating NULL byte is counted in */ @@ -1499,7 +1500,7 @@ int mbedtls_x509_crt_parse( mbedtls_x509_crt *chain, */ int mbedtls_x509_crt_parse_file( mbedtls_x509_crt *chain, const char *path ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n; unsigned char *buf; @@ -1737,7 +1738,7 @@ static int x509_info_subject_alt_name( char **buf, size_t *size, *subject_alt_name, const char *prefix ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n = *size; char *p = *buf; const mbedtls_x509_sequence *cur = subject_alt_name; @@ -1848,7 +1849,7 @@ static int x509_info_subject_alt_name( char **buf, size_t *size, int mbedtls_x509_parse_subject_alt_name( const mbedtls_x509_buf *san_buf, mbedtls_x509_subject_alternative_name *san ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; switch( san_buf->tag & ( MBEDTLS_ASN1_TAG_CLASS_MASK | MBEDTLS_ASN1_TAG_VALUE_MASK ) ) @@ -1909,7 +1910,7 @@ int mbedtls_x509_parse_subject_alt_name( const mbedtls_x509_buf *san_buf, static int x509_info_cert_type( char **buf, size_t *size, unsigned char ns_cert_type ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n = *size; char *p = *buf; const char *sep = ""; @@ -1936,7 +1937,7 @@ static int x509_info_cert_type( char **buf, size_t *size, static int x509_info_key_usage( char **buf, size_t *size, unsigned int key_usage ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n = *size; char *p = *buf; const char *sep = ""; @@ -1960,7 +1961,7 @@ static int x509_info_key_usage( char **buf, size_t *size, static int x509_info_ext_key_usage( char **buf, size_t *size, const mbedtls_x509_sequence *extended_key_usage ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const char *desc; size_t n = *size; char *p = *buf; @@ -1989,7 +1990,7 @@ static int x509_info_ext_key_usage( char **buf, size_t *size, static int x509_info_cert_policies( char **buf, size_t *size, const mbedtls_x509_sequence *certificate_policies ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const char *desc; size_t n = *size; char *p = *buf; @@ -2023,7 +2024,7 @@ static int x509_info_cert_policies( char **buf, size_t *size, int mbedtls_x509_crt_info( char *buf, size_t size, const char *prefix, const mbedtls_x509_crt *crt ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n; char *p; char key_size_str[BEFORE_COLON]; @@ -2195,7 +2196,7 @@ static const struct x509_crt_verify_string x509_crt_verify_strings[] = { int mbedtls_x509_crt_verify_info( char *buf, size_t size, const char *prefix, uint32_t flags ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const struct x509_crt_verify_string *cur; char *p = buf; size_t n = size; @@ -2535,9 +2536,9 @@ static int x509_crt_find_parent_in( unsigned self_cnt, mbedtls_x509_crt_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_x509_crt *parent, *fallback_parent; - int signature_is_good, fallback_signature_is_good; + int signature_is_good = 0, fallback_signature_is_good; #if defined(MBEDTLS_ECDSA_C) && defined(MBEDTLS_ECP_RESTARTABLE) /* did we have something in progress? */ @@ -2658,7 +2659,7 @@ static int x509_crt_find_parent( unsigned self_cnt, mbedtls_x509_crt_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_x509_crt *search_list; *parent_is_trusted = 1; @@ -2791,7 +2792,7 @@ static int x509_crt_verify_chain( { /* Don't initialize any of those variables here, so that the compiler can * catch potential issues with jumping ahead when restarting */ - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; uint32_t *flags; mbedtls_x509_crt_verify_chain_item *cur; mbedtls_x509_crt *child; @@ -3020,7 +3021,7 @@ static int x509_crt_merge_flags_with_cb( int (*f_vrfy)(void *, mbedtls_x509_crt *, int, uint32_t *), void *p_vrfy ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned i; uint32_t cur_flags; const mbedtls_x509_crt_verify_chain_item *cur; @@ -3068,7 +3069,7 @@ static int x509_crt_verify_restartable_ca_cb( mbedtls_x509_crt *crt, void *p_vrfy, mbedtls_x509_crt_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_pk_type_t pk_type; mbedtls_x509_crt_verify_chain ver_chain; uint32_t ee_flags; diff --git a/features/mbedtls/src/x509_csr.c b/features/mbedtls/src/x509_csr.c index c8c08c87b2..7e2cfba2ae 100644 --- a/features/mbedtls/src/x509_csr.c +++ b/features/mbedtls/src/x509_csr.c @@ -38,6 +38,7 @@ #if defined(MBEDTLS_X509_CSR_PARSE_C) #include "mbedtls/x509_csr.h" +#include "mbedtls/error.h" #include "mbedtls/oid.h" #include "mbedtls/platform_util.h" @@ -68,7 +69,7 @@ static int x509_csr_get_version( unsigned char **p, const unsigned char *end, int *ver ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = mbedtls_asn1_get_int( p, end, ver ) ) != 0 ) { @@ -90,7 +91,7 @@ static int x509_csr_get_version( unsigned char **p, int mbedtls_x509_csr_parse_der( mbedtls_x509_csr *csr, const unsigned char *buf, size_t buflen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; unsigned char *p, *end; mbedtls_x509_buf sig_params; @@ -262,7 +263,7 @@ int mbedtls_x509_csr_parse_der( mbedtls_x509_csr *csr, int mbedtls_x509_csr_parse( mbedtls_x509_csr *csr, const unsigned char *buf, size_t buflen ) { #if defined(MBEDTLS_PEM_PARSE_C) - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t use_len; mbedtls_pem_context pem; #endif @@ -312,7 +313,7 @@ int mbedtls_x509_csr_parse( mbedtls_x509_csr *csr, const unsigned char *buf, siz */ int mbedtls_x509_csr_parse_file( mbedtls_x509_csr *csr, const char *path ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n; unsigned char *buf; @@ -336,7 +337,7 @@ int mbedtls_x509_csr_parse_file( mbedtls_x509_csr *csr, const char *path ) int mbedtls_x509_csr_info( char *buf, size_t size, const char *prefix, const mbedtls_x509_csr *csr ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n; char *p; char key_size_str[BEFORE_COLON]; diff --git a/features/mbedtls/src/x509write_crt.c b/features/mbedtls/src/x509write_crt.c index 03fb3fd945..5947e439de 100644 --- a/features/mbedtls/src/x509write_crt.c +++ b/features/mbedtls/src/x509write_crt.c @@ -34,10 +34,11 @@ #if defined(MBEDTLS_X509_CRT_WRITE_C) #include "mbedtls/x509_crt.h" -#include "mbedtls/oid.h" #include "mbedtls/asn1write.h" -#include "mbedtls/sha1.h" +#include "mbedtls/error.h" +#include "mbedtls/oid.h" #include "mbedtls/platform_util.h" +#include "mbedtls/sha1.h" #include @@ -45,16 +46,6 @@ #include "mbedtls/pem.h" #endif /* MBEDTLS_PEM_WRITE_C */ -/* - * For the currently used signature algorithms the buffer to store any signature - * must be at least of size MAX(MBEDTLS_ECDSA_MAX_LEN, MBEDTLS_MPI_MAX_SIZE) - */ -#if MBEDTLS_ECDSA_MAX_LEN > MBEDTLS_MPI_MAX_SIZE -#define SIGNATURE_MAX_SIZE MBEDTLS_ECDSA_MAX_LEN -#else -#define SIGNATURE_MAX_SIZE MBEDTLS_MPI_MAX_SIZE -#endif - void mbedtls_x509write_crt_init( mbedtls_x509write_cert *ctx ) { memset( ctx, 0, sizeof( mbedtls_x509write_cert ) ); @@ -113,7 +104,7 @@ int mbedtls_x509write_crt_set_issuer_name( mbedtls_x509write_cert *ctx, int mbedtls_x509write_crt_set_serial( mbedtls_x509write_cert *ctx, const mbedtls_mpi *serial ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = mbedtls_mpi_copy( &ctx->serial, serial ) ) != 0 ) return( ret ); @@ -150,7 +141,7 @@ int mbedtls_x509write_crt_set_extension( mbedtls_x509write_cert *ctx, int mbedtls_x509write_crt_set_basic_constraints( mbedtls_x509write_cert *ctx, int is_ca, int max_pathlen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char buf[9]; unsigned char *c = buf + sizeof(buf); size_t len = 0; @@ -184,7 +175,7 @@ int mbedtls_x509write_crt_set_basic_constraints( mbedtls_x509write_cert *ctx, #if defined(MBEDTLS_SHA1_C) int mbedtls_x509write_crt_set_subject_key_identifier( mbedtls_x509write_cert *ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char buf[MBEDTLS_MPI_MAX_SIZE * 2 + 20]; /* tag, length + 2xMPI */ unsigned char *c = buf + sizeof(buf); size_t len = 0; @@ -212,7 +203,7 @@ int mbedtls_x509write_crt_set_subject_key_identifier( mbedtls_x509write_cert *ct int mbedtls_x509write_crt_set_authority_key_identifier( mbedtls_x509write_cert *ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char buf[MBEDTLS_MPI_MAX_SIZE * 2 + 20]; /* tag, length + 2xMPI */ unsigned char *c = buf + sizeof( buf ); size_t len = 0; @@ -250,7 +241,7 @@ int mbedtls_x509write_crt_set_key_usage( mbedtls_x509write_cert *ctx, { unsigned char buf[5], ku[2]; unsigned char *c; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const unsigned int allowed_bits = MBEDTLS_X509_KU_DIGITAL_SIGNATURE | MBEDTLS_X509_KU_NON_REPUDIATION | MBEDTLS_X509_KU_KEY_ENCIPHERMENT | @@ -289,7 +280,7 @@ int mbedtls_x509write_crt_set_ns_cert_type( mbedtls_x509write_cert *ctx, { unsigned char buf[4]; unsigned char *c; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; c = buf + 4; @@ -309,7 +300,7 @@ int mbedtls_x509write_crt_set_ns_cert_type( mbedtls_x509write_cert *ctx, static int x509_write_time( unsigned char **p, unsigned char *start, const char *t, size_t size ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; /* @@ -342,12 +333,12 @@ int mbedtls_x509write_crt_der( mbedtls_x509write_cert *ctx, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const char *sig_oid; size_t sig_oid_len = 0; unsigned char *c, *c2; unsigned char hash[64]; - unsigned char sig[SIGNATURE_MAX_SIZE]; + unsigned char sig[MBEDTLS_PK_SIGNATURE_MAX_SIZE]; size_t sub_len = 0, pub_len = 0, sig_and_oid_len = 0, sig_len; size_t len = 0; mbedtls_pk_type_t pk_alg; @@ -536,7 +527,7 @@ int mbedtls_x509write_crt_pem( mbedtls_x509write_cert *crt, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t olen; if( ( ret = mbedtls_x509write_crt_der( crt, buf, size, diff --git a/features/mbedtls/src/x509write_csr.c b/features/mbedtls/src/x509write_csr.c index 0d62d1d485..7c5179862c 100644 --- a/features/mbedtls/src/x509write_csr.c +++ b/features/mbedtls/src/x509write_csr.c @@ -33,8 +33,9 @@ #if defined(MBEDTLS_X509_CSR_WRITE_C) #include "mbedtls/x509_csr.h" -#include "mbedtls/oid.h" #include "mbedtls/asn1write.h" +#include "mbedtls/error.h" +#include "mbedtls/oid.h" #include "mbedtls/platform_util.h" #if defined(MBEDTLS_USE_PSA_CRYPTO) @@ -49,16 +50,6 @@ #include "mbedtls/pem.h" #endif -/* - * For the currently used signature algorithms the buffer to store any signature - * must be at least of size MAX(MBEDTLS_ECDSA_MAX_LEN, MBEDTLS_MPI_MAX_SIZE) - */ -#if MBEDTLS_ECDSA_MAX_LEN > MBEDTLS_MPI_MAX_SIZE -#define SIGNATURE_MAX_SIZE MBEDTLS_ECDSA_MAX_LEN -#else -#define SIGNATURE_MAX_SIZE MBEDTLS_MPI_MAX_SIZE -#endif - void mbedtls_x509write_csr_init( mbedtls_x509write_csr *ctx ) { memset( ctx, 0, sizeof( mbedtls_x509write_csr ) ); @@ -100,7 +91,7 @@ int mbedtls_x509write_csr_set_key_usage( mbedtls_x509write_csr *ctx, unsigned ch { unsigned char buf[4]; unsigned char *c; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; c = buf + 4; @@ -122,7 +113,7 @@ int mbedtls_x509write_csr_set_ns_cert_type( mbedtls_x509write_csr *ctx, { unsigned char buf[4]; unsigned char *c; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; c = buf + 4; @@ -143,12 +134,12 @@ int mbedtls_x509write_csr_der( mbedtls_x509write_csr *ctx, unsigned char *buf, s int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const char *sig_oid; size_t sig_oid_len = 0; unsigned char *c, *c2; unsigned char hash[64]; - unsigned char sig[SIGNATURE_MAX_SIZE]; + unsigned char sig[MBEDTLS_PK_SIGNATURE_MAX_SIZE]; unsigned char tmp_buf[2048]; size_t pub_len = 0, sig_and_oid_len = 0, sig_len; size_t len = 0; @@ -223,7 +214,9 @@ int mbedtls_x509write_csr_der( mbedtls_x509write_csr *ctx, unsigned char *buf, s return( MBEDTLS_ERR_X509_FATAL_ERROR ); } #else /* MBEDTLS_USE_PSA_CRYPTO */ - mbedtls_md( mbedtls_md_info_from_type( ctx->md_alg ), c, len, hash ); + ret = mbedtls_md( mbedtls_md_info_from_type( ctx->md_alg ), c, len, hash ); + if( ret != 0 ) + return( ret ); #endif if( ( ret = mbedtls_pk_sign( ctx->key, ctx->md_alg, hash, 0, sig, &sig_len, f_rng, p_rng ) ) != 0 ) @@ -273,18 +266,17 @@ int mbedtls_x509write_csr_pem( mbedtls_x509write_csr *ctx, unsigned char *buf, s int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; - unsigned char output_buf[4096]; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t olen = 0; - if( ( ret = mbedtls_x509write_csr_der( ctx, output_buf, sizeof(output_buf), + if( ( ret = mbedtls_x509write_csr_der( ctx, buf, size, f_rng, p_rng ) ) < 0 ) { return( ret ); } if( ( ret = mbedtls_pem_write_buffer( PEM_BEGIN_CSR, PEM_END_CSR, - output_buf + sizeof(output_buf) - ret, + buf + size - ret, ret, buf, size, &olen ) ) != 0 ) { return( ret ); From 8eef39b8f1d802e80830d14a06369d1929cc3e3c Mon Sep 17 00:00:00 2001 From: Jaeden Amero Date: Tue, 7 Apr 2020 10:11:16 +0100 Subject: [PATCH 39/49] crypto: Upgrade to Mbed Crypto 3.1.0 --- features/mbedtls/mbed-crypto/VERSION.txt | 2 +- .../mbedtls/mbed-crypto/importer/Makefile | 4 +- .../mbedtls/mbed-crypto/inc/mbedtls/asn1.h | 166 +++++++- .../mbed-crypto/inc/mbedtls/asn1write.h | 15 + .../mbedtls/mbed-crypto/inc/mbedtls/bignum.h | 20 +- .../mbed-crypto/inc/mbedtls/ctr_drbg.h | 187 +++++---- .../mbed-crypto/inc/mbedtls/hmac_drbg.h | 19 +- .../mbed-crypto/inc/mbedtls/md_internal.h | 2 + features/mbedtls/mbed-crypto/inc/mbedtls/pk.h | 76 +++- .../mbed-crypto/inc/mbedtls/psa_util.h | 210 ++++------ .../mbedtls/mbed-crypto/inc/mbedtls/rsa.h | 9 +- .../mbedtls/mbed-crypto/inc/mbedtls/sha512.h | 18 +- features/mbedtls/mbed-crypto/inc/psa/crypto.h | 40 +- .../mbed-crypto/inc/psa/crypto_compat.h | 196 ++++++++++ .../mbed-crypto/inc/psa/crypto_extra.h | 71 +++- .../mbed-crypto/inc/psa/crypto_sizes.h | 80 +--- .../mbed-crypto/inc/psa/crypto_types.h | 74 +--- .../mbed-crypto/inc/psa/crypto_values.h | 230 ++++++----- .../COMPONENT_NSPE/crypto_struct.h | 4 +- .../COMPONENT_PSA_SRV_IMPL/psa_crypto.c | 366 ++++++++++++------ .../psa_crypto_storage.c | 15 +- .../COMPONENT_SPE/crypto_struct_spe.h | 9 +- features/mbedtls/mbed-crypto/src/aes.c | 31 +- features/mbedtls/mbed-crypto/src/asn1parse.c | 186 ++++++--- features/mbedtls/mbed-crypto/src/asn1write.c | 33 +- features/mbedtls/mbed-crypto/src/bignum.c | 167 ++++++-- features/mbedtls/mbed-crypto/src/ccm.c | 9 +- features/mbedtls/mbed-crypto/src/chacha20.c | 5 +- features/mbedtls/mbed-crypto/src/chachapoly.c | 15 +- features/mbedtls/mbed-crypto/src/cipher.c | 27 +- .../mbedtls/mbed-crypto/src/cipher_wrap.c | 3 +- features/mbedtls/mbed-crypto/src/cmac.c | 13 +- features/mbedtls/mbed-crypto/src/ctr_drbg.c | 251 +++++++----- features/mbedtls/mbed-crypto/src/dhm.c | 15 +- features/mbedtls/mbed-crypto/src/ecdh.c | 21 +- features/mbedtls/mbed-crypto/src/ecdsa.c | 20 +- features/mbedtls/mbed-crypto/src/ecjpake.c | 33 +- features/mbedtls/mbed-crypto/src/ecp.c | 77 ++-- features/mbedtls/mbed-crypto/src/ecp_curves.c | 19 +- features/mbedtls/mbed-crypto/src/entropy.c | 23 +- .../mbedtls/mbed-crypto/src/entropy_poll.c | 3 +- features/mbedtls/mbed-crypto/src/gcm.c | 13 +- features/mbedtls/mbed-crypto/src/hkdf.c | 3 +- features/mbedtls/mbed-crypto/src/hmac_drbg.c | 40 +- features/mbedtls/mbed-crypto/src/md.c | 35 +- features/mbedtls/mbed-crypto/src/md2.c | 7 +- features/mbedtls/mbed-crypto/src/md4.c | 7 +- features/mbedtls/mbed-crypto/src/md5.c | 7 +- features/mbedtls/mbed-crypto/src/nist_kw.c | 3 +- features/mbedtls/mbed-crypto/src/oid.c | 3 +- features/mbedtls/mbed-crypto/src/pem.c | 11 +- features/mbedtls/mbed-crypto/src/pk.c | 18 +- features/mbedtls/mbed-crypto/src/pk_wrap.c | 53 +-- features/mbedtls/mbed-crypto/src/pkcs12.c | 7 +- features/mbedtls/mbed-crypto/src/pkcs5.c | 3 +- features/mbedtls/mbed-crypto/src/pkparse.c | 149 ++++--- features/mbedtls/mbed-crypto/src/pkwrite.c | 48 ++- features/mbedtls/mbed-crypto/src/platform.c | 5 +- features/mbedtls/mbed-crypto/src/poly1305.c | 5 +- features/mbedtls/mbed-crypto/src/ripemd160.c | 7 +- features/mbedtls/mbed-crypto/src/rsa.c | 40 +- features/mbedtls/mbed-crypto/src/sha1.c | 7 +- features/mbedtls/mbed-crypto/src/sha256.c | 7 +- features/mbedtls/mbed-crypto/src/sha512.c | 37 +- 64 files changed, 2141 insertions(+), 1138 deletions(-) create mode 100644 features/mbedtls/mbed-crypto/inc/psa/crypto_compat.h diff --git a/features/mbedtls/mbed-crypto/VERSION.txt b/features/mbedtls/mbed-crypto/VERSION.txt index 20ff92fea1..1a81f64d1d 100644 --- a/features/mbedtls/mbed-crypto/VERSION.txt +++ b/features/mbedtls/mbed-crypto/VERSION.txt @@ -1 +1 @@ -mbedcrypto-2.1.0d0 +mbedcrypto-3.1.0 diff --git a/features/mbedtls/mbed-crypto/importer/Makefile b/features/mbedtls/mbed-crypto/importer/Makefile index 74b65784ce..2c44e78e2a 100644 --- a/features/mbedtls/mbed-crypto/importer/Makefile +++ b/features/mbedtls/mbed-crypto/importer/Makefile @@ -29,8 +29,8 @@ # Set the Mbed Crypto release to import (this can/should be edited before # import) -CRYPTO_RELEASE ?= mbedcrypto-2.1.0d0 -CRYPTO_REPO_URL ?= git@github.com:ARMmbed/mbedtls-psa.git +CRYPTO_RELEASE ?= mbedcrypto-3.1.0 +CRYPTO_REPO_URL ?= git@github.com:ARMmbed/mbed-crypto.git # Translate between Mbed Crypto namespace and Mbed OS namespace TARGET_PREFIX:=.. diff --git a/features/mbedtls/mbed-crypto/inc/mbedtls/asn1.h b/features/mbedtls/mbed-crypto/inc/mbedtls/asn1.h index 1a76111684..33b30041a6 100644 --- a/features/mbedtls/mbed-crypto/inc/mbedtls/asn1.h +++ b/features/mbedtls/mbed-crypto/inc/mbedtls/asn1.h @@ -75,6 +75,7 @@ #define MBEDTLS_ASN1_OCTET_STRING 0x04 #define MBEDTLS_ASN1_NULL 0x05 #define MBEDTLS_ASN1_OID 0x06 +#define MBEDTLS_ASN1_ENUMERATED 0x0A #define MBEDTLS_ASN1_UTF8_STRING 0x0C #define MBEDTLS_ASN1_SEQUENCE 0x10 #define MBEDTLS_ASN1_SET 0x11 @@ -89,6 +90,18 @@ #define MBEDTLS_ASN1_CONSTRUCTED 0x20 #define MBEDTLS_ASN1_CONTEXT_SPECIFIC 0x80 +/* Slightly smaller way to check if tag is a string tag + * compared to canonical implementation. */ +#define MBEDTLS_ASN1_IS_STRING_TAG( tag ) \ + ( ( tag ) < 32u && ( \ + ( ( 1u << ( tag ) ) & ( ( 1u << MBEDTLS_ASN1_BMP_STRING ) | \ + ( 1u << MBEDTLS_ASN1_UTF8_STRING ) | \ + ( 1u << MBEDTLS_ASN1_T61_STRING ) | \ + ( 1u << MBEDTLS_ASN1_IA5_STRING ) | \ + ( 1u << MBEDTLS_ASN1_UNIVERSAL_STRING ) | \ + ( 1u << MBEDTLS_ASN1_PRINTABLE_STRING ) | \ + ( 1u << MBEDTLS_ASN1_BIT_STRING ) ) ) != 0 ) ) + /* * Bit masks for each of the components of an ASN.1 tag as specified in * ITU X.690 (08/2015), section 8.1 "General rules for encoding", @@ -119,6 +132,10 @@ ( ( MBEDTLS_OID_SIZE(oid_str) != (oid_buf)->len ) || \ memcmp( (oid_str), (oid_buf)->p, (oid_buf)->len) != 0 ) +#define MBEDTLS_OID_CMP_RAW(oid_str, oid_buf, oid_buf_len) \ + ( ( MBEDTLS_OID_SIZE(oid_str) != (oid_buf_len) ) || \ + memcmp( (oid_str), (oid_buf), (oid_buf_len) ) != 0 ) + #ifdef __cplusplus extern "C" { #endif @@ -254,13 +271,32 @@ int mbedtls_asn1_get_bool( unsigned char **p, * a valid ASN.1 INTEGER. * \return #MBEDTLS_ERR_ASN1_INVALID_LENGTH if the parsed value does * not fit in an \c int. - * \return An ASN.1 error code if the input does not start with - * a valid ASN.1 INTEGER. */ int mbedtls_asn1_get_int( unsigned char **p, const unsigned char *end, int *val ); +/** + * \brief Retrieve an enumerated ASN.1 tag and its value. + * Updates the pointer to immediately behind the full tag. + * + * \param p On entry, \c *p points to the start of the ASN.1 element. + * On successful completion, \c *p points to the first byte + * beyond the ASN.1 element. + * On error, the value of \c *p is undefined. + * \param end End of data. + * \param val On success, the parsed value. + * + * \return 0 if successful. + * \return An ASN.1 error code if the input does not start with + * a valid ASN.1 ENUMERATED. + * \return #MBEDTLS_ERR_ASN1_INVALID_LENGTH if the parsed value does + * not fit in an \c int. + */ +int mbedtls_asn1_get_enum( unsigned char **p, + const unsigned char *end, + int *val ); + /** * \brief Retrieve a bitstring ASN.1 tag and its value. * Updates the pointer to immediately behind the full tag. @@ -307,6 +343,9 @@ int mbedtls_asn1_get_bitstring_null( unsigned char **p, * \brief Parses and splits an ASN.1 "SEQUENCE OF ". * Updates the pointer to immediately behind the full sequence tag. * + * This function allocates memory for the sequence elements. You can free + * the allocated memory with mbedtls_asn1_sequence_free(). + * * \note On error, this function may return a partial list in \p cur. * You must set `cur->next = NULL` before calling this function! * Otherwise it is impossible to distinguish a previously non-null @@ -340,14 +379,133 @@ int mbedtls_asn1_get_bitstring_null( unsigned char **p, * \return 0 if successful. * \return #MBEDTLS_ERR_ASN1_LENGTH_MISMATCH if the input contains * extra data after a valid SEQUENCE OF \p tag. + * \return #MBEDTLS_ERR_ASN1_UNEXPECTED_TAG if the input starts with + * an ASN.1 SEQUENCE in which an element has a tag that + * is different from \p tag. * \return #MBEDTLS_ERR_ASN1_ALLOC_FAILED if a memory allocation failed. * \return An ASN.1 error code if the input does not start with - * a valid ASN.1 BIT STRING. + * a valid ASN.1 SEQUENCE. */ int mbedtls_asn1_get_sequence_of( unsigned char **p, const unsigned char *end, mbedtls_asn1_sequence *cur, int tag ); +/** + * \brief Free a heap-allocated linked list presentation of + * an ASN.1 sequence, including the first element. + * + * There are two common ways to manage the memory used for the representation + * of a parsed ASN.1 sequence: + * - Allocate a head node `mbedtls_asn1_sequence *head` with mbedtls_calloc(). + * Pass this node as the `cur` argument to mbedtls_asn1_get_sequence_of(). + * When you have finished processing the sequence, + * call mbedtls_asn1_sequence_free() on `head`. + * - Allocate a head node `mbedtls_asn1_sequence *head` in any manner, + * for example on the stack. Make sure that `head->next == NULL`. + * Pass `head` as the `cur` argument to mbedtls_asn1_get_sequence_of(). + * When you have finished processing the sequence, + * call mbedtls_asn1_sequence_free() on `head->cur`, + * then free `head` itself in the appropriate manner. + * + * \param seq The address of the first sequence component. This may + * be \c NULL, in which case this functions returns + * immediately. + */ +void mbedtls_asn1_sequence_free( mbedtls_asn1_sequence *seq ); + +/** + * \brief Traverse an ASN.1 SEQUENCE container and + * call a callback for each entry. + * + * This function checks that the input is a SEQUENCE of elements that + * each have a "must" tag, and calls a callback function on the elements + * that have a "may" tag. + * + * For example, to validate that the input is a SEQUENCE of `tag1` and call + * `cb` on each element, use + * ``` + * mbedtls_asn1_traverse_sequence_of(&p, end, 0xff, tag1, 0, 0, cb, ctx); + * ``` + * + * To validate that the input is a SEQUENCE of ANY and call `cb` on + * each element, use + * ``` + * mbedtls_asn1_traverse_sequence_of(&p, end, 0, 0, 0, 0, cb, ctx); + * ``` + * + * To validate that the input is a SEQUENCE of CHOICE {NULL, OCTET STRING} + * and call `cb` on each element that is an OCTET STRING, use + * ``` + * mbedtls_asn1_traverse_sequence_of(&p, end, 0xfe, 0x04, 0xff, 0x04, cb, ctx); + * ``` + * + * The callback is called on the elements with a "may" tag from left to + * right. If the input is not a valid SEQUENCE of elements with a "must" tag, + * the callback is called on the elements up to the leftmost point where + * the input is invalid. + * + * \warning This function is still experimental and may change + * at any time. + * + * \param p The address of the pointer to the beginning of + * the ASN.1 SEQUENCE header. This is updated to + * point to the end of the ASN.1 SEQUENCE container + * on a successful invocation. + * \param end The end of the ASN.1 SEQUENCE container. + * \param tag_must_mask A mask to be applied to the ASN.1 tags found within + * the SEQUENCE before comparing to \p tag_must_value. + * \param tag_must_val The required value of each ASN.1 tag found in the + * SEQUENCE, after masking with \p tag_must_mask. + * Mismatching tags lead to an error. + * For example, a value of \c 0 for both \p tag_must_mask + * and \p tag_must_val means that every tag is allowed, + * while a value of \c 0xFF for \p tag_must_mask means + * that \p tag_must_val is the only allowed tag. + * \param tag_may_mask A mask to be applied to the ASN.1 tags found within + * the SEQUENCE before comparing to \p tag_may_value. + * \param tag_may_val The desired value of each ASN.1 tag found in the + * SEQUENCE, after masking with \p tag_may_mask. + * Mismatching tags will be silently ignored. + * For example, a value of \c 0 for \p tag_may_mask and + * \p tag_may_val means that any tag will be considered, + * while a value of \c 0xFF for \p tag_may_mask means + * that all tags with value different from \p tag_may_val + * will be ignored. + * \param cb The callback to trigger for each component + * in the ASN.1 SEQUENCE that matches \p tag_may_val. + * The callback function is called with the following + * parameters: + * - \p ctx. + * - The tag of the current element. + * - A pointer to the start of the current element's + * content inside the input. + * - The length of the content of the current element. + * If the callback returns a non-zero value, + * the function stops immediately, + * forwarding the callback's return value. + * \param ctx The context to be passed to the callback \p cb. + * + * \return \c 0 if successful the entire ASN.1 SEQUENCE + * was traversed without parsing or callback errors. + * \return #MBEDTLS_ERR_ASN1_LENGTH_MISMATCH if the input + * contains extra data after a valid SEQUENCE + * of elements with an accepted tag. + * \return #MBEDTLS_ERR_ASN1_UNEXPECTED_TAG if the input starts + * with an ASN.1 SEQUENCE in which an element has a tag + * that is not accepted. + * \return An ASN.1 error code if the input does not start with + * a valid ASN.1 SEQUENCE. + * \return A non-zero error code forwarded from the callback + * \p cb in case the latter returns a non-zero value. + */ +int mbedtls_asn1_traverse_sequence_of( + unsigned char **p, + const unsigned char *end, + unsigned char tag_must_mask, unsigned char tag_must_val, + unsigned char tag_may_mask, unsigned char tag_may_val, + int (*cb)( void *ctx, int tag, + unsigned char* start, size_t len ), + void *ctx ); #if defined(MBEDTLS_BIGNUM_C) /** @@ -367,8 +525,6 @@ int mbedtls_asn1_get_sequence_of( unsigned char **p, * \return #MBEDTLS_ERR_ASN1_INVALID_LENGTH if the parsed value does * not fit in an \c int. * \return An MPI error code if the parsed value is too large. - * \return An ASN.1 error code if the input does not start with - * a valid ASN.1 INTEGER. */ int mbedtls_asn1_get_mpi( unsigned char **p, const unsigned char *end, diff --git a/features/mbedtls/mbed-crypto/inc/mbedtls/asn1write.h b/features/mbedtls/mbed-crypto/inc/mbedtls/asn1write.h index 982414626e..0bce28ed13 100644 --- a/features/mbedtls/mbed-crypto/inc/mbedtls/asn1write.h +++ b/features/mbedtls/mbed-crypto/inc/mbedtls/asn1write.h @@ -192,6 +192,21 @@ int mbedtls_asn1_write_bool( unsigned char **p, unsigned char *start, */ int mbedtls_asn1_write_int( unsigned char **p, unsigned char *start, int val ); +/** + * \brief Write an enum tag (#MBEDTLS_ASN1_ENUMERATED) and value + * in ASN.1 format. + * + * \note This function works backwards in data buffer. + * + * \param p The reference to the current position pointer. + * \param start The start of the buffer, for bounds-checking. + * \param val The integer value to write. + * + * \return The number of bytes written to \p p on success. + * \return A negative \c MBEDTLS_ERR_ASN1_XXX error code on failure. + */ +int mbedtls_asn1_write_enum( unsigned char **p, unsigned char *start, int val ); + /** * \brief Write a string in ASN.1 format using a specific * string encoding tag. diff --git a/features/mbedtls/mbed-crypto/inc/mbedtls/bignum.h b/features/mbedtls/mbed-crypto/inc/mbedtls/bignum.h index 2c5ace6901..1d00c560a6 100644 --- a/features/mbedtls/mbed-crypto/inc/mbedtls/bignum.h +++ b/features/mbedtls/mbed-crypto/inc/mbedtls/bignum.h @@ -185,7 +185,7 @@ extern "C" { */ typedef struct mbedtls_mpi { - int s; /*!< integer sign */ + int s; /*!< Sign: -1 if the mpi is negative, 1 otherwise */ size_t n; /*!< total # of limbs */ mbedtls_mpi_uint *p; /*!< pointer to limbs */ } @@ -594,6 +594,24 @@ int mbedtls_mpi_cmp_abs( const mbedtls_mpi *X, const mbedtls_mpi *Y ); */ int mbedtls_mpi_cmp_mpi( const mbedtls_mpi *X, const mbedtls_mpi *Y ); +/** + * \brief Check if an MPI is less than the other in constant time. + * + * \param X The left-hand MPI. This must point to an initialized MPI + * with the same allocated length as Y. + * \param Y The right-hand MPI. This must point to an initialized MPI + * with the same allocated length as X. + * \param ret The result of the comparison: + * \c 1 if \p X is less than \p Y. + * \c 0 if \p X is greater than or equal to \p Y. + * + * \return 0 on success. + * \return MBEDTLS_ERR_MPI_BAD_INPUT_DATA if the allocated length of + * the two input MPIs is not the same. + */ +int mbedtls_mpi_lt_mpi_ct( const mbedtls_mpi *X, const mbedtls_mpi *Y, + unsigned *ret ); + /** * \brief Compare an MPI with an integer. * diff --git a/features/mbedtls/mbed-crypto/inc/mbedtls/ctr_drbg.h b/features/mbedtls/mbed-crypto/inc/mbedtls/ctr_drbg.h index 2db4021336..234e6a0364 100644 --- a/features/mbedtls/mbed-crypto/inc/mbedtls/ctr_drbg.h +++ b/features/mbedtls/mbed-crypto/inc/mbedtls/ctr_drbg.h @@ -12,30 +12,14 @@ * The Mbed TLS implementation of CTR_DRBG uses AES-256 (default) or AES-128 * (if \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY is enabled at compile time) * as the underlying block cipher, with a derivation function. - * The initial seeding grabs #MBEDTLS_CTR_DRBG_ENTROPY_LEN bytes of entropy. - * See the documentation of mbedtls_ctr_drbg_seed() for more details. * - * Based on NIST SP 800-90A §10.2.1 table 3 and NIST SP 800-57 part 1 table 2, - * here are the security strengths achieved in typical configuration: - * - 256 bits under the default configuration of the library, with AES-256 - * and with #MBEDTLS_CTR_DRBG_ENTROPY_LEN set to 48 or more. - * - 256 bits if AES-256 is used, #MBEDTLS_CTR_DRBG_ENTROPY_LEN is set - * to 32 or more, and the DRBG is initialized with an explicit - * nonce in the \c custom parameter to mbedtls_ctr_drbg_seed(). - * - 128 bits if AES-256 is used but #MBEDTLS_CTR_DRBG_ENTROPY_LEN is - * between 24 and 47 and the DRBG is not initialized with an explicit - * nonce (see mbedtls_ctr_drbg_seed()). - * - 128 bits if AES-128 is used (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY enabled) - * and #MBEDTLS_CTR_DRBG_ENTROPY_LEN is set to 24 or more (which is - * always the case unless it is explicitly set to a different value - * in config.h). - * - * Note that the value of #MBEDTLS_CTR_DRBG_ENTROPY_LEN defaults to: - * - \c 48 if the module \c MBEDTLS_SHA512_C is enabled and the symbol - * \c MBEDTLS_ENTROPY_FORCE_SHA256 is disabled at compile time. - * This is the default configuration of the library. - * - \c 32 if the module \c MBEDTLS_SHA512_C is disabled at compile time. - * - \c 32 if \c MBEDTLS_ENTROPY_FORCE_SHA256 is enabled at compile time. + * The security strength as defined in NIST SP 800-90A is + * 128 bits when AES-128 is used (\c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY enabled) + * and 256 bits otherwise, provided that #MBEDTLS_CTR_DRBG_ENTROPY_LEN is + * kept at its default value (and not overridden in config.h) and that the + * DRBG instance is set up with default parameters. + * See the documentation of mbedtls_ctr_drbg_seed() for more + * information. */ /* * Copyright (C) 2006-2019, Arm Limited (or its affiliates), All Rights Reserved @@ -163,20 +147,49 @@ extern "C" { #endif +#if MBEDTLS_CTR_DRBG_ENTROPY_LEN >= MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 +/** The default length of the nonce read from the entropy source. + * + * This is \c 0 because a single read from the entropy source is sufficient + * to include a nonce. + * See the documentation of mbedtls_ctr_drbg_seed() for more information. + */ +#define MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN 0 +#else +/** The default length of the nonce read from the entropy source. + * + * This is half of the default entropy length because a single read from + * the entropy source does not provide enough material to form a nonce. + * See the documentation of mbedtls_ctr_drbg_seed() for more information. + */ +#define MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN ( MBEDTLS_CTR_DRBG_ENTROPY_LEN + 1 ) / 2 +#endif + /** * \brief The CTR_DRBG context structure. */ typedef struct mbedtls_ctr_drbg_context { unsigned char counter[16]; /*!< The counter (V). */ - int reseed_counter; /*!< The reseed counter. */ + int reseed_counter; /*!< The reseed counter. + * This is the number of requests that have + * been made since the last (re)seeding, + * minus one. + * Before the initial seeding, this field + * contains the amount of entropy in bytes + * to use as a nonce for the initial seeding, + * or -1 if no nonce length has been explicitly + * set (see mbedtls_ctr_drbg_set_nonce_len()). + */ int prediction_resistance; /*!< This determines whether prediction resistance is enabled, that is whether to systematically reseed before each random generation. */ size_t entropy_len; /*!< The amount of entropy grabbed on each - seed or reseed operation. */ - int reseed_interval; /*!< The reseed interval. */ + seed or reseed operation, in bytes. */ + int reseed_interval; /*!< The reseed interval. + * This is the maximum number of requests + * that can be made between reseedings. */ mbedtls_aes_context aes_ctx; /*!< The AES context. */ @@ -214,47 +227,71 @@ void mbedtls_ctr_drbg_init( mbedtls_ctr_drbg_context *ctx ); * with mbedtls_entropy_init() (which registers the platform's default * entropy sources). * - * \p f_entropy is always called with a buffer size equal to the entropy - * length. The entropy length is initially #MBEDTLS_CTR_DRBG_ENTROPY_LEN - * and this value is always used for the initial seeding. You can change - * the entropy length for subsequent seeding by calling - * mbedtls_ctr_drbg_set_entropy_len() after this function. + * The entropy length is #MBEDTLS_CTR_DRBG_ENTROPY_LEN by default. + * You can override it by calling mbedtls_ctr_drbg_set_entropy_len(). * - * You can provide a personalization string in addition to the + * The entropy nonce length is: + * - \c 0 if the entropy length is at least 3/2 times the entropy length, + * which guarantees that the security strength is the maximum permitted + * by the key size and entropy length according to NIST SP 800-90A §10.2.1; + * - Half the entropy length otherwise. + * You can override it by calling mbedtls_ctr_drbg_set_nonce_len(). + * With the default entropy length, the entropy nonce length is + * #MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN. + * + * You can provide a nonce and personalization string in addition to the * entropy source, to make this instantiation as unique as possible. + * See SP 800-90A §8.6.7 for more details about nonces. * - * \note The _seed_material_ value passed to the derivation - * function in the CTR_DRBG Instantiate Process - * described in NIST SP 800-90A §10.2.1.3.2 - * is the concatenation of the string obtained from - * calling \p f_entropy and the \p custom string. - * The origin of the nonce depends on the value of - * the entropy length relative to the security strength. - * - If the entropy length is at least 1.5 times the - * security strength then the nonce is taken from the - * string obtained with \p f_entropy. - * - If the entropy length is less than the security - * strength, then the nonce is taken from \p custom. - * In this case, for compliance with SP 800-90A, - * you must pass a unique value of \p custom at - * each invocation. See SP 800-90A §8.6.7 for more - * details. + * The _seed_material_ value passed to the derivation function in + * the CTR_DRBG Instantiate Process described in NIST SP 800-90A §10.2.1.3.2 + * is the concatenation of the following strings: + * - A string obtained by calling \p f_entropy function for the entropy + * length. */ -#if MBEDTLS_CTR_DRBG_ENTROPY_LEN < MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 -/** \warning When #MBEDTLS_CTR_DRBG_ENTROPY_LEN is less than - * #MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2, to achieve the - * maximum security strength permitted by CTR_DRBG, - * you must pass a value of \p custom that is a nonce: - * this value must never be repeated in subsequent - * runs of the same application or on a different - * device. +#if MBEDTLS_CTR_DRBG_ENTROPY_NONCE_LEN == 0 +/** + * - If mbedtls_ctr_drbg_set_nonce_len() has been called, a string + * obtained by calling \p f_entropy function for the specified length. + */ +#else +/** + * - A string obtained by calling \p f_entropy function for the entropy nonce + * length. If the entropy nonce length is \c 0, this function does not + * make a second call to \p f_entropy. */ #endif /** + * - The \p custom string. + * + * \note To achieve the nominal security strength permitted + * by CTR_DRBG, the entropy length must be: + * - at least 16 bytes for a 128-bit strength + * (maximum achievable strength when using AES-128); + * - at least 32 bytes for a 256-bit strength + * (maximum achievable strength when using AES-256). + * + * In addition, if you do not pass a nonce in \p custom, + * the sum of the entropy length + * and the entropy nonce length must be: + * - at least 24 bytes for a 128-bit strength + * (maximum achievable strength when using AES-128); + * - at least 48 bytes for a 256-bit strength + * (maximum achievable strength when using AES-256). + * * \param ctx The CTR_DRBG context to seed. + * It must have been initialized with + * mbedtls_ctr_drbg_init(). + * After a successful call to mbedtls_ctr_drbg_seed(), + * you may not call mbedtls_ctr_drbg_seed() again on + * the same context unless you call + * mbedtls_ctr_drbg_free() and mbedtls_ctr_drbg_init() + * again first. * \param f_entropy The entropy callback, taking as arguments the * \p p_entropy context, the buffer to fill, and the * length of the buffer. + * \p f_entropy is always called with a buffer size + * less than or equal to the entropy length. * \param p_entropy The entropy context to pass to \p f_entropy. * \param custom The personalization string. * This can be \c NULL, in which case the personalization @@ -298,15 +335,10 @@ void mbedtls_ctr_drbg_set_prediction_resistance( mbedtls_ctr_drbg_context *ctx, /** * \brief This function sets the amount of entropy grabbed on each - * subsequent reseed. + * seed or reseed. * * The default value is #MBEDTLS_CTR_DRBG_ENTROPY_LEN. * - * \note mbedtls_ctr_drbg_seed() always sets the entropy length - * to #MBEDTLS_CTR_DRBG_ENTROPY_LEN, so this function - * only has an effect when it is called after - * mbedtls_ctr_drbg_seed(). - * * \note The security strength of CTR_DRBG is bounded by the * entropy length. Thus: * - When using AES-256 @@ -321,11 +353,35 @@ void mbedtls_ctr_drbg_set_prediction_resistance( mbedtls_ctr_drbg_context *ctx, * * \param ctx The CTR_DRBG context. * \param len The amount of entropy to grab, in bytes. - * This must be at most #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. + * This must be at most #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT + * and at most the maximum length accepted by the + * entropy function that is set in the context. */ void mbedtls_ctr_drbg_set_entropy_len( mbedtls_ctr_drbg_context *ctx, size_t len ); +/** + * \brief This function sets the amount of entropy grabbed + * as a nonce for the initial seeding. + * + * Call this function before calling mbedtls_ctr_drbg_seed() to read + * a nonce from the entropy source during the initial seeding. + * + * \param ctx The CTR_DRBG context. + * \param len The amount of entropy to grab for the nonce, in bytes. + * This must be at most #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT + * and at most the maximum length accepted by the + * entropy function that is set in the context. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG if \p len is + * more than #MBEDTLS_CTR_DRBG_MAX_SEED_INPUT. + * \return #MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED + * if the initial seeding has already taken place. + */ +int mbedtls_ctr_drbg_set_nonce_len( mbedtls_ctr_drbg_context *ctx, + size_t len ); + /** * \brief This function sets the reseed interval. * @@ -499,11 +555,6 @@ int mbedtls_ctr_drbg_self_test( int verbose ); #endif /* MBEDTLS_SELF_TEST */ -/* Internal functions (do not call directly) */ -int mbedtls_ctr_drbg_seed_entropy_len( mbedtls_ctr_drbg_context *, - int (*)(void *, unsigned char *, size_t), void *, - const unsigned char *, size_t, size_t ); - #ifdef __cplusplus } #endif diff --git a/features/mbedtls/mbed-crypto/inc/mbedtls/hmac_drbg.h b/features/mbedtls/mbed-crypto/inc/mbedtls/hmac_drbg.h index 519d692fba..00be9df408 100644 --- a/features/mbedtls/mbed-crypto/inc/mbedtls/hmac_drbg.h +++ b/features/mbedtls/mbed-crypto/inc/mbedtls/hmac_drbg.h @@ -139,13 +139,11 @@ void mbedtls_hmac_drbg_init( mbedtls_hmac_drbg_context *ctx ); * Note that SHA-256 is just as efficient as SHA-224. * The security strength can be reduced if a smaller * entropy length is set with - * mbedtls_hmac_drbg_set_entropy_len() afterwards. + * mbedtls_hmac_drbg_set_entropy_len(). * - * \note The entropy length for the initial seeding is - * the security strength (converted from bits to bytes). - * You can set a different entropy length for subsequent - * seeding by calling mbedtls_hmac_drbg_set_entropy_len() - * after this function. + * \note The default entropy length is the security strength + * (converted from bits to bytes). You can override + * it by calling mbedtls_hmac_drbg_set_entropy_len(). * * \note During the initial seeding, this function calls * the entropy source to obtain a nonce @@ -224,14 +222,9 @@ void mbedtls_hmac_drbg_set_prediction_resistance( mbedtls_hmac_drbg_context *ctx /** * \brief This function sets the amount of entropy grabbed on each - * reseed. + * seed or reseed. * - * The default value is set by mbedtls_hmac_drbg_seed(). - * - * \note mbedtls_hmac_drbg_seed() always sets the entropy length - * to the default value based on the chosen MD algorithm, - * so this function only has an effect if it is called - * after mbedtls_hmac_drbg_seed(). + * See the documentation of mbedtls_hmac_drbg_seed() for the default value. * * \param ctx The HMAC_DRBG context. * \param len The amount of entropy to grab, in bytes. diff --git a/features/mbedtls/mbed-crypto/inc/mbedtls/md_internal.h b/features/mbedtls/mbed-crypto/inc/mbedtls/md_internal.h index bb876efc5b..0922dff9d3 100644 --- a/features/mbedtls/mbed-crypto/inc/mbedtls/md_internal.h +++ b/features/mbedtls/mbed-crypto/inc/mbedtls/md_internal.h @@ -79,7 +79,9 @@ extern const mbedtls_md_info_t mbedtls_sha224_info; extern const mbedtls_md_info_t mbedtls_sha256_info; #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) extern const mbedtls_md_info_t mbedtls_sha384_info; +#endif extern const mbedtls_md_info_t mbedtls_sha512_info; #endif diff --git a/features/mbedtls/mbed-crypto/inc/mbedtls/pk.h b/features/mbedtls/mbed-crypto/inc/mbedtls/pk.h index d750004d56..99e7a55a1d 100644 --- a/features/mbedtls/mbed-crypto/inc/mbedtls/pk.h +++ b/features/mbedtls/mbed-crypto/inc/mbedtls/pk.h @@ -101,6 +101,58 @@ typedef struct mbedtls_pk_rsassa_pss_options } mbedtls_pk_rsassa_pss_options; +/** + * \brief Maximum size of a signature made by mbedtls_pk_sign(). + */ +/* We need to set MBEDTLS_PK_SIGNATURE_MAX_SIZE to the maximum signature + * size among the supported signature types. Do it by starting at 0, + * then incrementally increasing to be large enough for each supported + * signature mechanism. + * + * The resulting value can be 0, for example if MBEDTLS_ECDH_C is enabled + * (which allows the pk module to be included) but neither MBEDTLS_ECDSA_C + * nor MBEDTLS_RSA_C nor any opaque signature mechanism (PSA or RSA_ALT). + */ +#define MBEDTLS_PK_SIGNATURE_MAX_SIZE 0 + +#if ( defined(MBEDTLS_RSA_C) || defined(MBEDTLS_PK_RSA_ALT_SUPPORT) ) && \ + MBEDTLS_MPI_MAX_SIZE > MBEDTLS_PK_SIGNATURE_MAX_SIZE +/* For RSA, the signature can be as large as the bignum module allows. + * For RSA_ALT, the signature size is not necessarily tied to what the + * bignum module can do, but in the absence of any specific setting, + * we use that (rsa_alt_sign_wrap in pk_wrap will check). */ +#undef MBEDTLS_PK_SIGNATURE_MAX_SIZE +#define MBEDTLS_PK_SIGNATURE_MAX_SIZE MBEDTLS_MPI_MAX_SIZE +#endif + +#if defined(MBEDTLS_ECDSA_C) && \ + MBEDTLS_ECDSA_MAX_LEN > MBEDTLS_PK_SIGNATURE_MAX_SIZE +/* For ECDSA, the ecdsa module exports a constant for the maximum + * signature size. */ +#undef MBEDTLS_PK_SIGNATURE_MAX_SIZE +#define MBEDTLS_PK_SIGNATURE_MAX_SIZE MBEDTLS_ECDSA_MAX_LEN +#endif + +#if defined(MBEDTLS_USE_PSA_CRYPTO) +#if PSA_SIGNATURE_MAX_SIZE > MBEDTLS_PK_SIGNATURE_MAX_SIZE +/* PSA_SIGNATURE_MAX_SIZE is the maximum size of a signature made + * through the PSA API in the PSA representation. */ +#undef MBEDTLS_PK_SIGNATURE_MAX_SIZE +#define MBEDTLS_PK_SIGNATURE_MAX_SIZE PSA_SIGNATURE_MAX_SIZE +#endif + +#if PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE + 11 > MBEDTLS_PK_SIGNATURE_MAX_SIZE +/* The Mbed TLS representation is different for ECDSA signatures: + * PSA uses the raw concatenation of r and s, + * whereas Mbed TLS uses the ASN.1 representation (SEQUENCE of two INTEGERs). + * Add the overhead of ASN.1: up to (1+2) + 2 * (1+2+1) for the + * types, lengths (represented by up to 2 bytes), and potential leading + * zeros of the INTEGERs and the SEQUENCE. */ +#undef MBEDTLS_PK_SIGNATURE_MAX_SIZE +#define MBEDTLS_PK_SIGNATURE_MAX_SIZE ( PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE + 11 ) +#endif +#endif /* defined(MBEDTLS_USE_PSA_CRYPTO) */ + /** * \brief Types for interfacing with the debug module */ @@ -442,8 +494,13 @@ int mbedtls_pk_verify_ext( mbedtls_pk_type_t type, const void *options, * \param md_alg Hash algorithm used (see notes) * \param hash Hash of the message to sign * \param hash_len Hash length or 0 (see notes) - * \param sig Place to write the signature - * \param sig_len Number of bytes written + * \param sig Place to write the signature. + * It must have enough room for the signature. + * #MBEDTLS_PK_SIGNATURE_MAX_SIZE is always enough. + * You may use a smaller buffer if it is large enough + * given the key type. + * \param sig_len On successful return, + * the number of bytes written to \p sig. * \param f_rng RNG function * \param p_rng RNG parameter * @@ -474,16 +531,21 @@ int mbedtls_pk_sign( mbedtls_pk_context *ctx, mbedtls_md_type_t md_alg, * * \param ctx The PK context to use. It must have been set up * with a private key. - * \param md_alg Hash algorithm used (see notes) + * \param md_alg Hash algorithm used (see notes for mbedtls_pk_sign()) * \param hash Hash of the message to sign - * \param hash_len Hash length or 0 (see notes) - * \param sig Place to write the signature - * \param sig_len Number of bytes written + * \param hash_len Hash length or 0 (see notes for mbedtls_pk_sign()) + * \param sig Place to write the signature. + * It must have enough room for the signature. + * #MBEDTLS_PK_SIGNATURE_MAX_SIZE is always enough. + * You may use a smaller buffer if it is large enough + * given the key type. + * \param sig_len On successful return, + * the number of bytes written to \p sig. * \param f_rng RNG function * \param p_rng RNG parameter * \param rs_ctx Restart context (NULL to disable restart) * - * \return See \c mbedtls_pk_sign(), or + * \return See \c mbedtls_pk_sign(). * \return #MBEDTLS_ERR_ECP_IN_PROGRESS if maximum number of * operations was reached: see \c mbedtls_ecp_set_max_ops(). */ diff --git a/features/mbedtls/mbed-crypto/inc/mbedtls/psa_util.h b/features/mbedtls/mbed-crypto/inc/mbedtls/psa_util.h index 8d18fcc57e..513bc5feb7 100644 --- a/features/mbedtls/mbed-crypto/inc/mbedtls/psa_util.h +++ b/features/mbedtls/mbed-crypto/inc/mbedtls/psa_util.h @@ -160,79 +160,96 @@ static inline psa_algorithm_t mbedtls_psa_translate_md( mbedtls_md_type_t md_alg /* Translations for ECC. */ static inline int mbedtls_psa_get_ecc_oid_from_id( - psa_ecc_curve_t curve, char const **oid, size_t *oid_len ) + psa_ecc_curve_t curve, size_t bits, + char const **oid, size_t *oid_len ) { switch( curve ) { + case PSA_ECC_CURVE_SECP_R1: + switch( bits ) + { #if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) - case PSA_ECC_CURVE_SECP192R1: - *oid = MBEDTLS_OID_EC_GRP_SECP192R1; - *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP192R1 ); - return( 0 ); + case 192: + *oid = MBEDTLS_OID_EC_GRP_SECP192R1; + *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP192R1 ); + return( 0 ); #endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ #if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) - case PSA_ECC_CURVE_SECP224R1: - *oid = MBEDTLS_OID_EC_GRP_SECP224R1; - *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP224R1 ); - return( 0 ); + case 224: + *oid = MBEDTLS_OID_EC_GRP_SECP224R1; + *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP224R1 ); + return( 0 ); #endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ #if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) - case PSA_ECC_CURVE_SECP256R1: - *oid = MBEDTLS_OID_EC_GRP_SECP256R1; - *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP256R1 ); - return( 0 ); + case 256: + *oid = MBEDTLS_OID_EC_GRP_SECP256R1; + *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP256R1 ); + return( 0 ); #endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) - case PSA_ECC_CURVE_SECP384R1: - *oid = MBEDTLS_OID_EC_GRP_SECP384R1; - *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP384R1 ); - return( 0 ); + case 384: + *oid = MBEDTLS_OID_EC_GRP_SECP384R1; + *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP384R1 ); + return( 0 ); #endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ #if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) - case PSA_ECC_CURVE_SECP521R1: - *oid = MBEDTLS_OID_EC_GRP_SECP521R1; - *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP521R1 ); - return( 0 ); + case 521: + *oid = MBEDTLS_OID_EC_GRP_SECP521R1; + *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP521R1 ); + return( 0 ); #endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + } + break; + case PSA_ECC_CURVE_SECP_K1: + switch( bits ) + { #if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) - case PSA_ECC_CURVE_SECP192K1: - *oid = MBEDTLS_OID_EC_GRP_SECP192K1; - *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP192K1 ); - return( 0 ); + case 192: + *oid = MBEDTLS_OID_EC_GRP_SECP192K1; + *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP192K1 ); + return( 0 ); #endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ #if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) - case PSA_ECC_CURVE_SECP224K1: - *oid = MBEDTLS_OID_EC_GRP_SECP224K1; - *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP224K1 ); - return( 0 ); + case 224: + *oid = MBEDTLS_OID_EC_GRP_SECP224K1; + *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP224K1 ); + return( 0 ); #endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ #if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) - case PSA_ECC_CURVE_SECP256K1: - *oid = MBEDTLS_OID_EC_GRP_SECP256K1; - *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP256K1 ); - return( 0 ); + case 256: + *oid = MBEDTLS_OID_EC_GRP_SECP256K1; + *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_SECP256K1 ); + return( 0 ); #endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + } + break; + case PSA_ECC_CURVE_BRAINPOOL_P_R1: + switch( bits ) + { #if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) - case PSA_ECC_CURVE_BRAINPOOL_P256R1: - *oid = MBEDTLS_OID_EC_GRP_BP256R1; - *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_BP256R1 ); - return( 0 ); + case 256: + *oid = MBEDTLS_OID_EC_GRP_BP256R1; + *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_BP256R1 ); + return( 0 ); #endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ #if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) - case PSA_ECC_CURVE_BRAINPOOL_P384R1: - *oid = MBEDTLS_OID_EC_GRP_BP384R1; - *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_BP384R1 ); - return( 0 ); + case 384: + *oid = MBEDTLS_OID_EC_GRP_BP384R1; + *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_BP384R1 ); + return( 0 ); #endif /* MBEDTLS_ECP_DP_BP384R1_ENABLED */ #if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) - case PSA_ECC_CURVE_BRAINPOOL_P512R1: - *oid = MBEDTLS_OID_EC_GRP_BP512R1; - *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_BP512R1 ); - return( 0 ); + case 512: + *oid = MBEDTLS_OID_EC_GRP_BP512R1; + *oid_len = MBEDTLS_OID_SIZE( MBEDTLS_OID_EC_GRP_BP512R1 ); + return( 0 ); #endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ + } + break; } - - return( -1 ); + (void) oid; + (void) oid_len; + return( -1 ); } #define MBEDTLS_PSA_MAX_EC_PUBKEY_LENGTH 1 @@ -315,85 +332,6 @@ static inline int mbedtls_psa_get_ecc_oid_from_id( #endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ -static inline psa_ecc_curve_t mbedtls_psa_translate_ecc_group( mbedtls_ecp_group_id grpid ) -{ - switch( grpid ) - { -#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) - case MBEDTLS_ECP_DP_SECP192R1: - return( PSA_ECC_CURVE_SECP192R1 ); -#endif -#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) - case MBEDTLS_ECP_DP_SECP224R1: - return( PSA_ECC_CURVE_SECP224R1 ); -#endif -#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) - case MBEDTLS_ECP_DP_SECP256R1: - return( PSA_ECC_CURVE_SECP256R1 ); -#endif -#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) - case MBEDTLS_ECP_DP_SECP384R1: - return( PSA_ECC_CURVE_SECP384R1 ); -#endif -#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) - case MBEDTLS_ECP_DP_SECP521R1: - return( PSA_ECC_CURVE_SECP521R1 ); -#endif -#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) - case MBEDTLS_ECP_DP_BP256R1: - return( PSA_ECC_CURVE_BRAINPOOL_P256R1 ); -#endif -#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) - case MBEDTLS_ECP_DP_BP384R1: - return( PSA_ECC_CURVE_BRAINPOOL_P384R1 ); -#endif -#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) - case MBEDTLS_ECP_DP_BP512R1: - return( PSA_ECC_CURVE_BRAINPOOL_P512R1 ); -#endif -#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) - case MBEDTLS_ECP_DP_CURVE25519: - return( PSA_ECC_CURVE_CURVE25519 ); -#endif -#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) - case MBEDTLS_ECP_DP_SECP192K1: - return( PSA_ECC_CURVE_SECP192K1 ); -#endif -#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) - case MBEDTLS_ECP_DP_SECP224K1: - return( PSA_ECC_CURVE_SECP224K1 ); -#endif -#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) - case MBEDTLS_ECP_DP_SECP256K1: - return( PSA_ECC_CURVE_SECP256K1 ); -#endif -#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) - case MBEDTLS_ECP_DP_CURVE448: - return( PSA_ECC_CURVE_CURVE448 ); -#endif - default: - return( 0 ); - } -} - - -#define MBEDTLS_PSA_ECC_KEY_BITS_OF_CURVE( curve ) \ - ( curve == PSA_ECC_CURVE_SECP192R1 ? 192 : \ - curve == PSA_ECC_CURVE_SECP224R1 ? 224 : \ - curve == PSA_ECC_CURVE_SECP256R1 ? 256 : \ - curve == PSA_ECC_CURVE_SECP384R1 ? 384 : \ - curve == PSA_ECC_CURVE_SECP521R1 ? 521 : \ - curve == PSA_ECC_CURVE_SECP192K1 ? 192 : \ - curve == PSA_ECC_CURVE_SECP224K1 ? 224 : \ - curve == PSA_ECC_CURVE_SECP256K1 ? 256 : \ - curve == PSA_ECC_CURVE_BRAINPOOL_P256R1 ? 256 : \ - curve == PSA_ECC_CURVE_BRAINPOOL_P384R1 ? 384 : \ - curve == PSA_ECC_CURVE_BRAINPOOL_P512R1 ? 512 : \ - 0 ) - -#define MBEDTLS_PSA_ECC_KEY_BYTES_OF_CURVE( curve ) \ - ( ( MBEDTLS_PSA_ECC_KEY_BITS_OF_CURVE( curve ) + 7 ) / 8 ) - /* Translations for PK layer */ static inline int mbedtls_psa_err_translate_pk( psa_status_t status ) @@ -427,13 +365,18 @@ static inline int mbedtls_psa_err_translate_pk( psa_status_t status ) /* This function transforms an ECC group identifier from * https://www.iana.org/assignments/tls-parameters/tls-parameters.xhtml#tls-parameters-8 * into a PSA ECC group identifier. */ -static inline psa_ecc_curve_t mbedtls_psa_parse_tls_ecc_group( - uint16_t tls_ecc_grp_reg_id ) +#if defined(MBEDTLS_ECP_C) +static inline psa_key_type_t mbedtls_psa_parse_tls_ecc_group( + uint16_t tls_ecc_grp_reg_id, size_t *bits ) { - /* The PSA identifiers are currently aligned with those from - * the TLS Supported Groups registry, so no conversion is necessary. */ - return( (psa_ecc_curve_t) tls_ecc_grp_reg_id ); + const mbedtls_ecp_curve_info *curve_info = + mbedtls_ecp_curve_info_from_tls_id( tls_ecc_grp_reg_id ); + if( curve_info == NULL ) + return( 0 ); + return( PSA_KEY_TYPE_ECC_KEY_PAIR( + mbedtls_ecc_group_to_psa( curve_info->grp_id, bits ) ) ); } +#endif /* MBEDTLS_ECP_C */ /* This function takes a buffer holding an EC public key * exported through psa_export_public_key(), and converts @@ -460,15 +403,12 @@ static inline int mbedtls_psa_tls_psa_ec_to_ecpoint( unsigned char *src, * exchanges) and converts it into a format that the PSA key * agreement API understands. */ -static inline int mbedtls_psa_tls_ecpoint_to_psa_ec( psa_ecc_curve_t curve, - unsigned char const *src, +static inline int mbedtls_psa_tls_ecpoint_to_psa_ec( unsigned char const *src, size_t srclen, unsigned char *dst, size_t dstlen, size_t *olen ) { - ((void) curve); - if( srclen > dstlen ) return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); diff --git a/features/mbedtls/mbed-crypto/inc/mbedtls/rsa.h b/features/mbedtls/mbed-crypto/inc/mbedtls/rsa.h index 840540b0d9..ec8d0d8ded 100644 --- a/features/mbedtls/mbed-crypto/inc/mbedtls/rsa.h +++ b/features/mbedtls/mbed-crypto/inc/mbedtls/rsa.h @@ -907,7 +907,8 @@ int mbedtls_rsa_rsaes_oaep_decrypt( mbedtls_rsa_context *ctx, * the size of the hash corresponding to \p md_alg. * \param sig The buffer to hold the signature. This must be a writable * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. + * for an 2048-bit RSA modulus. A buffer length of + * #MBEDTLS_MPI_MAX_SIZE is always safe. * * \return \c 0 if the signing operation was successful. * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. @@ -954,7 +955,8 @@ int mbedtls_rsa_pkcs1_sign( mbedtls_rsa_context *ctx, * the size of the hash corresponding to \p md_alg. * \param sig The buffer to hold the signature. This must be a writable * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. + * for an 2048-bit RSA modulus. A buffer length of + * #MBEDTLS_MPI_MAX_SIZE is always safe. * * \return \c 0 if the signing operation was successful. * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. @@ -1015,7 +1017,8 @@ int mbedtls_rsa_rsassa_pkcs1_v15_sign( mbedtls_rsa_context *ctx, * the size of the hash corresponding to \p md_alg. * \param sig The buffer to hold the signature. This must be a writable * buffer of length \c ctx->len Bytes. For example, \c 256 Bytes - * for an 2048-bit RSA modulus. + * for an 2048-bit RSA modulus. A buffer length of + * #MBEDTLS_MPI_MAX_SIZE is always safe. * * \return \c 0 if the signing operation was successful. * \return An \c MBEDTLS_ERR_RSA_XXX error code on failure. diff --git a/features/mbedtls/mbed-crypto/inc/mbedtls/sha512.h b/features/mbedtls/mbed-crypto/inc/mbedtls/sha512.h index 48923e5bc6..8e54ce01a7 100644 --- a/features/mbedtls/mbed-crypto/inc/mbedtls/sha512.h +++ b/features/mbedtls/mbed-crypto/inc/mbedtls/sha512.h @@ -59,8 +59,10 @@ typedef struct mbedtls_sha512_context uint64_t total[2]; /*!< The number of Bytes processed. */ uint64_t state[8]; /*!< The intermediate digest state. */ unsigned char buffer[128]; /*!< The data block being processed. */ +#if !defined(MBEDTLS_SHA512_NO_SHA384) int is384; /*!< Determines which function to use: 0: Use SHA-512, or 1: Use SHA-384. */ +#endif } mbedtls_sha512_context; @@ -101,7 +103,11 @@ void mbedtls_sha512_clone( mbedtls_sha512_context *dst, * * \param ctx The SHA-512 context to use. This must be initialized. * \param is384 Determines which function to use. This must be - * either \c for SHA-512, or \c 1 for SHA-384. + * either \c 0 for SHA-512, or \c 1 for SHA-384. + * + * \note When \c MBEDTLS_SHA512_NO_SHA384 is defined, \p is384 must + * be \c 0, or the function will return + * #MBEDTLS_ERR_SHA512_BAD_INPUT_DATA. * * \return \c 0 on success. * \return A negative error code on failure. @@ -169,6 +175,9 @@ int mbedtls_internal_sha512_process( mbedtls_sha512_context *ctx, * \param ctx The SHA-512 context to use. This must be initialized. * \param is384 Determines which function to use. This must be either * \c 0 for SHA-512 or \c 1 for SHA-384. + * + * \note When \c MBEDTLS_SHA512_NO_SHA384 is defined, \p is384 must + * be \c 0, or the function will fail to work. */ MBEDTLS_DEPRECATED void mbedtls_sha512_starts( mbedtls_sha512_context *ctx, int is384 ); @@ -239,6 +248,10 @@ MBEDTLS_DEPRECATED void mbedtls_sha512_process( * \param is384 Determines which function to use. This must be either * \c 0 for SHA-512, or \c 1 for SHA-384. * + * \note When \c MBEDTLS_SHA512_NO_SHA384 is defined, \p is384 must + * be \c 0, or the function will return + * #MBEDTLS_ERR_SHA512_BAD_INPUT_DATA. + * * \return \c 0 on success. * \return A negative error code on failure. */ @@ -273,6 +286,9 @@ int mbedtls_sha512_ret( const unsigned char *input, * be a writable buffer of length \c 64 Bytes. * \param is384 Determines which function to use. This must be either * \c 0 for SHA-512, or \c 1 for SHA-384. + * + * \note When \c MBEDTLS_SHA512_NO_SHA384 is defined, \p is384 must + * be \c 0, or the function will fail to work. */ MBEDTLS_DEPRECATED void mbedtls_sha512( const unsigned char *input, size_t ilen, diff --git a/features/mbedtls/mbed-crypto/inc/psa/crypto.h b/features/mbedtls/mbed-crypto/inc/psa/crypto.h index 7291c3e576..2b07b7471c 100644 --- a/features/mbedtls/mbed-crypto/inc/psa/crypto.h +++ b/features/mbedtls/mbed-crypto/inc/psa/crypto.h @@ -932,7 +932,7 @@ psa_status_t psa_hash_compare(psa_algorithm_t alg, const uint8_t *input, size_t input_length, const uint8_t *hash, - const size_t hash_length); + size_t hash_length); /** The type of the state data structure for multipart hash operations. * @@ -1300,7 +1300,7 @@ psa_status_t psa_mac_verify(psa_key_handle_t handle, const uint8_t *input, size_t input_length, const uint8_t *mac, - const size_t mac_length); + size_t mac_length); /** The type of the state data structure for multipart MAC operations. * @@ -2879,7 +2879,7 @@ psa_status_t psa_aead_abort(psa_aead_operation_t *operation); * \retval #PSA_ERROR_BUFFER_TOO_SMALL * The size of the \p signature buffer is too small. You can * determine a sufficient buffer size by calling - * #PSA_ASYMMETRIC_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) + * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) * where \c key_type and \c key_bits are the type and bit-size * respectively of \p handle. * \retval #PSA_ERROR_NOT_SUPPORTED @@ -2895,13 +2895,13 @@ psa_status_t psa_aead_abort(psa_aead_operation_t *operation); * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_asymmetric_sign(psa_key_handle_t handle, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length); +psa_status_t psa_sign_hash(psa_key_handle_t handle, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length); /** * \brief Verify the signature a hash or short message using a public key. @@ -2941,12 +2941,12 @@ psa_status_t psa_asymmetric_sign(psa_key_handle_t handle, * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_asymmetric_verify(psa_key_handle_t handle, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - const uint8_t *signature, - size_t signature_length); +psa_status_t psa_verify_hash(psa_key_handle_t handle, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length); /** * \brief Encrypt a short message with a public key. @@ -3502,10 +3502,10 @@ psa_status_t psa_key_derivation_output_bytes( * length is determined by the curve, and sets the mandatory bits * accordingly. That is: * - * - #PSA_ECC_CURVE_CURVE25519: draw a 32-byte string - * and process it as specified in RFC 7748 §5. - * - #PSA_ECC_CURVE_CURVE448: draw a 56-byte string - * and process it as specified in RFC 7748 §5. + * - Curve25519 (#PSA_ECC_CURVE_MONTGOMERY, 255 bits): draw a 32-byte + * string and process it as specified in RFC 7748 §5. + * - Curve448 (#PSA_ECC_CURVE_MONTGOMERY, 448 bits): draw a 56-byte + * string and process it as specified in RFC 7748 §5. * * - For key types for which the key is represented by a single sequence of * \p bits bits with constraints as to which bit sequences are acceptable, diff --git a/features/mbedtls/mbed-crypto/inc/psa/crypto_compat.h b/features/mbedtls/mbed-crypto/inc/psa/crypto_compat.h new file mode 100644 index 0000000000..1ed5f052b2 --- /dev/null +++ b/features/mbedtls/mbed-crypto/inc/psa/crypto_compat.h @@ -0,0 +1,196 @@ +/** + * \file psa/crypto_compat.h + * + * \brief PSA cryptography module: Backward compatibility aliases + * + * This header declares alternative names for macro and functions. + * New application code should not use these names. + * These names may be removed in a future version of Mbed Crypto. + * + * \note This file may not be included directly. Applications must + * include psa/crypto.h. + */ +/* + * Copyright (C) 2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file is part of mbed TLS (https://tls.mbed.org) + */ + +#ifndef PSA_CRYPTO_COMPAT_H +#define PSA_CRYPTO_COMPAT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) + +/* + * Mechanism for declaring deprecated values + */ +#if defined(MBEDTLS_DEPRECATED_WARNING) && !defined(MBEDTLS_PSA_DEPRECATED) +#define MBEDTLS_PSA_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_PSA_DEPRECATED +#endif + +typedef MBEDTLS_PSA_DEPRECATED size_t mbedtls_deprecated_size_t; +typedef MBEDTLS_PSA_DEPRECATED psa_status_t mbedtls_deprecated_psa_status_t; +typedef MBEDTLS_PSA_DEPRECATED psa_key_usage_t mbedtls_deprecated_psa_key_usage_t; +typedef MBEDTLS_PSA_DEPRECATED psa_ecc_curve_t mbedtls_deprecated_psa_ecc_curve_t; +typedef MBEDTLS_PSA_DEPRECATED psa_dh_group_t mbedtls_deprecated_psa_dh_group_t; + +#define MBEDTLS_DEPRECATED_CONSTANT( type, value ) \ + ( (mbedtls_deprecated_##type) ( value ) ) + +/* + * Deprecated PSA Crypto error code definitions (PSA Crypto API <= 1.0 beta2) + */ +#define PSA_ERROR_UNKNOWN_ERROR \ + MBEDTLS_DEPRECATED_CONSTANT( psa_status_t, PSA_ERROR_GENERIC_ERROR ) +#define PSA_ERROR_OCCUPIED_SLOT \ + MBEDTLS_DEPRECATED_CONSTANT( psa_status_t, PSA_ERROR_ALREADY_EXISTS ) +#define PSA_ERROR_EMPTY_SLOT \ + MBEDTLS_DEPRECATED_CONSTANT( psa_status_t, PSA_ERROR_DOES_NOT_EXIST ) +#define PSA_ERROR_INSUFFICIENT_CAPACITY \ + MBEDTLS_DEPRECATED_CONSTANT( psa_status_t, PSA_ERROR_INSUFFICIENT_DATA ) +#define PSA_ERROR_TAMPERING_DETECTED \ + MBEDTLS_DEPRECATED_CONSTANT( psa_status_t, PSA_ERROR_CORRUPTION_DETECTED ) + +/* + * Deprecated PSA Crypto numerical encodings (PSA Crypto API <= 1.0 beta3) + */ +#define PSA_KEY_USAGE_SIGN \ + MBEDTLS_DEPRECATED_CONSTANT( psa_key_usage_t, PSA_KEY_USAGE_SIGN_HASH ) +#define PSA_KEY_USAGE_VERIFY \ + MBEDTLS_DEPRECATED_CONSTANT( psa_key_usage_t, PSA_KEY_USAGE_VERIFY_HASH ) + +/* + * Deprecated PSA Crypto size calculation macros (PSA Crypto API <= 1.0 beta3) + */ +#define PSA_ASYMMETRIC_SIGNATURE_MAX_SIZE \ + MBEDTLS_DEPRECATED_CONSTANT( size_t, PSA_SIGNATURE_MAX_SIZE ) +#define PSA_ASYMMETRIC_SIGN_OUTPUT_SIZE( key_type, key_bits, alg ) \ + MBEDTLS_DEPRECATED_CONSTANT( size_t, PSA_SIGN_OUTPUT_SIZE( key_type, key_bits, alg ) ) + +/* + * Deprecated PSA Crypto function names (PSA Crypto API <= 1.0 beta3) + */ +MBEDTLS_PSA_DEPRECATED static inline psa_status_t psa_asymmetric_sign( psa_key_handle_t key, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length ) +{ + return psa_sign_hash( key, alg, hash, hash_length, signature, signature_size, signature_length ); +} + +MBEDTLS_PSA_DEPRECATED static inline psa_status_t psa_asymmetric_verify( psa_key_handle_t key, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length ) +{ + return psa_verify_hash( key, alg, hash, hash_length, signature, signature_length ); +} + + + +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +/* + * Size-specific elliptic curve and Diffie-Hellman group names + */ +#define PSA_ECC_CURVE_SECP160K1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECP_K1 ) +#define PSA_ECC_CURVE_SECP192K1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECP_K1 ) +#define PSA_ECC_CURVE_SECP224K1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECP_K1 ) +#define PSA_ECC_CURVE_SECP256K1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECP_K1 ) +#define PSA_ECC_CURVE_SECP160R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECP_R1 ) +#define PSA_ECC_CURVE_SECP192R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECP_R1 ) +#define PSA_ECC_CURVE_SECP224R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECP_R1 ) +#define PSA_ECC_CURVE_SECP256R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECP_R1 ) +#define PSA_ECC_CURVE_SECP384R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECP_R1 ) +#define PSA_ECC_CURVE_SECP521R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECP_R1 ) +#define PSA_ECC_CURVE_SECP160R2 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECP_R2 ) +#define PSA_ECC_CURVE_SECT163K1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_K1 ) +#define PSA_ECC_CURVE_SECT233K1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_K1 ) +#define PSA_ECC_CURVE_SECT239K1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_K1 ) +#define PSA_ECC_CURVE_SECT283K1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_K1 ) +#define PSA_ECC_CURVE_SECT409K1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_K1 ) +#define PSA_ECC_CURVE_SECT571K1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_K1 ) +#define PSA_ECC_CURVE_SECT163R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_R1 ) +#define PSA_ECC_CURVE_SECT193R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_R1 ) +#define PSA_ECC_CURVE_SECT233R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_R1 ) +#define PSA_ECC_CURVE_SECT283R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_R1 ) +#define PSA_ECC_CURVE_SECT409R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_R1 ) +#define PSA_ECC_CURVE_SECT571R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_R1 ) +#define PSA_ECC_CURVE_SECT163R2 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_R2 ) +#define PSA_ECC_CURVE_SECT193R2 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_SECT_R2 ) +#define PSA_ECC_CURVE_BRAINPOOL_P256R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_BRAINPOOL_P_R1 ) +#define PSA_ECC_CURVE_BRAINPOOL_P384R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_BRAINPOOL_P_R1 ) +#define PSA_ECC_CURVE_BRAINPOOL_P512R1 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_BRAINPOOL_P_R1 ) +#define PSA_ECC_CURVE_CURVE25519 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_MONTGOMERY ) +#define PSA_ECC_CURVE_CURVE448 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_ecc_curve_t, PSA_ECC_CURVE_MONTGOMERY ) + +#define PSA_DH_GROUP_FFDHE2048 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_dh_group_t, PSA_DH_GROUP_RFC7919 ) +#define PSA_DH_GROUP_FFDHE3072 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_dh_group_t, PSA_DH_GROUP_RFC7919 ) +#define PSA_DH_GROUP_FFDHE4096 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_dh_group_t, PSA_DH_GROUP_RFC7919 ) +#define PSA_DH_GROUP_FFDHE6144 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_dh_group_t, PSA_DH_GROUP_RFC7919 ) +#define PSA_DH_GROUP_FFDHE8192 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_dh_group_t, PSA_DH_GROUP_RFC7919 ) + +#ifdef __cplusplus +} +#endif + +#endif /* PSA_CRYPTO_COMPAT_H */ diff --git a/features/mbedtls/mbed-crypto/inc/psa/crypto_extra.h b/features/mbedtls/mbed-crypto/inc/psa/crypto_extra.h index c5313d619e..e9fa31189c 100644 --- a/features/mbedtls/mbed-crypto/inc/psa/crypto_extra.h +++ b/features/mbedtls/mbed-crypto/inc/psa/crypto_extra.h @@ -32,6 +32,8 @@ #include "mbedtls/platform_util.h" +#include "crypto_compat.h" + #ifdef __cplusplus extern "C" { #endif @@ -39,21 +41,6 @@ extern "C" { /* UID for secure storage seed */ #define PSA_CRYPTO_ITS_RANDOM_SEED_UID 0xFFFFFF52 -/* - * Deprecated PSA Crypto error code definitions - */ -#if !defined(MBEDTLS_DEPRECATED_REMOVED) -#define PSA_ERROR_UNKNOWN_ERROR \ - MBEDTLS_DEPRECATED_NUMERIC_CONSTANT( PSA_ERROR_GENERIC_ERROR ) -#define PSA_ERROR_OCCUPIED_SLOT \ - MBEDTLS_DEPRECATED_NUMERIC_CONSTANT( PSA_ERROR_ALREADY_EXISTS ) -#define PSA_ERROR_EMPTY_SLOT \ - MBEDTLS_DEPRECATED_NUMERIC_CONSTANT( PSA_ERROR_DOES_NOT_EXIST ) -#define PSA_ERROR_INSUFFICIENT_CAPACITY \ - MBEDTLS_DEPRECATED_NUMERIC_CONSTANT( PSA_ERROR_INSUFFICIENT_DATA ) -#define PSA_ERROR_TAMPERING_DETECTED \ - MBEDTLS_DEPRECATED_NUMERIC_CONSTANT( PSA_ERROR_CORRUPTION_DETECTED ) -#endif /** \addtogroup attributes * @{ @@ -342,7 +329,7 @@ psa_status_t mbedtls_psa_inject_entropy(const uint8_t *seed, * string. The length of the byte string is the length of the base prime `p` * in bytes. */ -#define PSA_KEY_TYPE_DSA_PUBLIC_KEY ((psa_key_type_t)0x60020000) +#define PSA_KEY_TYPE_DSA_PUBLIC_KEY ((psa_key_type_t)0x4002) /** DSA key pair (private and public key). * @@ -360,7 +347,7 @@ psa_status_t mbedtls_psa_inject_entropy(const uint8_t *seed, * Add 1 to the resulting integer and use this as the private key *x*. * */ -#define PSA_KEY_TYPE_DSA_KEY_PAIR ((psa_key_type_t)0x70020000) +#define PSA_KEY_TYPE_DSA_KEY_PAIR ((psa_key_type_t)0x7002) /** Whether a key type is an DSA key (pair or public-only). */ #define PSA_KEY_TYPE_IS_DSA(type) \ @@ -384,7 +371,7 @@ psa_status_t mbedtls_psa_inject_entropy(const uint8_t *seed, #define PSA_ALG_DSA(hash_alg) \ (PSA_ALG_DSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) #define PSA_ALG_DETERMINISTIC_DSA_BASE ((psa_algorithm_t)0x10050000) -#define PSA_ALG_DSA_DETERMINISTIC_FLAG ((psa_algorithm_t)0x00010000) +#define PSA_ALG_DSA_DETERMINISTIC_FLAG PSA_ALG_ECDSA_DETERMINISTIC_FLAG /** Deterministic DSA signature with hashing. * * This is the deterministic variant defined by RFC 6979 of @@ -431,9 +418,7 @@ psa_status_t mbedtls_psa_inject_entropy(const uint8_t *seed, * #PSA_KEY_TYPE_DH_KEY_PAIR(#PSA_DH_GROUP_CUSTOM), the group data comes * from domain parameters set by psa_set_key_domain_parameters(). */ -/* This value is a deprecated value meaning an explicit curve in the IANA - * registry. */ -#define PSA_DH_GROUP_CUSTOM ((psa_dh_group_t) 0xff01) +#define PSA_DH_GROUP_CUSTOM ((psa_dh_group_t) 0x7e) /** @@ -573,6 +558,50 @@ psa_status_t psa_get_key_domain_parameters( /**@}*/ +/** \defgroup psa_tls_helpers TLS helper functions + * @{ + */ + +#if defined(MBEDTLS_ECP_C) +#include + +/** Convert an ECC curve identifier from the Mbed TLS encoding to PSA. + * + * \note This function is provided solely for the convenience of + * Mbed TLS and may be removed at any time without notice. + * + * \param grpid An Mbed TLS elliptic curve identifier + * (`MBEDTLS_ECP_DP_xxx`). + * \param[out] bits On success, the bit size of the curve. + * + * \return The corresponding PSA elliptic curve identifier + * (`PSA_ECC_CURVE_xxx`). + * \return \c 0 on failure (\p grpid is not recognized). + */ +psa_ecc_curve_t mbedtls_ecc_group_to_psa( mbedtls_ecp_group_id grpid, + size_t *bits ); + +/** Convert an ECC curve identifier from the PSA encoding to Mbed TLS. + * + * \note This function is provided solely for the convenience of + * Mbed TLS and may be removed at any time without notice. + * + * \param curve A PSA elliptic curve identifier + * (`PSA_ECC_CURVE_xxx`). + * \param byte_length The byte-length of a private key on \p curve. + * + * \return The corresponding Mbed TLS elliptic curve identifier + * (`MBEDTLS_ECP_DP_xxx`). + * \return #MBEDTLS_ECP_DP_NONE if \c curve is not recognized. + * \return #MBEDTLS_ECP_DP_NONE if \p byte_length is not + * correct for \p curve. + */ +mbedtls_ecp_group_id mbedtls_ecc_group_of_psa( psa_ecc_curve_t curve, + size_t byte_length ); +#endif /* MBEDTLS_ECP_C */ + +/**@}*/ + #ifdef __cplusplus } #endif diff --git a/features/mbedtls/mbed-crypto/inc/psa/crypto_sizes.h b/features/mbedtls/mbed-crypto/inc/psa/crypto_sizes.h index bcca72482f..1f04222c24 100644 --- a/features/mbedtls/mbed-crypto/inc/psa/crypto_sizes.h +++ b/features/mbedtls/mbed-crypto/inc/psa/crypto_sizes.h @@ -190,47 +190,6 @@ #define PSA_VENDOR_ECC_MAX_CURVE_BITS 0 #endif -/** Bit size associated with an elliptic curve. - * - * \param curve An elliptic curve (value of type #psa_ecc_curve_t). - * - * \return The size associated with \p curve, in bits. - * This may be 0 if the implementation does not support - * the specified curve. - */ -#define PSA_ECC_CURVE_BITS(curve) \ - ((curve) == PSA_ECC_CURVE_SECT163K1 ? 163 : \ - (curve) == PSA_ECC_CURVE_SECT163R1 ? 163 : \ - (curve) == PSA_ECC_CURVE_SECT163R2 ? 163 : \ - (curve) == PSA_ECC_CURVE_SECT193R1 ? 193 : \ - (curve) == PSA_ECC_CURVE_SECT193R2 ? 193 : \ - (curve) == PSA_ECC_CURVE_SECT233K1 ? 233 : \ - (curve) == PSA_ECC_CURVE_SECT233R1 ? 233 : \ - (curve) == PSA_ECC_CURVE_SECT239K1 ? 239 : \ - (curve) == PSA_ECC_CURVE_SECT283K1 ? 283 : \ - (curve) == PSA_ECC_CURVE_SECT283R1 ? 283 : \ - (curve) == PSA_ECC_CURVE_SECT409K1 ? 409 : \ - (curve) == PSA_ECC_CURVE_SECT409R1 ? 409 : \ - (curve) == PSA_ECC_CURVE_SECT571K1 ? 571 : \ - (curve) == PSA_ECC_CURVE_SECT571R1 ? 571 : \ - (curve) == PSA_ECC_CURVE_SECP160K1 ? 160 : \ - (curve) == PSA_ECC_CURVE_SECP160R1 ? 160 : \ - (curve) == PSA_ECC_CURVE_SECP160R2 ? 160 : \ - (curve) == PSA_ECC_CURVE_SECP192K1 ? 192 : \ - (curve) == PSA_ECC_CURVE_SECP192R1 ? 192 : \ - (curve) == PSA_ECC_CURVE_SECP224K1 ? 224 : \ - (curve) == PSA_ECC_CURVE_SECP224R1 ? 224 : \ - (curve) == PSA_ECC_CURVE_SECP256K1 ? 256 : \ - (curve) == PSA_ECC_CURVE_SECP256R1 ? 256 : \ - (curve) == PSA_ECC_CURVE_SECP384R1 ? 384 : \ - (curve) == PSA_ECC_CURVE_SECP521R1 ? 521 : \ - (curve) == PSA_ECC_CURVE_BRAINPOOL_P256R1 ? 256 : \ - (curve) == PSA_ECC_CURVE_BRAINPOOL_P384R1 ? 384 : \ - (curve) == PSA_ECC_CURVE_BRAINPOOL_P512R1 ? 512 : \ - (curve) == PSA_ECC_CURVE_CURVE25519 ? 255 : \ - (curve) == PSA_ECC_CURVE_CURVE448 ? 448 : \ - 0) - /** \def PSA_ALG_TLS12_PSK_TO_MS_MAX_PSK_LEN * * This macro returns the maximum length of the PSK supported @@ -247,21 +206,6 @@ */ #define PSA_ALG_TLS12_PSK_TO_MS_MAX_PSK_LEN 128 -/** \def PSA_ASYMMETRIC_SIGNATURE_MAX_SIZE - * - * Maximum size of an asymmetric signature. - * - * This macro must expand to a compile-time constant integer. This value - * should be the maximum size of a MAC supported by the implementation, - * in bytes, and must be no smaller than this maximum. - */ -#define PSA_ASYMMETRIC_SIGNATURE_MAX_SIZE \ - PSA_BITS_TO_BYTES( \ - PSA_VENDOR_RSA_MAX_KEY_BITS > PSA_VENDOR_ECC_MAX_CURVE_BITS ? \ - PSA_VENDOR_RSA_MAX_KEY_BITS : \ - PSA_VENDOR_ECC_MAX_CURVE_BITS \ - ) - /** The maximum size of a block cipher supported by the implementation. */ #define PSA_MAX_BLOCK_CIPHER_BLOCK_SIZE 16 @@ -426,7 +370,7 @@ #define PSA_ECDSA_SIGNATURE_SIZE(curve_bits) \ (PSA_BITS_TO_BYTES(curve_bits) * 2) -/** Sufficient signature buffer size for psa_asymmetric_sign(). +/** Sufficient signature buffer size for psa_sign_hash(). * * This macro returns a sufficient buffer size for a signature using a key * of the specified type and size, with the specified algorithm. @@ -444,7 +388,7 @@ * * \return If the parameters are valid and supported, return * a buffer size in bytes that guarantees that - * psa_asymmetric_sign() will not fail with + * psa_sign_hash() will not fail with * #PSA_ERROR_BUFFER_TOO_SMALL. * If the parameters are a valid combination that is not supported * by the implementation, this macro shall return either a @@ -452,11 +396,27 @@ * If the parameters are not valid, the * return value is unspecified. */ -#define PSA_ASYMMETRIC_SIGN_OUTPUT_SIZE(key_type, key_bits, alg) \ +#define PSA_SIGN_OUTPUT_SIZE(key_type, key_bits, alg) \ (PSA_KEY_TYPE_IS_RSA(key_type) ? ((void)alg, PSA_BITS_TO_BYTES(key_bits)) : \ PSA_KEY_TYPE_IS_ECC(key_type) ? PSA_ECDSA_SIGNATURE_SIZE(key_bits) : \ ((void)alg, 0)) +#define PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE \ + PSA_ECDSA_SIGNATURE_SIZE(PSA_VENDOR_ECC_MAX_CURVE_BITS) + +/** \def PSA_SIGNATURE_MAX_SIZE + * + * Maximum size of an asymmetric signature. + * + * This macro must expand to a compile-time constant integer. This value + * should be the maximum size of a signature supported by the implementation, + * in bytes, and must be no smaller than this maximum. + */ +#define PSA_SIGNATURE_MAX_SIZE \ + (PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS) > PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE ? \ + PSA_BITS_TO_BYTES(PSA_VENDOR_RSA_MAX_KEY_BITS) : \ + PSA_VENDOR_ECDSA_SIGNATURE_MAX_SIZE) + /** Sufficient output buffer size for psa_asymmetric_encrypt(). * * This macro returns a sufficient buffer size for a ciphertext produced using @@ -681,7 +641,7 @@ * * \return If the parameters are valid and supported, return * a buffer size in bytes that guarantees that - * psa_asymmetric_sign() will not fail with + * psa_sign_hash() will not fail with * #PSA_ERROR_BUFFER_TOO_SMALL. * If the parameters are a valid combination that is not supported * by the implementation, this macro shall return either a diff --git a/features/mbedtls/mbed-crypto/inc/psa/crypto_types.h b/features/mbedtls/mbed-crypto/inc/psa/crypto_types.h index c4f9acd460..d96c66e5c4 100644 --- a/features/mbedtls/mbed-crypto/inc/psa/crypto_types.h +++ b/features/mbedtls/mbed-crypto/inc/psa/crypto_types.h @@ -63,85 +63,29 @@ typedef int32_t psa_status_t; /** \brief Encoding of a key type. */ -typedef uint32_t psa_key_type_t; +typedef uint16_t psa_key_type_t; -/** The type of PSA elliptic curve identifiers. +/** The type of PSA elliptic curve family identifiers. * * The curve identifier is required to create an ECC key using the * PSA_KEY_TYPE_ECC_KEY_PAIR() or PSA_KEY_TYPE_ECC_PUBLIC_KEY() * macros. * - * The encoding of curve identifiers is taken from the - * TLS Supported Groups Registry (formerly known as the - * TLS EC Named Curve Registry) - * https://www.iana.org/assignments/tls-parameters/tls-parameters.xhtml#tls-parameters-8 - * - * This specification defines identifiers for some of the curves in the IANA - * registry. Implementations that support other curves that are in the IANA - * registry should use the IANA value and a implementation-specific identifier. - * Implemenations that support non-IANA curves should use one of the following - * approaches for allocating a key type: - * - * 1. Select a ::psa_ecc_curve_t value in the range #PSA_ECC_CURVE_VENDOR_MIN to - * #PSA_ECC_CURVE_VENDOR_MAX, which is a subset of the IANA private use - * range. - * 2. Use a ::psa_key_type_t value that is vendor-defined. - * - * The first option is recommended. + * Values defined by this standard will never be in the range 0x80-0xff. + * Vendors who define additional families must use an encoding in this range. */ -typedef uint16_t psa_ecc_curve_t; +typedef uint8_t psa_ecc_curve_t; -/** The type of PSA Diffie-Hellman group identifiers. +/** The type of PSA Diffie-Hellman group family identifiers. * * The group identifier is required to create an Diffie-Hellman key using the * PSA_KEY_TYPE_DH_KEY_PAIR() or PSA_KEY_TYPE_DH_PUBLIC_KEY() * macros. * - * The encoding of group identifiers is taken from the - * TLS Supported Groups Registry (formerly known as the - * TLS EC Named Curve Registry) - * https://www.iana.org/assignments/tls-parameters/tls-parameters.xhtml#tls-parameters-8 - * - * This specification defines identifiers for some of the groups in the IANA - * registry. Implementations that support other groups that are in the IANA - * registry should use the IANA value and a implementation-specific identifier. - * Implemenations that support non-IANA groups should use one of the following - * approaches for allocating a key type: - * - * 1. Select a ::psa_dh_group_t value in the range #PSA_DH_GROUP_VENDOR_MIN to - * #PSA_DH_GROUP_VENDOR_MAX, which is a subset of the IANA private use - * range. - * 2. Select a ::psa_dh_group_t value from the named groups allocated for - * GREASE in the IETF draft specification. The GREASE specification and - * values are listed below. - * 3. Use a ::psa_key_type_t value that is vendor-defined. - * - * Option 1 or 2 are recommended. - * - * The current draft of the GREASE specification is - * https://datatracker.ietf.org/doc/draft-ietf-tls-grease - * - * The following GREASE values are allocated for named groups: - * \code - * 0x0A0A - * 0x1A1A - * 0x2A2A - * 0x3A3A - * 0x4A4A - * 0x5A5A - * 0x6A6A - * 0x7A7A - * 0x8A8A - * 0x9A9A - * 0xAAAA - * 0xBABA - * 0xCACA - * 0xDADA - * 0xEAEA - * 0xFAFA - * \endcode + * Values defined by this standard will never be in the range 0x80-0xff. + * Vendors who define additional families must use an encoding in this range. */ -typedef uint16_t psa_dh_group_t; +typedef uint8_t psa_dh_group_t; /** \brief Encoding of a cryptographic algorithm. * diff --git a/features/mbedtls/mbed-crypto/inc/psa/crypto_values.h b/features/mbedtls/mbed-crypto/inc/psa/crypto_values.h index 1e0c2136a0..baaabff1e0 100644 --- a/features/mbedtls/mbed-crypto/inc/psa/crypto_values.h +++ b/features/mbedtls/mbed-crypto/inc/psa/crypto_values.h @@ -282,7 +282,7 @@ * * Zero is not the encoding of any key type. */ -#define PSA_KEY_TYPE_NONE ((psa_key_type_t)0x00000000) +#define PSA_KEY_TYPE_NONE ((psa_key_type_t)0x0000) /** Vendor-defined key type flag. * @@ -291,15 +291,15 @@ * must use an encoding with the #PSA_KEY_TYPE_VENDOR_FLAG bit set and should * respect the bitwise structure used by standard encodings whenever practical. */ -#define PSA_KEY_TYPE_VENDOR_FLAG ((psa_key_type_t)0x80000000) +#define PSA_KEY_TYPE_VENDOR_FLAG ((psa_key_type_t)0x8000) -#define PSA_KEY_TYPE_CATEGORY_MASK ((psa_key_type_t)0x70000000) -#define PSA_KEY_TYPE_CATEGORY_SYMMETRIC ((psa_key_type_t)0x40000000) -#define PSA_KEY_TYPE_CATEGORY_RAW ((psa_key_type_t)0x50000000) -#define PSA_KEY_TYPE_CATEGORY_PUBLIC_KEY ((psa_key_type_t)0x60000000) -#define PSA_KEY_TYPE_CATEGORY_KEY_PAIR ((psa_key_type_t)0x70000000) +#define PSA_KEY_TYPE_CATEGORY_MASK ((psa_key_type_t)0x7000) +#define PSA_KEY_TYPE_CATEGORY_RAW ((psa_key_type_t)0x1000) +#define PSA_KEY_TYPE_CATEGORY_SYMMETRIC ((psa_key_type_t)0x2000) +#define PSA_KEY_TYPE_CATEGORY_PUBLIC_KEY ((psa_key_type_t)0x4000) +#define PSA_KEY_TYPE_CATEGORY_KEY_PAIR ((psa_key_type_t)0x7000) -#define PSA_KEY_TYPE_CATEGORY_FLAG_PAIR ((psa_key_type_t)0x10000000) +#define PSA_KEY_TYPE_CATEGORY_FLAG_PAIR ((psa_key_type_t)0x3000) /** Whether a key type is vendor-defined. * @@ -313,8 +313,8 @@ * This encompasses both symmetric keys and non-key data. */ #define PSA_KEY_TYPE_IS_UNSTRUCTURED(type) \ - (((type) & PSA_KEY_TYPE_CATEGORY_MASK & ~(psa_key_type_t)0x10000000) == \ - PSA_KEY_TYPE_CATEGORY_SYMMETRIC) + (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_RAW || \ + ((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_SYMMETRIC) /** Whether a key type is asymmetric: either a key pair or a public key. */ #define PSA_KEY_TYPE_IS_ASYMMETRIC(type) \ @@ -357,7 +357,7 @@ * * A "key" of this type cannot be used for any cryptographic operation. * Applications may use this type to store arbitrary data in the keystore. */ -#define PSA_KEY_TYPE_RAW_DATA ((psa_key_type_t)0x50000001) +#define PSA_KEY_TYPE_RAW_DATA ((psa_key_type_t)0x1001) /** HMAC key. * @@ -367,21 +367,21 @@ * HMAC keys should generally have the same size as the underlying hash. * This size can be calculated with #PSA_HASH_SIZE(\c alg) where * \c alg is the HMAC algorithm or the underlying hash algorithm. */ -#define PSA_KEY_TYPE_HMAC ((psa_key_type_t)0x51000000) +#define PSA_KEY_TYPE_HMAC ((psa_key_type_t)0x1100) /** A secret for key derivation. * * The key policy determines which key derivation algorithm the key * can be used for. */ -#define PSA_KEY_TYPE_DERIVE ((psa_key_type_t)0x52000000) +#define PSA_KEY_TYPE_DERIVE ((psa_key_type_t)0x1200) /** Key for a cipher, AEAD or MAC algorithm based on the AES block cipher. * * The size of the key can be 16 bytes (AES-128), 24 bytes (AES-192) or * 32 bytes (AES-256). */ -#define PSA_KEY_TYPE_AES ((psa_key_type_t)0x40000001) +#define PSA_KEY_TYPE_AES ((psa_key_type_t)0x2400) /** Key for a cipher or MAC algorithm based on DES or 3DES (Triple-DES). * @@ -392,17 +392,17 @@ * deprecated and should only be used to decrypt legacy data. 3-key 3DES * is weak and deprecated and should only be used in legacy protocols. */ -#define PSA_KEY_TYPE_DES ((psa_key_type_t)0x40000002) +#define PSA_KEY_TYPE_DES ((psa_key_type_t)0x2301) /** Key for a cipher, AEAD or MAC algorithm based on the * Camellia block cipher. */ -#define PSA_KEY_TYPE_CAMELLIA ((psa_key_type_t)0x40000003) +#define PSA_KEY_TYPE_CAMELLIA ((psa_key_type_t)0x2403) /** Key for the RC4 stream cipher. * * Note that RC4 is weak and deprecated and should only be used in * legacy protocols. */ -#define PSA_KEY_TYPE_ARC4 ((psa_key_type_t)0x40000004) +#define PSA_KEY_TYPE_ARC4 ((psa_key_type_t)0x2002) /** Key for the ChaCha20 stream cipher or the Chacha20-Poly1305 AEAD algorithm. * @@ -411,19 +411,19 @@ * Implementations must support 12-byte nonces, may support 8-byte nonces, * and should reject other sizes. */ -#define PSA_KEY_TYPE_CHACHA20 ((psa_key_type_t)0x40000005) +#define PSA_KEY_TYPE_CHACHA20 ((psa_key_type_t)0x2004) /** RSA public key. */ -#define PSA_KEY_TYPE_RSA_PUBLIC_KEY ((psa_key_type_t)0x60010000) +#define PSA_KEY_TYPE_RSA_PUBLIC_KEY ((psa_key_type_t)0x4001) /** RSA key pair (private and public key). */ -#define PSA_KEY_TYPE_RSA_KEY_PAIR ((psa_key_type_t)0x70010000) +#define PSA_KEY_TYPE_RSA_KEY_PAIR ((psa_key_type_t)0x7001) /** Whether a key type is an RSA key (pair or public-only). */ #define PSA_KEY_TYPE_IS_RSA(type) \ (PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) == PSA_KEY_TYPE_RSA_PUBLIC_KEY) -#define PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE ((psa_key_type_t)0x60030000) -#define PSA_KEY_TYPE_ECC_KEY_PAIR_BASE ((psa_key_type_t)0x70030000) -#define PSA_KEY_TYPE_ECC_CURVE_MASK ((psa_key_type_t)0x0000ffff) +#define PSA_KEY_TYPE_ECC_PUBLIC_KEY_BASE ((psa_key_type_t)0x4100) +#define PSA_KEY_TYPE_ECC_KEY_PAIR_BASE ((psa_key_type_t)0x7100) +#define PSA_KEY_TYPE_ECC_CURVE_MASK ((psa_key_type_t)0x00ff) /** Elliptic curve key pair. * * \param curve A value of type ::psa_ecc_curve_t that identifies the @@ -458,70 +458,82 @@ ((type) & PSA_KEY_TYPE_ECC_CURVE_MASK) : \ 0)) -/* The encoding of curve identifiers is currently aligned with the - * TLS Supported Groups Registry (formerly known as the - * TLS EC Named Curve Registry) - * https://www.iana.org/assignments/tls-parameters/tls-parameters.xhtml#tls-parameters-8 - * The values are defined by RFC 8422 and RFC 7027. */ -#define PSA_ECC_CURVE_SECT163K1 ((psa_ecc_curve_t) 0x0001) -#define PSA_ECC_CURVE_SECT163R1 ((psa_ecc_curve_t) 0x0002) -#define PSA_ECC_CURVE_SECT163R2 ((psa_ecc_curve_t) 0x0003) -#define PSA_ECC_CURVE_SECT193R1 ((psa_ecc_curve_t) 0x0004) -#define PSA_ECC_CURVE_SECT193R2 ((psa_ecc_curve_t) 0x0005) -#define PSA_ECC_CURVE_SECT233K1 ((psa_ecc_curve_t) 0x0006) -#define PSA_ECC_CURVE_SECT233R1 ((psa_ecc_curve_t) 0x0007) -#define PSA_ECC_CURVE_SECT239K1 ((psa_ecc_curve_t) 0x0008) -#define PSA_ECC_CURVE_SECT283K1 ((psa_ecc_curve_t) 0x0009) -#define PSA_ECC_CURVE_SECT283R1 ((psa_ecc_curve_t) 0x000a) -#define PSA_ECC_CURVE_SECT409K1 ((psa_ecc_curve_t) 0x000b) -#define PSA_ECC_CURVE_SECT409R1 ((psa_ecc_curve_t) 0x000c) -#define PSA_ECC_CURVE_SECT571K1 ((psa_ecc_curve_t) 0x000d) -#define PSA_ECC_CURVE_SECT571R1 ((psa_ecc_curve_t) 0x000e) -#define PSA_ECC_CURVE_SECP160K1 ((psa_ecc_curve_t) 0x000f) -#define PSA_ECC_CURVE_SECP160R1 ((psa_ecc_curve_t) 0x0010) -#define PSA_ECC_CURVE_SECP160R2 ((psa_ecc_curve_t) 0x0011) -#define PSA_ECC_CURVE_SECP192K1 ((psa_ecc_curve_t) 0x0012) -#define PSA_ECC_CURVE_SECP192R1 ((psa_ecc_curve_t) 0x0013) -#define PSA_ECC_CURVE_SECP224K1 ((psa_ecc_curve_t) 0x0014) -#define PSA_ECC_CURVE_SECP224R1 ((psa_ecc_curve_t) 0x0015) -#define PSA_ECC_CURVE_SECP256K1 ((psa_ecc_curve_t) 0x0016) -#define PSA_ECC_CURVE_SECP256R1 ((psa_ecc_curve_t) 0x0017) -#define PSA_ECC_CURVE_SECP384R1 ((psa_ecc_curve_t) 0x0018) -#define PSA_ECC_CURVE_SECP521R1 ((psa_ecc_curve_t) 0x0019) -#define PSA_ECC_CURVE_BRAINPOOL_P256R1 ((psa_ecc_curve_t) 0x001a) -#define PSA_ECC_CURVE_BRAINPOOL_P384R1 ((psa_ecc_curve_t) 0x001b) -#define PSA_ECC_CURVE_BRAINPOOL_P512R1 ((psa_ecc_curve_t) 0x001c) -/** Curve25519. +/** SEC Koblitz curves over prime fields. * - * This is the curve defined in Bernstein et al., - * _Curve25519: new Diffie-Hellman speed records_, LNCS 3958, 2006. - * The algorithm #PSA_ALG_ECDH performs X25519 when used with this curve. + * This family comprises the following curves: + * secp192k1, secp224k1, secp256k1. + * They are defined in _Standards for Efficient Cryptography_, + * _SEC 2: Recommended Elliptic Curve Domain Parameters_. + * https://www.secg.org/sec2-v2.pdf */ -#define PSA_ECC_CURVE_CURVE25519 ((psa_ecc_curve_t) 0x001d) -/** Curve448 - * - * This is the curve defined in Hamburg, - * _Ed448-Goldilocks, a new elliptic curve_, NIST ECC Workshop, 2015. - * The algorithm #PSA_ALG_ECDH performs X448 when used with this curve. - */ -#define PSA_ECC_CURVE_CURVE448 ((psa_ecc_curve_t) 0x001e) +#define PSA_ECC_CURVE_SECP_K1 ((psa_ecc_curve_t) 0x17) -/** Minimum value for a vendor-defined ECC curve identifier +/** SEC random curves over prime fields. * - * The range for vendor-defined curve identifiers is a subset of the IANA - * registry private use range, `0xfe00` - `0xfeff`. + * This family comprises the following curves: + * secp192k1, secp224r1, secp256r1, secp384r1, secp521r1. + * They are defined in _Standards for Efficient Cryptography_, + * _SEC 2: Recommended Elliptic Curve Domain Parameters_. + * https://www.secg.org/sec2-v2.pdf */ -#define PSA_ECC_CURVE_VENDOR_MIN ((psa_ecc_curve_t) 0xfe00) -/** Maximum value for a vendor-defined ECC curve identifier - * - * The range for vendor-defined curve identifiers is a subset of the IANA - * registry private use range, `0xfe00` - `0xfeff`. - */ -#define PSA_ECC_CURVE_VENDOR_MAX ((psa_ecc_curve_t) 0xfe7f) +#define PSA_ECC_CURVE_SECP_R1 ((psa_ecc_curve_t) 0x12) +/* SECP160R2 (SEC2 v1, obsolete) */ +#define PSA_ECC_CURVE_SECP_R2 ((psa_ecc_curve_t) 0x1b) -#define PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE ((psa_key_type_t)0x60040000) -#define PSA_KEY_TYPE_DH_KEY_PAIR_BASE ((psa_key_type_t)0x70040000) -#define PSA_KEY_TYPE_DH_GROUP_MASK ((psa_key_type_t)0x0000ffff) +/** SEC Koblitz curves over binary fields. + * + * This family comprises the following curves: + * sect163k1, sect233k1, sect239k1, sect283k1, sect409k1, sect571k1. + * They are defined in _Standards for Efficient Cryptography_, + * _SEC 2: Recommended Elliptic Curve Domain Parameters_. + * https://www.secg.org/sec2-v2.pdf + */ +#define PSA_ECC_CURVE_SECT_K1 ((psa_ecc_curve_t) 0x27) + +/** SEC random curves over binary fields. + * + * This family comprises the following curves: + * sect163r1, sect233r1, sect283r1, sect409r1, sect571r1. + * They are defined in _Standards for Efficient Cryptography_, + * _SEC 2: Recommended Elliptic Curve Domain Parameters_. + * https://www.secg.org/sec2-v2.pdf + */ +#define PSA_ECC_CURVE_SECT_R1 ((psa_ecc_curve_t) 0x22) + +/** SEC additional random curves over binary fields. + * + * This family comprises the following curve: + * sect163r2. + * It is defined in _Standards for Efficient Cryptography_, + * _SEC 2: Recommended Elliptic Curve Domain Parameters_. + * https://www.secg.org/sec2-v2.pdf + */ +#define PSA_ECC_CURVE_SECT_R2 ((psa_ecc_curve_t) 0x2b) + +/** Brainpool P random curves. + * + * This family comprises the following curves: + * brainpoolP160r1, brainpoolP192r1, brainpoolP224r1, brainpoolP256r1, + * brainpoolP320r1, brainpoolP384r1, brainpoolP512r1. + * It is defined in RFC 5639. + */ +#define PSA_ECC_CURVE_BRAINPOOL_P_R1 ((psa_ecc_curve_t) 0x30) + +/** Curve25519 and Curve448. + * + * This family comprises the following Montgomery curves: + * - 255-bit: Bernstein et al., + * _Curve25519: new Diffie-Hellman speed records_, LNCS 3958, 2006. + * The algorithm #PSA_ALG_ECDH performs X25519 when used with this curve. + * - 448-bit: Hamburg, + * _Ed448-Goldilocks, a new elliptic curve_, NIST ECC Workshop, 2015. + * The algorithm #PSA_ALG_ECDH performs X448 when used with this curve. + */ +#define PSA_ECC_CURVE_MONTGOMERY ((psa_ecc_curve_t) 0x41) + +#define PSA_KEY_TYPE_DH_PUBLIC_KEY_BASE ((psa_key_type_t)0x4200) +#define PSA_KEY_TYPE_DH_KEY_PAIR_BASE ((psa_key_type_t)0x7200) +#define PSA_KEY_TYPE_DH_GROUP_MASK ((psa_key_type_t)0x00ff) /** Diffie-Hellman key pair. * * \param group A value of type ::psa_dh_group_t that identifies the @@ -556,30 +568,16 @@ ((type) & PSA_KEY_TYPE_DH_GROUP_MASK) : \ 0)) -/* The encoding of group identifiers is currently aligned with the - * TLS Supported Groups Registry (formerly known as the - * TLS EC Named Curve Registry) - * https://www.iana.org/assignments/tls-parameters/tls-parameters.xhtml#tls-parameters-8 - * The values are defined by RFC 7919. */ -#define PSA_DH_GROUP_FFDHE2048 ((psa_dh_group_t) 0x0100) -#define PSA_DH_GROUP_FFDHE3072 ((psa_dh_group_t) 0x0101) -#define PSA_DH_GROUP_FFDHE4096 ((psa_dh_group_t) 0x0102) -#define PSA_DH_GROUP_FFDHE6144 ((psa_dh_group_t) 0x0103) -#define PSA_DH_GROUP_FFDHE8192 ((psa_dh_group_t) 0x0104) - -/** Minimum value for a vendor-defined Diffie Hellman group identifier +/** Diffie-Hellman groups defined in RFC 7919 Appendix A. * - * The range for vendor-defined group identifiers is a subset of the IANA - * registry private use range, `0x01fc` - `0x01ff`. + * This family includes groups with the following key sizes (in bits): + * 2048, 3072, 4096, 6144, 8192. A given implementation may support + * all of these sizes or only a subset. */ -#define PSA_DH_GROUP_VENDOR_MIN ((psa_dh_group_t) 0x01fc) -/** Maximum value for a vendor-defined Diffie Hellman group identifier - * - * The range for vendor-defined group identifiers is a subset of the IANA - * registry private use range, `0x01fc` - `0x01ff`. - */ -#define PSA_DH_GROUP_VENDOR_MAX ((psa_dh_group_t) 0x01fd) +#define PSA_DH_GROUP_RFC7919 ((psa_dh_group_t) 0x03) +#define PSA_GET_KEY_TYPE_BLOCK_SIZE_EXPONENT(type) \ + (((type) >> 8) & 7) /** The block size of a block cipher. * * \param type A cipher key type (value of type #psa_key_type_t). @@ -599,12 +597,9 @@ * \warning This macro may evaluate its argument multiple times. */ #define PSA_BLOCK_CIPHER_BLOCK_SIZE(type) \ - ( \ - (type) == PSA_KEY_TYPE_AES ? 16 : \ - (type) == PSA_KEY_TYPE_DES ? 8 : \ - (type) == PSA_KEY_TYPE_CAMELLIA ? 16 : \ - (type) == PSA_KEY_TYPE_ARC4 ? 1 : \ - 0) + (((type) & PSA_KEY_TYPE_CATEGORY_MASK) == PSA_KEY_TYPE_CATEGORY_SYMMETRIC ? \ + 1u << PSA_GET_KEY_TYPE_BLOCK_SIZE_EXPONENT(type) : \ + 0u) /** Vendor-defined algorithm flag. * @@ -766,17 +761,17 @@ * Then you may create and use a key as follows: * - Set the key usage field using #PSA_ALG_ANY_HASH, for example: * ``` - * psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_SIGN); // or VERIFY + * psa_set_key_usage_flags(&attributes, PSA_KEY_USAGE_SIGN_HASH); // or VERIFY * psa_set_key_algorithm(&attributes, PSA_xxx_SIGNATURE(PSA_ALG_ANY_HASH)); * ``` * - Import or generate key material. - * - Call psa_asymmetric_sign() or psa_asymmetric_verify(), passing + * - Call psa_sign_hash() or psa_verify_hash(), passing * an algorithm built from `PSA_xxx_SIGNATURE` and a specific hash. Each * call to sign or verify a message may use a different hash. * ``` - * psa_asymmetric_sign(handle, PSA_xxx_SIGNATURE(PSA_ALG_SHA_256), ...); - * psa_asymmetric_sign(handle, PSA_xxx_SIGNATURE(PSA_ALG_SHA_512), ...); - * psa_asymmetric_sign(handle, PSA_xxx_SIGNATURE(PSA_ALG_SHA3_256), ...); + * psa_sign_hash(handle, PSA_xxx_SIGNATURE(PSA_ALG_SHA_256), ...); + * psa_sign_hash(handle, PSA_xxx_SIGNATURE(PSA_ALG_SHA_512), ...); + * psa_sign_hash(handle, PSA_xxx_SIGNATURE(PSA_ALG_SHA3_256), ...); * ``` * * This value may not be used to build other algorithms that are @@ -1197,11 +1192,12 @@ */ #define PSA_ALG_DETERMINISTIC_ECDSA(hash_alg) \ (PSA_ALG_DETERMINISTIC_ECDSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) +#define PSA_ALG_ECDSA_DETERMINISTIC_FLAG ((psa_algorithm_t)0x00010000) #define PSA_ALG_IS_ECDSA(alg) \ - (((alg) & ~PSA_ALG_HASH_MASK & ~PSA_ALG_DSA_DETERMINISTIC_FLAG) == \ + (((alg) & ~PSA_ALG_HASH_MASK & ~PSA_ALG_ECDSA_DETERMINISTIC_FLAG) == \ PSA_ALG_ECDSA_BASE) #define PSA_ALG_ECDSA_IS_DETERMINISTIC(alg) \ - (((alg) & PSA_ALG_DSA_DETERMINISTIC_FLAG) != 0) + (((alg) & PSA_ALG_ECDSA_DETERMINISTIC_FLAG) != 0) #define PSA_ALG_IS_DETERMINISTIC_ECDSA(alg) \ (PSA_ALG_IS_ECDSA(alg) && PSA_ALG_ECDSA_IS_DETERMINISTIC(alg)) #define PSA_ALG_IS_RANDOMIZED_ECDSA(alg) \ @@ -1640,7 +1636,7 @@ * * For a key pair, this concerns the private key. */ -#define PSA_KEY_USAGE_SIGN ((psa_key_usage_t)0x00000400) +#define PSA_KEY_USAGE_SIGN_HASH ((psa_key_usage_t)0x00000400) /** Whether the key may be used to verify a message signature. * @@ -1650,7 +1646,7 @@ * * For a key pair, this concerns the public key. */ -#define PSA_KEY_USAGE_VERIFY ((psa_key_usage_t)0x00000800) +#define PSA_KEY_USAGE_VERIFY_HASH ((psa_key_usage_t)0x00000800) /** Whether the key may be used to derive other keys. */ diff --git a/features/mbedtls/mbed-crypto/platform/COMPONENT_PSA_SRV_IMPL/COMPONENT_NSPE/crypto_struct.h b/features/mbedtls/mbed-crypto/platform/COMPONENT_PSA_SRV_IMPL/COMPONENT_NSPE/crypto_struct.h index 9f55484e2f..938abd07b8 100644 --- a/features/mbedtls/mbed-crypto/platform/COMPONENT_PSA_SRV_IMPL/COMPONENT_NSPE/crypto_struct.h +++ b/features/mbedtls/mbed-crypto/platform/COMPONENT_PSA_SRV_IMPL/COMPONENT_NSPE/crypto_struct.h @@ -330,14 +330,14 @@ typedef uint16_t psa_key_attributes_flag_t; typedef struct { psa_key_type_t type; + psa_key_bits_t bits; psa_key_lifetime_t lifetime; psa_key_id_t id; psa_key_policy_t policy; - psa_key_bits_t bits; psa_key_attributes_flag_t flags; } psa_core_key_attributes_t; -#define PSA_CORE_KEY_ATTRIBUTES_INIT {0, 0, PSA_KEY_ID_INIT, PSA_KEY_POLICY_INIT, 0, 0} +#define PSA_CORE_KEY_ATTRIBUTES_INIT {PSA_KEY_TYPE_NONE, 0, PSA_KEY_LIFETIME_VOLATILE, PSA_KEY_ID_INIT, PSA_KEY_POLICY_INIT, 0} struct psa_key_attributes_s { diff --git a/features/mbedtls/mbed-crypto/platform/COMPONENT_PSA_SRV_IMPL/psa_crypto.c b/features/mbedtls/mbed-crypto/platform/COMPONENT_PSA_SRV_IMPL/psa_crypto.c index 42c2969bfd..733a2e46c4 100644 --- a/features/mbedtls/mbed-crypto/platform/COMPONENT_PSA_SRV_IMPL/psa_crypto.c +++ b/features/mbedtls/mbed-crypto/platform/COMPONENT_PSA_SRV_IMPL/psa_crypto.c @@ -75,6 +75,7 @@ #include "mbedtls/pk.h" #include "mbedtls/pk_internal.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include "mbedtls/ripemd160.h" #include "mbedtls/rsa.h" #include "mbedtls/sha1.h" @@ -351,6 +352,8 @@ static psa_status_t mbedtls_to_psa_error( int ret ) return( PSA_ERROR_INSUFFICIENT_MEMORY ); case MBEDTLS_ERR_ECP_HW_ACCEL_FAILED: return( PSA_ERROR_HARDWARE_FAILURE ); + case MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED: + return( PSA_ERROR_CORRUPTION_DETECTED ); default: return( PSA_ERROR_GENERIC_ERROR ); @@ -372,71 +375,118 @@ static inline int psa_key_slot_is_external( const psa_key_slot_t *slot ) #endif /* MBEDTLS_PSA_CRYPTO_SE_C */ #if defined(MBEDTLS_ECP_C) -static psa_ecc_curve_t mbedtls_ecc_group_to_psa( mbedtls_ecp_group_id grpid ) +psa_ecc_curve_t mbedtls_ecc_group_to_psa( mbedtls_ecp_group_id grpid, + size_t *bits ) { switch( grpid ) { case MBEDTLS_ECP_DP_SECP192R1: - return( PSA_ECC_CURVE_SECP192R1 ); + *bits = 192; + return( PSA_ECC_CURVE_SECP_R1 ); case MBEDTLS_ECP_DP_SECP224R1: - return( PSA_ECC_CURVE_SECP224R1 ); + *bits = 224; + return( PSA_ECC_CURVE_SECP_R1 ); case MBEDTLS_ECP_DP_SECP256R1: - return( PSA_ECC_CURVE_SECP256R1 ); + *bits = 256; + return( PSA_ECC_CURVE_SECP_R1 ); case MBEDTLS_ECP_DP_SECP384R1: - return( PSA_ECC_CURVE_SECP384R1 ); + *bits = 384; + return( PSA_ECC_CURVE_SECP_R1 ); case MBEDTLS_ECP_DP_SECP521R1: - return( PSA_ECC_CURVE_SECP521R1 ); + *bits = 521; + return( PSA_ECC_CURVE_SECP_R1 ); case MBEDTLS_ECP_DP_BP256R1: - return( PSA_ECC_CURVE_BRAINPOOL_P256R1 ); + *bits = 256; + return( PSA_ECC_CURVE_BRAINPOOL_P_R1 ); case MBEDTLS_ECP_DP_BP384R1: - return( PSA_ECC_CURVE_BRAINPOOL_P384R1 ); + *bits = 384; + return( PSA_ECC_CURVE_BRAINPOOL_P_R1 ); case MBEDTLS_ECP_DP_BP512R1: - return( PSA_ECC_CURVE_BRAINPOOL_P512R1 ); + *bits = 512; + return( PSA_ECC_CURVE_BRAINPOOL_P_R1 ); case MBEDTLS_ECP_DP_CURVE25519: - return( PSA_ECC_CURVE_CURVE25519 ); + *bits = 255; + return( PSA_ECC_CURVE_MONTGOMERY ); case MBEDTLS_ECP_DP_SECP192K1: - return( PSA_ECC_CURVE_SECP192K1 ); + *bits = 192; + return( PSA_ECC_CURVE_SECP_K1 ); case MBEDTLS_ECP_DP_SECP224K1: - return( PSA_ECC_CURVE_SECP224K1 ); + *bits = 224; + return( PSA_ECC_CURVE_SECP_K1 ); case MBEDTLS_ECP_DP_SECP256K1: - return( PSA_ECC_CURVE_SECP256K1 ); + *bits = 256; + return( PSA_ECC_CURVE_SECP_K1 ); case MBEDTLS_ECP_DP_CURVE448: - return( PSA_ECC_CURVE_CURVE448 ); + *bits = 448; + return( PSA_ECC_CURVE_MONTGOMERY ); default: return( 0 ); } } -static mbedtls_ecp_group_id mbedtls_ecc_group_of_psa( psa_ecc_curve_t curve ) +mbedtls_ecp_group_id mbedtls_ecc_group_of_psa( psa_ecc_curve_t curve, + size_t byte_length ) { switch( curve ) { - case PSA_ECC_CURVE_SECP192R1: - return( MBEDTLS_ECP_DP_SECP192R1 ); - case PSA_ECC_CURVE_SECP224R1: - return( MBEDTLS_ECP_DP_SECP224R1 ); - case PSA_ECC_CURVE_SECP256R1: - return( MBEDTLS_ECP_DP_SECP256R1 ); - case PSA_ECC_CURVE_SECP384R1: - return( MBEDTLS_ECP_DP_SECP384R1 ); - case PSA_ECC_CURVE_SECP521R1: - return( MBEDTLS_ECP_DP_SECP521R1 ); - case PSA_ECC_CURVE_BRAINPOOL_P256R1: - return( MBEDTLS_ECP_DP_BP256R1 ); - case PSA_ECC_CURVE_BRAINPOOL_P384R1: - return( MBEDTLS_ECP_DP_BP384R1 ); - case PSA_ECC_CURVE_BRAINPOOL_P512R1: - return( MBEDTLS_ECP_DP_BP512R1 ); - case PSA_ECC_CURVE_CURVE25519: - return( MBEDTLS_ECP_DP_CURVE25519 ); - case PSA_ECC_CURVE_SECP192K1: - return( MBEDTLS_ECP_DP_SECP192K1 ); - case PSA_ECC_CURVE_SECP224K1: - return( MBEDTLS_ECP_DP_SECP224K1 ); - case PSA_ECC_CURVE_SECP256K1: - return( MBEDTLS_ECP_DP_SECP256K1 ); - case PSA_ECC_CURVE_CURVE448: - return( MBEDTLS_ECP_DP_CURVE448 ); + case PSA_ECC_CURVE_SECP_R1: + switch( byte_length ) + { + case PSA_BITS_TO_BYTES( 192 ): + return( MBEDTLS_ECP_DP_SECP192R1 ); + case PSA_BITS_TO_BYTES( 224 ): + return( MBEDTLS_ECP_DP_SECP224R1 ); + case PSA_BITS_TO_BYTES( 256 ): + return( MBEDTLS_ECP_DP_SECP256R1 ); + case PSA_BITS_TO_BYTES( 384 ): + return( MBEDTLS_ECP_DP_SECP384R1 ); + case PSA_BITS_TO_BYTES( 521 ): + return( MBEDTLS_ECP_DP_SECP521R1 ); + default: + return( MBEDTLS_ECP_DP_NONE ); + } + break; + + case PSA_ECC_CURVE_BRAINPOOL_P_R1: + switch( byte_length ) + { + case PSA_BITS_TO_BYTES( 256 ): + return( MBEDTLS_ECP_DP_BP256R1 ); + case PSA_BITS_TO_BYTES( 384 ): + return( MBEDTLS_ECP_DP_BP384R1 ); + case PSA_BITS_TO_BYTES( 512 ): + return( MBEDTLS_ECP_DP_BP512R1 ); + default: + return( MBEDTLS_ECP_DP_NONE ); + } + break; + + case PSA_ECC_CURVE_MONTGOMERY: + switch( byte_length ) + { + case PSA_BITS_TO_BYTES( 255 ): + return( MBEDTLS_ECP_DP_CURVE25519 ); + case PSA_BITS_TO_BYTES( 448 ): + return( MBEDTLS_ECP_DP_CURVE448 ); + default: + return( MBEDTLS_ECP_DP_NONE ); + } + break; + + case PSA_ECC_CURVE_SECP_K1: + switch( byte_length ) + { + case PSA_BITS_TO_BYTES( 192 ): + return( MBEDTLS_ECP_DP_SECP192K1 ); + case PSA_BITS_TO_BYTES( 224 ): + return( MBEDTLS_ECP_DP_SECP224K1 ); + case PSA_BITS_TO_BYTES( 256 ): + return( MBEDTLS_ECP_DP_SECP256K1 ); + default: + return( MBEDTLS_ECP_DP_NONE ); + } + break; + default: return( MBEDTLS_ECP_DP_NONE ); } @@ -584,6 +634,37 @@ exit: #endif /* defined(MBEDTLS_RSA_C) && defined(MBEDTLS_PK_PARSE_C) */ #if defined(MBEDTLS_ECP_C) +static psa_status_t psa_prepare_import_ec_key( psa_ecc_curve_t curve, + size_t data_length, + int is_public, + mbedtls_ecp_keypair **p_ecp ) +{ + mbedtls_ecp_group_id grp_id = MBEDTLS_ECP_DP_NONE; + *p_ecp = mbedtls_calloc( 1, sizeof( mbedtls_ecp_keypair ) ); + if( *p_ecp == NULL ) + return( PSA_ERROR_INSUFFICIENT_MEMORY ); + mbedtls_ecp_keypair_init( *p_ecp ); + + if( is_public ) + { + /* A public key is represented as: + * - The byte 0x04; + * - `x_P` as a `ceiling(m/8)`-byte string, big-endian; + * - `y_P` as a `ceiling(m/8)`-byte string, big-endian. + * So its data length is 2m+1 where n is the key size in bits. + */ + if( ( data_length & 1 ) == 0 ) + return( PSA_ERROR_INVALID_ARGUMENT ); + data_length = data_length / 2; + } + + /* Load the group. */ + grp_id = mbedtls_ecc_group_of_psa( curve, data_length ); + if( grp_id == MBEDTLS_ECP_DP_NONE ) + return( PSA_ERROR_INVALID_ARGUMENT ); + return( mbedtls_to_psa_error( + mbedtls_ecp_group_load( &( *p_ecp )->grp, grp_id ) ) ); +} /* Import a public key given as the uncompressed representation defined by SEC1 * 2.3.3 as the content of an ECPoint. */ @@ -594,19 +675,11 @@ static psa_status_t psa_import_ec_public_key( psa_ecc_curve_t curve, { psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_keypair *ecp = NULL; - mbedtls_ecp_group_id grp_id = mbedtls_ecc_group_of_psa( curve ); - *p_ecp = NULL; - ecp = mbedtls_calloc( 1, sizeof( *ecp ) ); - if( ecp == NULL ) - return( PSA_ERROR_INSUFFICIENT_MEMORY ); - mbedtls_ecp_keypair_init( ecp ); - - /* Load the group. */ - status = mbedtls_to_psa_error( - mbedtls_ecp_group_load( &ecp->grp, grp_id ) ); + status = psa_prepare_import_ec_key( curve, data_length, 1, &ecp ); if( status != PSA_SUCCESS ) goto exit; + /* Load the public value. */ status = mbedtls_to_psa_error( mbedtls_ecp_point_read_binary( &ecp->grp, &ecp->Q, @@ -631,9 +704,7 @@ exit: } return( status ); } -#endif /* defined(MBEDTLS_ECP_C) */ -#if defined(MBEDTLS_ECP_C) /* Import a private key given as a byte string which is the private value * in big-endian order. */ static psa_status_t psa_import_ec_private_key( psa_ecc_curve_t curve, @@ -643,22 +714,11 @@ static psa_status_t psa_import_ec_private_key( psa_ecc_curve_t curve, { psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_keypair *ecp = NULL; - mbedtls_ecp_group_id grp_id = mbedtls_ecc_group_of_psa( curve ); - if( PSA_BITS_TO_BYTES( PSA_ECC_CURVE_BITS( curve ) ) != data_length ) - return( PSA_ERROR_INVALID_ARGUMENT ); - - *p_ecp = NULL; - ecp = mbedtls_calloc( 1, sizeof( mbedtls_ecp_keypair ) ); - if( ecp == NULL ) - return( PSA_ERROR_INSUFFICIENT_MEMORY ); - mbedtls_ecp_keypair_init( ecp ); - - /* Load the group. */ - status = mbedtls_to_psa_error( - mbedtls_ecp_group_load( &ecp->grp, grp_id ) ); + status = psa_prepare_import_ec_key( curve, data_length, 0, &ecp ); if( status != PSA_SUCCESS ) goto exit; + /* Load the secret value. */ status = mbedtls_to_psa_error( mbedtls_mpi_read_binary( &ecp->d, data, data_length ) ); @@ -1145,7 +1205,7 @@ static psa_status_t psa_get_rsa_public_exponent( psa_key_attributes_t *attributes ) { mbedtls_mpi mpi; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; uint8_t *buffer = NULL; size_t buflen; mbedtls_mpi_init( &mpi ); @@ -1249,7 +1309,7 @@ psa_status_t psa_get_key_slot_number( static int pk_write_pubkey_simple( mbedtls_pk_context *key, unsigned char *buf, size_t size ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *c; size_t len = 0; @@ -1334,7 +1394,7 @@ static psa_status_t psa_internal_export_key( const psa_key_slot_t *slot, PSA_KEY_TYPE_IS_ECC( slot->attr.type ) ) { mbedtls_pk_context pk; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( PSA_KEY_TYPE_IS_RSA( slot->attr.type ) ) { #if defined(MBEDTLS_RSA_C) @@ -1462,8 +1522,8 @@ static psa_status_t psa_validate_key_policy( const psa_key_policy_t *policy ) PSA_KEY_USAGE_COPY | PSA_KEY_USAGE_ENCRYPT | PSA_KEY_USAGE_DECRYPT | - PSA_KEY_USAGE_SIGN | - PSA_KEY_USAGE_VERIFY | + PSA_KEY_USAGE_SIGN_HASH | + PSA_KEY_USAGE_VERIFY_HASH | PSA_KEY_USAGE_DERIVE ) ) != 0 ) return( PSA_ERROR_INVALID_ARGUMENT ); @@ -1782,7 +1842,7 @@ static psa_status_t psa_validate_optional_attributes( if( PSA_KEY_TYPE_IS_RSA( slot->attr.type ) ) { mbedtls_mpi actual, required; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi_init( &actual ); mbedtls_mpi_init( &required ); ret = mbedtls_rsa_export( slot->data.rsa, @@ -2006,6 +2066,7 @@ exit: /* Message digests */ /****************************************************************/ +#if defined(MBEDTLS_RSA_C) || defined(MBEDTLS_ECDSA_DETERMINISTIC) static const mbedtls_md_info_t *mbedtls_md_info_from_psa( psa_algorithm_t alg ) { switch( alg ) @@ -2037,8 +2098,10 @@ static const mbedtls_md_info_t *mbedtls_md_info_from_psa( psa_algorithm_t alg ) return( &mbedtls_sha256_info ); #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case PSA_ALG_SHA_384: return( &mbedtls_sha384_info ); +#endif case PSA_ALG_SHA_512: return( &mbedtls_sha512_info ); #endif @@ -2046,6 +2109,7 @@ static const mbedtls_md_info_t *mbedtls_md_info_from_psa( psa_algorithm_t alg ) return( NULL ); } } +#endif psa_status_t psa_hash_abort( psa_hash_operation_t *operation ) { @@ -2088,7 +2152,9 @@ psa_status_t psa_hash_abort( psa_hash_operation_t *operation ) break; #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case PSA_ALG_SHA_384: +#endif case PSA_ALG_SHA_512: mbedtls_sha512_free( &operation->ctx.sha512 ); break; @@ -2103,7 +2169,7 @@ psa_status_t psa_hash_abort( psa_hash_operation_t *operation ) psa_status_t psa_hash_setup( psa_hash_operation_t *operation, psa_algorithm_t alg ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* A context must be freshly initialized before it can be set up. */ if( operation->alg != 0 ) @@ -2154,10 +2220,12 @@ psa_status_t psa_hash_setup( psa_hash_operation_t *operation, break; #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case PSA_ALG_SHA_384: mbedtls_sha512_init( &operation->ctx.sha512 ); ret = mbedtls_sha512_starts_ret( &operation->ctx.sha512, 1 ); break; +#endif case PSA_ALG_SHA_512: mbedtls_sha512_init( &operation->ctx.sha512 ); ret = mbedtls_sha512_starts_ret( &operation->ctx.sha512, 0 ); @@ -2179,7 +2247,7 @@ psa_status_t psa_hash_update( psa_hash_operation_t *operation, const uint8_t *input, size_t input_length ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* Don't require hash implementations to behave correctly on a * zero-length input, which may have an invalid pointer. */ @@ -2226,7 +2294,9 @@ psa_status_t psa_hash_update( psa_hash_operation_t *operation, break; #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case PSA_ALG_SHA_384: +#endif case PSA_ALG_SHA_512: ret = mbedtls_sha512_update_ret( &operation->ctx.sha512, input, input_length ); @@ -2247,7 +2317,7 @@ psa_status_t psa_hash_finish( psa_hash_operation_t *operation, size_t *hash_length ) { psa_status_t status; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t actual_hash_length = PSA_HASH_SIZE( operation->alg ); /* Fill the output buffer with something that isn't a valid hash @@ -2299,7 +2369,9 @@ psa_status_t psa_hash_finish( psa_hash_operation_t *operation, break; #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case PSA_ALG_SHA_384: +#endif case PSA_ALG_SHA_512: ret = mbedtls_sha512_finish_ret( &operation->ctx.sha512, hash ); break; @@ -2340,6 +2412,58 @@ psa_status_t psa_hash_verify( psa_hash_operation_t *operation, return( PSA_SUCCESS ); } +psa_status_t psa_hash_compute( psa_algorithm_t alg, + const uint8_t *input, size_t input_length, + uint8_t *hash, size_t hash_size, + size_t *hash_length ) +{ + psa_hash_operation_t operation = PSA_HASH_OPERATION_INIT; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + *hash_length = hash_size; + status = psa_hash_setup( &operation, alg ); + if( status != PSA_SUCCESS ) + goto exit; + status = psa_hash_update( &operation, input, input_length ); + if( status != PSA_SUCCESS ) + goto exit; + status = psa_hash_finish( &operation, hash, hash_size, hash_length ); + if( status != PSA_SUCCESS ) + goto exit; + +exit: + if( status == PSA_SUCCESS ) + status = psa_hash_abort( &operation ); + else + psa_hash_abort( &operation ); + return( status ); +} + +psa_status_t psa_hash_compare( psa_algorithm_t alg, + const uint8_t *input, size_t input_length, + const uint8_t *hash, size_t hash_length ) +{ + psa_hash_operation_t operation = PSA_HASH_OPERATION_INIT; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + status = psa_hash_setup( &operation, alg ); + if( status != PSA_SUCCESS ) + goto exit; + status = psa_hash_update( &operation, input, input_length ); + if( status != PSA_SUCCESS ) + goto exit; + status = psa_hash_verify( &operation, hash, hash_length ); + if( status != PSA_SUCCESS ) + goto exit; + +exit: + if( status == PSA_SUCCESS ) + status = psa_hash_abort( &operation ); + else + psa_hash_abort( &operation ); + return( status ); +} + psa_status_t psa_hash_clone( const psa_hash_operation_t *source_operation, psa_hash_operation_t *target_operation ) { @@ -2388,7 +2512,9 @@ psa_status_t psa_hash_clone( const psa_hash_operation_t *source_operation, break; #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case PSA_ALG_SHA_384: +#endif case PSA_ALG_SHA_512: mbedtls_sha512_clone( &target_operation->ctx.sha512, &source_operation->ctx.sha512 ); @@ -2630,7 +2756,7 @@ static int psa_cmac_setup( psa_mac_operation_t *operation, psa_key_slot_t *slot, const mbedtls_cipher_info_t *cipher_info ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; operation->mac_size = cipher_info->block_size; @@ -2672,14 +2798,8 @@ static psa_status_t psa_hmac_setup_internal( psa_hmac_internal_data *hmac, if( key_length > block_size ) { - status = psa_hash_setup( &hmac->hash_ctx, hash_alg ); - if( status != PSA_SUCCESS ) - goto cleanup; - status = psa_hash_update( &hmac->hash_ctx, key, key_length ); - if( status != PSA_SUCCESS ) - goto cleanup; - status = psa_hash_finish( &hmac->hash_ctx, - ipad, sizeof( ipad ), &key_length ); + status = psa_hash_compute( hash_alg, key, key_length, + ipad, sizeof( ipad ), &key_length ); if( status != PSA_SUCCESS ) goto cleanup; } @@ -2724,7 +2844,7 @@ static psa_status_t psa_mac_setup( psa_mac_operation_t *operation, psa_key_slot_t *slot; size_t key_bits; psa_key_usage_t usage = - is_sign ? PSA_KEY_USAGE_SIGN : PSA_KEY_USAGE_VERIFY; + is_sign ? PSA_KEY_USAGE_SIGN_HASH : PSA_KEY_USAGE_VERIFY_HASH; uint8_t truncated = PSA_MAC_TRUNCATED_LENGTH( alg ); psa_algorithm_t full_length_alg = PSA_ALG_FULL_LENGTH_MAC( alg ); @@ -2751,7 +2871,7 @@ static psa_status_t psa_mac_setup( psa_mac_operation_t *operation, const mbedtls_cipher_info_t *cipher_info = mbedtls_cipher_info_from_psa( full_length_alg, slot->attr.type, key_bits, NULL ); - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( cipher_info == NULL ) { status = PSA_ERROR_NOT_SUPPORTED; @@ -3029,6 +3149,8 @@ psa_status_t psa_mac_verify_finish( psa_mac_operation_t *operation, status = psa_mac_finish_internal( operation, actual_mac, sizeof( actual_mac ) ); + if( status != PSA_SUCCESS ) + goto cleanup; if( safer_memcmp( mac, actual_mac, mac_length ) != 0 ) status = PSA_ERROR_INVALID_SIGNATURE; @@ -3103,7 +3225,7 @@ static psa_status_t psa_rsa_sign( mbedtls_rsa_context *rsa, size_t *signature_length ) { psa_status_t status; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_md_type_t md_alg; status = psa_rsa_decode_md_type( alg, hash_length, &md_alg ); @@ -3161,7 +3283,7 @@ static psa_status_t psa_rsa_verify( mbedtls_rsa_context *rsa, size_t signature_length ) { psa_status_t status; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_md_type_t md_alg; status = psa_rsa_decode_md_type( alg, hash_length, &md_alg ); @@ -3227,7 +3349,7 @@ static psa_status_t psa_ecdsa_sign( mbedtls_ecp_keypair *ecp, size_t signature_size, size_t *signature_length ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi r, s; size_t curve_bytes = PSA_BITS_TO_BYTES( ecp->grp.pbits ); mbedtls_mpi_init( &r ); @@ -3282,7 +3404,7 @@ static psa_status_t psa_ecdsa_verify( mbedtls_ecp_keypair *ecp, const uint8_t *signature, size_t signature_length ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi r, s; size_t curve_bytes = PSA_BITS_TO_BYTES( ecp->grp.pbits ); mbedtls_mpi_init( &r ); @@ -3308,13 +3430,13 @@ cleanup: } #endif /* MBEDTLS_ECDSA_C */ -psa_status_t psa_asymmetric_sign( psa_key_handle_t handle, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length ) +psa_status_t psa_sign_hash( psa_key_handle_t handle, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length ) { psa_key_slot_t *slot; psa_status_t status; @@ -3331,7 +3453,7 @@ psa_status_t psa_asymmetric_sign( psa_key_handle_t handle, if( signature_size == 0 ) return( PSA_ERROR_BUFFER_TOO_SMALL ); - status = psa_get_key_from_slot( handle, &slot, PSA_KEY_USAGE_SIGN, alg ); + status = psa_get_key_from_slot( handle, &slot, PSA_KEY_USAGE_SIGN_HASH, alg ); if( status != PSA_SUCCESS ) goto exit; if( ! PSA_KEY_TYPE_IS_KEY_PAIR( slot->attr.type ) ) @@ -3412,12 +3534,12 @@ exit: return( status ); } -psa_status_t psa_asymmetric_verify( psa_key_handle_t handle, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - const uint8_t *signature, - size_t signature_length ) +psa_status_t psa_verify_hash( psa_key_handle_t handle, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length ) { psa_key_slot_t *slot; psa_status_t status; @@ -3426,7 +3548,7 @@ psa_status_t psa_asymmetric_verify( psa_key_handle_t handle, psa_drv_se_context_t *drv_context; #endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - status = psa_get_key_from_slot( handle, &slot, PSA_KEY_USAGE_VERIFY, alg ); + status = psa_get_key_from_slot( handle, &slot, PSA_KEY_USAGE_VERIFY_HASH, alg ); if( status != PSA_SUCCESS ) return( status ); @@ -3521,7 +3643,7 @@ psa_status_t psa_asymmetric_encrypt( psa_key_handle_t handle, if( PSA_KEY_TYPE_IS_RSA( slot->attr.type ) ) { mbedtls_rsa_context *rsa = slot->data.rsa; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( output_size < mbedtls_rsa_get_len( rsa ) ) return( PSA_ERROR_BUFFER_TOO_SMALL ); #if defined(MBEDTLS_PKCS1_V15) @@ -3600,7 +3722,7 @@ psa_status_t psa_asymmetric_decrypt( psa_key_handle_t handle, if( slot->attr.type == PSA_KEY_TYPE_RSA_KEY_PAIR ) { mbedtls_rsa_context *rsa = slot->data.rsa; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( input_length != mbedtls_rsa_get_len( rsa ) ) return( PSA_ERROR_INVALID_ARGUMENT ); @@ -3797,7 +3919,7 @@ psa_status_t psa_cipher_generate_iv( psa_cipher_operation_t *operation, size_t *iv_length ) { psa_status_t status; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( operation->iv_set || ! operation->iv_required ) { return( PSA_ERROR_BAD_STATE ); @@ -3829,7 +3951,7 @@ psa_status_t psa_cipher_set_iv( psa_cipher_operation_t *operation, size_t iv_length ) { psa_status_t status; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( operation->iv_set || ! operation->iv_required ) { return( PSA_ERROR_BAD_STATE ); @@ -3857,7 +3979,7 @@ psa_status_t psa_cipher_update( psa_cipher_operation_t *operation, size_t *output_length ) { psa_status_t status; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t expected_output_size; if( operation->alg == 0 ) @@ -5192,12 +5314,13 @@ static psa_status_t psa_key_agreement_ecdh( const uint8_t *peer_key, mbedtls_ecp_keypair *their_key = NULL; mbedtls_ecdh_context ecdh; psa_status_t status; + size_t bits = 0; + psa_ecc_curve_t curve = mbedtls_ecc_group_to_psa( our_key->grp.id, &bits ); mbedtls_ecdh_init( &ecdh ); - status = psa_import_ec_public_key( - mbedtls_ecc_group_to_psa( our_key->grp.id ), - peer_key, peer_key_length, - &their_key ); + status = psa_import_ec_public_key( curve, + peer_key, peer_key_length, + &their_key ); if( status != PSA_SUCCESS ) goto exit; @@ -5216,8 +5339,14 @@ static psa_status_t psa_key_agreement_ecdh( const uint8_t *peer_key, shared_secret, shared_secret_size, mbedtls_ctr_drbg_random, &global_data.ctr_drbg ) ); + if( status != PSA_SUCCESS ) + goto exit; + if( PSA_BITS_TO_BYTES( bits ) != *shared_secret_length ) + status = PSA_ERROR_CORRUPTION_DETECTED; exit: + if( status != PSA_SUCCESS ) + mbedtls_platform_zeroize( shared_secret, shared_secret_size ); mbedtls_ecdh_free( &ecdh ); mbedtls_ecp_keypair_free( their_key ); mbedtls_free( their_key ); @@ -5367,7 +5496,7 @@ exit: psa_status_t psa_generate_random( uint8_t *output, size_t output_size ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; GUARD_MODULE_INITIALIZED; while( output_size > MBEDTLS_CTR_DRBG_MAX_REQUEST ) @@ -5462,7 +5591,7 @@ static psa_status_t psa_generate_key_internal( if ( type == PSA_KEY_TYPE_RSA_KEY_PAIR ) { mbedtls_rsa_context *rsa; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; int exponent; psa_status_t status; if( bits > PSA_VENDOR_RSA_MAX_KEY_BITS ) @@ -5500,11 +5629,12 @@ static psa_status_t psa_generate_key_internal( if ( PSA_KEY_TYPE_IS_ECC( type ) && PSA_KEY_TYPE_IS_KEY_PAIR( type ) ) { psa_ecc_curve_t curve = PSA_KEY_TYPE_GET_CURVE( type ); - mbedtls_ecp_group_id grp_id = mbedtls_ecc_group_of_psa( curve ); + mbedtls_ecp_group_id grp_id = + mbedtls_ecc_group_of_psa( curve, PSA_BITS_TO_BYTES( bits ) ); const mbedtls_ecp_curve_info *curve_info = mbedtls_ecp_curve_info_from_grp_id( grp_id ); mbedtls_ecp_keypair *ecp; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( domain_parameters_size != 0 ) return( PSA_ERROR_NOT_SUPPORTED ); if( grp_id == MBEDTLS_ECP_DP_NONE || curve_info == NULL ) diff --git a/features/mbedtls/mbed-crypto/platform/COMPONENT_PSA_SRV_IMPL/psa_crypto_storage.c b/features/mbedtls/mbed-crypto/platform/COMPONENT_PSA_SRV_IMPL/psa_crypto_storage.c index a27442cd90..fa1214c86d 100644 --- a/features/mbedtls/mbed-crypto/platform/COMPONENT_PSA_SRV_IMPL/psa_crypto_storage.c +++ b/features/mbedtls/mbed-crypto/platform/COMPONENT_PSA_SRV_IMPL/psa_crypto_storage.c @@ -259,7 +259,9 @@ typedef struct { uint8_t magic[PSA_KEY_STORAGE_MAGIC_HEADER_LENGTH]; uint8_t version[4]; uint8_t lifetime[sizeof( psa_key_lifetime_t )]; - uint8_t type[sizeof( psa_key_type_t )]; + uint8_t type[4]; /* Size=4 for a 2-byte type to keep the structure more + * regular and aligned and to make potential future + * extensibility easier. */ uint8_t policy[sizeof( psa_key_policy_t )]; uint8_t data_len[4]; uint8_t key_data[]; @@ -276,7 +278,7 @@ void psa_format_key_data_for_storage( const uint8_t *data, memcpy( storage_format->magic, PSA_KEY_STORAGE_MAGIC_HEADER, PSA_KEY_STORAGE_MAGIC_HEADER_LENGTH ); PUT_UINT32_LE( 0, storage_format->version, 0 ); PUT_UINT32_LE( attr->lifetime, storage_format->lifetime, 0 ); - PUT_UINT32_LE( attr->type, storage_format->type, 0 ); + PUT_UINT32_LE( (uint32_t) attr->type, storage_format->type, 0 ); PUT_UINT32_LE( attr->policy.usage, storage_format->policy, 0 ); PUT_UINT32_LE( attr->policy.alg, storage_format->policy, sizeof( uint32_t ) ); PUT_UINT32_LE( attr->policy.alg2, storage_format->policy, 2 * sizeof( uint32_t ) ); @@ -302,6 +304,7 @@ psa_status_t psa_parse_key_data_from_storage( const uint8_t *storage_data, const psa_persistent_key_storage_format *storage_format = (const psa_persistent_key_storage_format *)storage_data; uint32_t version; + uint32_t type; if( storage_data_length < sizeof(*storage_format) ) return( PSA_ERROR_STORAGE_FAILURE ); @@ -332,7 +335,11 @@ psa_status_t psa_parse_key_data_from_storage( const uint8_t *storage_data, } GET_UINT32_LE( attr->lifetime, storage_format->lifetime, 0 ); - GET_UINT32_LE( attr->type, storage_format->type, 0 ); + GET_UINT32_LE( type, storage_format->type, 0 ); + if( type <= (psa_key_type_t) -1 ) + attr->type = (psa_key_type_t) type; + else + return( PSA_ERROR_STORAGE_FAILURE ); GET_UINT32_LE( attr->policy.usage, storage_format->policy, 0 ); GET_UINT32_LE( attr->policy.alg, storage_format->policy, sizeof( uint32_t ) ); GET_UINT32_LE( attr->policy.alg2, storage_format->policy, 2 * sizeof( uint32_t ) ); @@ -419,7 +426,7 @@ psa_status_t psa_crypto_save_transaction( void ) { struct psa_storage_info_t p_info; psa_status_t status; - status = psa_its_get_info( PSA_CRYPTO_ITS_RANDOM_SEED_UID, &p_info ); + status = psa_its_get_info( PSA_CRYPTO_ITS_TRANSACTION_UID, &p_info ); if( status == PSA_SUCCESS ) { /* This shouldn't happen: we're trying to start a transaction while diff --git a/features/mbedtls/mbed-crypto/platform/COMPONENT_SPE/crypto_struct_spe.h b/features/mbedtls/mbed-crypto/platform/COMPONENT_SPE/crypto_struct_spe.h index fa0466e6ca..35a25f1ff9 100644 --- a/features/mbedtls/mbed-crypto/platform/COMPONENT_SPE/crypto_struct_spe.h +++ b/features/mbedtls/mbed-crypto/platform/COMPONENT_SPE/crypto_struct_spe.h @@ -330,10 +330,10 @@ typedef uint16_t psa_key_attributes_flag_t; typedef struct { psa_key_type_t type; + psa_key_bits_t bits; psa_key_lifetime_t lifetime; psa_key_id_t id; psa_key_policy_t policy; - psa_key_bits_t bits; psa_key_attributes_flag_t flags; } psa_core_key_attributes_t; @@ -344,14 +344,14 @@ typedef struct typedef struct { psa_key_type_t type; + psa_key_bits_t bits; psa_key_lifetime_t lifetime; psa_app_key_id_t id; psa_key_policy_t policy; - psa_key_bits_t bits; - uint16_t flags; + psa_key_attributes_flag_t flags; } psa_client_core_key_attributes_t; -#define PSA_CORE_KEY_ATTRIBUTES_INIT {0, 0, PSA_KEY_ID_INIT, PSA_KEY_POLICY_INIT, 0, 0} +#define PSA_CORE_KEY_ATTRIBUTES_INIT {PSA_KEY_TYPE_NONE, 0, PSA_KEY_LIFETIME_VOLATILE, PSA_KEY_ID_INIT, PSA_KEY_POLICY_INIT, 0} struct psa_key_attributes_s { @@ -368,6 +368,7 @@ struct psa_key_attributes_s #else #define PSA_KEY_ATTRIBUTES_INIT {PSA_CORE_KEY_ATTRIBUTES_INIT, NULL, 0} #endif + typedef struct psa_client_key_attributes_s { psa_client_core_key_attributes_t core; diff --git a/features/mbedtls/mbed-crypto/src/aes.c b/features/mbedtls/mbed-crypto/src/aes.c index aff0a9939a..604d0f3d7f 100644 --- a/features/mbedtls/mbed-crypto/src/aes.c +++ b/features/mbedtls/mbed-crypto/src/aes.c @@ -38,6 +38,7 @@ #include "mbedtls/aes.h" #include "mbedtls/platform.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #if defined(MBEDTLS_PADLOCK_C) #include "mbedtls/padlock.h" #endif @@ -766,7 +767,7 @@ int mbedtls_aes_xts_setkey_enc( mbedtls_aes_xts_context *ctx, const unsigned char *key, unsigned int keybits) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const unsigned char *key1, *key2; unsigned int key1bits, key2bits; @@ -791,7 +792,7 @@ int mbedtls_aes_xts_setkey_dec( mbedtls_aes_xts_context *ctx, const unsigned char *key, unsigned int keybits) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const unsigned char *key1, *key2; unsigned int key1bits, key2bits; @@ -918,6 +919,18 @@ int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx, PUT_UINT32_LE( X2, output, 8 ); PUT_UINT32_LE( X3, output, 12 ); + mbedtls_platform_zeroize( &X0, sizeof( X0 ) ); + mbedtls_platform_zeroize( &X1, sizeof( X1 ) ); + mbedtls_platform_zeroize( &X2, sizeof( X2 ) ); + mbedtls_platform_zeroize( &X3, sizeof( X3 ) ); + + mbedtls_platform_zeroize( &Y0, sizeof( Y0 ) ); + mbedtls_platform_zeroize( &Y1, sizeof( Y1 ) ); + mbedtls_platform_zeroize( &Y2, sizeof( Y2 ) ); + mbedtls_platform_zeroize( &Y3, sizeof( Y3 ) ); + + mbedtls_platform_zeroize( &RK, sizeof( RK ) ); + return( 0 ); } #endif /* !MBEDTLS_AES_ENCRYPT_ALT */ @@ -986,6 +999,18 @@ int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx, PUT_UINT32_LE( X2, output, 8 ); PUT_UINT32_LE( X3, output, 12 ); + mbedtls_platform_zeroize( &X0, sizeof( X0 ) ); + mbedtls_platform_zeroize( &X1, sizeof( X1 ) ); + mbedtls_platform_zeroize( &X2, sizeof( X2 ) ); + mbedtls_platform_zeroize( &X3, sizeof( X3 ) ); + + mbedtls_platform_zeroize( &Y0, sizeof( Y0 ) ); + mbedtls_platform_zeroize( &Y1, sizeof( Y1 ) ); + mbedtls_platform_zeroize( &Y2, sizeof( Y2 ) ); + mbedtls_platform_zeroize( &Y3, sizeof( Y3 ) ); + + mbedtls_platform_zeroize( &RK, sizeof( RK ) ); + return( 0 ); } #endif /* !MBEDTLS_AES_DECRYPT_ALT */ @@ -1175,7 +1200,7 @@ int mbedtls_aes_crypt_xts( mbedtls_aes_xts_context *ctx, const unsigned char *input, unsigned char *output ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t blocks = length / 16; size_t leftover = length % 16; unsigned char tweak[16]; diff --git a/features/mbedtls/mbed-crypto/src/asn1parse.c b/features/mbedtls/mbed-crypto/src/asn1parse.c index 412259e358..34c660775d 100644 --- a/features/mbedtls/mbed-crypto/src/asn1parse.c +++ b/features/mbedtls/mbed-crypto/src/asn1parse.c @@ -29,6 +29,7 @@ #include "mbedtls/asn1.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -124,7 +125,7 @@ int mbedtls_asn1_get_bool( unsigned char **p, const unsigned char *end, int *val ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; if( ( ret = mbedtls_asn1_get_tag( p, end, &len, MBEDTLS_ASN1_BOOLEAN ) ) != 0 ) @@ -139,17 +140,20 @@ int mbedtls_asn1_get_bool( unsigned char **p, return( 0 ); } -int mbedtls_asn1_get_int( unsigned char **p, - const unsigned char *end, - int *val ) +static int asn1_get_tagged_int( unsigned char **p, + const unsigned char *end, + int tag, int *val ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; - if( ( ret = mbedtls_asn1_get_tag( p, end, &len, MBEDTLS_ASN1_INTEGER ) ) != 0 ) + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, tag ) ) != 0 ) return( ret ); - /* len==0 is malformed (0 must be represented as 020100). */ + /* + * len==0 is malformed (0 must be represented as 020100 for INTEGER, + * or 0A0100 for ENUMERATED tags + */ if( len == 0 ) return( MBEDTLS_ERR_ASN1_INVALID_LENGTH ); /* This is a cryptography library. Reject negative integers. */ @@ -180,12 +184,26 @@ int mbedtls_asn1_get_int( unsigned char **p, return( 0 ); } +int mbedtls_asn1_get_int( unsigned char **p, + const unsigned char *end, + int *val ) +{ + return( asn1_get_tagged_int( p, end, MBEDTLS_ASN1_INTEGER, val) ); +} + +int mbedtls_asn1_get_enum( unsigned char **p, + const unsigned char *end, + int *val ) +{ + return( asn1_get_tagged_int( p, end, MBEDTLS_ASN1_ENUMERATED, val) ); +} + #if defined(MBEDTLS_BIGNUM_C) int mbedtls_asn1_get_mpi( unsigned char **p, const unsigned char *end, mbedtls_mpi *X ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; if( ( ret = mbedtls_asn1_get_tag( p, end, &len, MBEDTLS_ASN1_INTEGER ) ) != 0 ) @@ -202,7 +220,7 @@ int mbedtls_asn1_get_mpi( unsigned char **p, int mbedtls_asn1_get_bitstring( unsigned char **p, const unsigned char *end, mbedtls_asn1_bitstring *bs) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* Certificate type is a single byte bitstring */ if( ( ret = mbedtls_asn1_get_tag( p, end, &bs->len, MBEDTLS_ASN1_BIT_STRING ) ) != 0 ) @@ -229,13 +247,65 @@ int mbedtls_asn1_get_bitstring( unsigned char **p, const unsigned char *end, return( 0 ); } +/* + * Traverse an ASN.1 "SEQUENCE OF " + * and call a callback for each entry found. + */ +int mbedtls_asn1_traverse_sequence_of( + unsigned char **p, + const unsigned char *end, + unsigned char tag_must_mask, unsigned char tag_must_val, + unsigned char tag_may_mask, unsigned char tag_may_val, + int (*cb)( void *ctx, int tag, + unsigned char *start, size_t len ), + void *ctx ) +{ + int ret; + size_t len; + + /* Get main sequence tag */ + if( ( ret = mbedtls_asn1_get_tag( p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) + { + return( ret ); + } + + if( *p + len != end ) + return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); + + while( *p < end ) + { + unsigned char const tag = *(*p)++; + + if( ( tag & tag_must_mask ) != tag_must_val ) + return( MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ); + + if( ( ret = mbedtls_asn1_get_len( p, end, &len ) ) != 0 ) + return( ret ); + + if( ( tag & tag_may_mask ) == tag_may_val ) + { + if( cb != NULL ) + { + ret = cb( ctx, tag, *p, len ); + if( ret != 0 ) + return( ret ); + } + } + + *p += len; + } + + return( 0 ); +} + /* * Get a bit string without unused bits */ int mbedtls_asn1_get_bitstring_null( unsigned char **p, const unsigned char *end, size_t *len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = mbedtls_asn1_get_tag( p, end, len, MBEDTLS_ASN1_BIT_STRING ) ) != 0 ) return( ret ); @@ -251,7 +321,51 @@ int mbedtls_asn1_get_bitstring_null( unsigned char **p, const unsigned char *end return( 0 ); } +void mbedtls_asn1_sequence_free( mbedtls_asn1_sequence *seq ) +{ + while( seq != NULL ) + { + mbedtls_asn1_sequence *next = seq->next; + mbedtls_platform_zeroize( seq, sizeof( *seq ) ); + mbedtls_free( seq ); + seq = next; + } +} +typedef struct +{ + int tag; + mbedtls_asn1_sequence *cur; +} asn1_get_sequence_of_cb_ctx_t; + +static int asn1_get_sequence_of_cb( void *ctx, + int tag, + unsigned char *start, + size_t len ) +{ + asn1_get_sequence_of_cb_ctx_t *cb_ctx = + (asn1_get_sequence_of_cb_ctx_t *) ctx; + mbedtls_asn1_sequence *cur = + cb_ctx->cur; + + if( cur->buf.p != NULL ) + { + cur->next = + mbedtls_calloc( 1, sizeof( mbedtls_asn1_sequence ) ); + + if( cur->next == NULL ) + return( MBEDTLS_ERR_ASN1_ALLOC_FAILED ); + + cur = cur->next; + } + + cur->buf.p = start; + cur->buf.len = len; + cur->buf.tag = tag; + + cb_ctx->cur = cur; + return( 0 ); +} /* * Parses and splits an ASN.1 "SEQUENCE OF " @@ -261,56 +375,18 @@ int mbedtls_asn1_get_sequence_of( unsigned char **p, mbedtls_asn1_sequence *cur, int tag) { - int ret; - size_t len; - mbedtls_asn1_buf *buf; - - /* Get main sequence tag */ - if( ( ret = mbedtls_asn1_get_tag( p, end, &len, - MBEDTLS_ASN1_CONSTRUCTED | MBEDTLS_ASN1_SEQUENCE ) ) != 0 ) - return( ret ); - - if( *p + len != end ) - return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); - - while( *p < end ) - { - buf = &(cur->buf); - buf->tag = **p; - - if( ( ret = mbedtls_asn1_get_tag( p, end, &buf->len, tag ) ) != 0 ) - return( ret ); - - buf->p = *p; - *p += buf->len; - - /* Allocate and assign next pointer */ - if( *p < end ) - { - cur->next = (mbedtls_asn1_sequence*)mbedtls_calloc( 1, - sizeof( mbedtls_asn1_sequence ) ); - - if( cur->next == NULL ) - return( MBEDTLS_ERR_ASN1_ALLOC_FAILED ); - - cur = cur->next; - } - } - - /* Set final sequence entry's next pointer to NULL */ - cur->next = NULL; - - if( *p != end ) - return( MBEDTLS_ERR_ASN1_LENGTH_MISMATCH ); - - return( 0 ); + asn1_get_sequence_of_cb_ctx_t cb_ctx = { tag, cur }; + memset( cur, 0, sizeof( mbedtls_asn1_sequence ) ); + return( mbedtls_asn1_traverse_sequence_of( + p, end, 0xFF, tag, 0, 0, + asn1_get_sequence_of_cb, &cb_ctx ) ); } int mbedtls_asn1_get_alg( unsigned char **p, const unsigned char *end, mbedtls_asn1_buf *alg, mbedtls_asn1_buf *params ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; if( ( ret = mbedtls_asn1_get_tag( p, end, &len, @@ -354,7 +430,7 @@ int mbedtls_asn1_get_alg_null( unsigned char **p, const unsigned char *end, mbedtls_asn1_buf *alg ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_asn1_buf params; memset( ¶ms, 0, sizeof(mbedtls_asn1_buf) ); diff --git a/features/mbedtls/mbed-crypto/src/asn1write.c b/features/mbedtls/mbed-crypto/src/asn1write.c index a138d0b75c..503db930b5 100644 --- a/features/mbedtls/mbed-crypto/src/asn1write.c +++ b/features/mbedtls/mbed-crypto/src/asn1write.c @@ -28,6 +28,7 @@ #if defined(MBEDTLS_ASN1_WRITE_C) #include "mbedtls/asn1write.h" +#include "mbedtls/error.h" #include @@ -131,7 +132,7 @@ int mbedtls_asn1_write_raw_buffer( unsigned char **p, unsigned char *start, #if defined(MBEDTLS_BIGNUM_C) int mbedtls_asn1_write_mpi( unsigned char **p, unsigned char *start, const mbedtls_mpi *X ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; // Write the MPI @@ -168,7 +169,7 @@ cleanup: int mbedtls_asn1_write_null( unsigned char **p, unsigned char *start ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; // Write NULL @@ -182,7 +183,7 @@ int mbedtls_asn1_write_null( unsigned char **p, unsigned char *start ) int mbedtls_asn1_write_oid( unsigned char **p, unsigned char *start, const char *oid, size_t oid_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_raw_buffer( p, start, @@ -197,7 +198,7 @@ int mbedtls_asn1_write_algorithm_identifier( unsigned char **p, unsigned char *s const char *oid, size_t oid_len, size_t par_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; if( par_len == 0 ) @@ -216,7 +217,7 @@ int mbedtls_asn1_write_algorithm_identifier( unsigned char **p, unsigned char *s int mbedtls_asn1_write_bool( unsigned char **p, unsigned char *start, int boolean ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; if( *p - start < 1 ) @@ -231,9 +232,9 @@ int mbedtls_asn1_write_bool( unsigned char **p, unsigned char *start, int boolea return( (int) len ); } -int mbedtls_asn1_write_int( unsigned char **p, unsigned char *start, int val ) +static int asn1_write_tagged_int( unsigned char **p, unsigned char *start, int val, int tag ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; do @@ -255,15 +256,25 @@ int mbedtls_asn1_write_int( unsigned char **p, unsigned char *start, int val ) } MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_len( p, start, len ) ); - MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_tag( p, start, MBEDTLS_ASN1_INTEGER ) ); + MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_tag( p, start, tag ) ); return( (int) len ); } +int mbedtls_asn1_write_int( unsigned char **p, unsigned char *start, int val ) +{ + return( asn1_write_tagged_int( p, start, val, MBEDTLS_ASN1_INTEGER ) ); +} + +int mbedtls_asn1_write_enum( unsigned char **p, unsigned char *start, int val ) +{ + return( asn1_write_tagged_int( p, start, val, MBEDTLS_ASN1_ENUMERATED ) ); +} + int mbedtls_asn1_write_tagged_string( unsigned char **p, unsigned char *start, int tag, const char *text, size_t text_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_raw_buffer( p, start, @@ -339,7 +350,7 @@ int mbedtls_asn1_write_named_bitstring( unsigned char **p, int mbedtls_asn1_write_bitstring( unsigned char **p, unsigned char *start, const unsigned char *buf, size_t bits ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; size_t unused_bits, byte_len; @@ -372,7 +383,7 @@ int mbedtls_asn1_write_bitstring( unsigned char **p, unsigned char *start, int mbedtls_asn1_write_octet_string( unsigned char **p, unsigned char *start, const unsigned char *buf, size_t size ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_raw_buffer( p, start, buf, size ) ); diff --git a/features/mbedtls/mbed-crypto/src/bignum.c b/features/mbedtls/mbed-crypto/src/bignum.c index d5bde8b2cb..d53aefd5b0 100644 --- a/features/mbedtls/mbed-crypto/src/bignum.c +++ b/features/mbedtls/mbed-crypto/src/bignum.c @@ -46,6 +46,7 @@ #include "mbedtls/bignum.h" #include "mbedtls/bn_mul.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -157,9 +158,10 @@ int mbedtls_mpi_shrink( mbedtls_mpi *X, size_t nblimbs ) if( nblimbs > MBEDTLS_MPI_MAX_LIMBS ) return( MBEDTLS_ERR_MPI_ALLOC_FAILED ); - /* Actually resize up in this case */ + /* Actually resize up if there are currently fewer than nblimbs limbs. */ if( X->n <= nblimbs ) return( mbedtls_mpi_grow( X, nblimbs ) ); + /* After this point, then X->n > nblimbs and in particular X->n > 0. */ for( i = X->n - 1; i > 0; i-- ) if( X->p[i] != 0 ) @@ -198,7 +200,7 @@ int mbedtls_mpi_copy( mbedtls_mpi *X, const mbedtls_mpi *Y ) if( X == Y ) return( 0 ); - if( Y->p == NULL ) + if( Y->n == 0 ) { mbedtls_mpi_free( X ); return( 0 ); @@ -314,7 +316,7 @@ cleanup: */ int mbedtls_mpi_lset( mbedtls_mpi *X, mbedtls_mpi_sint z ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; MPI_VALIDATE_RET( X != NULL ); MBEDTLS_MPI_CHK( mbedtls_mpi_grow( X, 1 ) ); @@ -457,7 +459,7 @@ static int mpi_get_digit( mbedtls_mpi_uint *d, int radix, char c ) */ int mbedtls_mpi_read_string( mbedtls_mpi *X, int radix, const char *s ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i, j, slen, n; mbedtls_mpi_uint d; mbedtls_mpi T; @@ -532,7 +534,7 @@ cleanup: static int mpi_write_hlp( mbedtls_mpi *X, int radix, char **p, const size_t buflen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi_uint r; size_t length = 0; char *p_end = *p + buflen; @@ -697,7 +699,7 @@ int mbedtls_mpi_read_file( mbedtls_mpi *X, int radix, FILE *fin ) */ int mbedtls_mpi_write_file( const char *p, const mbedtls_mpi *X, int radix, FILE *fout ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n, slen, plen; /* * Buffer should have space for (short) label and decimal formatted MPI, @@ -832,7 +834,7 @@ static void mpi_bigendian_to_host( mbedtls_mpi_uint * const p, size_t limbs ) int mbedtls_mpi_read_binary_le( mbedtls_mpi *X, const unsigned char *buf, size_t buflen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i; size_t const limbs = CHARS_TO_LIMBS( buflen ); @@ -864,7 +866,7 @@ cleanup: */ int mbedtls_mpi_read_binary( mbedtls_mpi *X, const unsigned char *buf, size_t buflen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t const limbs = CHARS_TO_LIMBS( buflen ); size_t const overhead = ( limbs * ciL ) - buflen; unsigned char *Xp; @@ -991,7 +993,7 @@ int mbedtls_mpi_write_binary( const mbedtls_mpi *X, */ int mbedtls_mpi_shift_l( mbedtls_mpi *X, size_t count ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i, v0, t1; mbedtls_mpi_uint r0 = 0, r1; MPI_VALIDATE_RET( X != NULL ); @@ -1148,6 +1150,107 @@ int mbedtls_mpi_cmp_mpi( const mbedtls_mpi *X, const mbedtls_mpi *Y ) return( 0 ); } +/** Decide if an integer is less than the other, without branches. + * + * \param x First integer. + * \param y Second integer. + * + * \return 1 if \p x is less than \p y, 0 otherwise + */ +static unsigned ct_lt_mpi_uint( const mbedtls_mpi_uint x, + const mbedtls_mpi_uint y ) +{ + mbedtls_mpi_uint ret; + mbedtls_mpi_uint cond; + + /* + * Check if the most significant bits (MSB) of the operands are different. + */ + cond = ( x ^ y ); + /* + * If the MSB are the same then the difference x-y will be negative (and + * have its MSB set to 1 during conversion to unsigned) if and only if x> ( biL - 1 ); + + return (unsigned) ret; +} + +/* + * Compare signed values in constant time + */ +int mbedtls_mpi_lt_mpi_ct( const mbedtls_mpi *X, const mbedtls_mpi *Y, + unsigned *ret ) +{ + size_t i; + /* The value of any of these variables is either 0 or 1 at all times. */ + unsigned cond, done, X_is_negative, Y_is_negative; + + MPI_VALIDATE_RET( X != NULL ); + MPI_VALIDATE_RET( Y != NULL ); + MPI_VALIDATE_RET( ret != NULL ); + + if( X->n != Y->n ) + return MBEDTLS_ERR_MPI_BAD_INPUT_DATA; + + /* + * Set sign_N to 1 if N >= 0, 0 if N < 0. + * We know that N->s == 1 if N >= 0 and N->s == -1 if N < 0. + */ + X_is_negative = ( X->s & 2 ) >> 1; + Y_is_negative = ( Y->s & 2 ) >> 1; + + /* + * If the signs are different, then the positive operand is the bigger. + * That is if X is negative (X_is_negative == 1), then X < Y is true and it + * is false if X is positive (X_is_negative == 0). + */ + cond = ( X_is_negative ^ Y_is_negative ); + *ret = cond & X_is_negative; + + /* + * This is a constant-time function. We might have the result, but we still + * need to go through the loop. Record if we have the result already. + */ + done = cond; + + for( i = X->n; i > 0; i-- ) + { + /* + * If Y->p[i - 1] < X->p[i - 1] then X < Y is true if and only if both + * X and Y are negative. + * + * Again even if we can make a decision, we just mark the result and + * the fact that we are done and continue looping. + */ + cond = ct_lt_mpi_uint( Y->p[i - 1], X->p[i - 1] ); + *ret |= cond & ( 1 - done ) & X_is_negative; + done |= cond; + + /* + * If X->p[i - 1] < Y->p[i - 1] then X < Y is true if and only if both + * X and Y are positive. + * + * Again even if we can make a decision, we just mark the result and + * the fact that we are done and continue looping. + */ + cond = ct_lt_mpi_uint( X->p[i - 1], Y->p[i - 1] ); + *ret |= cond & ( 1 - done ) & ( 1 - X_is_negative ); + done |= cond; + } + + return( 0 ); +} + /* * Compare signed values */ @@ -1170,7 +1273,7 @@ int mbedtls_mpi_cmp_int( const mbedtls_mpi *X, mbedtls_mpi_sint z ) */ int mbedtls_mpi_add_abs( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i, j; mbedtls_mpi_uint *o, *p, c, tmp; MPI_VALIDATE_RET( X != NULL ); @@ -1251,7 +1354,7 @@ static void mpi_sub_hlp( size_t n, mbedtls_mpi_uint *s, mbedtls_mpi_uint *d ) int mbedtls_mpi_sub_abs( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B ) { mbedtls_mpi TB; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n; MPI_VALIDATE_RET( X != NULL ); MPI_VALIDATE_RET( A != NULL ); @@ -1474,7 +1577,7 @@ void mpi_mul_hlp( size_t i, mbedtls_mpi_uint *s, mbedtls_mpi_uint *d, mbedtls_mp */ int mbedtls_mpi_mul_mpi( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *B ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i, j; mbedtls_mpi TA, TB; MPI_VALIDATE_RET( X != NULL ); @@ -1629,9 +1732,10 @@ static mbedtls_mpi_uint mbedtls_int_div_int( mbedtls_mpi_uint u1, int mbedtls_mpi_div_mpi( mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, const mbedtls_mpi *B ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i, n, t, k; mbedtls_mpi X, Y, Z, T1, T2; + mbedtls_mpi_uint TP2[3]; MPI_VALIDATE_RET( A != NULL ); MPI_VALIDATE_RET( B != NULL ); @@ -1639,7 +1743,17 @@ int mbedtls_mpi_div_mpi( mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, return( MBEDTLS_ERR_MPI_DIVISION_BY_ZERO ); mbedtls_mpi_init( &X ); mbedtls_mpi_init( &Y ); mbedtls_mpi_init( &Z ); - mbedtls_mpi_init( &T1 ); mbedtls_mpi_init( &T2 ); + mbedtls_mpi_init( &T1 ); + /* + * Avoid dynamic memory allocations for constant-size T2. + * + * T2 is used for comparison only and the 3 limbs are assigned explicitly, + * so nobody increase the size of the MPI and we're safe to use an on-stack + * buffer. + */ + T2.s = 1; + T2.n = sizeof( TP2 ) / sizeof( *TP2 ); + T2.p = TP2; if( mbedtls_mpi_cmp_abs( A, B ) < 0 ) { @@ -1655,7 +1769,6 @@ int mbedtls_mpi_div_mpi( mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &Z, A->n + 2 ) ); MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &Z, 0 ) ); MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &T1, 2 ) ); - MBEDTLS_MPI_CHK( mbedtls_mpi_grow( &T2, 3 ) ); k = mbedtls_mpi_bitlen( &Y ) % biL; if( k < biL - 1 ) @@ -1687,6 +1800,10 @@ int mbedtls_mpi_div_mpi( mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, Y.p[t], NULL); } + T2.p[0] = ( i < 2 ) ? 0 : X.p[i - 2]; + T2.p[1] = ( i < 1 ) ? 0 : X.p[i - 1]; + T2.p[2] = X.p[i]; + Z.p[i - t - 1]++; do { @@ -1696,11 +1813,6 @@ int mbedtls_mpi_div_mpi( mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, T1.p[0] = ( t < 1 ) ? 0 : Y.p[t - 1]; T1.p[1] = Y.p[t]; MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &T1, &T1, Z.p[i - t - 1] ) ); - - MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &T2, 0 ) ); - T2.p[0] = ( i < 2 ) ? 0 : X.p[i - 2]; - T2.p[1] = ( i < 1 ) ? 0 : X.p[i - 1]; - T2.p[2] = X.p[i]; } while( mbedtls_mpi_cmp_mpi( &T1, &T2 ) > 0 ); @@ -1736,7 +1848,8 @@ int mbedtls_mpi_div_mpi( mbedtls_mpi *Q, mbedtls_mpi *R, const mbedtls_mpi *A, cleanup: mbedtls_mpi_free( &X ); mbedtls_mpi_free( &Y ); mbedtls_mpi_free( &Z ); - mbedtls_mpi_free( &T1 ); mbedtls_mpi_free( &T2 ); + mbedtls_mpi_free( &T1 ); + mbedtls_platform_zeroize( TP2, sizeof( TP2 ) ); return( ret ); } @@ -1765,7 +1878,7 @@ int mbedtls_mpi_div_int( mbedtls_mpi *Q, mbedtls_mpi *R, */ int mbedtls_mpi_mod_mpi( mbedtls_mpi *R, const mbedtls_mpi *A, const mbedtls_mpi *B ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; MPI_VALIDATE_RET( R != NULL ); MPI_VALIDATE_RET( A != NULL ); MPI_VALIDATE_RET( B != NULL ); @@ -1927,7 +2040,7 @@ int mbedtls_mpi_exp_mod( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *E, const mbedtls_mpi *N, mbedtls_mpi *_RR ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t wbits, wsize, one = 1; size_t i, j, nblimbs; size_t bufsize, nbits; @@ -2142,7 +2255,7 @@ cleanup: */ int mbedtls_mpi_gcd( mbedtls_mpi *G, const mbedtls_mpi *A, const mbedtls_mpi *B ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t lz, lzt; mbedtls_mpi TA, TB; @@ -2204,7 +2317,7 @@ int mbedtls_mpi_fill_random( mbedtls_mpi *X, size_t size, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t const limbs = CHARS_TO_LIMBS( size ); size_t const overhead = ( limbs * ciL ) - size; unsigned char *Xp; @@ -2235,7 +2348,7 @@ cleanup: */ int mbedtls_mpi_inv_mod( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi *N ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi G, TA, TU, U1, U2, TB, TV, V1, V2; MPI_VALIDATE_RET( X != NULL ); MPI_VALIDATE_RET( A != NULL ); @@ -2488,7 +2601,7 @@ int mbedtls_mpi_is_prime_ext( const mbedtls_mpi *X, int rounds, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi XX; MPI_VALIDATE_RET( X != NULL ); MPI_VALIDATE_RET( f_rng != NULL ); diff --git a/features/mbedtls/mbed-crypto/src/ccm.c b/features/mbedtls/mbed-crypto/src/ccm.c index a7e360ecf4..eaef106a11 100644 --- a/features/mbedtls/mbed-crypto/src/ccm.c +++ b/features/mbedtls/mbed-crypto/src/ccm.c @@ -38,6 +38,7 @@ #include "mbedtls/ccm.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -74,7 +75,7 @@ int mbedtls_ccm_setkey( mbedtls_ccm_context *ctx, const unsigned char *key, unsigned int keybits ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const mbedtls_cipher_info_t *cipher_info; CCM_VALIDATE_RET( ctx != NULL ); @@ -156,7 +157,7 @@ static int ccm_auth_crypt( mbedtls_ccm_context *ctx, int mode, size_t length, const unsigned char *input, unsigned char *output, unsigned char *tag, size_t tag_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char i; unsigned char q; size_t len_left, olen; @@ -366,7 +367,7 @@ int mbedtls_ccm_star_auth_decrypt( mbedtls_ccm_context *ctx, size_t length, const unsigned char *input, unsigned char *output, const unsigned char *tag, size_t tag_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char check_tag[16]; unsigned char i; int diff; @@ -479,7 +480,7 @@ int mbedtls_ccm_self_test( int verbose ) unsigned char plaintext[CCM_SELFTEST_PT_MAX_LEN]; unsigned char ciphertext[CCM_SELFTEST_CT_MAX_LEN]; size_t i; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ccm_init( &ctx ); diff --git a/features/mbedtls/mbed-crypto/src/chacha20.c b/features/mbedtls/mbed-crypto/src/chacha20.c index 8a3610f0e0..343b2167cd 100644 --- a/features/mbedtls/mbed-crypto/src/chacha20.c +++ b/features/mbedtls/mbed-crypto/src/chacha20.c @@ -33,6 +33,7 @@ #include "mbedtls/chacha20.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include #include @@ -325,7 +326,7 @@ int mbedtls_chacha20_crypt( const unsigned char key[32], unsigned char* output ) { mbedtls_chacha20_context ctx; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; CHACHA20_VALIDATE_RET( key != NULL ); CHACHA20_VALIDATE_RET( nonce != NULL ); @@ -536,7 +537,7 @@ int mbedtls_chacha20_self_test( int verbose ) { unsigned char output[381]; unsigned i; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; for( i = 0U; i < 2U; i++ ) { diff --git a/features/mbedtls/mbed-crypto/src/chachapoly.c b/features/mbedtls/mbed-crypto/src/chachapoly.c index dc643dd618..f0af5ded26 100644 --- a/features/mbedtls/mbed-crypto/src/chachapoly.c +++ b/features/mbedtls/mbed-crypto/src/chachapoly.c @@ -30,6 +30,7 @@ #include "mbedtls/chachapoly.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -122,7 +123,7 @@ void mbedtls_chachapoly_free( mbedtls_chachapoly_context *ctx ) int mbedtls_chachapoly_setkey( mbedtls_chachapoly_context *ctx, const unsigned char key[32] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; CHACHAPOLY_VALIDATE_RET( ctx != NULL ); CHACHAPOLY_VALIDATE_RET( key != NULL ); @@ -135,7 +136,7 @@ int mbedtls_chachapoly_starts( mbedtls_chachapoly_context *ctx, const unsigned char nonce[12], mbedtls_chachapoly_mode_t mode ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char poly1305_key[64]; CHACHAPOLY_VALIDATE_RET( ctx != NULL ); CHACHAPOLY_VALIDATE_RET( nonce != NULL ); @@ -191,7 +192,7 @@ int mbedtls_chachapoly_update( mbedtls_chachapoly_context *ctx, const unsigned char *input, unsigned char *output ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; CHACHAPOLY_VALIDATE_RET( ctx != NULL ); CHACHAPOLY_VALIDATE_RET( len == 0 || input != NULL ); CHACHAPOLY_VALIDATE_RET( len == 0 || output != NULL ); @@ -240,7 +241,7 @@ int mbedtls_chachapoly_update( mbedtls_chachapoly_context *ctx, int mbedtls_chachapoly_finish( mbedtls_chachapoly_context *ctx, unsigned char mac[16] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char len_block[16]; CHACHAPOLY_VALIDATE_RET( ctx != NULL ); CHACHAPOLY_VALIDATE_RET( mac != NULL ); @@ -304,7 +305,7 @@ static int chachapoly_crypt_and_tag( mbedtls_chachapoly_context *ctx, unsigned char *output, unsigned char tag[16] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ret = mbedtls_chachapoly_starts( ctx, nonce, mode ); if( ret != 0 ) @@ -354,7 +355,7 @@ int mbedtls_chachapoly_auth_decrypt( mbedtls_chachapoly_context *ctx, const unsigned char *input, unsigned char *output ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char check_tag[16]; size_t i; int diff; @@ -492,7 +493,7 @@ int mbedtls_chachapoly_self_test( int verbose ) { mbedtls_chachapoly_context ctx; unsigned i; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char output[200]; unsigned char mac[16]; diff --git a/features/mbedtls/mbed-crypto/src/cipher.c b/features/mbedtls/mbed-crypto/src/cipher.c index 69079aae7a..409c3fe674 100644 --- a/features/mbedtls/mbed-crypto/src/cipher.c +++ b/features/mbedtls/mbed-crypto/src/cipher.c @@ -34,6 +34,7 @@ #include "mbedtls/cipher.h" #include "mbedtls/cipher_internal.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include #include @@ -504,7 +505,7 @@ int mbedtls_cipher_update_ad( mbedtls_cipher_context_t *ctx, int mbedtls_cipher_update( mbedtls_cipher_context_t *ctx, const unsigned char *input, size_t ilen, unsigned char *output, size_t *olen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t block_size; CIPHER_VALIDATE_RET( ctx != NULL ); @@ -526,6 +527,10 @@ int mbedtls_cipher_update( mbedtls_cipher_context_t *ctx, const unsigned char *i *olen = 0; block_size = mbedtls_cipher_get_block_size( ctx ); + if ( 0 == block_size ) + { + return( MBEDTLS_ERR_CIPHER_INVALID_CONTEXT ); + } if( ctx->cipher_info->mode == MBEDTLS_MODE_ECB ) { @@ -561,11 +566,6 @@ int mbedtls_cipher_update( mbedtls_cipher_context_t *ctx, const unsigned char *i } #endif - if ( 0 == block_size ) - { - return( MBEDTLS_ERR_CIPHER_INVALID_CONTEXT ); - } - if( input == output && ( ctx->unprocessed_len != 0 || ilen % block_size ) ) { @@ -624,11 +624,6 @@ int mbedtls_cipher_update( mbedtls_cipher_context_t *ctx, const unsigned char *i */ if( 0 != ilen ) { - if( 0 == block_size ) - { - return( MBEDTLS_ERR_CIPHER_INVALID_CONTEXT ); - } - /* Encryption: only cache partial blocks * Decryption w/ padding: always keep at least one whole block * Decryption w/o padding: only cache partial blocks @@ -1134,7 +1129,7 @@ int mbedtls_cipher_check_tag( mbedtls_cipher_context_t *ctx, const unsigned char *tag, size_t tag_len ) { unsigned char check_tag[16]; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; CIPHER_VALIDATE_RET( ctx != NULL ); CIPHER_VALIDATE_RET( tag_len == 0 || tag != NULL ); @@ -1211,7 +1206,7 @@ int mbedtls_cipher_crypt( mbedtls_cipher_context_t *ctx, const unsigned char *input, size_t ilen, unsigned char *output, size_t *olen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t finish_olen; CIPHER_VALIDATE_RET( ctx != NULL ); @@ -1455,7 +1450,7 @@ int mbedtls_cipher_auth_decrypt( mbedtls_cipher_context_t *ctx, #if defined(MBEDTLS_GCM_C) if( MBEDTLS_MODE_GCM == ctx->cipher_info->mode ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; *olen = ilen; ret = mbedtls_gcm_auth_decrypt( ctx->cipher_ctx, ilen, @@ -1471,7 +1466,7 @@ int mbedtls_cipher_auth_decrypt( mbedtls_cipher_context_t *ctx, #if defined(MBEDTLS_CCM_C) if( MBEDTLS_MODE_CCM == ctx->cipher_info->mode ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; *olen = ilen; ret = mbedtls_ccm_auth_decrypt( ctx->cipher_ctx, ilen, @@ -1487,7 +1482,7 @@ int mbedtls_cipher_auth_decrypt( mbedtls_cipher_context_t *ctx, #if defined(MBEDTLS_CHACHAPOLY_C) if ( MBEDTLS_CIPHER_CHACHA20_POLY1305 == ctx->cipher_info->type ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* ChachaPoly has fixed length nonce and MAC (tag) */ if ( ( iv_len != ctx->cipher_info->iv_size ) || diff --git a/features/mbedtls/mbed-crypto/src/cipher_wrap.c b/features/mbedtls/mbed-crypto/src/cipher_wrap.c index 7fc40b5f0c..a813426be2 100644 --- a/features/mbedtls/mbed-crypto/src/cipher_wrap.c +++ b/features/mbedtls/mbed-crypto/src/cipher_wrap.c @@ -32,6 +32,7 @@ #if defined(MBEDTLS_CIPHER_C) #include "mbedtls/cipher_internal.h" +#include "mbedtls/error.h" #if defined(MBEDTLS_CHACHAPOLY_C) #include "mbedtls/chachapoly.h" @@ -1916,7 +1917,7 @@ static int chacha20_stream_wrap( void *ctx, size_t length, const unsigned char *input, unsigned char *output ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ret = mbedtls_chacha20_update( ctx, length, input, output ); if( ret == MBEDTLS_ERR_CHACHA20_BAD_INPUT_DATA ) diff --git a/features/mbedtls/mbed-crypto/src/cmac.c b/features/mbedtls/mbed-crypto/src/cmac.c index 5d101e1c7d..642680d556 100644 --- a/features/mbedtls/mbed-crypto/src/cmac.c +++ b/features/mbedtls/mbed-crypto/src/cmac.c @@ -50,6 +50,7 @@ #include "mbedtls/cmac.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -136,7 +137,7 @@ static int cmac_multiply_by_u( unsigned char *output, static int cmac_generate_subkeys( mbedtls_cipher_context_t *ctx, unsigned char* K1, unsigned char* K2 ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char L[MBEDTLS_CIPHER_BLKSIZE_MAX]; size_t olen, block_size; @@ -315,7 +316,7 @@ int mbedtls_cipher_cmac_finish( mbedtls_cipher_context_t *ctx, unsigned char K1[MBEDTLS_CIPHER_BLKSIZE_MAX]; unsigned char K2[MBEDTLS_CIPHER_BLKSIZE_MAX]; unsigned char M_last[MBEDTLS_CIPHER_BLKSIZE_MAX]; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t olen, block_size; if( ctx == NULL || ctx->cipher_info == NULL || ctx->cmac_ctx == NULL || @@ -393,7 +394,7 @@ int mbedtls_cipher_cmac( const mbedtls_cipher_info_t *cipher_info, unsigned char *output ) { mbedtls_cipher_context_t ctx; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( cipher_info == NULL || key == NULL || input == NULL || output == NULL ) return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); @@ -427,7 +428,7 @@ int mbedtls_aes_cmac_prf_128( const unsigned char *key, size_t key_length, const unsigned char *input, size_t in_len, unsigned char *output ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const mbedtls_cipher_info_t *cipher_info; unsigned char zero_key[MBEDTLS_AES_BLOCK_SIZE]; unsigned char int_key[MBEDTLS_AES_BLOCK_SIZE]; @@ -894,7 +895,7 @@ exit: static int test_aes128_cmac_prf( int verbose ) { int i; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char output[MBEDTLS_AES_BLOCK_SIZE]; for( i = 0; i < NB_PRF_TESTS; i++ ) @@ -921,7 +922,7 @@ static int test_aes128_cmac_prf( int verbose ) int mbedtls_cmac_self_test( int verbose ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; #if defined(MBEDTLS_AES_C) /* AES-128 */ diff --git a/features/mbedtls/mbed-crypto/src/ctr_drbg.c b/features/mbedtls/mbed-crypto/src/ctr_drbg.c index 0db7beb29d..8a2920a328 100644 --- a/features/mbedtls/mbed-crypto/src/ctr_drbg.c +++ b/features/mbedtls/mbed-crypto/src/ctr_drbg.c @@ -34,6 +34,7 @@ #include "mbedtls/ctr_drbg.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -56,76 +57,15 @@ void mbedtls_ctr_drbg_init( mbedtls_ctr_drbg_context *ctx ) { memset( ctx, 0, sizeof( mbedtls_ctr_drbg_context ) ); + /* Indicate that the entropy nonce length is not set explicitly. + * See mbedtls_ctr_drbg_set_nonce_len(). */ + ctx->reseed_counter = -1; #if defined(MBEDTLS_THREADING_C) mbedtls_mutex_init( &ctx->mutex ); #endif } -/* - * Non-public function wrapped by mbedtls_ctr_drbg_seed(). Necessary to allow - * NIST tests to succeed (which require known length fixed entropy) - */ -/* CTR_DRBG_Instantiate with derivation function (SP 800-90A §10.2.1.3.2) - * mbedtls_ctr_drbg_seed_entropy_len(ctx, f_entropy, p_entropy, - * custom, len, entropy_len) - * implements - * CTR_DRBG_Instantiate(entropy_input, nonce, personalization_string, - * security_strength) -> initial_working_state - * with inputs - * custom[:len] = nonce || personalization_string - * where entropy_input comes from f_entropy for entropy_len bytes - * and with outputs - * ctx = initial_working_state - */ -int mbedtls_ctr_drbg_seed_entropy_len( - mbedtls_ctr_drbg_context *ctx, - int (*f_entropy)(void *, unsigned char *, size_t), - void *p_entropy, - const unsigned char *custom, - size_t len, - size_t entropy_len ) -{ - int ret; - unsigned char key[MBEDTLS_CTR_DRBG_KEYSIZE]; - - memset( key, 0, MBEDTLS_CTR_DRBG_KEYSIZE ); - - mbedtls_aes_init( &ctx->aes_ctx ); - - ctx->f_entropy = f_entropy; - ctx->p_entropy = p_entropy; - - ctx->entropy_len = entropy_len; - ctx->reseed_interval = MBEDTLS_CTR_DRBG_RESEED_INTERVAL; - - /* - * Initialize with an empty key - */ - if( ( ret = mbedtls_aes_setkey_enc( &ctx->aes_ctx, key, - MBEDTLS_CTR_DRBG_KEYBITS ) ) != 0 ) - { - return( ret ); - } - - if( ( ret = mbedtls_ctr_drbg_reseed( ctx, custom, len ) ) != 0 ) - { - return( ret ); - } - return( 0 ); -} - -int mbedtls_ctr_drbg_seed( mbedtls_ctr_drbg_context *ctx, - int (*f_entropy)(void *, unsigned char *, size_t), - void *p_entropy, - const unsigned char *custom, - size_t len ) -{ - return( mbedtls_ctr_drbg_seed_entropy_len( ctx, f_entropy, p_entropy, - custom, len, - MBEDTLS_CTR_DRBG_ENTROPY_LEN ) ); -} - void mbedtls_ctr_drbg_free( mbedtls_ctr_drbg_context *ctx ) { if( ctx == NULL ) @@ -150,6 +90,32 @@ void mbedtls_ctr_drbg_set_entropy_len( mbedtls_ctr_drbg_context *ctx, ctx->entropy_len = len; } +int mbedtls_ctr_drbg_set_nonce_len( mbedtls_ctr_drbg_context *ctx, + size_t len ) +{ + /* If mbedtls_ctr_drbg_seed() has already been called, it's + * too late. Return the error code that's closest to making sense. */ + if( ctx->f_entropy != NULL ) + return( MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED ); + + if( len > MBEDTLS_CTR_DRBG_MAX_SEED_INPUT ) + return( MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG ); +#if SIZE_MAX > INT_MAX + /* This shouldn't be an issue because + * MBEDTLS_CTR_DRBG_MAX_SEED_INPUT < INT_MAX in any sensible + * configuration, but make sure anyway. */ + if( len > INT_MAX ) + return( MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG ); +#endif + + /* For backward compatibility with Mbed TLS <= 2.19, store the + * entropy nonce length in a field that already exists, but isn't + * used until after the initial seeding. */ + /* Due to the capping of len above, the value fits in an int. */ + ctx->reseed_counter = (int) len; + return( 0 ); +} + void mbedtls_ctr_drbg_set_reseed_interval( mbedtls_ctr_drbg_context *ctx, int interval ) { @@ -354,7 +320,7 @@ int mbedtls_ctr_drbg_update_ret( mbedtls_ctr_drbg_context *ctx, size_t add_len ) { unsigned char add_input[MBEDTLS_CTR_DRBG_SEEDLEN]; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( add_len == 0 ) return( 0 ); @@ -383,7 +349,7 @@ void mbedtls_ctr_drbg_update( mbedtls_ctr_drbg_context *ctx, #endif /* MBEDTLS_DEPRECATED_REMOVED */ /* CTR_DRBG_Reseed with derivation function (SP 800-90A §10.2.1.4.2) - * mbedtls_ctr_drbg_reseed(ctx, additional, len) + * mbedtls_ctr_drbg_reseed(ctx, additional, len, nonce_len) * implements * CTR_DRBG_Reseed(working_state, entropy_input, additional_input) * -> new_working_state @@ -391,51 +357,57 @@ void mbedtls_ctr_drbg_update( mbedtls_ctr_drbg_context *ctx, * ctx contains working_state * additional[:len] = additional_input * and entropy_input comes from calling ctx->f_entropy + * for (ctx->entropy_len + nonce_len) bytes * and with output * ctx contains new_working_state */ -int mbedtls_ctr_drbg_reseed( mbedtls_ctr_drbg_context *ctx, - const unsigned char *additional, size_t len ) +static int mbedtls_ctr_drbg_reseed_internal( mbedtls_ctr_drbg_context *ctx, + const unsigned char *additional, + size_t len, + size_t nonce_len ) { unsigned char seed[MBEDTLS_CTR_DRBG_MAX_SEED_INPUT]; size_t seedlen = 0; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; - if( ctx->entropy_len > MBEDTLS_CTR_DRBG_MAX_SEED_INPUT || - len > MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - ctx->entropy_len ) + if( ctx->entropy_len > MBEDTLS_CTR_DRBG_MAX_SEED_INPUT ) + return( MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG ); + if( nonce_len > MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - ctx->entropy_len ) + return( MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG ); + if( len > MBEDTLS_CTR_DRBG_MAX_SEED_INPUT - ctx->entropy_len - nonce_len ) return( MBEDTLS_ERR_CTR_DRBG_INPUT_TOO_BIG ); memset( seed, 0, MBEDTLS_CTR_DRBG_MAX_SEED_INPUT ); - /* - * Gather entropy_len bytes of entropy to seed state - */ - if( 0 != ctx->f_entropy( ctx->p_entropy, seed, - ctx->entropy_len ) ) + /* Gather entropy_len bytes of entropy to seed state. */ + if( 0 != ctx->f_entropy( ctx->p_entropy, seed, ctx->entropy_len ) ) { return( MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED ); } - seedlen += ctx->entropy_len; - /* - * Add additional data - */ - if( additional && len ) + /* Gather entropy for a nonce if requested. */ + if( nonce_len != 0 ) + { + if( 0 != ctx->f_entropy( ctx->p_entropy, seed, nonce_len ) ) + { + return( MBEDTLS_ERR_CTR_DRBG_ENTROPY_SOURCE_FAILED ); + } + seedlen += nonce_len; + } + + /* Add additional data if provided. */ + if( additional != NULL && len != 0 ) { memcpy( seed + seedlen, additional, len ); seedlen += len; } - /* - * Reduce to 384 bits - */ + /* Reduce to 384 bits. */ if( ( ret = block_cipher_df( seed, seed, seedlen ) ) != 0 ) goto exit; - /* - * Update state - */ + /* Update state. */ if( ( ret = ctr_drbg_update_internal( ctx, seed ) ) != 0 ) goto exit; ctx->reseed_counter = 1; @@ -445,6 +417,81 @@ exit: return( ret ); } +int mbedtls_ctr_drbg_reseed( mbedtls_ctr_drbg_context *ctx, + const unsigned char *additional, size_t len ) +{ + return( mbedtls_ctr_drbg_reseed_internal( ctx, additional, len, 0 ) ); +} + +/* Return a "good" nonce length for CTR_DRBG. The chosen nonce length + * is sufficient to achieve the maximum security strength given the key + * size and entropy length. If there is enough entropy in the initial + * call to the entropy function to serve as both the entropy input and + * the nonce, don't make a second call to get a nonce. */ +static size_t good_nonce_len( size_t entropy_len ) +{ + if( entropy_len >= MBEDTLS_CTR_DRBG_KEYSIZE * 3 / 2 ) + return( 0 ); + else + return( ( entropy_len + 1 ) / 2 ); +} + +/* CTR_DRBG_Instantiate with derivation function (SP 800-90A §10.2.1.3.2) + * mbedtls_ctr_drbg_seed(ctx, f_entropy, p_entropy, custom, len) + * implements + * CTR_DRBG_Instantiate(entropy_input, nonce, personalization_string, + * security_strength) -> initial_working_state + * with inputs + * custom[:len] = nonce || personalization_string + * where entropy_input comes from f_entropy for ctx->entropy_len bytes + * and with outputs + * ctx = initial_working_state + */ +int mbedtls_ctr_drbg_seed( mbedtls_ctr_drbg_context *ctx, + int (*f_entropy)(void *, unsigned char *, size_t), + void *p_entropy, + const unsigned char *custom, + size_t len ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + unsigned char key[MBEDTLS_CTR_DRBG_KEYSIZE]; + size_t nonce_len; + + memset( key, 0, MBEDTLS_CTR_DRBG_KEYSIZE ); + + mbedtls_aes_init( &ctx->aes_ctx ); + + ctx->f_entropy = f_entropy; + ctx->p_entropy = p_entropy; + + if( ctx->entropy_len == 0 ) + ctx->entropy_len = MBEDTLS_CTR_DRBG_ENTROPY_LEN; + /* ctx->reseed_counter contains the desired amount of entropy to + * grab for a nonce (see mbedtls_ctr_drbg_set_nonce_len()). + * If it's -1, indicating that the entropy nonce length was not set + * explicitly, use a sufficiently large nonce for security. */ + nonce_len = ( ctx->reseed_counter >= 0 ? + (size_t) ctx->reseed_counter : + good_nonce_len( ctx->entropy_len ) ); + + ctx->reseed_interval = MBEDTLS_CTR_DRBG_RESEED_INTERVAL; + + /* Initialize with an empty key. */ + if( ( ret = mbedtls_aes_setkey_enc( &ctx->aes_ctx, key, + MBEDTLS_CTR_DRBG_KEYBITS ) ) != 0 ) + { + return( ret ); + } + + /* Do the initial seeding. */ + if( ( ret = mbedtls_ctr_drbg_reseed_internal( ctx, custom, len, + nonce_len ) ) != 0 ) + { + return( ret ); + } + return( 0 ); +} + /* CTR_DRBG_Generate with derivation function (SP 800-90A §10.2.1.5.2) * mbedtls_ctr_drbg_random_with_add(ctx, output, output_len, additional, add_len) * implements @@ -538,13 +585,13 @@ int mbedtls_ctr_drbg_random_with_add( void *p_rng, exit: mbedtls_platform_zeroize( add_input, sizeof( add_input ) ); mbedtls_platform_zeroize( tmp, sizeof( tmp ) ); - return( 0 ); + return( ret ); } int mbedtls_ctr_drbg_random( void *p_rng, unsigned char *output, size_t output_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ctr_drbg_context *ctx = (mbedtls_ctr_drbg_context *) p_rng; #if defined(MBEDTLS_THREADING_C) @@ -666,6 +713,15 @@ static const unsigned char nonce_pers_nopr[16] = { 0x1b, 0x54, 0xb8, 0xff, 0x06, 0x42, 0xbf, 0xf5, 0x21, 0xf1, 0x5c, 0x1c, 0x0b, 0x66, 0x5f, 0x3f }; +#if defined(MBEDTLS_CTR_DRBG_USE_128_BIT_KEY) +static const unsigned char result_pr[16] = + { 0x95, 0x3c, 0xa5, 0xbd, 0x44, 0x1, 0x34, 0xb7, + 0x13, 0x58, 0x3e, 0x6a, 0x6c, 0x7e, 0x88, 0x8a }; + +static const unsigned char result_nopr[16] = + { 0x6c, 0x25, 0x27, 0x95, 0xa3, 0x62, 0xd6, 0xdb, + 0x90, 0xfd, 0x69, 0xb5, 0x42, 0x9, 0x4b, 0x84 }; +#else /* MBEDTLS_CTR_DRBG_USE_128_BIT_KEY */ static const unsigned char result_pr[16] = { 0x34, 0x01, 0x16, 0x56, 0xb4, 0x29, 0x00, 0x8f, 0x35, 0x63, 0xec, 0xb5, 0xf2, 0x59, 0x07, 0x23 }; @@ -673,6 +729,7 @@ static const unsigned char result_pr[16] = static const unsigned char result_nopr[16] = { 0xa0, 0x54, 0x30, 0x3d, 0x8a, 0x7e, 0xa9, 0x88, 0x9d, 0x90, 0x3e, 0x07, 0x7c, 0x6f, 0x21, 0x8f }; +#endif /* MBEDTLS_CTR_DRBG_USE_128_BIT_KEY */ static size_t test_offset; static int ctr_drbg_self_test_entropy( void *data, unsigned char *buf, @@ -708,8 +765,12 @@ int mbedtls_ctr_drbg_self_test( int verbose ) mbedtls_printf( " CTR_DRBG (PR = TRUE) : " ); test_offset = 0; - CHK( mbedtls_ctr_drbg_seed_entropy_len( &ctx, ctr_drbg_self_test_entropy, - (void *) entropy_source_pr, nonce_pers_pr, 16, 32 ) ); + mbedtls_ctr_drbg_set_entropy_len( &ctx, 32 ); + mbedtls_ctr_drbg_set_nonce_len( &ctx, 0 ); + CHK( mbedtls_ctr_drbg_seed( &ctx, + ctr_drbg_self_test_entropy, + (void *) entropy_source_pr, + nonce_pers_pr, 16 ) ); mbedtls_ctr_drbg_set_prediction_resistance( &ctx, MBEDTLS_CTR_DRBG_PR_ON ); CHK( mbedtls_ctr_drbg_random( &ctx, buf, MBEDTLS_CTR_DRBG_BLOCKSIZE ) ); CHK( mbedtls_ctr_drbg_random( &ctx, buf, MBEDTLS_CTR_DRBG_BLOCKSIZE ) ); @@ -729,8 +790,12 @@ int mbedtls_ctr_drbg_self_test( int verbose ) mbedtls_ctr_drbg_init( &ctx ); test_offset = 0; - CHK( mbedtls_ctr_drbg_seed_entropy_len( &ctx, ctr_drbg_self_test_entropy, - (void *) entropy_source_nopr, nonce_pers_nopr, 16, 32 ) ); + mbedtls_ctr_drbg_set_entropy_len( &ctx, 32 ); + mbedtls_ctr_drbg_set_nonce_len( &ctx, 0 ); + CHK( mbedtls_ctr_drbg_seed( &ctx, + ctr_drbg_self_test_entropy, + (void *) entropy_source_nopr, + nonce_pers_nopr, 16 ) ); CHK( mbedtls_ctr_drbg_random( &ctx, buf, 16 ) ); CHK( mbedtls_ctr_drbg_reseed( &ctx, NULL, 0 ) ); CHK( mbedtls_ctr_drbg_random( &ctx, buf, 16 ) ); diff --git a/features/mbedtls/mbed-crypto/src/dhm.c b/features/mbedtls/mbed-crypto/src/dhm.c index 8255632a99..392ed0c150 100644 --- a/features/mbedtls/mbed-crypto/src/dhm.c +++ b/features/mbedtls/mbed-crypto/src/dhm.c @@ -37,6 +37,7 @@ #include "mbedtls/dhm.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -137,7 +138,7 @@ int mbedtls_dhm_read_params( mbedtls_dhm_context *ctx, unsigned char **p, const unsigned char *end ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; DHM_VALIDATE_RET( ctx != NULL ); DHM_VALIDATE_RET( p != NULL && *p != NULL ); DHM_VALIDATE_RET( end != NULL ); @@ -239,7 +240,7 @@ int mbedtls_dhm_set_group( mbedtls_dhm_context *ctx, const mbedtls_mpi *P, const mbedtls_mpi *G ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; DHM_VALIDATE_RET( ctx != NULL ); DHM_VALIDATE_RET( P != NULL ); DHM_VALIDATE_RET( G != NULL ); @@ -260,7 +261,7 @@ int mbedtls_dhm_set_group( mbedtls_dhm_context *ctx, int mbedtls_dhm_read_public( mbedtls_dhm_context *ctx, const unsigned char *input, size_t ilen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; DHM_VALIDATE_RET( ctx != NULL ); DHM_VALIDATE_RET( input != NULL ); @@ -396,7 +397,7 @@ int mbedtls_dhm_calc_secret( mbedtls_dhm_context *ctx, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi GYb; DHM_VALIDATE_RET( ctx != NULL ); DHM_VALIDATE_RET( output != NULL ); @@ -473,7 +474,7 @@ void mbedtls_dhm_free( mbedtls_dhm_context *ctx ) int mbedtls_dhm_parse_dhm( mbedtls_dhm_context *dhm, const unsigned char *dhmin, size_t dhminlen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; unsigned char *p, *end; #if defined(MBEDTLS_PEM_PARSE_C) @@ -627,7 +628,7 @@ static int load_file( const char *path, unsigned char **buf, size_t *n ) */ int mbedtls_dhm_parse_dhmfile( mbedtls_dhm_context *dhm, const char *path ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n; unsigned char *buf; DHM_VALIDATE_RET( dhm != NULL ); @@ -679,7 +680,7 @@ static const size_t mbedtls_test_dhm_params_len = sizeof( mbedtls_test_dhm_param */ int mbedtls_dhm_self_test( int verbose ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_dhm_context dhm; mbedtls_dhm_init( &dhm ); diff --git a/features/mbedtls/mbed-crypto/src/ecdh.c b/features/mbedtls/mbed-crypto/src/ecdh.c index 914eb5055d..3cf5333712 100644 --- a/features/mbedtls/mbed-crypto/src/ecdh.c +++ b/features/mbedtls/mbed-crypto/src/ecdh.c @@ -36,6 +36,7 @@ #include "mbedtls/ecdh.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -80,7 +81,7 @@ static int ecdh_gen_public_restartable( mbedtls_ecp_group *grp, void *p_rng, mbedtls_ecp_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* If multiplication is in progress, we already generated a privkey */ #if defined(MBEDTLS_ECP_RESTARTABLE) @@ -121,7 +122,7 @@ static int ecdh_compute_shared_restartable( mbedtls_ecp_group *grp, void *p_rng, mbedtls_ecp_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_point P; mbedtls_ecp_point_init( &P ); @@ -199,7 +200,7 @@ void mbedtls_ecdh_init( mbedtls_ecdh_context *ctx ) static int ecdh_setup_internal( mbedtls_ecdh_context_mbed *ctx, mbedtls_ecp_group_id grp_id ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ret = mbedtls_ecp_group_load( &ctx->grp, grp_id ); if( ret != 0 ) @@ -307,7 +308,7 @@ static int ecdh_make_params_internal( mbedtls_ecdh_context_mbed *ctx, void *p_rng, int restart_enabled ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t grp_len, pt_len; #if defined(MBEDTLS_ECP_RESTARTABLE) mbedtls_ecp_restart_ctx *rs_ctx = NULL; @@ -414,7 +415,7 @@ int mbedtls_ecdh_read_params( mbedtls_ecdh_context *ctx, const unsigned char **buf, const unsigned char *end ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_group_id grp_id; ECDH_VALIDATE_RET( ctx != NULL ); ECDH_VALIDATE_RET( buf != NULL ); @@ -451,7 +452,7 @@ static int ecdh_get_params_internal( mbedtls_ecdh_context_mbed *ctx, const mbedtls_ecp_keypair *key, mbedtls_ecdh_side side ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* If it's not our key, just import the public part as Qp */ if( side == MBEDTLS_ECDH_THEIRS ) @@ -475,7 +476,7 @@ int mbedtls_ecdh_get_params( mbedtls_ecdh_context *ctx, const mbedtls_ecp_keypair *key, mbedtls_ecdh_side side ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ECDH_VALIDATE_RET( ctx != NULL ); ECDH_VALIDATE_RET( key != NULL ); ECDH_VALIDATE_RET( side == MBEDTLS_ECDH_OURS || @@ -530,7 +531,7 @@ static int ecdh_make_public_internal( mbedtls_ecdh_context_mbed *ctx, void *p_rng, int restart_enabled ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; #if defined(MBEDTLS_ECP_RESTARTABLE) mbedtls_ecp_restart_ctx *rs_ctx = NULL; #endif @@ -602,7 +603,7 @@ int mbedtls_ecdh_make_public( mbedtls_ecdh_context *ctx, size_t *olen, static int ecdh_read_public_internal( mbedtls_ecdh_context_mbed *ctx, const unsigned char *buf, size_t blen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const unsigned char *p = buf; if( ( ret = mbedtls_ecp_tls_read_point( &ctx->grp, &ctx->Qp, &p, @@ -652,7 +653,7 @@ static int ecdh_calc_secret_internal( mbedtls_ecdh_context_mbed *ctx, void *p_rng, int restart_enabled ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; #if defined(MBEDTLS_ECP_RESTARTABLE) mbedtls_ecp_restart_ctx *rs_ctx = NULL; #endif diff --git a/features/mbedtls/mbed-crypto/src/ecdsa.c b/features/mbedtls/mbed-crypto/src/ecdsa.c index bda9262c9e..5acd2d00e8 100644 --- a/features/mbedtls/mbed-crypto/src/ecdsa.c +++ b/features/mbedtls/mbed-crypto/src/ecdsa.c @@ -51,6 +51,7 @@ #endif #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" /* Parameter validation macros based on platform_util.h */ #define ECDSA_VALIDATE_RET( cond ) \ @@ -229,7 +230,7 @@ static void ecdsa_restart_det_free( mbedtls_ecdsa_restart_det_ctx *ctx ) static int derive_mpi( const mbedtls_ecp_group *grp, mbedtls_mpi *x, const unsigned char *buf, size_t blen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n_size = ( grp->nbits + 7 ) / 8; size_t use_size = blen > n_size ? n_size : blen; @@ -297,7 +298,7 @@ static int ecdsa_sign_restartable( mbedtls_ecp_group *grp, *p_sign_tries = 0; do { - if( *p_sign_tries++ > 10 ) + if( (*p_sign_tries)++ > 10 ) { ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; goto cleanup; @@ -310,7 +311,7 @@ static int ecdsa_sign_restartable( mbedtls_ecp_group *grp, *p_key_tries = 0; do { - if( *p_key_tries++ > 10 ) + if( (*p_key_tries)++ > 10 ) { ret = MBEDTLS_ERR_ECP_RANDOM_FAILED; goto cleanup; @@ -363,6 +364,7 @@ modn: MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &e, &e, s ) ); MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &e, &e, &t ) ); MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( pk, pk, &t ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( pk, pk, &grp->N ) ); MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( s, pk, &grp->N ) ); MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( s, s, &e ) ); MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( s, s, &grp->N ) ); @@ -429,7 +431,7 @@ static int ecdsa_sign_det_restartable( mbedtls_ecp_group *grp, void *p_rng_blind, mbedtls_ecdsa_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_hmac_drbg_context rng_ctx; mbedtls_hmac_drbg_context *p_rng = &rng_ctx; unsigned char data[2 * MBEDTLS_ECP_MAX_BYTES]; @@ -599,7 +601,7 @@ static int ecdsa_verify_restartable( mbedtls_ecp_group *grp, const mbedtls_mpi *r, const mbedtls_mpi *s, mbedtls_ecdsa_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi e, s_inv, u1, u2; mbedtls_ecp_point R; mbedtls_mpi *pu1 = &u1, *pu2 = &u2; @@ -723,7 +725,7 @@ int mbedtls_ecdsa_verify( mbedtls_ecp_group *grp, static int ecdsa_signature_to_asn1( const mbedtls_mpi *r, const mbedtls_mpi *s, unsigned char *sig, size_t *slen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char buf[MBEDTLS_ECDSA_MAX_LEN]; unsigned char *p = buf + sizeof( buf ); size_t len = 0; @@ -752,7 +754,7 @@ int mbedtls_ecdsa_write_signature_restartable( mbedtls_ecdsa_context *ctx, void *p_rng, mbedtls_ecdsa_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi r, s; ECDSA_VALIDATE_RET( ctx != NULL ); ECDSA_VALIDATE_RET( hash != NULL ); @@ -845,7 +847,7 @@ int mbedtls_ecdsa_read_signature_restartable( mbedtls_ecdsa_context *ctx, const unsigned char *sig, size_t slen, mbedtls_ecdsa_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *p = (unsigned char *) sig; const unsigned char *end = sig + slen; size_t len; @@ -925,7 +927,7 @@ int mbedtls_ecdsa_genkey( mbedtls_ecdsa_context *ctx, mbedtls_ecp_group_id gid, */ int mbedtls_ecdsa_from_keypair( mbedtls_ecdsa_context *ctx, const mbedtls_ecp_keypair *key ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ECDSA_VALIDATE_RET( ctx != NULL ); ECDSA_VALIDATE_RET( key != NULL ); diff --git a/features/mbedtls/mbed-crypto/src/ecjpake.c b/features/mbedtls/mbed-crypto/src/ecjpake.c index 1845c936ab..79ea3cbec4 100644 --- a/features/mbedtls/mbed-crypto/src/ecjpake.c +++ b/features/mbedtls/mbed-crypto/src/ecjpake.c @@ -34,6 +34,7 @@ #include "mbedtls/ecjpake.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -110,7 +111,7 @@ int mbedtls_ecjpake_setup( mbedtls_ecjpake_context *ctx, const unsigned char *secret, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ECJPAKE_VALIDATE_RET( ctx != NULL ); ECJPAKE_VALIDATE_RET( role == MBEDTLS_ECJPAKE_CLIENT || @@ -159,7 +160,7 @@ static int ecjpake_write_len_point( unsigned char **p, const int pf, const mbedtls_ecp_point *P ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; /* Need at least 4 for length plus 1 for point */ @@ -199,7 +200,7 @@ static int ecjpake_hash( const mbedtls_md_info_t *md_info, const char *id, mbedtls_mpi *h ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char buf[ECJPAKE_HASH_BUF_LEN]; unsigned char *p = buf; const unsigned char *end = buf + sizeof( buf ); @@ -249,7 +250,7 @@ static int ecjpake_zkp_read( const mbedtls_md_info_t *md_info, const unsigned char **p, const unsigned char *end ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_point V, VV; mbedtls_mpi r, h; size_t r_len; @@ -324,7 +325,7 @@ static int ecjpake_zkp_write( const mbedtls_md_info_t *md_info, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_point V; mbedtls_mpi v; mbedtls_mpi h; /* later recycled to hold r */ @@ -382,7 +383,7 @@ static int ecjpake_kkp_read( const mbedtls_md_info_t *md_info, const unsigned char **p, const unsigned char *end ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( end < *p ) return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); @@ -422,7 +423,7 @@ static int ecjpake_kkp_write( const mbedtls_md_info_t *md_info, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; if( end < *p ) @@ -457,7 +458,7 @@ static int ecjpake_kkpp_read( const mbedtls_md_info_t *md_info, const unsigned char *buf, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const unsigned char *p = buf; const unsigned char *end = buf + len; @@ -495,7 +496,7 @@ static int ecjpake_kkpp_write( const mbedtls_md_info_t *md_info, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *p = buf; const unsigned char *end = buf + len; @@ -553,7 +554,7 @@ static int ecjpake_ecp_add3( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, const mbedtls_ecp_point *B, const mbedtls_ecp_point *C ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi one; mbedtls_mpi_init( &one ); @@ -575,7 +576,7 @@ int mbedtls_ecjpake_read_round_two( mbedtls_ecjpake_context *ctx, const unsigned char *buf, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const unsigned char *p = buf; const unsigned char *end = buf + len; mbedtls_ecp_group grp; @@ -639,7 +640,7 @@ static int ecjpake_mul_secret( mbedtls_mpi *R, int sign, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi b; /* Blinding value, then s + N * blinding */ mbedtls_mpi_init( &b ); @@ -668,7 +669,7 @@ int mbedtls_ecjpake_write_round_two( mbedtls_ecjpake_context *ctx, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_point G; /* C: GA, S: GB */ mbedtls_ecp_point Xm; /* C: Xc, S: Xs */ mbedtls_mpi xm; /* C: xc, S: xs */ @@ -750,7 +751,7 @@ int mbedtls_ecjpake_derive_secret( mbedtls_ecjpake_context *ctx, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_point K; mbedtls_mpi m_xm2_s, one; unsigned char kx[MBEDTLS_ECP_MAX_BYTES]; @@ -956,7 +957,7 @@ static int ecjpake_test_load( mbedtls_ecjpake_context *ctx, const unsigned char *xm1, size_t len1, const unsigned char *xm2, size_t len2 ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &ctx->xm1, xm1, len1 ) ); MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &ctx->xm2, xm2, len2 ) ); @@ -1004,7 +1005,7 @@ static int ecjpake_lgc( void *p, unsigned char *out, size_t len ) */ int mbedtls_ecjpake_self_test( int verbose ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecjpake_context cli; mbedtls_ecjpake_context srv; unsigned char buf[512], pms[32]; diff --git a/features/mbedtls/mbed-crypto/src/ecp.c b/features/mbedtls/mbed-crypto/src/ecp.c index c281d84195..e156fcbe2d 100644 --- a/features/mbedtls/mbed-crypto/src/ecp.c +++ b/features/mbedtls/mbed-crypto/src/ecp.c @@ -81,6 +81,7 @@ #include "mbedtls/ecp.h" #include "mbedtls/threading.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -634,7 +635,7 @@ void mbedtls_ecp_keypair_free( mbedtls_ecp_keypair *key ) */ int mbedtls_ecp_copy( mbedtls_ecp_point *P, const mbedtls_ecp_point *Q ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ECP_VALIDATE_RET( P != NULL ); ECP_VALIDATE_RET( Q != NULL ); @@ -662,7 +663,7 @@ int mbedtls_ecp_group_copy( mbedtls_ecp_group *dst, const mbedtls_ecp_group *src */ int mbedtls_ecp_set_zero( mbedtls_ecp_point *pt ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ECP_VALIDATE_RET( pt != NULL ); MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->X , 1 ) ); @@ -708,7 +709,7 @@ int mbedtls_ecp_point_cmp( const mbedtls_ecp_point *P, int mbedtls_ecp_point_read_string( mbedtls_ecp_point *P, int radix, const char *x, const char *y ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ECP_VALIDATE_RET( P != NULL ); ECP_VALIDATE_RET( x != NULL ); ECP_VALIDATE_RET( y != NULL ); @@ -903,7 +904,7 @@ int mbedtls_ecp_tls_write_point( const mbedtls_ecp_group *grp, const mbedtls_ecp int format, size_t *olen, unsigned char *buf, size_t blen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ECP_VALIDATE_RET( grp != NULL ); ECP_VALIDATE_RET( pt != NULL ); ECP_VALIDATE_RET( olen != NULL ); @@ -936,7 +937,7 @@ int mbedtls_ecp_tls_write_point( const mbedtls_ecp_group *grp, const mbedtls_ecp int mbedtls_ecp_tls_read_group( mbedtls_ecp_group *grp, const unsigned char **buf, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_group_id grp_id; ECP_VALIDATE_RET( grp != NULL ); ECP_VALIDATE_RET( buf != NULL ); @@ -1031,7 +1032,7 @@ int mbedtls_ecp_tls_write_group( const mbedtls_ecp_group *grp, size_t *olen, */ static int ecp_modp( mbedtls_mpi *N, const mbedtls_ecp_group *grp ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( grp->modp == NULL ) return( mbedtls_mpi_mod_mpi( N, N, &grp->P ) ); @@ -1088,7 +1089,7 @@ static inline int mbedtls_mpi_mul_mod( const mbedtls_ecp_group *grp, const mbedtls_mpi *A, const mbedtls_mpi *B ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( X, A, B ) ); MOD_MUL( *X ); cleanup: @@ -1108,7 +1109,7 @@ static inline int mbedtls_mpi_sub_mod( const mbedtls_ecp_group *grp, const mbedtls_mpi *A, const mbedtls_mpi *B ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( X, A, B ) ); MOD_SUB( *X ); cleanup: @@ -1129,7 +1130,7 @@ static inline int mbedtls_mpi_add_mod( const mbedtls_ecp_group *grp, const mbedtls_mpi *A, const mbedtls_mpi *B ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( X, A, B ) ); MOD_ADD( *X ); cleanup: @@ -1140,7 +1141,7 @@ static inline int mbedtls_mpi_shift_l_mod( const mbedtls_ecp_group *grp, mbedtls_mpi *X, size_t count ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( X, count ) ); MOD_ADD( *X ); cleanup: @@ -1162,7 +1163,7 @@ cleanup: */ static int ecp_normalize_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *pt ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi Zi, ZZi; if( mbedtls_mpi_cmp_int( &pt->Z, 0 ) == 0 ) @@ -1214,7 +1215,7 @@ cleanup: static int ecp_normalize_jac_many( const mbedtls_ecp_group *grp, mbedtls_ecp_point *T[], size_t T_size ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i; mbedtls_mpi *c, u, Zi, ZZi; @@ -1303,7 +1304,7 @@ static int ecp_safe_invert_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *Q, unsigned char inv ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char nonzero; mbedtls_mpi mQY; @@ -1337,7 +1338,7 @@ cleanup: static int ecp_double_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, const mbedtls_ecp_point *P ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi M, S, T, U; #if defined(MBEDTLS_SELF_TEST) @@ -1433,7 +1434,7 @@ cleanup: static int ecp_add_mixed( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, const mbedtls_ecp_point *P, const mbedtls_ecp_point *Q ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi T1, T2, T3, T4, X, Y, Z; #if defined(MBEDTLS_SELF_TEST) @@ -1521,7 +1522,7 @@ cleanup: static int ecp_randomize_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *pt, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi l, ll; size_t p_size; int count = 0; @@ -1693,7 +1694,7 @@ static int ecp_precompute_comb( const mbedtls_ecp_group *grp, unsigned char w, size_t d, mbedtls_ecp_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char i; size_t j = 0; const unsigned char T_size = 1U << ( w - 1 ); @@ -1829,7 +1830,7 @@ static int ecp_select_comb( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, const mbedtls_ecp_point T[], unsigned char T_size, unsigned char i ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char ii, j; /* Ignore the "sign" bit and scale down */ @@ -1862,7 +1863,7 @@ static int ecp_mul_comb_core( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R void *p_rng, mbedtls_ecp_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_point Txi; size_t i; @@ -1942,7 +1943,7 @@ static int ecp_comb_recode_scalar( const mbedtls_ecp_group *grp, unsigned char w, unsigned char *parity_trick ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi M, mm; mbedtls_mpi_init( &M ); @@ -1988,7 +1989,7 @@ static int ecp_mul_comb_after_precomp( const mbedtls_ecp_group *grp, void *p_rng, mbedtls_ecp_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char parity_trick; unsigned char k[COMB_MAX_D + 1]; mbedtls_ecp_point *RR = R; @@ -2083,7 +2084,7 @@ static int ecp_mul_comb( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, void *p_rng, mbedtls_ecp_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char w, p_eq_g, i; size_t d; unsigned char T_size, T_ok; @@ -2215,7 +2216,7 @@ cleanup: */ static int ecp_normalize_mxz( const mbedtls_ecp_group *grp, mbedtls_ecp_point *P ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; #if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) if( mbedtls_internal_ecp_grp_capable( grp ) ) @@ -2241,7 +2242,7 @@ cleanup: static int ecp_randomize_mxz( const mbedtls_ecp_group *grp, mbedtls_ecp_point *P, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi l; size_t p_size; int count = 0; @@ -2296,7 +2297,7 @@ static int ecp_double_add_mxz( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *P, const mbedtls_ecp_point *Q, const mbedtls_mpi *d ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi A, AA, B, BB, E, C, D, DA, CB; #if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) @@ -2344,7 +2345,7 @@ static int ecp_mul_mxz( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i; unsigned char b; mbedtls_ecp_point RP; @@ -2484,7 +2485,7 @@ int mbedtls_ecp_mul( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, */ static int ecp_check_pubkey_sw( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi YY, RHS; /* pt coordinates must be normalized for our checks */ @@ -2537,7 +2538,7 @@ static int mbedtls_ecp_mul_shortcuts( mbedtls_ecp_group *grp, const mbedtls_ecp_point *P, mbedtls_ecp_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( mbedtls_mpi_cmp_int( m, 1 ) == 0 ) { @@ -2569,7 +2570,7 @@ int mbedtls_ecp_muladd_restartable( const mbedtls_mpi *n, const mbedtls_ecp_point *Q, mbedtls_ecp_restart_ctx *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_point mP; mbedtls_ecp_point *pmP = &mP; mbedtls_ecp_point *pR = R; @@ -2803,6 +2804,7 @@ int mbedtls_ecp_gen_privkey( const mbedtls_ecp_group *grp, { /* SEC1 3.2.1: Generate d such that 1 <= n < N */ int count = 0; + unsigned cmp = 0; /* * Match the procedure given in RFC 6979 (deterministic ECDSA): @@ -2827,9 +2829,14 @@ int mbedtls_ecp_gen_privkey( const mbedtls_ecp_group *grp, */ if( ++count > 30 ) return( MBEDTLS_ERR_ECP_RANDOM_FAILED ); + + ret = mbedtls_mpi_lt_mpi_ct( d, &grp->N, &cmp ); + if( ret != 0 ) + { + goto cleanup; + } } - while( mbedtls_mpi_cmp_int( d, 1 ) < 0 || - mbedtls_mpi_cmp_mpi( d, &grp->N ) >= 0 ); + while( mbedtls_mpi_cmp_int( d, 1 ) < 0 || cmp != 1 ); } #endif /* ECP_SHORTWEIERSTRASS */ @@ -2846,7 +2853,7 @@ int mbedtls_ecp_gen_keypair_base( mbedtls_ecp_group *grp, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ECP_VALIDATE_RET( grp != NULL ); ECP_VALIDATE_RET( d != NULL ); ECP_VALIDATE_RET( G != NULL ); @@ -2882,7 +2889,7 @@ int mbedtls_ecp_gen_keypair( mbedtls_ecp_group *grp, int mbedtls_ecp_gen_key( mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ECP_VALIDATE_RET( key != NULL ); ECP_VALIDATE_RET( f_rng != NULL ); @@ -2966,7 +2973,7 @@ cleanup: */ int mbedtls_ecp_check_pub_priv( const mbedtls_ecp_keypair *pub, const mbedtls_ecp_keypair *prv ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_point Q; mbedtls_ecp_group grp; ECP_VALIDATE_RET( pub != NULL ); @@ -3012,7 +3019,7 @@ cleanup: */ int mbedtls_ecp_self_test( int verbose ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i; mbedtls_ecp_group grp; mbedtls_ecp_point R, P; diff --git a/features/mbedtls/mbed-crypto/src/ecp_curves.c b/features/mbedtls/mbed-crypto/src/ecp_curves.c index dcc70739d0..a24a50c031 100644 --- a/features/mbedtls/mbed-crypto/src/ecp_curves.c +++ b/features/mbedtls/mbed-crypto/src/ecp_curves.c @@ -29,6 +29,7 @@ #include "mbedtls/ecp.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -669,7 +670,7 @@ static int ecp_mod_p256k1( mbedtls_mpi * ); */ static int ecp_use_curve25519( mbedtls_ecp_group *grp ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* Actually ( A + 2 ) / 4 */ MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &grp->A, 16, "01DB42" ) ); @@ -709,7 +710,7 @@ cleanup: static int ecp_use_curve448( mbedtls_ecp_group *grp ) { mbedtls_mpi Ns; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi_init( &Ns ); @@ -900,7 +901,7 @@ static inline void carry64( mbedtls_mpi_uint *dst, mbedtls_mpi_uint *carry ) */ static int ecp_mod_p192( mbedtls_mpi *N ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi_uint c = 0; mbedtls_mpi_uint *p, *end; @@ -991,7 +992,7 @@ static inline void sub32( uint32_t *dst, uint32_t src, signed char *carry ) * (see fix_negative for the motivation of C) */ #define INIT( b ) \ - int ret; \ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; \ signed char c = 0, cc; \ uint32_t cur; \ size_t i = 0, bits = (b); \ @@ -1027,7 +1028,7 @@ static inline void sub32( uint32_t *dst, uint32_t src, signed char *carry ) */ static inline int fix_negative( mbedtls_mpi *N, signed char c, mbedtls_mpi *C, size_t bits ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* C = - c * 2^(bits + 32) */ #if !defined(MBEDTLS_HAVE_INT64) @@ -1185,7 +1186,7 @@ cleanup: */ static int ecp_mod_p521( mbedtls_mpi *N ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i; mbedtls_mpi M; mbedtls_mpi_uint Mp[P521_WIDTH + 1]; @@ -1234,7 +1235,7 @@ cleanup: */ static int ecp_mod_p255( mbedtls_mpi *N ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i; mbedtls_mpi M; mbedtls_mpi_uint Mp[P255_WIDTH + 2]; @@ -1291,7 +1292,7 @@ cleanup: */ static int ecp_mod_p448( mbedtls_mpi *N ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i; mbedtls_mpi M, Q; mbedtls_mpi_uint Mp[P448_WIDTH + 1], Qp[P448_WIDTH]; @@ -1353,7 +1354,7 @@ cleanup: static inline int ecp_mod_koblitz( mbedtls_mpi *N, mbedtls_mpi_uint *Rp, size_t p_limbs, size_t adjust, size_t shift, mbedtls_mpi_uint mask ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i; mbedtls_mpi M, R; mbedtls_mpi_uint Mp[P_KOBLITZ_MAX + P_KOBLITZ_R + 1]; diff --git a/features/mbedtls/mbed-crypto/src/entropy.c b/features/mbedtls/mbed-crypto/src/entropy.c index f8db1a5503..102f9f1c40 100644 --- a/features/mbedtls/mbed-crypto/src/entropy.c +++ b/features/mbedtls/mbed-crypto/src/entropy.c @@ -36,6 +36,7 @@ #include "mbedtls/entropy.h" #include "mbedtls/entropy_poll.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -236,7 +237,7 @@ cleanup: int mbedtls_entropy_update_manual( mbedtls_entropy_context *ctx, const unsigned char *data, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; #if defined(MBEDTLS_THREADING_C) if( ( ret = mbedtls_mutex_lock( &ctx->mutex ) ) != 0 ) @@ -258,7 +259,9 @@ int mbedtls_entropy_update_manual( mbedtls_entropy_context *ctx, */ static int entropy_gather_internal( mbedtls_entropy_context *ctx ) { - int ret, i, have_one_strong = 0; + int ret = MBEDTLS_ERR_ENTROPY_SOURCE_FAILED; + int i; + int have_one_strong = 0; unsigned char buf[MBEDTLS_ENTROPY_MAX_GATHER]; size_t olen; @@ -306,7 +309,7 @@ cleanup: */ int mbedtls_entropy_gather( mbedtls_entropy_context *ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; #if defined(MBEDTLS_THREADING_C) if( ( ret = mbedtls_mutex_lock( &ctx->mutex ) ) != 0 ) @@ -325,7 +328,8 @@ int mbedtls_entropy_gather( mbedtls_entropy_context *ctx ) int mbedtls_entropy_func( void *data, unsigned char *output, size_t len ) { - int ret, count = 0, i, done; + int ret, count = 0, i, thresholds_reached; + size_t strong_size; mbedtls_entropy_context *ctx = (mbedtls_entropy_context *) data; unsigned char buf[MBEDTLS_ENTROPY_BLOCK_SIZE]; @@ -363,12 +367,17 @@ int mbedtls_entropy_func( void *data, unsigned char *output, size_t len ) if( ( ret = entropy_gather_internal( ctx ) ) != 0 ) goto exit; - done = 1; + thresholds_reached = 1; + strong_size = 0; for( i = 0; i < ctx->source_count; i++ ) + { if( ctx->source[i].size < ctx->source[i].threshold ) - done = 0; + thresholds_reached = 0; + if( ctx->source[i].strong == MBEDTLS_ENTROPY_SOURCE_STRONG ) + strong_size += ctx->source[i].size; + } } - while( ! done ); + while( ! thresholds_reached || strong_size < MBEDTLS_ENTROPY_BLOCK_SIZE ); memset( buf, 0, MBEDTLS_ENTROPY_BLOCK_SIZE ); diff --git a/features/mbedtls/mbed-crypto/src/entropy_poll.c b/features/mbedtls/mbed-crypto/src/entropy_poll.c index 4556f88a55..c9b2c95c60 100644 --- a/features/mbedtls/mbed-crypto/src/entropy_poll.c +++ b/features/mbedtls/mbed-crypto/src/entropy_poll.c @@ -36,6 +36,7 @@ #include "mbedtls/entropy.h" #include "mbedtls/entropy_poll.h" +#include "mbedtls/error.h" #if defined(MBEDTLS_TIMING_C) #include "mbedtls/timing.h" @@ -121,7 +122,7 @@ int mbedtls_platform_entropy_poll( void *data, { FILE *file; size_t read_len; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ((void) data); #if defined(HAVE_GETRANDOM) diff --git a/features/mbedtls/mbed-crypto/src/gcm.c b/features/mbedtls/mbed-crypto/src/gcm.c index 5121a7ac7e..e34f1dae40 100644 --- a/features/mbedtls/mbed-crypto/src/gcm.c +++ b/features/mbedtls/mbed-crypto/src/gcm.c @@ -39,6 +39,7 @@ #include "mbedtls/gcm.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -168,7 +169,7 @@ int mbedtls_gcm_setkey( mbedtls_gcm_context *ctx, const unsigned char *key, unsigned int keybits ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const mbedtls_cipher_info_t *cipher_info; GCM_VALIDATE_RET( ctx != NULL ); @@ -246,7 +247,7 @@ static void gcm_mult( mbedtls_gcm_context *ctx, const unsigned char x[16], for( i = 15; i >= 0; i-- ) { lo = x[i] & 0xf; - hi = x[i] >> 4; + hi = ( x[i] >> 4 ) & 0xf; if( i != 15 ) { @@ -280,7 +281,7 @@ int mbedtls_gcm_starts( mbedtls_gcm_context *ctx, const unsigned char *add, size_t add_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char work_buf[16]; size_t i; const unsigned char *p; @@ -365,7 +366,7 @@ int mbedtls_gcm_update( mbedtls_gcm_context *ctx, const unsigned char *input, unsigned char *output ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char ectr[16]; size_t i; const unsigned char *p; @@ -476,7 +477,7 @@ int mbedtls_gcm_crypt_and_tag( mbedtls_gcm_context *ctx, size_t tag_len, unsigned char *tag ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; GCM_VALIDATE_RET( ctx != NULL ); GCM_VALIDATE_RET( iv != NULL ); @@ -508,7 +509,7 @@ int mbedtls_gcm_auth_decrypt( mbedtls_gcm_context *ctx, const unsigned char *input, unsigned char *output ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char check_tag[16]; size_t i; int diff; diff --git a/features/mbedtls/mbed-crypto/src/hkdf.c b/features/mbedtls/mbed-crypto/src/hkdf.c index 82d8a429f4..379035ddbb 100644 --- a/features/mbedtls/mbed-crypto/src/hkdf.c +++ b/features/mbedtls/mbed-crypto/src/hkdf.c @@ -29,13 +29,14 @@ #include #include "mbedtls/hkdf.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" int mbedtls_hkdf( const mbedtls_md_info_t *md, const unsigned char *salt, size_t salt_len, const unsigned char *ikm, size_t ikm_len, const unsigned char *info, size_t info_len, unsigned char *okm, size_t okm_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char prk[MBEDTLS_MD_MAX_SIZE]; ret = mbedtls_hkdf_extract( md, salt, salt_len, ikm, ikm_len, prk ); diff --git a/features/mbedtls/mbed-crypto/src/hmac_drbg.c b/features/mbedtls/mbed-crypto/src/hmac_drbg.c index 50d88bd54b..f811885c9f 100644 --- a/features/mbedtls/mbed-crypto/src/hmac_drbg.c +++ b/features/mbedtls/mbed-crypto/src/hmac_drbg.c @@ -35,6 +35,7 @@ #include "mbedtls/hmac_drbg.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -74,7 +75,7 @@ int mbedtls_hmac_drbg_update_ret( mbedtls_hmac_drbg_context *ctx, unsigned char rounds = ( additional != NULL && add_len != 0 ) ? 2 : 1; unsigned char sep[1]; unsigned char K[MBEDTLS_MD_MAX_SIZE]; - int ret; + int ret = MBEDTLS_ERR_MD_BAD_INPUT_DATA; for( sep[0] = 0; sep[0] < rounds; sep[0]++ ) { @@ -127,7 +128,7 @@ int mbedtls_hmac_drbg_seed_buf( mbedtls_hmac_drbg_context *ctx, const mbedtls_md_info_t * md_info, const unsigned char *data, size_t data_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = mbedtls_md_setup( &ctx->md_ctx, md_info, 1 ) ) != 0 ) return( ret ); @@ -159,7 +160,7 @@ static int hmac_drbg_reseed_core( mbedtls_hmac_drbg_context *ctx, { unsigned char seed[MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT]; size_t seedlen = 0; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; { size_t total_entropy_len; @@ -251,7 +252,7 @@ int mbedtls_hmac_drbg_seed( mbedtls_hmac_drbg_context *ctx, const unsigned char *custom, size_t len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t md_size; if( ( ret = mbedtls_md_setup( &ctx->md_ctx, md_info, 1 ) ) != 0 ) @@ -273,16 +274,19 @@ int mbedtls_hmac_drbg_seed( mbedtls_hmac_drbg_context *ctx, ctx->reseed_interval = MBEDTLS_HMAC_DRBG_RESEED_INTERVAL; - /* - * See SP800-57 5.6.1 (p. 65-66) for the security strength provided by - * each hash function, then according to SP800-90A rev1 10.1 table 2, - * min_entropy_len (in bits) is security_strength. - * - * (This also matches the sizes used in the NIST test vectors.) - */ - ctx->entropy_len = md_size <= 20 ? 16 : /* 160-bits hash -> 128 bits */ - md_size <= 28 ? 24 : /* 224-bits hash -> 192 bits */ - 32; /* better (256+) -> 256 bits */ + if( ctx->entropy_len == 0 ) + { + /* + * See SP800-57 5.6.1 (p. 65-66) for the security strength provided by + * each hash function, then according to SP800-90A rev1 10.1 table 2, + * min_entropy_len (in bits) is security_strength. + * + * (This also matches the sizes used in the NIST test vectors.) + */ + ctx->entropy_len = md_size <= 20 ? 16 : /* 160-bits hash -> 128 bits */ + md_size <= 28 ? 24 : /* 224-bits hash -> 192 bits */ + 32; /* better (256+) -> 256 bits */ + } if( ( ret = hmac_drbg_reseed_core( ctx, custom, len, 1 /* add nonce */ ) ) != 0 ) @@ -303,7 +307,7 @@ void mbedtls_hmac_drbg_set_prediction_resistance( mbedtls_hmac_drbg_context *ctx } /* - * Set entropy length grabbed for reseeds + * Set entropy length grabbed for seeding */ void mbedtls_hmac_drbg_set_entropy_len( mbedtls_hmac_drbg_context *ctx, size_t len ) { @@ -326,7 +330,7 @@ int mbedtls_hmac_drbg_random_with_add( void *p_rng, unsigned char *output, size_t out_len, const unsigned char *additional, size_t add_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_hmac_drbg_context *ctx = (mbedtls_hmac_drbg_context *) p_rng; size_t md_len = mbedtls_md_get_size( ctx->md_ctx.md_info ); size_t left = out_len; @@ -395,7 +399,7 @@ exit: */ int mbedtls_hmac_drbg_random( void *p_rng, unsigned char *output, size_t out_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_hmac_drbg_context *ctx = (mbedtls_hmac_drbg_context *) p_rng; #if defined(MBEDTLS_THREADING_C) @@ -431,7 +435,7 @@ void mbedtls_hmac_drbg_free( mbedtls_hmac_drbg_context *ctx ) #if defined(MBEDTLS_FS_IO) int mbedtls_hmac_drbg_write_seed_file( mbedtls_hmac_drbg_context *ctx, const char *path ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; FILE *f; unsigned char buf[ MBEDTLS_HMAC_DRBG_MAX_INPUT ]; diff --git a/features/mbedtls/mbed-crypto/src/md.c b/features/mbedtls/mbed-crypto/src/md.c index e1b5183b6a..e235bc8daf 100644 --- a/features/mbedtls/mbed-crypto/src/md.c +++ b/features/mbedtls/mbed-crypto/src/md.c @@ -34,6 +34,7 @@ #include "mbedtls/md.h" #include "mbedtls/md_internal.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include "mbedtls/md2.h" #include "mbedtls/md4.h" @@ -119,12 +120,14 @@ const mbedtls_md_info_t mbedtls_sha256_info = { #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) const mbedtls_md_info_t mbedtls_sha384_info = { "SHA384", MBEDTLS_MD_SHA384, 48, 128, }; +#endif const mbedtls_md_info_t mbedtls_sha512_info = { "SHA512", @@ -141,8 +144,10 @@ static const int supported_digests[] = { #if defined(MBEDTLS_SHA512_C) MBEDTLS_MD_SHA512, +#if !defined(MBEDTLS_SHA512_NO_SHA384) MBEDTLS_MD_SHA384, #endif +#endif #if defined(MBEDTLS_SHA256_C) MBEDTLS_MD_SHA256, @@ -210,8 +215,10 @@ const mbedtls_md_info_t *mbedtls_md_info_from_string( const char *md_name ) return mbedtls_md_info_from_type( MBEDTLS_MD_SHA256 ); #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) if( !strcmp( "SHA384", md_name ) ) return mbedtls_md_info_from_type( MBEDTLS_MD_SHA384 ); +#endif if( !strcmp( "SHA512", md_name ) ) return mbedtls_md_info_from_type( MBEDTLS_MD_SHA512 ); #endif @@ -249,8 +256,10 @@ const mbedtls_md_info_t *mbedtls_md_info_from_type( mbedtls_md_type_t md_type ) return( &mbedtls_sha256_info ); #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case MBEDTLS_MD_SHA384: return( &mbedtls_sha384_info ); +#endif case MBEDTLS_MD_SHA512: return( &mbedtls_sha512_info ); #endif @@ -305,7 +314,9 @@ void mbedtls_md_free( mbedtls_md_context_t *ctx ) break; #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case MBEDTLS_MD_SHA384: +#endif case MBEDTLS_MD_SHA512: mbedtls_sha512_free( ctx->md_ctx ); break; @@ -371,7 +382,9 @@ int mbedtls_md_clone( mbedtls_md_context_t *dst, break; #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case MBEDTLS_MD_SHA384: +#endif case MBEDTLS_MD_SHA512: mbedtls_sha512_clone( dst->md_ctx, src->md_ctx ); break; @@ -438,7 +451,9 @@ int mbedtls_md_setup( mbedtls_md_context_t *ctx, const mbedtls_md_info_t *md_inf break; #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case MBEDTLS_MD_SHA384: +#endif case MBEDTLS_MD_SHA512: ALLOC( sha512 ); break; @@ -497,8 +512,10 @@ int mbedtls_md_starts( mbedtls_md_context_t *ctx ) return( mbedtls_sha256_starts_ret( ctx->md_ctx, 0 ) ); #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case MBEDTLS_MD_SHA384: return( mbedtls_sha512_starts_ret( ctx->md_ctx, 1 ) ); +#endif case MBEDTLS_MD_SHA512: return( mbedtls_sha512_starts_ret( ctx->md_ctx, 0 ) ); #endif @@ -541,8 +558,10 @@ int mbedtls_md_update( mbedtls_md_context_t *ctx, const unsigned char *input, si return( mbedtls_sha256_update_ret( ctx->md_ctx, input, ilen ) ); #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case MBEDTLS_MD_SHA384: return( mbedtls_sha512_update_ret( ctx->md_ctx, input, ilen ) ); +#endif case MBEDTLS_MD_SHA512: return( mbedtls_sha512_update_ret( ctx->md_ctx, input, ilen ) ); #endif @@ -585,8 +604,10 @@ int mbedtls_md_finish( mbedtls_md_context_t *ctx, unsigned char *output ) return( mbedtls_sha256_finish_ret( ctx->md_ctx, output ) ); #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case MBEDTLS_MD_SHA384: return( mbedtls_sha512_finish_ret( ctx->md_ctx, output ) ); +#endif case MBEDTLS_MD_SHA512: return( mbedtls_sha512_finish_ret( ctx->md_ctx, output ) ); #endif @@ -630,8 +651,10 @@ int mbedtls_md( const mbedtls_md_info_t *md_info, const unsigned char *input, si return( mbedtls_sha256_ret( input, ilen, output, 0 ) ); #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case MBEDTLS_MD_SHA384: return( mbedtls_sha512_ret( input, ilen, output, 1 ) ); +#endif case MBEDTLS_MD_SHA512: return( mbedtls_sha512_ret( input, ilen, output, 0 ) ); #endif @@ -643,7 +666,7 @@ int mbedtls_md( const mbedtls_md_info_t *md_info, const unsigned char *input, si #if defined(MBEDTLS_FS_IO) int mbedtls_md_file( const mbedtls_md_info_t *md_info, const char *path, unsigned char *output ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; FILE *f; size_t n; mbedtls_md_context_t ctx; @@ -683,7 +706,7 @@ cleanup: int mbedtls_md_hmac_starts( mbedtls_md_context_t *ctx, const unsigned char *key, size_t keylen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char sum[MBEDTLS_MD_MAX_SIZE]; unsigned char *ipad, *opad; size_t i; @@ -738,7 +761,7 @@ int mbedtls_md_hmac_update( mbedtls_md_context_t *ctx, const unsigned char *inpu int mbedtls_md_hmac_finish( mbedtls_md_context_t *ctx, unsigned char *output ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char tmp[MBEDTLS_MD_MAX_SIZE]; unsigned char *opad; @@ -762,7 +785,7 @@ int mbedtls_md_hmac_finish( mbedtls_md_context_t *ctx, unsigned char *output ) int mbedtls_md_hmac_reset( mbedtls_md_context_t *ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *ipad; if( ctx == NULL || ctx->md_info == NULL || ctx->hmac_ctx == NULL ) @@ -781,7 +804,7 @@ int mbedtls_md_hmac( const mbedtls_md_info_t *md_info, unsigned char *output ) { mbedtls_md_context_t ctx; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( md_info == NULL ) return( MBEDTLS_ERR_MD_BAD_INPUT_DATA ); @@ -838,8 +861,10 @@ int mbedtls_md_process( mbedtls_md_context_t *ctx, const unsigned char *data ) return( mbedtls_internal_sha256_process( ctx->md_ctx, data ) ); #endif #if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) case MBEDTLS_MD_SHA384: return( mbedtls_internal_sha512_process( ctx->md_ctx, data ) ); +#endif case MBEDTLS_MD_SHA512: return( mbedtls_internal_sha512_process( ctx->md_ctx, data ) ); #endif diff --git a/features/mbedtls/mbed-crypto/src/md2.c b/features/mbedtls/mbed-crypto/src/md2.c index 1c0b3df52d..82aed8e73c 100644 --- a/features/mbedtls/mbed-crypto/src/md2.c +++ b/features/mbedtls/mbed-crypto/src/md2.c @@ -35,6 +35,7 @@ #include "mbedtls/md2.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -170,7 +171,7 @@ int mbedtls_md2_update_ret( mbedtls_md2_context *ctx, const unsigned char *input, size_t ilen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t fill; while( ilen > 0 ) @@ -212,7 +213,7 @@ void mbedtls_md2_update( mbedtls_md2_context *ctx, int mbedtls_md2_finish_ret( mbedtls_md2_context *ctx, unsigned char output[16] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i; unsigned char x; @@ -250,7 +251,7 @@ int mbedtls_md2_ret( const unsigned char *input, size_t ilen, unsigned char output[16] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_md2_context ctx; mbedtls_md2_init( &ctx ); diff --git a/features/mbedtls/mbed-crypto/src/md4.c b/features/mbedtls/mbed-crypto/src/md4.c index 828fd42999..6a658e31d4 100644 --- a/features/mbedtls/mbed-crypto/src/md4.c +++ b/features/mbedtls/mbed-crypto/src/md4.c @@ -35,6 +35,7 @@ #include "mbedtls/md4.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -253,7 +254,7 @@ int mbedtls_md4_update_ret( mbedtls_md4_context *ctx, const unsigned char *input, size_t ilen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t fill; uint32_t left; @@ -323,7 +324,7 @@ static const unsigned char md4_padding[64] = int mbedtls_md4_finish_ret( mbedtls_md4_context *ctx, unsigned char output[16] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; uint32_t last, padn; uint32_t high, low; unsigned char msglen[8]; @@ -371,7 +372,7 @@ int mbedtls_md4_ret( const unsigned char *input, size_t ilen, unsigned char output[16] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_md4_context ctx; mbedtls_md4_init( &ctx ); diff --git a/features/mbedtls/mbed-crypto/src/md5.c b/features/mbedtls/mbed-crypto/src/md5.c index a93da8a061..2306855f46 100644 --- a/features/mbedtls/mbed-crypto/src/md5.c +++ b/features/mbedtls/mbed-crypto/src/md5.c @@ -34,6 +34,7 @@ #include "mbedtls/md5.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -259,7 +260,7 @@ int mbedtls_md5_update_ret( mbedtls_md5_context *ctx, const unsigned char *input, size_t ilen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t fill; uint32_t left; @@ -318,7 +319,7 @@ void mbedtls_md5_update( mbedtls_md5_context *ctx, int mbedtls_md5_finish_ret( mbedtls_md5_context *ctx, unsigned char output[16] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; uint32_t used; uint32_t high, low; @@ -386,7 +387,7 @@ int mbedtls_md5_ret( const unsigned char *input, size_t ilen, unsigned char output[16] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_md5_context ctx; mbedtls_md5_init( &ctx ); diff --git a/features/mbedtls/mbed-crypto/src/nist_kw.c b/features/mbedtls/mbed-crypto/src/nist_kw.c index 317a2426ae..03e807202d 100644 --- a/features/mbedtls/mbed-crypto/src/nist_kw.c +++ b/features/mbedtls/mbed-crypto/src/nist_kw.c @@ -39,6 +39,7 @@ #include "mbedtls/nist_kw.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include #include @@ -116,7 +117,7 @@ int mbedtls_nist_kw_setkey( mbedtls_nist_kw_context *ctx, unsigned int keybits, const int is_wrap ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const mbedtls_cipher_info_t *cipher_info; cipher_info = mbedtls_cipher_info_from_values( cipher, diff --git a/features/mbedtls/mbed-crypto/src/oid.c b/features/mbedtls/mbed-crypto/src/oid.c index 27c455e877..891d3cdea9 100644 --- a/features/mbedtls/mbed-crypto/src/oid.c +++ b/features/mbedtls/mbed-crypto/src/oid.c @@ -31,6 +31,7 @@ #include "mbedtls/oid.h" #include "mbedtls/rsa.h" +#include "mbedtls/error.h" #include #include @@ -732,7 +733,7 @@ FN_OID_GET_ATTR2(mbedtls_oid_get_pkcs12_pbe_alg, oid_pkcs12_pbe_alg_t, pkcs12_pb int mbedtls_oid_get_numeric_string( char *buf, size_t size, const mbedtls_asn1_buf *oid ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t i, n; unsigned int value; char *p; diff --git a/features/mbedtls/mbed-crypto/src/pem.c b/features/mbedtls/mbed-crypto/src/pem.c index 897c8a0d6f..31f4a9a25e 100644 --- a/features/mbedtls/mbed-crypto/src/pem.c +++ b/features/mbedtls/mbed-crypto/src/pem.c @@ -34,6 +34,7 @@ #include "mbedtls/md5.h" #include "mbedtls/cipher.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -85,7 +86,7 @@ static int pem_pbkdf1( unsigned char *key, size_t keylen, mbedtls_md5_context md5_ctx; unsigned char md5sum[16]; size_t use_len; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_md5_init( &md5_ctx ); @@ -146,7 +147,7 @@ static int pem_des_decrypt( unsigned char des_iv[8], { mbedtls_des_context des_ctx; unsigned char des_key[8]; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_des_init( &des_ctx ); @@ -174,7 +175,7 @@ static int pem_des3_decrypt( unsigned char des3_iv[8], { mbedtls_des3_context des3_ctx; unsigned char des3_key[24]; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_des3_init( &des3_ctx ); @@ -204,7 +205,7 @@ static int pem_aes_decrypt( unsigned char aes_iv[16], unsigned int keylen, { mbedtls_aes_context aes_ctx; unsigned char aes_key[32]; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_aes_init( &aes_ctx ); @@ -439,7 +440,7 @@ int mbedtls_pem_write_buffer( const char *header, const char *footer, const unsigned char *der_data, size_t der_len, unsigned char *buf, size_t buf_len, size_t *olen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *encode_buf = NULL, *c, *p = buf; size_t len = 0, use_len, add_len = 0; diff --git a/features/mbedtls/mbed-crypto/src/pk.c b/features/mbedtls/mbed-crypto/src/pk.c index e93ccfdab9..b83ba8e71d 100644 --- a/features/mbedtls/mbed-crypto/src/pk.c +++ b/features/mbedtls/mbed-crypto/src/pk.c @@ -30,6 +30,7 @@ #include "mbedtls/pk_internal.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #if defined(MBEDTLS_RSA_C) #include "mbedtls/rsa.h" @@ -297,7 +298,7 @@ int mbedtls_pk_verify_restartable( mbedtls_pk_context *ctx, mbedtls_ecp_restart_is_enabled() && ctx->pk_info->verify_rs_func != NULL ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = pk_restart_setup( rs_ctx, ctx->pk_info ) ) != 0 ) return( ret ); @@ -354,7 +355,7 @@ int mbedtls_pk_verify_ext( mbedtls_pk_type_t type, const void *options, if( type == MBEDTLS_PK_RSASSA_PSS ) { #if defined(MBEDTLS_RSA_C) && defined(MBEDTLS_PKCS1_V21) - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const mbedtls_pk_rsassa_pss_options *pss_opts; #if SIZE_MAX > UINT_MAX @@ -420,7 +421,7 @@ int mbedtls_pk_sign_restartable( mbedtls_pk_context *ctx, mbedtls_ecp_restart_is_enabled() && ctx->pk_info->sign_rs_func != NULL ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = pk_restart_setup( rs_ctx, ctx->pk_info ) ) != 0 ) return( ret ); @@ -604,7 +605,8 @@ int mbedtls_pk_wrap_as_opaque( mbedtls_pk_context *pk, psa_ecc_curve_t curve_id; psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; psa_key_type_t key_type; - int ret; + size_t bits; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* export the private key material in the format PSA wants */ if( mbedtls_pk_get_type( pk ) != MBEDTLS_PK_ECKEY ) @@ -615,13 +617,13 @@ int mbedtls_pk_wrap_as_opaque( mbedtls_pk_context *pk, if( ( ret = mbedtls_mpi_write_binary( &ec->d, d, d_len ) ) != 0 ) return( ret ); - curve_id = mbedtls_ecp_curve_info_from_grp_id( ec->grp.id )->tls_id; - key_type = PSA_KEY_TYPE_ECC_KEY_PAIR( - mbedtls_psa_parse_tls_ecc_group ( curve_id ) ); + curve_id = mbedtls_ecc_group_to_psa( ec->grp.id, &bits ); + key_type = PSA_KEY_TYPE_ECC_KEY_PAIR( curve_id ); /* prepare the key attributes */ psa_set_key_type( &attributes, key_type ); - psa_set_key_usage_flags( &attributes, PSA_KEY_USAGE_SIGN ); + psa_set_key_bits( &attributes, bits ); + psa_set_key_usage_flags( &attributes, PSA_KEY_USAGE_SIGN_HASH ); psa_set_key_algorithm( &attributes, PSA_ALG_ECDSA(hash_alg) ); /* import private key into PSA */ diff --git a/features/mbedtls/mbed-crypto/src/pk_wrap.c b/features/mbedtls/mbed-crypto/src/pk_wrap.c index 5a699c030b..f736431495 100644 --- a/features/mbedtls/mbed-crypto/src/pk_wrap.c +++ b/features/mbedtls/mbed-crypto/src/pk_wrap.c @@ -27,6 +27,7 @@ #if defined(MBEDTLS_PK_C) #include "mbedtls/pk_internal.h" +#include "mbedtls/error.h" /* Even if RSA not activated, for the sake of RSA-alt */ #include "mbedtls/rsa.h" @@ -83,7 +84,7 @@ static int rsa_verify_wrap( void *ctx, mbedtls_md_type_t md_alg, const unsigned char *hash, size_t hash_len, const unsigned char *sig, size_t sig_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_rsa_context * rsa = (mbedtls_rsa_context *) ctx; size_t rsa_len = mbedtls_rsa_get_len( rsa ); @@ -248,7 +249,7 @@ static int eckey_verify_wrap( void *ctx, mbedtls_md_type_t md_alg, const unsigned char *hash, size_t hash_len, const unsigned char *sig, size_t sig_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecdsa_context ecdsa; mbedtls_ecdsa_init( &ecdsa ); @@ -266,7 +267,7 @@ static int eckey_sign_wrap( void *ctx, mbedtls_md_type_t md_alg, unsigned char *sig, size_t *sig_len, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecdsa_context ecdsa; mbedtls_ecdsa_init( &ecdsa ); @@ -340,7 +341,7 @@ static int eckey_verify_rs_wrap( void *ctx, mbedtls_md_type_t md_alg, const unsigned char *sig, size_t sig_len, void *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; eckey_restart_ctx *rs = rs_ctx; /* Should never happen */ @@ -365,7 +366,7 @@ static int eckey_sign_rs_wrap( void *ctx, mbedtls_md_type_t md_alg, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, void *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; eckey_restart_ctx *rs = rs_ctx; /* Should never happen */ @@ -490,7 +491,7 @@ static int ecdsa_can_do( mbedtls_pk_type_t type ) static int extract_ecdsa_sig_int( unsigned char **from, const unsigned char *end, unsigned char *to, size_t to_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t unpadded_len, padding_len; if( ( ret = mbedtls_asn1_get_tag( from, end, &unpadded_len, @@ -524,7 +525,7 @@ static int extract_ecdsa_sig_int( unsigned char **from, const unsigned char *end static int extract_ecdsa_sig( unsigned char **p, const unsigned char *end, unsigned char *sig, size_t int_size ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t tmp_size; if( ( ret = mbedtls_asn1_get_tag( p, end, &tmp_size, @@ -541,11 +542,12 @@ static int extract_ecdsa_sig( unsigned char **p, const unsigned char *end, return( 0 ); } -static int ecdsa_verify_wrap( void *ctx, mbedtls_md_type_t md_alg, +static int ecdsa_verify_wrap( void *ctx_arg, mbedtls_md_type_t md_alg, const unsigned char *hash, size_t hash_len, const unsigned char *sig, size_t sig_len ) { - int ret; + mbedtls_ecdsa_context *ctx = ctx_arg; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; psa_key_handle_t key_handle = 0; psa_status_t status; @@ -556,9 +558,10 @@ static int ecdsa_verify_wrap( void *ctx, mbedtls_md_type_t md_alg, unsigned char *p; mbedtls_pk_info_t pk_info = mbedtls_eckey_info; psa_algorithm_t psa_sig_md, psa_md; - psa_ecc_curve_t curve = mbedtls_psa_translate_ecc_group( - ( (mbedtls_ecdsa_context *) ctx )->grp.id ); - const size_t signature_part_size = ( ( (mbedtls_ecdsa_context *) ctx )->grp.nbits + 7 ) / 8; + size_t curve_bits; + psa_ecc_curve_t curve = + mbedtls_ecc_group_to_psa( ctx->grp.id, &curve_bits ); + const size_t signature_part_size = ( ctx->grp.nbits + 7 ) / 8; if( curve == 0 ) return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); @@ -578,7 +581,7 @@ static int ecdsa_verify_wrap( void *ctx, mbedtls_md_type_t md_alg, psa_sig_md = PSA_ALG_ECDSA( psa_md ); psa_set_key_type( &attributes, PSA_KEY_TYPE_ECC_PUBLIC_KEY( curve ) ); - psa_set_key_usage_flags( &attributes, PSA_KEY_USAGE_VERIFY ); + psa_set_key_usage_flags( &attributes, PSA_KEY_USAGE_VERIFY_HASH ); psa_set_key_algorithm( &attributes, psa_sig_md ); status = psa_import_key( &attributes, @@ -605,9 +608,9 @@ static int ecdsa_verify_wrap( void *ctx, mbedtls_md_type_t md_alg, goto cleanup; } - if( psa_asymmetric_verify( key_handle, psa_sig_md, - hash, hash_len, - buf, 2 * signature_part_size ) + if( psa_verify_hash( key_handle, psa_sig_md, + hash, hash_len, + buf, 2 * signature_part_size ) != PSA_SUCCESS ) { ret = MBEDTLS_ERR_ECP_VERIFY_FAILED; @@ -630,7 +633,7 @@ static int ecdsa_verify_wrap( void *ctx, mbedtls_md_type_t md_alg, const unsigned char *hash, size_t hash_len, const unsigned char *sig, size_t sig_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ((void) md_alg); ret = mbedtls_ecdsa_read_signature( (mbedtls_ecdsa_context *) ctx, @@ -658,7 +661,7 @@ static int ecdsa_verify_rs_wrap( void *ctx, mbedtls_md_type_t md_alg, const unsigned char *sig, size_t sig_len, void *rs_ctx ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; ((void) md_alg); ret = mbedtls_ecdsa_read_signature_restartable( @@ -774,6 +777,8 @@ static int rsa_alt_sign_wrap( void *ctx, mbedtls_md_type_t md_alg, #endif /* SIZE_MAX > UINT_MAX */ *sig_len = rsa_alt->key_len_func( rsa_alt->key ); + if( *sig_len > MBEDTLS_PK_SIGNATURE_MAX_SIZE ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); return( rsa_alt->sign_func( rsa_alt->key, f_rng, p_rng, MBEDTLS_RSA_PRIVATE, md_alg, (unsigned int) hash_len, hash, sig ) ); @@ -802,7 +807,7 @@ static int rsa_alt_check_pair( const void *pub, const void *prv ) unsigned char sig[MBEDTLS_MPI_MAX_SIZE]; unsigned char hash[32]; size_t sig_len = 0; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( rsa_alt_get_bitlen( prv ) != rsa_get_bitlen( pub ) ) return( MBEDTLS_ERR_RSA_KEY_CHECK_FAILED ); @@ -923,7 +928,7 @@ static int pk_opaque_can_do( mbedtls_pk_type_t type ) static int asn1_write_mpibuf( unsigned char **p, unsigned char *start, size_t n_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; if( (size_t)( *p - start ) < n_len ) @@ -975,7 +980,7 @@ static int asn1_write_mpibuf( unsigned char **p, unsigned char *start, static int pk_ecdsa_sig_asn1_from_psa( unsigned char *sig, size_t *sig_len, size_t buf_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; const size_t rs_len = *sig_len / 2; unsigned char *p = sig + buf_len; @@ -1017,10 +1022,12 @@ static int pk_opaque_sign_wrap( void *ctx, mbedtls_md_type_t md_alg, return( mbedtls_psa_err_translate_pk( status ) ); buf_len = MBEDTLS_ECDSA_MAX_SIG_LEN( psa_get_key_bits( &attributes ) ); psa_reset_key_attributes( &attributes ); + if( buf_len > MBEDTLS_PK_SIGNATURE_MAX_SIZE ) + return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); /* make the signature */ - status = psa_asymmetric_sign( *key, alg, hash, hash_len, - sig, buf_len, sig_len ); + status = psa_sign_hash( *key, alg, hash, hash_len, + sig, buf_len, sig_len ); if( status != PSA_SUCCESS ) return( mbedtls_psa_err_translate_pk( status ) ); diff --git a/features/mbedtls/mbed-crypto/src/pkcs12.c b/features/mbedtls/mbed-crypto/src/pkcs12.c index 7edf064c13..96c64ad63c 100644 --- a/features/mbedtls/mbed-crypto/src/pkcs12.c +++ b/features/mbedtls/mbed-crypto/src/pkcs12.c @@ -37,6 +37,7 @@ #include "mbedtls/asn1.h" #include "mbedtls/cipher.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -53,7 +54,7 @@ static int pkcs12_parse_pbe_params( mbedtls_asn1_buf *params, mbedtls_asn1_buf *salt, int *iterations ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char **p = ¶ms->p; const unsigned char *end = params->p + params->len; @@ -145,7 +146,7 @@ int mbedtls_pkcs12_pbe_sha1_rc4_128( mbedtls_asn1_buf *pbe_params, int mode, ((void) output); return( MBEDTLS_ERR_PKCS12_FEATURE_UNAVAILABLE ); #else - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char key[16]; mbedtls_arc4_context ctx; ((void) mode); @@ -250,7 +251,7 @@ int mbedtls_pkcs12_derivation( unsigned char *data, size_t datalen, const unsigned char *salt, size_t saltlen, mbedtls_md_type_t md_type, int id, int iterations ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned int j; unsigned char diversifier[128]; diff --git a/features/mbedtls/mbed-crypto/src/pkcs5.c b/features/mbedtls/mbed-crypto/src/pkcs5.c index 3d29fd7e59..8832322257 100644 --- a/features/mbedtls/mbed-crypto/src/pkcs5.c +++ b/features/mbedtls/mbed-crypto/src/pkcs5.c @@ -38,6 +38,7 @@ #if defined(MBEDTLS_PKCS5_C) #include "mbedtls/pkcs5.h" +#include "mbedtls/error.h" #if defined(MBEDTLS_ASN1_PARSE_C) #include "mbedtls/asn1.h" @@ -59,7 +60,7 @@ static int pkcs5_parse_pbkdf2_params( const mbedtls_asn1_buf *params, mbedtls_asn1_buf *salt, int *iterations, int *keylen, mbedtls_md_type_t *md_type ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_asn1_buf prf_alg_oid; unsigned char *p = params->p; const unsigned char *end = params->p + params->len; diff --git a/features/mbedtls/mbed-crypto/src/pkparse.c b/features/mbedtls/mbed-crypto/src/pkparse.c index ae210bca6a..1cbb8cc339 100644 --- a/features/mbedtls/mbed-crypto/src/pkparse.c +++ b/features/mbedtls/mbed-crypto/src/pkparse.c @@ -31,6 +31,7 @@ #include "mbedtls/asn1.h" #include "mbedtls/oid.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -130,7 +131,7 @@ int mbedtls_pk_load_file( const char *path, unsigned char **buf, size_t *n ) int mbedtls_pk_parse_keyfile( mbedtls_pk_context *ctx, const char *path, const char *pwd ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n; unsigned char *buf; @@ -157,7 +158,7 @@ int mbedtls_pk_parse_keyfile( mbedtls_pk_context *ctx, */ int mbedtls_pk_parse_public_keyfile( mbedtls_pk_context *ctx, const char *path ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t n; unsigned char *buf; @@ -188,7 +189,7 @@ int mbedtls_pk_parse_public_keyfile( mbedtls_pk_context *ctx, const char *path ) static int pk_get_ecparams( unsigned char **p, const unsigned char *end, mbedtls_asn1_buf *params ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if ( end - *p < 1 ) return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT + @@ -243,7 +244,7 @@ static int pk_get_ecparams( unsigned char **p, const unsigned char *end, */ static int pk_group_from_specified( const mbedtls_asn1_buf *params, mbedtls_ecp_group *grp ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *p = params->p; const unsigned char * const end = params->p + params->len; const unsigned char *end_field, *end_curve; @@ -433,7 +434,7 @@ cleanup: static int pk_group_id_from_specified( const mbedtls_asn1_buf *params, mbedtls_ecp_group_id *grp_id ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_group grp; mbedtls_ecp_group_init( &grp ); @@ -460,7 +461,7 @@ cleanup: */ static int pk_use_ecparams( const mbedtls_asn1_buf *params, mbedtls_ecp_group *grp ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ecp_group_id grp_id; if( params->tag == MBEDTLS_ASN1_OID ) @@ -500,7 +501,7 @@ static int pk_use_ecparams( const mbedtls_asn1_buf *params, mbedtls_ecp_group *g static int pk_get_ecpubkey( unsigned char **p, const unsigned char *end, mbedtls_ecp_keypair *key ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; if( ( ret = mbedtls_ecp_point_read_binary( &key->grp, &key->Q, (const unsigned char *) *p, end - *p ) ) == 0 ) @@ -528,7 +529,7 @@ static int pk_get_rsapubkey( unsigned char **p, const unsigned char *end, mbedtls_rsa_context *rsa ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; if( ( ret = mbedtls_asn1_get_tag( p, end, &len, @@ -583,7 +584,7 @@ static int pk_get_pk_alg( unsigned char **p, const unsigned char *end, mbedtls_pk_type_t *pk_alg, mbedtls_asn1_buf *params ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_asn1_buf alg_oid; memset( params, 0, sizeof(mbedtls_asn1_buf) ); @@ -615,7 +616,7 @@ static int pk_get_pk_alg( unsigned char **p, int mbedtls_pk_parse_subpubkey( unsigned char **p, const unsigned char *end, mbedtls_pk_context *pk ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len; mbedtls_asn1_buf alg_params; mbedtls_pk_type_t pk_alg = MBEDTLS_PK_NONE; @@ -677,6 +678,32 @@ int mbedtls_pk_parse_subpubkey( unsigned char **p, const unsigned char *end, } #if defined(MBEDTLS_RSA_C) +/* + * Wrapper around mbedtls_asn1_get_mpi() that rejects zero. + * + * The value zero is: + * - never a valid value for an RSA parameter + * - interpreted as "omitted, please reconstruct" by mbedtls_rsa_complete(). + * + * Since values can't be omitted in PKCS#1, passing a zero value to + * rsa_complete() would be incorrect, so reject zero values early. + */ +static int asn1_get_nonzero_mpi( unsigned char **p, + const unsigned char *end, + mbedtls_mpi *X ) +{ + int ret; + + ret = mbedtls_asn1_get_mpi( p, end, X ); + if( ret != 0 ) + return( ret ); + + if( mbedtls_mpi_cmp_int( X, 0 ) == 0 ) + return( MBEDTLS_ERR_PK_KEY_INVALID_FORMAT ); + + return( 0 ); +} + /* * Parse a PKCS#1 encoded private RSA key */ @@ -729,54 +756,84 @@ static int pk_parse_key_pkcs1_der( mbedtls_rsa_context *rsa, } /* Import N */ - if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, - MBEDTLS_ASN1_INTEGER ) ) != 0 || - ( ret = mbedtls_rsa_import_raw( rsa, p, len, NULL, 0, NULL, 0, - NULL, 0, NULL, 0 ) ) != 0 ) + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_rsa_import( rsa, &T, NULL, NULL, + NULL, NULL ) ) != 0 ) goto cleanup; - p += len; /* Import E */ - if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, - MBEDTLS_ASN1_INTEGER ) ) != 0 || - ( ret = mbedtls_rsa_import_raw( rsa, NULL, 0, NULL, 0, NULL, 0, - NULL, 0, p, len ) ) != 0 ) + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_rsa_import( rsa, NULL, NULL, NULL, + NULL, &T ) ) != 0 ) goto cleanup; - p += len; /* Import D */ - if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, - MBEDTLS_ASN1_INTEGER ) ) != 0 || - ( ret = mbedtls_rsa_import_raw( rsa, NULL, 0, NULL, 0, NULL, 0, - p, len, NULL, 0 ) ) != 0 ) + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_rsa_import( rsa, NULL, NULL, NULL, + &T, NULL ) ) != 0 ) goto cleanup; - p += len; /* Import P */ - if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, - MBEDTLS_ASN1_INTEGER ) ) != 0 || - ( ret = mbedtls_rsa_import_raw( rsa, NULL, 0, p, len, NULL, 0, - NULL, 0, NULL, 0 ) ) != 0 ) + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_rsa_import( rsa, NULL, &T, NULL, + NULL, NULL ) ) != 0 ) goto cleanup; - p += len; /* Import Q */ - if( ( ret = mbedtls_asn1_get_tag( &p, end, &len, - MBEDTLS_ASN1_INTEGER ) ) != 0 || - ( ret = mbedtls_rsa_import_raw( rsa, NULL, 0, NULL, 0, p, len, - NULL, 0, NULL, 0 ) ) != 0 ) - goto cleanup; - p += len; - - /* Complete the RSA private key */ - if( ( ret = mbedtls_rsa_complete( rsa ) ) != 0 ) + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_rsa_import( rsa, NULL, NULL, &T, + NULL, NULL ) ) != 0 ) goto cleanup; - /* Check optional parameters */ - if( ( ret = mbedtls_asn1_get_mpi( &p, end, &T ) ) != 0 || - ( ret = mbedtls_asn1_get_mpi( &p, end, &T ) ) != 0 || - ( ret = mbedtls_asn1_get_mpi( &p, end, &T ) ) != 0 ) +#if !defined(MBEDTLS_RSA_NO_CRT) && !defined(MBEDTLS_RSA_ALT) + /* + * The RSA CRT parameters DP, DQ and QP are nominally redundant, in + * that they can be easily recomputed from D, P and Q. However by + * parsing them from the PKCS1 structure it is possible to avoid + * recalculating them which both reduces the overhead of loading + * RSA private keys into memory and also avoids side channels which + * can arise when computing those values, since all of D, P, and Q + * are secret. See https://eprint.iacr.org/2020/055 for a + * description of one such attack. + */ + + /* Import DP */ + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_mpi_copy( &rsa->DP, &T ) ) != 0 ) + goto cleanup; + + /* Import DQ */ + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_mpi_copy( &rsa->DQ, &T ) ) != 0 ) + goto cleanup; + + /* Import QP */ + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = mbedtls_mpi_copy( &rsa->QP, &T ) ) != 0 ) + goto cleanup; + +#else + /* Verify existance of the CRT params */ + if( ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 || + ( ret = asn1_get_nonzero_mpi( &p, end, &T ) ) != 0 ) + goto cleanup; +#endif + + /* rsa_complete() doesn't complete anything with the default + * implementation but is still called: + * - for the benefit of alternative implementation that may want to + * pre-compute stuff beyond what's provided (eg Montgomery factors) + * - as is also sanity-checks the key + * + * Furthermore, we also check the public part for consistency with + * mbedtls_pk_parse_pubkey(), as it includes size minima for example. + */ + if( ( ret = mbedtls_rsa_complete( rsa ) ) != 0 || + ( ret = mbedtls_rsa_check_pubkey( rsa ) ) != 0 ) + { goto cleanup; + } if( p != end ) { @@ -811,7 +868,7 @@ static int pk_parse_key_sec1_der( mbedtls_ecp_keypair *eck, const unsigned char *key, size_t keylen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; int version, pubkey_done; size_t len; mbedtls_asn1_buf params; @@ -1164,7 +1221,7 @@ int mbedtls_pk_parse_key( mbedtls_pk_context *pk, const unsigned char *key, size_t keylen, const unsigned char *pwd, size_t pwdlen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const mbedtls_pk_info_t *pk_info; #if defined(MBEDTLS_PEM_PARSE_C) size_t len; @@ -1376,7 +1433,7 @@ int mbedtls_pk_parse_key( mbedtls_pk_context *pk, int mbedtls_pk_parse_public_key( mbedtls_pk_context *ctx, const unsigned char *key, size_t keylen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *p; #if defined(MBEDTLS_RSA_C) const mbedtls_pk_info_t *pk_info; diff --git a/features/mbedtls/mbed-crypto/src/pkwrite.c b/features/mbedtls/mbed-crypto/src/pkwrite.c index 4388160786..b1b5f4685a 100644 --- a/features/mbedtls/mbed-crypto/src/pkwrite.c +++ b/features/mbedtls/mbed-crypto/src/pkwrite.c @@ -31,6 +31,7 @@ #include "mbedtls/asn1write.h" #include "mbedtls/oid.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -38,7 +39,9 @@ #include "mbedtls/rsa.h" #endif #if defined(MBEDTLS_ECP_C) +#include "mbedtls/bignum.h" #include "mbedtls/ecp.h" +#include "mbedtls/platform_util.h" #endif #if defined(MBEDTLS_ECDSA_C) #include "mbedtls/ecdsa.h" @@ -75,7 +78,7 @@ static int pk_write_rsa_pubkey( unsigned char **p, unsigned char *start, mbedtls_rsa_context *rsa ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; mbedtls_mpi T; @@ -114,7 +117,7 @@ end_of_export: static int pk_write_ec_pubkey( unsigned char **p, unsigned char *start, mbedtls_ecp_keypair *ec ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; unsigned char buf[MBEDTLS_ECP_MAX_PT_LEN]; @@ -142,7 +145,7 @@ static int pk_write_ec_pubkey( unsigned char **p, unsigned char *start, static int pk_write_ec_param( unsigned char **p, unsigned char *start, mbedtls_ecp_keypair *ec ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; const char *oid; size_t oid_len; @@ -154,12 +157,32 @@ static int pk_write_ec_param( unsigned char **p, unsigned char *start, return( (int) len ); } + +/* + * privateKey OCTET STRING -- always of length ceil(log2(n)/8) + */ +static int pk_write_ec_private( unsigned char **p, unsigned char *start, + mbedtls_ecp_keypair *ec ) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + size_t byte_length = ( ec->grp.pbits + 7 ) / 8; + unsigned char tmp[MBEDTLS_ECP_MAX_BYTES]; + + ret = mbedtls_mpi_write_binary( &ec->d, tmp, byte_length ); + if( ret != 0 ) + goto exit; + ret = mbedtls_asn1_write_octet_string( p, start, tmp, byte_length ); + +exit: + mbedtls_platform_zeroize( tmp, byte_length ); + return( ret ); +} #endif /* MBEDTLS_ECP_C */ int mbedtls_pk_write_pubkey( unsigned char **p, unsigned char *start, const mbedtls_pk_context *key ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t len = 0; PK_VALIDATE_RET( p != NULL ); @@ -207,7 +230,7 @@ int mbedtls_pk_write_pubkey( unsigned char **p, unsigned char *start, int mbedtls_pk_write_pubkey_der( mbedtls_pk_context *key, unsigned char *buf, size_t size ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *c; size_t len = 0, par_len = 0, oid_len; mbedtls_pk_type_t pk_type; @@ -250,18 +273,20 @@ int mbedtls_pk_write_pubkey_der( mbedtls_pk_context *key, unsigned char *buf, si psa_key_type_t key_type; psa_key_handle_t handle; psa_ecc_curve_t curve; + size_t bits; handle = *((psa_key_handle_t*) key->pk_ctx ); if( PSA_SUCCESS != psa_get_key_attributes( handle, &attributes ) ) return( MBEDTLS_ERR_PK_HW_ACCEL_FAILED ); key_type = psa_get_key_type( &attributes ); + bits = psa_get_key_bits( &attributes ); psa_reset_key_attributes( &attributes ); curve = PSA_KEY_TYPE_GET_CURVE( key_type ); if( curve == 0 ) return( MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE ); - ret = mbedtls_psa_get_ecc_oid_from_id( curve, &oid, &oid_len ); + ret = mbedtls_psa_get_ecc_oid_from_id( curve, bits, &oid, &oid_len ); if( ret != 0 ) return( MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE ); @@ -293,7 +318,7 @@ int mbedtls_pk_write_pubkey_der( mbedtls_pk_context *key, unsigned char *buf, si int mbedtls_pk_write_key_der( mbedtls_pk_context *key, unsigned char *buf, size_t size ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *c; size_t len = 0; @@ -424,9 +449,8 @@ int mbedtls_pk_write_key_der( mbedtls_pk_context *key, unsigned char *buf, size_ MBEDTLS_ASN1_CONTEXT_SPECIFIC | MBEDTLS_ASN1_CONSTRUCTED | 0 ) ); len += par_len; - /* privateKey: write as MPI then fix tag */ - MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_mpi( &c, buf, &ec->d ) ); - *c = MBEDTLS_ASN1_OCTET_STRING; + /* privateKey */ + MBEDTLS_ASN1_CHK_ADD( len, pk_write_ec_private( &c, buf, ec ) ); /* version */ MBEDTLS_ASN1_CHK_ADD( len, mbedtls_asn1_write_int( &c, buf, 1 ) ); @@ -537,7 +561,7 @@ int mbedtls_pk_write_key_der( mbedtls_pk_context *key, unsigned char *buf, size_ int mbedtls_pk_write_pubkey_pem( mbedtls_pk_context *key, unsigned char *buf, size_t size ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char output_buf[PUB_DER_MAX_BYTES]; size_t olen = 0; @@ -562,7 +586,7 @@ int mbedtls_pk_write_pubkey_pem( mbedtls_pk_context *key, unsigned char *buf, si int mbedtls_pk_write_key_pem( mbedtls_pk_context *key, unsigned char *buf, size_t size ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char output_buf[PRV_DER_MAX_BYTES]; const char *begin, *end; size_t olen = 0; diff --git a/features/mbedtls/mbed-crypto/src/platform.c b/features/mbedtls/mbed-crypto/src/platform.c index 5756159543..420d09ea1e 100644 --- a/features/mbedtls/mbed-crypto/src/platform.c +++ b/features/mbedtls/mbed-crypto/src/platform.c @@ -29,6 +29,7 @@ #include "mbedtls/platform.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" /* The compile time configuration of memory allocation via the macros * MBEDTLS_PLATFORM_{FREE/CALLOC}_MACRO takes precedence over the runtime @@ -86,7 +87,7 @@ int mbedtls_platform_set_calloc_free( void * (*calloc_func)( size_t, size_t ), #include int mbedtls_platform_win32_snprintf( char *s, size_t n, const char *fmt, ... ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; va_list argp; va_start( argp, fmt ); @@ -131,7 +132,7 @@ int mbedtls_platform_set_snprintf( int (*snprintf_func)( char * s, size_t n, #include int mbedtls_platform_win32_vsnprintf( char *s, size_t n, const char *fmt, va_list arg ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; /* Avoid calling the invalid parameter handler by checking ourselves */ if( s == NULL || n == 0 || fmt == NULL ) diff --git a/features/mbedtls/mbed-crypto/src/poly1305.c b/features/mbedtls/mbed-crypto/src/poly1305.c index 2b56c5f7ef..bc1e8a6496 100644 --- a/features/mbedtls/mbed-crypto/src/poly1305.c +++ b/features/mbedtls/mbed-crypto/src/poly1305.c @@ -30,6 +30,7 @@ #include "mbedtls/poly1305.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -423,7 +424,7 @@ int mbedtls_poly1305_mac( const unsigned char key[32], unsigned char mac[16] ) { mbedtls_poly1305_context ctx; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; POLY1305_VALIDATE_RET( key != NULL ); POLY1305_VALIDATE_RET( mac != NULL ); POLY1305_VALIDATE_RET( ilen == 0 || input != NULL ); @@ -529,7 +530,7 @@ int mbedtls_poly1305_self_test( int verbose ) { unsigned char mac[16]; unsigned i; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; for( i = 0U; i < 2U; i++ ) { diff --git a/features/mbedtls/mbed-crypto/src/ripemd160.c b/features/mbedtls/mbed-crypto/src/ripemd160.c index 0791ae4cc9..a62f4b824e 100644 --- a/features/mbedtls/mbed-crypto/src/ripemd160.c +++ b/features/mbedtls/mbed-crypto/src/ripemd160.c @@ -35,6 +35,7 @@ #include "mbedtls/ripemd160.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -322,7 +323,7 @@ int mbedtls_ripemd160_update_ret( mbedtls_ripemd160_context *ctx, const unsigned char *input, size_t ilen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t fill; uint32_t left; @@ -390,7 +391,7 @@ static const unsigned char ripemd160_padding[64] = int mbedtls_ripemd160_finish_ret( mbedtls_ripemd160_context *ctx, unsigned char output[20] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; uint32_t last, padn; uint32_t high, low; unsigned char msglen[8]; @@ -439,7 +440,7 @@ int mbedtls_ripemd160_ret( const unsigned char *input, size_t ilen, unsigned char output[20] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_ripemd160_context ctx; mbedtls_ripemd160_init( &ctx ); diff --git a/features/mbedtls/mbed-crypto/src/rsa.c b/features/mbedtls/mbed-crypto/src/rsa.c index a35af44746..6c457468ea 100644 --- a/features/mbedtls/mbed-crypto/src/rsa.c +++ b/features/mbedtls/mbed-crypto/src/rsa.c @@ -49,6 +49,7 @@ #include "mbedtls/rsa_internal.h" #include "mbedtls/oid.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -98,7 +99,7 @@ int mbedtls_rsa_import( mbedtls_rsa_context *ctx, const mbedtls_mpi *P, const mbedtls_mpi *Q, const mbedtls_mpi *D, const mbedtls_mpi *E ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; RSA_VALIDATE_RET( ctx != NULL ); if( ( N != NULL && ( ret = mbedtls_mpi_copy( &ctx->N, N ) ) != 0 ) || @@ -249,6 +250,9 @@ int mbedtls_rsa_complete( mbedtls_rsa_context *ctx ) { int ret = 0; int have_N, have_P, have_Q, have_D, have_E; +#if !defined(MBEDTLS_RSA_NO_CRT) + int have_DP, have_DQ, have_QP; +#endif int n_missing, pq_missing, d_missing, is_pub, is_priv; RSA_VALIDATE_RET( ctx != NULL ); @@ -259,6 +263,12 @@ int mbedtls_rsa_complete( mbedtls_rsa_context *ctx ) have_D = ( mbedtls_mpi_cmp_int( &ctx->D, 0 ) != 0 ); have_E = ( mbedtls_mpi_cmp_int( &ctx->E, 0 ) != 0 ); +#if !defined(MBEDTLS_RSA_NO_CRT) + have_DP = ( mbedtls_mpi_cmp_int( &ctx->DP, 0 ) != 0 ); + have_DQ = ( mbedtls_mpi_cmp_int( &ctx->DQ, 0 ) != 0 ); + have_QP = ( mbedtls_mpi_cmp_int( &ctx->QP, 0 ) != 0 ); +#endif + /* * Check whether provided parameters are enough * to deduce all others. The following incomplete @@ -324,7 +334,7 @@ int mbedtls_rsa_complete( mbedtls_rsa_context *ctx ) */ #if !defined(MBEDTLS_RSA_NO_CRT) - if( is_priv ) + if( is_priv && ! ( have_DP && have_DQ && have_QP ) ) { ret = mbedtls_rsa_deduce_crt( &ctx->P, &ctx->Q, &ctx->D, &ctx->DP, &ctx->DQ, &ctx->QP ); @@ -392,7 +402,7 @@ int mbedtls_rsa_export( const mbedtls_rsa_context *ctx, mbedtls_mpi *N, mbedtls_mpi *P, mbedtls_mpi *Q, mbedtls_mpi *D, mbedtls_mpi *E ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; int is_priv; RSA_VALIDATE_RET( ctx != NULL ); @@ -436,7 +446,7 @@ int mbedtls_rsa_export( const mbedtls_rsa_context *ctx, int mbedtls_rsa_export_crt( const mbedtls_rsa_context *ctx, mbedtls_mpi *DP, mbedtls_mpi *DQ, mbedtls_mpi *QP ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; int is_priv; RSA_VALIDATE_RET( ctx != NULL ); @@ -527,7 +537,7 @@ int mbedtls_rsa_gen_key( mbedtls_rsa_context *ctx, void *p_rng, unsigned int nbits, int exponent ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_mpi H, G, L; int prime_quality = 0; RSA_VALIDATE_RET( ctx != NULL ); @@ -719,7 +729,7 @@ int mbedtls_rsa_public( mbedtls_rsa_context *ctx, const unsigned char *input, unsigned char *output ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t olen; mbedtls_mpi T; RSA_VALIDATE_RET( ctx != NULL ); @@ -832,7 +842,7 @@ int mbedtls_rsa_private( mbedtls_rsa_context *ctx, const unsigned char *input, unsigned char *output ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t olen; /* Temporary holding the result */ @@ -1125,7 +1135,7 @@ int mbedtls_rsa_rsaes_oaep_encrypt( mbedtls_rsa_context *ctx, unsigned char *output ) { size_t olen; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *p = output; unsigned int hlen; const mbedtls_md_info_t *md_info; @@ -1212,7 +1222,7 @@ int mbedtls_rsa_rsaes_pkcs1_v15_encrypt( mbedtls_rsa_context *ctx, unsigned char *output ) { size_t nb_pad, olen; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *p = output; RSA_VALIDATE_RET( ctx != NULL ); @@ -1322,7 +1332,7 @@ int mbedtls_rsa_rsaes_oaep_decrypt( mbedtls_rsa_context *ctx, unsigned char *output, size_t output_max_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t ilen, i, pad_len; unsigned char *p, bad, pad_done; unsigned char buf[MBEDTLS_MPI_MAX_SIZE]; @@ -1558,7 +1568,7 @@ int mbedtls_rsa_rsaes_pkcs1_v15_decrypt( mbedtls_rsa_context *ctx, unsigned char *output, size_t output_max_len ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t ilen, i, plaintext_max_size; unsigned char buf[MBEDTLS_MPI_MAX_SIZE]; /* The following variables take sensitive values: their value must @@ -1774,7 +1784,7 @@ int mbedtls_rsa_rsassa_pss_sign( mbedtls_rsa_context *ctx, unsigned char *p = sig; unsigned char salt[MBEDTLS_MD_MAX_SIZE]; size_t slen, min_slen, hlen, offset = 0; - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t msb; const mbedtls_md_info_t *md_info; mbedtls_md_context_t md_ctx; @@ -2029,7 +2039,7 @@ int mbedtls_rsa_rsassa_pkcs1_v15_sign( mbedtls_rsa_context *ctx, const unsigned char *hash, unsigned char *sig ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned char *sig_try = NULL, *verif = NULL; RSA_VALIDATE_RET( ctx != NULL ); @@ -2151,7 +2161,7 @@ int mbedtls_rsa_rsassa_pss_verify_ext( mbedtls_rsa_context *ctx, int expected_salt_len, const unsigned char *sig ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t siglen; unsigned char *p; unsigned char *hash_start; @@ -2448,7 +2458,7 @@ int mbedtls_rsa_pkcs1_verify( mbedtls_rsa_context *ctx, */ int mbedtls_rsa_copy( mbedtls_rsa_context *dst, const mbedtls_rsa_context *src ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; RSA_VALIDATE_RET( dst != NULL ); RSA_VALIDATE_RET( src != NULL ); diff --git a/features/mbedtls/mbed-crypto/src/sha1.c b/features/mbedtls/mbed-crypto/src/sha1.c index 355c83d2f7..9233943415 100644 --- a/features/mbedtls/mbed-crypto/src/sha1.c +++ b/features/mbedtls/mbed-crypto/src/sha1.c @@ -34,6 +34,7 @@ #include "mbedtls/sha1.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -307,7 +308,7 @@ int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t fill; uint32_t left; @@ -368,7 +369,7 @@ void mbedtls_sha1_update( mbedtls_sha1_context *ctx, int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx, unsigned char output[20] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; uint32_t used; uint32_t high, low; @@ -440,7 +441,7 @@ int mbedtls_sha1_ret( const unsigned char *input, size_t ilen, unsigned char output[20] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_sha1_context ctx; SHA1_VALIDATE_RET( ilen == 0 || input != NULL ); diff --git a/features/mbedtls/mbed-crypto/src/sha256.c b/features/mbedtls/mbed-crypto/src/sha256.c index 2dc0e1a2c9..087a8e349c 100644 --- a/features/mbedtls/mbed-crypto/src/sha256.c +++ b/features/mbedtls/mbed-crypto/src/sha256.c @@ -34,6 +34,7 @@ #include "mbedtls/sha256.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #include @@ -275,7 +276,7 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t fill; uint32_t left; @@ -336,7 +337,7 @@ void mbedtls_sha256_update( mbedtls_sha256_context *ctx, int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, unsigned char output[32] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; uint32_t used; uint32_t high, low; @@ -414,7 +415,7 @@ int mbedtls_sha256_ret( const unsigned char *input, unsigned char output[32], int is224 ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_sha256_context ctx; SHA256_VALIDATE_RET( is224 == 0 || is224 == 1 ); diff --git a/features/mbedtls/mbed-crypto/src/sha512.c b/features/mbedtls/mbed-crypto/src/sha512.c index 2e2b797872..30dd719540 100644 --- a/features/mbedtls/mbed-crypto/src/sha512.c +++ b/features/mbedtls/mbed-crypto/src/sha512.c @@ -34,6 +34,7 @@ #include "mbedtls/sha512.h" #include "mbedtls/platform_util.h" +#include "mbedtls/error.h" #if defined(_MSC_VER) || defined(__WATCOMC__) #define UL64(x) x##ui64 @@ -131,7 +132,11 @@ void mbedtls_sha512_clone( mbedtls_sha512_context *dst, int mbedtls_sha512_starts_ret( mbedtls_sha512_context *ctx, int is384 ) { SHA512_VALIDATE_RET( ctx != NULL ); +#if !defined(MBEDTLS_SHA512_NO_SHA384) SHA512_VALIDATE_RET( is384 == 0 || is384 == 1 ); +#else + SHA512_VALIDATE_RET( is384 == 0 ); +#endif ctx->total[0] = 0; ctx->total[1] = 0; @@ -150,6 +155,9 @@ int mbedtls_sha512_starts_ret( mbedtls_sha512_context *ctx, int is384 ) } else { +#if defined(MBEDTLS_SHA512_NO_SHA384) + return( MBEDTLS_ERR_SHA512_BAD_INPUT_DATA ); +#else /* SHA-384 */ ctx->state[0] = UL64(0xCBBB9D5DC1059ED8); ctx->state[1] = UL64(0x629A292A367CD507); @@ -159,9 +167,12 @@ int mbedtls_sha512_starts_ret( mbedtls_sha512_context *ctx, int is384 ) ctx->state[5] = UL64(0x8EB44A8768581511); ctx->state[6] = UL64(0xDB0C2E0D64F98FA7); ctx->state[7] = UL64(0x47B5481DBEFA4FA4); +#endif /* MBEDTLS_SHA512_NO_SHA384 */ } +#if !defined(MBEDTLS_SHA512_NO_SHA384) ctx->is384 = is384; +#endif return( 0 ); } @@ -323,7 +334,7 @@ int mbedtls_sha512_update_ret( mbedtls_sha512_context *ctx, const unsigned char *input, size_t ilen ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; size_t fill; unsigned int left; @@ -383,7 +394,7 @@ void mbedtls_sha512_update( mbedtls_sha512_context *ctx, int mbedtls_sha512_finish_ret( mbedtls_sha512_context *ctx, unsigned char output[64] ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; unsigned used; uint64_t high, low; @@ -436,7 +447,9 @@ int mbedtls_sha512_finish_ret( mbedtls_sha512_context *ctx, sha512_put_uint64_be( ctx->state[4], output, 32 ); sha512_put_uint64_be( ctx->state[5], output, 40 ); +#if !defined(MBEDTLS_SHA512_NO_SHA384) if( ctx->is384 == 0 ) +#endif { sha512_put_uint64_be( ctx->state[6], output, 48 ); sha512_put_uint64_be( ctx->state[7], output, 56 ); @@ -463,10 +476,14 @@ int mbedtls_sha512_ret( const unsigned char *input, unsigned char output[64], int is384 ) { - int ret; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; mbedtls_sha512_context ctx; +#if !defined(MBEDTLS_SHA512_NO_SHA384) SHA512_VALIDATE_RET( is384 == 0 || is384 == 1 ); +#else + SHA512_VALIDATE_RET( is384 == 0 ); +#endif SHA512_VALIDATE_RET( ilen == 0 || input != NULL ); SHA512_VALIDATE_RET( (unsigned char *)output != NULL ); @@ -515,8 +532,9 @@ static const size_t sha512_test_buflen[3] = 3, 112, 1000 }; -static const unsigned char sha512_test_sum[6][64] = +static const unsigned char sha512_test_sum[][64] = { +#if !defined(MBEDTLS_SHA512_NO_SHA384) /* * SHA-384 test vectors */ @@ -538,6 +556,7 @@ static const unsigned char sha512_test_sum[6][64] = 0x79, 0x72, 0xCE, 0xC5, 0x70, 0x4C, 0x2A, 0x5B, 0x07, 0xB8, 0xB3, 0xDC, 0x38, 0xEC, 0xC4, 0xEB, 0xAE, 0x97, 0xDD, 0xD8, 0x7F, 0x3D, 0x89, 0x85 }, +#endif /* !MBEDTLS_SHA512_NO_SHA384 */ /* * SHA-512 test vectors @@ -568,6 +587,8 @@ static const unsigned char sha512_test_sum[6][64] = 0x4E, 0xAD, 0xB2, 0x17, 0xAD, 0x8C, 0xC0, 0x9B } }; +#define ARRAY_LENGTH( a ) ( sizeof( a ) / sizeof( ( a )[0] ) ) + /* * Checkup routine */ @@ -589,10 +610,14 @@ int mbedtls_sha512_self_test( int verbose ) mbedtls_sha512_init( &ctx ); - for( i = 0; i < 6; i++ ) + for( i = 0; i < (int) ARRAY_LENGTH(sha512_test_sum); i++ ) { j = i % 3; +#if !defined(MBEDTLS_SHA512_NO_SHA384) k = i < 3; +#else + k = 0; +#endif if( verbose != 0 ) mbedtls_printf( " SHA-%d test #%d: ", 512 - k * 128, j + 1 ); @@ -648,6 +673,8 @@ exit: return( ret ); } +#undef ARRAY_LENGTH + #endif /* MBEDTLS_SELF_TEST */ #endif /* MBEDTLS_SHA512_C */ From 7ed3f9c998e6deb45812dff4480ef7290ee814ad Mon Sep 17 00:00:00 2001 From: Jaeden Amero Date: Fri, 20 Dec 2019 15:50:24 +0000 Subject: [PATCH 40/49] crypto: Update the service for Mbed Crypto 3.x Update Mbed OS's PSA Crypto service to work with Mbed Crypto 3.x. - psa_asymmetric_verify() is now called psa_verify_hash(). - psa_asymmetric_sign() is now called psa_sign_hash(). Compatibilty wrappers are provided via crypto_compat.h for source-level backwards compatibility. --- TESTS/mbed-crypto/sanity/main.cpp | 8 ++--- .../COMPONENT_NSPE/main.cpp | 8 ++--- .../COMPONENT_PSA_SRV_IMPL/attest_crypto.c | 14 ++++----- .../tfm_impl/attestation_core.c | 2 +- .../crypto_platform_spe.h | 4 +-- .../COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c | 30 +++++++++---------- .../crypto/COMPONENT_SPE/crypto_spe.h | 4 +-- .../COMPONENT_SPE/psa_crypto_partition.c | 16 +++++----- 8 files changed, 43 insertions(+), 43 deletions(-) diff --git a/TESTS/mbed-crypto/sanity/main.cpp b/TESTS/mbed-crypto/sanity/main.cpp index 98cd169e47..9fdeca3689 100644 --- a/TESTS/mbed-crypto/sanity/main.cpp +++ b/TESTS/mbed-crypto/sanity/main.cpp @@ -262,13 +262,13 @@ void test_crypto_asymmetric_sign_verify(void) psa_set_key_algorithm(&attributes, alg); psa_set_key_type(&attributes, key_type); TEST_ASSERT_EQUAL(PSA_SUCCESS, psa_import_key(&attributes, key, sizeof(key), &key_handle)); - TEST_ASSERT_EQUAL(PSA_SUCCESS, psa_asymmetric_sign(key_handle, alg, input, sizeof(input), - signature, sizeof(signature), &signature_len)); + TEST_ASSERT_EQUAL(PSA_SUCCESS, psa_sign_hash(key_handle, alg, input, sizeof(input), + signature, sizeof(signature), &signature_len)); TEST_ASSERT_EQUAL(sizeof(signature), signature_len); TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_signature, signature, signature_len); - TEST_ASSERT_EQUAL(PSA_SUCCESS, psa_asymmetric_verify(key_handle, alg, input, sizeof(input), - signature, signature_len)); + TEST_ASSERT_EQUAL(PSA_SUCCESS, psa_verify_hash(key_handle, alg, input, sizeof(input), + signature, signature_len)); TEST_ASSERT_EQUAL(PSA_SUCCESS, psa_destroy_key(key_handle)); } diff --git a/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp b/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp index f260e96f18..a0f8852368 100644 --- a/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp +++ b/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp @@ -373,12 +373,12 @@ void test_use_other_partition_key_asymmetric_sign_verify(void) TEST_ASSERT_NOT_EQUAL(0, key_handle); /* try to asymmetric sign using the key that was created by the test partition */ - TEST_ASSERT_EQUAL(PSA_ERROR_INVALID_HANDLE, psa_asymmetric_sign(key_handle, key_alg, input, sizeof(input), - signature, sizeof(signature), &len)); + TEST_ASSERT_EQUAL(PSA_ERROR_INVALID_HANDLE, psa_sign_hash(key_handle, key_alg, input, sizeof(input), + signature, sizeof(signature), &len)); /* try to asymmetric verify using the key that was created by the test partition */ - TEST_ASSERT_EQUAL(PSA_ERROR_INVALID_HANDLE, psa_asymmetric_verify(key_handle, key_alg, input, sizeof(input), - signature, sizeof(signature))); + TEST_ASSERT_EQUAL(PSA_ERROR_INVALID_HANDLE, psa_verify_hash(key_handle, key_alg, input, sizeof(input), + signature, sizeof(signature))); /* via test partition - destroy the key created by the test partition */ TEST_ASSERT_EQUAL(PSA_SUCCESS, test_partition_crypto_destroy_key(key_handle)); diff --git a/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/attest_crypto.c b/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/attest_crypto.c index 60252919ac..f92fc18f56 100755 --- a/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/attest_crypto.c +++ b/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/attest_crypto.c @@ -58,13 +58,13 @@ t_cose_crypto_pub_key_sign(int32_t cose_alg_id, return T_COSE_ERR_NO_KID; } - crypto_ret = psa_asymmetric_sign(handle, - PSA_ALG_DETERMINISTIC_ECDSA(PSA_ALG_SHA_256), - hash_to_sign.ptr, - hash_to_sign.len, - signature_buffer.ptr, - signature_buffer.len, - &(signature->len)); + crypto_ret = psa_sign_hash(handle, + PSA_ALG_DETERMINISTIC_ECDSA(PSA_ALG_SHA_256), + hash_to_sign.ptr, + hash_to_sign.len, + signature_buffer.ptr, + signature_buffer.len, + &(signature->len)); if (crypto_ret != PSA_SUCCESS) diff --git a/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/tfm_impl/attestation_core.c b/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/tfm_impl/attestation_core.c index 87a5486ce7..a7e46dab26 100755 --- a/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/tfm_impl/attestation_core.c +++ b/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/tfm_impl/attestation_core.c @@ -942,7 +942,7 @@ error: /* Limitations of the current implementation: * - Token is not signed yet properly, just a fake signature is added to the - * token due to lack of psa_asymmetric_sign() implementation in crypto + * token due to lack of psa_sign_hash() implementation in crypto * service. */ enum psa_attest_err_t diff --git a/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/crypto_platform_spe.h b/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/crypto_platform_spe.h index 6783e292f4..05fe728fbf 100644 --- a/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/crypto_platform_spe.h +++ b/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/crypto_platform_spe.h @@ -87,8 +87,8 @@ typedef enum psa_sec_function_s { PSA_AEAD_FINISH, PSA_AEAD_VERIFY, PSA_AEAD_ABORT, - PSA_ASYMMETRIC_SIGN, - PSA_ASYMMETRIC_VERIFY, + PSA_SIGN_HASH, + PSA_VERIFY_HASH, PSA_ASYMMETRIC_ENCRYPT, PSA_ASYMMETRIC_DECRYPT, PSA_KEY_DERIVATION_SETUP, diff --git a/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c b/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c index a1d09e2587..c50004a8e9 100644 --- a/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c +++ b/components/TARGET_PSA/services/crypto/COMPONENT_PSA_SRV_IPC/psa_crypto_spm.c @@ -1216,16 +1216,16 @@ psa_status_t psa_aead_abort(psa_aead_operation_t *operation) return ipc_call(&operation->handle, &in_vec, 1, NULL, 0, true); } -psa_status_t psa_asymmetric_sign(psa_key_handle_t handle, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - uint8_t *signature, - size_t signature_size, - size_t *signature_length) +psa_status_t psa_sign_hash(psa_key_handle_t handle, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length) { psa_crypto_ipc_asymmetric_t psa_crypto_ipc = { - .func = PSA_ASYMMETRIC_SIGN, + .func = PSA_SIGN_HASH, .handle = handle, .alg = alg, .input_length = 0, @@ -1246,15 +1246,15 @@ psa_status_t psa_asymmetric_sign(psa_key_handle_t handle, return (status); } -psa_status_t psa_asymmetric_verify(psa_key_handle_t handle, - psa_algorithm_t alg, - const uint8_t *hash, - size_t hash_length, - const uint8_t *signature, - size_t signature_size) +psa_status_t psa_verify_hash(psa_key_handle_t handle, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_size) { psa_crypto_ipc_asymmetric_t psa_crypto_ipc = { - .func = PSA_ASYMMETRIC_VERIFY, + .func = PSA_VERIFY_HASH, .handle = handle, .alg = alg, .input_length = 0, diff --git a/components/TARGET_PSA/services/crypto/COMPONENT_SPE/crypto_spe.h b/components/TARGET_PSA/services/crypto/COMPONENT_SPE/crypto_spe.h index 6b6bf19370..be55586abd 100644 --- a/components/TARGET_PSA/services/crypto/COMPONENT_SPE/crypto_spe.h +++ b/components/TARGET_PSA/services/crypto/COMPONENT_SPE/crypto_spe.h @@ -59,8 +59,8 @@ extern "C" { #define psa_aead_finish psa_sec_aead_finish #define psa_aead_verify psa_sec_aead_verify #define psa_aead_abort psa_sec_aead_abort -#define psa_asymmetric_sign psa_sec_asymmetric_sign -#define psa_asymmetric_verify psa_sec_asymmetric_verify +#define psa_sign_hash psa_sec_sign_hash +#define psa_verify_hash psa_sec_verify_hash #define psa_asymmetric_encrypt psa_sec_asymmetric_encrypt #define psa_asymmetric_decrypt psa_sec_asymmetric_decrypt #define psa_key_derivation_setup psa_sec_key_derivation_setup diff --git a/components/TARGET_PSA/services/crypto/COMPONENT_SPE/psa_crypto_partition.c b/components/TARGET_PSA/services/crypto/COMPONENT_SPE/psa_crypto_partition.c index 08893ce757..b6522bcdb9 100644 --- a/components/TARGET_PSA/services/crypto/COMPONENT_SPE/psa_crypto_partition.c +++ b/components/TARGET_PSA/services/crypto/COMPONENT_SPE/psa_crypto_partition.c @@ -989,7 +989,7 @@ static void psa_asymmetric_operation(void) } switch (psa_crypto.func) { - case PSA_ASYMMETRIC_SIGN: { + case PSA_SIGN_HASH: { uint8_t *signature = NULL; uint8_t *hash = NULL; size_t signature_length = 0, @@ -1015,9 +1015,9 @@ static void psa_asymmetric_operation(void) } if (status == PSA_SUCCESS) { - status = psa_asymmetric_sign(psa_crypto.handle, psa_crypto.alg, - hash, hash_size, - signature, signature_size, &signature_length); + status = psa_sign_hash(psa_crypto.handle, psa_crypto.alg, + hash, hash_size, + signature, signature_size, &signature_length); if (status == PSA_SUCCESS) { psa_write(msg.handle, 0, signature, signature_length); @@ -1030,7 +1030,7 @@ static void psa_asymmetric_operation(void) break; } - case PSA_ASYMMETRIC_VERIFY: { + case PSA_VERIFY_HASH: { uint8_t *signature = NULL; uint8_t *hash = NULL; size_t signature_size = msg.in_size[1], @@ -1060,9 +1060,9 @@ static void psa_asymmetric_operation(void) } if (status == PSA_SUCCESS) { - status = psa_asymmetric_verify(psa_crypto.handle, psa_crypto.alg, - hash, hash_size, - signature, signature_size); + status = psa_verify_hash(psa_crypto.handle, psa_crypto.alg, + hash, hash_size, + signature, signature_size); } mbedtls_free(signature); From 65e91244fa4889b9ea08af0272d50f71b8d8e4a0 Mon Sep 17 00:00:00 2001 From: Darryl Green Date: Thu, 26 Mar 2020 17:12:03 +0000 Subject: [PATCH 41/49] crypto: Use updated ECC curve macros --- TESTS/psa/attestation/main.cpp | 2 +- .../crypto_access_control/COMPONENT_NSPE/main.cpp | 2 +- .../COMPONENT_PSA_SRV_IMPL/attest_crypto_keys.c | 13 ++----------- .../frameworks/TARGET_PSA/pal/pal_mbed_os_intf.cpp | 2 +- 4 files changed, 5 insertions(+), 14 deletions(-) diff --git a/TESTS/psa/attestation/main.cpp b/TESTS/psa/attestation/main.cpp index 52430eea28..4bba662405 100755 --- a/TESTS/psa/attestation/main.cpp +++ b/TESTS/psa/attestation/main.cpp @@ -98,7 +98,7 @@ static void check_initial_attestation_get_token() TEST_ASSERT_EQUAL(status, PSA_SUCCESS); status = psa_attestation_inject_key(private_key_data, sizeof(private_key_data), - PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_CURVE_SECP256R1), + PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_CURVE_SECP_R1), exported, sizeof(exported), &exported_length); diff --git a/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp b/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp index a0f8852368..88d0d33e65 100644 --- a/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp +++ b/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp @@ -348,7 +348,7 @@ void test_use_other_partition_key_aead(void) void test_use_other_partition_key_asymmetric_sign_verify(void) { static const psa_key_id_t key_id = 999; - static const psa_key_type_t key_type = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_CURVE_SECP256R1); + static const psa_key_type_t key_type = PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_CURVE_SECP_R1); static const psa_algorithm_t key_alg = PSA_ALG_ECDSA(PSA_ALG_SHA_256); static const psa_key_usage_t key_usage = PSA_KEY_USAGE_SIGN | PSA_KEY_USAGE_VERIFY; static const size_t key_bits = 256; diff --git a/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/attest_crypto_keys.c b/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/attest_crypto_keys.c index e3b19a0749..e67227c8ff 100755 --- a/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/attest_crypto_keys.c +++ b/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/attest_crypto_keys.c @@ -48,21 +48,12 @@ static psa_status_t get_curve(psa_key_type_t type, enum ecc_curve_t *curve_type) { psa_ecc_curve_t curve = PSA_KEY_TYPE_GET_CURVE(type); switch (curve) { - case PSA_ECC_CURVE_SECP256R1: + case PSA_ECC_CURVE_SECP_R1: *curve_type = P_256; break; - case PSA_ECC_CURVE_SECP384R1: - *curve_type = P_384; - break; - case PSA_ECC_CURVE_SECP521R1: - *curve_type = P_521; - break; - case PSA_ECC_CURVE_CURVE25519: + case PSA_ECC_CURVE_MONTGOMERY: *curve_type = X25519; break; - case PSA_ECC_CURVE_CURVE448: - *curve_type = X448; - break; default: return (PSA_ERROR_NOT_SUPPORTED); } diff --git a/features/frameworks/TARGET_PSA/pal/pal_mbed_os_intf.cpp b/features/frameworks/TARGET_PSA/pal/pal_mbed_os_intf.cpp index ab1803ddc1..8eb71f15c2 100644 --- a/features/frameworks/TARGET_PSA/pal/pal_mbed_os_intf.cpp +++ b/features/frameworks/TARGET_PSA/pal/pal_mbed_os_intf.cpp @@ -63,7 +63,7 @@ static void psa_attestation_inject_key_for_test(void) psa_attestation_destroy_key_for_test(); psa_attestation_inject_key(private_key_data, sizeof(private_key_data), - PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_CURVE_SECP256R1), + PSA_KEY_TYPE_ECC_KEY_PAIR(PSA_ECC_CURVE_SECP_R1), exported, sizeof(exported), &exported_length); From d55117f2aaecd099afb222137cada97d33dd0c7e Mon Sep 17 00:00:00 2001 From: midd Date: Mon, 6 Apr 2020 15:00:57 -0700 Subject: [PATCH 42/49] WHD: Remove an assert from get_rssi() This assert in WhdSTAInterface.cpp causes rssi greentea test to fail on Cypress parts. This is because the rssi GT test expects the negative test case to return 0 and not assert. --- .../TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp index 0995b10145..1cbe7ebc2a 100644 --- a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp +++ b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp @@ -377,7 +377,6 @@ int8_t WhdSTAInterface::get_rssi() int32_t rssi; whd_result_t res; - // initialize wiced, this is noop if already init if (!_whd_emac.powered_up) { if(!_whd_emac.power_up()) { CY_ASSERT(false); @@ -386,7 +385,7 @@ int8_t WhdSTAInterface::get_rssi() res = (whd_result_t)whd_wifi_get_rssi(_whd_emac.ifp, &rssi); if (res != 0) { - CY_ASSERT(false); + /* The network GT tests expect that this function should return 0 in case of an error and not assert */ return 0; } From 6d2bc4f144f5d0ee90c61e21c3cb54690637b8f9 Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Tue, 18 Feb 2020 14:40:58 +0200 Subject: [PATCH 43/49] Update STM32 EMAC driver - limit RX frame length DISCO_F769NI EMAC driver may return ethernet packet with illegal length when driver is under heavy load. In one case, the received bytes indicate frame length of 53 bytes but advertised data length was 65518 bytes. In another case EMAC driver variable `EthHandle.RxFrameInfos.length` contained value 0xFFFF FFFC. As a work-around accept only 1-1500 bytes long ethernet packets. --- features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) mode change 100644 => 100755 features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp diff --git a/features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp b/features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp old mode 100644 new mode 100755 index a13e4d124c..55f82b16cb --- a/features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp +++ b/features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp @@ -546,7 +546,7 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf) dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc; - if (len > 0) { + if (len > 0 && EthHandle.RxFrameInfos.length <= 1500) { /* Allocate a memory buffer chain from buffer pool */ *buf = memory_manager->alloc_pool(len, 0); } From 38f9a09f127c141929c92db092a564cd5402ca22 Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Thu, 20 Feb 2020 15:49:58 +0200 Subject: [PATCH 44/49] Update STM32 EMAC driver based on review -Fix len type -Use ETH_RX_BUF_SIZE instead of hard-coded value 1500 --- features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp b/features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp index 55f82b16cb..6935b157ef 100755 --- a/features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp +++ b/features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp @@ -526,7 +526,7 @@ error: int STM32_EMAC::low_level_input(emac_mem_buf_t **buf) #ifndef ETH_IP_VERSION_V2 { - uint16_t len = 0; + uint32_t len = 0; uint8_t *buffer; __IO ETH_DMADescTypeDef *dmarxdesc; uint32_t bufferoffset = 0; @@ -546,7 +546,7 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf) dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc; - if (len > 0 && EthHandle.RxFrameInfos.length <= 1500) { + if (len > 0 && len <= ETH_RX_BUF_SIZE) { /* Allocate a memory buffer chain from buffer pool */ *buf = memory_manager->alloc_pool(len, 0); } From 6554e3951eba8d351adcbc936aecc782e072331a Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Wed, 8 Apr 2020 14:14:11 -0700 Subject: [PATCH 45/49] Revert "Backport #12603: Add CYSBSYSKIT_01" This reverts commit 4e6692b529a8814c0974ad2e23354b8b32c333ac. There are issues with wifi connectivity on this target that mean it is not ready to ship with 5.15.2. --- .../qspi/flash_configs/flash_configs.h | 3 +- .../interface/SclSTAInterface.cpp | 328 ----- .../COMPONENT_SCL/interface/SclSTAInterface.h | 165 --- .../interface/default_wifi_interface.cpp | 35 - .../COMPONENT_SCL/interface/scl_emac.cpp | 203 --- .../COMPONENT_SCL/interface/scl_emac.h | 189 --- features/netsocket/ppp/mbed_lib.json | 3 - .../COMPONENT_SCL/generated_mac_address.txt | 9 - .../COMPONENT_SCL/inc/scl_common.h | 211 --- .../TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h | 120 -- .../COMPONENT_SCL/inc/scl_types.h | 115 -- .../COMPONENT_SCL/inc/scl_wifi_api.h | 151 -- .../COMPONENT_SCL/src/IPC/scl_ipc.c | 293 ---- .../src/include/scl_buffer_api.h | 113 -- .../COMPONENT_SCL/src/scl_buffer_api.c | 82 -- .../COMPONENT_SCL/src/scl_wifi_api.c | 160 --- .../GeneratedSource/cycfg.c | 33 - .../GeneratedSource/cycfg.h | 47 - .../GeneratedSource/cycfg.timestamp | 26 - .../GeneratedSource/cycfg_notices.h | 32 - .../GeneratedSource/cycfg_pins.c | 177 --- .../GeneratedSource/cycfg_pins.h | 190 --- .../GeneratedSource/cycfg_qspi_memslot.c | 266 ---- .../GeneratedSource/cycfg_qspi_memslot.h | 51 - .../GeneratedSource/cycfg_routing.c | 31 - .../GeneratedSource/cycfg_routing.h | 46 - .../GeneratedSource/cycfg_system.c | 28 - .../GeneratedSource/cycfg_system.h | 43 - .../GeneratedSource/qspi_config.cfg | 2 - .../cyreservedresources.list | 99 -- .../design.cycapsense | 71 - .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 63 - .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 106 -- .../TARGET_CYSBSYSKIT_01/PeripheralPins.c | 427 ------ .../TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c | 115 -- .../TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h | 76 - .../TARGET_CYSBSYSKIT_01/cybsp_types.h | 194 --- .../TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct | 298 ---- .../TOOLCHAIN_ARM/startup_psoc6_02_cm4.S | 703 --------- .../TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld | 448 ------ .../TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S | 673 --------- .../TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf | 274 ---- .../TOOLCHAIN_IAR/startup_psoc6_02_cm4.S | 1263 ----------------- .../device/COMPONENT_CM4/system_psoc6_cm4.c | 552 ------- .../device/system_psoc6.h | 680 --------- targets/targets.json | 49 - 46 files changed, 1 insertion(+), 9242 deletions(-) delete mode 100644 features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp delete mode 100644 features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h delete mode 100644 features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp delete mode 100644 features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.cpp delete mode 100644 features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/generated_mac_address.txt delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/include/scl_buffer_api.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_buffer_api.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h diff --git a/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h b/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h index 215c75caf7..180a3d3bd7 100644 --- a/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h +++ b/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h @@ -69,8 +69,7 @@ defined(TARGET_CY8CPROTO_062S2_43012) || \ defined(TARGET_CY8CPROTO_062S3_4343W) || \ defined(TARGET_CYW943012P6EVB_01) || \ - defined(TARGET_CYW9P62S1_43438EVB_01) || \ - defined(TARGET_CYSBSYSKIT_01)) + defined(TARGET_CYW9P62S1_43438EVB_01)) #include "S25FL512S_config.h" #elif defined(TARGET_CYW9P62S1_43012EVB_01) diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp deleted file mode 100644 index 5a17077efb..0000000000 --- a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp +++ /dev/null @@ -1,328 +0,0 @@ -/* - * Copyright 2018-2020 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include "SclSTAInterface.h" -#include "nsapi.h" -#include "lwipopts.h" -#include "lwip/etharp.h" -#include "lwip/ethip6.h" -#include "rtos.h" -#include "scl_emac.h" -#include "scl_ipc.h" -#include "mbed_wait_api.h" - - -/** @file - * Provides SCL interface functions to be used with WiFiInterface or NetworkInterface Objects - */ - -struct scl_tx_nw_credentials { - nsapi_security_t network_security_type; - int ssid_len; - int pass_len; - const char *network_ssid; - const char *network_passphrase; -} scl_tx_nw_credentials_t; - -network_params_t network_parameter; - -int scl_toerror(scl_result_t res) -{ - switch (res) { - case SCL_SUCCESS: - return NSAPI_ERROR_OK; - case SCL_UNSUPPORTED: - return NSAPI_ERROR_UNSUPPORTED; - case SCL_BADARG: - return NSAPI_ERROR_PARAMETER; - case SCL_INVALID_JOIN_STATUS: - return NSAPI_ERROR_NO_CONNECTION; - case SCL_BUFFER_UNAVAILABLE_PERMANENT: - case SCL_BUFFER_UNAVAILABLE_TEMPORARY: - case SCL_RX_BUFFER_ALLOC_FAIL: - case SCL_BUFFER_ALLOC_FAIL: - case SCL_MALLOC_FAILURE: - return NSAPI_ERROR_NO_MEMORY; - case SCL_ACCESS_POINT_NOT_FOUND: - case SCL_NETWORK_NOT_FOUND: - return NSAPI_ERROR_NO_SSID; - case SCL_NOT_AUTHENTICATED: - case SCL_INVALID_KEY: - case SCL_NOT_KEYED: - return NSAPI_ERROR_AUTH_FAILURE; - case SCL_PENDING: - case SCL_JOIN_IN_PROGRESS: - return NSAPI_ERROR_IN_PROGRESS; - case SCL_CONNECTION_LOST: - return NSAPI_ERROR_CONNECTION_LOST; - case SCL_TIMEOUT: - case SCL_EAPOL_KEY_PACKET_M1_TIMEOUT: - case SCL_EAPOL_KEY_PACKET_M3_TIMEOUT: - case SCL_EAPOL_KEY_PACKET_G1_TIMEOUT: - return NSAPI_ERROR_CONNECTION_TIMEOUT; - default: - return -res; - } -} - -nsapi_security_t scl_tosecurity(scl_security_t sec) -{ - switch (sec) { - case SCL_SECURITY_OPEN: - return NSAPI_SECURITY_NONE; - case SCL_SECURITY_WEP_PSK: - case SCL_SECURITY_WEP_SHARED: - return NSAPI_SECURITY_WEP; - case SCL_SECURITY_WPA_TKIP_PSK: - case SCL_SECURITY_WPA_TKIP_ENT: - return NSAPI_SECURITY_WPA; - case SCL_SECURITY_WPA2_MIXED_PSK: - return NSAPI_SECURITY_WPA_WPA2; - case SCL_SECURITY_WPA2_AES_PSK: - case SCL_SECURITY_WPA2_AES_ENT: - case SCL_SECURITY_WPA2_FBT_PSK: - case SCL_SECURITY_WPA2_FBT_ENT: - return NSAPI_SECURITY_WPA2; - default: - return NSAPI_SECURITY_UNKNOWN; - } -} - -scl_security_t scl_fromsecurity(nsapi_security_t sec) -{ - switch (sec) { - case NSAPI_SECURITY_NONE: - return SCL_SECURITY_OPEN; - case NSAPI_SECURITY_WEP: - return SCL_SECURITY_WEP_PSK; - case NSAPI_SECURITY_WPA: - return SCL_SECURITY_WPA_MIXED_PSK; - case NSAPI_SECURITY_WPA2: - return SCL_SECURITY_WPA2_AES_PSK; - case NSAPI_SECURITY_WPA_WPA2: - return SCL_SECURITY_WPA2_MIXED_PSK; - default: - return SCL_SECURITY_UNKNOWN; - } -} - -SclSTAInterface::SclSTAInterface(SCL_EMAC &emac, OnboardNetworkStack &stack) - : EMACInterface(emac, stack), - _ssid("\0"), - _pass("\0"), - _security(NSAPI_SECURITY_NONE), - _scl_emac(emac) -{ -} - -nsapi_error_t SclSTAInterface::connect(const char *ssid, const char *pass, nsapi_security_t security, uint8_t channel) -{ - int err = set_channel(channel); - if (err) { - return err; - } - - err = set_credentials(ssid, pass, security); - if (err) { - return err; - } - - return connect(); -} - -nsapi_error_t SclSTAInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) -{ - if ((ssid == NULL) || - (strlen(ssid) == 0) || - (pass == NULL && (security != NSAPI_SECURITY_NONE)) || - (strlen(pass) == 0 && (security != NSAPI_SECURITY_NONE)) || - (strlen(pass) > 63 && (security == NSAPI_SECURITY_WPA2 || security == NSAPI_SECURITY_WPA || security == NSAPI_SECURITY_WPA_WPA2)) - ) { - return NSAPI_ERROR_PARAMETER; - } - - memset(_ssid, 0, sizeof(_ssid)); - strncpy(_ssid, ssid, sizeof(_ssid)); - - memset(_pass, 0, sizeof(_pass)); - strncpy(_pass, pass, sizeof(_pass)); - - _security = security; - - return NSAPI_ERROR_OK; -} - -nsapi_error_t SclSTAInterface::connect() -{ - - uint32_t delay_timeout = 0; - scl_result_t ret_val; - nsapi_error_t interface_status; - uint32_t connection_status = 0; - - scl_tx_nw_credentials_t.network_ssid = _ssid; - if (strlen(_ssid) < MAX_SSID_LENGTH) { - scl_tx_nw_credentials_t.ssid_len = strlen(_ssid); - } - scl_tx_nw_credentials_t.network_passphrase = _pass; - if (strlen(_pass) < MAX_PASSWORD_LENGTH) { - scl_tx_nw_credentials_t.pass_len = strlen(_pass); - } - scl_tx_nw_credentials_t.network_security_type = _security; - - ret_val = scl_send_data(SCL_TX_CONNECT, (char *)&scl_tx_nw_credentials_t, TIMER_DEFAULT_VALUE); - - if (ret_val == SCL_SUCCESS) { - SCL_LOG(("wifi provisioning in progress")); - } - - network_parameter.connection_status = NSAPI_STATUS_DISCONNECTED; - - - //Get the network parameter from NP - while ((network_parameter.connection_status != NSAPI_STATUS_GLOBAL_UP) && delay_timeout < NW_CONNECT_TIMEOUT) { - ret_val = scl_get_nw_parameters(&network_parameter); - wait_us(NW_DELAY_TIME_US); - delay_timeout++; - } - - if (delay_timeout >= NW_CONNECT_TIMEOUT || ret_val != SCL_SUCCESS) { - return NSAPI_ERROR_NO_CONNECTION; - } - - if (!_scl_emac.powered_up) { - _scl_emac.power_up(); - } - - if (!_interface) { - nsapi_error_t err = _stack.add_ethernet_interface(_emac, true, &_interface); - if (err != NSAPI_ERROR_OK) { - _interface = NULL; - return err; - } - _interface->attach(_connection_status_cb); - } - - if (!scl_wifi_is_ready_to_transceive()) { - scl_emac_wifi_link_state_changed(true); - } - - interface_status = _interface->bringup(false, - network_parameter.ip_address, - network_parameter.netmask, - network_parameter.gateway, - DEFAULT_STACK); - - scl_send_data(SCL_TX_CONNECTION_STATUS, (char *)&connection_status, TIMER_DEFAULT_VALUE); - - return interface_status; -} - -void SclSTAInterface::wifi_on() -{ - if (!_scl_emac.powered_up) { - _scl_emac.power_up(); - } -} - -nsapi_error_t SclSTAInterface::disconnect() -{ - scl_result_t ret_val; - nsapi_error_t disconnect_status; - ret_val = scl_send_data(SCL_TX_DISCONNECT, (char *)&disconnect_status, TIMER_DEFAULT_VALUE); - - if (ret_val == SCL_ERROR) { - return NSAPI_ERROR_TIMEOUT; - } - - if (!_interface) { - return NSAPI_STATUS_DISCONNECTED; - } - - // bring down - int err = _interface->bringdown(); - if (err) { - return err; - } - - scl_emac_wifi_link_state_changed(false); - - return NSAPI_ERROR_OK; -} - -int SclSTAInterface::scan(WiFiAccessPoint *res, unsigned count) -{ - /* To Do */ - return NSAPI_ERROR_UNSUPPORTED; -} - -int8_t SclSTAInterface::get_rssi() -{ - int32_t rssi; - scl_result_t res; - - if (!_scl_emac.powered_up) { - _scl_emac.power_up(); - } - - res = (scl_result_t) scl_wifi_get_rssi(&rssi); - if (res == SCL_ERROR) { - return SCL_ERROR; - } - - return (int8_t)rssi; -} - -int SclSTAInterface::is_interface_connected(void) -{ - if (scl_wifi_is_ready_to_transceive() == SCL_SUCCESS) { - return SCL_SUCCESS; - } else { - return SCL_CONNECTION_LOST; - } -} - -int SclSTAInterface::get_bssid(uint8_t *bssid) -{ - scl_mac_t ap_mac; - scl_result_t res = SCL_SUCCESS; - - if (bssid == NULL) { - return SCL_BADARG; - } - - memset(&ap_mac, 0, sizeof(ap_mac)); - if (scl_wifi_is_ready_to_transceive() == SCL_SUCCESS) { - res = (scl_result_t) scl_wifi_get_bssid(&ap_mac); - if (res == SCL_SUCCESS) { - memcpy(bssid, ap_mac.octet, sizeof(ap_mac.octet)); - } - } else { - return SCL_CONNECTION_LOST; - } - return res; -} - -int SclSTAInterface::wifi_set_up(void) -{ - int res = SCL_SUCCESS; - res = scl_wifi_set_up(); - return res; -} diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h deleted file mode 100644 index 801a9a5dfc..0000000000 --- a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright 2018-2020 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SCL_STA_INTERFACE_H -#define SCL_STA_INTERFACE_H - - -/** @file - * Provides SCL interface functions to be used with WiFiInterface or NetworkInterface Objects - */ - -#include "netsocket/WiFiInterface.h" -#include "netsocket/EMACInterface.h" -#include "netsocket/OnboardNetworkStack.h" -#include "scl_emac.h" -#include "scl_wifi_api.h" -#include "scl_types.h" -#define MAX_SSID_LENGTH (33) /**< Maximum ssid length */ -#define MAX_PASSWORD_LENGTH (64) /**< Maximum password length */ - -/** SclSTAInterface class - * Implementation of the Network Stack for the SCL - */ -class SclSTAInterface : public WiFiInterface, public EMACInterface { -public: - - SclSTAInterface( - SCL_EMAC &emac = SCL_EMAC::get_instance(), - OnboardNetworkStack &stack = OnboardNetworkStack::get_default_instance()); - - /** Gets the current instance of the SclSTAInterface - * - * @return Pointer to the object of class SclSTAInterface. - */ - static SclSTAInterface *get_default_instance(); - - /** Turns on the Wi-Fi device - * - * @return void - */ - void wifi_on(); - - /** Starts the interface - * - * Attempts to connect to a Wi-Fi network. Requires ssid and passphrase to be set. - * If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned. - * - * @return 0 on success, negative error code on failure. - */ - nsapi_error_t connect(); - - /** Starts the interface - * - * Attempts to connect to a Wi-Fi network. - * - * @param ssid Name of the network to connect to. - * @param pass Security passphrase to connect to the network. - * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE). - * @param channel This parameter is not supported, setting it to a value other than 0 will result in NSAPI_ERROR_UNSUPPORTED. - * @return 0 on success, negative error code on failure. - */ - nsapi_error_t connect(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE, uint8_t channel = 0); - - /** Disconnects the interface - * - * @return 0 on success, negative error code on failure. - */ - nsapi_error_t disconnect(); - - /** Set the Wi-Fi network credentials - * - * @param ssid Name of the network to connect to. - * @param pass Security passphrase to connect to the network. - * @param security Type of encryption for connection. - * (defaults to NSAPI_SECURITY_NONE) - * @return 0 on success, negative error code on failure. - */ - nsapi_error_t set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE); - - /** Sets the Wi-Fi network channel - NOT SUPPORTED - * - * This function is not supported and will return NSAPI_ERROR_UNSUPPORTED. - * - * @param channel Channel on which the connection is to be made (Default: 0). - * @return Not supported, returns NSAPI_ERROR_UNSUPPORTED. - */ - nsapi_error_t set_channel(uint8_t channel) - { - if (channel != 0) { - return NSAPI_ERROR_UNSUPPORTED; - } - return 0; - } - - /** Set blocking status of interface. - * Nonblocking mode is not supported. - * - * @param blocking True if connect is blocking - * @return 0 on success, negative error code on failure - */ - nsapi_error_t set_blocking(bool blocking) - { - if (blocking) { - _blocking = blocking; - return NSAPI_ERROR_OK; - } else { - return NSAPI_ERROR_UNSUPPORTED; - } - } - /** Gets the current radio signal strength for active connection - * - * @return Connection strength in dBm (negative value). - */ - int8_t get_rssi(); - - /** Scans for available networks - NOT SUPPORTED - * - * @return NSAPI_ERROR_UNSUPPORTED - */ - int scan(WiFiAccessPoint *res, unsigned count); - - /** This function is used to indicate if the device is connected to the network. - * - * @return SCL_SUCCESS if device is connected. - */ - int is_interface_connected(); - - /** Gets the BSSID (MAC address of device connected to). - * - * @param bssid Pointer to the BSSID value. - * @return SCL_SUCCESS if BSSID is obtained successfully. - * @return SCL_BADARG if input parameter is NULL. - * @return SCL_ERROR if unable to fetch BSSID. - */ - int get_bssid(uint8_t *bssid); - - /** This function is used to set up the Wi-Fi interface. - * This function should be used after the wifi_on. - * - * @return SCL_SUCCESS if the Wi-Fi interface is set up successfully. - */ - int wifi_set_up(void); - -private: - - char _ssid[MAX_SSID_LENGTH]; /**< The longest possible name (defined in 802.11) +1 for the \0 */ - char _pass[MAX_PASSWORD_LENGTH]; /**< The longest allowed passphrase + 1 */ - nsapi_security_t _security; /**< Security type */ - SCL_EMAC &_scl_emac; /**< SCL_EMAC object */ -}; -#endif /* ifndef SCL_STA_INTERFACE_H */ diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp deleted file mode 100644 index 59cb5ef0ab..0000000000 --- a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2018-2020 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "SclSTAInterface.h" - -/** @file -* Provides function definition to override get_target_default_intance of WiFiInterface and NetworkInterface classes -*/ - -/** - * Returns the WiFiInterface Object - * This function can be called using WiFiInterface or NetworkInterface objects - * - * @return pointer to WiFiInterface object. - */ - -WiFiInterface *WiFiInterface::get_target_default_instance() -{ - static SclSTAInterface wifi; - return &wifi; -} diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.cpp b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.cpp deleted file mode 100644 index d7a276858e..0000000000 --- a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.cpp +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright 2018-2020 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include -#include -#include - -#include "cmsis_os.h" -#include "scl_emac.h" -#include "lwip/etharp.h" -#include "lwip/ethip6.h" -#include "mbed_shared_queues.h" -#include "scl_buffer_api.h" -#include "cy_result.h" -#include "cy_pdl.h" -#include "scl_ipc.h" - -/** @file - * Provides EMAC interface functions to be used with the SCL_EMAC object - */ - -SCL_EMAC::SCL_EMAC(scl_interface_role_t role) - : interface_type(role) -{ -} - -SCL_EMAC::SCL_EMAC() - : interface_type(SCL_STA_ROLE) -{ -} - -SCL_EMAC &SCL_EMAC::get_instance() -{ - return get_instance(SCL_STA_ROLE); -} - -SCL_EMAC &SCL_EMAC::get_instance(scl_interface_role_t role) -{ - static SCL_EMAC emac_sta(SCL_STA_ROLE); - static SCL_EMAC emac_ap(SCL_AP_ROLE); - return role == SCL_AP_ROLE ? emac_ap : emac_sta; -} - -uint32_t SCL_EMAC::get_mtu_size() const -{ - return SCL_PAYLOAD_MTU; -} - -uint32_t SCL_EMAC::get_align_preference() const -{ - return 0; -} - -void SCL_EMAC::add_multicast_group(const uint8_t *addr) -{ - memcpy(multicast_addr.octet, addr, sizeof(multicast_addr.octet)); - scl_wifi_register_multicast_address(&multicast_addr); -} - -void SCL_EMAC::remove_multicast_group(const uint8_t *address) -{ - /* To Do */ -} -void SCL_EMAC::set_all_multicast(bool all) -{ - /* No-op at this stage */ -} - -void SCL_EMAC::power_down() -{ - /* No-op at this stage */ -} - -bool SCL_EMAC::power_up() -{ - if (!powered_up) { - if (scl_wifi_on() != true) { - SCL_LOG(("returning False in scl_wifi_on()\n")); - return false; - } - powered_up = true; - if (link_state && emac_link_state_cb) { - emac_link_state_cb(link_state); - } - } - return true; -} - -bool SCL_EMAC::get_hwaddr(uint8_t *addr) const -{ - scl_mac_t mac; - scl_result_t res = scl_wifi_get_mac_address(&mac); - if (res == SCL_SUCCESS) { - memcpy(addr, mac.octet, sizeof(mac.octet)); - return true; - } else { - SCL_LOG(("return False in SCL_EMAC::gethwaddr\n")); - return false; - } - -} - -void SCL_EMAC::set_hwaddr(const uint8_t *addr) -{ - /* No-op at this stage */ -} - -uint8_t SCL_EMAC::get_hwaddr_size() const -{ - scl_mac_t mac; - return sizeof(mac.octet); -} - -void SCL_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb) -{ - emac_link_input_cb = input_cb; -} - -void SCL_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb) -{ - emac_link_state_cb = state_cb; -} - -void SCL_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr) -{ - memory_manager = &mem_mngr; -} - -bool SCL_EMAC::link_out(emac_mem_buf_t *buf) -{ - scl_result_t retval; - scl_tx_buf_t scl_tx_data; - scl_tx_data.size = memory_manager->get_total_len(buf); - scl_tx_data.buffer = buf; - if (buf == NULL) { - return false; - } - retval = scl_network_send_ethernet_data(scl_tx_data); - if (retval != SCL_SUCCESS) { - return false; - } - memory_manager->free(buf); - return true; -} - -void SCL_EMAC::get_ifname(char *name, uint8_t size) const -{ - if (name != NULL) { - memcpy(name, "scl", size); - } -} - -void SCL_EMAC::set_activity_cb(mbed::Callback cb) -{ - activity_cb = cb; -} - -extern "C" -{ - void scl_network_process_ethernet_data(scl_buffer_t buffer) - { - emac_mem_buf_t *mem_buf = NULL; - - SCL_EMAC &emac = SCL_EMAC::get_instance(SCL_STA_ROLE); - - if (!emac.powered_up && !emac.emac_link_input_cb) { - scl_buffer_release(buffer, SCL_NETWORK_RX); - return; - } - mem_buf = buffer; - if (emac.activity_cb) { - emac.activity_cb(false); - } - emac.emac_link_input_cb(mem_buf); - } - - void scl_emac_wifi_link_state_changed(bool state_up) - { - SCL_EMAC &emac = SCL_EMAC::get_instance(SCL_STA_ROLE); - - emac.link_state = state_up; - if (emac.emac_link_state_cb) { - emac.emac_link_state_cb(state_up); - } - } -} // extern "C" - - diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.h b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.h deleted file mode 100644 index e6e3ecd8a9..0000000000 --- a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright 2018-2020 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef SCL_EMAC_H_ -#define SCL_EMAC_H_ - -/** @file - * Provides EMAC interface functions to be used with the SCL_EMAC object - * - */ -#include "EMAC.h" -#include "EMACInterface.h" -#include "WiFiInterface.h" -#include "scl_common.h" -#include "rtos/Semaphore.h" -#include "rtos/Mutex.h" -#include "scl_wifi_api.h" -class SCL_EMAC : public EMAC { -public: - SCL_EMAC(); - SCL_EMAC(scl_interface_role_t itype); - - /** - * Get the EMAC instance - * - * @return Reference to SCL_EMAC object. - */ - static SCL_EMAC &get_instance(); - - /** - * Get the EMAC instance - * - * @param role Interface type. - * - * @return Reference to SCL_EMAC object. - */ - static SCL_EMAC &get_instance(scl_interface_role_t role); - - /** - * Returns the maximum transmission unit - * - * @return MTU in bytes. - */ - virtual uint32_t get_mtu_size() const; - - /** - * Gets the memory buffer alignment preference - * - * Gets the preferred memory buffer alignment of the EMAC device. IP stack may or may not - * align with the link out memory buffer chains using the alignment. - * - * @return Memory alignment requirement in bytes. - */ - virtual uint32_t get_align_preference() const; - - /** - * Returns the interface name - * - * @param name Pointer to the location where the name should be written. - * @param size Maximum number of characters to copy. - */ - virtual void get_ifname(char *name, uint8_t size) const; - - /** - * Returns the size of the underlying interface HW address size. - * - * @return HW address size in bytes. - */ - virtual uint8_t get_hwaddr_size() const; - - /** - * Returns the interface supplied HW address - * Copies the HW address to the provided memory - * @param addr HW address of the underlying interface. It must be of correct size. See @a get_hwaddr_size. - * @return True if HW address is available. - */ - virtual bool get_hwaddr(uint8_t *addr) const; - - /** - * Set HW address for the interface - * - * Provided address must be of correct size. See @a get_hwaddr_size. - * - * Called to set the MAC address to be used - if @a get_hwaddr is provided - * the stack would normally use that, but it could be overridden for test - * purposes. - * - * @param addr Address to be set - */ - virtual void set_hwaddr(const uint8_t *addr); - - /** - * Sends the packet over the link - * - * This cannot be called from an interrupt context. - * - * @param buf Packet to be sent. - * @return True if the packet was sent successfully. False otherwise. - */ - virtual bool link_out(emac_mem_buf_t *buf); - - /** - * Initializes the HW - * - * @return True on success. False in case of an error. - */ - virtual bool power_up(); - - /** - * De-initializes the HW - */ - virtual void power_down(); - - /** - * Sets a callback that is called for packets received for a given interface - * - * @param input_cb Function to be registered as a callback. - */ - virtual void set_link_input_cb(emac_link_input_cb_t input_cb); - - /** - * Sets a callback that is called on changes in the link status for a given interface - * - * @param state_cb Function to be registered as a callback. - */ - virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb); - - /** Adds a device to a multicast group - * - * @param address A multicast group hardware address. - */ - virtual void add_multicast_group(const uint8_t *address); - - /** Removes a device from a multicast group - * - * @param address A multicast group hardware address. - */ - virtual void remove_multicast_group(const uint8_t *address); - - /** Requests reception of all multicast packets - * - * @param all True to receive all multicasts. - * False to receive only multicasts addressed to specified groups. - */ - virtual void set_all_multicast(bool all); - - /** Sets memory manager used to handle memory buffers - * - * @param mem_mngr Pointer to memory manager. - */ - virtual void set_memory_manager(EMACMemoryManager &mem_mngr); - - /** Sets callback to receive EMAC activity events - * - * @param activity_cb The callback for activity events. - */ - virtual void set_activity_cb(mbed::Callback activity_cb); - - emac_link_input_cb_t emac_link_input_cb = NULL; /**< Callback for incoming data */ - emac_link_state_change_cb_t emac_link_state_cb = NULL; /**< Callback for network connection status */ - EMACMemoryManager *memory_manager; /**< Pointer to hold memory manager object */ - bool powered_up = false; /**< Flag for Wi-Fi power on status */ - bool link_state = false; /**< Flag for network connection status */ - scl_interface_role_t interface_type; /**< Type of the interface */ - scl_mac_t multicast_addr; /**< Multicast address */ - mbed::Callback activity_cb; /**< Callback for activity on network */ - -}; -/** Sends the change in network connection state to network stack -* -* @param state_up Connection status. -*/ -extern "C" void scl_emac_wifi_link_state_changed(bool state_up); - -#endif /* SCL_EMAC_H_ */ diff --git a/features/netsocket/ppp/mbed_lib.json b/features/netsocket/ppp/mbed_lib.json index a95bfd25bb..33bdb3df99 100644 --- a/features/netsocket/ppp/mbed_lib.json +++ b/features/netsocket/ppp/mbed_lib.json @@ -47,9 +47,6 @@ }, "CY8CKIT_062S2_43012": { "thread-stacksize": 896 - }, - "CYSBSYSKIT_01": { - "thread-stacksize": 896 } } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/generated_mac_address.txt b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/generated_mac_address.txt deleted file mode 100644 index cba1ab8625..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/generated_mac_address.txt +++ /dev/null @@ -1,9 +0,0 @@ -/* - * This file is used to set the MAC address in NVRAM. - * The MAC address of the Wi-Fi device may be configured in OTP and/or in NVRAM. - * If both OTP and NVRAM contains the MAC address then OTP programmed MAC address will be used. - * PSOC boards are usually programmed with OTP MAC address. - * MAC address is printed during SCL power up - */ - -#define NVRAM_GENERATED_MAC_ADDRESS "macaddr=00:A0:50:45:2e:c8" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h deleted file mode 100644 index 42e0b1c02d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright 2018-2020 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** @file scl_common.h - * Defines common data types used in SCL - */ - -#include -#include "cy_result.h" - -#ifndef INCLUDED_SCL_COMMON_H_ -#define INCLUDED_SCL_COMMON_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/****************************************************** -* Constants -******************************************************/ - -#define SCL_LOG_ENABLE false /**< Flag to enable SCL debug logs */ -#define SCL_LOG(x) if (SCL_LOG_ENABLE) \ - { printf x; } /**< SCL log interface */ -#define CHECK_BUFFER_NULL(buf) if (buf == NULL)\ - { SCL_LOG(("Buffer pointer is null\n")); \ - return SCL_BADARG; } /**< Helper macro to check if the input buffer pointer is null */ - -#define MODULE_BASE_CODE (0x0080U) /**< Base code for the SCL error status */ -#define SCL_RESULT_TYPE (0) /**< SCL Result type */ - -/* - * scl_result_t Error code format - * |31-18 (14 bit) for module id|17-16 (2 bit) for result type|15-0 for SCL Error code| - * for example, for Error code 1026, the result of SCL_RESULT_CREATE is 33555458. - */ -#define SCL_RESULT_CREATE(x) CY_RSLT_CREATE(SCL_RESULT_TYPE, MODULE_BASE_CODE, (x) ) /**< Create a result value from the specified type, module, and result code */ - -#define SCL_SUCCESS (0) /**< IPC success */ -#define SCL_ERROR (100) /**< IPC error */ -#define SCL_PENDING SCL_RESULT_CREATE(1) /**< IPC Pending */ -#define SCL_TIMEOUT SCL_RESULT_CREATE(2) /**< Timeout */ -#define SCL_BADARG SCL_RESULT_CREATE(5) /**< Bad Arguments */ -#define SCL_UNFINISHED SCL_RESULT_CREATE(10) /**< Operation not finished yet (maybe aborted) */ -#define SCL_PARTIAL_RESULTS SCL_RESULT_CREATE(1003) /**< Partial results */ -#define SCL_INVALID_KEY SCL_RESULT_CREATE(1004) /**< Invalid key */ -#define SCL_DOES_NOT_EXIST SCL_RESULT_CREATE(1005) /**< Does not exist */ -#define SCL_NOT_AUTHENTICATED SCL_RESULT_CREATE(1006) /**< Not authenticated */ -#define SCL_NOT_KEYED SCL_RESULT_CREATE(1007) /**< Not keyed */ -#define SCL_IOCTL_FAIL SCL_RESULT_CREATE(1008) /**< IOCTL fail */ -#define SCL_BUFFER_UNAVAILABLE_TEMPORARY SCL_RESULT_CREATE(1009) /**< Buffer unavailable temporarily */ -#define SCL_BUFFER_UNAVAILABLE_PERMANENT SCL_RESULT_CREATE(1010) /**< Buffer unavailable permanently */ -#define SCL_CONNECTION_LOST SCL_RESULT_CREATE(1012) /**< Connection lost */ -#define SCL_OUT_OF_EVENT_HANDLER_SPACE SCL_RESULT_CREATE(1013) /**< Cannot add extra event handler */ -#define SCL_SEMAPHORE_ERROR SCL_RESULT_CREATE(1014) /**< Error manipulating a semaphore */ -#define SCL_FLOW_CONTROLLED SCL_RESULT_CREATE(1015) /**< Packet retrieval cancelled due to flow control */ -#define SCL_NO_CREDITS SCL_RESULT_CREATE(1016) /**< Packet retrieval cancelled due to lack of bus credits */ -#define SCL_NO_PACKET_TO_SEND SCL_RESULT_CREATE(1017) /**< Packet retrieval cancelled due to no pending packets */ -#define SCL_CORE_CLOCK_NOT_ENABLED SCL_RESULT_CREATE(1018) /**< Core disabled due to no clock */ -#define SCL_CORE_IN_RESET SCL_RESULT_CREATE(1019) /**< Core disabled - in reset */ -#define SCL_UNSUPPORTED SCL_RESULT_CREATE(1020) /**< Unsupported function */ -#define SCL_BUS_WRITE_REGISTER_ERROR SCL_RESULT_CREATE(1021) /**< Error writing to WLAN register */ -#define SCL_SDIO_BUS_UP_FAIL SCL_RESULT_CREATE(1022) /**< SDIO bus failed to come up */ -#define SCL_JOIN_IN_PROGRESS SCL_RESULT_CREATE(1023) /**< Join not finished yet */ -#define SCL_NETWORK_NOT_FOUND SCL_RESULT_CREATE(1024) /**< Specified network was not found */ -#define SCL_INVALID_JOIN_STATUS SCL_RESULT_CREATE(1025) /**< Join status error */ -#define SCL_UNKNOWN_INTERFACE SCL_RESULT_CREATE(1026) /**< Unknown interface specified */ -#define SCL_SDIO_RX_FAIL SCL_RESULT_CREATE(1027) /**< Error during SDIO receive */ -#define SCL_HWTAG_MISMATCH SCL_RESULT_CREATE(1028) /**< Hardware tag header corrupt */ -#define SCL_RX_BUFFER_ALLOC_FAIL SCL_RESULT_CREATE(1029) /**< Failed to allocate a buffer to receive into */ -#define SCL_BUS_READ_REGISTER_ERROR SCL_RESULT_CREATE(1030) /**< Error reading a bus hardware register */ -#define SCL_THREAD_CREATE_FAILED SCL_RESULT_CREATE(1031) /**< Failed to create a new thread */ -#define SCL_QUEUE_ERROR SCL_RESULT_CREATE(1032) /**< Error manipulating a queue */ -#define SCL_BUFFER_POINTER_MOVE_ERROR SCL_RESULT_CREATE(1033) /**< Error moving the current pointer of a packet buffer */ -#define SCL_BUFFER_SIZE_SET_ERROR SCL_RESULT_CREATE(1034) /**< Error setting size of packet buffer */ -#define SCL_THREAD_STACK_NULL SCL_RESULT_CREATE(1035) /**< Null stack pointer passed when non null was required */ -#define SCL_THREAD_DELETE_FAIL SCL_RESULT_CREATE(1036) /**< Error deleting a thread */ -#define SCL_SLEEP_ERROR SCL_RESULT_CREATE(1037) /**< Error sleeping a thread */ -#define SCL_BUFFER_ALLOC_FAIL SCL_RESULT_CREATE(1038) /**< Failed to allocate a packet buffer */ -#define SCL_NO_PACKET_TO_RECEIVE SCL_RESULT_CREATE(1039) /**< No Packets waiting to be received */ -#define SCL_INTERFACE_NOT_UP SCL_RESULT_CREATE(1040) /**< Requested interface is not active */ -#define SCL_DELAY_TOO_LONG SCL_RESULT_CREATE(1041) /**< Requested delay is too long */ -#define SCL_INVALID_DUTY_CYCLE SCL_RESULT_CREATE(1042) /**< Duty cycle is outside limit 0 to 100 */ -#define SCL_PMK_WRONG_LENGTH SCL_RESULT_CREATE(1043) /**< Returned pmk was the wrong length */ -#define SCL_UNKNOWN_SECURITY_TYPE SCL_RESULT_CREATE(1044) /**< AP security type was unknown */ -#define SCL_WEP_NOT_ALLOWED SCL_RESULT_CREATE(1045) /**< AP not allowed to use WEP - it is not secure - use Open instead */ -#define SCL_WPA_KEYLEN_BAD SCL_RESULT_CREATE(1046) /**< WPA / WPA2 key length must be between 8 & 64 bytes */ -#define SCL_FILTER_NOT_FOUND SCL_RESULT_CREATE(1047) /**< Specified filter id not found */ -#define SCL_SPI_ID_READ_FAIL SCL_RESULT_CREATE(1048) /**< Failed to read 0xfeedbead SPI id from chip */ -#define SCL_SPI_SIZE_MISMATCH SCL_RESULT_CREATE(1049) /**< Mismatch in sizes between SPI header and SDPCM header */ -#define SCL_ADDRESS_ALREADY_REGISTERED SCL_RESULT_CREATE(1050) /**< Attempt to register a multicast address twice */ -#define SCL_SDIO_RETRIES_EXCEEDED SCL_RESULT_CREATE(1051) /**< SDIO transfer failed too many times. */ -#define SCL_NULL_PTR_ARG SCL_RESULT_CREATE(1052) /**< Null Pointer argument passed to function. */ -#define SCL_THREAD_FINISH_FAIL SCL_RESULT_CREATE(1053) /**< Error deleting a thread */ -#define SCL_WAIT_ABORTED SCL_RESULT_CREATE(1054) /**< Semaphore/mutex wait has been aborted */ -#define SCL_SET_BLOCK_ACK_WINDOW_FAIL SCL_RESULT_CREATE(1055) /**< Failed to set block ack window */ -#define SCL_DELAY_TOO_SHORT SCL_RESULT_CREATE(1056) /**< Requested delay is too short */ -#define SCL_INVALID_INTERFACE SCL_RESULT_CREATE(1057) /**< Invalid interface provided */ -#define SCL_WEP_KEYLEN_BAD SCL_RESULT_CREATE(1058) /**< WEP / WEP_SHARED key length must be 5 or 13 bytes */ -#define SCL_HANDLER_ALREADY_REGISTERED SCL_RESULT_CREATE(1059) /**< EAPOL handler already registered */ -#define SCL_AP_ALREADY_UP SCL_RESULT_CREATE(1060) /**< Soft AP or P2P group owner already up */ -#define SCL_EAPOL_KEY_PACKET_M1_TIMEOUT SCL_RESULT_CREATE(1061) /**< Timeout occurred while waiting for EAPOL packet M1 from AP */ -#define SCL_EAPOL_KEY_PACKET_M3_TIMEOUT SCL_RESULT_CREATE(1062) /**< Timeout occurred while waiting for EAPOL packet M3 from AP which may indicate incorrect WPA2/WPA passphrase */ -#define SCL_EAPOL_KEY_PACKET_G1_TIMEOUT SCL_RESULT_CREATE(1063) /**< Timeout occurred while waiting for EAPOL packet G1 from AP */ -#define SCL_EAPOL_KEY_FAILURE SCL_RESULT_CREATE(1064) /**< Unknown failure occurred during the EAPOL key handshake */ -#define SCL_MALLOC_FAILURE SCL_RESULT_CREATE(1065) /**< Memory allocation failure */ -#define SCL_ACCESS_POINT_NOT_FOUND SCL_RESULT_CREATE(1066) /**< Access point not found */ -#define SCL_RTOS_ERROR SCL_RESULT_CREATE(1067) /**< RTOS operation failed */ -#define SCL_CLM_BLOB_DLOAD_ERROR SCL_RESULT_CREATE(1068) /**< CLM blob download failed */ -#define SCL_HAL_ERROR SCL_RESULT_CREATE(1069) /**< SCL HAL Error */ -#define SCL_RTOS_STATIC_MEM_LIMIT SCL_RESULT_CREATE(1070) /**< Exceeding the RTOS static objects memory */ - -/* Application uses the following constants to allocate the buffer pool: */ - -#define BDC_HEADER_WITH_PAD 6 /**< BDC Header with padding 4 + 2 */ - -#define SCL_PAYLOAD_MTU (1500) /**< The maximum size, in bytes, of the data part of an Ethernet frame */ - -/****************************************************** -* Type Definitions -******************************************************/ -/** - * Typedef for SCL buffer pointer - */ -typedef void *scl_buffer_t; - -/** - * Typedef for SCL result - */ -typedef uint32_t scl_result_t; - -/****************************************************** -* Structures and Enumerations -******************************************************/ - -/** - * Typedef for SCL boolean flags - */ -typedef enum { - SCL_FALSE = 0, /**< Boolean False */ - SCL_TRUE = 1 /**< Boolean True */ -} scl_bool_t; - -/** - * Typedef for SCL interface roles - */ -typedef enum { - SCL_INVALID_ROLE = 0, /**< Invalid role */ - SCL_STA_ROLE = 1, /**< STA or Client Interface */ - SCL_AP_ROLE = 2, /**< softAP Interface */ - SCL_P2P_ROLE = 3 /**< P2P Interface */ -} scl_interface_role_t; - -/** - * Typedef for SCL IPC receive index - */ -typedef enum { - SCL_RX_DATA = 0, /**< Received buffer */ - SCL_RX_TEST_MSG = 1, /**< Test message */ - SCL_RX_GET_BUFFER = 2, /**< Get the buffer */ - SCL_RX_GET_CONNECTION_STATUS = 3 /**< Get the connection status */ -} scl_ipc_rx_t; - -/** - * Typedef for SCL IPC transmit index - */ -typedef enum { - SCL_TX_TEST_MSG = 1, /**< Test Message */ - SCL_TX_WIFI_INIT = 2, /**< Initialize Wi-Fi */ - SCL_TX_CONFIG_PARAMETERS = 3, /**< Configuration parameters */ - SCL_TX_GET_MAC = 4, /**< Get MAC address */ - SCL_TX_REGISTER_MULTICAST_ADDRESS = 5, /**< Register multicast address */ - SCL_TX_SEND_OUT = 6, /**< Transmit buffer */ - SCL_TX_TRANSCEIVE_READY = 7, /**< Wi-Fi transmit/receive ready */ - SCL_TX_WIFI_ON = 8, /**< Wi-Fi on */ - SCL_TX_WIFI_SET_UP = 9, /**< Wi-Fi setup */ - SCL_TX_WIFI_NW_PARAM = 10, /**< Get network parameters */ - SCL_TX_WIFI_GET_RSSI = 11, /**< Get RSSI */ - SCL_TX_WIFI_GET_BSSID = 12, /**< Get BSSID */ - SCL_TX_CONNECT = 13, /**< Wi-Fi connect */ - SCL_TX_DISCONNECT = 14, /**< Wi-Fi disconnect */ - SCL_TX_CONNECTION_STATUS = 15 /**< Transmit connection status */ -} scl_ipc_tx_t; - - -/** - * Structure for storing a MAC address (Wi-Fi Media Access Control address). - */ -typedef struct { - uint8_t octet[6]; /**< Unique 6-byte MAC address */ -} scl_mac_t; - -#ifdef __cplusplus -} /* extern "C" */ -#endif -#endif /* ifndef INCLUDED_SCL_COMMON_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h deleted file mode 100644 index a9d3e23700..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright 2018-2020 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** @file - * Provides SCL functionality to communicate with Network Processor - */ - -#include "scl_common.h" -#include "cy_device.h" -#include "cy_sysint.h" -#include "cy_ipc_drv.h" -#include "scl_wifi_api.h" -#include "ip4_addr.h" - -#ifndef INCLUDED_SCL_IPC_H -#define INCLUDED_SCL_IPC_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/****************************************************** - * Macros - ******************************************************/ -/** - * Hardware address of IPC_DATA0 register - */ -#define REG_IPC_STRUCT_DATA0(base) (((IPC_STRUCT_V2_Type*)(base))->DATA0) -/** - * Default timeout value (in ms) for SCL operations - */ -#define TIMER_DEFAULT_VALUE (100) -/** - * Default timeout value (in ms) for Wi-Fi on - */ -#define WIFI_ON_TIMEOUT (5000) -/** - * Default timeout value (in seconds) for Wi-Fi connection - */ -#define NW_CONNECT_TIMEOUT (30) -/** - * Default interval (in micro seconds) for polling the Network Processor - */ -#define NW_DELAY_TIME_US (3000000) -/** - * Default parameter length - */ -#define PARAM_LEN (20) - -/****************************************************** -* Variables -******************************************************/ -/** - * Network parameters structure. - */ -typedef struct network_params { - char ip_address[PARAM_LEN]; /**< IP address */ - char netmask[PARAM_LEN]; /**< Netmask */ - char gateway[PARAM_LEN]; /**< Gateway */ - int connection_status; /**< Connection status */ -} network_params_t; - -/****************************************************** -* Function Declarations -******************************************************/ - -/** @addtogroup communication SCL communication API - * APIs for communicating with Network Processor - * @{ - */ - -/** Initializes the SCL thread and necessary artifacts - * - * @return SCL_SUCCESS on successful initialization or SCL_ERROR otherwise - */ -extern scl_result_t scl_init(void); - -/** Sends the SCL data and respective command to Network Processor - * - * @param index Index of the command. - * @param buffer Data to be sent. - * @param timeout The maximum time (in ms) to wait for the Network Processor to release IPC channel. - * - * @return SCL_SUCCESS on successful communication within SCL timeout duration or SCL_ERROR - */ -extern scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout); - -/** Terminates the SCL thread and disables the interrupts - * - * @return SCL_SUCCESS on successful termination of SCL thread and disabling of interrupts or SCL_ERROR on timeout - */ -extern scl_result_t scl_end(void); - -/** Gets the network parameters like IP Address, Netmask, and Gateway from Network Processor - * - * @param nw_param structure pointer of type @a network_params_t - * - * @return SCL_SUCCESS on successful communication or SCL_ERROR - */ -extern scl_result_t scl_get_nw_parameters(network_params_t *nw_param); - -#ifdef __cplusplus -} /* extern "C" */ -#endif -#endif /* ifndef INCLUDED_SCL_IPC_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h deleted file mode 100644 index bda316cb79..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright 2018-2020 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** @file scl_types.h - * Defines common data types used in SCL - * - */ - -#include -#include "cy_result.h" - -#ifndef INCLUDED_SCL_TYPES_H_ -#define INCLUDED_SCL_TYPES_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif -/****************************************************** -* Macros -******************************************************/ -#define SSID_NAME_SIZE (32) /**< SSID Length */ - -#define WEP_ENABLED 0x0001 /**< Flag to enable WEP Security */ -#define TKIP_ENABLED 0x0002 /**< Flag to enable TKIP Encryption */ -#define AES_ENABLED 0x0004 /**< Flag to enable AES Encryption */ -#define SHARED_ENABLED 0x00008000 /**< Flag to enable Shared key Security */ -#define WPA_SECURITY 0x00200000 /**< Flag to enable WPA Security */ -#define WPA2_SECURITY 0x00400000 /**< Flag to enable WPA2 Security */ -#define WPA3_SECURITY 0x01000000 /**< Flag to enable WPA3 PSK Security */ - -#define ENTERPRISE_ENABLED 0x02000000 /**< Flag to enable Enterprise Security */ -#define WPS_ENABLED 0x10000000 /**< Flag to enable WPS Security */ -#define IBSS_ENABLED 0x20000000 /**< Flag to enable IBSS mode */ -#define FBT_ENABLED 0x40000000 /**< Flag to enable FBT */ - -#define NO_POWERSAVE_MODE (0) /**< No Power save mode */ -#define PM1_POWERSAVE_MODE (1) /**< Power save mode on specified interface without regard for throughput reduction */ -#define PM2_POWERSAVE_MODE (2) /**< Power save mode on specified interface with High throughput */ - -/** - * Suppresses unused parameter warning - */ -#define UNUSED_PARAMETER(x) ( (void)(x) ) - -/** - * Suppresses unused variable warning - */ -#define UNUSED_VARIABLE(x) ( (void)(x) ) - -/** - * Suppresses unused variable warning that occurs due to an assert being disabled in release mode - */ -#define REFERENCE_DEBUG_ONLY_VARIABLE(x) ( (void)(x) ) - -/****************************************************** -* Constants -******************************************************/ - -/****************************************************** -* Structures and Enumerations -******************************************************/ - -/** - * Enumeration of Wi-Fi security modes - */ -typedef enum { - SCL_SECURITY_OPEN = 0, /**< Open security */ - SCL_SECURITY_WEP_PSK = WEP_ENABLED, /**< WEP PSK Security with open authentication */ - SCL_SECURITY_WEP_SHARED = (WEP_ENABLED | SHARED_ENABLED), /**< WEP PSK Security with shared authentication */ - SCL_SECURITY_WPA_TKIP_PSK = (WPA_SECURITY | TKIP_ENABLED), /**< WPA PSK Security with TKIP */ - SCL_SECURITY_WPA_AES_PSK = (WPA_SECURITY | AES_ENABLED), /**< WPA PSK Security with AES */ - SCL_SECURITY_WPA_MIXED_PSK = (WPA_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA PSK Security with AES & TKIP */ - SCL_SECURITY_WPA2_AES_PSK = (WPA2_SECURITY | AES_ENABLED), /**< WPA2 PSK Security with AES */ - SCL_SECURITY_WPA2_TKIP_PSK = (WPA2_SECURITY | TKIP_ENABLED), /**< WPA2 PSK Security with TKIP */ - SCL_SECURITY_WPA2_MIXED_PSK = (WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA2 PSK Security with AES & TKIP */ - SCL_SECURITY_WPA2_FBT_PSK = (WPA2_SECURITY | AES_ENABLED | FBT_ENABLED), /**< WPA2 FBT PSK Security with AES & TKIP */ - SCL_SECURITY_WPA3_SAE = (WPA3_SECURITY | AES_ENABLED), /**< WPA3 Security with AES */ - SCL_SECURITY_WPA3_WPA2_PSK = (WPA3_SECURITY | WPA2_SECURITY | AES_ENABLED), /**< WPA3 WPA2 PSK Security with AES */ - - SCL_SECURITY_WPA_TKIP_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | TKIP_ENABLED), /**< WPA Enterprise Security with TKIP */ - SCL_SECURITY_WPA_AES_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | AES_ENABLED), /**< WPA Enterprise Security with AES */ - SCL_SECURITY_WPA_MIXED_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA Enterprise Security with AES & TKIP */ - SCL_SECURITY_WPA2_TKIP_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | TKIP_ENABLED), /**< WPA2 Enterprise Security with TKIP */ - SCL_SECURITY_WPA2_AES_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | AES_ENABLED), /**< WPA2 Enterprise Security with AES */ - SCL_SECURITY_WPA2_MIXED_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA2 Enterprise Security with AES & TKIP */ - SCL_SECURITY_WPA2_FBT_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | AES_ENABLED | FBT_ENABLED), /**< WPA2 Enterprise Security with AES & FBT */ - - SCL_SECURITY_IBSS_OPEN = (IBSS_ENABLED), /**< Open security on IBSS ad-hoc network */ - SCL_SECURITY_WPS_OPEN = (WPS_ENABLED), /**< WPS with open security */ - SCL_SECURITY_WPS_SECURE = (WPS_ENABLED | AES_ENABLED), /**< WPS with AES security */ - - SCL_SECURITY_UNKNOWN = -1, /**< Returned by scan function if security is unknown. Do not pass this to the join function! */ - - SCL_SECURITY_FORCE_32_BIT = 0x7fffffff /**< Exists only to force scl_security_t type to 32 bits */ -} scl_security_t; - -#ifdef __cplusplus -} /* extern "C" */ -#endif -#endif /* ifndef INCLUDED_SCL_TYPES_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h deleted file mode 100644 index f880559a52..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright 2018-2020 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** @file - * Prototypes of functions for controlling the Wi-Fi system - * - * This file provides prototypes for end-user functions, which allow - * actions such as scanning for Wi-Fi networks, joining Wi-Fi - * networks, getting the MAC address, and so on. - * - */ - -#include -#include "scl_common.h" -#ifndef INCLUDED_SCL_WIFI_API_H -#define INCLUDED_SCL_WIFI_API_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/** - * SCL transmit buffer structure - */ -typedef struct scl_tx_buf { - scl_buffer_t buffer; /**< pointer to the buffer */ - uint32_t size; /**< size of the buffer */ -} scl_tx_buf_t; - -/****************************************************** -* Function Declarations -******************************************************/ - -/** @addtogroup wifi SCL Wi-Fi API - * APIs for controlling the Wi-Fi system - * @{ - */ - -/** Turn on the Wi-Fi device - * - * @note This API should be called before using any SCL Wi-Fi API. - * - * @return True if initialization is successful, False otherwise. - */ -extern bool scl_wifi_on(void); - -/** Brings up the Wi-Fi core - * - * @return SCL_SUCCESS or Error code. - */ -extern scl_result_t scl_wifi_set_up(void); - -/** Retrieves the current Media Access Control (MAC) address - * (or Ethernet hardware address) of the 802.11 device - * - * @param mac Pointer to a variable to which the current MAC address will be written. - * - * @return SCL_SUCCESS or Error code. - */ -extern scl_result_t scl_wifi_get_mac_address(scl_mac_t *mac); - -/** Gets the BSSID of the interface - * - * @note This API should be used after the device is connected to a network. - * - * @param bssid Returns the BSSID address (mac address), if associated. - * - * @return SCL_SUCCESS or Error code. - */ -extern scl_result_t scl_wifi_get_bssid(scl_mac_t *bssid); - -/** Registers interest in a multicast address - * - * Once a multicast address has been registered, all packets detected on the - * medium destined for that address are forwarded to the host. - * Otherwise, the packets are ignored. - * - * @param mac Ethernet MAC address. - * - * @return SCL_SUCCESS If the address was registered successfully or Error code. - */ -extern scl_result_t scl_wifi_register_multicast_address(scl_mac_t *mac); - -/** Determines if an interface is ready to transmit/receive ethernet packets. - * - * @note This function must be called after the connection is established; otherwise, it returns Error code. - * - * @return SCL_SUCCESS If the interface is ready to transmit/receive ethernet packets. - * SCL_NOTFOUND If no AP with a matching SSID was found. - * SCL_NOT_AUTHENTICATED If matching AP was found, but it does not let you authenticate. - * @note This can occur if the device is in the blocklist of the AP. - * SCL_NOT_KEYED If the device has authenticated and associated but has not completed the key exchange. - * @note This can occur if the passphrase is incorrect. - * Error code If the interface is not ready to transmit/receive ethernet packets. - */ -extern scl_result_t scl_wifi_is_ready_to_transceive(void); - -/** Sends an ethernet frame to SCL (called by the Network Stack) - * - * This function takes ethernet data from the network stack and transmits over the wireless network. - * This function returns immediately after the packet has been queued for transmission, - * NOT after it has been transmitted. Packet buffers passed to the SCL - * are released inside the SCL once they have been transmitted. - * - * @param buffer Handle of the packet buffer to be sent. - * - * @return SCL_SUCCESS or Error code. - */ -extern scl_result_t scl_network_send_ethernet_data(scl_tx_buf_t buffer); - -/** Retrieves the latest RSSI value - * - * @note This API must be called after the device is connected to a network. - * - * @param rssi Location where the RSSI value will be stored. - * - * @return SCL_SUCCESS If the RSSI was successfully retrieved or Error code. - */ -extern scl_result_t scl_wifi_get_rssi(int32_t *rssi); - -/** Retrieves the RX data packet - * - * @param buffer Pointer to RX buffer. - */ -extern void scl_network_process_ethernet_data(scl_buffer_t buffer); - -/** Notifies network stack about the change in network connection state - * - * @param state_up Connection state. - */ -extern void scl_emac_wifi_link_state_changed(bool state_up); - -#ifdef __cplusplus -} /* extern "C" */ -#endif -#endif /* ifndef INCLUDED_SCL_WIFI_API_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c deleted file mode 100644 index f3d462f558..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c +++ /dev/null @@ -1,293 +0,0 @@ -/* - * Copyright 2018-2020 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** @file - * Provides SCL functionality to communicate with Network Processor - */ -#include "scl_ipc.h" -#include "scl_buffer_api.h" -#include "cyabs_rtos.h" -#include "mbed_wait_api.h" -#include "string.h" -#include "nsapi_types.h" -/****************************************************** - ** Macros - *******************************************************/ -#define SCL_THREAD_STACK_SIZE (1000) -#define SCL_THREAD_PRIORITY (CY_RTOS_PRIORITY_HIGH) -#define SCL_INTR_SRC (cpuss_interrupts_ipc_4_IRQn) -#define SCL_INTR_PRI (1) -#define SCL_RX_CHANNEL (4) -#define SCL_CHANNEL_NOTIFY_INTR ((1 << SCL_RX_CHANNEL) << 16) -#define SCL_NOTIFY (1 << SCL_TX_CHANNEL) -#define SCL_LOCK_ACQUIRE_STATUS (0x80000000) -#define SCL_TX_CHANNEL (3) -#define SCL_RELEASE (0) -#define DELAY_TIME (1000) -#define SEMAPHORE_MAXCOUNT (1) -#define SEMAPHORE_INITCOUNT (0) -/****************************************************** - ** Function Declarations - *******************************************************/ -static void scl_isr(void); -static void scl_config(void); -static void scl_rx_handler(void); -static scl_result_t scl_thread_init(void); -scl_result_t scl_get_nw_parameters(network_params_t *nw_param); -scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout); -scl_result_t scl_end(void); -scl_result_t scl_init(void); -/****************************************************** - * Variables Definitions - *****************************************************/ -/* Structure of SCL thread info - * scl_thread_quit_flag: flag used to determine if thread is to be quit - * scl_inited: flag used to determine if thread is started - * scl_thread: variable for thread handle - * scl_thread_stack_start: pointer to start of thread stack - * scl_thread_stack_size: size of thread stack - * scl_thread_priority: priority of thread - * scl_rx_ready: semaphore for blocking the thread - */ -struct scl_thread_info_t { - volatile scl_bool_t scl_inited; - volatile scl_bool_t scl_thread_quit_flag; - void *scl_thread_stack_start; - cy_thread_t scl_thread; - cy_semaphore_t scl_rx_ready; - uint32_t scl_thread_stack_size; - cy_thread_priority_t scl_thread_priority; -}; -struct scl_thread_info_t g_scl_thread_info; - -/****************************************************** - * Function Definitions - ******************************************************/ - -/** ISR for the IPC receiver channel interrupt - */ -static void scl_isr(void) -{ - IPC_INTR_STRUCT_Type *scl_rx_intr = NULL; - scl_rx_intr = Cy_IPC_Drv_GetIntrBaseAddr(SCL_RX_CHANNEL); - - if (REG_IPC_INTR_STRUCT_INTR_MASKED(scl_rx_intr) & SCL_CHANNEL_NOTIFY_INTR) { - REG_IPC_INTR_STRUCT_INTR(scl_rx_intr) |= SCL_CHANNEL_NOTIFY_INTR; - if (g_scl_thread_info.scl_inited == SCL_TRUE) { - cy_rtos_set_semaphore(&g_scl_thread_info.scl_rx_ready, true); - } - } -} -/** Configures the IPC interrupt channel - */ -static void scl_config(void) -{ - IPC_INTR_STRUCT_Type *scl_rx_intr = NULL; - cy_stc_sysint_t intrCfg = { - .intrSrc = SCL_INTR_SRC, - .intrPriority = SCL_INTR_PRI - }; - - scl_rx_intr = Cy_IPC_Drv_GetIntrBaseAddr(SCL_RX_CHANNEL); - REG_IPC_INTR_STRUCT_INTR_MASK(scl_rx_intr) |= SCL_CHANNEL_NOTIFY_INTR; - Cy_SysInt_Init(&intrCfg, &scl_isr); - NVIC_EnableIRQ(intrCfg.intrSrc); -} -/** Create the SCL thread and initialize the semaphore for handling the events from Network Processor - * - * @return SCL_SUCCESS on successful initialization of thread or SCL_ERROR on failure - */ -static scl_result_t scl_thread_init(void) -{ - cy_rslt_t retval, tmp = 0; - memset(&g_scl_thread_info, 0, sizeof(g_scl_thread_info)); - g_scl_thread_info.scl_thread_stack_start = (uint8_t *) malloc(SCL_THREAD_STACK_SIZE);; - g_scl_thread_info.scl_thread_stack_size = (uint32_t) SCL_THREAD_STACK_SIZE; - g_scl_thread_info.scl_thread_priority = (cy_thread_priority_t) SCL_THREAD_PRIORITY; - - if (g_scl_thread_info.scl_inited != SCL_TRUE) { - retval = cy_rtos_init_semaphore(&g_scl_thread_info.scl_rx_ready, SEMAPHORE_MAXCOUNT, SEMAPHORE_INITCOUNT); - if (retval != SCL_SUCCESS) { - return SCL_ERROR; - } - retval = cy_rtos_create_thread(&g_scl_thread_info.scl_thread, (cy_thread_entry_fn_t) scl_rx_handler, - "SCL_thread", g_scl_thread_info.scl_thread_stack_start, - g_scl_thread_info.scl_thread_stack_size, - g_scl_thread_info.scl_thread_priority, (uint32_t) tmp); - if (retval != SCL_SUCCESS) { - return SCL_ERROR; - } - g_scl_thread_info.scl_inited = SCL_TRUE; - } else { - return SCL_ERROR; - } - return SCL_SUCCESS; -} - -scl_result_t scl_init(void) -{ - scl_result_t retval = SCL_SUCCESS; - uint32_t configuration_parameters = 0; -#ifdef MBED_CONF_TARGET_NP_CLOUD_DISABLE - configuration_parameters = (MBED_CONF_TARGET_NP_CLOUD_DISABLE << 1); -#else - configuration_parameters = (false << 1); -#endif -#ifdef MBED_CONF_TARGET_NP_WIFI_ENABLE - configuration_parameters |= MBED_CONF_TARGET_NP_WIFI_ENABLE; -#else - configuration_parameters |= false; -#endif - //SCL_LOG("configuration_parameters = %lu\n", configuration_parameters); - scl_config(); - if (g_scl_thread_info.scl_inited != SCL_TRUE) { - retval = scl_thread_init(); - if (retval != SCL_SUCCESS) { - SCL_LOG(("Thread init failed\n")); - return SCL_ERROR; - } else { - retval = scl_send_data(SCL_TX_CONFIG_PARAMETERS, (char *) &configuration_parameters, TIMER_DEFAULT_VALUE); - return retval; - } - } - return SCL_SUCCESS; -} - -scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout) -{ - uint32_t acquire_state; - IPC_STRUCT_Type *scl_send = NULL; - uint32_t delay_timeout; - - SCL_LOG(("scl_send_data index = %d\n", index)); - scl_send = Cy_IPC_Drv_GetIpcBaseAddress(SCL_TX_CHANNEL); - CHECK_BUFFER_NULL(buffer); - if (!(REG_IPC_STRUCT_LOCK_STATUS(scl_send) & SCL_LOCK_ACQUIRE_STATUS)) { - acquire_state = REG_IPC_STRUCT_ACQUIRE(scl_send); - if (!(acquire_state & SCL_LOCK_ACQUIRE_STATUS)) { - SCL_LOG(("IPC Channel 3 Acquired Failed\r\n")); - return SCL_ERROR; - } - REG_IPC_STRUCT_DATA0(scl_send) = index; - REG_IPC_STRUCT_DATA1(scl_send) = (uint32_t) buffer; - REG_IPC_STRUCT_NOTIFY(scl_send) = SCL_NOTIFY; - delay_timeout = 0; - while ((REG_IPC_STRUCT_LOCK_STATUS(scl_send) & SCL_LOCK_ACQUIRE_STATUS) && delay_timeout <= timeout) { - wait_us(DELAY_TIME); - delay_timeout++; - } - if (delay_timeout > timeout) { - REG_IPC_STRUCT_RELEASE(scl_send) = SCL_RELEASE; - delay_timeout = 0; - return SCL_ERROR; - } else { - return SCL_SUCCESS; - } - } else { - SCL_LOG(("unable to acquire lock\n")); - return SCL_ERROR; - } -} - -scl_result_t scl_end(void) -{ - scl_result_t retval = SCL_SUCCESS; - if (g_scl_thread_info.scl_inited == SCL_TRUE) { - retval = (scl_result_t) cy_rtos_terminate_thread(&g_scl_thread_info.scl_thread); - if (retval == SCL_SUCCESS) { - retval = (scl_result_t) cy_rtos_join_thread(&g_scl_thread_info.scl_thread); - if (retval == SCL_SUCCESS) { - retval = (scl_result_t) cy_rtos_deinit_semaphore(&g_scl_thread_info.scl_rx_ready); - if (retval == SCL_SUCCESS) { - g_scl_thread_info.scl_inited = SCL_FALSE; - } - } - } - } - return retval; -} - -/** Thread to handle the received buffer - */ -static void scl_rx_handler(void) -{ - char *buffer = NULL; - nsapi_connection_status_t connection_status; - uint32_t index; - IPC_STRUCT_Type *scl_receive = NULL; - scl_buffer_t cp_buffer; - scl_buffer_t scl_buffer; - uint32_t rx_ipc_size; - struct rx_ipc_info { - uint32_t size; - int *buf_alloc; - }*rx_cp = NULL; - - SCL_LOG(("Starting CP Rx thread\r\n")); - scl_receive = Cy_IPC_Drv_GetIpcBaseAddress(SCL_RX_CHANNEL); - - while (SCL_TRUE) { - cy_rtos_get_semaphore(&g_scl_thread_info.scl_rx_ready, CY_RTOS_NEVER_TIMEOUT, SCL_FALSE); - index = (uint32_t)REG_IPC_STRUCT_DATA0(scl_receive); - SCL_LOG(("scl_rx_handler index = %lu\n", index)); - switch (index) { - case SCL_RX_DATA: { - rx_cp = (struct rx_ipc_info *) REG_IPC_STRUCT_DATA1(scl_receive); - scl_buffer = rx_cp->buf_alloc; - REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; - SCL_LOG(("scl_buffer = %p\n", scl_buffer)); - scl_network_process_ethernet_data(scl_buffer); - break; - } - case SCL_RX_TEST_MSG: { - buffer = (char *) REG_IPC_STRUCT_DATA1(scl_receive); - SCL_LOG(("%s\r\n", (char *) buffer)); - REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; - break; - } - case SCL_RX_GET_BUFFER: { - rx_ipc_size = (uint32_t) REG_IPC_STRUCT_DATA1(scl_receive); - scl_host_buffer_get(&cp_buffer, SCL_NETWORK_RX, rx_ipc_size, SCL_FALSE); - REG_IPC_STRUCT_DATA1(scl_receive) = (uint32_t)cp_buffer; - REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; - break; - } - case SCL_RX_GET_CONNECTION_STATUS: { - connection_status = (nsapi_connection_status_t) REG_IPC_STRUCT_DATA1(scl_receive); - if (connection_status == NSAPI_STATUS_GLOBAL_UP) { - scl_emac_wifi_link_state_changed(true); - } else { - scl_emac_wifi_link_state_changed(false); - } - SCL_LOG(("connection status = %d\n", connection_status)); - break; - } - default: { - SCL_LOG(("incorrect IPC from Network Processor\n")); - REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; - break; - } - } - } -} - -scl_result_t scl_get_nw_parameters(network_params_t *nw_param) -{ - scl_result_t status = SCL_ERROR; - status = scl_send_data(SCL_TX_WIFI_NW_PARAM, (char *)nw_param, TIMER_DEFAULT_VALUE); - return status; -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/include/scl_buffer_api.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/include/scl_buffer_api.h deleted file mode 100644 index 7a188ce9d2..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/include/scl_buffer_api.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright 2018-2020 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** @file - * Provides declarations for buffer management functionality - */ -#ifndef _SCL_INTERNAL_BUFFER_API_H_ -#define _SCL_INTERNAL_BUFFER_API_H_ - -#include "scl_types.h" -#include "scl_common.h" -#include -#include "cy_utils.h" -#include "memp.h" -#include "pbuf.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/****************************************************** -* Constants -******************************************************/ -/** - * Size of the SDIO block - */ -#define SDIO_BLOCK_SIZE (64U) - -/****************************************************** -* Macros -******************************************************/ - -/****************************************************** -* Structures and Enumerations -******************************************************/ -/** - * Indicates the transmit/receive direction that the buffer has - * been used for. This is needed if transmit/receive pools are separate. - */ -typedef enum { - SCL_NETWORK_TX = 0, /**< Transmit direction */ - SCL_NETWORK_RX = 1 /**< Receive direction */ -} scl_buffer_dir_t; - -/****************************************************** -* Function Prototypes -******************************************************/ -/** Allocates the SCL buffer. - * - * Attempts to allocate a buffer of the requested size. A buffer - * is either allocated from a static pool of memory or allocated dynamically. - * - * @param buffer A pointer which receives the allocated buffer. - * @param direction Indicates transmit/receive direction that the buffer is - * used for. This may be needed if transmit/receive pools are separate. - * @param size The number of bytes to allocate. - * @param wait Time to wait for a buffer to be available in milli-seconds. - * - * @return SCL_SUCCESS or Error code - * - */ -scl_result_t scl_host_buffer_get(scl_buffer_t *buffer, scl_buffer_dir_t direction, - uint16_t size, uint32_t wait); - -/** Releases the SCL buffer. - * - * This function is used by SCL to indicate that it no longer requires - * the buffer. The buffer can then be released back into a pool for - * reuse or the dynamically allocated memory can be freed. - * - * @param buffer The buffer to be released. - * @param direction Indicates the transmit/receive direction that the buffer has - * been used for. This might be needed if transmit/receive pools are separate. - * - */ -void scl_buffer_release(scl_buffer_t buffer, scl_buffer_dir_t direction); - -/** Retrieves the pointer to the payload of the buffer. - * - * @param buffer The buffer whose payload pointer is to be retrieved. - * - * @return Pointer to the payload. - */ -uint8_t *scl_buffer_get_current_piece_data_pointer(scl_buffer_t buffer); - -/** Retrieves the size of the buffer. - * - * @param buffer The buffer whose size is to be retrieved. - * - * @return The size of the buffer. - */ -uint16_t scl_buffer_get_current_piece_size(scl_buffer_t buffer); - -#ifdef __cplusplus -} /*extern "C" */ -#endif - -#endif /* ifndef _SCL_INTERNAL_BUFFER_API_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_buffer_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_buffer_api.c deleted file mode 100644 index ec4d33a412..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_buffer_api.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright 2018-2020 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "scl_buffer_api.h" - -/****************************************************** -** @cond Constants -*******************************************************/ - -/****************************************************** -** Enumerations -*******************************************************/ - -/****************************************************** -** Function Declarations -*******************************************************/ - -/****************************************************** - * Variables Definitions - *****************************************************/ - -/****************************************************** -* Function Definitions -******************************************************/ - -scl_result_t scl_host_buffer_get(scl_buffer_t *buffer, scl_buffer_dir_t direction, - uint16_t size, uint32_t wait) -{ - UNUSED_PARAMETER(direction); - struct pbuf *p = NULL; - if ((direction == SCL_NETWORK_TX) && (size <= PBUF_POOL_BUFSIZE)) { - p = pbuf_alloc(PBUF_RAW, size, PBUF_POOL); - } else { - p = pbuf_alloc(PBUF_RAW, size + SDIO_BLOCK_SIZE, PBUF_RAM); - if (p != NULL) { - p->len = size; - p->tot_len -= SDIO_BLOCK_SIZE; - } - } - if (p != NULL) { - *buffer = p; - return SCL_SUCCESS; - } else { - return SCL_BUFFER_ALLOC_FAIL; - } - -} - -void scl_buffer_release(scl_buffer_t buffer, scl_buffer_dir_t direction) -{ - UNUSED_PARAMETER(direction); - (void) pbuf_free((struct pbuf *)buffer); -} - -uint8_t *scl_buffer_get_current_piece_data_pointer(scl_buffer_t buffer) -{ - CY_ASSERT(buffer != NULL); - struct pbuf *pbuffer = (struct pbuf *) buffer; - return (uint8_t *) pbuffer->payload; -} - -uint16_t scl_buffer_get_current_piece_size(scl_buffer_t buffer) -{ - CY_ASSERT(buffer != NULL); - struct pbuf *pbuffer = (struct pbuf *) buffer; - return (uint16_t) pbuffer->len; -} - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c deleted file mode 100644 index 92b7e43d8d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright 2018-2020 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "scl_wifi_api.h" -#include "scl_ipc.h" - -/****************************************************** - * Variables Definitions - *****************************************************/ - -typedef struct { - scl_mac_t *mac; - uint32_t retval; -} scl_mac; - -/****************************************************** - * Function Definitions - ******************************************************/ - -scl_result_t scl_wifi_is_ready_to_transceive(void) -{ - scl_result_t result = SCL_SUCCESS; - scl_result_t retval = SCL_SUCCESS; - - result = scl_send_data(SCL_TX_TRANSCEIVE_READY, (char *)&retval, TIMER_DEFAULT_VALUE); - if (result == SCL_ERROR) { - SCL_LOG(("Ready to tranceive error\n")); - return SCL_ERROR; - } else { - return retval; - } -} - -bool scl_wifi_on(void) -{ - bool retval = false; - scl_result_t result = SCL_SUCCESS; - result = scl_send_data(SCL_TX_WIFI_ON, (char *)&retval, WIFI_ON_TIMEOUT); - if (result == SCL_ERROR) { - SCL_LOG(("wifi_on Error\n")); - return false; - } else { - return retval; - } -} - -scl_result_t scl_wifi_set_up(void) -{ - scl_result_t retval = SCL_SUCCESS; - scl_result_t result = SCL_SUCCESS; - result = scl_send_data(SCL_TX_WIFI_SET_UP, (char *)&retval, TIMER_DEFAULT_VALUE); - if (result == SCL_SUCCESS) { - return retval; - } else { - SCL_LOG(("Wifi set up error\n")); - return SCL_ERROR; - } -} - -scl_result_t scl_wifi_get_mac_address(scl_mac_t *mac) -{ - scl_mac scl_mac_data; - scl_result_t scl_retval = SCL_SUCCESS; - scl_mac_data.mac = mac; - scl_mac_data.retval = SCL_SUCCESS; - - if (mac == NULL) { - return SCL_BADARG; - } - scl_retval = scl_send_data(SCL_TX_GET_MAC, (char *)&scl_mac_data, TIMER_DEFAULT_VALUE); - if (scl_retval == SCL_SUCCESS) { - return scl_mac_data.retval; - } else { - SCL_LOG(("Get MAC address error\n")); - return SCL_ERROR; - } -} - -scl_result_t scl_wifi_get_bssid(scl_mac_t *bssid) -{ - struct scl_bssid { - scl_mac_t *bssid; - uint32_t retval; - } scl_bssid_t; - scl_result_t scl_retval = SCL_SUCCESS; - scl_bssid_t.bssid = bssid; - scl_bssid_t.retval = 0; - if (bssid == NULL) { - return SCL_BADARG; - } - scl_retval = scl_send_data(SCL_TX_WIFI_GET_BSSID, (char *)&scl_bssid_t, TIMER_DEFAULT_VALUE); - if (scl_retval == SCL_SUCCESS) { - return scl_bssid_t.retval; - } else { - SCL_LOG(("get bssid error\n")); - return SCL_ERROR; - } -} - -scl_result_t scl_wifi_register_multicast_address(scl_mac_t *mac) -{ - scl_mac scl_mac_t; - scl_mac_t.mac = mac; - scl_mac_t.retval = 0; - scl_result_t scl_retval = SCL_SUCCESS; - if (mac == NULL) { - return SCL_BADARG; - } - scl_retval = scl_send_data(SCL_TX_REGISTER_MULTICAST_ADDRESS, (char *)&scl_mac_t, TIMER_DEFAULT_VALUE); - if (scl_retval != SCL_SUCCESS) { - SCL_LOG(("Register Multicast Address IPC Error")); - return SCL_ERROR; - } - return (scl_mac_t.retval); -} - -scl_result_t scl_network_send_ethernet_data(scl_tx_buf_t scl_buffer) -{ - scl_result_t retval = SCL_SUCCESS; - if (scl_buffer.buffer == NULL) { - return SCL_BADARG; - } - retval = scl_send_data(SCL_TX_SEND_OUT, (char *)&scl_buffer, TIMER_DEFAULT_VALUE); - return retval; -} - -scl_result_t scl_wifi_get_rssi(int32_t *rssi) -{ - struct tx_param { - uint32_t retval; - int32_t *get_rssi; - } tx_param_t; - scl_result_t scl_retval = SCL_SUCCESS; - - if (rssi == NULL) { - return SCL_BADARG; - } - tx_param_t.get_rssi = rssi; - scl_retval = scl_send_data(SCL_TX_WIFI_GET_RSSI, (char *) &tx_param_t, TIMER_DEFAULT_VALUE); - if (scl_retval == SCL_SUCCESS) { - return tx_param_t.retval; - } else { - SCL_LOG(("get rssi error\n")); - return SCL_ERROR; - } -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c deleted file mode 100644 index 54662185ad..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ /dev/null @@ -1,33 +0,0 @@ -/******************************************************************************* -* File Name: cycfg.c -* -* Description: -* Wrapper function to initialize all generated code. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg.h" - -void init_cycfg_all(void) -{ - init_cycfg_routing(); - init_cycfg_pins(); -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h deleted file mode 100644 index 6ceb622e4f..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ /dev/null @@ -1,47 +0,0 @@ -/******************************************************************************* -* File Name: cycfg.h -* -* Description: -* Simple wrapper header containing all generated files. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_H) -#define CYCFG_H - -#if defined(__cplusplus) -extern "C" { -#endif - -#include "cycfg_notices.h" -#include "cycfg_system.h" -#include "cycfg_routing.h" -#include "cycfg_pins.h" - -void init_cycfg_all(void); - - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp deleted file mode 100644 index 8619de1542..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ /dev/null @@ -1,26 +0,0 @@ -/******************************************************************************* -* File Name: cycfg.timestamp -* -* Description: -* Sentinel file for determining if generated source is up to date. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h deleted file mode 100644 index 3587d0e5f0..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ /dev/null @@ -1,32 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_notices.h -* -* Description: -* Contains warnings and errors that occurred while generating code for the -* design. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_NOTICES_H) -#define CYCFG_NOTICES_H - - -#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c deleted file mode 100644 index 41daa132b4..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ /dev/null @@ -1,177 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_pins.c -* -* Description: -* Pin configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_pins.h" - -const cy_stc_gpio_pin_config_t CYBSP_SW1_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = CYBSP_SW1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SW1_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_SW1_PORT_NUM, - .channel_num = CYBSP_SW1_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_LED1_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_LED1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_LED1_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_LED1_PORT_NUM, - .channel_num = CYBSP_LED1_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWO_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_SWO_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWO_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_SWO_PORT_NUM, - .channel_num = CYBSP_SWO_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_PULLUP, - .hsiom = CYBSP_SWDIO_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDIO_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_SWDIO_PORT_NUM, - .channel_num = CYBSP_SWDIO_PIN, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_PULLDOWN, - .hsiom = CYBSP_SWDCK_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SWDCK_obj = - { - .type = CYHAL_RSC_GPIO, - .block_num = CYBSP_SWDCK_PORT_NUM, - .channel_num = CYBSP_SWDCK_PIN, - }; -#endif //defined (CY_USING_HAL) - - -void init_cycfg_pins(void) -{ - Cy_GPIO_Pin_Init(CYBSP_SW1_PORT, CYBSP_SW1_PIN, &CYBSP_SW1_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SW1_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_LED1_PORT, CYBSP_LED1_PIN, &CYBSP_LED1_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_LED1_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWO_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); -#endif //defined (CY_USING_HAL) - - Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h deleted file mode 100644 index 4aacaaa8d3..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ /dev/null @@ -1,190 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_pins.h -* -* Description: -* Pin configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_PINS_H) -#define CYCFG_PINS_H - -#include "cycfg_notices.h" -#include "cy_gpio.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) -#include "cycfg_routing.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYBSP_SW1_ENABLED 1U -#define CYBSP_SW1_PORT GPIO_PRT0 -#define CYBSP_SW1_PORT_NUM 0U -#define CYBSP_SW1_PIN 4U -#define CYBSP_SW1_NUM 4U -#define CYBSP_SW1_DRIVEMODE CY_GPIO_DM_ANALOG -#define CYBSP_SW1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_0_pin_4_HSIOM - #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SW1_HSIOM ioss_0_port_0_pin_4_HSIOM -#define CYBSP_SW1_IRQ ioss_interrupts_gpio_0_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_SW1_HAL_PORT_PIN P0_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SW1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SW1_HAL_DIR CYHAL_GPIO_DIR_INPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SW1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG -#endif //defined (CY_USING_HAL) -#define CYBSP_LED1_ENABLED 1U -#define CYBSP_LED1_PORT GPIO_PRT11 -#define CYBSP_LED1_PORT_NUM 11U -#define CYBSP_LED1_PIN 1U -#define CYBSP_LED1_NUM 1U -#define CYBSP_LED1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_LED1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_11_pin_1_HSIOM - #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_LED1_HSIOM ioss_0_port_11_pin_1_HSIOM -#define CYBSP_LED1_IRQ ioss_interrupts_gpio_11_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_LED1_HAL_PORT_PIN P11_1 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_LED1_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_LED1_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_LED1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_SWO_ENABLED 1U -#define CYBSP_SWO_PORT GPIO_PRT6 -#define CYBSP_SWO_PORT_NUM 6U -#define CYBSP_SWO_PIN 4U -#define CYBSP_SWO_NUM 4U -#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_SWO_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_4_HSIOM - #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM -#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_PORT_PIN P6_4 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG -#endif //defined (CY_USING_HAL) -#define CYBSP_SWDIO_ENABLED 1U -#define CYBSP_SWDIO_PORT GPIO_PRT6 -#define CYBSP_SWDIO_PORT_NUM 6U -#define CYBSP_SWDIO_PIN 6U -#define CYBSP_SWDIO_NUM 6U -#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP -#define CYBSP_SWDIO_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_6_HSIOM - #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM -#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_PORT_PIN P6_6 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP -#endif //defined (CY_USING_HAL) -#define CYBSP_SWDCK_ENABLED 1U -#define CYBSP_SWDCK_PORT GPIO_PRT6 -#define CYBSP_SWDCK_PORT_NUM 6U -#define CYBSP_SWDCK_PIN 7U -#define CYBSP_SWDCK_NUM 7U -#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN -#define CYBSP_SWDCK_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_6_pin_7_HSIOM - #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM -#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn -#if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_PORT_PIN P6_7 -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN -#endif //defined (CY_USING_HAL) - -extern const cy_stc_gpio_pin_config_t CYBSP_SW1_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SW1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_LED1_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_LED1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SWO_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SWDIO_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SWDCK_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_pins(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c deleted file mode 100644 index 92d57a03ff..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ /dev/null @@ -1,266 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_qspi_memslot.c -* -* Description: -* Provides definitions of the SMIF-driver memory configuration. -* This file was automatically generated and should not be modified. -* QSPI Configurator: 2.0.0.1483 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_qspi_memslot.h" - -const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0xEBU, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_QUAD, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0x01U, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_QUAD, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 4U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_QUAD -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x06U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x04U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0xD8U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x60U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x38U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_QUAD, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_QUAD -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x35U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x05U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd = -{ - /* The 8-bit command. 1 x I/O read command. */ - .command = 0x01U, - /* The width of the command transfer. */ - .cmdWidth = CY_SMIF_WIDTH_SINGLE, - /* The width of the address transfer. */ - .addrWidth = CY_SMIF_WIDTH_SINGLE, - /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ - .mode = 0xFFFFFFFFU, - /* The width of the mode command transfer. */ - .modeWidth = CY_SMIF_WIDTH_SINGLE, - /* The number of dummy cycles. A zero value suggests no dummy cycles. */ - .dummyCycles = 0U, - /* The width of the data transfer. */ - .dataWidth = CY_SMIF_WIDTH_SINGLE -}; - -const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 = -{ - /* Specifies the number of address bytes used by the memory slave device. */ - .numOfAddrBytes = 0x03U, - /* The size of the memory. */ - .memSize = 0x04000000U, - /* Specifies the Read command. */ - .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd, - /* Specifies the Write Enable command. */ - .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd, - /* Specifies the Write Disable command. */ - .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd, - /* Specifies the Erase command. */ - .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd, - /* Specifies the sector size of each erase. */ - .eraseSize = 0x00040000U, - /* Specifies the Chip Erase command. */ - .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd, - /* Specifies the Program command. */ - .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd, - /* Specifies the page size for programming. */ - .programSize = 0x00000200U, - /* Specifies the command to read the QE-containing status register. */ - .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd, - /* Specifies the command to read the WIP-containing status register. */ - .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd, - /* Specifies the command to write into the QE-containing status register. */ - .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd, - /* The mask for the status register. */ - .stsRegBusyMask = 0x01U, - /* The mask for the status register. */ - .stsRegQuadEnableMask = 0x02U, - /* The max time for the erase type-1 cycle-time in ms. */ - .eraseTime = 2600U, - /* The max time for the chip-erase cycle-time in ms. */ - .chipEraseTime = 460000U, - /* The max time for the page-program cycle-time in us. */ - .programTime = 1300U -}; - -const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 = -{ - /* Determines the slot number where the memory device is placed. */ - .slaveSelect = CY_SMIF_SLAVE_SELECT_0, - /* Flags. */ - .flags = CY_SMIF_FLAG_WR_EN, - /* The data-line selection options for a slave device. */ - .dataSelect = CY_SMIF_DATA_SEL0, - /* The base address the memory slave is mapped to in the PSoC memory map. - Valid when the memory-mapped mode is enabled. */ - .baseAddress = 0x18000000U, - /* The size allocated in the PSoC memory map, for the memory slave device. - The size is allocated from the base address. Valid when the memory mapped mode is enabled. */ - .memMappedSize = 0x10000U, - /* If this memory device is one of the devices in the dual quad SPI configuration. - Valid when the memory mapped mode is enabled. */ - .dualQuadSlots = 0, - /* The configuration of the device. */ - .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0 -}; - -const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { - &S25FL512S_SlaveSlot_0 -}; - -const cy_stc_smif_block_config_t smifBlockConfig = -{ - /* The number of SMIF memories defined. */ - .memCount = CY_SMIF_DEVICE_NUM, - /* The pointer to the array of memory config structures of size memCount. */ - .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs, - /* The version of the SMIF driver. */ - .majorVersion = CY_SMIF_DRV_VERSION_MAJOR, - /* The version of the SMIF driver. */ - .minorVersion = CY_SMIF_DRV_VERSION_MINOR -}; - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h deleted file mode 100644 index c313452c10..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ /dev/null @@ -1,51 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_qspi_memslot.h -* -* Description: -* Provides declarations of the SMIF-driver memory configuration. -* This file was automatically generated and should not be modified. -* QSPI Configurator: 2.0.0.1483 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#ifndef CYCFG_QSPI_MEMSLOT_H -#define CYCFG_QSPI_MEMSLOT_H -#include "cy_smif_memslot.h" - -#define CY_SMIF_DEVICE_NUM 1 - -extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd; - -extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0; - -extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0; -extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; - -extern const cy_stc_smif_block_config_t smifBlockConfig; - - -#endif /*CY_SMIF_MEMCONFIG_H*/ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c deleted file mode 100644 index a8de1e3d5f..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ /dev/null @@ -1,31 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_routing.c -* -* Description: -* Establishes all necessary connections between hardware elements. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_routing.h" - -void init_cycfg_routing(void) -{ -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h deleted file mode 100644 index 645fc6902d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ /dev/null @@ -1,46 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_routing.h -* -* Description: -* Establishes all necessary connections between hardware elements. -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_ROUTING_H) -#define CYCFG_ROUTING_H - -#if defined(__cplusplus) -extern "C" { -#endif - -#include "cycfg_notices.h" -void init_cycfg_routing(void); -#define init_cycfg_connectivity() init_cycfg_routing() -#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO -#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS -#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c deleted file mode 100644 index d06a4b5f86..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ /dev/null @@ -1,28 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_system.c -* -* Description: -* System configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_system.h" - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h deleted file mode 100644 index 106e61a459..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ /dev/null @@ -1,43 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_system.h -* -* Description: -* System configuration -* This file was automatically generated and should not be modified. -* Device Configurator: 2.0.0.1483 -* Device Support Library (../../../psoc6pdl): 1.3.1.1499 -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_SYSTEM_H) -#define CYCFG_SYSTEM_H - -#include "cycfg_notices.h" -#if defined(__cplusplus) -extern "C" { -#endif - -#define cpuss_0_dap_0_ENABLED 1U - - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_SYSTEM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg deleted file mode 100644 index a561643dcf..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg +++ /dev/null @@ -1,2 +0,0 @@ -set SMIF_BANKS { -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list deleted file mode 100644 index edb189b2e2..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ /dev/null @@ -1,99 +0,0 @@ -[Device=CY8C624AFNI-D43] - -[Blocks] -# WIFI -# CYBSP_WIFI_SDIO -sdhc[0] -# CYBSP_WIFI_SDIO_D0 -ioss[0].port[2].pin[0] -# CYBSP_WIFI_SDIO_D1 -ioss[0].port[2].pin[1] -# CYBSP_WIFI_SDIO_D2 -ioss[0].port[2].pin[2] -# CYBSP_WIFI_SDIO_D3 -ioss[0].port[2].pin[3] -# CYBSP_WIFI_SDIO_CMD -ioss[0].port[2].pin[4] -# CYBSP_WIFI_SDIO_CLK -ioss[0].port[2].pin[5] -# CYBSP_WIFI_WL_REG_ON -ioss[0].port[2].pin[6] -# CYBSP_WIFI_DEVICE_WAKE -ioss[0].port[2].pin[7] -# CYBSP_WIFI_HOST_WAKE -ioss[0].port[1].pin[4] - -# BT UART -# CYBSP_BT_UART -scb[12] -# CYBSP_BT_POWER -ioss[0].port[12].pin[0] -# CYBSP_BT_DEVICE_WAKE -ioss[0].port[12].pin[2] -# CYBSP_BT_HOST_WAKE -ioss[0].port[12].pin[3] -# CYBSP_BT_UART_RX -ioss[0].port[13].pin[4] -# CYBSP_BT_UART_TX -ioss[0].port[13].pin[5] -# CYBSP_BT_UART_RTS -ioss[0].port[13].pin[6] -# CYBSP_BT_UART_CTS -ioss[0].port[13].pin[7] -# CYBSP_BT_UART_CLK_DIV -peri[0].div_16[1] - -# UART -# CYBSP_DEBUG_UART -scb[10] -# CYBSP_DEBUG_UART_RX -ioss[0].port[5].pin[4] -# CYBSP_DEBUG_UART_TX -ioss[0].port[5].pin[5] -# CYBSP_DEBUG_UART_CLK_DIV -peri[0].div_16[0] - -# POWER -srss[0].power[0] - -# SYSTEM CLOCK -srss[0].clock[0] -# CLK_ALT_SYS_TICK -srss[0].clock[0].altsystickclk[0] -# CLK_BAK -srss[0].clock[0].bakclk[0] -# CLK_FAST -srss[0].clock[0].fastclk[0] -# CLK_HF0 -srss[0].clock[0].hfclk[0] -# CLK_HF2 -srss[0].clock[0].hfclk[2] -# CLK_HF4 -srss[0].clock[0].hfclk[4] -# CLK_ILO -srss[0].clock[0].ilo[0] -# CLK_IMO -srss[0].clock[0].imo[0] -# CLK_LF -srss[0].clock[0].lfclk[0] -# PATH_MUX0 -srss[0].clock[0].pathmux[0] -# PATH_MUX1 -srss[0].clock[0].pathmux[1] -# CLK_PERI -srss[0].clock[0].periclk[0] -# CLK_PLL0 -srss[0].clock[0].pll[0] -# CLK_SLOW -srss[0].clock[0].slowclk[0] -# CLK_TIMER -srss[0].clock[0].timerclk[0] - -# RTC -srss[0].rtc[0] - -# CM0(NP) I2C -# CYBSP_I2C_SCL -ioss[0].port[8].pin[0] -# CYBSP_I2C_SDA -ioss[0].port[8].pin[1] diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense deleted file mode 100644 index a31d15e293..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ /dev/null @@ -1,71 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi deleted file mode 100644 index f0610e1067..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi +++ /dev/null @@ -1,63 +0,0 @@ - - - - PSoC 6.xml - - - 0 - S25FL512S - false - None - 0x18000000 - 0x10000 - 0x1800FFFF - true - false - QUAD_SPI_DATA_0_3 - S25FL512S - true - - - 1 - Not used - false - None - 0x18010000 - 0x10000 - 0x1801FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - false - - - 2 - Not used - false - None - 0x18020000 - 0x10000 - 0x1802FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - false - - - 3 - Not used - false - None - 0x18030000 - 0x10000 - 0x1803FFFF - false - false - SPI_MOSI_MISO_DATA_0_1 - default_memory.xml - false - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus deleted file mode 100644 index 120837b1b1..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ /dev/null @@ -1,106 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c deleted file mode 100644 index 57eb8a28a6..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c +++ /dev/null @@ -1,427 +0,0 @@ -/* - * mbed Microcontroller Library - * Copyright (c) 2017-2018 Future Electronics - * Copyright (c) 2019 Cypress Semiconductor Corporation - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralNames.h" -#include "PeripheralPins.h" -#include "pinmap.h" - -#if DEVICE_SERIAL -//*** SERIAL *** -const PinMap PinMap_UART_RX[] = { - {P0_2, UART_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)}, - {P1_0, UART_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)}, - {P2_0, UART_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_UART_RX)}, - {P2_4, UART_9, CYHAL_PIN_IN_FUNCTION(P2_4_SCB9_UART_RX)}, - {P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)}, - {P5_4, UART_10, CYHAL_PIN_IN_FUNCTION(P5_4_SCB10_UART_RX)}, - {P6_0, UART_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)}, - {P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)}, - {P7_0, UART_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)}, - {P8_0, UART_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)}, - {P8_4, UART_11, CYHAL_PIN_IN_FUNCTION(P8_4_SCB11_UART_RX)}, - {P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)}, - {P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)}, - {P11_0, UART_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)}, - {P12_0, UART_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)}, - {P13_0, UART_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)}, - {P13_4, UART_12, CYHAL_PIN_IN_FUNCTION(P13_4_SCB12_UART_RX)}, - {NC, NC, 0} -}; -const PinMap PinMap_UART_TX[] = { - {P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)}, - {P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)}, - {P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_UART_TX)}, - {P2_5, UART_9, CYHAL_PIN_OUT_FUNCTION(P2_5_SCB9_UART_TX)}, - {P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)}, - {P5_5, UART_10, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB10_UART_TX)}, - {P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)}, - {P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)}, - {P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)}, - {P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)}, - {P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)}, - {P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)}, - {P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)}, - {P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)}, - {P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)}, - {P13_5, UART_12, CYHAL_PIN_OUT_FUNCTION(P13_5_SCB12_UART_TX)}, - {NC, NC, 0} -}; -const PinMap PinMap_UART_RTS[] = { - {P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)}, - {P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_UART_RTS)}, - {P2_6, UART_9, CYHAL_PIN_OUT_FUNCTION(P2_6_SCB9_UART_RTS)}, - {P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)}, - {P5_6, UART_10, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB10_UART_RTS)}, - {P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)}, - {P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)}, - {P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)}, - {P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)}, - {P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)}, - {P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)}, - {P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)}, - {P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)}, - {P13_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_UART_RTS)}, - {P13_6, UART_12, CYHAL_PIN_OUT_FUNCTION(P13_6_SCB12_UART_RTS)}, - {NC, NC, 0} -}; -const PinMap PinMap_UART_CTS[] = { - {P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)}, - {P2_3, UART_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_UART_CTS)}, - {P2_7, UART_9, CYHAL_PIN_IN_FUNCTION(P2_7_SCB9_UART_CTS)}, - {P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)}, - {P5_7, UART_10, CYHAL_PIN_IN_FUNCTION(P5_7_SCB10_UART_CTS)}, - {P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)}, - {P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)}, - {P7_3, UART_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)}, - {P8_3, UART_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)}, - {P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)}, - {P10_3, UART_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)}, - {P11_3, UART_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)}, - {P12_3, UART_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)}, - {P13_3, UART_6, CYHAL_PIN_IN_FUNCTION(P13_3_SCB6_UART_CTS)}, - {P13_7, UART_12, CYHAL_PIN_IN_FUNCTION(P13_7_SCB12_UART_CTS)}, - {NC, NC, 0} -}; -#endif // DEVICE_SERIAL - - -#if DEVICE_I2C -//*** I2C *** -const PinMap PinMap_I2C_SCL[] = { - {P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)}, - {P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)}, - {P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_0_SCB1_I2C_SCL)}, - {P2_4, I2C_9, CYHAL_PIN_OD_FUNCTION(P2_4_SCB9_I2C_SCL)}, - {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)}, - {P5_4, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_4_SCB10_I2C_SCL)}, - {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)}, - {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)}, - {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)}, - {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)}, - {P8_4, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_4_SCB11_I2C_SCL)}, - {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)}, - {P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)}, - {P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)}, - {P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)}, - {P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)}, - {P13_4, I2C_12, CYHAL_PIN_OD_FUNCTION(P13_4_SCB12_I2C_SCL)}, - {NC, NC, 0} -}; -const PinMap PinMap_I2C_SDA[] = { - {P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)}, - {P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)}, - {P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_1_SCB1_I2C_SDA)}, - {P2_5, I2C_9, CYHAL_PIN_OD_FUNCTION(P2_5_SCB9_I2C_SDA)}, - {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)}, - {P5_5, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_5_SCB10_I2C_SDA)}, - {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)}, - {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)}, - {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)}, - {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)}, - {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)}, - {P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)}, - {P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)}, - {P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)}, - {P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)}, - {P13_5, I2C_12, CYHAL_PIN_OD_FUNCTION(P13_5_SCB12_I2C_SDA)}, - {NC, NC, 0} -}; -#endif // DEVICE_I2C - -#if DEVICE_SPI -//*** SPI *** -const PinMap PinMap_SPI_MOSI[] = { - {P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)}, - {P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)}, - {P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_0_SCB1_SPI_MOSI)}, - {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)}, - {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)}, - {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)}, - {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)}, - {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)}, - {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)}, - {P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)}, - {P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)}, - {P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)}, - {P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)}, - {NC, NC, 0} -}; -const PinMap PinMap_SPI_MISO[] = { - {P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)}, - {P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)}, - {P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P2_1_SCB1_SPI_MISO)}, - {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)}, - {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)}, - {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)}, - {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)}, - {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)}, - {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)}, - {P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)}, - {P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)}, - {P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)}, - {P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)}, - {NC, NC, 0} -}; -const PinMap PinMap_SPI_SCLK[] = { - {P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)}, - {P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_SPI_CLK)}, - {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)}, - {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)}, - {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)}, - {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)}, - {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)}, - {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)}, - {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)}, - {P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)}, - {P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)}, - {P13_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_SPI_CLK)}, - {NC, NC, 0} -}; -const PinMap PinMap_SPI_SSEL[] = { - {P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)}, - {P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_3_SCB1_SPI_SELECT0)}, - {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)}, - {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)}, - {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)}, - {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)}, - {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)}, - {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)}, - {P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)}, - {P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)}, - {P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)}, - {P13_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_3_SCB6_SPI_SELECT0)}, - {NC, NC, 0} -}; -#endif // DEVICE_SPI - -#if DEVICE_PWMOUT -//*** PWM *** -const PinMap PinMap_PWM_OUT[] = { - // 16-bit PWM outputs - {P0_0, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)}, - {P0_2, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)}, - {P0_4, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)}, - {P1_0, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)}, - {P1_4, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)}, - {P2_0, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM1_LINE15)}, - {P2_2, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM1_LINE16)}, - {P2_4, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM1_LINE17)}, - {P2_6, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM1_LINE18)}, - {P5_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)}, - {P5_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)}, - {P5_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)}, - {P5_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)}, - {P6_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)}, - {P6_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)}, - {P6_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)}, - {P6_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)}, - {P7_0, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)}, - {P7_2, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)}, - {P8_0, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)}, - {P8_2, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)}, - {P8_4, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)}, - {P9_0, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)}, - {P9_2, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)}, - {P9_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)}, - {P10_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)}, - {P10_2, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)}, - {P10_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)}, - {P10_6, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)}, - {P11_0, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)}, - {P11_2, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)}, - {P11_4, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)}, - {P12_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)}, - {P12_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)}, - {P12_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)}, - {P12_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)}, - {P13_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)}, - {P13_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9)}, - {P13_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10)}, - {P13_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)}, - // 16-bit PWM inverted outputs - {P0_1, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)}, - {P0_3, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)}, - {P0_5, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)}, - {P1_1, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)}, - {P1_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)}, - {P2_1, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM1_LINE_COMPL15)}, - {P2_3, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM1_LINE_COMPL16)}, - {P2_5, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM1_LINE_COMPL17)}, - {P2_7, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM1_LINE_COMPL18)}, - {P5_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)}, - {P5_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)}, - {P5_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)}, - {P5_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)}, - {P6_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)}, - {P6_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)}, - {P6_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)}, - {P6_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)}, - {P7_1, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)}, - {P7_3, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)}, - {P7_7, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)}, - {P8_1, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)}, - {P8_3, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)}, - {P9_1, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)}, - {P9_3, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)}, - {P9_7, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)}, - {P10_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)}, - {P10_3, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)}, - {P10_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)}, - {P10_7, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)}, - {P11_1, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)}, - {P11_3, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)}, - {P11_5, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)}, - {P12_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)}, - {P12_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)}, - {P12_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)}, - {P12_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)}, - {P13_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)}, - {P13_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9)}, - {P13_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10)}, - {P13_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)}, - // 32-bit PWM outputs - {P0_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, - {P0_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)}, - {P0_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)}, - {P1_0, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)}, - {P1_4, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)}, - {P2_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM0_LINE6)}, - {P2_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM0_LINE7)}, - {P2_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM0_LINE0)}, - {P2_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM0_LINE1)}, - {P5_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)}, - {P5_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)}, - {P5_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)}, - {P5_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)}, - {P6_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)}, - {P6_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)}, - {P6_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)}, - {P6_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)}, - {P7_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)}, - {P7_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)}, - {P8_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)}, - {P8_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)}, - {P8_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)}, - {P9_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)}, - {P9_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)}, - {P9_4, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)}, - {P10_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)}, - {P10_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)}, - {P10_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)}, - {P10_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)}, - {P11_0, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)}, - {P11_2, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)}, - {P11_4, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)}, - {P12_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)}, - {P12_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)}, - {P12_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)}, - {P12_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)}, - {P13_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)}, - {P13_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1)}, - {P13_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2)}, - {P13_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)}, - // 32-bit PWM inverted outputs - {P0_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)}, - {P0_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)}, - {P0_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)}, - {P1_1, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)}, - {P1_5, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)}, - {P2_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM0_LINE_COMPL6)}, - {P2_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM0_LINE_COMPL7)}, - {P2_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM0_LINE_COMPL0)}, - {P2_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM0_LINE_COMPL1)}, - {P5_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)}, - {P5_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)}, - {P5_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)}, - {P5_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)}, - {P6_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)}, - {P6_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)}, - {P6_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)}, - {P6_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)}, - {P7_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)}, - {P7_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)}, - {P7_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)}, - {P8_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)}, - {P8_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)}, - {P9_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)}, - {P9_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)}, - {P9_7, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)}, - {P10_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)}, - {P10_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)}, - {P10_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)}, - {P10_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)}, - {P11_1, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)}, - {P11_3, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)}, - {P11_5, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)}, - {P12_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)}, - {P12_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)}, - {P12_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)}, - {P12_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)}, - {P13_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)}, - {P13_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1)}, - {P13_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2)}, - {P13_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)}, - {NC, NC, 0} -}; -#endif // DEVICE_PWMOUT - -#if DEVICE_ANALOGIN -const PinMap PinMap_ADC[] = { - {P9_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_0 pin through the AMUXA bus - {P9_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_1 pin through the AMUXA bus - {P9_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_2 pin through the AMUXA bus - {P9_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_4 pin through the AMUXA bus - {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_0 pin - {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_1 pin - {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_2 pin - {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_3 pin - {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_4 pin - {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_5 pin - {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_6 pin - {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_7 pin - {NC, NC, 0} -}; -#endif // DEVICE_ANALOGIN - -#if DEVICE_QSPI -const PinMap PinMap_QSPI_SCLK[] = { - {P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_SSEL[] = { - {P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_DATA0[] = { - {P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_DATA1[] = { - {P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_DATA2[] = { - {P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)}, - {NC, NC, 0}, -}; -const PinMap PinMap_QSPI_DATA3[] = { - {P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)}, - {NC, NC, 0}, -}; -#endif // DEVICE_QSPI diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c deleted file mode 100644 index a935ed999b..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c +++ /dev/null @@ -1,115 +0,0 @@ -/***************************************************************************//** -* \file cybsp.c -* -* Description: -* Provides initialization code for starting up the hardware contained on the -* Cypress board. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "cy_syspm.h" -#include "cy_sysclk.h" -#include "cybsp.h" -#if defined(CY_USING_HAL) -#include "cyhal_hwmgr.h" -#endif - -#if !defined (CY_CFG_PWR_SYS_IDLE_MODE) -#include "mbed_power_mgmt.h" -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -/* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon -* exit the deep sleep mode. -* Doing so minimizes the time spent on low power mode entry and exit. -*/ -#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER - #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) -#endif - -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) -static cyhal_sdio_t sdio_obj; - -cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) -{ - return &sdio_obj; -} -#endif - -/** - * Registers a power management callback that prepares the clock system - * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. - * NOTE: This is called automatically as part of \ref cybsp_init - */ -static cy_rslt_t cybsp_register_sysclk_pm_callback(void) -{ - cy_rslt_t result = CY_RSLT_SUCCESS; - static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; - static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { - .callback = &Cy_SysClk_DeepSleepCallback, - .type = CY_SYSPM_DEEPSLEEP, - .callbackParams = &cybsp_sysclk_pm_callback_param, - .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER - }; - - if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) - { - result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; - } - return result; -} - -cy_rslt_t cybsp_init(void) -{ - /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ -#if defined(CY_USING_HAL) - cy_rslt_t result = cyhal_hwmgr_init(); -#else - cy_rslt_t result = CY_RSLT_SUCCESS; -#endif - -#if defined(COMPONENT_BSP_DESIGN_MODUS) - init_cycfg_all(); -#endif - - if (CY_RSLT_SUCCESS == result) - { - result = cybsp_register_sysclk_pm_callback(); - } - -#if !defined(CY_CFG_PWR_SYS_IDLE_MODE) - /* Disable deep-sleep. */ - sleep_manager_lock_deep_sleep(); -#endif - - /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by - * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list - * (cyreservedresources.list) to make sure no resources are reserved by both. - */ - return result; -} - -#if defined(__cplusplus) -} -#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h deleted file mode 100644 index 7d15280e71..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h +++ /dev/null @@ -1,76 +0,0 @@ -/***************************************************************************//** -* \file cybsp.h -* -* \brief -* Basic API for setting up boards containing a Cypress MCU. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#pragma once - -#include "cy_result.h" -#include "cybsp_types.h" -#if defined(COMPONENT_BSP_DESIGN_MODUS) -#include "cycfg.h" -#endif -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) -#include "cyhal_sdio.h" -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_bsp_macros Macros -* \{ -*/ - -/** Failed to configure sysclk power management callback */ -#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) - -/** \} group_bsp_macros */ - -/** -* \addtogroup group_bsp_functions Functions -* \{ -*/ - -/** - * \brief Initialize all hardware on the board - * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is - * a problem initializing any hardware it returns an error code specific - * to the hardware module that had a problem. - */ -cy_rslt_t cybsp_init(void); - -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) -/** - * \brief Get the initialized sdio object used for communicating with the WiFi Chip. - * \note This function should only be called after cybsp_init(); - * \returns The initialized sdio object. - */ -cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); -#endif /* defined(CYBSP_WIFI_CAPABLE) */ - -/** \} group_bsp_functions */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h deleted file mode 100644 index 64ef452d65..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h +++ /dev/null @@ -1,194 +0,0 @@ -/***************************************************************************//** -* \file CYSBSYSKIT_01/cybsp_types.h -* -* Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CYSBSYSKIT_01 kit. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#pragma once - -#if defined(CY_USING_HAL) -#include "cyhal_pin_package.h" -#endif - -#if defined(__cplusplus) -extern "C" { -#endif - -#ifndef CY_CFG_SYSCLK_CLKLF_FREQ_HZ -#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ (32000U) -#endif - -/** -* \addtogroup group_bsp_settings BSP Settings -* \{ -* -*
Peripheral Default HAL Settings:
-* | Resource | Parameter | Value | Remarks | -* | :------: | :-------: | :---: | :------ | -* | ADC | VREF | 1.2 V | | -* | ^ | Measurement type | Single Ended | | -* | ^ | Input voltage range | 0 to 2.4 V (0 to 2*VREF) | | -* | ^ | Output range | 0x000 to 0x7FF | | -* | DAC | Reference source | VDDA | | -* | ^ | Input range | 0x000 to 0xFFF | | -* | ^ | Output range | 0 to VDDA | | -* | ^ | Output type | Unbuffered output | | -* | I2C | Role | Master | Configurable to slave mode through HAL function | -* | ^ | Data rate | 100 kbps | Configurable through HAL function | -* | ^ | Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required | -* | LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter. 1 count = 1/32768 second or 32768 counts = 1 second. ||| -* | SPI | Data rate | 100 kpbs | Configurable through HAL function | -* | ^ | Slave select polarity | Active low | | -* | UART | Flow control | No flow control | Configurable through HAL function | -* | ^ | Data format | 8N1 | Configurable through HAL function | -* | ^ | Baud rate | 115200 | Configurable through HAL function | -*/ -/** \} group_bsp_settings */ - -/** -* \addtogroup group_bsp_pin_state Pin States -* \{ -*/ - -/** Pin state for the LED on. */ -#define CYBSP_LED_STATE_ON (0U) -/** Pin state for the LED off. */ -#define CYBSP_LED_STATE_OFF (1U) - -/** Pin state for when a button is pressed. */ -#define CYBSP_BTN_PRESSED (0U) -/** Pin state for when a button is released. */ -#define CYBSP_BTN_OFF (1U) - -/** \} group_bsp_pin_state */ - -#if defined(CY_USING_HAL) - -/** -* \addtogroup group_bsp_pins Pin Mappings -* \{ -*/ - -/** -* \addtogroup group_bsp_pins_led LED Pins -* \{ -*/ - -/** BSP user LED1 reference designator to pin mapping */ -#define CYBSP_USER_LED1 (P11_1) - -/** \} group_bsp_pins_led */ - -/** -* \addtogroup group_bsp_pins_btn Button Pins -* \{ -*/ - -/** BSP user button reference designator to pin mapping */ -#define CYBSP_USER_BTN (P0_4) - -/** \} group_bsp_pins_btn */ - -/** -* \addtogroup group_bsp_pins_comm Communication Pins -* \{ -*/ - -/** Pin: WIFI SDIO D0 */ -#define CYBSP_WIFI_SDIO_D0 (P2_0) -/** Pin: WIFI SDIO D1 */ -#define CYBSP_WIFI_SDIO_D1 (P2_1) -/** Pin: WIFI SDIO D2 */ -#define CYBSP_WIFI_SDIO_D2 (P2_2) -/** Pin: WIFI SDIO D3 */ -#define CYBSP_WIFI_SDIO_D3 (P2_3) -/** Pin: WIFI SDIO CMD */ -#define CYBSP_WIFI_SDIO_CMD (P2_4) -/** Pin: WIFI SDIO CLK */ -#define CYBSP_WIFI_SDIO_CLK (P2_5) -/** Pin: WIFI ON */ -#define CYBSP_WIFI_WL_REG_ON (P2_6) -/** Pin: WIFI Host Wakeup */ -#define CYBSP_WIFI_HOST_WAKE (P1_4) - -/** Host-wake GPIO drive mode */ -#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) -/** Host-wake IRQ event */ -#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) -/** Pin: BT UART RX */ -#define CYBSP_BT_UART_RX (P13_4) -/** Pin: BT UART TX */ -#define CYBSP_BT_UART_TX (P13_5) -/** Pin: BT UART RTS */ -#define CYBSP_BT_UART_RTS (P13_6) -/** Pin: BT UART CTS */ -#define CYBSP_BT_UART_CTS (P13_7) - -/** Pin: BT Power */ -#define CYBSP_BT_POWER (P12_0) -/** Pin: BT Host Wakeup */ -#define CYBSP_BT_HOST_WAKE (P12_3) -/** Pin: BT Device Wakeup */ -#define CYBSP_BT_DEVICE_WAKE (P12_2) - -/** Pin: UART RX */ -#define CYBSP_DEBUG_UART_RX (P5_4) -/** Pin: UART TX */ -#define CYBSP_DEBUG_UART_TX (P5_5) - -/** Pin: SWO */ -#define CYBSP_SWO (P6_4) -/** Pin: SWDIO */ -#define CYBSP_SWDIO (P6_6) -/** Pin: SWDCK */ -#define CYBSP_SWDCK (P6_7) - -/** Pin: QUAD SPI SS */ -#define CYBSP_QSPI_SS (P11_2) -/** Pin: QUAD SPI D3 */ -#define CYBSP_QSPI_D3 (P11_3) -/** Pin: QUAD SPI D2 */ -#define CYBSP_QSPI_D2 (P11_4) -/** Pin: QUAD SPI D1 */ -#define CYBSP_QSPI_D1 (P11_5) -/** Pin: QUAD SPI D0 */ -#define CYBSP_QSPI_D0 (P11_6) -/** Pin: QUAD SPI SCK */ -#define CYBSP_QSPI_SCK (P11_7) - -/** Pin: I2C SCL */ -#define CYBSP_I2C_SCL (P6_0) -/** Pin: I2C SDA */ -#define CYBSP_I2C_SDA (P6_1) - -/** \} group_bsp_pins_comm */ - -/** \} group_bsp_pins */ - - - - -#endif /* defined(CY_USING_HAL) */ - -#if defined(__cplusplus) -} -#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct deleted file mode 100644 index ea1cfaefe9..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct +++ /dev/null @@ -1,298 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -; The first line specifies a preprocessor command that the linker invokes -; to pass a scatter file through a C preprocessor. - -;******************************************************************************* -;* \file cy8c6xxa_cm4_dual.sct -;* \version 2.60 -;* -;* Linker file for the ARMCC. -;* -;* The main purpose of the linker script is to describe how the sections in the -;* input files should be mapped into the output file, and to control the memory -;* layout of the output file. -;* -;* \note The entry point location is fixed and starts at 0x10000000. The valid -;* application image should be placed there. -;* -;* \note The linker files included with the PDL template projects must be -;* generic and handle all common use cases. Your project may not use every -;* section defined in the linker files. In that case you may see the warnings -;* during the build process: L6314W (no section matches pattern) and/or L6329W -;* (pattern only matches removed unused sections). In your project, you can -;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -;* the linker, simply comment out or remove the relevant code in the linker -;* file. -;* -;******************************************************************************* -;* \copyright -;* Copyright 2016-2019 Cypress Semiconductor Corporation -;* SPDX-License-Identifier: Apache-2.0 -;* -;* Licensed under the Apache License, Version 2.0 (the "License"); -;* you may not use this file except in compliance with the License. -;* You may obtain a copy of the License at -;* -;* http://www.apache.org/licenses/LICENSE-2.0 -;* -;* Unless required by applicable law or agreed to in writing, software -;* distributed under the License is distributed on an "AS IS" BASIS, -;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;* See the License for the specific language governing permissions and -;* limitations under the License. -;******************************************************************************/ - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10180000 -#endif - -;* MBED_APP_START is being used by the bootloader build script and -;* will be calculate by the system. In case if MBED_APP_START address is -;* customized by the bootloader config, the application image should not -;* include CM0p prebuilt image. -;* - -#if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -;* MBED_APP_SIZE is being used by the bootloader build script and -;* will be calculate by the system. -;* -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE (MBED_ROM_SIZE) -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08080000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x7F800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; Size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_BOOT_STACK_SIZE - -; The defines below describe the location and size of blocks of memory in the target. -; Use these defines to specify the memory regions available for allocation. - -; The following defines control RAM and flash memory allocation for the CM4 core. -; You can change the memory allocation by editing RAM and Flash defines. -; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. -; Using this memory region for other purposes will lead to unexpected behavior. -; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', -; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. -; RAM -#define RAM_START MBED_RAM_START -#define RAM_SIZE MBED_RAM_SIZE -; Flash -#define FLASH_START MBED_APP_START -#define FLASH_SIZE MBED_APP_SIZE - -; The following defines describe a 32K flash region used for EEPROM emulation. -; This region can also be used as the general purpose flash. -; You can assign sections to this memory region for only one of the cores. -; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. -; Therefore, repurposing this memory region will prevent such middleware from operation. -#define EM_EEPROM_START 0x14000000 -#define EM_EEPROM_SIZE 0x8000 - -; The following defines describe device specific memory regions and must not be changed. -; Supervisory flash: User data -#define SFLASH_USER_DATA_START 0x16000800 -#define SFLASH_USER_DATA_SIZE 0x00000800 - -; Supervisory flash: Normal Access Restrictions (NAR) -#define SFLASH_NAR_START 0x16001A00 -#define SFLASH_NAR_SIZE 0x00000200 - -; Supervisory flash: Public Key -#define SFLASH_PUBLIC_KEY_START 0x16005A00 -#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 - -; Supervisory flash: Table of Content # 2 -#define SFLASH_TOC_2_START 0x16007C00 -#define SFLASH_TOC_2_SIZE 0x00000200 - -; Supervisory flash: Table of Content # 2 Copy -#define SFLASH_RTOC_2_START 0x16007E00 -#define SFLASH_RTOC_2_SIZE 0x00000200 - -; External memory -#define XIP_START 0x18000000 -#define XIP_SIZE 0x08000000 - -; eFuse -#define EFUSE_START 0x90700000 -#define EFUSE_SIZE 0x100000 - -; Cortex-M4 application flash area -LR_IROM1 FLASH_START FLASH_SIZE -{ - ER_FLASH_VECTORS +0 - { - * (RESET, +FIRST) - } - - ER_FLASH_CODE +0 FIXED - { - * (InRoot$$Sections) - * (+RO) - } - - ER_RAM_VECTORS RAM_START UNINIT - { - * (RESET_RAM, +FIRST) - } - - RW_RAM_DATA +0 - { - * (.cy_ramfunc) - * (+RW, +ZI) - } - - ; Place variables in the section that should not be initialized during the - ; device startup. - RW_IRAM1 +0 UNINIT - { - * (.noinit) - } - - ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE - { - } - - ; Used for the digital signature of the secure application and the - ; Bootloader SDK application. The size of the section depends on the required - ; data size. - .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 - { - * (.cy_app_signature) - } -} - - -; Emulated EEPROM Flash area -LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE -{ - .cy_em_eeprom +0 - { - * (.cy_em_eeprom) - } -} - -; Supervisory flash: User data -LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE -{ - .cy_sflash_user_data +0 - { - * (.cy_sflash_user_data) - } -} - -; Supervisory flash: Normal Access Restrictions (NAR) -LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE -{ - .cy_sflash_nar +0 - { - * (.cy_sflash_nar) - } -} - -; Supervisory flash: Public Key -LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE -{ - .cy_sflash_public_key +0 - { - * (.cy_sflash_public_key) - } -} - -; Supervisory flash: Table of Content # 2 -LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE -{ - .cy_toc_part2 +0 - { - * (.cy_toc_part2) - } -} - -; Supervisory flash: Table of Content # 2 Copy -LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE -{ - .cy_rtoc_part2 +0 - { - * (.cy_rtoc_part2) - } -} - - -; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. -LR_EROM XIP_START XIP_SIZE -{ - .cy_xip +0 - { - * (.cy_xip) - } -} - - -; eFuse -LR_EFUSE EFUSE_START EFUSE_SIZE -{ - .cy_efuse +0 - { - * (.cy_efuse) - } -} - - -; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. -CYMETA 0x90500000 -{ - .cymeta +0 { * (.cymeta) } -} - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -#define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00200000 -#define __cy_memory_0_row_size 0x200 - -/* Emulated EEPROM Flash area */ -#define __cy_memory_1_start 0x14000000 -#define __cy_memory_1_length 0x8000 -#define __cy_memory_1_row_size 0x200 - -/* Supervisory Flash */ -#define __cy_memory_2_start 0x16000000 -#define __cy_memory_2_length 0x8000 -#define __cy_memory_2_row_size 0x200 - -/* XIP */ -#define __cy_memory_3_start 0x18000000 -#define __cy_memory_3_length 0x08000000 -#define __cy_memory_3_row_size 0x200 - -/* eFuse */ -#define __cy_memory_4_start 0x90700000 -#define __cy_memory_4_length 0x100000 -#define __cy_memory_4_row_size 1 - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S deleted file mode 100644 index 88eb1f471d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S +++ /dev/null @@ -1,703 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_02_cm4.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM4 Device Series -; * @version V5.00 -; * @date 02. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD 0x0000000D ; NMI Handler located at ROM code - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External interrupts Description - DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 - DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 - DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 - DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 - DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 - DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 - DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 - DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 - DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 - DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 - DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 - DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 - DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 - DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 - DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 - DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports - DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt - DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt - DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) - DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt - DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) - DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 - DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 - DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 - DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 - DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 - DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 - DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 - DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 - DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 - DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 - DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 - DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 - DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 - DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 - DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 - DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 - DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 - DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 - DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 - DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 - DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 - DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 - DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 - DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 - DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 - DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 - DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 - DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 - DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt - DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 - DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 - DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 - DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 - DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 - DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 - DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 - DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 - DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 - DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 - DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 - DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 - DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 - DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 - DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 - DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 - DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 - DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 - DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 - DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 - DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 - DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 - DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 - DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 - DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 - DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 - DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 - DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 - DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 - DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 - DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 - DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 - DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 - DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 - DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 - DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 - DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 - DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 - DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 - DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 - DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 - DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 - DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 - DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 - DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 - DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 - DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 - DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 - DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 - DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 - DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 - DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 - DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 - DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 - DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 - DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 - DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 - DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 - DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 - DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 - DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 - DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 - DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 - DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 - DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt - DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt - DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault - DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 - DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 - DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 - DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 - DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 - DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 - DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 - DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 - DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 - DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 - DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 - DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 - DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 - DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 - DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 - DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 - DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 - DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 - DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 - DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 - DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 - DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 - DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 - DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 - DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 - DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 - DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 - DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 - DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 - DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 - DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 - DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 - DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 - DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 - DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 - DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 - DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt - DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt - DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt - DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt - DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt - DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt - DCD usb_interrupt_hi_IRQHandler ; USB Interrupt - DCD usb_interrupt_med_IRQHandler ; USB Interrupt - DCD usb_interrupt_lo_IRQHandler ; USB Interrupt - DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc - DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else - DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used - DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - EXPORT __ramVectors - AREA RESET_RAM, READWRITE, NOINIT -__ramVectors SPACE __Vectors_Size - - - AREA |.text|, CODE, READONLY - - -; Weak function for startup customization -; -; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -; because this function is executed as the first instruction in the ResetHandler. -; The PDL is also not initialized to use the proper register offsets. -; The user of this function is responsible for initializing the PDL and resources before using them. -; -Cy_OnResetUser PROC - EXPORT Cy_OnResetUser [WEAK] - BX LR - ENDP - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT Cy_SystemInitFpuEnable - IMPORT __main - - ; Define strong function for startup customization - BL Cy_OnResetUser - - ; Disable global interrupts - CPSID I - - ; Copy vectors from ROM to RAM - LDR r1, =__Vectors - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -Vectors_Copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE Vectors_Copy - - ; Update Vector Table Offset Register. */ - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb 0xF - - ; Enable the FPU if used - LDR R0, =Cy_SystemInitFpuEnable - BLX R0 - - LDR R0, =__main - BLX R0 - - ; Should never get here - B . - - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -Cy_SysLib_FaultHandler PROC - EXPORT Cy_SysLib_FaultHandler [WEAK] - B . - ENDP -HardFault_Wrapper\ - PROC - EXPORT HardFault_Wrapper [WEAK] - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - bl L_API_call -L_MSP - mrs r0, MSP -L_API_call - bl Cy_SysLib_FaultHandler - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B HardFault_Wrapper - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B HardFault_Wrapper - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B HardFault_Wrapper - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B HardFault_Wrapper - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT Default_Handler [WEAK] - EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] - EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] - EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] - EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] - EXPORT lpcomp_interrupt_IRQHandler [WEAK] - EXPORT scb_8_interrupt_IRQHandler [WEAK] - EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] - EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] - EXPORT srss_interrupt_backup_IRQHandler [WEAK] - EXPORT srss_interrupt_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] - EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] - EXPORT scb_0_interrupt_IRQHandler [WEAK] - EXPORT scb_1_interrupt_IRQHandler [WEAK] - EXPORT scb_2_interrupt_IRQHandler [WEAK] - EXPORT scb_3_interrupt_IRQHandler [WEAK] - EXPORT scb_4_interrupt_IRQHandler [WEAK] - EXPORT scb_5_interrupt_IRQHandler [WEAK] - EXPORT scb_6_interrupt_IRQHandler [WEAK] - EXPORT scb_7_interrupt_IRQHandler [WEAK] - EXPORT scb_9_interrupt_IRQHandler [WEAK] - EXPORT scb_10_interrupt_IRQHandler [WEAK] - EXPORT scb_11_interrupt_IRQHandler [WEAK] - EXPORT scb_12_interrupt_IRQHandler [WEAK] - EXPORT csd_interrupt_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dmac_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dmac_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] - EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] - EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] - EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] - EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] - EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] - EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] - EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] - EXPORT pass_interrupt_sar_IRQHandler [WEAK] - EXPORT audioss_0_interrupt_i2s_IRQHandler [WEAK] - EXPORT audioss_0_interrupt_pdm_IRQHandler [WEAK] - EXPORT audioss_1_interrupt_i2s_IRQHandler [WEAK] - EXPORT profile_interrupt_IRQHandler [WEAK] - EXPORT smif_interrupt_IRQHandler [WEAK] - EXPORT usb_interrupt_hi_IRQHandler [WEAK] - EXPORT usb_interrupt_med_IRQHandler [WEAK] - EXPORT usb_interrupt_lo_IRQHandler [WEAK] - EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK] - EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK] - EXPORT sdhc_1_interrupt_wakeup_IRQHandler [WEAK] - EXPORT sdhc_1_interrupt_general_IRQHandler [WEAK] - -ioss_interrupts_gpio_0_IRQHandler -ioss_interrupts_gpio_1_IRQHandler -ioss_interrupts_gpio_2_IRQHandler -ioss_interrupts_gpio_3_IRQHandler -ioss_interrupts_gpio_4_IRQHandler -ioss_interrupts_gpio_5_IRQHandler -ioss_interrupts_gpio_6_IRQHandler -ioss_interrupts_gpio_7_IRQHandler -ioss_interrupts_gpio_8_IRQHandler -ioss_interrupts_gpio_9_IRQHandler -ioss_interrupts_gpio_10_IRQHandler -ioss_interrupts_gpio_11_IRQHandler -ioss_interrupts_gpio_12_IRQHandler -ioss_interrupts_gpio_13_IRQHandler -ioss_interrupts_gpio_14_IRQHandler -ioss_interrupt_gpio_IRQHandler -ioss_interrupt_vdd_IRQHandler -lpcomp_interrupt_IRQHandler -scb_8_interrupt_IRQHandler -srss_interrupt_mcwdt_0_IRQHandler -srss_interrupt_mcwdt_1_IRQHandler -srss_interrupt_backup_IRQHandler -srss_interrupt_IRQHandler -cpuss_interrupts_ipc_0_IRQHandler -cpuss_interrupts_ipc_1_IRQHandler -cpuss_interrupts_ipc_2_IRQHandler -cpuss_interrupts_ipc_3_IRQHandler -cpuss_interrupts_ipc_4_IRQHandler -cpuss_interrupts_ipc_5_IRQHandler -cpuss_interrupts_ipc_6_IRQHandler -cpuss_interrupts_ipc_7_IRQHandler -cpuss_interrupts_ipc_8_IRQHandler -cpuss_interrupts_ipc_9_IRQHandler -cpuss_interrupts_ipc_10_IRQHandler -cpuss_interrupts_ipc_11_IRQHandler -cpuss_interrupts_ipc_12_IRQHandler -cpuss_interrupts_ipc_13_IRQHandler -cpuss_interrupts_ipc_14_IRQHandler -cpuss_interrupts_ipc_15_IRQHandler -scb_0_interrupt_IRQHandler -scb_1_interrupt_IRQHandler -scb_2_interrupt_IRQHandler -scb_3_interrupt_IRQHandler -scb_4_interrupt_IRQHandler -scb_5_interrupt_IRQHandler -scb_6_interrupt_IRQHandler -scb_7_interrupt_IRQHandler -scb_9_interrupt_IRQHandler -scb_10_interrupt_IRQHandler -scb_11_interrupt_IRQHandler -scb_12_interrupt_IRQHandler -csd_interrupt_IRQHandler -cpuss_interrupts_dmac_0_IRQHandler -cpuss_interrupts_dmac_1_IRQHandler -cpuss_interrupts_dmac_2_IRQHandler -cpuss_interrupts_dmac_3_IRQHandler -cpuss_interrupts_dw0_0_IRQHandler -cpuss_interrupts_dw0_1_IRQHandler -cpuss_interrupts_dw0_2_IRQHandler -cpuss_interrupts_dw0_3_IRQHandler -cpuss_interrupts_dw0_4_IRQHandler -cpuss_interrupts_dw0_5_IRQHandler -cpuss_interrupts_dw0_6_IRQHandler -cpuss_interrupts_dw0_7_IRQHandler -cpuss_interrupts_dw0_8_IRQHandler -cpuss_interrupts_dw0_9_IRQHandler -cpuss_interrupts_dw0_10_IRQHandler -cpuss_interrupts_dw0_11_IRQHandler -cpuss_interrupts_dw0_12_IRQHandler -cpuss_interrupts_dw0_13_IRQHandler -cpuss_interrupts_dw0_14_IRQHandler -cpuss_interrupts_dw0_15_IRQHandler -cpuss_interrupts_dw0_16_IRQHandler -cpuss_interrupts_dw0_17_IRQHandler -cpuss_interrupts_dw0_18_IRQHandler -cpuss_interrupts_dw0_19_IRQHandler -cpuss_interrupts_dw0_20_IRQHandler -cpuss_interrupts_dw0_21_IRQHandler -cpuss_interrupts_dw0_22_IRQHandler -cpuss_interrupts_dw0_23_IRQHandler -cpuss_interrupts_dw0_24_IRQHandler -cpuss_interrupts_dw0_25_IRQHandler -cpuss_interrupts_dw0_26_IRQHandler -cpuss_interrupts_dw0_27_IRQHandler -cpuss_interrupts_dw0_28_IRQHandler -cpuss_interrupts_dw1_0_IRQHandler -cpuss_interrupts_dw1_1_IRQHandler -cpuss_interrupts_dw1_2_IRQHandler -cpuss_interrupts_dw1_3_IRQHandler -cpuss_interrupts_dw1_4_IRQHandler -cpuss_interrupts_dw1_5_IRQHandler -cpuss_interrupts_dw1_6_IRQHandler -cpuss_interrupts_dw1_7_IRQHandler -cpuss_interrupts_dw1_8_IRQHandler -cpuss_interrupts_dw1_9_IRQHandler -cpuss_interrupts_dw1_10_IRQHandler -cpuss_interrupts_dw1_11_IRQHandler -cpuss_interrupts_dw1_12_IRQHandler -cpuss_interrupts_dw1_13_IRQHandler -cpuss_interrupts_dw1_14_IRQHandler -cpuss_interrupts_dw1_15_IRQHandler -cpuss_interrupts_dw1_16_IRQHandler -cpuss_interrupts_dw1_17_IRQHandler -cpuss_interrupts_dw1_18_IRQHandler -cpuss_interrupts_dw1_19_IRQHandler -cpuss_interrupts_dw1_20_IRQHandler -cpuss_interrupts_dw1_21_IRQHandler -cpuss_interrupts_dw1_22_IRQHandler -cpuss_interrupts_dw1_23_IRQHandler -cpuss_interrupts_dw1_24_IRQHandler -cpuss_interrupts_dw1_25_IRQHandler -cpuss_interrupts_dw1_26_IRQHandler -cpuss_interrupts_dw1_27_IRQHandler -cpuss_interrupts_dw1_28_IRQHandler -cpuss_interrupts_fault_0_IRQHandler -cpuss_interrupts_fault_1_IRQHandler -cpuss_interrupt_crypto_IRQHandler -cpuss_interrupt_fm_IRQHandler -cpuss_interrupts_cm4_fp_IRQHandler -cpuss_interrupts_cm0_cti_0_IRQHandler -cpuss_interrupts_cm0_cti_1_IRQHandler -cpuss_interrupts_cm4_cti_0_IRQHandler -cpuss_interrupts_cm4_cti_1_IRQHandler -tcpwm_0_interrupts_0_IRQHandler -tcpwm_0_interrupts_1_IRQHandler -tcpwm_0_interrupts_2_IRQHandler -tcpwm_0_interrupts_3_IRQHandler -tcpwm_0_interrupts_4_IRQHandler -tcpwm_0_interrupts_5_IRQHandler -tcpwm_0_interrupts_6_IRQHandler -tcpwm_0_interrupts_7_IRQHandler -tcpwm_1_interrupts_0_IRQHandler -tcpwm_1_interrupts_1_IRQHandler -tcpwm_1_interrupts_2_IRQHandler -tcpwm_1_interrupts_3_IRQHandler -tcpwm_1_interrupts_4_IRQHandler -tcpwm_1_interrupts_5_IRQHandler -tcpwm_1_interrupts_6_IRQHandler -tcpwm_1_interrupts_7_IRQHandler -tcpwm_1_interrupts_8_IRQHandler -tcpwm_1_interrupts_9_IRQHandler -tcpwm_1_interrupts_10_IRQHandler -tcpwm_1_interrupts_11_IRQHandler -tcpwm_1_interrupts_12_IRQHandler -tcpwm_1_interrupts_13_IRQHandler -tcpwm_1_interrupts_14_IRQHandler -tcpwm_1_interrupts_15_IRQHandler -tcpwm_1_interrupts_16_IRQHandler -tcpwm_1_interrupts_17_IRQHandler -tcpwm_1_interrupts_18_IRQHandler -tcpwm_1_interrupts_19_IRQHandler -tcpwm_1_interrupts_20_IRQHandler -tcpwm_1_interrupts_21_IRQHandler -tcpwm_1_interrupts_22_IRQHandler -tcpwm_1_interrupts_23_IRQHandler -pass_interrupt_sar_IRQHandler -audioss_0_interrupt_i2s_IRQHandler -audioss_0_interrupt_pdm_IRQHandler -audioss_1_interrupt_i2s_IRQHandler -profile_interrupt_IRQHandler -smif_interrupt_IRQHandler -usb_interrupt_hi_IRQHandler -usb_interrupt_med_IRQHandler -usb_interrupt_lo_IRQHandler -sdhc_0_interrupt_wakeup_IRQHandler -sdhc_0_interrupt_general_IRQHandler -sdhc_1_interrupt_wakeup_IRQHandler -sdhc_1_interrupt_general_IRQHandler - - B . - ENDP - - ALIGN - - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld deleted file mode 100644 index 8f5a345f18..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld +++ /dev/null @@ -1,448 +0,0 @@ -/***************************************************************************//** -* \file cy8c6xxa_cm4_dual.ld -* \version 2.60 -* -* Linker file for the GNU C compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point location is fixed and starts at 0x10000000. The valid -* application image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -SEARCH_DIR(.) -GROUP(-lgcc -lc -lnosys) -ENTRY(Reset_Handler) - -#if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10180000 -#endif - -/* MBED_APP_START is being used by the bootloader build script and -* will be calculate by the system. In case if MBED_APP_START address is -* customized by the bootloader config, the application image should not -* include CM0p prebuilt image. -*/ -#if !defined(MBED_APP_START) - #define MBED_APP_START (MBED_ROM_START) -#endif - -#if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x80000 -#endif - -/* MBED_APP_SIZE is being used by the bootloader build script and -* will be calculate by the system. -*/ -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08080000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x7F800 -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -/* Size of the stack section at the end of CM4 SRAM */ -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Force symbol to be entered in the output file as an undefined symbol. Doing -* this may, for example, trigger linking of additional modules from standard -* libraries. You may list several symbols for each EXTERN, and you may use -* EXTERN multiple times. This command has the same effect as the -u command-line -* option. -*/ -EXTERN(Reset_Handler) - -/* The MEMORY section below describes the location and size of blocks of memory in the target. -* Use this section to specify the memory regions available for allocation. -*/ -MEMORY -{ - /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing the 'ram' and 'flash' regions. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. - */ - ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE - flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - - /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ - em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ - - /* The following regions define device specific memory regions and must not be changed. */ - sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ - sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ - sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ - sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ - sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ - xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ - efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - */ - - -SECTIONS -{ - /* Cortex-M4 application flash area */ - .text ORIGIN(flash) : - { - . = ALIGN(4); - __Vectors = . ; - KEEP(*(.vectors)) - . = ALIGN(4); - __Vectors_End = .; - __Vectors_Size = __Vectors_End - __Vectors; - __end__ = .; - - . = ALIGN(4); - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - /* Read-only code (constants). */ - *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) - - KEEP(*(.eh_frame*)) - } > flash - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash - - __exidx_start = .; - - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - /* Copy interrupt vectors from flash to RAM */ - LONG (__Vectors) /* From */ - LONG (__ram_vectors_start__) /* To */ - LONG (__Vectors_End - __Vectors) /* Size */ - - /* Copy data section to RAM */ - LONG (__etext) /* From */ - LONG (__data_start__) /* To */ - LONG (__data_end__ - __data_start__) /* Size */ - - __copy_table_end__ = .; - } > flash - - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - __zero_table_end__ = .; - } > flash - - __etext = . ; - - - .ramVectors (NOLOAD) : ALIGN(8) - { - __ram_vectors_start__ = .; - KEEP(*(.ram_vectors)) - __ram_vectors_end__ = .; - } > ram - - - .data __ram_vectors_end__ : AT (__etext) - { - __data_start__ = .; - - *(vtable) - *(.data*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - - KEEP(*(.cy_ramfunc*)) - . = ALIGN(4); - - __data_end__ = .; - - } > ram - - - /* Place variables in the section that should not be initialized during the - * device startup. - */ - .noinit (NOLOAD) : ALIGN(8) - { - KEEP(*(.noinit)) - } > ram - - - /* The uninitialized global or static variables are placed in this section. - * - * The NOLOAD attribute tells linker that .bss section does not consume - * any space in the image. The NOLOAD attribute changes the .bss type to - * NOBITS, and that makes linker to A) not allocate section in memory, and - * A) put information to clear the section with all zeros during application - * loading. - * - * Without the NOLOAD attribute, the .bss section might get PROGBITS type. - * This makes linker to A) allocate zeroed section in memory, and B) copy - * this section to RAM during application loading. - */ - .bss (NOLOAD): - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > ram - - - .heap (NOLOAD): - { - __HeapBase = .; - __end__ = .; - end = __end__; - KEEP(*(.heap*)) - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - __HeapLimit = .; - } > ram - - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(ram) + LENGTH(ram); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - - /* Used for the digital signature of the secure application and the Bootloader SDK application. - * The size of the section depends on the required data size. */ - .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : - { - KEEP(*(.cy_app_signature)) - } > flash - - - /* Emulated EEPROM Flash area */ - .cy_em_eeprom : - { - KEEP(*(.cy_em_eeprom)) - } > em_eeprom - - - /* Supervisory Flash: User data */ - .cy_sflash_user_data : - { - KEEP(*(.cy_sflash_user_data)) - } > sflash_user_data - - - /* Supervisory Flash: Normal Access Restrictions (NAR) */ - .cy_sflash_nar : - { - KEEP(*(.cy_sflash_nar)) - } > sflash_nar - - - /* Supervisory Flash: Public Key */ - .cy_sflash_public_key : - { - KEEP(*(.cy_sflash_public_key)) - } > sflash_public_key - - - /* Supervisory Flash: Table of Content # 2 */ - .cy_toc_part2 : - { - KEEP(*(.cy_toc_part2)) - } > sflash_toc_2 - - - /* Supervisory Flash: Table of Content # 2 Copy */ - .cy_rtoc_part2 : - { - KEEP(*(.cy_rtoc_part2)) - } > sflash_rtoc_2 - - - /* Places the code in the Execute in Place (XIP) section. See the smif driver - * documentation for details. - */ - .cy_xip : - { - KEEP(*(.cy_xip)) - } > xip - - - /* eFuse */ - .cy_efuse : - { - KEEP(*(.cy_efuse)) - } > efuse - - - /* These sections are used for additional metadata (silicon revision, - * Silicon/JTAG ID, etc.) storage. - */ - .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE -} - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -__cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x00200000; -__cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -__cy_memory_1_start = 0x14000000; -__cy_memory_1_length = 0x8000; -__cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -__cy_memory_2_start = 0x16000000; -__cy_memory_2_length = 0x8000; -__cy_memory_2_row_size = 0x200; - -/* XIP */ -__cy_memory_3_start = 0x18000000; -__cy_memory_3_length = 0x08000000; -__cy_memory_3_row_size = 0x200; - -/* eFuse */ -__cy_memory_4_start = 0x90700000; -__cy_memory_4_length = 0x100000; -__cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S deleted file mode 100644 index 1ebcac39f8..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S +++ /dev/null @@ -1,673 +0,0 @@ -/**************************************************************************//** - * @file startup_psoc6_02_cm4.S - * @brief CMSIS Core Device Startup File for - * ARMCM4 Device Series - * @version V5.00 - * @date 02. March 2016 - ******************************************************************************/ -/* - * Copyright (c) 2009-2016 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - /* Address of the NMI handler */ - #define CY_NMI_HANLDER_ADDR 0x0000000D - - /* The CPU VTOR register */ - #define CY_CPU_VTOR_ADDR 0xE000ED08 - - /* Copy flash vectors and data section to RAM */ - #define __STARTUP_COPY_MULTIPLE - - /* Clear single BSS section */ - #define __STARTUP_CLEAR_BSS - - .syntax unified - .arch armv7-m - - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x00001000 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x00000400 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .if Heap_Size - .space Heap_Size - .endif - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long CY_NMI_HANLDER_ADDR /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External interrupts Description */ - .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ - .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ - .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ - .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ - .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ - .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ - .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ - .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ - .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ - .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ - .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ - .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ - .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ - .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ - .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ - .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ - .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ - .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ - .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ - .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ - .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ - .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ - .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ - .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ - .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ - .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ - .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ - .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ - .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ - .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ - .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ - .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ - .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ - .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ - .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ - .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ - .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ - .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ - .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ - .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ - .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ - .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ - .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ - .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ - .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ - .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ - .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ - .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ - .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ - .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ - .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ - .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ - .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ - .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ - .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ - .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ - .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ - .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ - .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ - .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ - .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ - .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ - .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ - .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ - .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ - .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ - .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ - .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ - .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ - .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ - .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ - .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ - .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ - .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ - .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ - .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ - .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ - .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ - .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ - .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ - .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ - .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ - .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ - .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ - .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ - .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ - .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ - .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ - .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ - .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ - .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ - .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ - .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ - .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ - .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ - .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ - .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ - .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ - .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ - .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ - .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ - .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ - .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ - .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ - .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ - .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ - .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ - .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ - .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ - .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ - .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ - .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ - .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ - .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ - .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ - .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ - .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ - .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ - .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ - .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ - .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ - .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ - .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ - .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ - .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ - .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ - .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ - .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ - .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ - .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ - .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ - .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ - .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ - .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ - .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ - .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ - .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ - .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ - .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ - .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ - .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ - .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ - .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ - .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ - .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ - .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ - .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ - .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ - .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ - .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ - .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ - .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ - .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ - .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ - .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ - .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ - .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ - .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ - .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ - .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ - .long usb_interrupt_med_IRQHandler /* USB Interrupt */ - .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ - .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ - .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ - .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ - .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ - - - .size __Vectors, . - __Vectors - .equ __VectorsSize, . - __Vectors - - .section .ram_vectors - .align 2 - .globl __ramVectors -__ramVectors: - .space __VectorsSize - .size __ramVectors, . - __ramVectors - - - .text - .thumb - .thumb_func - .align 2 - - /* - * Device startup customization - * - * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) - * because this function is executed as the first instruction in the ResetHandler. - * The PDL is also not initialized to use the proper register offsets. - * The user of this function is responsible for initializing the PDL and resources before using them. - */ - .weak Cy_OnResetUser - .func Cy_OnResetUser, Cy_OnResetUser - .type Cy_OnResetUser, %function - -Cy_OnResetUser: - bx lr - .size Cy_OnResetUser, . - Cy_OnResetUser - .endfunc - - /* Reset handler */ - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: - bl Cy_OnResetUser - cpsid i - -/* Firstly it copies data from read only memory to RAM. There are two schemes - * to copy. One can copy more than one sections. Another can only copy - * one section. The former scheme needs more instructions and read-only - * data to implement than the latter. - * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ - -#ifdef __STARTUP_COPY_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of triplets, each of which specify: - * offset 0: LMA of start of a section to copy from - * offset 4: VMA of start of a section to copy to - * offset 8: size of the section to copy. Must be multiply of 4 - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r4, =__copy_table_start__ - ldr r5, =__copy_table_end__ - -.L_loop0: - cmp r4, r5 - bge .L_loop0_done - ldr r1, [r4] - ldr r2, [r4, #4] - ldr r3, [r4, #8] - -.L_loop0_0: - subs r3, #4 - ittt ge - ldrge r0, [r1, r3] - strge r0, [r2, r3] - bge .L_loop0_0 - - adds r4, #12 - b .L_loop0 - -.L_loop0_done: -#else -/* Single section scheme. - * - * The ranges of copy from/to are specified by following symbols - * __etext: LMA of start of the section to copy from. Usually end of text - * __data_start__: VMA of start of the section to copy to - * __data_end__: VMA of end of the section to copy to - * - * All addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -.L_loop1: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .L_loop1 -#endif /*__STARTUP_COPY_MULTIPLE */ - -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * There are two schemes too. One can clear multiple BSS sections. Another - * can only clear one section. The former is more size expensive than the - * latter. - * - * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. - * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. - */ -#ifdef __STARTUP_CLEAR_BSS_MULTIPLE -/* Multiple sections scheme. - * - * Between symbol address __copy_table_start__ and __copy_table_end__, - * there are array of tuples specifying: - * offset 0: Start of a BSS section - * offset 4: Size of this BSS section. Must be multiply of 4 - */ - ldr r3, =__zero_table_start__ - ldr r4, =__zero_table_end__ - -.L_loop2: - cmp r3, r4 - bge .L_loop2_done - ldr r1, [r3] - ldr r2, [r3, #4] - movs r0, 0 - -.L_loop2_0: - subs r2, #4 - itt ge - strge r0, [r1, r2] - bge .L_loop2_0 - - adds r3, #8 - b .L_loop2 -.L_loop2_done: -#elif defined (__STARTUP_CLEAR_BSS) -/* Single BSS section scheme. - * - * The BSS section is specified by following symbols - * __bss_start__: start of the BSS section. - * __bss_end__: end of the BSS section. - * - * Both addresses must be aligned to 4 bytes boundary. - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.L_loop3: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .L_loop3 -#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ - - /* Update Vector Table Offset Register. */ - ldr r0, =__ramVectors - ldr r1, =CY_CPU_VTOR_ADDR - str r0, [r1] - dsb 0xF - - /* Enable the FPU if used */ - bl Cy_SystemInitFpuEnable - - bl _start - - /* Should never get here */ - b . - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak Default_Handler - .type Default_Handler, %function - -Default_Handler: - b . - .size Default_Handler, . - Default_Handler - - - .weak Cy_SysLib_FaultHandler - .type Cy_SysLib_FaultHandler, %function - -Cy_SysLib_FaultHandler: - b . - .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler - .type Fault_Handler, %function - -Fault_Handler: - /* Storing LR content for Creator call stack trace */ - push {LR} - movs r0, #4 - mov r1, LR - tst r0, r1 - beq .L_MSP - mrs r0, PSP - b .L_API_call -.L_MSP: - mrs r0, MSP -.L_API_call: - /* Compensation of stack pointer address due to pushing 4 bytes of LR */ - adds r0, r0, #4 - bl Cy_SysLib_FaultHandler - b . - .size Fault_Handler, . - Fault_Handler - -.macro def_fault_Handler fault_handler_name - .weak \fault_handler_name - .set \fault_handler_name, Fault_Handler - .endm - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_handler NMI_Handler - - def_fault_Handler HardFault_Handler - def_fault_Handler MemManage_Handler - def_fault_Handler BusFault_Handler - def_fault_Handler UsageFault_Handler - - def_irq_handler SVC_Handler - def_irq_handler DebugMon_Handler - def_irq_handler PendSV_Handler - def_irq_handler SysTick_Handler - - def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ - def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ - def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ - def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ - def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ - def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ - def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ - def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ - def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ - def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ - def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ - def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ - def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ - def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ - def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ - def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ - def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ - def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ - def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ - def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ - def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ - def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ - def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ - def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ - def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ - def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ - def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ - def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ - def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ - def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ - def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ - def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ - def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ - def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ - def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ - def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ - def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ - def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ - def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ - def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ - def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ - def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ - def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ - def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ - def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ - def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ - def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ - def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ - def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ - def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ - def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ - def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ - def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ - def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ - def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ - def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ - def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ - def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ - def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ - def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ - def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ - def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ - def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ - def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ - def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ - def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ - def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ - def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ - def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ - def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ - def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ - def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ - def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ - def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ - def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ - def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ - def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ - def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ - def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ - def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ - def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ - def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ - def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ - def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ - def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ - def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ - def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ - def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ - def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ - def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ - def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ - def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ - def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ - def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ - def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ - def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ - def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ - def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ - def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ - def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ - def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ - def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ - def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ - def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ - def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ - def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ - def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ - def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ - def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ - def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ - def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ - def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ - def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ - def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ - def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ - def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ - def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ - def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ - def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ - def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ - def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ - def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ - def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ - def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ - def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ - def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ - def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ - def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ - def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ - def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ - def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ - def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ - def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ - def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ - def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ - def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ - def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ - def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ - def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ - def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ - def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ - def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ - def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ - def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ - def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ - def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ - def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ - def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ - def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ - def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ - def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ - def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ - def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ - def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ - def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ - def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ - def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ - def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ - def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ - def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ - def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ - def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ - def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ - def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ - def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ - def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ - def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ - - .end - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf deleted file mode 100644 index 019967a0c1..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf +++ /dev/null @@ -1,274 +0,0 @@ -/***************************************************************************//** -* \file cy8c6xxa_cm4_dual.icf -* \version 2.60 -* -* Linker file for the IAR compiler. -* -* The main purpose of the linker script is to describe how the sections in the -* input files should be mapped into the output file, and to control the memory -* layout of the output file. -* -* \note The entry point is fixed and starts at 0x10000000. The valid application -* image should be placed there. -* -* \note The linker files included with the PDL template projects must be generic -* and handle all common use cases. Your project may not use every section -* defined in the linker files. In that case you may see warnings during the -* build process. In your project, you can simply comment out or remove the -* relevant code in the linker file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -if (!isdefinedsymbol(MBED_ROM_START)) { - define symbol MBED_ROM_START = 0x10180000; -} - -/* MBED_APP_START is being used by the bootloader build script and - * will be calculate by the system. In case if MBED_APP_START address is - * customized by the bootloader config, the application image should not - * include CM0p prebuilt image. - */ -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = (MBED_ROM_START); -} - -if (!isdefinedsymbol(MBED_ROM_SIZE)) { - define symbol MBED_ROM_SIZE = 0x80000; -} - -/* MBED_APP_SIZE is being used by the bootloader build script and - * will be calculate by the system. - */ -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = (MBED_ROM_SIZE); -} - -if (!isdefinedsymbol(MBED_RAM_START)) { - define symbol MBED_RAM_START = 0x08080000; -} - -if (!isdefinedsymbol(MBED_RAM_SIZE)) { - define symbol MBED_RAM_SIZE = 0x7F800; -} - -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - - if (!isdefinedsymbol(__STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x0400; - } else { - define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; - } -} - -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; - -/* The symbols below define the location and size of blocks of memory in the target. - * Use these symbols to specify the memory regions available for allocation. - */ - -/* The following symbols control RAM and flash memory allocation for the CM4 core. - * You can change the memory allocation by editing RAM and Flash symbols. - * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. - * Using this memory region for other purposes will lead to unexpected behavior. - * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', - * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. - */ -/* RAM */ -define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; -define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); -/* Flash */ -define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; -define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); - -/* The following symbols define a 32K flash region used for EEPROM emulation. - * This region can also be used as the general purpose flash. - * You can assign sections to this memory region for only one of the cores. - * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. - * Therefore, repurposing this memory region will prevent such middleware from operation. - */ -define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; -define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; - -/* The following symbols define device specific memory regions and must not be changed. */ -/* Supervisory FLASH - User Data */ -define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; -define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; - -/* Supervisory FLASH - Normal Access Restrictions (NAR) */ -define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; -define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; - -/* Supervisory FLASH - Public Key */ -define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; -define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; - -/* Supervisory FLASH - Table of Content # 2 */ -define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; -define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; - -/* Supervisory FLASH - Table of Content # 2 Copy */ -define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; -define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; - -/* eFuse */ -define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; -define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; - -/* XIP */ -define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; -define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; - -define symbol __ICFEDIT_region_EROM2_start__ = 0x0; -define symbol __ICFEDIT_region_EROM2_end__ = 0x0; -define symbol __ICFEDIT_region_EROM3_start__ = 0x0; -define symbol __ICFEDIT_region_EROM3_end__ = 0x0; - - -define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; -define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; -define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/*-Sizes-*/ -/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ -if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x0400; -} else { - define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; -} -/**** End of ICF editor section. ###ICF###*/ - -define memory mem with size = 4G; -define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; -define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; -define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; -define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; -define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; -define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; -define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; -define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; -define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; - -define block RAM_DATA {readwrite section .data}; -define block RAM_OTHER {readwrite section * }; -define block RAM_NOINIT {readwrite section .noinit}; -define block RAM_BSS {readwrite section .bss}; -define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; - -define block RO {first section .intvec, readonly}; - -/*-Initializations-*/ -initialize by copy { readwrite }; -do not initialize { section .noinit, section .intvec_ram }; - -/*-Placement-*/ - -/* Flash - Cortex-M4 application */ -place at start of IROM1_region { block RO }; - -/* Used for the digital signature of the secure application and the Bootloader SDK application. */ -".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; - -/* Emulated EEPROM Flash area */ -".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; - -/* Supervisory Flash - User Data */ -".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; - -/* Supervisory Flash - NAR */ -".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; - -/* Supervisory Flash - Public Key */ -".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; - -/* Supervisory Flash - TOC2 */ -".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; - -/* Supervisory Flash - RTOC2 */ -".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; - -/* eFuse */ -".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; - -/* Execute in Place (XIP). See the smif driver documentation for details. */ -".cy_xip" : place at start of EROM1_region { section .cy_xip }; - -/* RAM */ -place at start of IRAM1_region { readwrite section .intvec_ram}; -place in IRAM1_region { block RAM}; -place in IRAM1_region { block HEAP}; -place at end of IRAM1_region { block CSTACK }; - -/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ -".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; - - -keep { section .cy_app_signature, - section .cy_em_eeprom, - section .cy_sflash_user_data, - section .cy_sflash_nar, - section .cy_sflash_public_key, - section .cy_toc_part2, - section .cy_rtoc_part2, - section .cy_efuse, - section .cy_xip, - section .cymeta, - }; - - -/* The following symbols used by the cymcuelftool. */ -/* Flash */ -define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x00200000; -define exported symbol __cy_memory_0_row_size = 0x200; - -/* Emulated EEPROM Flash area */ -define exported symbol __cy_memory_1_start = 0x14000000; -define exported symbol __cy_memory_1_length = 0x8000; -define exported symbol __cy_memory_1_row_size = 0x200; - -/* Supervisory Flash */ -define exported symbol __cy_memory_2_start = 0x16000000; -define exported symbol __cy_memory_2_length = 0x8000; -define exported symbol __cy_memory_2_row_size = 0x200; - -/* XIP */ -define exported symbol __cy_memory_3_start = 0x18000000; -define exported symbol __cy_memory_3_length = 0x08000000; -define exported symbol __cy_memory_3_row_size = 0x200; - -/* eFuse */ -define exported symbol __cy_memory_4_start = 0x90700000; -define exported symbol __cy_memory_4_length = 0x100000; -define exported symbol __cy_memory_4_row_size = 1; - -/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S deleted file mode 100644 index 3257b6f20c..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S +++ /dev/null @@ -1,1263 +0,0 @@ -;/**************************************************************************//** -; * @file startup_psoc6_02_cm4.S -; * @brief CMSIS Core Device Startup File for -; * ARMCM4 Device Series -; * @version V5.00 -; * @date 08. March 2016 -; ******************************************************************************/ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - SECTION .intvec_ram:DATA:NOROOT(2) - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN Cy_SystemInitFpuEnable - EXTERN __iar_data_init3 - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - PUBLIC __ramVectors - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD 0x0000000D ; NMI_Handler is defined in ROM code - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External interrupts Description - DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 - DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 - DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 - DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 - DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 - DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 - DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 - DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 - DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 - DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 - DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 - DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 - DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 - DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 - DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 - DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports - DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt - DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt - DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) - DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt - DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt - DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) - DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 - DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 - DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 - DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 - DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 - DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 - DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 - DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 - DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 - DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 - DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 - DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 - DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 - DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 - DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 - DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 - DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 - DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 - DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 - DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 - DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 - DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 - DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 - DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 - DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 - DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 - DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 - DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 - DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt - DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 - DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 - DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 - DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 - DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 - DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 - DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 - DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 - DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 - DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 - DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 - DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 - DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 - DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 - DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 - DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 - DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 - DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 - DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 - DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 - DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 - DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 - DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 - DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 - DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 - DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 - DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 - DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 - DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 - DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 - DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 - DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 - DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 - DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 - DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 - DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 - DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 - DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 - DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 - DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 - DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 - DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 - DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 - DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 - DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 - DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 - DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 - DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 - DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 - DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 - DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 - DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 - DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 - DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 - DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 - DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 - DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 - DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 - DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 - DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 - DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 - DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 - DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 - DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 - DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt - DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt - DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault - DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 - DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 - DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 - DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 - DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 - DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 - DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 - DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 - DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 - DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 - DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 - DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 - DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 - DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 - DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 - DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 - DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 - DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 - DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 - DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 - DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 - DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 - DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 - DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 - DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 - DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 - DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 - DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 - DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 - DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 - DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 - DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 - DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 - DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 - DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 - DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 - DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt - DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt - DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt - DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt - DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt - DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt - DCD usb_interrupt_hi_IRQHandler ; USB Interrupt - DCD usb_interrupt_med_IRQHandler ; USB Interrupt - DCD usb_interrupt_lo_IRQHandler ; USB Interrupt - DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc - DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else - DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used - DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - SECTION .intvec_ram:DATA:REORDER:NOROOT(2) -__ramVectors - DS32 __Vectors_Size - - - THUMB - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default handlers -;; - PUBWEAK Default_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Default_Handler - B Default_Handler - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Weak function for startup customization -;; -;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) -;; because this function is executed as the first instruction in the ResetHandler. -;; The PDL is also not initialized to use the proper register offsets. -;; The user of this function is responsible for initializing the PDL and resources before using them. -;; - PUBWEAK Cy_OnResetUser - SECTION .text:CODE:REORDER:NOROOT(2) -Cy_OnResetUser - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Define strong version to return zero for -;; __iar_program_start to skip data sections -;; initialization. -;; - PUBLIC __low_level_init - SECTION .text:CODE:REORDER:NOROOT(2) -__low_level_init - MOVS R0, #0 - BX LR - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - ; Define strong function for startup customization - LDR R0, =Cy_OnResetUser - BLX R0 - - ; Disable global interrupts - CPSID I - - ; Copy vectors from ROM to RAM - LDR r1, =__vector_table - LDR r0, =__ramVectors - LDR r2, =__Vectors_Size -intvec_copy - LDR r3, [r1] - STR r3, [r0] - ADDS r0, r0, #4 - ADDS r1, r1, #4 - SUBS r2, r2, #1 - CMP r2, #0 - BNE intvec_copy - - ; Update Vector Table Offset Register - LDR r0, =__ramVectors - LDR r1, =0xE000ED08 - STR r0, [r1] - dsb - - ; Initialize data sections - LDR R0, =__iar_data_init3 - BLX R0 - - LDR R0, =SystemInit - BLX R0 - - LDR R0, =__iar_program_start - BLX R0 - -; Should never get here -Cy_Main_Exited - B Cy_Main_Exited - - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - - PUBWEAK Cy_SysLib_FaultHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Cy_SysLib_FaultHandler - B Cy_SysLib_FaultHandler - - PUBWEAK HardFault_Wrapper - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Wrapper - IMPORT Cy_SysLib_FaultHandler - movs r0, #4 - mov r1, LR - tst r0, r1 - beq L_MSP - mrs r0, PSP - b L_API_call -L_MSP - mrs r0, MSP -L_API_call - ; Storing LR content for Creator call stack trace - push {LR} - bl Cy_SysLib_FaultHandler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Wrapper - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B HardFault_Wrapper - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B HardFault_Wrapper - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B HardFault_Wrapper - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - ; External interrupts - PUBWEAK ioss_interrupts_gpio_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_0_IRQHandler - B ioss_interrupts_gpio_0_IRQHandler - - PUBWEAK ioss_interrupts_gpio_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_1_IRQHandler - B ioss_interrupts_gpio_1_IRQHandler - - PUBWEAK ioss_interrupts_gpio_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_2_IRQHandler - B ioss_interrupts_gpio_2_IRQHandler - - PUBWEAK ioss_interrupts_gpio_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_3_IRQHandler - B ioss_interrupts_gpio_3_IRQHandler - - PUBWEAK ioss_interrupts_gpio_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_4_IRQHandler - B ioss_interrupts_gpio_4_IRQHandler - - PUBWEAK ioss_interrupts_gpio_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_5_IRQHandler - B ioss_interrupts_gpio_5_IRQHandler - - PUBWEAK ioss_interrupts_gpio_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_6_IRQHandler - B ioss_interrupts_gpio_6_IRQHandler - - PUBWEAK ioss_interrupts_gpio_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_7_IRQHandler - B ioss_interrupts_gpio_7_IRQHandler - - PUBWEAK ioss_interrupts_gpio_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_8_IRQHandler - B ioss_interrupts_gpio_8_IRQHandler - - PUBWEAK ioss_interrupts_gpio_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_9_IRQHandler - B ioss_interrupts_gpio_9_IRQHandler - - PUBWEAK ioss_interrupts_gpio_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_10_IRQHandler - B ioss_interrupts_gpio_10_IRQHandler - - PUBWEAK ioss_interrupts_gpio_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_11_IRQHandler - B ioss_interrupts_gpio_11_IRQHandler - - PUBWEAK ioss_interrupts_gpio_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_12_IRQHandler - B ioss_interrupts_gpio_12_IRQHandler - - PUBWEAK ioss_interrupts_gpio_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_13_IRQHandler - B ioss_interrupts_gpio_13_IRQHandler - - PUBWEAK ioss_interrupts_gpio_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupts_gpio_14_IRQHandler - B ioss_interrupts_gpio_14_IRQHandler - - PUBWEAK ioss_interrupt_gpio_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupt_gpio_IRQHandler - B ioss_interrupt_gpio_IRQHandler - - PUBWEAK ioss_interrupt_vdd_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ioss_interrupt_vdd_IRQHandler - B ioss_interrupt_vdd_IRQHandler - - PUBWEAK lpcomp_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -lpcomp_interrupt_IRQHandler - B lpcomp_interrupt_IRQHandler - - PUBWEAK scb_8_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_8_interrupt_IRQHandler - B scb_8_interrupt_IRQHandler - - PUBWEAK srss_interrupt_mcwdt_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_mcwdt_0_IRQHandler - B srss_interrupt_mcwdt_0_IRQHandler - - PUBWEAK srss_interrupt_mcwdt_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_mcwdt_1_IRQHandler - B srss_interrupt_mcwdt_1_IRQHandler - - PUBWEAK srss_interrupt_backup_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_backup_IRQHandler - B srss_interrupt_backup_IRQHandler - - PUBWEAK srss_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -srss_interrupt_IRQHandler - B srss_interrupt_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_0_IRQHandler - B cpuss_interrupts_ipc_0_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_1_IRQHandler - B cpuss_interrupts_ipc_1_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_2_IRQHandler - B cpuss_interrupts_ipc_2_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_3_IRQHandler - B cpuss_interrupts_ipc_3_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_4_IRQHandler - B cpuss_interrupts_ipc_4_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_5_IRQHandler - B cpuss_interrupts_ipc_5_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_6_IRQHandler - B cpuss_interrupts_ipc_6_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_7_IRQHandler - B cpuss_interrupts_ipc_7_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_8_IRQHandler - B cpuss_interrupts_ipc_8_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_9_IRQHandler - B cpuss_interrupts_ipc_9_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_10_IRQHandler - B cpuss_interrupts_ipc_10_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_11_IRQHandler - B cpuss_interrupts_ipc_11_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_12_IRQHandler - B cpuss_interrupts_ipc_12_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_13_IRQHandler - B cpuss_interrupts_ipc_13_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_14_IRQHandler - B cpuss_interrupts_ipc_14_IRQHandler - - PUBWEAK cpuss_interrupts_ipc_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_ipc_15_IRQHandler - B cpuss_interrupts_ipc_15_IRQHandler - - PUBWEAK scb_0_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_0_interrupt_IRQHandler - B scb_0_interrupt_IRQHandler - - PUBWEAK scb_1_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_1_interrupt_IRQHandler - B scb_1_interrupt_IRQHandler - - PUBWEAK scb_2_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_2_interrupt_IRQHandler - B scb_2_interrupt_IRQHandler - - PUBWEAK scb_3_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_3_interrupt_IRQHandler - B scb_3_interrupt_IRQHandler - - PUBWEAK scb_4_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_4_interrupt_IRQHandler - B scb_4_interrupt_IRQHandler - - PUBWEAK scb_5_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_5_interrupt_IRQHandler - B scb_5_interrupt_IRQHandler - - PUBWEAK scb_6_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_6_interrupt_IRQHandler - B scb_6_interrupt_IRQHandler - - PUBWEAK scb_7_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_7_interrupt_IRQHandler - B scb_7_interrupt_IRQHandler - - PUBWEAK scb_9_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_9_interrupt_IRQHandler - B scb_9_interrupt_IRQHandler - - PUBWEAK scb_10_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_10_interrupt_IRQHandler - B scb_10_interrupt_IRQHandler - - PUBWEAK scb_11_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_11_interrupt_IRQHandler - B scb_11_interrupt_IRQHandler - - PUBWEAK scb_12_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -scb_12_interrupt_IRQHandler - B scb_12_interrupt_IRQHandler - - PUBWEAK csd_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -csd_interrupt_IRQHandler - B csd_interrupt_IRQHandler - - PUBWEAK cpuss_interrupts_dmac_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dmac_0_IRQHandler - B cpuss_interrupts_dmac_0_IRQHandler - - PUBWEAK cpuss_interrupts_dmac_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dmac_1_IRQHandler - B cpuss_interrupts_dmac_1_IRQHandler - - PUBWEAK cpuss_interrupts_dmac_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dmac_2_IRQHandler - B cpuss_interrupts_dmac_2_IRQHandler - - PUBWEAK cpuss_interrupts_dmac_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dmac_3_IRQHandler - B cpuss_interrupts_dmac_3_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_0_IRQHandler - B cpuss_interrupts_dw0_0_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_1_IRQHandler - B cpuss_interrupts_dw0_1_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_2_IRQHandler - B cpuss_interrupts_dw0_2_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_3_IRQHandler - B cpuss_interrupts_dw0_3_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_4_IRQHandler - B cpuss_interrupts_dw0_4_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_5_IRQHandler - B cpuss_interrupts_dw0_5_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_6_IRQHandler - B cpuss_interrupts_dw0_6_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_7_IRQHandler - B cpuss_interrupts_dw0_7_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_8_IRQHandler - B cpuss_interrupts_dw0_8_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_9_IRQHandler - B cpuss_interrupts_dw0_9_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_10_IRQHandler - B cpuss_interrupts_dw0_10_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_11_IRQHandler - B cpuss_interrupts_dw0_11_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_12_IRQHandler - B cpuss_interrupts_dw0_12_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_13_IRQHandler - B cpuss_interrupts_dw0_13_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_14_IRQHandler - B cpuss_interrupts_dw0_14_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_15_IRQHandler - B cpuss_interrupts_dw0_15_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_16_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_16_IRQHandler - B cpuss_interrupts_dw0_16_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_17_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_17_IRQHandler - B cpuss_interrupts_dw0_17_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_18_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_18_IRQHandler - B cpuss_interrupts_dw0_18_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_19_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_19_IRQHandler - B cpuss_interrupts_dw0_19_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_20_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_20_IRQHandler - B cpuss_interrupts_dw0_20_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_21_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_21_IRQHandler - B cpuss_interrupts_dw0_21_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_22_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_22_IRQHandler - B cpuss_interrupts_dw0_22_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_23_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_23_IRQHandler - B cpuss_interrupts_dw0_23_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_24_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_24_IRQHandler - B cpuss_interrupts_dw0_24_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_25_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_25_IRQHandler - B cpuss_interrupts_dw0_25_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_26_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_26_IRQHandler - B cpuss_interrupts_dw0_26_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_27_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_27_IRQHandler - B cpuss_interrupts_dw0_27_IRQHandler - - PUBWEAK cpuss_interrupts_dw0_28_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw0_28_IRQHandler - B cpuss_interrupts_dw0_28_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_0_IRQHandler - B cpuss_interrupts_dw1_0_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_1_IRQHandler - B cpuss_interrupts_dw1_1_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_2_IRQHandler - B cpuss_interrupts_dw1_2_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_3_IRQHandler - B cpuss_interrupts_dw1_3_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_4_IRQHandler - B cpuss_interrupts_dw1_4_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_5_IRQHandler - B cpuss_interrupts_dw1_5_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_6_IRQHandler - B cpuss_interrupts_dw1_6_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_7_IRQHandler - B cpuss_interrupts_dw1_7_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_8_IRQHandler - B cpuss_interrupts_dw1_8_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_9_IRQHandler - B cpuss_interrupts_dw1_9_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_10_IRQHandler - B cpuss_interrupts_dw1_10_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_11_IRQHandler - B cpuss_interrupts_dw1_11_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_12_IRQHandler - B cpuss_interrupts_dw1_12_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_13_IRQHandler - B cpuss_interrupts_dw1_13_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_14_IRQHandler - B cpuss_interrupts_dw1_14_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_15_IRQHandler - B cpuss_interrupts_dw1_15_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_16_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_16_IRQHandler - B cpuss_interrupts_dw1_16_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_17_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_17_IRQHandler - B cpuss_interrupts_dw1_17_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_18_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_18_IRQHandler - B cpuss_interrupts_dw1_18_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_19_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_19_IRQHandler - B cpuss_interrupts_dw1_19_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_20_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_20_IRQHandler - B cpuss_interrupts_dw1_20_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_21_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_21_IRQHandler - B cpuss_interrupts_dw1_21_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_22_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_22_IRQHandler - B cpuss_interrupts_dw1_22_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_23_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_23_IRQHandler - B cpuss_interrupts_dw1_23_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_24_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_24_IRQHandler - B cpuss_interrupts_dw1_24_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_25_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_25_IRQHandler - B cpuss_interrupts_dw1_25_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_26_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_26_IRQHandler - B cpuss_interrupts_dw1_26_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_27_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_27_IRQHandler - B cpuss_interrupts_dw1_27_IRQHandler - - PUBWEAK cpuss_interrupts_dw1_28_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_dw1_28_IRQHandler - B cpuss_interrupts_dw1_28_IRQHandler - - PUBWEAK cpuss_interrupts_fault_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_fault_0_IRQHandler - B cpuss_interrupts_fault_0_IRQHandler - - PUBWEAK cpuss_interrupts_fault_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_fault_1_IRQHandler - B cpuss_interrupts_fault_1_IRQHandler - - PUBWEAK cpuss_interrupt_crypto_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupt_crypto_IRQHandler - B cpuss_interrupt_crypto_IRQHandler - - PUBWEAK cpuss_interrupt_fm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupt_fm_IRQHandler - B cpuss_interrupt_fm_IRQHandler - - PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm4_fp_IRQHandler - B cpuss_interrupts_cm4_fp_IRQHandler - - PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm0_cti_0_IRQHandler - B cpuss_interrupts_cm0_cti_0_IRQHandler - - PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm0_cti_1_IRQHandler - B cpuss_interrupts_cm0_cti_1_IRQHandler - - PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm4_cti_0_IRQHandler - B cpuss_interrupts_cm4_cti_0_IRQHandler - - PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -cpuss_interrupts_cm4_cti_1_IRQHandler - B cpuss_interrupts_cm4_cti_1_IRQHandler - - PUBWEAK tcpwm_0_interrupts_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_0_IRQHandler - B tcpwm_0_interrupts_0_IRQHandler - - PUBWEAK tcpwm_0_interrupts_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_1_IRQHandler - B tcpwm_0_interrupts_1_IRQHandler - - PUBWEAK tcpwm_0_interrupts_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_2_IRQHandler - B tcpwm_0_interrupts_2_IRQHandler - - PUBWEAK tcpwm_0_interrupts_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_3_IRQHandler - B tcpwm_0_interrupts_3_IRQHandler - - PUBWEAK tcpwm_0_interrupts_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_4_IRQHandler - B tcpwm_0_interrupts_4_IRQHandler - - PUBWEAK tcpwm_0_interrupts_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_5_IRQHandler - B tcpwm_0_interrupts_5_IRQHandler - - PUBWEAK tcpwm_0_interrupts_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_6_IRQHandler - B tcpwm_0_interrupts_6_IRQHandler - - PUBWEAK tcpwm_0_interrupts_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_0_interrupts_7_IRQHandler - B tcpwm_0_interrupts_7_IRQHandler - - PUBWEAK tcpwm_1_interrupts_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_0_IRQHandler - B tcpwm_1_interrupts_0_IRQHandler - - PUBWEAK tcpwm_1_interrupts_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_1_IRQHandler - B tcpwm_1_interrupts_1_IRQHandler - - PUBWEAK tcpwm_1_interrupts_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_2_IRQHandler - B tcpwm_1_interrupts_2_IRQHandler - - PUBWEAK tcpwm_1_interrupts_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_3_IRQHandler - B tcpwm_1_interrupts_3_IRQHandler - - PUBWEAK tcpwm_1_interrupts_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_4_IRQHandler - B tcpwm_1_interrupts_4_IRQHandler - - PUBWEAK tcpwm_1_interrupts_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_5_IRQHandler - B tcpwm_1_interrupts_5_IRQHandler - - PUBWEAK tcpwm_1_interrupts_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_6_IRQHandler - B tcpwm_1_interrupts_6_IRQHandler - - PUBWEAK tcpwm_1_interrupts_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_7_IRQHandler - B tcpwm_1_interrupts_7_IRQHandler - - PUBWEAK tcpwm_1_interrupts_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_8_IRQHandler - B tcpwm_1_interrupts_8_IRQHandler - - PUBWEAK tcpwm_1_interrupts_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_9_IRQHandler - B tcpwm_1_interrupts_9_IRQHandler - - PUBWEAK tcpwm_1_interrupts_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_10_IRQHandler - B tcpwm_1_interrupts_10_IRQHandler - - PUBWEAK tcpwm_1_interrupts_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_11_IRQHandler - B tcpwm_1_interrupts_11_IRQHandler - - PUBWEAK tcpwm_1_interrupts_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_12_IRQHandler - B tcpwm_1_interrupts_12_IRQHandler - - PUBWEAK tcpwm_1_interrupts_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_13_IRQHandler - B tcpwm_1_interrupts_13_IRQHandler - - PUBWEAK tcpwm_1_interrupts_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_14_IRQHandler - B tcpwm_1_interrupts_14_IRQHandler - - PUBWEAK tcpwm_1_interrupts_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_15_IRQHandler - B tcpwm_1_interrupts_15_IRQHandler - - PUBWEAK tcpwm_1_interrupts_16_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_16_IRQHandler - B tcpwm_1_interrupts_16_IRQHandler - - PUBWEAK tcpwm_1_interrupts_17_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_17_IRQHandler - B tcpwm_1_interrupts_17_IRQHandler - - PUBWEAK tcpwm_1_interrupts_18_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_18_IRQHandler - B tcpwm_1_interrupts_18_IRQHandler - - PUBWEAK tcpwm_1_interrupts_19_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_19_IRQHandler - B tcpwm_1_interrupts_19_IRQHandler - - PUBWEAK tcpwm_1_interrupts_20_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_20_IRQHandler - B tcpwm_1_interrupts_20_IRQHandler - - PUBWEAK tcpwm_1_interrupts_21_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_21_IRQHandler - B tcpwm_1_interrupts_21_IRQHandler - - PUBWEAK tcpwm_1_interrupts_22_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_22_IRQHandler - B tcpwm_1_interrupts_22_IRQHandler - - PUBWEAK tcpwm_1_interrupts_23_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -tcpwm_1_interrupts_23_IRQHandler - B tcpwm_1_interrupts_23_IRQHandler - - PUBWEAK pass_interrupt_sar_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -pass_interrupt_sar_IRQHandler - B pass_interrupt_sar_IRQHandler - - PUBWEAK audioss_0_interrupt_i2s_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -audioss_0_interrupt_i2s_IRQHandler - B audioss_0_interrupt_i2s_IRQHandler - - PUBWEAK audioss_0_interrupt_pdm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -audioss_0_interrupt_pdm_IRQHandler - B audioss_0_interrupt_pdm_IRQHandler - - PUBWEAK audioss_1_interrupt_i2s_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -audioss_1_interrupt_i2s_IRQHandler - B audioss_1_interrupt_i2s_IRQHandler - - PUBWEAK profile_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -profile_interrupt_IRQHandler - B profile_interrupt_IRQHandler - - PUBWEAK smif_interrupt_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -smif_interrupt_IRQHandler - B smif_interrupt_IRQHandler - - PUBWEAK usb_interrupt_hi_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -usb_interrupt_hi_IRQHandler - B usb_interrupt_hi_IRQHandler - - PUBWEAK usb_interrupt_med_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -usb_interrupt_med_IRQHandler - B usb_interrupt_med_IRQHandler - - PUBWEAK usb_interrupt_lo_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -usb_interrupt_lo_IRQHandler - B usb_interrupt_lo_IRQHandler - - PUBWEAK sdhc_0_interrupt_wakeup_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -sdhc_0_interrupt_wakeup_IRQHandler - B sdhc_0_interrupt_wakeup_IRQHandler - - PUBWEAK sdhc_0_interrupt_general_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -sdhc_0_interrupt_general_IRQHandler - B sdhc_0_interrupt_general_IRQHandler - - PUBWEAK sdhc_1_interrupt_wakeup_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -sdhc_1_interrupt_wakeup_IRQHandler - B sdhc_1_interrupt_wakeup_IRQHandler - - PUBWEAK sdhc_1_interrupt_general_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -sdhc_1_interrupt_general_IRQHandler - B sdhc_1_interrupt_general_IRQHandler - - - END - - -; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c deleted file mode 100644 index 0a18f50a4d..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c +++ /dev/null @@ -1,552 +0,0 @@ -/***************************************************************************//** -* \file system_psoc6_cm4.c -* \version 2.60 -* -* The device system-source file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "system_psoc6.h" -#include "cy_device.h" -#include "cy_device_headers.h" -#include "cy_syslib.h" -#include "cy_wdt.h" - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - #include "cy_ipc_sema.h" - #include "cy_ipc_pipe.h" - #include "cy_ipc_drv.h" - - #if defined(CY_DEVICE_PSOC6ABLE2) - #include "cy_flash.h" - #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ - - -/******************************************************************************* -* SystemCoreClockUpdate() -*******************************************************************************/ - -/** Default HFClk frequency in Hz */ -#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) - -/** Default PeriClk frequency in Hz */ -#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) - -/** Default SlowClk system core frequency in Hz */ -#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) - -/** IMO frequency in Hz */ -#define CY_CLK_IMO_FREQ_HZ (8000000UL) - -/** HVILO frequency in Hz */ -#define CY_CLK_HVILO_FREQ_HZ (32000UL) - -/** PILO frequency in Hz */ -#define CY_CLK_PILO_FREQ_HZ (32768UL) - -/** WCO frequency in Hz */ -#define CY_CLK_WCO_FREQ_HZ (32768UL) - -/** ALTLF frequency in Hz */ -#define CY_CLK_ALTLF_FREQ_HZ (32768UL) - - -/** -* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, -* which is the system clock frequency supplied to the SysTick timer and the -* processor core clock. -* This variable implements CMSIS Core global variable. -* Refer to the [CMSIS documentation] -* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") -* for more details. -* This variable can be used by debuggers to query the frequency -* of the debug timer or to configure the trace clock speed. -* -* \attention Compilers must be configured to avoid removing this variable in case -* the application program is not using it. Debugging systems require the variable -* to be physically present in memory so that it can be examined to configure the debugger. */ -uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; - -/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; - -/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ -uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; - -/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ -#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) - uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; -#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ - -/* SCB->CPACR */ -#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) - - -/******************************************************************************* -* SystemInit() -*******************************************************************************/ - -/* CLK_FLL_CONFIG default values */ -#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) -#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) -#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) -#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) - - -/******************************************************************************* -* SystemCoreClockUpdate (void) -*******************************************************************************/ - -/* Do not use these definitions directly in your application */ -#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) -#define CY_DELAY_1K_THRESHOLD (1000u) -#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) -#define CY_DELAY_1M_THRESHOLD (1000000u) -#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) -uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; - -uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / - CY_DELAY_1K_THRESHOLD; - -uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / - CY_DELAY_1M_THRESHOLD); - -uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * - ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); - -#define CY_ROOT_PATH_SRC_IMO (0UL) -#define CY_ROOT_PATH_SRC_EXT (1UL) -#if (SRSS_ECO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ECO (2UL) -#endif /* (SRSS_ECO_PRESENT == 1U) */ -#if (SRSS_ALTHF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_ALTHF (3UL) -#endif /* (SRSS_ALTHF_PRESENT == 1U) */ -#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) -#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) -#if (SRSS_ALTLF_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) -#endif /* (SRSS_ALTLF_PRESENT == 1U) */ -#if (SRSS_PILO_PRESENT == 1U) - #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) -#endif /* (SRSS_PILO_PRESENT == 1U) */ - - -/******************************************************************************* -* Function Name: SystemInit -****************************************************************************//** -* \cond -* Initializes the system: -* - Restores FLL registers to the default state for single core devices. -* - Unlocks and disables WDT. -* - Calls Cy_PDL_Init() function to define the driver library. -* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. -* - Calls \ref SystemCoreClockUpdate(). -* \endcond -*******************************************************************************/ -void SystemInit(void) -{ - Cy_PDL_Init(CY_DEVICE_CFG); - -#ifdef __CM0P_PRESENT - #if (__CM0P_PRESENT == 0) - /* Restore FLL registers to the default state as they are not restored by the ROM code */ - uint32_t copy = SRSS->CLK_FLL_CONFIG; - copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; - SRSS->CLK_FLL_CONFIG = copy; - - copy = SRSS->CLK_ROOT_SELECT[0u]; - copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ - SRSS->CLK_ROOT_SELECT[0u] = copy; - - SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; - SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; - SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; - SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; - - /* Unlock and disable WDT */ - Cy_WDT_Unlock(); - Cy_WDT_Disable(); - #endif /* (__CM0P_PRESENT == 0) */ -#endif /* __CM0P_PRESENT */ - - Cy_SystemInit(); - SystemCoreClockUpdate(); - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) - -#ifdef __CM0P_PRESENT - #if (__CM0P_PRESENT == 0) - /* Allocate and initialize semaphores for the system operations. */ - static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); - #else - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); - #endif /* (__CM0P_PRESENT) */ -#else - (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); -#endif /* __CM0P_PRESENT */ - - - /******************************************************************************** - * - * Initializes the system pipes. The system pipes are used by BLE and Flash. - * - * If the default startup file is not used, or SystemInit() is not called in your - * project, call the following three functions prior to executing any flash or - * EmEEPROM write or erase operation: - * -# Cy_IPC_Sema_Init() - * -# Cy_IPC_Pipe_Config() - * -# Cy_IPC_Pipe_Init() - * -# Cy_Flash_Init() - * - *******************************************************************************/ - /* Create an array of endpoint structures */ - static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; - - Cy_IPC_Pipe_Config(systemIpcPipeEpArray); - - static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; - - static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = - { - /* .ep0ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, - /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 - }, - /* .ep1ConfigData */ - { - /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, - /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, - /* .ipcNotifierMuxNumber */ 0u, - /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, - /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 - }, - /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, - /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, - /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 - }; - - if (cy_device->flashPipeRequired != 0u) - { - Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); - } - -#if defined(CY_DEVICE_PSOC6ABLE2) - Cy_Flash_Init(); -#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ - -#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ -} - - -/******************************************************************************* -* Function Name: Cy_SystemInit -****************************************************************************//** -* -* The function is called during device startup. Once project compiled as part of -* the PSoC Creator project, the Cy_SystemInit() function is generated by the -* PSoC Creator. -* -* The function generated by PSoC Creator performs all of the necessary device -* configuration based on the design settings. This includes settings from the -* Design Wide Resources (DWR) such as Clocks and Pins as well as any component -* configuration that is necessary. -* -*******************************************************************************/ -__WEAK void Cy_SystemInit(void) -{ - /* Empty weak function. The actual implementation to be in the PSoC Creator - * generated strong function. - */ -} - - -/******************************************************************************* -* Function Name: SystemCoreClockUpdate -****************************************************************************//** -* -* Gets core clock frequency and updates \ref SystemCoreClock, \ref -* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. -* -* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref -* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). -* -*******************************************************************************/ -void SystemCoreClockUpdate (void) -{ - uint32_t srcFreqHz; - uint32_t pathFreqHz; - uint32_t fastClkDiv; - uint32_t periClkDiv; - uint32_t rootPath; - uint32_t srcClk; - - /* Get root path clock for the high-frequency clock # 0 */ - rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); - - /* Get source of the root path clock */ - srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); - - /* Get frequency of the source */ - switch (srcClk) - { - case CY_ROOT_PATH_SRC_IMO: - srcFreqHz = CY_CLK_IMO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_EXT: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - - #if (SRSS_ECO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ECO: - srcFreqHz = CY_CLK_ECO_FREQ_HZ; - break; - #endif /* (SRSS_ECO_PRESENT == 1U) */ - -#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_ALTHF: - srcFreqHz = cy_BleEcoClockFreqHz; - break; -#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ - - case CY_ROOT_PATH_SRC_DSI_MUX: - { - uint32_t dsi_src; - dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); - switch (dsi_src) - { - case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - - case CY_ROOT_PATH_SRC_DSI_MUX_WCO: - srcFreqHz = CY_CLK_WCO_FREQ_HZ; - break; - - #if (SRSS_ALTLF_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: - srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; - break; - #endif /* (SRSS_ALTLF_PRESENT == 1U) */ - - #if (SRSS_PILO_PRESENT == 1U) - case CY_ROOT_PATH_SRC_DSI_MUX_PILO: - srcFreqHz = CY_CLK_PILO_FREQ_HZ; - break; - #endif /* (SRSS_PILO_PRESENT == 1U) */ - - default: - srcFreqHz = CY_CLK_HVILO_FREQ_HZ; - break; - } - } - break; - - default: - srcFreqHz = CY_CLK_EXT_FREQ_HZ; - break; - } - - if (rootPath == 0UL) - { - /* FLL */ - bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); - bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); - bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || - (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); - if ((fllOutputAuto && fllLocked) || fllOutputOutput) - { - uint32_t fllMult; - uint32_t refDiv; - uint32_t outputDiv; - - fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); - refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); - outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; - - pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; - } - else - { - pathFreqHz = srcFreqHz; - } - } - else if ((rootPath == 1UL) || (rootPath == 2UL)) - { - /* PLL */ - bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); - bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); - bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || - (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); - if ((pllOutputAuto && pllLocked) || pllOutputOutput) - { - uint32_t feedbackDiv; - uint32_t referenceDiv; - uint32_t outputDiv; - - feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); - - pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; - - } - else - { - pathFreqHz = srcFreqHz; - } - } - else - { - /* Direct */ - pathFreqHz = srcFreqHz; - } - - /* Get frequency after hf_clk pre-divider */ - pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); - cy_Hfclk0FreqHz = pathFreqHz; - - /* Fast Clock Divider */ - fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); - - /* Peripheral Clock Divider */ - periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); - cy_PeriClkFreqHz = pathFreqHz / periClkDiv; - - pathFreqHz = pathFreqHz / fastClkDiv; - SystemCoreClock = pathFreqHz; - - /* Sets clock frequency for Delay API */ - cy_delayFreqHz = SystemCoreClock; - cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); - cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; - cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; -} - - -/******************************************************************************* -* Function Name: Cy_SystemInitFpuEnable -****************************************************************************//** -* -* Enables the FPU if it is used. The function is called from the startup file. -* -*******************************************************************************/ -void Cy_SystemInitFpuEnable(void) -{ - #if defined (__FPU_USED) && (__FPU_USED == 1U) - uint32_t interruptState; - interruptState = Cy_SysLib_EnterCriticalSection(); - SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; - __DSB(); - __ISB(); - Cy_SysLib_ExitCriticalSection(interruptState); - #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ -} - - -#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) -/******************************************************************************* -* Function Name: Cy_SysIpcPipeIsrCm4 -****************************************************************************//** -* -* This is the interrupt service routine for the system pipe. -* -*******************************************************************************/ -void Cy_SysIpcPipeIsrCm4(void) -{ - Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); -} -#endif - - -/******************************************************************************* -* Function Name: Cy_MemorySymbols -****************************************************************************//** -* -* The intention of the function is to declare boundaries of the memories for the -* MDK compilers. For the rest of the supported compilers, this is done using -* linker configuration files. The following symbols used by the cymcuelftool. -* -*******************************************************************************/ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) -__asm void Cy_MemorySymbols(void) -{ - /* Flash */ - EXPORT __cy_memory_0_start - EXPORT __cy_memory_0_length - EXPORT __cy_memory_0_row_size - - /* Working Flash */ - EXPORT __cy_memory_1_start - EXPORT __cy_memory_1_length - EXPORT __cy_memory_1_row_size - - /* Supervisory Flash */ - EXPORT __cy_memory_2_start - EXPORT __cy_memory_2_length - EXPORT __cy_memory_2_row_size - - /* XIP */ - EXPORT __cy_memory_3_start - EXPORT __cy_memory_3_length - EXPORT __cy_memory_3_row_size - - /* eFuse */ - EXPORT __cy_memory_4_start - EXPORT __cy_memory_4_length - EXPORT __cy_memory_4_row_size - - /* Flash */ -__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) -__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) -__cy_memory_0_row_size EQU 0x200 - - /* Flash region for EEPROM emulation */ -__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) -__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) -__cy_memory_1_row_size EQU 0x200 - - /* Supervisory Flash */ -__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) -__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) -__cy_memory_2_row_size EQU 0x200 - - /* XIP */ -__cy_memory_3_start EQU __cpp(CY_XIP_BASE) -__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) -__cy_memory_3_row_size EQU 0x200 - - /* eFuse */ -__cy_memory_4_start EQU __cpp(0x90700000) -__cy_memory_4_length EQU __cpp(0x100000) -__cy_memory_4_row_size EQU __cpp(1) -} -#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ - - -/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h deleted file mode 100644 index 423361f58a..0000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h +++ /dev/null @@ -1,680 +0,0 @@ -/***************************************************************************//** -* \file system_psoc6.h -* \version 2.60 -* -* \brief Device system header file. -* -******************************************************************************** -* \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - - -#ifndef _SYSTEM_PSOC6_H_ -#define _SYSTEM_PSOC6_H_ - -/** -* \addtogroup group_system_config -* \{ -* Provides device startup, system configuration, and linker script files. -* The system startup provides the followings features: -* - See \ref group_system_config_device_initialization for the: -* * \ref group_system_config_dual_core_device_initialization -* * \ref group_system_config_single_core_device_initialization -* - \ref group_system_config_device_memory_definition -* - \ref group_system_config_heap_stack_config -* - \ref group_system_config_merge_apps -* - \ref group_system_config_default_handlers -* - \ref group_system_config_device_vector_table -* - \ref group_system_config_cm4_functions -* -* \section group_system_config_configuration Configuration Considerations -* -* \subsection group_system_config_device_memory_definition Device Memory Definition -* The flash and RAM allocation for each CPU is defined by the linker scripts. -* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. -* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. -* For Single-Core devices the system reserves additional 80 bytes of RAM. -* Using the reserved memory area for other purposes will lead to unexpected behavior. -* -* \note The linker files provided with the PDL are generic and handle all common -* use cases. Your project may not use every section defined in the linker files. -* In that case you may see warnings during the build process. To eliminate build -* warnings in your project, you can simply comment out or remove the relevant -* code in the linker file. -* -* ARM GCC\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the -* Cy_SysEnableCM4() function call. -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.ld', where 'xx' is the device group: -* \code -* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 -* \endcode -* - 'xx_cm4_dual.ld', where 'xx' is the device group: -* \code -* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 -* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's -* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this -* by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode -* -* ARM MDK\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref -* Cy_SysEnableCM4() function call. -* -* \note The linker files provided with the PDL are generic and handle all common -* use cases. Your project may not use every section defined in the linker files. -* In that case you may see the warnings during the build process: -* L6314W (no section matches pattern) and/or L6329W -* (pattern only matches removed unused sections). In your project, you can -* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to -* the linker. You can also comment out or remove the relevant code in the linker -* file. -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.scat', where 'xx' is the device group: -* \code -* #define FLASH_START 0x10000000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08000000 -* #define RAM_SIZE 0x00024000 -* \endcode -* - 'xx_cm4_dual.scat', where 'xx' is the device group: -* \code -* #define FLASH_START 0x10080000 -* #define FLASH_SIZE 0x00080000 -* #define RAM_START 0x08024000 -* #define RAM_SIZE 0x00023800 -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START -* value in the 'xx_cm4_dual.scat' file, -* where 'xx' is the device group. Do this by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode -* -* IAR\n -* The flash and RAM sections for the CPU are defined in the linker files: -* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, -* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. -* \note If the start of the Cortex-M4 application image is changed, the value -* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The -* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref -* Cy_SysEnableCM4() function call. -* -* Change the flash and RAM sizes by editing the macros value in the -* linker files for both CPUs: -* - 'xx_cm0plus.icf', where 'xx' is the device group: -* \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; -* \endcode -* - 'xx_cm4_dual.icf', where 'xx' is the device group: -* \code -* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; -* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; -* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; -* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; -* \endcode -* -* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the -* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' -* is the device group. Do this by either: -* - Passing the following commands to the compiler:\n -* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode -* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where -* 'xx' is device family:\n -* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode -* -* \subsection group_system_config_device_initialization Device Initialization -* After a power-on-reset (POR), the boot process is handled by the boot code -* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot -* code passes the control to the Cortex-M0+ startup code located in flash. -* -* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices -* The Cortex-M0+ startup code performs the device initialization by a call to -* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled -* by default. Enable the core using the \ref Cy_SysEnableCM4() function. -* See \ref group_system_config_cm4_functions for more details. -* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. -* The function has a separate implementation on each core. -* Both function implementations unlock and disable the WDT. -* Therefore enable the WDT after both cores have been initialized. -* -* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices -* The Cortex-M0+ core is not user-accessible on these devices. In this case the -* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. -* -* \subsection group_system_config_heap_stack_config Heap and Stack Configuration -* There are two ways to adjust heap and stack configurations: -* -# Editing source code files -* -# Specifying via command line -* -* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. -* -* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC -* - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). -* Change the heap and stack sizes by modifying the following lines:\n -* \code .equ Stack_Size, 0x00001000 \endcode -* \code .equ Heap_Size, 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the compiler:\n -* \code -D __STACK_SIZE=0x000000400 \endcode -* \code -D __HEAP_SIZE=0x000000100 \endcode -* -* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK -* - Editing source code files\n -* The heap and stack sizes are defined in the assembler startup files -* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the assembler:\n -* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode -* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode -* -* \subsubsection group_system_config_heap_stack_config_iar IAR -* - Editing source code files\n -* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', -* where 'xx' is the device family, and 'yy' is the target CPU; for example, -* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. -* Change the heap and stack sizes by modifying the following lines:\n -* \code Stack_Size EQU 0x00001000 \endcode -* \code Heap_Size EQU 0x00000400 \endcode -* -* - Specifying via command line\n -* Change the heap and stack sizes passing the following commands to the -* linker (including quotation marks):\n -* \code --define_symbol __STACK_SIZE=0x000000400 \endcode -* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode -* -* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables -* The CM0+ project and linker script build the CM0+ application image. Similarly, -* the CM4 linker script builds the CM4 application image. Each specifies -* locations, sizes, and contents of sections in memory. See -* \ref group_system_config_device_memory_definition for the symbols and default -* values. -* -* The cymcuelftool is invoked by a post-build command. The precise project -* setting is IDE-specific. -* -* The cymcuelftool combines the two executables. The tool examines the -* executables to ensure that memory regions either do not overlap, or contain -* identical bytes (shared). If there are no problems, it creates a new ELF file -* with the merged image, without changing any of the addresses or data. -* -* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition -* The default interrupt handler functions are defined as weak functions to a dummy -* handler in the startup file. The naming convention for the interrupt handler names -* is \_IRQHandler. A default interrupt handler can be overwritten in -* user code by defining the handler function using the same name. For example: -* \code -* void scb_0_interrupt_IRQHandler(void) -*{ -* ... -*} -* \endcode -* -* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM -* This process uses memory sections defined in the linker script. The startup -* code actually defines the contents of the vector table and performs the copy. -* \subsubsection group_system_config_device_vector_table_gcc ARM GCC -* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and -* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. -* It defines sections and locations in memory.\n -* Copy interrupt vectors from flash to RAM: \n -* From: \code LONG (__Vectors) \endcode -* To: \code LONG (__ram_vectors_start__) \endcode -* Size: \code LONG (__Vectors_End - __Vectors) \endcode -* The vector table address (and the vector table itself) are defined in the -* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). -* The code in these files copies the vector table from Flash to RAM. -* \subsubsection group_system_config_device_vector_table_mdk ARM MDK -* The linker script file is 'xx_yy.scat', where 'xx' is the device family, -* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and -* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table -* (RESET_RAM) shall be first in the RAM section.\n -* RESET_RAM represents the vector table. It is defined in the assembler startup -* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* The code in these files copies the vector table from Flash to RAM. -* -* \subsubsection group_system_config_device_vector_table_iar IAR -* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and -* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. -* This file defines the .intvec_ram section and its location. -* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode -* The vector table address (and the vector table itself) are defined in the -* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). -* The code in these files copies the vector table from Flash to RAM. -* -* \section group_system_config_more_information More Information -* Refer to the PDL User Guide for the -* more details. -* -* \section group_system_config_MISRA MISRA Compliance -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
-* -* \section group_system_config_changelog Changelog -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
VersionChangesReason for Change
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n -* Removed $Sub$$main symbol for ARM MDK compiler. -* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n -* Added note about WDT disabling by SystemInit() function. -* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. -* Single core device support. -*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n -* Renamed 'wflash' memory region to 'em_eeprom'. -* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
-* -* -* \defgroup group_system_config_macro Macro -* \{ -* \defgroup group_system_config_system_macro System -* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status -* \defgroup group_system_config_user_settings_macro User Settings -* \} -* \defgroup group_system_config_functions Functions -* \{ -* \defgroup group_system_config_system_functions System -* \defgroup group_system_config_cm4_functions Cortex-M4 Control -* \} -* \defgroup group_system_config_globals Global Variables -* -* \} -*/ - -/** -* \addtogroup group_system_config_system_functions -* \{ -* \details -* The following system functions implement CMSIS Core functions. -* Refer to the [CMSIS documentation] -* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") -* for more details. -* \} -*/ - -#ifdef __cplusplus -extern "C" { -#endif - - -/******************************************************************************* -* Include files -*******************************************************************************/ -#include - - -/******************************************************************************* -* Global preprocessor symbols/macros ('define') -*******************************************************************************/ -#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ - (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ - (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) - #define CY_SYSTEM_CPU_CM0P 1UL -#else - #define CY_SYSTEM_CPU_CM0P 0UL -#endif - -#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) - #include "cyfitter.h" -#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ - - - - -/******************************************************************************* -* -* START OF USER SETTINGS HERE -* =========================== -* -* All lines with '<<<' can be set by user. -* -*******************************************************************************/ - -/** -* \addtogroup group_system_config_user_settings_macro -* \{ -*/ - -#if defined (CYDEV_CLK_EXTCLK__HZ) - #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) -#else - /***************************************************************************//** - * External Clock Frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_EXTCLK__HZ) */ - - -#if defined (CYDEV_CLK_ECO__HZ) - #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) -#else - /***************************************************************************//** - * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled - * within PSoC Creator and the clock is enabled in the DWR, the value from DWR - * used. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ -#endif /* (CYDEV_CLK_ECO__HZ) */ - - -#if defined (CYDEV_CLK_ALTHF__HZ) - #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) -#else - /***************************************************************************//** - * \brief Alternate high frequency (in Hz, [value]UL). If compiled within - * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. - * Otherwise, edit the value below. - * (USER SETTING) - *******************************************************************************/ - #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ -#endif /* (CYDEV_CLK_ALTHF__HZ) */ - - -/***************************************************************************//** -* \brief Start address of the Cortex-M4 application ([address]UL) -* (USER SETTING) -*******************************************************************************/ -#if !defined (CY_CORTEX_M4_APPL_ADDR) - #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ -#endif /* (CY_CORTEX_M4_APPL_ADDR) */ - - -/***************************************************************************//** -* \brief IPC Semaphores allocation ([value]UL). -* (USER SETTING) -*******************************************************************************/ -#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ - - -/***************************************************************************//** -* \brief IPC Pipe definitions ([value]UL). -* (USER SETTING) -*******************************************************************************/ -#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ - - -/******************************************************************************* -* -* END OF USER SETTINGS HERE -* ========================= -* -*******************************************************************************/ - -/** \} group_system_config_user_settings_macro */ - - -/** -* \addtogroup group_system_config_system_macro -* \{ -*/ - -#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) - /** The Cortex-M0+ startup driver identifier */ - #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) -#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ - -#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) - /** The Cortex-M4 startup driver identifier */ - #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) -#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ - -/** \} group_system_config_system_macro */ - - -/** -* \addtogroup group_system_config_system_functions -* \{ -*/ -extern void SystemInit(void); - -extern void SystemCoreClockUpdate(void); -/** \} group_system_config_system_functions */ - - -/** -* \addtogroup group_system_config_cm4_functions -* \{ -*/ -extern uint32_t Cy_SysGetCM4Status(void); -extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); -extern void Cy_SysDisableCM4(void); -extern void Cy_SysRetainCM4(void); -extern void Cy_SysResetCM4(void); -/** \} group_system_config_cm4_functions */ - - -/** \cond */ -extern void Default_Handler (void); - -void Cy_SysIpcPipeIsrCm0(void); -void Cy_SysIpcPipeIsrCm4(void); - -extern void Cy_SystemInit(void); -extern void Cy_SystemInitFpuEnable(void); - -extern uint32_t cy_delayFreqHz; -extern uint32_t cy_delayFreqKhz; -extern uint8_t cy_delayFreqMhz; -extern uint32_t cy_delay32kMs; -/** \endcond */ - - -#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) -/** -* \addtogroup group_system_config_cm4_status_macro -* \{ -*/ -#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ -#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ -#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ -#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ -/** \} group_system_config_cm4_status_macro */ - -#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ - - -/******************************************************************************* -* IPC Configuration -* ========================= -*******************************************************************************/ -/* IPC CY_PIPE default configuration */ -#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) - -#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ -#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ -#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ - -#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) -#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) - - -/******************************************************************************/ -/* - * The System pipe configuration defines the IPC channel number, interrupt - * number, and the pipe interrupt mask for the endpoint. - * - * The format of the endPoint configuration - * Bits[31:16] Interrupt Mask - * Bits[15:8 ] IPC interrupt - * Bits[ 7:0 ] IPC channel - */ - -/* System Pipe addresses */ -/* CyPipe defines */ - -#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) - -#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP0) -#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ - | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ - | CY_IPC_CHAN_CYPIPE_EP1) - -/******************************************************************************/ - - -/** \addtogroup group_system_config_globals -* \{ -*/ - -extern uint32_t SystemCoreClock; -extern uint32_t cy_BleEcoClockFreqHz; -extern uint32_t cy_Hfclk0FreqHz; -extern uint32_t cy_PeriClkFreqHz; - -/** \} group_system_config_globals */ - - - -/** \cond INTERNAL */ -/******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must -* not be used in new projects -*******************************************************************************/ - -/* BWC defines for functions related to enter/exit critical section */ -#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection -#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection -#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) -#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) - -/** \endcond */ - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_PSOC6_H_ */ - - -/* [] END OF FILE */ diff --git a/targets/targets.json b/targets/targets.json index 2e819738c9..5093e46a81 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9377,55 +9377,6 @@ "network-default-interface-type": "WIFI" } }, - "CYSBSYSKIT_01": { - "inherits": [ - "MCU_PSOC6_M4" - ], - "components_add": [ - "SCL", - "43012", - "CYW43XXX" - ], - "device_has_remove": [ - "ANALOGOUT" - ], - "components_remove": [ - "CM0P_SLEEP" - ], - "extra_labels_add": [ - "PSOC6_02", - "MXCRYPTO_02" - ], - "macros_add": [ - "CY8C624AFNI_D43", - "CYBSP_WIFI_CAPABLE" - ], - "overrides": { - "network-default-interface-type": "WIFI", - "deep-sleep-latency": 0 - }, - "detect_code": [ - "1912" - ], - "macros_remove": [ - "CYBSP_WIFI_CAPABLE", - "MBED_TICKLESS" - ], - "config": { - "np_cloud_disable": { - "help": "Value: Tells the np to connect to cloud or not", - "value": false - }, - "np_wifi_enable": { - "help": "Value: Tells the np to connect to wifi with its network credentials or wait till cp provides network credentials to it", - "value": false - } - }, - "forced_reset_timeout": 5, - "post_binary_hook": { - "function": "PSOC6Code.complete" - } - }, "FUTURE_SEQUANA_M0": { "inherits": ["MCU_PSOC6_M0"], "supported_form_factors": ["ARDUINO"], From 199407f4d4890900342686f4f202b623f9e73ac3 Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Thu, 16 Apr 2020 11:37:16 +0300 Subject: [PATCH 46/49] Squashed 'features/nanostack/coap-service/' changes from e5e0c138e6..5aa54b8e62 5aa54b8e62 Merge pull request #127 from ARMmbed/sync_with_mbedos 6fe78412d2 Follow Mbed OS coding style 2b708be451 trace group defiined for shared_rng d4c2caca41 more error handling added for ctr and hmac cace1e9c22 Added missing optimizations based on mbedtls/baremetal.h config 2cc7442ba5 Added new global rng, needed for MbedTLS optimisations f861157576 Prepare for upcoming MbedTLS changes git-subtree-dir: features/nanostack/coap-service git-subtree-split: 5aa54b8e622ec2b44bdf323cc02bd1cfc5ffd904 --- .../source/coap_security_handler.c | 4 ++-- .../coap-service/unittest/stub/mbedtls_stub.c | 20 +++++++++---------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/features/nanostack/coap-service/source/coap_security_handler.c b/features/nanostack/coap-service/source/coap_security_handler.c index b2ec1b69d5..5afd2abf02 100644 --- a/features/nanostack/coap-service/source/coap_security_handler.c +++ b/features/nanostack/coap-service/source/coap_security_handler.c @@ -155,8 +155,8 @@ static int coap_security_handler_init(coap_security_t *sec) #elif defined(MBEDTLS_HMAC_DRBG_C) if ((mbedtls_hmac_drbg_seed(&sec->_drbg, mbedtls_md_info_from_type(MBEDTLS_MD_SHA256), mbedtls_entropy_func, &sec->_entropy, - (const unsigned char *) pers, - strlen(pers))) != 0) { + (const unsigned char *) pers, + strlen(pers))) != 0) { return -1; } #else diff --git a/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c b/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c index de419181a7..403ae9a57a 100644 --- a/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c +++ b/features/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c @@ -249,33 +249,33 @@ int mbedtls_ctr_drbg_random(void *p_rng, } // from hmac_drbg.h -void mbedtls_hmac_drbg_init( mbedtls_hmac_drbg_context *ctx ) +void mbedtls_hmac_drbg_init(mbedtls_hmac_drbg_context *ctx) { } -void mbedtls_hmac_drbg_free( mbedtls_hmac_drbg_context *ctx ) +void mbedtls_hmac_drbg_free(mbedtls_hmac_drbg_context *ctx) { } -int mbedtls_hmac_drbg_seed( mbedtls_hmac_drbg_context *ctx, - const mbedtls_md_info_t * md_info, - int (*f_entropy)(void *, unsigned char *, size_t), - void *p_entropy, - const unsigned char *custom, - size_t len ) +int mbedtls_hmac_drbg_seed(mbedtls_hmac_drbg_context *ctx, + const mbedtls_md_info_t *md_info, + int (*f_entropy)(void *, unsigned char *, size_t), + void *p_entropy, + const unsigned char *custom, + size_t len) { return mbedtls_stub.crt_expected_int; } -int mbedtls_hmac_drbg_random( void *p_rng, unsigned char *output, size_t out_len ) +int mbedtls_hmac_drbg_random(void *p_rng, unsigned char *output, size_t out_len) { return mbedtls_stub.crt_expected_int; } // from md.h -const mbedtls_md_info_t *mbedtls_md_info_from_type( mbedtls_md_type_t md_type ) +const mbedtls_md_info_t *mbedtls_md_info_from_type(mbedtls_md_type_t md_type) { return 0; } From 8696907765975bba8cb098c2772c89198c71a783 Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Thu, 16 Apr 2020 14:23:55 +0300 Subject: [PATCH 47/49] Squashed 'features/nanostack/sal-stack-nanostack/' changes from fb7413b846..cc03296c27 cc03296c27 Merge branch 'release_internal' into release_external 59397d17c4 Fixed Wi-SUN border router restart after settings change 8295a43668 PAE authenticator TLS authentication limit based on dynamic value 2776cfef50 RPL config update not re-start whole BR again just increment version number and with new parameters. bec4d48946 Fixed FHSS testing now it follow configured channel count not a wi-sun configured Default. b9cad9d362 Remove floating point literals from Thread code 423a48f48b RPL link etx validation update 89a497a386 Merge branch 'release_internal' into release_external c8cc6601fd Merge pull request #2336 from ARMmbed/sync_with_mbedos ac5f369d70 MBEDTLS_SSL_EXPORT_KEYS added to Nanostack's tls_sec_prot_lib 6522a086ef Added missing optimizations based on mbedtls/baremetal.h config 0e8739fae3 Added new global rng, needed for MbedTLS optimisations d5db37eec8 Prepare for upcoming MbedTLS changes 4271a9dda9 Merge pull request #2335 from ARMmbed/sync_with_mbedos e2db6ffefb Fixed error of function 'mac_fcf_lenght' 28fc2a9543 Fixed error of structure 194e81beda Fixed spelling mistake of structure 00ea3fb83c Remove test files d7f7cc582a Merge branch 'release_internal' into release_external 132cd12107 Merge pull request #2333 from ARMmbed/sync_with_mbedos 550a78e544 Fix function spelling mistake in Thread 74c60242e1 Fix function spelling mistake in border_router.c 89830ecf1a Fix function spelling mistake in iphc_decompress.c 1728ae12dc Fix function spelling mistake in lowpan_context.c ed5d253fcc Fix function spelling mistake in lowpan_context.h ecbca0a2ed Fixed typo 'thead' in thread_neighbor_class.h 071911b30a Changed nanostack API network size to be a range of values 4756be4766 NEW API for Validation RX Unicast schedule channel. 0b48e5c018 Channel Mask update ,support for excluded Channels and FHSS API pdate ead1ade5a7 Start sending PAS message after EAPOL parent TX fails. 8de473b245 Implemented 802.15.4 mode setting (#2328) 975b9e670b Added missing configuration api empty functions f7db06eb1e Added configuration storage (#2283) e9561f0fe4 Removed mbedTLS internal include file fe812c3c1f Changed certificate error message wording to be less fatal 97aaf5f613 Add network property API to Nanostack (#2318) cfd1a4d271 Fixed Route cost calculation 5094614813 Added opeation mode validation for detect unsupported values. 44f85aaf4b Enabled RPL candidate list filtering and only certificate setup accept without limit. 145c7399b3 Wi-sun address registration trigger update d492575adb Modified ARO registrations timeouts from the address lifetime b898f04b5b Removed Extra version number update at revocation start. b9d14097e2 Wi-sun config message consustent filter dcebff9bb5 Use RPL parent soft filtering only after bootstrap. 523593e014 Fixed Broken new channel mask update. a3bcc2d2c8 Removed the PAN version change requirement from routers bc919d8241 Merge pull request #2315 from ARMmbed/merge_release_internal_to_master git-subtree-dir: features/nanostack/sal-stack-nanostack git-subtree-split: cc03296c27fbe26663182d90586e2d31f140e300 --- nanostack/fhss_config.h | 5 +- nanostack/fhss_ws_extension.h | 9 + nanostack/mac_common_defines.h | 1 + nanostack/mlme.h | 1 + nanostack/ns_sha256.h | 16 +- nanostack/platform/arm_hal_phy.h | 12 +- nanostack/socket_api.h | 63 +- nanostack/ws_bbr_api.h | 85 ++ nanostack/ws_management_api.h | 295 ++++- .../Bootstraps/Generic/protocol_6lowpan.c | 88 +- source/6LoWPAN/Bootstraps/protocol_6lowpan.h | 2 + source/6LoWPAN/IPHC_Decode/iphc_decompress.c | 4 +- source/6LoWPAN/IPHC_Decode/lowpan_context.c | 4 +- source/6LoWPAN/IPHC_Decode/lowpan_context.h | 2 +- source/6LoWPAN/Thread/thread_bootstrap.c | 2 +- source/6LoWPAN/Thread/thread_common.c | 2 +- .../Thread/thread_mle_message_handler.c | 2 +- source/6LoWPAN/Thread/thread_neighbor_class.h | 2 +- .../6LoWPAN/Thread/thread_router_bootstrap.c | 2 +- source/6LoWPAN/ws/ws_bbr_api.c | 217 ++- source/6LoWPAN/ws/ws_bbr_api_internal.h | 3 + source/6LoWPAN/ws/ws_bootstrap.c | 527 ++++++-- source/6LoWPAN/ws/ws_bootstrap.h | 5 + source/6LoWPAN/ws/ws_cfg_settings.c | 1169 +++++++++++++++++ source/6LoWPAN/ws/ws_cfg_settings.h | 184 +++ source/6LoWPAN/ws/ws_common.c | 301 ++--- source/6LoWPAN/ws/ws_common.h | 47 +- source/6LoWPAN/ws/ws_common_defines.h | 53 +- source/6LoWPAN/ws/ws_config.h | 68 +- source/6LoWPAN/ws/ws_empty_functions.c | 181 +++ source/6LoWPAN/ws/ws_ie_lib.c | 89 +- source/6LoWPAN/ws/ws_llc_data_service.c | 6 + source/6LoWPAN/ws/ws_management_api.c | 686 +++++++--- source/6LoWPAN/ws/ws_neighbor_class.c | 132 +- source/6LoWPAN/ws/ws_pae_auth.c | 49 +- source/6LoWPAN/ws/ws_pae_auth.h | 28 +- source/6LoWPAN/ws/ws_pae_controller.c | 70 +- source/6LoWPAN/ws/ws_pae_controller.h | 37 +- source/6LoWPAN/ws/ws_pae_lib.c | 7 +- source/6LoWPAN/ws/ws_pae_lib.h | 2 +- source/6LoWPAN/ws/ws_pae_supp.c | 27 +- source/6LoWPAN/ws/ws_pae_supp.h | 30 +- source/6LoWPAN/ws/ws_pae_timers.c | 54 +- source/6LoWPAN/ws/ws_pae_timers.h | 35 +- source/6LoWPAN/ws/ws_test_api.c | 68 +- source/BorderRouter/border_router.c | 8 +- source/Common_Protocols/icmpv6.c | 5 +- source/Core/include/ns_error_types.h | 4 +- source/Core/include/ns_socket.h | 6 +- source/Core/ns_socket.c | 6 +- source/MAC/IEEE802_15_4/mac_defines.h | 2 + .../mac_header_helper_functions.c | 12 +- source/MAC/IEEE802_15_4/mac_mcps_sap.c | 16 +- source/MAC/IEEE802_15_4/mac_mlme.c | 61 +- source/MAC/IEEE802_15_4/mac_mlme.h | 2 +- source/MAC/IEEE802_15_4/mac_pd_sap.c | 2 +- source/MAC/IEEE802_15_4/mac_security_mib.c | 10 +- source/MAC/IEEE802_15_4/mac_security_mib.h | 2 +- source/MAC/IEEE802_15_4/sw_mac.c | 26 +- source/NWK_INTERFACE/Include/protocol.h | 1 + source/RPL/rpl_control.c | 31 +- source/RPL/rpl_control.h | 10 +- source/RPL/rpl_downward.c | 77 +- source/RPL/rpl_downward.h | 3 +- source/RPL/rpl_policy.c | 73 +- source/RPL/rpl_policy.h | 7 + source/RPL/rpl_structures.h | 1 + source/RPL/rpl_upward.c | 1 + source/Security/kmp/kmp_api.c | 4 +- source/Security/kmp/kmp_api.h | 5 +- source/Security/kmp/kmp_eapol_pdu_if.c | 1 + source/Security/kmp/kmp_socket_if.c | 1 + .../eap_tls_sec_prot/auth_eap_tls_sec_prot.c | 42 +- .../eap_tls_sec_prot/eap_tls_sec_prot_lib.c | 1 + .../eap_tls_sec_prot/supp_eap_tls_sec_prot.c | 20 +- .../eap_tls_sec_prot/supp_eap_tls_sec_prot.h | 22 - .../fwh_sec_prot/auth_fwh_sec_prot.c | 35 +- .../fwh_sec_prot/supp_fwh_sec_prot.c | 23 +- .../fwh_sec_prot/supp_fwh_sec_prot.h | 22 - .../gkh_sec_prot/auth_gkh_sec_prot.c | 33 +- .../gkh_sec_prot/supp_gkh_sec_prot.c | 1 + .../protocols/key_sec_prot/key_sec_prot.c | 1 + source/Security/protocols/sec_prot.h | 1 + source/Security/protocols/sec_prot_cfg.h | 29 + source/Security/protocols/sec_prot_keys.c | 1 + source/Security/protocols/sec_prot_lib.c | 1 + .../protocols/tls_sec_prot/tls_sec_prot.c | 2 + .../protocols/tls_sec_prot/tls_sec_prot_lib.c | 47 +- source/Service_Libs/fhss/fhss_common.h | 1 + source/Service_Libs/fhss/fhss_ws.c | 44 +- source/libNET/src/socket_api.c | 69 +- sources.mk | 1 + 92 files changed, 4358 insertions(+), 1087 deletions(-) create mode 100644 source/6LoWPAN/ws/ws_cfg_settings.c create mode 100644 source/6LoWPAN/ws/ws_cfg_settings.h create mode 100644 source/Security/protocols/sec_prot_cfg.h diff --git a/nanostack/fhss_config.h b/nanostack/fhss_config.h index a388f5643f..9a286128ac 100644 --- a/nanostack/fhss_config.h +++ b/nanostack/fhss_config.h @@ -116,9 +116,12 @@ typedef struct fhss_ws_configuration { /** Broadcast fixed channel */ uint8_t broadcast_fixed_channel; - /** Channel mask. */ + /** Channel mask. Wi-SUN will use this for broadcast */ uint32_t channel_mask[8]; + /** Wi-SUN specific unicast channel mask */ + uint32_t unicast_channel_mask[8]; + /** Vendor defined channel function. */ fhss_vendor_defined_cf *vendor_defined_cf; diff --git a/nanostack/fhss_ws_extension.h b/nanostack/fhss_ws_extension.h index 1d8e2998ee..ac2e1b446f 100644 --- a/nanostack/fhss_ws_extension.h +++ b/nanostack/fhss_ws_extension.h @@ -30,6 +30,14 @@ extern "C" { #endif +/** + * @brief ws_channel_mask_t WS neighbour supported channel mask + */ +typedef struct ws_channel_mask { + uint16_t channel_count; /**eth_mac_api) { + // either PPP or Ethernet interface. + latency_estimate = 100; + } else if (thread_info(cur_interface)) { + // thread network + latency_estimate = 1000; + } else if (ws_info(cur_interface)) { + latency_estimate = ws_common_latency_estimate_get(cur_interface); + } else { + // 6LoWPAN ND + latency_estimate = 8000; + } + + if (latency_estimate != 0) { + *latency = latency_estimate; + return true; + } + + return false; +} + +bool protocol_6lowpan_stagger_estimate_get(int8_t interface_id, uint32_t data_amount, uint16_t *stagger_min, uint16_t *stagger_max, uint16_t *stagger_rand) +{ + size_t network_size; + uint32_t datarate; + protocol_interface_info_entry_t *cur_interface = protocol_stack_interface_info_get_by_id(interface_id); + + if (!cur_interface) { + return false; + } + + *stagger_min = 1; + + if (cur_interface->eth_mac_api) { + // either PPP or Ethernet interface. + network_size = 1; + datarate = 1000000; + } else if (thread_info(cur_interface)) { + // thread network + network_size = 23; + datarate = 250000; + } else if (ws_info(cur_interface)) { + network_size = ws_common_network_size_estimate_get(cur_interface); + datarate = ws_common_datarate_get(cur_interface); + } else { + // 6LoWPAN ND + network_size = 1000; + datarate = 250000; + } + + if (data_amount == 0) { + // If no data amount given, use 1kB + data_amount = 1; + } + /**Example: + * Maximum stagger value to send 1kB on 50 devices network using datarate 50000 kb/: + * (1 * 1024 * 8 * 50) / (50000/4)) = ~ 32s + * + * devices: 50, datarate: 250kbps => stagger ~ 6s + * devices: 1000, datarate: 50kbps => stagger ~ 655s + */ + /* Do not occupy whole bandwidth, halve the theoretical datarate and reserve room for other channel usage */ + datarate = datarate / 4; + *stagger_max = (uint16_t) * stagger_min + ((data_amount * 1024 * 8 * network_size) / datarate); + + // Randomize stagger value + *stagger_rand = randLIB_get_random_in_range(*stagger_min, *stagger_max); + + return true; +} diff --git a/source/6LoWPAN/Bootstraps/protocol_6lowpan.h b/source/6LoWPAN/Bootstraps/protocol_6lowpan.h index ebd3ccf5b8..95515c1fd4 100644 --- a/source/6LoWPAN/Bootstraps/protocol_6lowpan.h +++ b/source/6LoWPAN/Bootstraps/protocol_6lowpan.h @@ -75,5 +75,7 @@ uint8_t protocol_6lowpan_beacon_join_priority_tx(int8_t interface_id); uint8_t protocol_6lowpan_beacon_compare_rx(int8_t interface_id, uint8_t join_priority, uint8_t link_quality); bool protocol_6lowpan_bootsrap_start(struct protocol_interface_info_entry *interface); bool protocol_6lowpan_bootsrap_link_set(struct protocol_interface_info_entry *interface, struct mlme_pan_descriptor_s *pan_descriptor, const uint8_t *beacon_payload, uint8_t beacon_length); +bool protocol_6lowpan_latency_estimate_get(int8_t interface_id, uint32_t *latency); +bool protocol_6lowpan_stagger_estimate_get(int8_t interface_id, uint32_t data_amount, uint16_t *stagger_min, uint16_t *stagger_max, uint16_t *stagger_rand); #endif /* PROTOCOL_6LOWPAN_H_ */ diff --git a/source/6LoWPAN/IPHC_Decode/iphc_decompress.c b/source/6LoWPAN/IPHC_Decode/iphc_decompress.c index 8b584297e1..eeeb48c2e1 100644 --- a/source/6LoWPAN/IPHC_Decode/iphc_decompress.c +++ b/source/6LoWPAN/IPHC_Decode/iphc_decompress.c @@ -249,7 +249,7 @@ static bool decompress_mc_addr(const lowpan_context_list_t *context_list, uint8_ *in_ptr = in; return true; case HC_48BIT_CONTEXT_MULTICAST: { - lowpan_context_t *ctx = lowpan_contex_get_by_id(context_list, context); + lowpan_context_t *ctx = lowpan_context_get_by_id(context_list, context); if (!ctx) { return false; } @@ -312,7 +312,7 @@ static bool decompress_addr(const lowpan_context_list_t *context_list, uint8_t * } if (mode & HC_DSTADR_COMP) { - lowpan_context_t *ctx = lowpan_contex_get_by_id(context_list, context); + lowpan_context_t *ctx = lowpan_context_get_by_id(context_list, context); if (!ctx) { return false; } diff --git a/source/6LoWPAN/IPHC_Decode/lowpan_context.c b/source/6LoWPAN/IPHC_Decode/lowpan_context.c index c4391fd76c..1d9a68904a 100644 --- a/source/6LoWPAN/IPHC_Decode/lowpan_context.c +++ b/source/6LoWPAN/IPHC_Decode/lowpan_context.c @@ -31,7 +31,7 @@ #define TRACE_GROUP "lCon" -lowpan_context_t *lowpan_contex_get_by_id(const lowpan_context_list_t *list, uint8_t id) +lowpan_context_t *lowpan_context_get_by_id(const lowpan_context_list_t *list, uint8_t id) { id &= LOWPAN_CONTEXT_CID_MASK; /* Check to see we already have info for this context */ @@ -65,7 +65,7 @@ int_fast8_t lowpan_context_update(lowpan_context_list_t *list, uint8_t cid_flags /* Check to see we already have info for this context */ - ctx = lowpan_contex_get_by_id(list, cid); + ctx = lowpan_context_get_by_id(list, cid); if (ctx) { //Remove from the list - it will be reinserted below, sorted by its //new context length. (Don't need "safe" foreach, as we break diff --git a/source/6LoWPAN/IPHC_Decode/lowpan_context.h b/source/6LoWPAN/IPHC_Decode/lowpan_context.h index e31f9e1afb..0b8daf32cc 100644 --- a/source/6LoWPAN/IPHC_Decode/lowpan_context.h +++ b/source/6LoWPAN/IPHC_Decode/lowpan_context.h @@ -88,7 +88,7 @@ void lowpan_context_timer(lowpan_context_list_t *list, uint_fast16_t ticks); * \return NULL Not supported Context ID * */ -lowpan_context_t *lowpan_contex_get_by_id(const lowpan_context_list_t *list, uint8_t id); +lowpan_context_t *lowpan_context_get_by_id(const lowpan_context_list_t *list, uint8_t id); /** * \brief Get Longest match Context entry from the list for given IPv6 address diff --git a/source/6LoWPAN/Thread/thread_bootstrap.c b/source/6LoWPAN/Thread/thread_bootstrap.c index 483932b578..07e231c864 100644 --- a/source/6LoWPAN/Thread/thread_bootstrap.c +++ b/source/6LoWPAN/Thread/thread_bootstrap.c @@ -955,7 +955,7 @@ static void thread_interface_bootsrap_mode_init(protocol_interface_info_entry_t cur->thread_info->thread_device_mode = THREAD_DEVICE_MODE_SLEEPY_END_DEVICE; //SET Sleepy Host To RX on Idle mode for bootsrap nwk_thread_host_control(cur, NET_HOST_RX_ON_IDLE, 0); - cur->thread_info->childUpdateReqTimer = 0.8 * cur->thread_info->host_link_timeout; + cur->thread_info->childUpdateReqTimer = 8 * cur->thread_info->host_link_timeout / 10; } else { tr_debug("Set End node Mode"); cur->thread_info->thread_device_mode = THREAD_DEVICE_MODE_END_DEVICE; diff --git a/source/6LoWPAN/Thread/thread_common.c b/source/6LoWPAN/Thread/thread_common.c index bfea2ba7a9..8e843f5673 100644 --- a/source/6LoWPAN/Thread/thread_common.c +++ b/source/6LoWPAN/Thread/thread_common.c @@ -381,7 +381,7 @@ void thread_key_guard_timer_calculate(protocol_interface_info_entry_t *cur, link } cur->thread_info->masterSecretMaterial.keyRotation = key_rotation * 3600; // setting value is hours converting to seconds - cur->thread_info->masterSecretMaterial.keySwitchGuardTimer = is_init ? 0 : (key_rotation * 3600 * 0.93); + cur->thread_info->masterSecretMaterial.keySwitchGuardTimer = is_init ? 0 : (key_rotation * 3600 * 93 / 100); } void thread_key_guard_timer_reset(protocol_interface_info_entry_t *cur) diff --git a/source/6LoWPAN/Thread/thread_mle_message_handler.c b/source/6LoWPAN/Thread/thread_mle_message_handler.c index 31e2f3416c..9a465fbc27 100644 --- a/source/6LoWPAN/Thread/thread_mle_message_handler.c +++ b/source/6LoWPAN/Thread/thread_mle_message_handler.c @@ -892,7 +892,7 @@ static void thread_parse_child_update_response(protocol_interface_info_entry_t * if (cur->thread_info->thread_device_mode == THREAD_DEVICE_MODE_SLEEPY_END_DEVICE) { if (cur->thread_info->childUpdateReqTimer < 1) { - cur->thread_info->childUpdateReqTimer = 0.8 * timeout; + cur->thread_info->childUpdateReqTimer = 8 * timeout / 10; } } //This process is ready diff --git a/source/6LoWPAN/Thread/thread_neighbor_class.h b/source/6LoWPAN/Thread/thread_neighbor_class.h index 8dc22889ae..5244441741 100644 --- a/source/6LoWPAN/Thread/thread_neighbor_class.h +++ b/source/6LoWPAN/Thread/thread_neighbor_class.h @@ -32,7 +32,7 @@ struct thread_neighbor_class_s; -/** Thead Spesific ModeFlags */ +/** Thread Spesific ModeFlags */ #define MLE_THREAD_SECURED_DATA_REQUEST 0x04 #define MLE_THREAD_REQ_FULL_DATA_SET 0x01 diff --git a/source/6LoWPAN/Thread/thread_router_bootstrap.c b/source/6LoWPAN/Thread/thread_router_bootstrap.c index 81d5449447..df32d174f6 100644 --- a/source/6LoWPAN/Thread/thread_router_bootstrap.c +++ b/source/6LoWPAN/Thread/thread_router_bootstrap.c @@ -1398,7 +1398,7 @@ static void thread_address_registration_tlv_parse(uint8_t *ptr, uint16_t data_le ctxId = *ptr++; if (ctxId & 0x80) { ctxId &= 0x0f; - ctx = lowpan_contex_get_by_id(&cur->lowpan_contexts, ctxId); + ctx = lowpan_context_get_by_id(&cur->lowpan_contexts, ctxId); if (ctx) { memcpy(tempIPv6Address, ctx->prefix, 8); memcpy(&tempIPv6Address[8], ptr, 8); diff --git a/source/6LoWPAN/ws/ws_bbr_api.c b/source/6LoWPAN/ws/ws_bbr_api.c index 7961f10cc9..d180102e4a 100644 --- a/source/6LoWPAN/ws/ws_bbr_api.c +++ b/source/6LoWPAN/ws/ws_bbr_api.c @@ -27,6 +27,7 @@ #include "6LoWPAN/ws/ws_config.h" #include "6LoWPAN/ws/ws_common.h" #include "6LoWPAN/ws/ws_bootstrap.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" #include "RPL/rpl_control.h" #include "RPL/rpl_data.h" #include "Common_Protocols/icmpv6.h" @@ -61,6 +62,7 @@ static uint8_t current_instance_id = RPL_INSTANCE_ID; */ static int8_t backbone_interface_id = -1; // BBR backbone information static uint16_t configuration = 0; +static uint32_t pan_version_timer = 0; static uint8_t static_dodag_prefix[8] = {0xfd, 0x00, 0x72, 0x83, 0x7e}; static uint8_t static_dodag_id_prefix[8] = {0xfd, 0x00, 0x61, 0x72, 0x6d}; @@ -80,9 +82,9 @@ static rpl_dodag_conf_t rpl_conf = { .dag_max_rank_increase = WS_RPL_MAX_HOP_RANK_INCREASE, .min_hop_rank_increase = WS_RPL_MIN_HOP_RANK_INCREASE, // DIO configuration - .dio_interval_min = WS_RPL_DIO_IMIN, - .dio_interval_doublings = WS_RPL_DIO_DOUBLING, - .dio_redundancy_constant = WS_RPL_DIO_REDUNDANCY + .dio_interval_min = WS_RPL_DIO_IMIN_SMALL, + .dio_interval_doublings = WS_RPL_DIO_DOUBLING_SMALL, + .dio_redundancy_constant = WS_RPL_DIO_REDUNDANCY_SMALL }; static void ws_bbr_rpl_version_timer_start(protocol_interface_info_entry_t *cur, uint8_t version) @@ -109,9 +111,9 @@ void ws_bbr_rpl_config(protocol_interface_info_entry_t *cur, uint8_t imin, uint8 { if (imin == 0 || doubling == 0) { // use default values - imin = WS_RPL_DIO_IMIN; - doubling = WS_RPL_DIO_DOUBLING; - redundancy = WS_RPL_DIO_REDUNDANCY; + imin = WS_RPL_DIO_IMIN_SMALL; + doubling = WS_RPL_DIO_DOUBLING_SMALL; + redundancy = WS_RPL_DIO_REDUNDANCY_SMALL; } if (rpl_conf.dio_interval_min == imin && @@ -532,6 +534,22 @@ static void ws_bbr_rpl_status_check(protocol_interface_info_entry_t *cur) } } } +void ws_bbr_pan_version_increase(protocol_interface_info_entry_t *cur) +{ + if (!cur) { + return; + } + tr_debug("Border router version number update"); + if (configuration & BBR_REQUIRE_DAO_REFRESH) { + // Version number is not periodically increased forcing nodes to check Border router availability using DAO + pan_version_timer = 0; + } else { + pan_version_timer = cur->ws_info->cfg->timing.pan_timeout / PAN_VERSION_CHANGE_INTERVAL; + } + cur->ws_info->pan_information.pan_version++; + // Inconsistent for border router to make information distribute faster + ws_bootstrap_configuration_trickle_reset(cur); +} void ws_bbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds) { @@ -574,18 +592,21 @@ void ws_bbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds } // Normal BBR operation if (protocol_6lowpan_rpl_root_dodag) { - if (cur->ws_info->pan_version_timer > seconds) { - cur->ws_info->pan_version_timer -= seconds; - } else { - // PAN version number update - tr_debug("Border router version number update"); - cur->ws_info->pan_version_timer = ws_common_version_lifetime_get(cur->ws_info->network_size_config); - cur->ws_info->pan_information.pan_version++; - // Inconsistent for border router to make information distribute faster - ws_bootstrap_configuration_trickle_reset(cur); - - if (cur->ws_info->network_size_config == NETWORK_SIZE_AUTOMATIC) { - ws_common_network_size_configure(cur, cur->ws_info->pan_information.pan_size); + /* + * PAN version change is one way to enable nodes to detect the border router availability + * if this is not done periodically devices need to have other means to detect border router condiftion + * + * If devices do not see version change they need to send DAO to border router before PAN timeout + * + * The update frequency should be related to PAN timeout and happen for example 4 times. + */ + if (pan_version_timer > 0) { + if (pan_version_timer > seconds) { + pan_version_timer -= seconds; + } else { + // PAN version number update + pan_version_timer = 0; + ws_bbr_pan_version_increase(cur); } } if (cur->ws_info->rpl_version_timer > seconds) { @@ -754,3 +775,163 @@ int ws_bbr_ext_certificate_validation_set(int8_t interface_id, uint8_t validatio return -1; #endif } + +int ws_bbr_rpl_parameters_set(int8_t interface_id, uint8_t dio_interval_min, uint8_t dio_interval_doublings, uint8_t dio_redundancy_constant) +{ + (void) interface_id; +#ifdef HAVE_WS_BORDER_ROUTER + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); + + ws_rpl_cfg_t cfg; + if (ws_cfg_rpl_get(&cfg, NULL) < 0) { + return -1; + } + + if (dio_interval_min > 0) { + cfg.dio_interval_min = dio_interval_min; + } + if (dio_interval_doublings > 0) { + cfg.dio_interval_doublings = dio_interval_doublings; + } + if (dio_redundancy_constant != 0xff) { + cfg.dio_redundancy_constant = dio_redundancy_constant; + } + + if (ws_cfg_rpl_set(cur, NULL, &cfg, 0) < 0) { + return -2; + } + + return 0; +#else + (void) dio_interval_min; + (void) dio_interval_doublings; + (void) dio_redundancy_constant; + return -1; +#endif +} + +int ws_bbr_rpl_parameters_get(int8_t interface_id, uint8_t *dio_interval_min, uint8_t *dio_interval_doublings, uint8_t *dio_redundancy_constant) +{ + (void) interface_id; +#ifdef HAVE_WS_BORDER_ROUTER + if (!dio_interval_min || !dio_interval_doublings || !dio_redundancy_constant) { + return -1; + } + + ws_rpl_cfg_t cfg; + if (ws_cfg_rpl_get(&cfg, NULL) < 0) { + return -2; + } + + *dio_interval_min = cfg.dio_interval_min; + *dio_interval_doublings = cfg.dio_interval_doublings; + *dio_redundancy_constant = cfg.dio_redundancy_constant; + + return 0; +#else + (void) dio_interval_min; + (void) dio_interval_doublings; + (void) dio_redundancy_constant; + return -1; +#endif +} + +int ws_bbr_rpl_parameters_validate(int8_t interface_id, uint8_t dio_interval_min, uint8_t dio_interval_doublings, uint8_t dio_redundancy_constant) +{ + (void) interface_id; +#ifdef HAVE_WS_BORDER_ROUTER + ws_rpl_cfg_t cfg; + if (ws_cfg_rpl_get(&cfg, NULL) < 0) { + return -2; + } + + if (dio_interval_min > 0) { + cfg.dio_interval_min = dio_interval_min; + } + if (dio_interval_doublings > 0) { + cfg.dio_interval_doublings = dio_interval_doublings; + } + if (dio_redundancy_constant != 0xff) { + cfg.dio_redundancy_constant = dio_redundancy_constant; + } + + if (ws_cfg_rpl_validate(NULL, &cfg) < 0) { + return -3; + } + + return 0; +#else + (void) dio_interval_min; + (void) dio_interval_doublings; + (void) dio_redundancy_constant; + return -1; +#endif +} + +int ws_bbr_pan_configuration_set(int8_t interface_id, uint16_t pan_id) +{ + (void) interface_id; +#ifdef HAVE_WS_BORDER_ROUTER + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); + + ws_gen_cfg_t cfg; + if (ws_cfg_gen_get(&cfg, NULL) < 0) { + return -1; + } + + cfg.network_pan_id = pan_id; + + if (ws_cfg_gen_set(cur, NULL, &cfg, 0) < 0) { + return -2; + } + + return 0; +#else + (void) pan_id; + return -1; +#endif +} + +int ws_bbr_pan_configuration_get(int8_t interface_id, uint16_t *pan_id) +{ + (void) interface_id; +#ifdef HAVE_WS_BORDER_ROUTER + if (!pan_id) { + return -1; + } + + ws_gen_cfg_t cfg; + if (ws_cfg_gen_get(&cfg, NULL) < 0) { + return -2; + } + + *pan_id = cfg.network_pan_id; + + return 0; +#else + (void) pan_id; + return -1; +#endif +} + +int ws_bbr_pan_configuration_validate(int8_t interface_id, uint16_t pan_id) +{ + (void) interface_id; +#ifdef HAVE_WS_BORDER_ROUTER + ws_gen_cfg_t cfg; + if (ws_cfg_gen_get(&cfg, NULL) < 0) { + return -1; + } + + cfg.network_pan_id = pan_id; + + if (ws_cfg_gen_validate(NULL, &cfg) < 0) { + return -2; + } + + return 0; +#else + (void) pan_id; + return -1; +#endif +} diff --git a/source/6LoWPAN/ws/ws_bbr_api_internal.h b/source/6LoWPAN/ws/ws_bbr_api_internal.h index b07565a96c..ee465916af 100644 --- a/source/6LoWPAN/ws/ws_bbr_api_internal.h +++ b/source/6LoWPAN/ws/ws_bbr_api_internal.h @@ -25,6 +25,8 @@ extern uint16_t test_pan_size_override; void ws_bbr_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds); +void ws_bbr_pan_version_increase(protocol_interface_info_entry_t *cur); + uint16_t ws_bbr_pan_size(protocol_interface_info_entry_t *cur); void ws_bbr_rpl_config(protocol_interface_info_entry_t *cur, uint8_t imin, uint8_t doubling, uint8_t redundancy, uint16_t dag_max_rank_increase, uint16_t min_hop_rank_increase); @@ -35,6 +37,7 @@ bool ws_bbr_ready_to_start(protocol_interface_info_entry_t *cur); #else #define ws_bbr_seconds_timer( cur, seconds) +#define ws_bbr_pan_version_increase(cur) #define ws_bbr_pan_size(cur) 0 #define ws_bbr_rpl_config( cur, imin, doubling, redundancy, dag_max_rank_increase, min_hop_rank_increase) #define ws_bbr_ready_to_start(cur) true diff --git a/source/6LoWPAN/ws/ws_bootstrap.c b/source/6LoWPAN/ws/ws_bootstrap.c index 6aaffc1a8e..6a6079acfa 100644 --- a/source/6LoWPAN/ws/ws_bootstrap.c +++ b/source/6LoWPAN/ws/ws_bootstrap.c @@ -17,6 +17,7 @@ #include #include "nsconfig.h" +#ifdef HAVE_WS #include "ns_types.h" #include "ns_trace.h" #include "net_interface.h" @@ -38,6 +39,7 @@ #include "RPL/rpl_protocol.h" #include "RPL/rpl_control.h" #include "RPL/rpl_data.h" +#include "RPL/rpl_policy.h" #include "Common_Protocols/icmpv6.h" #include "Common_Protocols/icmpv6_radv.h" #include "Common_Protocols/ipv6_constants.h" @@ -54,6 +56,7 @@ #include "6LoWPAN/ws/ws_neighbor_class.h" #include "6LoWPAN/ws/ws_ie_lib.h" #include "6LoWPAN/ws/ws_stats.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" #include "6LoWPAN/lowpan_adaptation_interface.h" #include "Service_Libs/etx/etx.h" #include "Service_Libs/mac_neighbor_table/mac_neighbor_table.h" @@ -72,7 +75,7 @@ #define TRACE_GROUP "wsbs" -#ifdef HAVE_WS + static void ws_bootstrap_event_handler(arm_event_s *event); static void ws_bootstrap_state_change(protocol_interface_info_entry_t *cur, icmp_state_t nwk_bootstrap_state); @@ -98,6 +101,8 @@ static ws_nud_table_entry_t *ws_nud_entry_discover(protocol_interface_info_entry static void ws_nud_entry_remove(protocol_interface_info_entry_t *cur, mac_neighbor_table_entry_t *entry_ptr); static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, void *user_data); +static void ws_address_registration_update(protocol_interface_info_entry_t *interface, const uint8_t addr[16]); + static void ws_bootstrap_candidate_table_reset(protocol_interface_info_entry_t *cur); static parent_info_t *ws_bootstrap_candidate_parent_get(struct protocol_interface_info_entry *cur, const uint8_t *addr, bool create); @@ -151,17 +156,28 @@ static void ws_bootstrap_neighbor_list_clean(struct protocol_interface_info_entr mac_neighbor_table_neighbor_list_clean(mac_neighbor_info(interface)); } +static void ws_address_reregister_trig(struct protocol_interface_info_entry *interface) +{ + if (interface->ws_info->aro_registration_timer == 0) { + interface->ws_info->aro_registration_timer = WS_NEIGHBOR_NUD_TIMEOUT; + } +} + static void ws_bootstrap_address_notification_cb(struct protocol_interface_info_entry *interface, const struct if_address_entry *addr, if_address_callback_t reason) { /* No need for LL address registration */ - if (addr->source == ADDR_SOURCE_UNKNOWN) { + if (addr->source == ADDR_SOURCE_UNKNOWN || !interface->ws_info) { return; } if (reason == ADDR_CALLBACK_DAD_COMPLETE) { //Trig Address Registartion only when Bootstrap is ready - if (interface->nwk_bootstrap_state == ER_BOOTSRAP_DONE && addr->source != ADDR_SOURCE_DHCP) { - tr_debug("Address registration %s", trace_ipv6(addr->address)); - rpl_control_register_address(interface, addr->address); + if (addr->source != ADDR_SOURCE_DHCP) { + if (interface->nwk_bootstrap_state == ER_BOOTSRAP_DONE) { + tr_debug("Address registration %s", trace_ipv6(addr->address)); + ws_address_registration_update(interface, addr->address); + } + ws_address_reregister_trig(interface); + } if (addr_ipv6_scope(addr->address, interface) > IPV6_SCOPE_LINK_LOCAL) { // at least ula address available inside mesh. @@ -188,12 +204,6 @@ static void ws_bootstrap_address_notification_cb(struct protocol_interface_info_ break; } } - } else if (reason == ADDR_CALLBACK_TIMER) { - if (addr->source != ADDR_SOURCE_DHCP) { - tr_debug("Address Re registration %s", trace_ipv6(addr->address)); - //Register - rpl_control_register_address(interface, addr->address); - } } } @@ -409,11 +419,10 @@ static fhss_ws_neighbor_timing_info_t *ws_get_neighbor_info(const fhss_api_t *ap } static void ws_bootstrap_llc_hopping_update(struct protocol_interface_info_entry *cur, const fhss_ws_configuration_t *fhss_configuration) { - memcpy(cur->ws_info->hopping_schdule.channel_mask, fhss_configuration->channel_mask, sizeof(uint32_t) * 8); cur->ws_info->hopping_schdule.uc_fixed_channel = fhss_configuration->unicast_fixed_channel; cur->ws_info->hopping_schdule.bc_fixed_channel = fhss_configuration->broadcast_fixed_channel; // Read UC channel function from WS info because FHSS might be temporarily configured to fixed channel during discovery. - cur->ws_info->hopping_schdule.uc_channel_function = cur->ws_info->fhss_uc_channel_function; + cur->ws_info->hopping_schdule.uc_channel_function = cur->ws_info->cfg->fhss.fhss_uc_channel_function; cur->ws_info->hopping_schdule.bc_channel_function = fhss_configuration->ws_bc_channel_function; cur->ws_info->hopping_schdule.fhss_bc_dwell_interval = fhss_configuration->fhss_bc_dwell_interval; cur->ws_info->hopping_schdule.fhss_broadcast_interval = fhss_configuration->fhss_broadcast_interval; @@ -421,65 +430,129 @@ static void ws_bootstrap_llc_hopping_update(struct protocol_interface_info_entry cur->ws_info->hopping_schdule.fhss_bsi = fhss_configuration->bsi; } +static uint8_t ws_generate_exluded_channel_list_from_active_channels(ws_excluded_channel_data_t *excluded_data, const uint32_t *selected_channel_mask, uint16_t number_of_channels) +{ + bool active_range = false; + + //Clear Old Data + memset(excluded_data, 0, sizeof(ws_excluded_channel_data_t)); + + for (uint8_t i = 0; i < number_of_channels; i++) { + if (selected_channel_mask[0 + (i / 32)] & (1 << (i % 32))) { + if (active_range) { + //Mark range stop here + active_range = false; + } + } else { + //Mark excluded channel + //Swap Order already here + excluded_data->channel_mask[0 + (i / 32)] |= 1 << (31 - (i % 32)); + excluded_data->excluded_channel_count++; + + if (excluded_data->excluded_range_length < WS_EXCLUDED_MAX_RANGE_TO_SEND) { + if (!active_range) { + excluded_data->excluded_range_length++; + active_range = true; + //Set start channel + excluded_data->exluded_range[excluded_data->excluded_range_length - 1].range_start = i; + } else { + excluded_data->exluded_range[excluded_data->excluded_range_length - 1].range_end = i; + } + } + } + } + + excluded_data->channel_mask_bytes_inline = ((number_of_channels + 7) / 8); + + uint8_t channel_plan = 0; + if (excluded_data->excluded_range_length == 0) { + excluded_data->excuded_channel_ctrl = WS_EXC_CHAN_CTRL_NONE; + } else if (excluded_data->excluded_range_length <= WS_EXCLUDED_MAX_RANGE_TO_SEND) { + + uint8_t range_length = (excluded_data->excluded_range_length * 4) + 3; + if (range_length <= ((number_of_channels + 7) / 8) + 6) { + excluded_data->excuded_channel_ctrl = WS_EXC_CHAN_CTRL_RANGE; + } else { + excluded_data->excuded_channel_ctrl = WS_EXC_CHAN_CTRL_BITMASK; + channel_plan = 1; + } + } else { + excluded_data->excuded_channel_ctrl = WS_EXC_CHAN_CTRL_BITMASK; + channel_plan = 1; + } + tr_debug("Excluded ctrl %u, exluded channel count %u, total domain channels %u", excluded_data->excuded_channel_ctrl, excluded_data->excluded_channel_count, number_of_channels); + return channel_plan; +} + +static void ws_fhss_configure_channel_masks(protocol_interface_info_entry_t *cur, fhss_ws_configuration_t *fhss_configuration) +{ + ws_generate_channel_list(fhss_configuration->channel_mask, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->hopping_schdule.regulatory_domain); + ws_generate_channel_list(fhss_configuration->unicast_channel_mask, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->hopping_schdule.regulatory_domain); + // using bitwise AND operation for user set channel mask to remove channels not allowed in this device + for (uint8_t n = 0; n < 8; n++) { + fhss_configuration->unicast_channel_mask[n] &= cur->ws_info->cfg->fhss.fhss_channel_mask[n]; + } + //Update Exluded channels + cur->ws_info->hopping_schdule.channel_plan = ws_generate_exluded_channel_list_from_active_channels(&cur->ws_info->hopping_schdule.excluded_channels, fhss_configuration->unicast_channel_mask, cur->ws_info->hopping_schdule.number_of_channels); +} + static int8_t ws_fhss_initialize(protocol_interface_info_entry_t *cur) { fhss_api_t *fhss_api = ns_sw_mac_get_fhss_api(cur->mac_api); + fhss_ws_configuration_t fhss_configuration; + memset(&fhss_configuration, 0, sizeof(fhss_ws_configuration_t)); if (!fhss_api) { // When FHSS doesn't exist yet, create one - fhss_ws_configuration_t fhss_configuration; - memset(&fhss_configuration, 0, sizeof(fhss_ws_configuration_t)); - ws_generate_channel_list(fhss_configuration.channel_mask, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->hopping_schdule.regulatory_domain); + ws_fhss_configure_channel_masks(cur, &fhss_configuration); - // using bitwise AND operation for user set channel mask to remove channels not allowed in this device - for (uint8_t n = 0; n < 8; n++) { - fhss_configuration.channel_mask[n] &= cur->ws_info->fhss_channel_mask[n]; - } - - fhss_configuration.fhss_uc_dwell_interval = cur->ws_info->fhss_uc_dwell_interval; - fhss_configuration.ws_uc_channel_function = (fhss_ws_channel_functions)cur->ws_info->fhss_uc_channel_function; - fhss_configuration.ws_bc_channel_function = (fhss_ws_channel_functions)cur->ws_info->fhss_bc_channel_function; - fhss_configuration.fhss_bc_dwell_interval = cur->ws_info->fhss_bc_dwell_interval; - fhss_configuration.fhss_broadcast_interval = cur->ws_info->fhss_bc_interval; + fhss_configuration.fhss_uc_dwell_interval = cur->ws_info->cfg->fhss.fhss_uc_dwell_interval; + fhss_configuration.ws_uc_channel_function = (fhss_ws_channel_functions)cur->ws_info->cfg->fhss.fhss_uc_channel_function; + fhss_configuration.ws_bc_channel_function = (fhss_ws_channel_functions)cur->ws_info->cfg->fhss.fhss_bc_channel_function; + fhss_configuration.fhss_bc_dwell_interval = cur->ws_info->cfg->fhss.fhss_bc_dwell_interval; + fhss_configuration.fhss_broadcast_interval = cur->ws_info->cfg->fhss.fhss_bc_interval; fhss_api = ns_fhss_ws_create(&fhss_configuration, cur->ws_info->fhss_timer_ptr); + if (!fhss_api) { return -1; } ns_sw_mac_fhss_register(cur->mac_api, fhss_api); } else { // Read defaults from the configuration to help FHSS testing - const fhss_ws_configuration_t *fhss_configuration = ns_fhss_ws_configuration_get(fhss_api); - if (!fhss_configuration) { + const fhss_ws_configuration_t *fhss_configuration_copy = ns_fhss_ws_configuration_get(fhss_api); + if (!fhss_configuration_copy) { // no configuration set yet return 0; } - memcpy(cur->ws_info->fhss_channel_mask, fhss_configuration->channel_mask, sizeof(uint32_t) * 8); - cur->ws_info->fhss_uc_channel_function = fhss_configuration->ws_uc_channel_function; - cur->ws_info->fhss_bc_channel_function = fhss_configuration->ws_bc_channel_function; - cur->ws_info->fhss_bc_dwell_interval = fhss_configuration->fhss_bc_dwell_interval; - cur->ws_info->fhss_bc_interval = fhss_configuration->fhss_broadcast_interval; - cur->ws_info->fhss_uc_dwell_interval = fhss_configuration->fhss_uc_dwell_interval; - cur->ws_info->fhss_bc_fixed_channel = fhss_configuration->broadcast_fixed_channel; - cur->ws_info->fhss_uc_fixed_channel = fhss_configuration->unicast_fixed_channel; + fhss_configuration = *fhss_configuration_copy; + //Overwrite domain channel setup this will over write a default 35 channel + int num_of_channels = channel_list_count_channels(fhss_configuration_copy->unicast_channel_mask); + cur->ws_info->hopping_schdule.number_of_channels = (uint8_t) num_of_channels; + memcpy(cur->ws_info->cfg->fhss.fhss_channel_mask, fhss_configuration_copy->unicast_channel_mask, sizeof(uint32_t) * 8); + cur->ws_info->cfg->fhss.fhss_uc_channel_function = fhss_configuration_copy->ws_uc_channel_function; + cur->ws_info->cfg->fhss.fhss_bc_channel_function = fhss_configuration_copy->ws_bc_channel_function; + cur->ws_info->cfg->fhss.fhss_bc_dwell_interval = fhss_configuration_copy->fhss_bc_dwell_interval; + cur->ws_info->cfg->fhss.fhss_bc_interval = fhss_configuration_copy->fhss_broadcast_interval; + cur->ws_info->cfg->fhss.fhss_uc_dwell_interval = fhss_configuration_copy->fhss_uc_dwell_interval; + cur->ws_info->cfg->fhss.fhss_bc_fixed_channel = fhss_configuration_copy->broadcast_fixed_channel; + cur->ws_info->cfg->fhss.fhss_uc_fixed_channel = fhss_configuration_copy->unicast_fixed_channel; + ws_fhss_configure_channel_masks(cur, &fhss_configuration); + ns_fhss_ws_configuration_set(fhss_api, &fhss_configuration); } + return 0; } + static int8_t ws_fhss_set_defaults(protocol_interface_info_entry_t *cur, fhss_ws_configuration_t *fhss_configuration) { - fhss_configuration->fhss_uc_dwell_interval = cur->ws_info->fhss_uc_dwell_interval; - fhss_configuration->ws_uc_channel_function = (fhss_ws_channel_functions)cur->ws_info->fhss_uc_channel_function; - fhss_configuration->ws_bc_channel_function = (fhss_ws_channel_functions)cur->ws_info->fhss_bc_channel_function; - fhss_configuration->fhss_bc_dwell_interval = cur->ws_info->fhss_bc_dwell_interval; - fhss_configuration->fhss_broadcast_interval = cur->ws_info->fhss_bc_interval; - if (cur->ws_info->fhss_uc_fixed_channel != 0xffff) { - fhss_configuration->unicast_fixed_channel = cur->ws_info->fhss_uc_fixed_channel; - } - fhss_configuration->broadcast_fixed_channel = cur->ws_info->fhss_bc_fixed_channel; - ws_generate_channel_list(fhss_configuration->channel_mask, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->hopping_schdule.regulatory_domain); - - // using bitwise AND operation for user set channel mask to remove channels not allowed in this device - for (uint8_t n = 0; n < 8; n++) { - fhss_configuration->channel_mask[n] &= cur->ws_info->fhss_channel_mask[n]; + fhss_configuration->fhss_uc_dwell_interval = cur->ws_info->cfg->fhss.fhss_uc_dwell_interval; + fhss_configuration->ws_uc_channel_function = (fhss_ws_channel_functions)cur->ws_info->cfg->fhss.fhss_uc_channel_function; + fhss_configuration->ws_bc_channel_function = (fhss_ws_channel_functions)cur->ws_info->cfg->fhss.fhss_bc_channel_function; + fhss_configuration->fhss_bc_dwell_interval = cur->ws_info->cfg->fhss.fhss_bc_dwell_interval; + fhss_configuration->fhss_broadcast_interval = cur->ws_info->cfg->fhss.fhss_bc_interval; + if (cur->ws_info->cfg->fhss.fhss_uc_fixed_channel != 0xffff) { + fhss_configuration->unicast_fixed_channel = cur->ws_info->cfg->fhss.fhss_uc_fixed_channel; } + fhss_configuration->broadcast_fixed_channel = cur->ws_info->cfg->fhss.fhss_bc_fixed_channel; return 0; } static int8_t ws_fhss_border_router_configure(protocol_interface_info_entry_t *cur) @@ -492,6 +565,7 @@ static int8_t ws_fhss_border_router_configure(protocol_interface_info_entry_t *c memcpy(&fhss_configuration, ns_fhss_ws_configuration_get(cur->ws_info->fhss_api), sizeof(fhss_ws_configuration_t)); } ws_fhss_set_defaults(cur, &fhss_configuration); + ws_fhss_configure_channel_masks(cur, &fhss_configuration); ns_fhss_ws_configuration_set(cur->ws_info->fhss_api, &fhss_configuration); ws_bootstrap_llc_hopping_update(cur, &fhss_configuration); @@ -515,17 +589,19 @@ static int8_t ws_fhss_configure(protocol_interface_info_entry_t *cur, bool disco if (ns_fhss_ws_configuration_get(cur->ws_info->fhss_api)) { memcpy(&fhss_configuration, ns_fhss_ws_configuration_get(cur->ws_info->fhss_api), sizeof(fhss_ws_configuration_t)); + ws_fhss_set_defaults(cur, &fhss_configuration); + ws_fhss_configure_channel_masks(cur, &fhss_configuration); } // Discovery is done using fixed channel if (discovery) { fhss_configuration.ws_uc_channel_function = WS_FIXED_CHANNEL; } else { - fhss_configuration.ws_uc_channel_function = (fhss_ws_channel_functions)cur->ws_info->fhss_uc_channel_function; + fhss_configuration.ws_uc_channel_function = (fhss_ws_channel_functions)cur->ws_info->cfg->fhss.fhss_uc_channel_function; } fhss_configuration.ws_bc_channel_function = WS_FIXED_CHANNEL; fhss_configuration.fhss_broadcast_interval = 0; - uint8_t tmp_uc_fixed_channel = ws_randomize_fixed_channel(cur->ws_info->fhss_uc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels); - uint8_t tmp_bc_fixed_channel = ws_randomize_fixed_channel(cur->ws_info->fhss_bc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels); + uint8_t tmp_uc_fixed_channel = ws_randomize_fixed_channel(cur->ws_info->cfg->fhss.fhss_uc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels); + uint8_t tmp_bc_fixed_channel = ws_randomize_fixed_channel(cur->ws_info->cfg->fhss.fhss_bc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels); fhss_configuration.unicast_fixed_channel = tmp_uc_fixed_channel; fhss_configuration.broadcast_fixed_channel = tmp_bc_fixed_channel; ns_fhss_ws_configuration_set(cur->ws_info->fhss_api, &fhss_configuration); @@ -577,12 +653,12 @@ static void ws_bootstrap_primary_parent_set(struct protocol_interface_info_entry fhss_configuration.ws_bc_channel_function = (fhss_ws_channel_functions)neighbor_info->ws_neighbor->fhss_data.bc_timing_info.broadcast_channel_function; if (fhss_configuration.ws_bc_channel_function == WS_FIXED_CHANNEL) { cur->ws_info->hopping_schdule.bc_fixed_channel = neighbor_info->ws_neighbor->fhss_data.bc_timing_info.fixed_channel; - cur->ws_info->fhss_bc_fixed_channel = neighbor_info->ws_neighbor->fhss_data.bc_timing_info.fixed_channel; + cur->ws_info->cfg->fhss.fhss_bc_fixed_channel = neighbor_info->ws_neighbor->fhss_data.bc_timing_info.fixed_channel; } fhss_configuration.bsi = neighbor_info->ws_neighbor->fhss_data.bc_timing_info.broadcast_schedule_id; fhss_configuration.fhss_bc_dwell_interval = neighbor_info->ws_neighbor->fhss_data.bc_timing_info.broadcast_dwell_interval; fhss_configuration.fhss_broadcast_interval = neighbor_info->ws_neighbor->fhss_data.bc_timing_info.broadcast_interval; - fhss_configuration.broadcast_fixed_channel = cur->ws_info->fhss_bc_fixed_channel; + fhss_configuration.broadcast_fixed_channel = cur->ws_info->cfg->fhss.fhss_bc_fixed_channel; neighbor_info->ws_neighbor->synch_done = true; } @@ -822,6 +898,7 @@ void ws_bootstrap_configuration_reset(protocol_interface_info_entry_t *cur) cur->ws_info->trickle_pa_running = false; cur->ws_info->trickle_pcs_running = false; cur->ws_info->trickle_pc_running = false; + cur->ws_info->trickle_pc_consistency_block_period = 0; //cur->mac_security_key_usage_update_cb = ws_management_mac_security_key_update_cb; return; @@ -896,12 +973,54 @@ static parent_info_t *ws_bootstrap_candidate_parent_get_best(protocol_interface_ return ns_list_get_first(&cur->ws_info->parent_list_reserved); } +static void ws_bootstrap_decode_exclude_range_to_mask_by_range(void *mask_buffer, ws_excluded_channel_range_t *range_info, uint16_t number_of_channels) +{ + uint16_t range_start, range_stop; + uint8_t mask_index = 0; + //uint8_t channel_index = 0; + uint8_t *range_ptr = range_info->range_start; + uint32_t *mask_ptr = mask_buffer; + while (range_info->number_of_range) { + range_start = common_read_16_bit_inverse(range_ptr); + range_ptr += 2; + range_stop = common_read_16_bit_inverse(range_ptr); + range_ptr += 2; + range_info->number_of_range--; + for (uint16_t channel = 0; channel < number_of_channels; channel++) { + + if (channel && (channel % 32 == 0)) { + mask_index++; + //channel_index = 0; + } + if (channel >= range_start && channel <= range_stop) { + //mask_ptr[mask_index] |= 1 << (31 - channel_index); + mask_ptr[0 + (channel / 32)] |= 1 << (31 - (channel % 32)); + } else if (channel > range_stop) { + break; + } + } + } +} + static void ws_bootstrap_candidate_parent_store(parent_info_t *parent, const struct mcps_data_ind_s *data, ws_utt_ie_t *ws_utt, ws_us_ie_t *ws_us, ws_pan_information_t *pan_information) { parent->ws_utt = *ws_utt; // Saved from unicast IE parent->ws_us = *ws_us; + //copy excluded channel here if it is inline + if (ws_us->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_RANGE) { + memset(parent->excluded_channel_data, 0, 32); + //Decode Range to mask here + ws_bootstrap_decode_exclude_range_to_mask_by_range(parent->excluded_channel_data, &parent->ws_us.excluded_channels.range, 256); + parent->ws_us.excluded_channels.mask.channel_mask = parent->excluded_channel_data; + parent->ws_us.excluded_channels.mask.mask_len_inline = 32; + parent->ws_us.excluded_channel_ctrl = WS_EXC_CHAN_CTRL_BITMASK; + } else if (ws_us->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_BITMASK) { + parent->ws_us.excluded_channels.mask.channel_mask = parent->excluded_channel_data; + memcpy(parent->excluded_channel_data, ws_us->excluded_channels.mask.channel_mask, ws_us->excluded_channels.mask.mask_len_inline); + } + // Saved from Pan information, do not overwrite pan_version as it is not valid here parent->pan_information.pan_size = pan_information->pan_size; parent->pan_information.routing_cost = pan_information->routing_cost; @@ -1088,6 +1207,13 @@ static void ws_bootstrap_pan_advertisement_analyse(struct protocol_interface_inf return; } + if (ws_us->excluded_channel_ctrl) { + //Validate that we can storage data + if (ws_us->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_BITMASK && ws_us->excluded_channels.mask.mask_len_inline > 32) { + return; + } + } + // Check pan flags so that it is valid if (!pan_information.rpl_routing_method) { // NOT RPL routing @@ -1130,9 +1256,9 @@ static void ws_bootstrap_pan_advertisement_analyse(struct protocol_interface_inf if (rpl_control_is_dodag_parent(cur, ll_address)) { // automatic network size adjustment learned - if (cur->ws_info->network_size_config == NETWORK_SIZE_AUTOMATIC && + if (cur->ws_info->cfg->gen.network_size == NETWORK_SIZE_AUTOMATIC && cur->ws_info->pan_information.pan_size != pan_information.pan_size) { - ws_common_network_size_configure(cur, pan_information.pan_size); + ws_cfg_network_size_configure(cur, pan_information.pan_size); } cur->ws_info->pan_information.pan_size = pan_information.pan_size; @@ -1247,8 +1373,12 @@ static void ws_bootstrap_pan_config_analyse(struct protocol_interface_info_entry if (cur->ws_info->configuration_learned) { tr_info("PAN Config analyse own:%d, heard:%d", cur->ws_info->pan_information.pan_version, pan_version); if (cur->ws_info->pan_information.pan_version == pan_version) { - // Same version heard so it is consistent - trickle_consistent_heard(&cur->ws_info->trickle_pan_config); + //Check if Trgigle have been resetted in short time skip this then + if (cur->ws_info->trickle_pc_consistency_block_period == 0) { + // Same version heard so it is consistent + trickle_consistent_heard(&cur->ws_info->trickle_pan_config); + } + if (neighbour_pointer_valid && neighbor_info.neighbor->link_role == PRIORITY_PARENT_NEIGHBOUR) { ws_bootstrap_primary_parent_set(cur, &neighbor_info, WS_PARENT_SOFT_SYNCH); } @@ -1264,6 +1394,7 @@ static void ws_bootstrap_pan_config_analyse(struct protocol_interface_info_entry // older version heard ignoring the message return; } + cur->ws_info->trickle_pc_consistency_block_period = WS_CONFIG_CONSISTENT_FILTER_PERIOD; } } @@ -1278,7 +1409,7 @@ static void ws_bootstrap_pan_config_analyse(struct protocol_interface_info_entry tr_info("Updated PAN configuration own:%d, heard:%d", cur->ws_info->pan_information.pan_version, pan_version); // restart PAN version timer - cur->ws_info->pan_version_timeout_timer = ws_common_version_timeout_get(cur->ws_info->network_size_config); + cur->ws_info->pan_timeout_timer = cur->ws_info->cfg->timing.pan_timeout; cur->ws_info->pan_information.pan_version = pan_version; ws_pae_controller_gtk_hash_update(cur, gtkhash_ptr); @@ -1359,7 +1490,20 @@ static bool ws_channel_plan_one_compare(ws_channel_plan_one_t *rx_plan, ws_hoppi return true; } +bool ws_bootstrap_validate_channel_plan(ws_us_ie_t *ws_us, struct protocol_interface_info_entry *cur) +{ + if (ws_us->channel_plan == 0) { + if (!ws_channel_plan_zero_compare(&ws_us->plan.zero, &cur->ws_info->hopping_schdule)) { + return false; + } + } else if (ws_us->channel_plan == 1) { + if (!ws_channel_plan_one_compare(&ws_us->plan.one, &cur->ws_info->hopping_schdule)) { + return false; + } + } + return true; +} static void ws_bootstrap_asynch_ind(struct protocol_interface_info_entry *cur, const struct mcps_data_ind_s *data, const struct mcps_data_ie_list *ie_ext, uint8_t message_type) @@ -1375,7 +1519,7 @@ static void ws_bootstrap_asynch_ind(struct protocol_interface_info_entry *cur, c case WS_FT_PAN_ADVERT_SOL: case WS_FT_PAN_CONF_SOL: //Check Network Name - if (!ws_bootstrap_network_name_matches(ie_ext, cur->ws_info->network_name)) { + if (!ws_bootstrap_network_name_matches(ie_ext, cur->ws_info->cfg->gen.network_name)) { // Not in our network return; } @@ -1399,21 +1543,10 @@ static void ws_bootstrap_asynch_ind(struct protocol_interface_info_entry *cur, c return; } - //Compare Unicast channel Plan - if (ws_us.channel_plan != cur->ws_info->hopping_schdule.channel_plan) { + if (!ws_bootstrap_validate_channel_plan(&ws_us, cur)) { return; } - if (ws_us.channel_plan == 0) { - if (!ws_channel_plan_zero_compare(&ws_us.plan.zero, &cur->ws_info->hopping_schdule)) { - return; - } - } else if (ws_us.channel_plan == 1) { - if (!ws_channel_plan_one_compare(&ws_us.plan.one, &cur->ws_info->hopping_schdule)) { - return; - } - } - //Handle Message's switch (message_type) { case WS_FT_PAN_ADVERT: @@ -1507,13 +1640,7 @@ static void ws_bootstrap_neighbor_table_clean(struct protocol_interface_info_ent //Read current timestamp uint32_t time_from_last_unicast_shedule = ws_time_from_last_unicast_traffic(current_time_stamp, ws_neighbor); - uint32_t min_timeout; - if (interface->ws_info->network_size_config == NETWORK_SIZE_LARGE) { - min_timeout = WS_NEIGHBOR_TEMPORARY_LINK_MIN_TIMEOUT_LARGE; - } else { - min_timeout = WS_NEIGHBOR_TEMPORARY_LINK_MIN_TIMEOUT_SMALL; - } - if (time_from_last_unicast_shedule > min_timeout) { + if (time_from_last_unicast_shedule > interface->ws_info->cfg->timing.temp_link_min_timeout) { //Accept only Enough Old Device if (!neighbor_entry_ptr) { //Accept first compare @@ -1615,12 +1742,19 @@ static bool ws_neighbor_entry_nud_notify(mac_neighbor_table_entry_t *entry_ptr, if (time_from_start > WS_NEIGHBOR_NUD_TIMEOUT) { - if (ipv6_neighbour_has_registered_by_eui64(&cur->ipv6_neighbour_cache, entry_ptr->mac64)) { - // This is our child with valid ARO registration Change link timeout to future we check at 2 minute intervals - entry_ptr->lifetime = entry_ptr->lifetime + 120; - if (entry_ptr->lifetime > entry_ptr->link_lifetime) { - entry_ptr->lifetime = entry_ptr->link_lifetime; - } + /* For parents ARO registration is sent in link timeout times + * For candidate parents NUD is needed + * For children NUD is sent only at very close to end + */ + if (ipv6_neighbour_has_registered_by_eui64(&cur->ipv6_neighbour_cache, entry_ptr->mac64) && + (time_from_start < WS_NEIGHBOR_NUD_TIMEOUT * 1.8)) { + /* This is our child with valid ARO registration send NUD if we are close to delete + * + * if ARO was received link is considered active so this is only in case of very long ARO registration times + * + * 1.8 means with link timeout of 30 minutes that NUD is sent 6 minutes before timeout + * + */ return false; } @@ -1766,6 +1900,11 @@ int ws_bootstrap_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode) goto init_fail; } + if (ws_cfg_settings_interface_set(cur) < 0) { + ret_val = -4; + goto init_fail; + } + if (ws_bootstrap_tasklet_init(cur) != 0) { ret_val = -4; goto init_fail; @@ -1786,6 +1925,10 @@ int ws_bootstrap_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode) ret_val = -4; goto init_fail; } + if (ws_pae_controller_configure(cur, &cur->ws_info->cfg->sec_timer, &cur->ws_info->cfg->sec_prot) < 0) { + ret_val = -4; + goto init_fail; + } //Init EAPOL PDU handler and register it to MPX if (ws_eapol_pdu_init(cur) < 0) { @@ -1817,19 +1960,13 @@ int ws_bootstrap_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode) // Set the default parameters for MPL cur->mpl_proactive_forwarding = true; - cur->mpl_data_trickle_params.Imin = MPL_MS_TO_TICKS(DATA_MESSAGE_IMIN); - cur->mpl_data_trickle_params.Imax = MPL_MS_TO_TICKS(DATA_MESSAGE_IMAX); - cur->mpl_data_trickle_params.TimerExpirations = DATA_MESSAGE_TIMER_EXPIRATIONS; - cur->mpl_data_trickle_params.k = 8; - // Specification is ruling out the compression mode, but we are now doing it. cur->mpl_seed = true; cur->mpl_seed_id_mode = MULTICAST_MPL_SEED_ID_IPV6_SRC_FOR_DOMAIN; - cur->mpl_seed_set_entry_lifetime = MPL_SEED_SET_ENTRY_TIMEOUT; cur->mpl_control_trickle_params.TimerExpirations = 0; - mpl_domain_create(cur, ADDR_ALL_MPL_FORWARDERS, NULL, MULTICAST_MPL_SEED_ID_DEFAULT, -1, 0, NULL, NULL); + cur->mpl_domain = mpl_domain_create(cur, ADDR_ALL_MPL_FORWARDERS, NULL, MULTICAST_MPL_SEED_ID_DEFAULT, -1, 0, NULL, NULL); addr_add_group(cur, ADDR_REALM_LOCAL_ALL_NODES); addr_add_group(cur, ADDR_REALM_LOCAL_ALL_ROUTERS); @@ -1858,9 +1995,26 @@ int ws_bootstrap_restart(int8_t interface_id) return 0; } +int ws_bootstrap_restart_delayed(int8_t interface_id) +{ + protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface_id); + if (!cur || !cur->ws_info) { + return -1; + } + ws_bootstrap_state_change(cur, ER_WAIT_RESTART); + cur->bootsrap_state_machine_cnt = 3; + return 0; +} + int ws_bootstrap_set_rf_config(protocol_interface_info_entry_t *cur, phy_rf_channel_configuration_s rf_configs) { mlme_set_t set_request; + // Set MAC mode + phy_802_15_4_mode_t mac_mode = IEEE_802_15_4G_2012; + set_request.attr = mac802_15_4Mode; + set_request.value_pointer = &mac_mode; + set_request.value_size = sizeof(phy_802_15_4_mode_t); + cur->mac_api->mlme_req(cur->mac_api, MLME_SET, &set_request); // Set RF configuration set_request.attr = macRfConfiguration; set_request.value_pointer = &rf_configs; @@ -1898,6 +2052,19 @@ int ws_bootstrap_aro_failure(protocol_interface_info_entry_t *cur, const uint8_t return 0; } +static int ws_bootstrap_set_domain_rf_config(protocol_interface_info_entry_t *cur) +{ + phy_rf_channel_configuration_s rf_configs; + rf_configs.channel_0_center_frequency = (uint32_t)cur->ws_info->hopping_schdule.ch0_freq * 100000; + rf_configs.channel_spacing = ws_decode_channel_spacing(cur->ws_info->hopping_schdule.channel_spacing); + rf_configs.datarate = ws_get_datarate_using_operating_mode(cur->ws_info->hopping_schdule.operating_mode); + rf_configs.modulation_index = ws_get_modulation_index_using_operating_mode(cur->ws_info->hopping_schdule.operating_mode); + rf_configs.modulation = M_2FSK; + rf_configs.number_of_channels = cur->ws_info->hopping_schdule.number_of_channels; + ws_bootstrap_set_rf_config(cur, rf_configs); + return 0; +} + static void ws_bootstrap_mac_activate(protocol_interface_info_entry_t *cur, uint16_t channel, uint16_t panid, bool coordinator) { mlme_start_t start_req; @@ -1928,7 +2095,7 @@ static void ws_bootstrap_fhss_activate(protocol_interface_info_entry_t *cur) mac_helper_pib_boolean_set(cur, macRxOnWhenIdle, true); cur->lowpan_info &= ~INTERFACE_NWK_CONF_MAC_RX_OFF_IDLE; ws_bootstrap_mac_security_enable(cur); - ws_bootstrap_mac_activate(cur, cur->ws_info->fhss_uc_fixed_channel, cur->ws_info->network_pan_id, true); + ws_bootstrap_mac_activate(cur, cur->ws_info->cfg->fhss.fhss_uc_fixed_channel, cur->ws_info->network_pan_id, true); return; } @@ -1986,10 +2153,33 @@ static void ws_set_fhss_hop(protocol_interface_info_entry_t *cur) tr_debug("own hop: %u, own rank: %u, rank inc: %u", own_hop, own_rank, rank_inc); } -static void ws_address_registration_update(protocol_interface_info_entry_t *interface) +static void ws_address_registration_update(protocol_interface_info_entry_t *interface, const uint8_t addr[16]) +{ + rpl_control_register_address(interface, addr); + // Timer is used only to track full registrations + + if (addr != NULL && interface->ws_info->aro_registration_timer) { + // Single address update and timer is running + return; + } + + if (interface->ws_info->aro_registration_timer == 0) { + // Timer expired and check if we have valid address to register + ns_list_foreach(if_address_entry_t, address, &interface->ip_addresses) { + if (!addr_is_ipv6_link_local(address->address)) { + // We have still valid addresses let the timer run for next period + tr_info("ARO registration timer start"); + interface->ws_info->aro_registration_timer = WS_NEIGHBOR_NUD_TIMEOUT; + return; + } + } + } +} + +static void ws_address_parent_update(protocol_interface_info_entry_t *interface) { - rpl_control_register_address(interface, NULL); tr_info("RPL parent update ... register ARO"); + ws_address_registration_update(interface, NULL); } static void ws_bootstrap_rpl_callback(rpl_event_t event, void *handle) @@ -2014,9 +2204,13 @@ static void ws_bootstrap_rpl_callback(rpl_event_t event, void *handle) // Set both own port and border router port to 10253 ws_eapol_relay_start(cur, EAPOL_RELAY_SOCKET_PORT, dodag_info.dodag_id, EAPOL_RELAY_SOCKET_PORT); // Set network information to PAE - ws_pae_controller_nw_info_set(cur, cur->ws_info->network_pan_id, cur->ws_info->network_name); + ws_pae_controller_nw_info_set(cur, cur->ws_info->network_pan_id, cur->ws_info->cfg->gen.network_name); // Network key is valid ws_pae_controller_nw_key_valid(cur); + + // After successful DAO ACK connection to border router is verified + cur->ws_info->pan_timeout_timer = cur->ws_info->cfg->timing.pan_timeout; + } ws_set_fhss_hop(cur); @@ -2031,7 +2225,7 @@ static void ws_bootstrap_rpl_callback(rpl_event_t event, void *handle) */ } else if (event == RPL_EVENT_DAO_PARENT_ADD) { - ws_address_registration_update(cur); + ws_address_parent_update(cur); } cur->ws_info->rpl_state = event; tr_info("RPL event %d", event); @@ -2046,7 +2240,7 @@ static void ws_dhcp_client_global_adress_cb(int8_t interface, uint8_t dhcp_addr[ if (register_status) { protocol_interface_info_entry_t *cur = protocol_stack_interface_info_get_by_id(interface); if (cur) { - rpl_control_register_address(cur, prefix); + ws_address_reregister_trig(cur); } } else { //Delete dhcpv6 client @@ -2114,13 +2308,18 @@ static void ws_rpl_prefix_callback(prefix_entry_t *prefix, void *handle, uint8_t static bool ws_rpl_candidate_soft_filtering(protocol_interface_info_entry_t *cur, struct rpl_instance *instance) { + //If bootstrap active we not need any candidate filtering + if ((cur->lowpan_info & INTERFACE_NWK_BOOTSRAP_ACTIVE) && (ws_info(cur)->cfg->gen.network_size == NETWORK_SIZE_CERTIFICATE)) { + return true; + } + //Already many candidates - if (rpl_control_candidate_list_size(cur, instance) > cur->ws_info->rpl_parent_candidate_max) { + if (rpl_control_candidate_list_size(cur, instance) > cur->ws_info->cfg->rpl.rpl_parent_candidate_max) { return false; } //Already enough selected candidates - if (rpl_control_selected_parent_count(cur, instance) >= cur->ws_info->rpl_selected_parent_max) { + if (rpl_control_selected_parent_count(cur, instance) >= cur->ws_info->cfg->rpl.rpl_selected_parent_max) { return false; } @@ -2267,12 +2466,20 @@ static void ws_bootstrap_rpl_activate(protocol_interface_info_entry_t *cur) rpl_control_process_routes(protocol_6lowpan_rpl_domain, false); // Wi-SUN assumes that no default route needed rpl_control_request_parent_link_confirmation(true); rpl_control_set_dio_multicast_min_config_advertisment_count(WS_MIN_DIO_MULTICAST_CONFIG_ADVERTISMENT_COUNT); + rpl_control_set_address_registration_timeout((WS_NEIGHBOR_LINK_TIMEOUT / 60) + 1); rpl_control_set_dao_retry_count(WS_MAX_DAO_RETRIES); rpl_control_set_initial_dao_ack_wait(WS_MAX_DAO_INITIAL_TIMEOUT); rpl_control_set_mrhof_parent_set_size(WS_MAX_PARENT_SET_COUNT); if (cur->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { rpl_control_set_memory_limits(WS_NODE_RPL_SOFT_MEM_LIMIT, WS_NODE_RPL_HARD_MEM_LIMIT); } + // Set RPL Link ETX Validation Threshold to 2.5 - 33.0 + // This setup will set ETX 0x800 to report ICMP error 18% probability + // When ETX start go over 0x280 forward dropping probability start increase linear to 100% at 0x2100 + rpl_policy_forward_link_etx_threshold_set(0x280, 0x2100); + + // Set the minimum target refresh to sen DAO registrations before pan timeout + rpl_control_set_minimum_dao_target_refresh(WS_RPL_DAO_MAX_TIMOUT); cur->ws_info->rpl_state = 0xff; // Set invalid state and learn from event } @@ -2280,7 +2487,7 @@ static void ws_bootstrap_rpl_activate(protocol_interface_info_entry_t *cur) static void ws_bootstrap_network_start(protocol_interface_info_entry_t *cur) { //Set Network names, Pan information configure, hopping schedule & GTKHash - ws_llc_set_network_name(cur, (uint8_t *)cur->ws_info->network_name, strlen(cur->ws_info->network_name)); + ws_llc_set_network_name(cur, (uint8_t *)cur->ws_info->cfg->gen.network_name, strlen(cur->ws_info->cfg->gen.network_name)); ws_llc_set_pan_information_pointer(cur, &cur->ws_info->pan_information); } @@ -2289,11 +2496,12 @@ static void ws_bootstrap_network_discovery_configure(protocol_interface_info_ent // Reset information to defaults cur->ws_info->network_pan_id = 0xffff; - ws_common_regulatory_domain_config(cur); + ws_common_regulatory_domain_config(cur, &cur->ws_info->hopping_schdule); + ws_bootstrap_set_domain_rf_config(cur); ws_fhss_configure(cur, true); //Set Network names, Pan information configure, hopping schedule & GTKHash - ws_llc_set_network_name(cur, (uint8_t *)cur->ws_info->network_name, strlen(cur->ws_info->network_name)); + ws_llc_set_network_name(cur, (uint8_t *)cur->ws_info->cfg->gen.network_name, strlen(cur->ws_info->cfg->gen.network_name)); } @@ -2302,12 +2510,14 @@ static void ws_bootstrap_advertise_start(protocol_interface_info_entry_t *cur) cur->ws_info->trickle_pa_running = true; trickle_start(&cur->ws_info->trickle_pan_advertisement, &cur->ws_info->trickle_params_pan_discovery); cur->ws_info->trickle_pc_running = true; + cur->ws_info->trickle_pc_consistency_block_period = 0; trickle_start(&cur->ws_info->trickle_pan_config, &cur->ws_info->trickle_params_pan_discovery); } static void ws_bootstrap_pan_version_increment(protocol_interface_info_entry_t *cur) { - cur->ws_info->pan_version_timer = 1; + (void)cur; + ws_bbr_pan_version_increase(cur); } // Start network scan @@ -2319,7 +2529,7 @@ static void ws_bootstrap_start_discovery(protocol_interface_info_entry_t *cur) ws_bootstrap_state_change(cur, ER_ACTIVE_SCAN); cur->nwk_nd_re_scan_count = 0; cur->ws_info->configuration_learned = false; - cur->ws_info->pan_version_timeout_timer = 0; + cur->ws_info->pan_timeout_timer = 0; // Clear learned neighbours ws_bootstrap_neighbor_list_clean(cur); @@ -2369,7 +2579,7 @@ static void ws_bootstrap_start_discovery(protocol_interface_info_entry_t *cur) static void ws_bootstrap_start_authentication(protocol_interface_info_entry_t *cur) { // Set PAN ID and network name to controller - ws_pae_controller_nw_info_set(cur, cur->ws_info->network_pan_id, cur->ws_info->network_name); + ws_pae_controller_nw_info_set(cur, cur->ws_info->network_pan_id, cur->ws_info->cfg->gen.network_name); ws_pae_controller_authenticate(cur); } @@ -2431,6 +2641,12 @@ static void ws_bootstrap_authentication_completed(protocol_interface_info_entry_ ws_bootstrap_candidate_parent_free(cur, target_eui_64); // Go back for network scanning ws_bootstrap_state_change(cur, ER_ACTIVE_SCAN); + + // Start PAS interval between imin - imax. + cur->ws_info->trickle_pas_running = true; + trickle_start(&cur->ws_info->trickle_pan_advertisement_solicit, &cur->ws_info->trickle_params_pan_discovery); + + // Parent selection is made before imin/2 so if there is parent candidates solicit is not sent cur->bootsrap_state_machine_cnt = randLIB_get_random_in_range(10, cur->ws_info->trickle_params_pan_discovery.Imin >> 1); tr_info("Making parent selection in %u s", (cur->bootsrap_state_machine_cnt / 10)); } else { @@ -2467,10 +2683,15 @@ static void ws_bootstrap_rpl_scan_start(protocol_interface_info_entry_t *cur) // routers wait until RPL root is contacted ws_bootstrap_state_change(cur, ER_RPL_SCAN); //For Large network and medium shuold do passive scan - if (cur->ws_info->network_size_config == NETWORK_SIZE_LARGE || cur->ws_info->network_size_config == NETWORK_SIZE_MEDIUM) { + if (cur->ws_info->cfg->gen.network_size > NETWORK_SIZE_SMALL) { // Set timeout for check to 30 -60 seconds cur->bootsrap_state_machine_cnt = randLIB_get_random_in_range(WS_RPL_DIS_INITIAL_TIMEOUT / 2, WS_RPL_DIS_INITIAL_TIMEOUT); } + /* While in Join State 4, if a non Border Router determines it has been unable to communicate with the PAN Border + * Router for an interval of PAN_TIMEOUT, a node MUST assume failure of the PAN Border Router and MUST + * Transition to Join State 1 + */ + cur->ws_info->pan_timeout_timer = cur->ws_info->cfg->timing.pan_timeout; } /* @@ -2505,9 +2726,9 @@ void ws_bootstrap_configuration_trickle_reset(protocol_interface_info_entry_t *c static void ws_set_asynch_channel_list(protocol_interface_info_entry_t *cur, asynch_request_t *async_req) { memset(&async_req->channel_list, 0, sizeof(channel_list_s)); - if (cur->ws_info->fhss_uc_channel_function == WS_FIXED_CHANNEL) { + if (cur->ws_info->cfg->fhss.fhss_uc_channel_function == WS_FIXED_CHANNEL) { //SET 1 Channel only - uint16_t channel_number = cur->ws_info->fhss_uc_fixed_channel; + uint16_t channel_number = cur->ws_info->cfg->fhss.fhss_uc_fixed_channel; async_req->channel_list.channel_mask[0 + (channel_number / 32)] = (1 << (channel_number % 32)); } else { ws_generate_channel_list(async_req->channel_list.channel_mask, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->hopping_schdule.regulatory_domain); @@ -2581,6 +2802,10 @@ static uint16_t ws_bootstrap_routing_cost_calculate(protocol_interface_info_entr //Scale to 128 based ETX (local read retur 0x100 - 0xffff etx = etx >> 1; } + // Make the 0xffff as maximum value + if (ws_neighbor->routing_cost + etx > 0xffff) { + return 0xffff; + } return ws_neighbor->routing_cost + etx; } @@ -2685,27 +2910,41 @@ static void ws_bootstrap_event_handler(arm_event_s *event) cur->ws_info->pending_key_index_info.state = NO_PENDING_PROCESS; cur->mac_parameters->mac_default_key_index = 0; + // Clear parent blacklist + blacklist_clear(); + // All trickle timers stopped to allow entry from any state cur->ws_info->trickle_pa_running = false; cur->ws_info->trickle_pc_running = false; cur->ws_info->trickle_pas_running = false; cur->ws_info->trickle_pcs_running = false; + cur->ws_info->trickle_pc_consistency_block_period = 0; if (cur->bootsrap_mode == ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER) { tr_info("Border router start network"); + if (!ws_bbr_ready_to_start(cur)) { // Wi-SUN not started yet we wait for Border router permission ws_bootstrap_state_change(cur, ER_WAIT_RESTART); cur->nwk_nd_re_scan_count = randLIB_get_random_in_range(40, 100); return; } + // Clear Old information from stack + + ws_nud_table_reset(cur); + ws_bootstrap_neighbor_list_clean(cur); + ws_bootstrap_ip_stack_reset(cur); ws_pae_controller_auth_init(cur); // Randomize fixed channels. Only used if channel plan is fixed. - cur->ws_info->fhss_uc_fixed_channel = ws_randomize_fixed_channel(cur->ws_info->fhss_uc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels); - cur->ws_info->fhss_bc_fixed_channel = ws_randomize_fixed_channel(cur->ws_info->fhss_bc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels); - cur->ws_info->network_pan_id = randLIB_get_random_in_range(0, 0xfffd); + cur->ws_info->cfg->fhss.fhss_uc_fixed_channel = ws_randomize_fixed_channel(cur->ws_info->cfg->fhss.fhss_uc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels); + cur->ws_info->cfg->fhss.fhss_bc_fixed_channel = ws_randomize_fixed_channel(cur->ws_info->cfg->fhss.fhss_bc_fixed_channel, cur->ws_info->hopping_schdule.number_of_channels); + if (cur->ws_info->cfg->gen.network_pan_id == 0xffff) { + cur->ws_info->network_pan_id = randLIB_get_random_in_range(0, 0xfffd); + } else { + cur->ws_info->network_pan_id = cur->ws_info->cfg->gen.network_pan_id; + } cur->ws_info->pan_information.pan_size = 0; cur->ws_info->pan_information.pan_version = randLIB_get_random_in_range(0, 0xffff); cur->ws_info->pan_information.routing_cost = 0; @@ -2715,12 +2954,13 @@ static void ws_bootstrap_event_handler(arm_event_s *event) uint8_t *gtkhash = ws_pae_controller_gtk_hash_ptr_get(cur); ws_llc_set_gtkhash(cur, gtkhash); - cur->ws_info->pan_version_timer = ws_common_version_lifetime_get(cur->ws_info->network_size_config); + ws_bbr_pan_version_increase(cur); // Set default parameters for FHSS when starting a discovery + ws_common_regulatory_domain_config(cur, &cur->ws_info->hopping_schdule); ws_fhss_border_router_configure(cur); + ws_bootstrap_set_domain_rf_config(cur); ws_bootstrap_fhss_activate(cur); - ws_bootstrap_event_operation_start(cur); uint8_t ll_addr[16]; addr_interface_get_ll_address(cur, ll_addr, 1); @@ -2735,10 +2975,12 @@ static void ws_bootstrap_event_handler(arm_event_s *event) ws_eapol_auth_relay_start(cur, EAPOL_RELAY_SOCKET_PORT, ll_addr, PAE_AUTH_SOCKET_PORT); // Set PAN ID and network name to controller - ws_pae_controller_nw_info_set(cur, cur->ws_info->network_pan_id, cur->ws_info->network_name); + ws_pae_controller_nw_info_set(cur, cur->ws_info->network_pan_id, cur->ws_info->cfg->gen.network_name); // Set PAE port to 10254 and authenticator relay to 10253 (and to own ll address) ws_pae_controller_authenticator_start(cur, PAE_AUTH_SOCKET_PORT, ll_addr, EAPOL_RELAY_SOCKET_PORT); + + ws_bootstrap_event_operation_start(cur); break; } ws_pae_controller_supp_init(cur); @@ -2757,6 +2999,7 @@ static void ws_bootstrap_event_handler(arm_event_s *event) cur->ws_info->trickle_pc_running = false; cur->ws_info->trickle_pas_running = false; cur->ws_info->trickle_pcs_running = false; + cur->ws_info->trickle_pc_consistency_block_period = 0; // Build list of possible neighbours and learn first broadcast schedule @@ -2769,6 +3012,7 @@ static void ws_bootstrap_event_handler(arm_event_s *event) cur->ws_info->trickle_pc_running = false; cur->ws_info->trickle_pas_running = false; cur->ws_info->trickle_pcs_running = false; + cur->ws_info->trickle_pc_consistency_block_period = 0; // Activate RPL // Activate IPv6 stack ws_bootstrap_ip_stack_activate(cur); @@ -2788,6 +3032,7 @@ static void ws_bootstrap_event_handler(arm_event_s *event) cur->ws_info->trickle_pc_running = false; cur->ws_info->trickle_pas_running = false; cur->ws_info->trickle_pcs_running = false; + cur->ws_info->trickle_pc_consistency_block_period = 0; // Indicate PAE controller that bootstrap is ready ws_pae_controller_bootstrap_done(cur); @@ -2947,6 +3192,7 @@ void ws_bootstrap_state_machine(protocol_interface_info_entry_t *cur) cur->ws_info->trickle_pc_running = false; cur->ws_info->trickle_pas_running = false; cur->ws_info->trickle_pcs_running = false; + cur->ws_info->trickle_pc_consistency_block_period = 0; ws_fhss_configure(cur, false); ws_bootstrap_start_authentication(cur); break; @@ -3007,27 +3253,58 @@ void ws_bootstrap_trickle_timer(protocol_interface_info_entry_t *cur, uint16_t t tr_info("Send PAN advertisement"); ws_bootstrap_pan_advert(cur); } - if (cur->ws_info->trickle_pc_running && - trickle_timer(&cur->ws_info->trickle_pan_config, &cur->ws_info->trickle_params_pan_discovery, ticks)) { - // send PAN Configuration - tr_info("Send PAN configuration"); - ws_bootstrap_pan_config(cur); + if (cur->ws_info->trickle_pc_running) { + + if (cur->ws_info->trickle_pc_consistency_block_period) { + if (ticks >= cur->ws_info->trickle_pc_consistency_block_period) { + cur->ws_info->trickle_pc_consistency_block_period = 0; + } else { + cur->ws_info->trickle_pc_consistency_block_period -= ticks; + } + } + + if (trickle_timer(&cur->ws_info->trickle_pan_config, &cur->ws_info->trickle_params_pan_discovery, ticks)) { + // send PAN Configuration + tr_info("Send PAN configuration"); + ws_bootstrap_pan_config(cur); + } } } void ws_bootstrap_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds) { - if (cur->ws_info->pan_version_timeout_timer) { + /* Border router keep alive check + */ + if (cur->ws_info->pan_timeout_timer) { // PAN version timer running - if (cur->ws_info->pan_version_timeout_timer > seconds) { - cur->ws_info->pan_version_timeout_timer -= seconds; + if (cur->ws_info->pan_timeout_timer > seconds) { + cur->ws_info->pan_timeout_timer -= seconds; + if (cur->ws_info->pan_timeout_timer < cur->ws_info->cfg->timing.pan_timeout / 10) { + /* pan timeout is closing need to verify that DAO is tested before the pan times out. + This will give some extra time for RPL to find better parents. + Border router liveliness can be checked from version number change or from successful DAO registrations + in this case there has not been any version number changes during this PAN lifetime. + */ + rpl_control_dao_timeout(cur->rpl_domain, 20); + } } else { // Border router has timed out + cur->ws_info->pan_timeout_timer = 0; tr_warn("Border router has timed out"); ws_bootstrap_event_discovery_start(cur); } } + if (cur->ws_info->aro_registration_timer) { + if (cur->ws_info->aro_registration_timer > seconds) { + cur->ws_info->aro_registration_timer -= seconds; + } else { + // Update all addressess. This function will update the timer value if needed + cur->ws_info->aro_registration_timer = 0; + ws_address_registration_update(cur, NULL); + } + } + } void ws_primary_parent_update(protocol_interface_info_entry_t *interface, mac_neighbor_table_entry_t *neighbor) @@ -3050,7 +3327,7 @@ void ws_secondary_parent_update(protocol_interface_info_entry_t *interface) if (interface->ws_info) { ns_list_foreach(if_address_entry_t, address, &interface->ip_addresses) { if (!addr_is_ipv6_link_local(address->address)) { - ws_address_registration_update(interface); + ws_address_parent_update(interface); } } } diff --git a/source/6LoWPAN/ws/ws_bootstrap.h b/source/6LoWPAN/ws/ws_bootstrap.h index 062dc767a3..949eac4a99 100644 --- a/source/6LoWPAN/ws/ws_bootstrap.h +++ b/source/6LoWPAN/ws/ws_bootstrap.h @@ -30,6 +30,7 @@ typedef enum { #ifdef HAVE_WS struct llc_neighbour_req; +struct ws_us_ie; int ws_bootstrap_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode); @@ -37,6 +38,8 @@ void ws_bootstrap_state_machine(protocol_interface_info_entry_t *cur); int ws_bootstrap_restart(int8_t interface_id); +int ws_bootstrap_restart_delayed(int8_t interface_id); + int ws_bootstrap_set_rf_config(protocol_interface_info_entry_t *cur, phy_rf_channel_configuration_s rf_configs); int ws_bootstrap_neighbor_remove(protocol_interface_info_entry_t *cur, const uint8_t *ll_address); @@ -76,6 +79,8 @@ bool ws_eapol_relay_state_active(protocol_interface_info_entry_t *cur); void ws_bootstrap_eapol_parent_synch(struct protocol_interface_info_entry *cur, struct llc_neighbour_req *neighbor_info); +bool ws_bootstrap_validate_channel_plan(struct ws_us_ie *ws_us, struct protocol_interface_info_entry *cur); + #else #define ws_bootstrap_init(interface_id, bootstrap_mode) (-1) diff --git a/source/6LoWPAN/ws/ws_cfg_settings.c b/source/6LoWPAN/ws/ws_cfg_settings.c new file mode 100644 index 0000000000..bebe6627d7 --- /dev/null +++ b/source/6LoWPAN/ws/ws_cfg_settings.c @@ -0,0 +1,1169 @@ +/* + * Copyright (c) 2020, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "nsconfig.h" +#include "ns_types.h" +#include "ns_list.h" +#include "ns_trace.h" +#include "nsdynmemLIB.h" +#include "net_interface.h" +#include "eventOS_event.h" +#include "NWK_INTERFACE/Include/protocol.h" +#include "6LoWPAN/ws/ws_common.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" +#include "6LoWPAN/ws/ws_bbr_api_internal.h" +#include "6LoWPAN/ws/ws_bootstrap.h" +#include "6LoWPAN/ws/ws_pae_controller.h" +#include "ws_management_api.h" +#include "MPL/mpl.h" + +#define TRACE_GROUP "cstr" + +#ifdef HAVE_WS + +#define CFG_SETTINGS_OK 0 +#define CFG_SETTINGS_CHANGED 1 + +#define CFG_FLAGS_DISABLE_VAL_SET 0x01 +#define CFG_FLAGS_OVERRIDE_DISABLE_VAL_SET 0x02 +#define CFG_FLAGS_FORCE_INTERNAL_CONFIG 0x04 +#define CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE 0x08 + +#define TRICKLE_IMIN_60_SECS 60 +#define TRICKLE_IMIN_30_SECS 30 +#define TRICKLE_IMIN_15_SECS 15 + +typedef struct ws_cfg_nw_size_s { + ws_timing_cfg_t timing; /**< Timing configuration */ + ws_rpl_cfg_t rpl; /**< RPL configuration */ + ws_sec_prot_cfg_t sec_prot; /**< Security protocols configuration */ +} ws_cfg_nw_size_t; + +typedef int8_t (*ws_cfg_default_set)(void *cfg); +typedef int8_t (*ws_cfg_validate)(void *cfg, void *new_cfg); +typedef int8_t (*ws_cfg_set)(protocol_interface_info_entry_t *cur, void *cfg, void *new_cfg, uint8_t *flags); + +typedef struct { + ws_cfg_default_set default_set; + ws_cfg_validate validate; + ws_cfg_set set; + uint16_t setting_offset; +} ws_cfg_cb_t; + +typedef union { + ws_gen_cfg_t gen; + ws_phy_cfg_t phy; + ws_timing_cfg_t timing; + ws_rpl_cfg_t rpl; + ws_fhss_cfg_t fhss; + ws_mpl_cfg_t mpl; + ws_sec_timer_cfg_t sec_timer; + ws_sec_prot_cfg_t sec_prot; +} ws_cfgs_t; + +static int8_t ws_cfg_to_get(ws_cfgs_t **cfg, ws_cfgs_t *new_cfg, ws_cfg_validate valid_cb, ws_cfgs_t *external_cfg, uint8_t *cfg_flags, uint8_t *flags); + +static void ws_cfg_network_size_config_set_small(ws_cfg_nw_size_t *cfg); +static void ws_cfg_network_size_config_set_medium(ws_cfg_nw_size_t *cfg); +static void ws_cfg_network_size_config_set_large(ws_cfg_nw_size_t *cfg); +static void ws_cfg_network_size_config_set_certificate(ws_cfg_nw_size_t *cfg); +static int8_t ws_cfg_network_size_default_set(ws_gen_cfg_t *cfg); +static int8_t ws_cfg_gen_default_set(ws_gen_cfg_t *cfg); +static int8_t ws_cfg_phy_default_set(ws_phy_cfg_t *cfg); +static int8_t ws_cfg_timing_default_set(ws_timing_cfg_t *cfg); +static int8_t ws_cfg_rpl_default_set(ws_rpl_cfg_t *cfg); +static int8_t ws_cfg_mpl_default_set(ws_mpl_cfg_t *cfg); +static int8_t ws_cfg_fhss_default_set(ws_fhss_cfg_t *cfg); +static int8_t ws_cfg_sec_timer_default_set(ws_sec_timer_cfg_t *cfg); +static int8_t ws_cfg_sec_prot_default_set(ws_sec_prot_cfg_t *cfg); + +#define CFG_CB(default_cb, validate_cb, set_cb, offset) \ + { \ + .default_set = (ws_cfg_default_set) default_cb, \ + .validate = (ws_cfg_validate) validate_cb, \ + .set = (ws_cfg_set) set_cb, \ + .setting_offset = offset, \ + } + +// Create validate and set callback table +static const ws_cfg_cb_t cfg_cb[] = { + // Network size configuration must be done first + CFG_CB(ws_cfg_network_size_default_set, ws_cfg_network_size_validate, ws_cfg_network_size_set, offsetof(ws_cfg_t, gen)), + CFG_CB(ws_cfg_gen_default_set, ws_cfg_gen_validate, ws_cfg_gen_set, offsetof(ws_cfg_t, gen)), + CFG_CB(ws_cfg_phy_default_set, ws_cfg_phy_validate, ws_cfg_phy_set, offsetof(ws_cfg_t, phy)), + CFG_CB(ws_cfg_timing_default_set, ws_cfg_timing_validate, ws_cfg_timing_set, offsetof(ws_cfg_t, timing)), + CFG_CB(ws_cfg_rpl_default_set, ws_cfg_rpl_validate, ws_cfg_rpl_set, offsetof(ws_cfg_t, rpl)), + CFG_CB(ws_cfg_mpl_default_set, ws_cfg_mpl_validate, ws_cfg_mpl_set, offsetof(ws_cfg_t, mpl)), + CFG_CB(ws_cfg_fhss_default_set, ws_cfg_fhss_validate, ws_cfg_fhss_set, offsetof(ws_cfg_t, fhss)), + CFG_CB(ws_cfg_sec_timer_default_set, ws_cfg_sec_timer_validate, ws_cfg_sec_timer_set, offsetof(ws_cfg_t, sec_timer)), + CFG_CB(ws_cfg_sec_prot_default_set, ws_cfg_sec_prot_validate, ws_cfg_sec_prot_set, offsetof(ws_cfg_t, sec_prot)), +}; + +#define CFG_CB_NUM (sizeof(cfg_cb) / sizeof(ws_cfg_cb_t)) + +// Wisun configuration storage +ws_cfg_t ws_cfg; + +// If automatic network size mode; external configuration shown to towards users of external APIs +ws_cfg_nw_size_t *nw_size_external_cfg = NULL; + +static int8_t ws_cfg_to_get(ws_cfgs_t **cfg, ws_cfgs_t *new_cfg, ws_cfg_validate valid_cb, ws_cfgs_t *ws_cfg_ptr, uint8_t *cfg_flags, uint8_t *flags) +{ + // In case target configuration is not set, uses ws_cfg storage + if (*cfg == NULL) { + // In case external configuration is not same as internal + if (nw_size_external_cfg && (!flags || !(*flags & CFG_FLAGS_FORCE_INTERNAL_CONFIG))) { + if (ws_cfg_ptr == (ws_cfgs_t *) &ws_cfg.timing) { + *cfg = (ws_cfgs_t *) &nw_size_external_cfg->timing; + } else if (ws_cfg_ptr == (ws_cfgs_t *) &ws_cfg.rpl) { + *cfg = (ws_cfgs_t *) &nw_size_external_cfg->rpl; + } else if (ws_cfg_ptr == (ws_cfgs_t *) &ws_cfg.sec_prot) { + *cfg = (ws_cfgs_t *) &nw_size_external_cfg->sec_prot; + } else { + *cfg = ws_cfg_ptr; + } + } else { + *cfg = ws_cfg_ptr; + } + + if (valid_cb) { + int8_t ret = valid_cb(*cfg, new_cfg); + // On failure and if nothing is changed, returns + if (ret != CFG_SETTINGS_CHANGED) { + return ret; + } + } + } + + if (!cfg_flags) { + return CFG_SETTINGS_CHANGED; + } + *cfg_flags = 0; + if (flags) { + *cfg_flags |= *flags; + } + if (nw_size_external_cfg && !(*cfg_flags & CFG_FLAGS_OVERRIDE_DISABLE_VAL_SET)) { + *cfg_flags |= CFG_FLAGS_DISABLE_VAL_SET; + } + + return CFG_SETTINGS_CHANGED; +} + +#ifdef FEA_TRACE_SUPPORT +static void ws_cfg_trace(ws_cfgs_t *cfg, ws_cfgs_t *new_cfg, uint8_t size, char *name) +{ + uint8_t *start = 0; + uint8_t *end = 0; + + tr_debug("config set: %s, changed fields:", name); + + bool print_index = true; + for (uint8_t i = 0; i < size; i++) { + if (((uint8_t *) cfg)[i] != ((uint8_t *) new_cfg)[i]) { + if (print_index) { + start = &((uint8_t *) new_cfg)[i]; + print_index = false; + } + end = &((uint8_t *) new_cfg)[i]; + } else { + if (start && end) { + tr_debug("i: %p v: %s ", (void *)(start - ((uint8_t *) new_cfg)), trace_array(start, end - start + 1)); + } + start = NULL; + end = NULL; + print_index = true; + } + } + + if (start && end) { + tr_debug("i: %p v: %s ", (void *)(start - ((uint8_t *) new_cfg)), trace_array(start, end - start + 1)); + } +} +#else +#define ws_cfg_trace(cfg, new_cfg, size, name) +#endif + +static int8_t ws_cfg_network_size_default_set(ws_gen_cfg_t *cfg) +{ + cfg->network_size = NETWORK_SIZE_MEDIUM; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_network_size_get(ws_gen_cfg_t *cfg, uint8_t *flags) +{ + ws_gen_cfg_t *get_cfg = NULL; + ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.gen, 0, flags); + *cfg = *get_cfg; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_network_size_validate(ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg) +{ + ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.gen, 0, 0); + + if (cfg->network_size != new_cfg->network_size) { + return CFG_SETTINGS_CHANGED; + } + + return CFG_SETTINGS_OK; +} + +typedef void (*ws_cfg_network_size_config_set_size)(ws_cfg_nw_size_t *cfg); + +int8_t ws_cfg_network_size_set(protocol_interface_info_entry_t *cur, ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg, uint8_t *flags) +{ + uint8_t cfg_flags; + int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_network_size_validate, (ws_cfgs_t *) &ws_cfg.gen, &cfg_flags, flags); + if (ret != CFG_SETTINGS_CHANGED) { + return ret; + } + + uint8_t old_network_size = cfg->network_size; + + // If network size configuration has not changed, returns + if (cfg->network_size == new_cfg->network_size) { + return CFG_SETTINGS_OK; + } + + cfg->network_size = new_cfg->network_size; + + ws_cfg_nw_size_t nw_size_cfg; + ws_cfg_timing_get(&nw_size_cfg.timing, NULL); + ws_cfg_rpl_get(&nw_size_cfg.rpl, NULL); + ws_cfg_sec_prot_get(&nw_size_cfg.sec_prot, NULL); + + ws_cfg_network_size_config_set_size set_function = NULL; + + if (cfg->network_size == NETWORK_SIZE_CERTIFICATE) { + set_function = ws_cfg_network_size_config_set_certificate; + } else if (cfg->network_size <= NETWORK_SIZE_SMALL || cfg->network_size == NETWORK_SIZE_AUTOMATIC) { + set_function = ws_cfg_network_size_config_set_small; + } else if (cfg->network_size <= NETWORK_SIZE_MEDIUM) { + set_function = ws_cfg_network_size_config_set_medium; + } else { + set_function = ws_cfg_network_size_config_set_large; + } + + // Overrides the values on the new configuration + if (set_function != NULL) { + set_function(&nw_size_cfg); + } + + /* If no longer in an automatic network size mode, frees automatic configuration, + so that new configuration is set */ + if (nw_size_external_cfg && old_network_size == NETWORK_SIZE_AUTOMATIC) { + ns_dyn_mem_free(nw_size_external_cfg); + nw_size_external_cfg = NULL; + } + + uint8_t set_flags = 0; + if (cfg->network_size == NETWORK_SIZE_AUTOMATIC) { + set_flags = CFG_FLAGS_DISABLE_VAL_SET; + } + /* Sets values if changed or network size has been previously automatic (to make sure + the settings are in sync */ + if (ws_cfg_timing_validate(&ws_cfg.timing, &nw_size_cfg.timing) == CFG_SETTINGS_CHANGED || + old_network_size == NETWORK_SIZE_AUTOMATIC) { + ws_cfg_timing_set(cur, &ws_cfg.timing, &nw_size_cfg.timing, &set_flags); + } + if (ws_cfg_rpl_validate(&ws_cfg.rpl, &nw_size_cfg.rpl) == CFG_SETTINGS_CHANGED || + old_network_size == NETWORK_SIZE_AUTOMATIC) { + ws_cfg_rpl_set(cur, &ws_cfg.rpl, &nw_size_cfg.rpl, &set_flags); + } + if (ws_cfg_sec_prot_validate(&ws_cfg.sec_prot, &nw_size_cfg.sec_prot) == CFG_SETTINGS_CHANGED || + old_network_size == NETWORK_SIZE_AUTOMATIC) { + ws_cfg_sec_prot_set(cur, &ws_cfg.sec_prot, &nw_size_cfg.sec_prot, &set_flags); + } + + // If is in an automatic network size mode, updates automatic configuration + if (cfg->network_size == NETWORK_SIZE_AUTOMATIC && cur) { + ws_cfg_network_size_configure(cur, cur->ws_info->pan_information.pan_size); + } + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_network_size_configure(protocol_interface_info_entry_t *cur, uint16_t network_size) +{ + // Read settings that are affected by network size + ws_cfg_nw_size_t new_nw_size_cfg; + uint8_t flags = CFG_FLAGS_OVERRIDE_DISABLE_VAL_SET | CFG_FLAGS_FORCE_INTERNAL_CONFIG; + ws_cfg_timing_get(&new_nw_size_cfg.timing, &flags); + ws_cfg_rpl_get(&new_nw_size_cfg.rpl, &flags); + ws_cfg_sec_prot_get(&new_nw_size_cfg.sec_prot, &flags); + + if (!nw_size_external_cfg) { + nw_size_external_cfg = ns_dyn_mem_alloc(sizeof(ws_cfg_nw_size_t)); + if (!nw_size_external_cfg) { + return -1; + } + memcpy(nw_size_external_cfg, &new_nw_size_cfg, sizeof(ws_cfg_nw_size_t)); + } + + // Small + if (network_size < 100) { + // Automatic + ws_cfg_network_size_config_set_small(&new_nw_size_cfg); + } else if (network_size < 300) { + // Medium + ws_cfg_network_size_config_set_medium(&new_nw_size_cfg); + } else { + // Large + ws_cfg_network_size_config_set_large(&new_nw_size_cfg); + } + + ws_cfg_timing_set(cur, NULL, &new_nw_size_cfg.timing, &flags); + ws_cfg_rpl_set(cur, NULL, &new_nw_size_cfg.rpl, &flags); + ws_cfg_sec_prot_set(cur, NULL, &new_nw_size_cfg.sec_prot, &flags); + + return CFG_SETTINGS_OK; +} + +static void ws_cfg_network_size_config_set_small(ws_cfg_nw_size_t *cfg) +{ + // Configure the Wi-SUN timing trickle parameter + cfg->timing.disc_trickle_imin = TRICKLE_IMIN_15_SECS; // 15 seconds + cfg->timing.disc_trickle_imax = TRICKLE_IMIN_15_SECS << 2; // 60 seconds + cfg->timing.disc_trickle_k = 1; + cfg->timing.pan_timeout = PAN_VERSION_SMALL_NETWORK_TIMEOUT; + cfg->timing.temp_link_min_timeout = WS_NEIGHBOR_TEMPORARY_LINK_MIN_TIMEOUT_SMALL; + + // RPL configuration + cfg->rpl.dio_interval_min = WS_RPL_DIO_IMIN_SMALL; // 15; 32s seconds + cfg->rpl.dio_interval_doublings = WS_RPL_DIO_DOUBLING_SMALL; // 2; 128 + cfg->rpl.dio_redundancy_constant = WS_RPL_DIO_REDUNDANCY_SMALL; // Disabled + cfg->rpl.dag_max_rank_increase = WS_RPL_MAX_HOP_RANK_INCREASE; + cfg->rpl.min_hop_rank_increase = WS_RPL_MIN_HOP_RANK_INCREASE; + cfg->rpl.rpl_parent_candidate_max = WS_RPL_PARENT_CANDIDATE_MAX; + cfg->rpl.rpl_selected_parent_max = WS_RPL_SELECTED_PARENT_MAX; + + // EAPOL configuration + cfg->sec_prot.sec_prot_trickle_imin = SEC_PROT_SMALL_IMIN; + cfg->sec_prot.sec_prot_trickle_imax = SEC_PROT_SMALL_IMAX; + cfg->sec_prot.sec_prot_trickle_timer_exp = SEC_PROT_TIMER_EXPIRATIONS; + cfg->sec_prot.sec_prot_retry_timeout = SEC_PROT_RETRY_TIMEOUT_SMALL; + cfg->sec_prot.sec_max_ongoing_authentication = MAX_SIMULTANEOUS_EAP_TLS_NEGOTIATIONS_SMALL; +} + +static void ws_cfg_network_size_config_set_medium(ws_cfg_nw_size_t *cfg) +{ + // Configure the Wi-SUN timing trickle parameters + cfg->timing.disc_trickle_imin = TRICKLE_IMIN_30_SECS; // 30 seconds + cfg->timing.disc_trickle_imax = TRICKLE_IMIN_30_SECS << 5; // 960 seconds; 16 minutes + cfg->timing.disc_trickle_k = 1; + cfg->timing.pan_timeout = PAN_VERSION_MEDIUM_NETWORK_TIMEOUT; + cfg->timing.temp_link_min_timeout = WS_NEIGHBOR_TEMPORARY_LINK_MIN_TIMEOUT_SMALL; + + // RPL configuration + cfg->rpl.dio_interval_min = WS_RPL_DIO_IMIN_MEDIUM; // 15; 32s + cfg->rpl.dio_interval_doublings = WS_RPL_DIO_DOUBLING_MEDIUM; // 2; 1024s + cfg->rpl.dio_redundancy_constant = WS_RPL_DIO_REDUNDANCY_MEDIUM; // 10 + cfg->rpl.dag_max_rank_increase = WS_RPL_MAX_HOP_RANK_INCREASE; + cfg->rpl.min_hop_rank_increase = WS_RPL_MIN_HOP_RANK_INCREASE; + cfg->rpl.rpl_parent_candidate_max = WS_RPL_PARENT_CANDIDATE_MAX; + cfg->rpl.rpl_selected_parent_max = WS_RPL_SELECTED_PARENT_MAX; + + // EAPOL configuration + cfg->sec_prot.sec_prot_trickle_imin = SEC_PROT_SMALL_IMIN; + cfg->sec_prot.sec_prot_trickle_imax = SEC_PROT_SMALL_IMAX; + cfg->sec_prot.sec_prot_trickle_timer_exp = SEC_PROT_TIMER_EXPIRATIONS; + cfg->sec_prot.sec_prot_retry_timeout = SEC_PROT_RETRY_TIMEOUT_SMALL; + cfg->sec_prot.sec_max_ongoing_authentication = MAX_SIMULTANEOUS_EAP_TLS_NEGOTIATIONS_MEDIUM; +} + +static void ws_cfg_network_size_config_set_large(ws_cfg_nw_size_t *cfg) +{ + // Configure the Wi-SUN timing trickle parameters + cfg->timing.disc_trickle_imin = TRICKLE_IMIN_60_SECS; // 60 seconds + cfg->timing.disc_trickle_imax = TRICKLE_IMIN_60_SECS << 4; // 960 seconds; 16 minutes + cfg->timing.disc_trickle_k = 1; + cfg->timing.pan_timeout = PAN_VERSION_LARGE_NETWORK_TIMEOUT; + cfg->timing.temp_link_min_timeout = WS_NEIGHBOR_TEMPORARY_LINK_MIN_TIMEOUT_LARGE; + + // RPL configuration + cfg->rpl.dio_interval_min = WS_RPL_DIO_IMIN_LARGE; // 19; 524s, 9min + cfg->rpl.dio_interval_doublings = WS_RPL_DIO_DOUBLING_LARGE; // 1; 1024s, 17min + cfg->rpl.dio_redundancy_constant = WS_RPL_DIO_REDUNDANCY_LARGE; // 10 + cfg->rpl.dag_max_rank_increase = WS_RPL_MAX_HOP_RANK_INCREASE; + cfg->rpl.min_hop_rank_increase = WS_RPL_MIN_HOP_RANK_INCREASE; + cfg->rpl.rpl_parent_candidate_max = WS_RPL_PARENT_CANDIDATE_MAX; + cfg->rpl.rpl_selected_parent_max = WS_RPL_SELECTED_PARENT_MAX; + + // EAPOL configuration + cfg->sec_prot.sec_prot_trickle_imin = SEC_PROT_LARGE_IMIN; + cfg->sec_prot.sec_prot_trickle_imax = SEC_PROT_LARGE_IMAX; + cfg->sec_prot.sec_prot_trickle_timer_exp = SEC_PROT_TIMER_EXPIRATIONS; + cfg->sec_prot.sec_prot_retry_timeout = SEC_PROT_RETRY_TIMEOUT_LARGE; + cfg->sec_prot.sec_max_ongoing_authentication = MAX_SIMULTANEOUS_EAP_TLS_NEGOTIATIONS_LARGE; +} + +static void ws_cfg_network_size_config_set_certificate(ws_cfg_nw_size_t *cfg) +{ + // Configure the Wi-SUN timing trickle parameters + cfg->timing.disc_trickle_imin = TRICKLE_IMIN_15_SECS; // 15 seconds + cfg->timing.disc_trickle_imax = TRICKLE_IMIN_15_SECS << 2; // 60 seconds + cfg->timing.disc_trickle_k = 1; + cfg->timing.pan_timeout = PAN_VERSION_SMALL_NETWORK_TIMEOUT; + cfg->timing.temp_link_min_timeout = WS_NEIGHBOR_TEMPORARY_LINK_MIN_TIMEOUT_SMALL; + + // RPL configuration (small) + cfg->rpl.dio_interval_min = WS_RPL_DIO_IMIN_SMALL; // 15; 32s seconds + cfg->rpl.dio_interval_doublings = WS_RPL_DIO_DOUBLING_SMALL; // 2; 128 + cfg->rpl.dio_redundancy_constant = WS_RPL_DIO_REDUNDANCY_SMALL; // Disabled + cfg->rpl.dag_max_rank_increase = WS_CERTIFICATE_RPL_MAX_HOP_RANK_INCREASE; + cfg->rpl.min_hop_rank_increase = WS_CERTIFICATE_RPL_MIN_HOP_RANK_INCREASE; + cfg->rpl.rpl_parent_candidate_max = WS_CERTIFICATE_RPL_PARENT_CANDIDATE_MAX; + cfg->rpl.rpl_selected_parent_max = WS_CERTIFICATE_RPL_SELECTED_PARENT_MAX; + + // EAPOL configuration + cfg->sec_prot.sec_prot_trickle_imin = SEC_PROT_SMALL_IMIN; + cfg->sec_prot.sec_prot_trickle_imax = SEC_PROT_SMALL_IMAX; + cfg->sec_prot.sec_prot_trickle_timer_exp = SEC_PROT_TIMER_EXPIRATIONS; + cfg->sec_prot.sec_prot_retry_timeout = SEC_PROT_RETRY_TIMEOUT_SMALL; + cfg->sec_prot.sec_max_ongoing_authentication = MAX_SIMULTANEOUS_EAP_TLS_NEGOTIATIONS_SMALL; +} + +static int8_t ws_cfg_gen_default_set(ws_gen_cfg_t *cfg) +{ + memset(cfg->network_name, 0, sizeof(cfg->network_name)); + cfg->network_pan_id = 0xffff; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_gen_get(ws_gen_cfg_t *cfg, uint8_t *flags) +{ + ws_gen_cfg_t *get_cfg = NULL; + ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.gen, 0, flags); + *cfg = *get_cfg; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_gen_validate(ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg) +{ + ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.gen, 0, 0); + + if (strlen(new_cfg->network_name) > 32) { + return CFG_SETTINGS_ERROR_GEN_CONF; + } + + // Regulator domain, operating mode or class has changed + if (strcmp(cfg->network_name, new_cfg->network_name) != 0 || + cfg->network_pan_id != new_cfg->network_pan_id) { + return CFG_SETTINGS_CHANGED; + } + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_gen_set(protocol_interface_info_entry_t *cur, ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg, uint8_t *flags) +{ + (void) cur; + (void) flags; + + uint8_t cfg_flags; + int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_gen_validate, (ws_cfgs_t *) &ws_cfg.gen, &cfg_flags, flags); + if (ret != CFG_SETTINGS_CHANGED) { + return ret; + } + if (cfg == new_cfg) { + return CFG_SETTINGS_OK; + } + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_gen_cfg_t), "gen"); + + if (&cfg->network_name != &new_cfg->network_name) { + strncpy(cfg->network_name, new_cfg->network_name, 32); + } + cfg->network_pan_id = new_cfg->network_pan_id; + + if (cur && !(cfg_flags & CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE)) { + ws_bootstrap_restart_delayed(cur->id); + } + + return CFG_SETTINGS_OK; +} + +static int8_t ws_cfg_phy_default_set(ws_phy_cfg_t *cfg) +{ + // FHSS configuration + cfg->regulatory_domain = REG_DOMAIN_EU; + cfg->operating_mode = OPERATING_MODE_3; + cfg->operating_class = 2; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_phy_get(ws_phy_cfg_t *cfg, uint8_t *flags) +{ + ws_phy_cfg_t *get_cfg = NULL; + ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.phy, 0, flags); + *cfg = *get_cfg; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_phy_validate(ws_phy_cfg_t *cfg, ws_phy_cfg_t *new_cfg) +{ + ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.phy, 0, 0); + + // Regulator domain, operating mode or class has changed + if (cfg->regulatory_domain != new_cfg->regulatory_domain || + cfg->operating_mode != new_cfg->operating_mode || + cfg->operating_class != new_cfg->operating_class) { + + ws_hopping_schedule_t hopping_schdule = { + .regulatory_domain = new_cfg->regulatory_domain, + .operating_mode = new_cfg->operating_mode, + .operating_class = new_cfg->operating_class + }; + + // Check that new settings are valid + if (ws_common_regulatory_domain_config(NULL, &hopping_schdule) < 0) { + // Invalid regulatory domain set + return CFG_SETTINGS_ERROR_PHY_CONF; + } + + return CFG_SETTINGS_CHANGED; + } + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_phy_set(protocol_interface_info_entry_t *cur, ws_phy_cfg_t *cfg, ws_phy_cfg_t *new_cfg, uint8_t *flags) +{ + uint8_t cfg_flags; + int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_phy_validate, (ws_cfgs_t *) &ws_cfg.phy, &cfg_flags, flags); + if (ret != CFG_SETTINGS_CHANGED) { + return ret; + } + + // Check settings and configure interface + if (cur && !(cfg_flags & CFG_FLAGS_DISABLE_VAL_SET)) { + cur->ws_info->hopping_schdule.regulatory_domain = new_cfg->regulatory_domain; + cur->ws_info->hopping_schdule.operating_mode = new_cfg->operating_mode; + cur->ws_info->hopping_schdule.operating_class = new_cfg->operating_class; + + if (ws_common_regulatory_domain_config(cur, &cur->ws_info->hopping_schdule) < 0) { + return CFG_SETTINGS_ERROR_PHY_CONF; + } + } + + if (cfg == new_cfg) { + return CFG_SETTINGS_OK; + } + + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_phy_cfg_t), "phy"); + + *cfg = *new_cfg; + + if (cur && !(cfg_flags & CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE)) { + ws_bootstrap_restart_delayed(cur->id); + } + + return CFG_SETTINGS_OK; +} + +static int8_t ws_cfg_timing_default_set(ws_timing_cfg_t *cfg) +{ + // Configure the Wi-SUN timing trickle parameters + cfg->disc_trickle_imin = TRICKLE_IMIN_30_SECS; // 30 seconds + cfg->disc_trickle_imax = TRICKLE_IMIN_30_SECS << 5; // 960 seconds; 16 minutes + cfg->disc_trickle_k = 1; + cfg->pan_timeout = PAN_VERSION_MEDIUM_NETWORK_TIMEOUT; + cfg->temp_link_min_timeout = WS_NEIGHBOR_TEMPORARY_LINK_MIN_TIMEOUT_SMALL; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_timing_get(ws_timing_cfg_t *cfg, uint8_t *flags) +{ + ws_timing_cfg_t *get_cfg = NULL; + ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.timing, 0, flags); + *cfg = *get_cfg; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_timing_validate(ws_timing_cfg_t *cfg, ws_timing_cfg_t *new_cfg) +{ + ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.timing, 0, 0); + + if (cfg->disc_trickle_imin != new_cfg->disc_trickle_imin || + cfg->disc_trickle_imax != new_cfg->disc_trickle_imax || + cfg->disc_trickle_k != new_cfg->disc_trickle_k || + cfg->pan_timeout != new_cfg->pan_timeout || + cfg->temp_link_min_timeout != new_cfg->temp_link_min_timeout) { + + // Discovery Imin 1 to 255 + if (new_cfg->disc_trickle_imin < 1 || new_cfg->disc_trickle_imin > 255) { + return CFG_SETTINGS_ERROR_TIMING_CONF; + } + // Discovery Imax, 1 to 8 doublings of imin + if (new_cfg->disc_trickle_imax < new_cfg->disc_trickle_imin * 2 || + new_cfg->disc_trickle_imax > new_cfg->disc_trickle_imin * 256) { + return CFG_SETTINGS_ERROR_TIMING_CONF; + } + // Discovery k parameter defined to be 1 + if (cfg->disc_trickle_k != 1) { + return CFG_SETTINGS_ERROR_TIMING_CONF; + } + + return CFG_SETTINGS_CHANGED; + } + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_timing_set(protocol_interface_info_entry_t *cur, ws_timing_cfg_t *cfg, ws_timing_cfg_t *new_cfg, uint8_t *flags) +{ + uint8_t cfg_flags; + int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_timing_validate, (ws_cfgs_t *) &ws_cfg.timing, &cfg_flags, flags); + if (ret != CFG_SETTINGS_CHANGED) { + return ret; + } + + if (cur && !(cfg_flags & CFG_FLAGS_DISABLE_VAL_SET)) { + cur->ws_info->trickle_params_pan_discovery.Imin = new_cfg->disc_trickle_imin * 10; + cur->ws_info->trickle_params_pan_discovery.Imax = new_cfg->disc_trickle_imax * 10; + cur->ws_info->trickle_params_pan_discovery.k = new_cfg->disc_trickle_k; + cur->ws_info->trickle_params_pan_discovery.TimerExpirations = TRICKLE_EXPIRATIONS_INFINITE; + } + + if (cfg == new_cfg) { + return CFG_SETTINGS_OK; + } + + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_timing_cfg_t), "timing"); + + *cfg = *new_cfg; + + return CFG_SETTINGS_OK; +} + +static int8_t ws_cfg_rpl_default_set(ws_rpl_cfg_t *cfg) +{ + // Something in between + // imin: 15 (32s) + // doublings:5 (960s) + // redundancy; 10 + //ws_bbr_rpl_config(cur, 15, 5, 10, WS_RPL_MAX_HOP_RANK_INCREASE, WS_RPL_MIN_HOP_RANK_INCREASE); + + cfg->dio_interval_min = 15; // 32s + cfg->dio_interval_doublings = 5; // 1024s + cfg->dio_redundancy_constant = 10; + cfg->dag_max_rank_increase = WS_RPL_MAX_HOP_RANK_INCREASE; + cfg->min_hop_rank_increase = WS_RPL_MIN_HOP_RANK_INCREASE; + cfg->rpl_parent_candidate_max = WS_RPL_PARENT_CANDIDATE_MAX; + cfg->rpl_selected_parent_max = WS_RPL_SELECTED_PARENT_MAX; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_rpl_get(ws_rpl_cfg_t *cfg, uint8_t *flags) +{ + ws_rpl_cfg_t *get_cfg = NULL; + ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.rpl, 0, flags); + *cfg = *get_cfg; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_rpl_validate(ws_rpl_cfg_t *cfg, ws_rpl_cfg_t *new_cfg) +{ + ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.rpl, 0, 0); + + if (cfg->dio_interval_min != new_cfg->dio_interval_min || + cfg->dio_interval_doublings != new_cfg->dio_interval_doublings || + cfg->dio_redundancy_constant != new_cfg->dio_redundancy_constant || + cfg->dag_max_rank_increase != new_cfg->dag_max_rank_increase || + cfg->min_hop_rank_increase != new_cfg->min_hop_rank_increase || + cfg->rpl_parent_candidate_max != new_cfg->rpl_parent_candidate_max || + cfg->rpl_selected_parent_max != new_cfg->rpl_selected_parent_max) { + return CFG_SETTINGS_CHANGED; + } + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_rpl_set(protocol_interface_info_entry_t *cur, ws_rpl_cfg_t *cfg, ws_rpl_cfg_t *new_cfg, uint8_t *flags) +{ + (void) cur; + (void) flags; + + uint8_t cfg_flags; + int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_rpl_validate, (ws_cfgs_t *) &ws_cfg.rpl, &cfg_flags, flags); + if (ret != CFG_SETTINGS_CHANGED) { + return ret; + } + + if (!(cfg_flags & CFG_FLAGS_DISABLE_VAL_SET)) { + // cur is optional, default values are for Wi-SUN small network parameters, + ws_bbr_rpl_config(cur, new_cfg->dio_interval_min, new_cfg->dio_interval_doublings, + new_cfg->dio_redundancy_constant, new_cfg->dag_max_rank_increase, + new_cfg->min_hop_rank_increase); + } + + if (cfg == new_cfg) { + return CFG_SETTINGS_OK; + } + + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_rpl_cfg_t), "rpl"); + + *cfg = *new_cfg; + + return CFG_SETTINGS_OK; +} + +static int8_t ws_cfg_mpl_default_set(ws_mpl_cfg_t *cfg) +{ + // MPL configuration + cfg->mpl_trickle_imin = DATA_MESSAGE_IMIN; + cfg->mpl_trickle_imax = DATA_MESSAGE_IMAX; + cfg->mpl_trickle_k = DATA_MESSAGE_K; + cfg->mpl_trickle_timer_exp = DATA_MESSAGE_TIMER_EXPIRATIONS; + cfg->seed_set_entry_lifetime = MPL_SEED_SET_ENTRY_TIMEOUT; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_mpl_get(ws_mpl_cfg_t *cfg, uint8_t *flags) +{ + ws_mpl_cfg_t *get_cfg = NULL; + ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.mpl, 0, flags); + *cfg = *get_cfg; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_mpl_validate(ws_mpl_cfg_t *cfg, ws_mpl_cfg_t *new_cfg) +{ + ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.mpl, 0, 0); + + // MPL configuration has changed + if (cfg->mpl_trickle_imin != new_cfg->mpl_trickle_imin || + cfg->mpl_trickle_imax != new_cfg->mpl_trickle_imax || + cfg->mpl_trickle_k != new_cfg->mpl_trickle_k || + cfg->mpl_trickle_timer_exp != new_cfg->mpl_trickle_timer_exp || + cfg->seed_set_entry_lifetime != new_cfg->seed_set_entry_lifetime) { + return CFG_SETTINGS_CHANGED; + } + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_mpl_set(protocol_interface_info_entry_t *cur, ws_mpl_cfg_t *cfg, ws_mpl_cfg_t *new_cfg, uint8_t *flags) +{ + uint8_t cfg_flags; + int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_mpl_validate, (ws_cfgs_t *) &ws_cfg.mpl, &cfg_flags, flags); + if (ret != CFG_SETTINGS_CHANGED) { + return ret; + } + + if (cur && !(cfg_flags & CFG_FLAGS_DISABLE_VAL_SET)) { + cur->mpl_data_trickle_params.Imin = MPL_MS_TO_TICKS(new_cfg->mpl_trickle_imin * 1000); + cur->mpl_data_trickle_params.Imax = MPL_MS_TO_TICKS(new_cfg->mpl_trickle_imax * 1000); + cur->mpl_data_trickle_params.k = new_cfg->mpl_trickle_k; + cur->mpl_data_trickle_params.TimerExpirations = new_cfg->mpl_trickle_timer_exp; + cur->mpl_seed_set_entry_lifetime = new_cfg->seed_set_entry_lifetime; + + if (cur->mpl_domain) { + // Update MPL settings + mpl_domain_change_timing(cur->mpl_domain, &cur->mpl_data_trickle_params, cur->mpl_seed_set_entry_lifetime); + } + } + + if (cfg == new_cfg) { + return CFG_SETTINGS_OK; + } + + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_mpl_cfg_t), "mpl"); + + *cfg = *new_cfg; + + return CFG_SETTINGS_OK; +} + +static int8_t ws_cfg_fhss_default_set(ws_fhss_cfg_t *cfg) +{ + // Set defaults for the device. user can modify these. + cfg->fhss_uc_fixed_channel = 0xffff; + cfg->fhss_bc_fixed_channel = 0xffff; + cfg->fhss_uc_dwell_interval = WS_FHSS_UC_DWELL_INTERVAL; + cfg->fhss_bc_interval = WS_FHSS_BC_INTERVAL; + cfg->fhss_bc_dwell_interval = WS_FHSS_BC_DWELL_INTERVAL; + cfg->fhss_uc_channel_function = WS_DH1CF; + cfg->fhss_bc_channel_function = WS_DH1CF; + + for (uint8_t n = 0; n < 8; n++) { + cfg->fhss_channel_mask[n] = 0xffffffff; + } + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_fhss_get(ws_fhss_cfg_t *cfg, uint8_t *flags) +{ + ws_fhss_cfg_t *get_cfg = NULL; + ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.fhss, 0, flags); + *cfg = *get_cfg; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_fhss_validate(ws_fhss_cfg_t *cfg, ws_fhss_cfg_t *new_cfg) +{ + ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.fhss, 0, 0); + + if (memcmp(cfg->fhss_channel_mask, new_cfg->fhss_channel_mask, sizeof(uint32_t) * 8) != 0 || + cfg->fhss_uc_dwell_interval != new_cfg->fhss_uc_dwell_interval || + cfg->fhss_bc_dwell_interval != new_cfg->fhss_bc_dwell_interval || + cfg->fhss_bc_interval != new_cfg->fhss_bc_interval || + cfg->fhss_uc_channel_function != new_cfg->fhss_uc_channel_function || + cfg->fhss_bc_channel_function != new_cfg->fhss_bc_channel_function || + cfg->fhss_uc_fixed_channel != new_cfg->fhss_uc_fixed_channel || + cfg->fhss_bc_fixed_channel != new_cfg->fhss_bc_fixed_channel) { + + if (new_cfg->fhss_uc_dwell_interval < 15) { + return CFG_SETTINGS_ERROR_FHSS_CONF; + } + + if (new_cfg->fhss_bc_dwell_interval < 15) { + return CFG_SETTINGS_ERROR_FHSS_CONF; + } + + if (cfg->fhss_uc_channel_function != WS_FIXED_CHANNEL && + cfg->fhss_uc_channel_function != WS_VENDOR_DEF_CF && + cfg->fhss_uc_channel_function != WS_DH1CF && + cfg->fhss_uc_channel_function != WS_TR51CF) { + return CFG_SETTINGS_ERROR_FHSS_CONF; + } + + return CFG_SETTINGS_CHANGED; + } + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_fhss_set(protocol_interface_info_entry_t *cur, ws_fhss_cfg_t *cfg, ws_fhss_cfg_t *new_cfg, uint8_t *flags) +{ + (void) cur; + + uint8_t cfg_flags; + int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_fhss_validate, (ws_cfgs_t *) &ws_cfg.fhss, &cfg_flags, flags); + if (ret != CFG_SETTINGS_CHANGED) { + return ret; + } + + if (cfg == new_cfg) { + return CFG_SETTINGS_OK; + } + + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_fhss_cfg_t), "fhss"); + + *cfg = *new_cfg; + + if (cfg->fhss_uc_channel_function == WS_FIXED_CHANNEL && cfg->fhss_uc_fixed_channel == 0xffff) { + cfg->fhss_uc_fixed_channel = 0; + tr_warn("UC fixed channel not configured. Set to 0"); + } + + if (cfg->fhss_uc_channel_function != WS_FIXED_CHANNEL) { + cfg->fhss_uc_fixed_channel = 0xffff; + } + + if (cfg->fhss_bc_channel_function == WS_FIXED_CHANNEL && cfg->fhss_bc_fixed_channel == 0xffff) { + cfg->fhss_bc_fixed_channel = 0; + tr_warn("BC fixed channel not configured. Set to 0"); + } + + if (cfg->fhss_bc_channel_function != WS_FIXED_CHANNEL) { + cfg->fhss_bc_fixed_channel = 0xffff; + } + + if (cur && !(cfg_flags & CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE)) { + ws_bootstrap_restart_delayed(cur->id); + } + + return CFG_SETTINGS_OK; +} + +static int8_t ws_cfg_sec_timer_default_set(ws_sec_timer_cfg_t *cfg) +{ + cfg->gtk_expire_offset = DEFAULT_GTK_EXPIRE_OFFSET; + cfg->pmk_lifetime = DEFAULT_PMK_LIFETIME; + cfg->ptk_lifetime = DEFAULT_PTK_LIFETIME; + cfg->gtk_new_act_time = DEFAULT_GTK_NEW_ACTIVATION_TIME; + cfg->revocat_lifetime_reduct = DEFAULT_REVOCATION_LIFETIME_REDUCTION; + cfg->gtk_request_imin = DEFAULT_GTK_REQUEST_IMIN; + cfg->gtk_request_imax = DEFAULT_GTK_REQUEST_IMAX; + cfg->gtk_max_mismatch = DEFAULT_GTK_MAX_MISMATCH; + cfg->gtk_new_install_req = DEFAULT_GTK_NEW_INSTALL_REQUIRED; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_sec_timer_get(ws_sec_timer_cfg_t *cfg, uint8_t *flags) +{ + ws_sec_timer_cfg_t *get_cfg = NULL; + ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.sec_timer, 0, flags); + *cfg = *get_cfg; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_sec_timer_validate(ws_sec_timer_cfg_t *cfg, ws_sec_timer_cfg_t *new_cfg) +{ + ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.sec_timer, 0, 0); + + if (cfg->gtk_expire_offset != new_cfg->gtk_expire_offset || + cfg->pmk_lifetime != new_cfg->pmk_lifetime || + cfg->ptk_lifetime != new_cfg->ptk_lifetime || + cfg->gtk_new_act_time != new_cfg->gtk_new_act_time || + cfg->revocat_lifetime_reduct != new_cfg->revocat_lifetime_reduct || + cfg->gtk_request_imin != new_cfg->gtk_request_imin || + cfg->gtk_request_imax != new_cfg->gtk_request_imax || + cfg->gtk_max_mismatch != new_cfg->gtk_max_mismatch || + cfg->gtk_new_install_req != new_cfg->gtk_new_install_req) { + + return CFG_SETTINGS_CHANGED; + } + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_sec_timer_set(protocol_interface_info_entry_t *cur, ws_sec_timer_cfg_t *cfg, ws_sec_timer_cfg_t *new_cfg, uint8_t *flags) +{ + uint8_t cfg_flags; + int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_sec_timer_validate, (ws_cfgs_t *) &ws_cfg.sec_timer, &cfg_flags, flags); + if (ret != CFG_SETTINGS_CHANGED) { + return ret; + } + + if (cur && !(cfg_flags & CFG_FLAGS_DISABLE_VAL_SET)) { + ws_pae_controller_configure(cur, new_cfg, NULL); + } + + if (cfg == new_cfg) { + return CFG_SETTINGS_OK; + } + + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_sec_timer_cfg_t), "sec_timer"); + + *cfg = *new_cfg; + + return CFG_SETTINGS_OK; +} + +static int8_t ws_cfg_sec_prot_default_set(ws_sec_prot_cfg_t *cfg) +{ + cfg->sec_prot_trickle_imin = SEC_PROT_SMALL_IMIN; + cfg->sec_prot_trickle_imax = SEC_PROT_SMALL_IMAX; + cfg->sec_prot_trickle_timer_exp = 2; + cfg->sec_prot_retry_timeout = SEC_PROT_RETRY_TIMEOUT_SMALL; + cfg->sec_max_ongoing_authentication = MAX_SIMULTANEOUS_EAP_TLS_NEGOTIATIONS_MEDIUM; + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_sec_prot_get(ws_sec_prot_cfg_t *cfg, uint8_t *flags) +{ + ws_sec_prot_cfg_t *get_cfg = NULL; + ws_cfg_to_get((ws_cfgs_t **) &get_cfg, NULL, NULL, (ws_cfgs_t *) &ws_cfg.sec_prot, 0, flags); + *cfg = *get_cfg; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_sec_prot_validate(ws_sec_prot_cfg_t *cfg, ws_sec_prot_cfg_t *new_cfg) +{ + ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, NULL, (ws_cfgs_t *) &ws_cfg.sec_prot, 0, 0); + + if (cfg->sec_prot_trickle_imin != new_cfg->sec_prot_trickle_imin || + cfg->sec_prot_trickle_imax != new_cfg->sec_prot_trickle_imax || + cfg->sec_prot_trickle_timer_exp != new_cfg->sec_prot_trickle_timer_exp || + cfg->sec_prot_retry_timeout != new_cfg->sec_prot_retry_timeout || + cfg->sec_max_ongoing_authentication != new_cfg->sec_max_ongoing_authentication) { + + return CFG_SETTINGS_CHANGED; + } + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_sec_prot_set(protocol_interface_info_entry_t *cur, ws_sec_prot_cfg_t *cfg, ws_sec_prot_cfg_t *new_cfg, uint8_t *flags) +{ + uint8_t cfg_flags; + int8_t ret = ws_cfg_to_get((ws_cfgs_t **) &cfg, (ws_cfgs_t *) new_cfg, (ws_cfg_validate) ws_cfg_sec_prot_validate, (ws_cfgs_t *) &ws_cfg.sec_prot, &cfg_flags, flags); + if (ret != CFG_SETTINGS_CHANGED) { + return ret; + } + + if (cur && !(cfg_flags & CFG_FLAGS_DISABLE_VAL_SET)) { + ws_pae_controller_configure(cur, NULL, new_cfg); + } + + if (cfg == new_cfg) { + return CFG_SETTINGS_OK; + } + + ws_cfg_trace((ws_cfgs_t *) cfg, (ws_cfgs_t *) new_cfg, sizeof(ws_sec_prot_cfg_t), "sec_prot"); + + *cfg = *new_cfg; + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_settings_init(void) +{ + ws_cfg_settings_default_set(); + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_settings_default_set(void) +{ + int8_t ret_value = 0; + + // Set default configuration values + for (uint8_t index = 0; index < CFG_CB_NUM; index++) { + if (cfg_cb[index].default_set) { + if (cfg_cb[index].default_set( + ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset) < 0) { + ret_value = CFG_SETTINGS_OTHER_ERROR; + } + } + } + + // Set new configuration values + for (uint8_t index = 0; index < CFG_CB_NUM; index++) { + uint8_t flags = 0; + if (cfg_cb[index].set(NULL, + ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, + ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, + &flags) < 0) { + tr_info("FATAL CONFIG FAILURE"); + ret_value = CFG_SETTINGS_OTHER_ERROR; + } + } + + return ret_value; +} + +int8_t ws_cfg_settings_interface_set(protocol_interface_info_entry_t *cur) +{ + int8_t ret_value = 0; + + cur->ws_info->cfg = &ws_cfg; + + // Set new configuration values + for (uint8_t index = 0; index < CFG_CB_NUM; index++) { + uint8_t flags = CFG_FLAGS_BOOTSTRAP_RESTART_DISABLE; + // Validation + if (cfg_cb[index].set) { + if (cfg_cb[index].set(cur, + ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, + ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, + &flags) < 0) { + tr_info("FATAL CONFIG FAILURE"); + ret_value = CFG_SETTINGS_OTHER_ERROR; + } + } + } + + return ret_value; +} + +int8_t ws_cfg_settings_get(protocol_interface_info_entry_t *cur, ws_cfg_t *cfg) +{ + (void) cur; + + *cfg = ws_cfg; + + ws_cfg_timing_get(&cfg->timing, NULL); + ws_cfg_rpl_get(&cfg->rpl, NULL); + ws_cfg_sec_prot_get(&cfg->sec_prot, NULL); + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_settings_validate(protocol_interface_info_entry_t *cur, struct ws_cfg_s *new_cfg) +{ + (void) cur; + + // Validate new configuration values + for (uint8_t index = 0; index < CFG_CB_NUM; index++) { + if (cfg_cb[index].validate) { + int8_t ret = cfg_cb[index].validate( + ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, + ((uint8_t *)new_cfg) + cfg_cb[index].setting_offset); + if (ret < 0) { + // Validation failed + return ret; + } + } + } + + return CFG_SETTINGS_OK; +} + +int8_t ws_cfg_settings_set(protocol_interface_info_entry_t *cur, ws_cfg_t *new_cfg) +{ + int8_t ret_value = CFG_SETTINGS_OK; + + bool call_cfg_set[CFG_CB_NUM]; + + // Validate new configuration values + for (uint8_t index = 0; index < CFG_CB_NUM; index++) { + if (cfg_cb[index].validate) { + int8_t ret = cfg_cb[index].validate( + ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, + ((uint8_t *)new_cfg) + cfg_cb[index].setting_offset); + + if (ret < 0) { + // Validation failed + return ret; + } else if (ret == CFG_SETTINGS_CHANGED) { + call_cfg_set[index] = true; + } else { + call_cfg_set[index] = false; + } + } else { + // If validation not needed, set right away + call_cfg_set[index] = true; + } + } + + // Set new configuration values + for (uint8_t index = 0; index < CFG_CB_NUM; index++) { + uint8_t flags = 0; + // Validation + if (call_cfg_set[index]) { + if (cfg_cb[index].set(cur, + ((uint8_t *)&ws_cfg) + cfg_cb[index].setting_offset, + ((uint8_t *)new_cfg) + cfg_cb[index].setting_offset, &flags) < 0) { + tr_info("FATAL CONFIG FAILURE"); + ret_value = CFG_SETTINGS_OTHER_ERROR; + } + } + } + + return ret_value; +} + +#endif //HAVE_WS diff --git a/source/6LoWPAN/ws/ws_cfg_settings.h b/source/6LoWPAN/ws/ws_cfg_settings.h new file mode 100644 index 0000000000..334489d513 --- /dev/null +++ b/source/6LoWPAN/ws/ws_cfg_settings.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2020, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef WS_CFG_STORAGE_H_ +#define WS_CFG_STORAGE_H_ + +/** + * \brief Struct ws_gen_cfg_t General configuration + */ +typedef struct ws_gen_cfg_s { + /* Changing the network size resets the configuration settings depending on it to + default values */ + uint8_t network_size; /**< Network size selection; default medium (= 8) */ + char network_name[33]; /**< Network name; max 32 octets + terminating 0 */ + uint16_t network_pan_id; /**< PAN identifier; PAN_ID; default 0xffff */ +} ws_gen_cfg_t; + +/** + * \brief Struct ws_phy_cfg_t Physical layer configuration + */ +typedef struct ws_phy_cfg_s { + uint8_t regulatory_domain; /**< PHY regulatory domain; default "KR" 0x09 */ + uint8_t operating_class; /**< PHY operating class; default 1 */ + uint8_t operating_mode; /**< PHY operating mode; default "1b" symbol rate 50, modulation index 1 */ +} ws_phy_cfg_t; + +/** + * \brief Struct ws_timing_cfg_t Timing configuration + */ +typedef struct ws_timing_cfg_s { + uint16_t disc_trickle_imin; /**< Discovery trickle Imin; DISC_IMIN; seconds; range 1-255; default 30 */ + uint16_t disc_trickle_imax; /**< Discovery trickle Imax; DISC_IMAX; seconds; range (2-2^8)*Imin‬; default 960 */ + uint8_t disc_trickle_k; /**< Discovery trickle k; DISC_K; default 1 */ + uint16_t pan_timeout; /**< PAN timeout; PAN_TIMEOUT; seconds; range 60-15300; default 3840 */ + uint16_t temp_link_min_timeout; /**< Temporary neighbor link minimum timeout; seconds; default 260 */ +} ws_timing_cfg_t; + +/** + * \brief Struct ws_rpl_cfg_t RPL configuration + */ +typedef struct ws_rpl_cfg_s { + uint8_t dio_interval_min; /**> DIO interval min; DEFAULT_DIO_INTERVAL_MIN; 2^value in milliseconds; range 1-255; default */ + uint8_t dio_interval_doublings; /**> DIO interval doublings; DEFAULT_DIO_INTERVAL_DOUBLINGS; range 1-8; default */ + uint8_t dio_redundancy_constant; /**> DIO redundancy constant; DEFAULT_DIO_REDUNDANCY_CONSTANT; range 0-10; default */ + uint16_t dag_max_rank_increase; + uint16_t min_hop_rank_increase; + uint16_t rpl_parent_candidate_max; /**< RPL parent candidate maximum value; default 5 */ + uint16_t rpl_selected_parent_max; /**< RPL selected parent maximum value; default 2 */ +} ws_rpl_cfg_t; + +/** + * \brief Struct ws_fhss_cfg_t Frequency hopping configuration + */ +typedef struct ws_fhss_cfg_s { + uint8_t fhss_uc_dwell_interval; /**< FHSS unicast dwell interval; range 15-250 milliseconds; default 255 */ + uint8_t fhss_bc_dwell_interval; /**< FHSS broadcast dwell interval; range 15-250 milliseconds; default 255 */ + uint32_t fhss_bc_interval; /**< FHSS broadcast interval; duration between broadcast dwell intervals. range: 0-16777216 milliseconds; default 1020 */ + uint8_t fhss_uc_channel_function; /**< FHSS WS unicast channel function; default 2 direct hash channel function */ + uint8_t fhss_bc_channel_function; /**< FHSS WS broadcast channel function; default 2 direct hash channel function */ + uint16_t fhss_uc_fixed_channel; /**< FHSS unicast fixed channel; default 0xffff */ + uint16_t fhss_bc_fixed_channel; /**< FHSS broadcast fixed channel; default 0xffff */ + uint32_t fhss_channel_mask[8]; /**< FHSS channel mask; default; 0xffffffff * 8 */ +} ws_fhss_cfg_t; + +/** + * \brief Struct ws_mpl_cfg_t Multicast configuration + */ +typedef struct ws_mpl_cfg_s { + uint16_t mpl_trickle_imin; /**< MPL trickle parameters Imin; DATA_MESSAGE_IMIN; seconds; range 1-255; default 10 */ + uint16_t mpl_trickle_imax; /**< MPL trickle parameters Imax; DATA_MESSAGE_IMAX; seconds; range (2-2^8)*Imin‬; default 10 */ + uint8_t mpl_trickle_k; /**< MPL trickle parameters k; default 8 */ + uint8_t mpl_trickle_timer_exp; /**< MPL trickle parameters timer expirations; default 3 */ + uint16_t seed_set_entry_lifetime; /**< MPL minimum seed set lifetime; seconds; default 960 */ +} ws_mpl_cfg_t; + +/** + * \brief Struct ws_sec_timer_cfg_t Security timers configuration + */ +typedef struct ws_sec_timer_cfg_s { + uint32_t gtk_expire_offset; /**< GTK lifetime; GTK_EXPIRE_OFFSET; minutes; default 43200 */ + uint32_t pmk_lifetime; /**< PMK lifetime; minutes; default 172800 */ + uint32_t ptk_lifetime; /**< PTK lifetime; minutes; default 86400 */ + uint16_t gtk_new_act_time; /**< GTK_NEW_ACTIVATION_TIME (1/X of expire offset); default 720 */ + uint16_t revocat_lifetime_reduct; /**< REVOCATION_LIFETIME_REDUCTION (reduction of lifetime); default 30 */ + uint16_t gtk_request_imin; /**< GTK_REQUEST_IMIN; minutes; range 1-255; default 4 */ + uint16_t gtk_request_imax; /**< GTK_REQUEST_IMAX; minutes; range (2-2^8)*Imin; default 64 */ + uint16_t gtk_max_mismatch; /**< GTK_MAX_MISMATCH; minutes; default 64 */ + uint8_t gtk_new_install_req; /**< GTK_NEW_INSTALL_REQUIRED; percent of GTK lifetime; range 1-100; default 80 */ +} ws_sec_timer_cfg_t; + +/** + * \brief Struct ws_sec_prot_cfg_t Security protocols configuration + */ +typedef struct ws_sec_prot_cfg_s { + uint16_t sec_prot_retry_timeout; /**< Security protocol retry timeout; seconds; default 330 */ + uint16_t sec_prot_trickle_imin; /**< Security protocol trickle parameters Imin; seconds; default 30 */ + uint16_t sec_prot_trickle_imax; /**< Security protocol trickle parameters Imax; seconds; default 90 */ + uint8_t sec_prot_trickle_timer_exp; /**< Security protocol trickle timer expirations; default 2 */ + uint16_t sec_max_ongoing_authentication; /**< Pae authenticator max Accept ongoing authentication count */ +} ws_sec_prot_cfg_t; + +/** + * \brief Struct ws_nw_size_cfg_t Network size configuration + */ +typedef struct ws_cfg_s { + ws_gen_cfg_t gen; /**< General configuration */ + ws_phy_cfg_t phy; /**< Physical layer configuration */ + ws_timing_cfg_t timing; /**< Timing configuration */ + ws_rpl_cfg_t rpl; /**< RPL configuration */ + ws_fhss_cfg_t fhss; /**< Frequency hopping configuration */ + ws_mpl_cfg_t mpl; /**< Multicast configuration */ + ws_sec_timer_cfg_t sec_timer; /**< Security timers configuration */ + ws_sec_prot_cfg_t sec_prot; /**< Security protocols configuration */ +} ws_cfg_t; + +/** Configuration setting errors. */ +#define CFG_SETTINGS_PARAMETER_ERROR -1 /**< Function parameter error */ +#define CFG_SETTINGS_OTHER_ERROR -2 /**< Other error */ +#define CFG_SETTINGS_ERROR_NW_SIZE_CONF -10 /**< Network size configuration error */ +#define CFG_SETTINGS_ERROR_GEN_CONF -11 /**< General configuration error */ +#define CFG_SETTINGS_ERROR_PHY_CONF -12 /**< Physical layer configuration error */ +#define CFG_SETTINGS_ERROR_TIMING_CONF -13 /**< Timing configuration error */ +#define CFG_SETTINGS_ERROR_RPL_CONF -14 /**< RPL configuration error */ +#define CFG_SETTINGS_ERROR_FHSS_CONF -15 /**< Frequency hopping configuration error */ +#define CFG_SETTINGS_ERROR_MPL_CONF -16 /**< Multicast configuration error */ +#define CFG_SETTINGS_ERROR_SEC_TIMER_CONF -17 /**< Security timers configuration error */ +#define CFG_SETTINGS_ERROR_SEC_PROT_CONF -18 /**< Security protocols configuration error */ + +int8_t ws_cfg_settings_init(void); +int8_t ws_cfg_settings_default_set(void); +int8_t ws_cfg_settings_interface_set(protocol_interface_info_entry_t *cur); +int8_t ws_cfg_network_size_configure(protocol_interface_info_entry_t *cur, uint16_t network_size); + +int8_t ws_cfg_network_size_get(ws_gen_cfg_t *cfg, uint8_t *flags); +int8_t ws_cfg_network_size_validate(ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg); +int8_t ws_cfg_network_size_set(protocol_interface_info_entry_t *cur, ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg, uint8_t *flags); + +int8_t ws_cfg_gen_get(ws_gen_cfg_t *cfg, uint8_t *flags); +int8_t ws_cfg_gen_validate(ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg); +int8_t ws_cfg_gen_set(protocol_interface_info_entry_t *cur, ws_gen_cfg_t *cfg, ws_gen_cfg_t *new_cfg, uint8_t *flags); + +int8_t ws_cfg_phy_get(ws_phy_cfg_t *cfg, uint8_t *flags); +int8_t ws_cfg_phy_validate(ws_phy_cfg_t *cfg, ws_phy_cfg_t *new_cfg); +int8_t ws_cfg_phy_set(protocol_interface_info_entry_t *cur, ws_phy_cfg_t *cfg, ws_phy_cfg_t *new_cfg, uint8_t *flags); + +int8_t ws_cfg_timing_get(ws_timing_cfg_t *cfg, uint8_t *flags); +int8_t ws_cfg_timing_validate(ws_timing_cfg_t *cfg, ws_timing_cfg_t *new_cfg); +int8_t ws_cfg_timing_set(protocol_interface_info_entry_t *cur, ws_timing_cfg_t *cfg, ws_timing_cfg_t *new_cfg, uint8_t *flags); + +int8_t ws_cfg_rpl_get(ws_rpl_cfg_t *cfg, uint8_t *flags); +int8_t ws_cfg_rpl_validate(ws_rpl_cfg_t *cfg, ws_rpl_cfg_t *new_cfg); +int8_t ws_cfg_rpl_set(protocol_interface_info_entry_t *cur, ws_rpl_cfg_t *cfg, ws_rpl_cfg_t *new_cfg, uint8_t *flags); + +int8_t ws_cfg_mpl_get(ws_mpl_cfg_t *cfg, uint8_t *flags); +int8_t ws_cfg_mpl_validate(ws_mpl_cfg_t *cfg, ws_mpl_cfg_t *new_cfg); +int8_t ws_cfg_mpl_set(protocol_interface_info_entry_t *cur, ws_mpl_cfg_t *cfg, ws_mpl_cfg_t *new_cfg, uint8_t *flags); + +int8_t ws_cfg_fhss_get(ws_fhss_cfg_t *cfg, uint8_t *flags); +int8_t ws_cfg_fhss_validate(ws_fhss_cfg_t *cfg, ws_fhss_cfg_t *new_cfg); +int8_t ws_cfg_fhss_set(protocol_interface_info_entry_t *cur, ws_fhss_cfg_t *cfg, ws_fhss_cfg_t *new_cfg, uint8_t *flags); + +int8_t ws_cfg_sec_timer_get(ws_sec_timer_cfg_t *cfg, uint8_t *flags); +int8_t ws_cfg_sec_timer_validate(ws_sec_timer_cfg_t *cfg, ws_sec_timer_cfg_t *new_cfg); +int8_t ws_cfg_sec_timer_set(protocol_interface_info_entry_t *cur, ws_sec_timer_cfg_t *cfg, ws_sec_timer_cfg_t *new_cfg, uint8_t *flags); + +int8_t ws_cfg_sec_prot_get(ws_sec_prot_cfg_t *cfg, uint8_t *flags); +int8_t ws_cfg_sec_prot_validate(ws_sec_prot_cfg_t *cfg, ws_sec_prot_cfg_t *new_cfg); +int8_t ws_cfg_sec_prot_set(protocol_interface_info_entry_t *cur, ws_sec_prot_cfg_t *cfg, ws_sec_prot_cfg_t *new_cfg, uint8_t *flags); + +#endif // WS_CFG_STORAGE_H_ diff --git a/source/6LoWPAN/ws/ws_common.c b/source/6LoWPAN/ws/ws_common.c index f89fbaa748..7bfb66df4e 100644 --- a/source/6LoWPAN/ws/ws_common.c +++ b/source/6LoWPAN/ws/ws_common.c @@ -29,6 +29,7 @@ #include "6LoWPAN/ws/ws_bootstrap.h" #include "6LoWPAN/ws/ws_bbr_api_internal.h" #include "6LoWPAN/ws/ws_pae_controller.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" #include "Service_Libs/etx/etx.h" #include "Service_Libs/mac_neighbor_table/mac_neighbor_table.h" #include "Service_Libs/blacklist/blacklist.h" @@ -44,30 +45,7 @@ // This provides a range of -174 (0) to +80 (254) dBm uint8_t DEVICE_MIN_SENS = 174 - 93; -#define TRICKLE_IMIN_60_SECS (60 * 10) -#define TRICKLE_IMIN_30_SECS (30 * 10) -#define TRICKLE_IMIN_15_SECS (15 * 10) -static const trickle_params_t trickle_params_pan_discovery_large = { - .Imin = TRICKLE_IMIN_60_SECS, /* 60 second; ticks are 1s */ - .Imax = TRICKLE_IMIN_60_SECS << 4, /* 960 seconds 16 min*/ - .k = 1, /* 1 */ - .TimerExpirations = TRICKLE_EXPIRATIONS_INFINITE -}; - -static const trickle_params_t trickle_params_pan_discovery_medium = { - .Imin = TRICKLE_IMIN_30_SECS, /* 30 second; ticks are 1s */ - .Imax = TRICKLE_IMIN_30_SECS << 5, /* 960 seconds 16 min*/ - .k = 1, /* 1 */ - .TimerExpirations = TRICKLE_EXPIRATIONS_INFINITE -}; - -static const trickle_params_t trickle_params_pan_discovery_small = { - .Imin = TRICKLE_IMIN_15_SECS, /* 15 second; ticks are 1s */ - .Imax = TRICKLE_IMIN_15_SECS << 2, /* 60 seconds 1 min*/ - .k = 1, /* 1 */ - .TimerExpirations = TRICKLE_EXPIRATIONS_INFINITE -}; uint16_t test_max_child_count_override = 0xffff; @@ -81,7 +59,7 @@ int8_t ws_generate_channel_list(uint32_t *channel_mask, uint16_t number_of_chann return 0; } -static uint32_t ws_decode_channel_spacing(uint8_t channel_spacing) +uint32_t ws_decode_channel_spacing(uint8_t channel_spacing) { if (CHANNEL_SPACING_100 == channel_spacing) { return 100000; @@ -97,7 +75,7 @@ static uint32_t ws_decode_channel_spacing(uint8_t channel_spacing) return 0; } -static uint32_t ws_get_datarate_using_operating_mode(uint8_t operating_mode) +uint32_t ws_get_datarate_using_operating_mode(uint8_t operating_mode) { if ((OPERATING_MODE_1a == operating_mode) || (OPERATING_MODE_1b == operating_mode)) { return 50000; @@ -113,7 +91,7 @@ static uint32_t ws_get_datarate_using_operating_mode(uint8_t operating_mode) return 0; } -static phy_modulation_index_e ws_get_modulation_index_using_operating_mode(uint8_t operating_mode) +phy_modulation_index_e ws_get_modulation_index_using_operating_mode(uint8_t operating_mode) { if ((OPERATING_MODE_1b == operating_mode) || (OPERATING_MODE_2b == operating_mode) || (OPERATING_MODE_4b == operating_mode)) { return MODULATION_INDEX_1_0; @@ -122,105 +100,95 @@ static phy_modulation_index_e ws_get_modulation_index_using_operating_mode(uint8 } } -static int ws_set_domain_rf_config(protocol_interface_info_entry_t *cur) +int8_t ws_common_regulatory_domain_config(protocol_interface_info_entry_t *cur, ws_hopping_schedule_t *hopping_schdule) { - phy_rf_channel_configuration_s rf_configs; - rf_configs.channel_0_center_frequency = (uint32_t)cur->ws_info->hopping_schdule.ch0_freq * 100000; - rf_configs.channel_spacing = ws_decode_channel_spacing(cur->ws_info->hopping_schdule.channel_spacing); - rf_configs.datarate = ws_get_datarate_using_operating_mode(cur->ws_info->hopping_schdule.operating_mode); - rf_configs.modulation_index = ws_get_modulation_index_using_operating_mode(cur->ws_info->hopping_schdule.operating_mode); - rf_configs.modulation = M_2FSK; - rf_configs.number_of_channels = cur->ws_info->hopping_schdule.number_of_channels; - ws_bootstrap_set_rf_config(cur, rf_configs); - return 0; -} + (void)cur; + if (ws_get_datarate_using_operating_mode(hopping_schdule->operating_mode) == 0) { + //Unsupported operation mode + return -1; + } -int8_t ws_common_regulatory_domain_config(protocol_interface_info_entry_t *cur) -{ - cur->ws_info->hopping_schdule.channel_plan = 0; + hopping_schdule->channel_plan = 0; - if (cur->ws_info->hopping_schdule.regulatory_domain == REG_DOMAIN_KR) { - if (cur->ws_info->hopping_schdule.operating_class == 1) { - cur->ws_info->hopping_schdule.ch0_freq = 9171; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_200; - } else if (cur->ws_info->hopping_schdule.operating_class == 2) { - cur->ws_info->hopping_schdule.ch0_freq = 9173; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_400; + if (hopping_schdule->regulatory_domain == REG_DOMAIN_KR) { + if (hopping_schdule->operating_class == 1) { + hopping_schdule->ch0_freq = 9171; + hopping_schdule->channel_spacing = CHANNEL_SPACING_200; + } else if (hopping_schdule->operating_class == 2) { + hopping_schdule->ch0_freq = 9173; + hopping_schdule->channel_spacing = CHANNEL_SPACING_400; } else { return -1; } - } else if (cur->ws_info->hopping_schdule.regulatory_domain == REG_DOMAIN_EU) { - if (cur->ws_info->hopping_schdule.operating_class == 1) { - cur->ws_info->hopping_schdule.ch0_freq = 8631; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_100; - } else if (cur->ws_info->hopping_schdule.operating_class == 2) { - cur->ws_info->hopping_schdule.ch0_freq = 8631; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_200; - } else if (cur->ws_info->hopping_schdule.operating_class == 3) { - cur->ws_info->hopping_schdule.ch0_freq = 8701; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_100; - } else if (cur->ws_info->hopping_schdule.operating_class == 4) { - cur->ws_info->hopping_schdule.ch0_freq = 8702; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_200; + } else if (hopping_schdule->regulatory_domain == REG_DOMAIN_EU) { + if (hopping_schdule->operating_class == 1) { + hopping_schdule->ch0_freq = 8631; + hopping_schdule->channel_spacing = CHANNEL_SPACING_100; + } else if (hopping_schdule->operating_class == 2) { + hopping_schdule->ch0_freq = 8631; + hopping_schdule->channel_spacing = CHANNEL_SPACING_200; + } else if (hopping_schdule->operating_class == 3) { + hopping_schdule->ch0_freq = 8701; + hopping_schdule->channel_spacing = CHANNEL_SPACING_100; + } else if (hopping_schdule->operating_class == 4) { + hopping_schdule->ch0_freq = 8702; + hopping_schdule->channel_spacing = CHANNEL_SPACING_200; } else { return -1; } - } else if (cur->ws_info->hopping_schdule.regulatory_domain == REG_DOMAIN_IN) { - if (cur->ws_info->hopping_schdule.operating_class == 1) { - cur->ws_info->hopping_schdule.ch0_freq = 8651; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_100; - } else if (cur->ws_info->hopping_schdule.operating_class == 2) { - cur->ws_info->hopping_schdule.ch0_freq = 8651; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_200; + } else if (hopping_schdule->regulatory_domain == REG_DOMAIN_IN) { + if (hopping_schdule->operating_class == 1) { + hopping_schdule->ch0_freq = 8651; + hopping_schdule->channel_spacing = CHANNEL_SPACING_100; + } else if (hopping_schdule->operating_class == 2) { + hopping_schdule->ch0_freq = 8651; + hopping_schdule->channel_spacing = CHANNEL_SPACING_200; } else { return -1; } - } else if (cur->ws_info->hopping_schdule.regulatory_domain == REG_DOMAIN_NA) { - if (cur->ws_info->hopping_schdule.operating_class == 1) { - cur->ws_info->hopping_schdule.ch0_freq = 9022; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_200; - } else if (cur->ws_info->hopping_schdule.operating_class == 2) { - cur->ws_info->hopping_schdule.ch0_freq = 9024; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_400; - } else if (cur->ws_info->hopping_schdule.operating_class == 3) { - cur->ws_info->hopping_schdule.ch0_freq = 9026; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_600; + } else if (hopping_schdule->regulatory_domain == REG_DOMAIN_NA) { + if (hopping_schdule->operating_class == 1) { + hopping_schdule->ch0_freq = 9022; + hopping_schdule->channel_spacing = CHANNEL_SPACING_200; + } else if (hopping_schdule->operating_class == 2) { + hopping_schdule->ch0_freq = 9024; + hopping_schdule->channel_spacing = CHANNEL_SPACING_400; + } else if (hopping_schdule->operating_class == 3) { + hopping_schdule->ch0_freq = 9026; + hopping_schdule->channel_spacing = CHANNEL_SPACING_600; } else { return -1; } - } else if (cur->ws_info->hopping_schdule.regulatory_domain == REG_DOMAIN_JP) { - if (cur->ws_info->hopping_schdule.operating_class == 1) { - cur->ws_info->hopping_schdule.ch0_freq = 9206; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_200; - } else if (cur->ws_info->hopping_schdule.operating_class == 2) { - cur->ws_info->hopping_schdule.ch0_freq = 9209; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_400; - } else if (cur->ws_info->hopping_schdule.operating_class == 3) { - cur->ws_info->hopping_schdule.ch0_freq = 9208; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_600; + } else if (hopping_schdule->regulatory_domain == REG_DOMAIN_JP) { + if (hopping_schdule->operating_class == 1) { + hopping_schdule->ch0_freq = 9206; + hopping_schdule->channel_spacing = CHANNEL_SPACING_200; + } else if (hopping_schdule->operating_class == 2) { + hopping_schdule->ch0_freq = 9209; + hopping_schdule->channel_spacing = CHANNEL_SPACING_400; + } else if (hopping_schdule->operating_class == 3) { + hopping_schdule->ch0_freq = 9208; + hopping_schdule->channel_spacing = CHANNEL_SPACING_600; } else { return -1; } - } else if (cur->ws_info->hopping_schdule.regulatory_domain == REG_DOMAIN_WW) { - if (cur->ws_info->hopping_schdule.operating_class == 1) { - cur->ws_info->hopping_schdule.ch0_freq = 24002; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_200; - } else if (cur->ws_info->hopping_schdule.operating_class == 2) { - cur->ws_info->hopping_schdule.ch0_freq = 24004; - cur->ws_info->hopping_schdule.channel_spacing = CHANNEL_SPACING_400; + } else if (hopping_schdule->regulatory_domain == REG_DOMAIN_WW) { + if (hopping_schdule->operating_class == 1) { + hopping_schdule->ch0_freq = 24002; + hopping_schdule->channel_spacing = CHANNEL_SPACING_200; + } else if (hopping_schdule->operating_class == 2) { + hopping_schdule->ch0_freq = 24004; + hopping_schdule->channel_spacing = CHANNEL_SPACING_400; } else { return -1; } } else { return -1; } - cur->ws_info->hopping_schdule.number_of_channels = (uint8_t)ws_common_channel_number_calc(cur->ws_info->hopping_schdule.regulatory_domain, cur->ws_info->hopping_schdule.operating_class); - if (!cur->ws_info->hopping_schdule.number_of_channels) { + hopping_schdule->number_of_channels = (uint8_t)ws_common_channel_number_calc(hopping_schdule->regulatory_domain, hopping_schdule->operating_class); + if (!hopping_schdule->number_of_channels) { return -1; } - // Note: doesn't work for Brazil region - ws_generate_channel_list(cur->ws_info->hopping_schdule.channel_mask, cur->ws_info->hopping_schdule.number_of_channels, cur->ws_info->hopping_schdule.regulatory_domain); - ws_set_domain_rf_config(cur); return 0; } @@ -292,10 +260,13 @@ int8_t ws_common_allocate_and_init(protocol_interface_info_entry_t *cur) ns_list_init(&cur->ws_info->parent_list_free); ns_list_init(&cur->ws_info->parent_list_reserved); + cur->ws_info->network_pan_id = 0xffff; cur->ws_info->pan_information.use_parent_bs = true; cur->ws_info->pan_information.rpl_routing_method = true; cur->ws_info->pan_information.version = WS_FAN_VERSION_1_0; + cur->ws_info->pending_key_index_info.state = NO_PENDING_PROCESS; + cur->ws_info->hopping_schdule.regulatory_domain = REG_DOMAIN_EU; cur->ws_info->hopping_schdule.operating_mode = OPERATING_MODE_3; cur->ws_info->hopping_schdule.operating_class = 2; @@ -303,70 +274,12 @@ int8_t ws_common_allocate_and_init(protocol_interface_info_entry_t *cur) cur->ws_info->hopping_schdule.clock_drift = 255; // Timing accuracy is given from 0 to 2.55msec with 10usec resolution cur->ws_info->hopping_schdule.timing_accurancy = 100; - ws_common_regulatory_domain_config(cur); - cur->ws_info->network_size_config = NETWORK_SIZE_MEDIUM; - cur->ws_info->rpl_parent_candidate_max = WS_RPL_PARENT_CANDIDATE_MAX; - cur->ws_info->rpl_selected_parent_max = WS_RPL_SELECTED_PARENT_MAX; - ws_common_network_size_configure(cur, 200); // defaults to medium network size - - // Set defaults for the device. user can modify these. - cur->ws_info->fhss_uc_fixed_channel = 0xffff; - cur->ws_info->fhss_bc_fixed_channel = 0xffff; - cur->ws_info->fhss_uc_dwell_interval = WS_FHSS_UC_DWELL_INTERVAL; - cur->ws_info->fhss_bc_interval = WS_FHSS_BC_INTERVAL; - cur->ws_info->fhss_bc_dwell_interval = WS_FHSS_BC_DWELL_INTERVAL; - cur->ws_info->fhss_uc_channel_function = WS_DH1CF; - cur->ws_info->fhss_bc_channel_function = WS_DH1CF; - + ws_common_regulatory_domain_config(cur, &cur->ws_info->hopping_schdule); cur->ws_info->pending_key_index_info.state = NO_PENDING_PROCESS; - for (uint8_t n = 0; n < 8; n++) { - cur->ws_info->fhss_channel_mask[n] = 0xffffffff; - } return 0; } -void ws_common_network_size_configure(protocol_interface_info_entry_t *cur, uint16_t network_size) -{ - // TODO Modify NUD timings based on network size - // TODO Modify EAPOLL timings - - if (network_size < 100) { - // Configure the Wi-SUN discovery trickle parameters - cur->ws_info->trickle_params_pan_discovery = trickle_params_pan_discovery_small; - // default values are for Wi-SUN small network parameters - // imin: 14 (16s) - // doublings:3 (128s) - // redundancy; 0 Disabled - if (cur->ws_info->network_size_config == NETWORK_SIZE_AUTOMATIC) { - ws_bbr_rpl_config(cur, 14, 3, 0, WS_RPL_MAX_HOP_RANK_INCREASE, WS_RPL_MIN_HOP_RANK_INCREASE); - } else if (cur->ws_info->network_size_config == NETWORK_SIZE_CERTIFICATE) { - ws_bbr_rpl_config(cur, 0, 0, 0, WS_CERTIFICATE_RPL_MAX_HOP_RANK_INCREASE, WS_CERTIFICATE_RPL_MIN_HOP_RANK_INCREASE); - } else { - ws_bbr_rpl_config(cur, 0, 0, 0, WS_RPL_MAX_HOP_RANK_INCREASE, WS_RPL_MIN_HOP_RANK_INCREASE); - } - ws_pae_controller_timing_adjust(1); // Fast and reactive network - } else if (network_size < 300) { - // Configure the Wi-SUN discovery trickle parameters - cur->ws_info->trickle_params_pan_discovery = trickle_params_pan_discovery_medium; - // Something in between - // imin: 15 (32s) - // doublings:5 (960s) - // redundancy; 10 - ws_bbr_rpl_config(cur, 15, 5, 10, WS_RPL_MAX_HOP_RANK_INCREASE, WS_RPL_MIN_HOP_RANK_INCREASE); - ws_pae_controller_timing_adjust(9); // medium limited network - } else { - // Configure the Wi-SUN discovery trickle parameters - cur->ws_info->trickle_params_pan_discovery = trickle_params_pan_discovery_large; - // Wi-SUN Large network parameters - // imin: 19 (524s, 9 min) - // doublings:1 (1048s, 17 min) - // redundancy; 10 May need some tuning still - ws_bbr_rpl_config(cur, 19, 1, 10, WS_RPL_MAX_HOP_RANK_INCREASE, WS_RPL_MIN_HOP_RANK_INCREASE); - ws_pae_controller_timing_adjust(24); // Very slow and high latency network - } - return; -} void ws_common_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds) { @@ -418,6 +331,14 @@ uint8_t ws_common_allow_child_registration(protocol_interface_info_entry_t *inte //Validate Is EUI64 already allocated for any address if (ipv6_neighbour_has_registered_by_eui64(&interface->ipv6_neighbour_cache, eui64)) { + /* + * ARO registration from child can update the link timeout so we don't need to send extra NUD if ARO received + */ + mac_neighbor_table_entry_t *mac_neighbor = mac_neighbor_entry_get_by_mac64(mac_neighbor_info(interface), eui64, false, false); + + if (mac_neighbor) { + mac_neighbor_table_neighbor_refresh(mac_neighbor_info(interface), mac_neighbor, mac_neighbor->link_lifetime); + } tr_info("Child registration from old child"); return ARO_SUCCESS; } @@ -456,35 +377,53 @@ bool ws_common_negative_aro_mark(protocol_interface_info_entry_t *interface, con return true; } -uint32_t ws_common_version_lifetime_get(uint8_t config) +uint32_t ws_common_latency_estimate_get(protocol_interface_info_entry_t *cur) { - uint32_t lifetime; - if (config == NETWORK_SIZE_SMALL || config == NETWORK_SIZE_CERTIFICATE) { - lifetime = PAN_VERSION_SMALL_NETWORK_LIFETIME; - } else if (config == NETWORK_SIZE_MEDIUM) { - lifetime = PAN_VERSION_MEDIUM_NETWORK_LIFETIME; - } else { - lifetime = PAN_VERSION_LARGE_NETWORK_LIFETIME; + uint32_t latency = 0; + uint8_t network_size = cur->ws_info->cfg->gen.network_size; + + if (network_size == NETWORK_SIZE_AUTOMATIC) { + network_size = cur->ws_info->pan_information.pan_size / 100; } - return lifetime; - -} - -uint32_t ws_common_version_timeout_get(uint8_t config) -{ - uint32_t lifetime; - if (config == NETWORK_SIZE_SMALL || config == NETWORK_SIZE_CERTIFICATE) { - lifetime = PAN_VERSION_SMALL_NETWORK_TIMEOUT; - } else if (config == NETWORK_SIZE_MEDIUM) { - lifetime = PAN_VERSION_MEDIUM_NETWORK_TIMEOUT; - } else { - lifetime = PAN_VERSION_LARGE_NETWORK_TIMEOUT; + if (network_size <= NETWORK_SIZE_SMALL) { + // handles also NETWORK_SIZE_CERTIFICATE + latency = 8000; + } else if (network_size <= NETWORK_SIZE_MEDIUM) { + latency = 16000; + } else { + latency = 32000; } - return lifetime; + return latency; } +uint32_t ws_common_datarate_get(protocol_interface_info_entry_t *cur) +{ + return ws_get_datarate_using_operating_mode(cur->ws_info->hopping_schdule.operating_mode); +} + +uint32_t ws_common_network_size_estimate_get(protocol_interface_info_entry_t *cur) +{ + uint32_t network_size_estimate = 0; + uint8_t network_size = cur->ws_info->cfg->gen.network_size; + + if (network_size == NETWORK_SIZE_AUTOMATIC) { + network_size = cur->ws_info->pan_information.pan_size / 100; + } + + if (network_size <= NETWORK_SIZE_SMALL) { + // tens of devices (now 30), handles also NETWORK_SIZE_CERTIFICATE + network_size_estimate = 30; + } else if (network_size <= NETWORK_SIZE_MEDIUM) { + // hundreds of devices (now 300) + network_size_estimate = 300; + } else { + // huge amount of devices (now 1000) + network_size_estimate = 1000; + } + + return network_size_estimate; +} #endif // HAVE_WS - diff --git a/source/6LoWPAN/ws/ws_common.h b/source/6LoWPAN/ws/ws_common.h index 588902753f..3aa154c052 100644 --- a/source/6LoWPAN/ws/ws_common.h +++ b/source/6LoWPAN/ws/ws_common.h @@ -35,6 +35,8 @@ extern uint16_t test_max_child_count_override; struct ws_pan_information_s; struct ws_neighbor_class_s; +struct ws_excluded_channel_data_s; +struct ws_cfg_s; typedef struct parent_info_s { uint16_t pan_id; /**< PAN ID */ @@ -46,6 +48,7 @@ typedef struct parent_info_s { ws_us_ie_t ws_us; uint32_t timestamp; /**< Timestamp when packet was received */ uint32_t age; /**< Age of entry in 100ms ticks */ + uint8_t excluded_channel_data[32]; //Channel mask Max length and it accept 8 different range ns_list_link_t link; } parent_info_t; @@ -72,45 +75,33 @@ typedef struct { typedef NS_LIST_HEAD(ws_nud_table_entry_t, link) ws_nud_table_list_t; typedef struct ws_info_s { - char network_name[33]; // Network name max 32 octets + terminating 0. - uint16_t network_pan_id; - trickle_t trickle_pan_config_solicit; trickle_t trickle_pan_config; trickle_t trickle_pan_advertisement_solicit; trickle_t trickle_pan_advertisement; trickle_params_t trickle_params_pan_discovery; - uint8_t network_size_config; // configuration for network size selection of application. - uint16_t rpl_parent_candidate_max; - uint16_t rpl_selected_parent_max; uint8_t rpl_state; // state from rpl_event_t uint8_t pas_requests; // Amount of PAN solicits sent parent_info_t parent_info[WS_PARENT_LIST_SIZE]; parent_info_list_t parent_list_free; parent_info_list_t parent_list_reserved; + uint16_t aro_registration_timer; /**< Aro registration timer */ uint16_t rpl_version_timer; /**< RPL version update timeout */ - uint32_t pan_version_timer; /**< border router version update timeout */ - uint32_t pan_version_timeout_timer; /**< routers will fallback to previous state after this */ + uint32_t pan_timeout_timer; /**< routers will fallback to previous state after this */ uint32_t pan_config_sol_max_timeout; uint8_t gtkhash[32]; + uint16_t network_pan_id; bool configuration_learned: 1; bool trickle_pas_running: 1; bool trickle_pa_running: 1; bool trickle_pcs_running: 1; bool trickle_pc_running: 1; + uint16_t trickle_pc_consistency_block_period; ws_pending_key_index_t pending_key_index_info; - // default fhss parameters for this device - uint8_t fhss_uc_dwell_interval; - uint8_t fhss_bc_dwell_interval; - uint32_t fhss_bc_interval; - uint8_t fhss_uc_channel_function; - uint8_t fhss_bc_channel_function; - uint16_t fhss_uc_fixed_channel; - uint16_t fhss_bc_fixed_channel; - uint32_t fhss_channel_mask[8]; ws_nud_table_entry_t nud_table_entrys[ACTIVE_NUD_PROCESS_MAX]; ws_nud_table_list_t active_nud_process; ws_nud_table_list_t free_nud_entries; + struct ws_cfg_s *cfg; /**< Wi-SUN configuration */ struct ws_pan_information_s pan_information; ws_hopping_schedule_t hopping_schdule; struct ws_statistics *stored_stats_ptr; @@ -123,14 +114,18 @@ typedef struct ws_info_s { int8_t ws_generate_channel_list(uint32_t *channel_mask, uint16_t number_of_channels, uint8_t regulatory_domain); -int8_t ws_common_regulatory_domain_config(protocol_interface_info_entry_t *cur); +uint32_t ws_decode_channel_spacing(uint8_t channel_spacing); + +uint32_t ws_get_datarate_using_operating_mode(uint8_t operating_mode); + +phy_modulation_index_e ws_get_modulation_index_using_operating_mode(uint8_t operating_mode); + +int8_t ws_common_regulatory_domain_config(protocol_interface_info_entry_t *cur, ws_hopping_schedule_t *hopping_schdule); uint16_t ws_common_channel_number_calc(uint8_t regulatory_domain, uint8_t operating_class); int8_t ws_common_allocate_and_init(protocol_interface_info_entry_t *cur); -void ws_common_network_size_configure(protocol_interface_info_entry_t *cur, uint16_t network_size); - void ws_common_seconds_timer(protocol_interface_info_entry_t *cur, uint32_t seconds); void ws_common_fast_timer(protocol_interface_info_entry_t *cur, uint16_t ticks); @@ -145,11 +140,14 @@ uint8_t ws_common_allow_child_registration(protocol_interface_info_entry_t *cur, bool ws_common_negative_aro_mark(protocol_interface_info_entry_t *interface, const uint8_t *eui64); - -uint32_t ws_common_version_lifetime_get(uint8_t config); - uint32_t ws_common_version_timeout_get(uint8_t config); +uint32_t ws_common_latency_estimate_get(protocol_interface_info_entry_t *cur); + +uint32_t ws_common_datarate_get(protocol_interface_info_entry_t *cur); + +uint32_t ws_common_network_size_estimate_get(protocol_interface_info_entry_t *cur); + #define ws_info(cur) ((cur)->ws_info) #else #define ws_info(cur) ((ws_info_t *) NULL) @@ -160,6 +158,9 @@ uint32_t ws_common_version_timeout_get(uint8_t config); #define ws_common_fast_timer(cur, ticks) ((void) 0) #define ws_common_allow_child_registration(cur, eui64) (2) #define ws_common_negative_aro_mark(interface, eui64)(false) +#define ws_common_latency_estimate_get(cur) 0 +#define ws_common_datarate_get(cur) 0 +#define ws_common_network_size_estimate_get(cur) 0 #endif //HAVE_WS #endif //WS_COMMON_H_ diff --git a/source/6LoWPAN/ws/ws_common_defines.h b/source/6LoWPAN/ws/ws_common_defines.h index 92f7da38eb..d2797f8e80 100644 --- a/source/6LoWPAN/ws/ws_common_defines.h +++ b/source/6LoWPAN/ws/ws_common_defines.h @@ -51,6 +51,12 @@ #define WS_FT_ACK 5 /**< Enhanced ACK */ #define WS_FT_EAPOL 6 /**< EAPOL message inside MPX */ +/* WS exluded channel Control */ +#define WS_EXC_CHAN_CTRL_NONE 0 /**< No excluded channels */ +#define WS_EXC_CHAN_CTRL_RANGE 1 /**< Excluded channels are in 1 or multiple channel range */ +#define WS_EXC_CHAN_CTRL_BITMASK 2 /**< Excluded channels are marked to bitmask which length based on configured channels */ + +#define WS_EXCLUDED_MAX_RANGE_TO_SEND 3 /** * @brief ws_pan_information_t PAN information @@ -64,6 +70,26 @@ typedef struct ws_pan_information_s { unsigned version: 3; /**< Pan version support. */ } ws_pan_information_t; +/** + * @brief ws_excluded_channel_range_data_t Excludd Chanel range information + */ +typedef struct ws_excluded_channel_range_data_s { + uint16_t range_start; + uint16_t range_end; +} ws_excluded_channel_range_data_t; + +/** + * @brief ws_excluded_channel_data_t Excludd Chanel information + */ +typedef struct ws_excluded_channel_data_s { + unsigned excuded_channel_ctrl: 2; + unsigned excluded_range_length: 3; + ws_excluded_channel_range_data_t exluded_range[WS_EXCLUDED_MAX_RANGE_TO_SEND]; + uint16_t excluded_channel_count; + uint8_t channel_mask_bytes_inline; + uint32_t channel_mask[8]; +} ws_excluded_channel_data_t; + /** * @brief ws_hopping_schedule_t Chanel hopping schedule information */ @@ -84,8 +110,8 @@ typedef struct ws_hopping_schedule_s { uint16_t bc_fixed_channel; uint16_t fhss_bsi; uint32_t fhss_broadcast_interval; - uint32_t channel_mask[8]; uint_fast24_t ch0_freq; // Default should be derived from regulatory domain + ws_excluded_channel_data_t excluded_channels; } ws_hopping_schedule_t; /** @@ -137,6 +163,22 @@ typedef struct ws_channel_function_three { uint8_t *channel_list; } ws_channel_function_three_t; +/** + * @brief ws_excluded_channel_range_t WS excluded channel range + */ +typedef struct ws_excluded_channel_range { + uint8_t number_of_range; + uint8_t *range_start; +} ws_excluded_channel_range_t; + +/** + * @brief ws_excluded_channel_mask_t WS excluded channel mask + */ +typedef struct ws_excluded_channel_mask { + uint8_t *channel_mask; + uint8_t mask_len_inline; +} ws_excluded_channel_mask_t; + /** * @brief ws_us_ie_t WS US-IE read */ @@ -155,6 +197,10 @@ typedef struct ws_us_ie { ws_channel_function_zero_t zero; ws_channel_function_three_t three; } function; + union { + ws_excluded_channel_range_t range; + ws_excluded_channel_mask_t mask; + } excluded_channels; } ws_us_ie_t; /** @@ -249,6 +295,11 @@ typedef struct ws_bs_ie { */ #define WS_TACK_MAX_MS 5 +/* + * Config new version consistent filter period in 100ms periods + */ +#define WS_CONFIG_CONSISTENT_FILTER_PERIOD 100 + // With FHSS we need to check CCA twice on TX channel #define WS_NUMBER_OF_CSMA_PERIODS 2 // Interval between two CCA checks diff --git a/source/6LoWPAN/ws/ws_config.h b/source/6LoWPAN/ws/ws_config.h index e7afc90d98..b2a9bd18c9 100644 --- a/source/6LoWPAN/ws/ws_config.h +++ b/source/6LoWPAN/ws/ws_config.h @@ -27,9 +27,21 @@ * */ -#define WS_RPL_DIO_IMIN 15 -#define WS_RPL_DIO_DOUBLING 2 -#define WS_RPL_DIO_REDUNDANCY 0 +#define WS_RPL_DIO_IMIN_SMALL 15 +#define WS_RPL_DIO_DOUBLING_SMALL 2 +#define WS_RPL_DIO_REDUNDANCY_SMALL 0 + +#define WS_RPL_DIO_IMIN_MEDIUM 15 +#define WS_RPL_DIO_DOUBLING_MEDIUM 5 +#define WS_RPL_DIO_REDUNDANCY_MEDIUM 10 + +#define WS_RPL_DIO_IMIN_LARGE 19 +#define WS_RPL_DIO_DOUBLING_LARGE 1 +#define WS_RPL_DIO_REDUNDANCY_LARGE 10 // May need some tuning still + +#define WS_RPL_DIO_IMIN_AUTOMATIC 14 +#define WS_RPL_DIO_DOUBLING_AUTOMATIC 3 +#define WS_RPL_DIO_REDUNDANCY_AUTOMATIC 0 #define WS_RPL_MIN_HOP_RANK_INCREASE 196 #define WS_RPL_MAX_HOP_RANK_INCREASE 2048 @@ -37,14 +49,17 @@ #define WS_CERTIFICATE_RPL_MIN_HOP_RANK_INCREASE 128 #define WS_CERTIFICATE_RPL_MAX_HOP_RANK_INCREASE 0 +/* + * RPL DAO timeout maximum value. This will force DAO timeout to happen before this time + */ +#define WS_RPL_DAO_MAX_TIMOUT (3600*2) + /* Border router version change interval * - * Minimum interval at which a Border Router shall increment its PAN Version value. + * Amount of version increases border router makes during PAN_TIMEOUT time */ -#define PAN_VERSION_SMALL_NETWORK_LIFETIME 4*60 -#define PAN_VERSION_MEDIUM_NETWORK_LIFETIME 15*60 -#define PAN_VERSION_LARGE_NETWORK_LIFETIME 30*60 //30min +#define PAN_VERSION_CHANGE_INTERVAL 3 // RPL version number update intervall // after restart version numbers are increased faster and then slowed down when network is stable @@ -101,10 +116,11 @@ extern uint8_t DEVICE_MIN_SENS; * IMIN = 10 seconds, IMAX = 3 doublings */ -#define DATA_MESSAGE_IMIN (10 * 1000) +#define DATA_MESSAGE_IMIN 10 #define DATA_MESSAGE_TIMER_EXPIRATIONS 3 -#define DATA_MESSAGE_IMAX (80 * 1000) -#define MPL_SEED_SET_ENTRY_TIMEOUT (DATA_MESSAGE_IMAX * 24 * 4 / 1000) // 10 seconds per hop making this 240 seconds +#define DATA_MESSAGE_IMAX 80 +#define DATA_MESSAGE_K 8 +#define MPL_SEED_SET_ENTRY_TIMEOUT (DATA_MESSAGE_IMAX * 24 * 4) // 10 seconds per hop making this 240 seconds /* DHCP client timeout configuration values * @@ -170,4 +186,36 @@ extern uint8_t DEVICE_MIN_SENS; */ #define WISUN_1_0_ERRATA_FIX +/* + * Security protocol message retry configuration parameters + */ +#define SEC_PROT_SMALL_IMIN 30 // Retries done in 30 seconds +#define SEC_PROT_SMALL_IMAX 90 // Largest value 90 seconds +#define SEC_PROT_RETRY_TIMEOUT_SMALL 330 // Retry timeout for small network additional 30 seconds for authenticator delay + +#define SEC_PROT_LARGE_IMIN 60 // Retries done in 60 seconds +#define SEC_PROT_LARGE_IMAX 240 // Largest value 240 seconds +#define SEC_PROT_RETRY_TIMEOUT_LARGE 750 // Retry timeout for large network additional 30 seconds for authenticator delay + +#define SEC_PROT_TIMER_EXPIRATIONS 2 // Number of retries + +// Maximum number of simultaneous EAP-TLS negotiations +#define MAX_SIMULTANEOUS_EAP_TLS_NEGOTIATIONS_SMALL 3 +#define MAX_SIMULTANEOUS_EAP_TLS_NEGOTIATIONS_MEDIUM 20 +#define MAX_SIMULTANEOUS_EAP_TLS_NEGOTIATIONS_LARGE 50 + +/* + * Security protocol timer configuration parameters + */ +#define MINUTES_IN_DAY 24 * 60 +#define DEFAULT_GTK_EXPIRE_OFFSET 43200 // 30 days +#define DEFAULT_PMK_LIFETIME 4 * 30 * MINUTES_IN_DAY // 4 months +#define DEFAULT_PTK_LIFETIME 2 * 30 * MINUTES_IN_DAY // 2 months +#define DEFAULT_GTK_NEW_ACTIVATION_TIME 720 // default 1/720 * 30 days --> 60 minutes +#define DEFAULT_REVOCATION_LIFETIME_REDUCTION 30 // default 1/30 * 30 days --> 1 day +#define DEFAULT_GTK_REQUEST_IMIN 4 // 4 minutes +#define DEFAULT_GTK_REQUEST_IMAX 64 // 64 minutes +#define DEFAULT_GTK_MAX_MISMATCH 64 // 64 minutes +#define DEFAULT_GTK_NEW_INSTALL_REQUIRED 80 // 80 percent of GTK lifetime --> 24 days + #endif /* WS_CONFIG_H_ */ diff --git a/source/6LoWPAN/ws/ws_empty_functions.c b/source/6LoWPAN/ws/ws_empty_functions.c index be07fd0126..e03e811d63 100644 --- a/source/6LoWPAN/ws/ws_empty_functions.c +++ b/source/6LoWPAN/ws/ws_empty_functions.c @@ -49,6 +49,24 @@ int ws_management_network_name_set( return -1; } +int ws_management_network_name_get( + int8_t interface_id, + char *network_name_ptr) +{ + (void)interface_id; + (void)network_name_ptr; + return -1; +} + +int ws_management_network_name_validate( + int8_t interface_id, + char *network_name_ptr) +{ + (void)interface_id; + (void)network_name_ptr; + return -1; +} + int ws_management_regulatory_domain_set( int8_t interface_id, uint8_t regulatory_domain, @@ -62,6 +80,32 @@ int ws_management_regulatory_domain_set( return -1; } +int ws_management_regulatory_domain_get( + int8_t interface_id, + uint8_t *regulatory_domain, + uint8_t *operating_class, + uint8_t *operating_mode) +{ + (void)interface_id; + (void)regulatory_domain; + (void)operating_class; + (void)operating_mode; + return -1; +} + +int ws_management_regulatory_domain_validate( + int8_t interface_id, + uint8_t regulatory_domain, + uint8_t operating_class, + uint8_t operating_mode) +{ + (void)interface_id; + (void)regulatory_domain; + (void)operating_class; + (void)operating_mode; + return -1; +} + int ws_management_network_size_set( int8_t interface_id, uint8_t network_size) @@ -71,6 +115,24 @@ int ws_management_network_size_set( return -1; } +int ws_management_network_size_get( + int8_t interface_id, + uint8_t *network_size) +{ + (void)interface_id; + (void)network_size; + return -1; +} + +int ws_management_network_size_validate( + int8_t interface_id, + uint8_t network_size) +{ + (void)interface_id; + (void)network_size; + return -1; +} + int ws_management_channel_mask_set( int8_t interface_id, uint32_t channel_mask[8]) @@ -80,6 +142,24 @@ int ws_management_channel_mask_set( return -1; } +int ws_management_channel_mask_get( + int8_t interface_id, + uint32_t *channel_mask) +{ + (void)interface_id; + (void)channel_mask; + return -1; +} + +int ws_management_channel_mask_validate( + int8_t interface_id, + uint32_t channel_mask[8]) +{ + (void)interface_id; + (void)channel_mask; + return -1; +} + int ws_management_channel_plan_set( int8_t interface_id, uint8_t channel_plan, @@ -125,6 +205,32 @@ int ws_management_fhss_unicast_channel_function_configure( return -1; } +int ws_management_fhss_unicast_channel_function_get( + int8_t interface_id, + uint8_t *channel_function, + uint16_t *fixed_channel, + uint8_t *dwell_interval) +{ + (void)interface_id; + (void)channel_function; + (void)fixed_channel; + (void)dwell_interval; + return -1; +} + +int ws_management_fhss_unicast_channel_function_validate( + int8_t interface_id, + uint8_t channel_function, + uint16_t fixed_channel, + uint8_t dwell_interval) +{ + (void)interface_id; + (void)channel_function; + (void)fixed_channel; + (void)dwell_interval; + return -1; +} + int ws_management_fhss_broadcast_channel_function_configure( int8_t interface_id, uint8_t channel_function, @@ -140,6 +246,81 @@ int ws_management_fhss_broadcast_channel_function_configure( return -1; } +int ws_management_fhss_broadcast_channel_function_get( + int8_t interface_id, + uint8_t *channel_function, + uint16_t *fixed_channel, + uint8_t *dwell_interval, + uint32_t *broadcast_interval) +{ + (void)interface_id; + (void)channel_function; + (void)fixed_channel; + (void)dwell_interval; + (void)broadcast_interval; + return -1; +} + +int ws_management_fhss_broadcast_channel_function_validate( + int8_t interface_id, + uint8_t channel_function, + uint16_t fixed_channel, + uint8_t dwell_interval, + uint32_t broadcast_interval) +{ + (void)interface_id; + (void)channel_function; + (void)fixed_channel; + (void)dwell_interval; + (void)broadcast_interval; + return -1; +} + +int ws_management_timing_parameters_set( + int8_t interface_id, + uint16_t disc_trickle_imin, + uint16_t disc_trickle_imax, + uint8_t disc_trickle_k, + uint16_t pan_timeout) +{ + (void)interface_id; + (void)disc_trickle_imin; + (void)disc_trickle_imax; + (void)disc_trickle_k; + (void)pan_timeout; + return -1; +} + +int ws_management_timing_parameters_get( + int8_t interface_id, + uint16_t *disc_trickle_imin, + uint16_t *disc_trickle_imax, + uint8_t *disc_trickle_k, + uint16_t *pan_timeout) +{ + (void)interface_id; + (void)disc_trickle_imin; + (void)disc_trickle_imax; + (void)disc_trickle_k; + (void)pan_timeout; + return -1; +} + +int ws_management_timing_parameters_validate( + int8_t interface_id, + uint16_t disc_trickle_imin, + uint16_t disc_trickle_imax, + uint8_t disc_trickle_k, + uint16_t pan_timeout) +{ + (void)interface_id; + (void)disc_trickle_imin; + (void)disc_trickle_imax; + (void)disc_trickle_k; + (void)pan_timeout; + return -1; +} + /* ### test api ### */ int ws_test_pan_size_set(int8_t interface_id, uint16_t pan_size) { diff --git a/source/6LoWPAN/ws/ws_ie_lib.c b/source/6LoWPAN/ws/ws_ie_lib.c index a3aa0d93a6..0dfdc8b5ac 100644 --- a/source/6LoWPAN/ws/ws_ie_lib.c +++ b/source/6LoWPAN/ws/ws_ie_lib.c @@ -82,7 +82,13 @@ uint16_t ws_wp_nested_hopping_schedule_length(struct ws_hopping_schedule_s *hopp length += ws_channel_function_length(channel_function, 1); - //Todo Derive some how exluded channel control + if (unicast_schedule && hopping_schedule->excluded_channels.excuded_channel_ctrl) { + if (hopping_schedule->excluded_channels.excuded_channel_ctrl == WS_EXC_CHAN_CTRL_RANGE) { + length += (hopping_schedule->excluded_channels.excluded_range_length * 4) + 1; + } else { + length += hopping_schedule->excluded_channels.channel_mask_bytes_inline; + } + } return length; } @@ -161,10 +167,11 @@ uint8_t *ws_wp_nested_hopping_schedule_write(uint8_t *ptr, struct ws_hopping_sch channel_info_base = (hopping_schedule->channel_plan); if (unicast_schedule) { channel_info_base |= (hopping_schedule->uc_channel_function << 3); + //Set Excluded Channel control part + channel_info_base |= (hopping_schedule->excluded_channels.excuded_channel_ctrl << 6); } else { channel_info_base |= (hopping_schedule->bc_channel_function << 3); } - //Todo define excluded channel ctrl *ptr++ = channel_info_base; @@ -176,9 +183,9 @@ uint8_t *ws_wp_nested_hopping_schedule_write(uint8_t *ptr, struct ws_hopping_sch break; case 1: //CHo, Channel spasing and number of channel's inline - ptr = common_write_24_bit(hopping_schedule->fhss_uc_dwell_interval, ptr); - *ptr++ = ((hopping_schedule->channel_spacing << 4) & 0xf0); - ptr = common_write_16_bit(hopping_schedule->number_of_channels, ptr); + ptr = common_write_24_bit_inverse(hopping_schedule->ch0_freq * 100, ptr); + *ptr++ = hopping_schedule->channel_spacing; + ptr = common_write_16_bit_inverse(hopping_schedule->number_of_channels, ptr); break; default: break; @@ -210,6 +217,44 @@ uint8_t *ws_wp_nested_hopping_schedule_write(uint8_t *ptr, struct ws_hopping_sch break; } + + if (unicast_schedule && hopping_schedule->excluded_channels.excuded_channel_ctrl) { + if (hopping_schedule->excluded_channels.excuded_channel_ctrl == WS_EXC_CHAN_CTRL_RANGE) { + uint8_t range_length = hopping_schedule->excluded_channels.excluded_range_length; + ws_excluded_channel_range_data_t *range_ptr = hopping_schedule->excluded_channels.exluded_range; + *ptr++ = range_length; + while (range_length) { + ptr = common_write_16_bit_inverse(range_ptr->range_start, ptr); + ptr = common_write_16_bit_inverse(range_ptr->range_end, ptr); + range_length--; + range_ptr++; + } + } else if (hopping_schedule->excluded_channels.excuded_channel_ctrl == WS_EXC_CHAN_CTRL_BITMASK) { + //Set Mask + uint16_t channel_mask_length = hopping_schedule->excluded_channels.channel_mask_bytes_inline * 8; + + for (uint8_t i = 0; i < 8; i++) { + uint32_t mask_value = hopping_schedule->excluded_channels.channel_mask[i]; + if (channel_mask_length >= 32) { + ptr = common_write_32_bit(mask_value, ptr); + channel_mask_length -= 32; + } else { + //Write MSB Bits from mask 24-8 top bits + uint8_t move_mask = 0; + while (channel_mask_length) { + *ptr++ = (uint8_t)(mask_value >> (24 - move_mask)); + channel_mask_length -= 8; + move_mask += 8; + } + } + + if (channel_mask_length == 0) { + break; + } + } + } + } + return ptr; } @@ -330,8 +375,9 @@ static uint8_t *ws_channel_plan_zero_read(uint8_t *ptr, ws_channel_plan_zero_t * static uint8_t *ws_channel_plan_one_read(uint8_t *ptr, ws_channel_plan_one_t *plan) { plan->ch0 = common_read_24_bit_inverse(ptr); + plan->ch0 /= 100; ptr += 3; - plan->channel_spacing = (*ptr++ & 0xf0) >> 4; + plan->channel_spacing = *ptr++; plan->number_of_channel = common_read_16_bit_inverse(ptr); ptr += 2; return ptr; @@ -358,6 +404,7 @@ bool ws_wp_nested_us_read(uint8_t *data, uint16_t length, struct ws_us_ie *us_ie if (mac_ie_nested_discover(data, length, &nested_payload_ie) < 4) { return false; } + data = nested_payload_ie.content_ptr; us_ie->dwell_interval = *data++; us_ie->clock_drift = *data++; @@ -419,6 +466,36 @@ bool ws_wp_nested_us_read(uint8_t *data, uint16_t length, struct ws_us_ie *us_ie } + switch (us_ie->excluded_channel_ctrl) { + case WS_EXC_CHAN_CTRL_NONE: + + break; + case WS_EXC_CHAN_CTRL_RANGE: + us_ie->excluded_channels.range.number_of_range = *data; + if (nested_payload_ie.length < (us_ie->excluded_channels.range.number_of_range * 4) + 1) { + return false; + } + //Set Range start after validation + us_ie->excluded_channels.range.range_start = data + 1; + break; + + case WS_EXC_CHAN_CTRL_BITMASK: + if (us_ie->channel_plan == 1) { + us_ie->excluded_channels.mask.mask_len_inline = ((us_ie->plan.one.number_of_channel + 7) / 8); + if (us_ie->excluded_channels.mask.mask_len_inline != nested_payload_ie.length) { + //Channel mask length is not correct + return false; + } + } else { + us_ie->excluded_channels.mask.mask_len_inline = nested_payload_ie.length; + } + + us_ie->excluded_channels.mask.channel_mask = data; + break; + default: + return false; + } + return true; } bool ws_wp_nested_bs_read(uint8_t *data, uint16_t length, struct ws_bs_ie *bs_ie) diff --git a/source/6LoWPAN/ws/ws_llc_data_service.c b/source/6LoWPAN/ws/ws_llc_data_service.c index 9e94dbbe4c..adef723d0c 100644 --- a/source/6LoWPAN/ws/ws_llc_data_service.c +++ b/source/6LoWPAN/ws/ws_llc_data_service.c @@ -547,6 +547,12 @@ static void ws_llc_mac_indication_cb(const mac_api_t *api, const mcps_data_ind_t bs_ie_inline = ws_wp_nested_bs_read(ws_wp_nested.content_ptr, ws_wp_nested.length, &ws_bs_ie); } + //Validate Unicast shedule Channel Plan + if (us_ie_inline && !ws_bootstrap_validate_channel_plan(&us_ie, interface)) { + //Channel plan configuration mismatch + return; + } + llc_neighbour_req_t neighbor_info; bool multicast; bool request_new_entry; diff --git a/source/6LoWPAN/ws/ws_management_api.c b/source/6LoWPAN/ws/ws_management_api.c index 63f7322326..cd4ce0cd80 100644 --- a/source/6LoWPAN/ws/ws_management_api.c +++ b/source/6LoWPAN/ws/ws_management_api.c @@ -21,11 +21,12 @@ #include "ns_trace.h" #include #include +#include "fhss_config.h" +#include "ws_management_api.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_common.h" #include "6LoWPAN/ws/ws_bootstrap.h" - -#include "ws_management_api.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" #define TRACE_GROUP "wsmg" @@ -40,19 +41,37 @@ int ws_management_node_init( protocol_interface_info_entry_t *cur; cur = protocol_stack_interface_info_get_by_id(interface_id); - if (!cur || !ws_info(cur)) { + if (interface_id >= 0 && (!cur || !ws_info(cur))) { return -1; } if (!network_name_ptr || !fhss_timer_ptr) { return -2; } - cur->ws_info->hopping_schdule.regulatory_domain = regulatory_domain; - if (ws_common_regulatory_domain_config(cur) < 0) { - // Invalid regulatory domain set + + ws_phy_cfg_t phy_cfg; + if (ws_cfg_phy_get(&phy_cfg, NULL) < 0) { return -3; } - strncpy(cur->ws_info->network_name, network_name_ptr, 32); + + phy_cfg.regulatory_domain = regulatory_domain; + + if (ws_cfg_phy_set(cur, NULL, &phy_cfg, 0) < 0) { + return -4; + } + + ws_gen_cfg_t gen_cfg; + if (ws_cfg_gen_get(&gen_cfg, NULL) < 0) { + return -3; + } + + strncpy(gen_cfg.network_name, network_name_ptr, 32); + + if (ws_cfg_gen_set(cur, NULL, &gen_cfg, 0) < 0) { + return -4; + } + cur->ws_info->fhss_timer_ptr = fhss_timer_ptr; + return 0; } @@ -62,65 +81,162 @@ int ws_management_network_name_set( { protocol_interface_info_entry_t *cur; cur = protocol_stack_interface_info_get_by_id(interface_id); - if (!cur || !ws_info(cur)) { + if (interface_id >= 0 && (!cur || !ws_info(cur))) { return -1; } - if (!network_name_ptr || strlen(network_name_ptr) == 0 || strlen(network_name_ptr) > 32) { + if (!network_name_ptr) { return -2; } - if (strcmp(cur->ws_info->network_name, network_name_ptr) == 0) { - // Network name is the same no further actions required. - return 0; + + ws_gen_cfg_t cfg; + if (ws_cfg_gen_get(&cfg, NULL) < 0) { + return -3; } - strncpy(cur->ws_info->network_name, network_name_ptr, 32); - // if settings change reset_restart for the settings needed - if (cur->lowpan_info & INTERFACE_NWK_ACTIVE) { - // bootstrap active need to restart - ws_bootstrap_restart(interface_id); + + strncpy(cfg.network_name, network_name_ptr, 32); + + if (ws_cfg_gen_set(cur, NULL, &cfg, 0) < 0) { + return -4; } return 0; } + +int ws_management_network_name_get( + int8_t interface_id, + char *network_name_ptr) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + if (!network_name_ptr) { + return -2; + } + + ws_gen_cfg_t cfg; + if (ws_cfg_gen_get(&cfg, NULL) < 0) { + return -3; + } + + memcpy(network_name_ptr, cfg.network_name, 32); + + return 0; +} + +int ws_management_network_name_validate( + int8_t interface_id, + char *network_name_ptr) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + if (!network_name_ptr) { + return -2; + } + + ws_gen_cfg_t cfg; + if (ws_cfg_gen_get(&cfg, NULL) < 0) { + return -3; + } + + strncpy(cfg.network_name, network_name_ptr, 32); + + if (ws_cfg_gen_validate(NULL, &cfg) < 0) { + return -4; + } + + return 0; +} + int ws_management_regulatory_domain_set( int8_t interface_id, uint8_t regulatory_domain, uint8_t operating_class, uint8_t operating_mode) { - uint8_t regulatory_domain_saved; - uint8_t operating_class_saved; - uint8_t operating_mode_saved; protocol_interface_info_entry_t *cur; cur = protocol_stack_interface_info_get_by_id(interface_id); - if (!cur || !ws_info(cur)) { + if (interface_id >= 0 && (!cur || !ws_info(cur))) { return -1; } - regulatory_domain_saved = cur->ws_info->hopping_schdule.regulatory_domain; - operating_class_saved = cur->ws_info->hopping_schdule.operating_mode; - operating_mode_saved = cur->ws_info->hopping_schdule.operating_class; + + ws_phy_cfg_t cfg; + if (ws_cfg_phy_get(&cfg, NULL) < 0) { + return -3; + } + if (regulatory_domain != 255) { - cur->ws_info->hopping_schdule.regulatory_domain = regulatory_domain; + cfg.regulatory_domain = regulatory_domain; } if (operating_mode != 255) { - cur->ws_info->hopping_schdule.operating_mode = operating_mode; + cfg.operating_mode = operating_mode; } if (operating_class != 255) { - cur->ws_info->hopping_schdule.operating_class = operating_class; + cfg.operating_class = operating_class; } - if (ws_common_regulatory_domain_config(cur) != 0) { - // Restore old config on failure - //tr_error("unsupported regulatory domain: %d class: %d, mode: %d", regulatory_domain, operating_class, operating_mode); - cur->ws_info->hopping_schdule.regulatory_domain = regulatory_domain_saved; - cur->ws_info->hopping_schdule.operating_mode = operating_mode_saved; - cur->ws_info->hopping_schdule.operating_class = operating_class_saved; - ws_common_regulatory_domain_config(cur); + + if (ws_cfg_phy_set(cur, NULL, &cfg, 0) < 0) { + return -4; + } + + return 0; +} + +int ws_management_regulatory_domain_get( + int8_t interface_id, + uint8_t *regulatory_domain, + uint8_t *operating_class, + uint8_t *operating_mode) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { return -1; } - // if settings change reset_restart for the settings needed - if (cur->lowpan_info & INTERFACE_NWK_ACTIVE) { - // bootstrap active need to restart - ws_bootstrap_restart(interface_id); + if (!regulatory_domain || !operating_class || !operating_mode) { + return -2; + } + + ws_phy_cfg_t cfg; + if (ws_cfg_phy_get(&cfg, NULL) < 0) { + return -3; + } + + *regulatory_domain = cfg.regulatory_domain; + *operating_class = cfg.operating_class; + *operating_mode = cfg.operating_mode; + + return 0; +} + +int ws_management_regulatory_domain_validate( + int8_t interface_id, + uint8_t regulatory_domain, + uint8_t operating_class, + uint8_t operating_mode) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + + ws_phy_cfg_t cfg; + if (ws_cfg_phy_get(&cfg, NULL) < 0) { + return -3; + } + + cfg.regulatory_domain = regulatory_domain; + cfg.operating_class = operating_class; + cfg.operating_mode = operating_mode; + + if (ws_cfg_phy_validate(NULL, &cfg) < 0) { + return -4; } return 0; @@ -133,38 +249,68 @@ int ws_management_network_size_set( protocol_interface_info_entry_t *cur; cur = protocol_stack_interface_info_get_by_id(interface_id); - if (!cur || !ws_info(cur)) { + if (interface_id >= 0 && (!cur || !ws_info(cur))) { return -1; } - //Store old setup if new is not accepted - uint8_t old_setup = ws_info(cur)->network_size_config; - ws_info(cur)->network_size_config = network_size; - uint16_t rpl_parent_candidate_max; - uint16_t rpl_selected_parent_max; - - if (network_size == NETWORK_SIZE_CERTIFICATE) { - rpl_parent_candidate_max = WS_CERTIFICATE_RPL_PARENT_CANDIDATE_MAX; - rpl_selected_parent_max = WS_CERTIFICATE_RPL_SELECTED_PARENT_MAX; - } else { - rpl_parent_candidate_max = WS_RPL_PARENT_CANDIDATE_MAX; - rpl_selected_parent_max = WS_RPL_SELECTED_PARENT_MAX; + ws_gen_cfg_t cfg; + if (ws_cfg_network_size_get(&cfg, NULL) < 0) { + return -3; } - if (network_size == NETWORK_SIZE_LARGE) { - ws_common_network_size_configure(cur, 5000); - } else if (network_size == NETWORK_SIZE_MEDIUM) { - ws_common_network_size_configure(cur, 200); - } else if (network_size == NETWORK_SIZE_SMALL) { - ws_common_network_size_configure(cur, 10); - } else if (network_size == NETWORK_SIZE_CERTIFICATE) { - ws_common_network_size_configure(cur, 0); - } else { - ws_info(cur)->network_size_config = old_setup; + cfg.network_size = network_size; + + if (ws_cfg_network_size_set(cur, NULL, &cfg, 0) < 0) { + return -3; + } + + return 0; +} + +int ws_management_network_size_get( + int8_t interface_id, + uint8_t *network_size) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + if (!network_size) { return -2; } - cur->ws_info->rpl_parent_candidate_max = rpl_parent_candidate_max; - cur->ws_info->rpl_selected_parent_max = rpl_selected_parent_max; + + ws_gen_cfg_t cfg; + if (ws_cfg_network_size_get(&cfg, NULL) < 0) { + return -3; + } + + *network_size = cfg.network_size; + + return 0; +} + +int ws_management_network_size_validate( + int8_t interface_id, + uint8_t network_size) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + + ws_gen_cfg_t cfg; + if (ws_cfg_network_size_get(&cfg, NULL) < 0) { + return -3; + } + + cfg.network_size = network_size; + + if (ws_cfg_network_size_validate(NULL, &cfg) < 0) { + return -4; + } + return 0; } @@ -175,10 +321,68 @@ int ws_management_channel_mask_set( protocol_interface_info_entry_t *cur; cur = protocol_stack_interface_info_get_by_id(interface_id); - if (!cur || !ws_info(cur)) { + if (interface_id >= 0 && (!cur || !ws_info(cur))) { return -1; } - memcpy(cur->ws_info->fhss_channel_mask, channel_mask, sizeof(uint32_t) * 8); + + ws_fhss_cfg_t cfg; + if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + return -2; + } + + memcpy(cfg.fhss_channel_mask, channel_mask, sizeof(uint32_t) * 8); + + if (ws_cfg_fhss_set(cur, NULL, &cfg, 0) < 0) { + return -3; + } + + return 0; +} + +int ws_management_channel_mask_get( + int8_t interface_id, + uint32_t *channel_mask) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + if (!channel_mask) { + return -2; + } + + ws_fhss_cfg_t cfg; + if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + return -2; + } + + memcpy(channel_mask, cfg.fhss_channel_mask, sizeof(uint32_t) * 8); + + return 0; +} + +int ws_management_channel_mask_validate( + int8_t interface_id, + uint32_t channel_mask[8]) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + + ws_fhss_cfg_t cfg; + if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + return -2; + } + + memcpy(cfg.fhss_channel_mask, channel_mask, sizeof(uint32_t) * 8); + + if (ws_cfg_fhss_validate(NULL, &cfg) < 0) { + return -4; + } + return 0; } @@ -194,7 +398,7 @@ int ws_management_channel_plan_set( protocol_interface_info_entry_t *cur; cur = protocol_stack_interface_info_get_by_id(interface_id); - if (!cur || !ws_info(cur)) { + if (interface_id >= 0 && (!cur || !ws_info(cur))) { return -1; } cur->ws_info->hopping_schdule.channel_plan = channel_plan; @@ -217,38 +421,29 @@ int ws_management_fhss_timing_configure( protocol_interface_info_entry_t *cur; cur = protocol_stack_interface_info_get_by_id(interface_id); - if (!cur || !ws_info(cur)) { + if (interface_id >= 0 && (!cur || !ws_info(cur))) { return -1; } - if (fhss_uc_dwell_interval && fhss_uc_dwell_interval < 15) { + ws_fhss_cfg_t cfg; + if (ws_cfg_fhss_get(&cfg, NULL) < 0) { return -2; } - if (fhss_bc_dwell_interval && fhss_bc_dwell_interval < 15) { - return -2; + if (fhss_uc_dwell_interval > 0) { + cfg.fhss_uc_dwell_interval = fhss_uc_dwell_interval; + } + if (fhss_broadcast_interval > 0) { + cfg.fhss_bc_interval = fhss_broadcast_interval; + } + if (fhss_bc_dwell_interval > 0) { + cfg.fhss_bc_dwell_interval = fhss_bc_dwell_interval; } - bool updated_configure = false; - - if (fhss_uc_dwell_interval > 0 && cur->ws_info->fhss_uc_dwell_interval != fhss_uc_dwell_interval) { - cur->ws_info->fhss_uc_dwell_interval = fhss_uc_dwell_interval; - updated_configure = true; - } - if (fhss_broadcast_interval > 0 && cur->ws_info->fhss_bc_interval != fhss_broadcast_interval) { - cur->ws_info->fhss_bc_interval = fhss_broadcast_interval; - updated_configure = true; - } - if (fhss_bc_dwell_interval > 0 && cur->ws_info->fhss_bc_dwell_interval != fhss_bc_dwell_interval) { - cur->ws_info->fhss_bc_dwell_interval = fhss_bc_dwell_interval; - updated_configure = true; + if (ws_cfg_fhss_set(cur, NULL, &cfg, 0) < 0) { + return -3; } - // if settings change reset_restart for the settings needed - if (updated_configure && (cur->lowpan_info & INTERFACE_NWK_ACTIVE)) { - // bootstrap active need to restart - ws_bootstrap_restart(interface_id); - } return 0; } @@ -261,53 +456,82 @@ int ws_management_fhss_unicast_channel_function_configure( protocol_interface_info_entry_t *cur; cur = protocol_stack_interface_info_get_by_id(interface_id); - if (!cur || !ws_info(cur)) { + if (interface_id >= 0 && (!cur || !ws_info(cur))) { return -1; } - if (channel_function != WS_FIXED_CHANNEL && - channel_function != WS_VENDOR_DEF_CF && - channel_function != WS_DH1CF && - channel_function != WS_TR51CF) { + + ws_fhss_cfg_t cfg; + if (ws_cfg_fhss_get(&cfg, NULL) < 0) { return -2; } - if (dwell_interval && dwell_interval < 15) { - return -2; + if (dwell_interval > 0) { + cfg.fhss_uc_dwell_interval = dwell_interval; } - if (channel_function == WS_FIXED_CHANNEL && fixed_channel == 0xffff) { - fixed_channel = 0; - tr_warn("Fixed channel not configured. Set to 0"); + cfg.fhss_uc_channel_function = channel_function; + cfg.fhss_uc_fixed_channel = fixed_channel; + + if (ws_cfg_fhss_set(cur, NULL, &cfg, 0) < 0) { + return -3; } - bool updated_config = false; - - if (cur->ws_info->fhss_uc_channel_function != channel_function) { - cur->ws_info->fhss_uc_channel_function = channel_function; - updated_config = true; - } - - if (cur->ws_info->fhss_uc_channel_function == WS_FIXED_CHANNEL) { - if (cur->ws_info->fhss_uc_fixed_channel != fixed_channel) { - cur->ws_info->fhss_uc_fixed_channel = fixed_channel; - updated_config = true; - } - } else { - cur->ws_info->fhss_uc_fixed_channel = 0xffff; - } - - if (dwell_interval && cur->ws_info->fhss_uc_dwell_interval != dwell_interval) { - cur->ws_info->fhss_uc_dwell_interval = dwell_interval; - updated_config = true; - } - - // if settings change reset_restart for the settings needed - if (updated_config && (cur->lowpan_info & INTERFACE_NWK_ACTIVE)) { - // bootstrap active need to restart - ws_bootstrap_restart(interface_id); - } return 0; +} +int ws_management_fhss_unicast_channel_function_get( + int8_t interface_id, + uint8_t *channel_function, + uint16_t *fixed_channel, + uint8_t *dwell_interval) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + if (!channel_function || !fixed_channel || !dwell_interval) { + return -2; + } + + ws_fhss_cfg_t cfg; + if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + return -2; + } + + *dwell_interval = cfg.fhss_uc_dwell_interval; + *channel_function = cfg.fhss_uc_channel_function; + *fixed_channel = cfg.fhss_uc_fixed_channel; + + return 0; +} + +int ws_management_fhss_unicast_channel_function_validate( + int8_t interface_id, + uint8_t channel_function, + uint16_t fixed_channel, + uint8_t dwell_interval) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + + ws_fhss_cfg_t cfg; + if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + return -2; + } + + cfg.fhss_uc_dwell_interval = dwell_interval; + cfg.fhss_uc_channel_function = channel_function; + cfg.fhss_uc_fixed_channel = fixed_channel; + + if (ws_cfg_fhss_validate(NULL, &cfg) < 0) { + return -4; + } + + return 0; } int ws_management_fhss_broadcast_channel_function_configure( @@ -320,57 +544,187 @@ int ws_management_fhss_broadcast_channel_function_configure( protocol_interface_info_entry_t *cur; cur = protocol_stack_interface_info_get_by_id(interface_id); - if (!cur || !ws_info(cur)) { + if (interface_id >= 0 && (!cur || !ws_info(cur))) { return -1; } - if (channel_function != WS_FIXED_CHANNEL && - channel_function != WS_VENDOR_DEF_CF && - channel_function != WS_DH1CF && - channel_function != WS_TR51CF) { + + ws_fhss_cfg_t cfg; + if (ws_cfg_fhss_get(&cfg, NULL) < 0) { return -2; } - if (dwell_interval && dwell_interval < 15) { - return -2; + if (dwell_interval > 0) { + cfg.fhss_bc_dwell_interval = dwell_interval; + } + if (broadcast_interval > 0) { + cfg.fhss_bc_interval = broadcast_interval; } - if (channel_function == WS_FIXED_CHANNEL && fixed_channel == 0xffff) { - fixed_channel = 0; - tr_warn("Fixed channel not configured. Set to 0"); + cfg.fhss_bc_channel_function = channel_function; + cfg.fhss_bc_fixed_channel = fixed_channel; + + if (ws_cfg_fhss_set(cur, NULL, &cfg, 0) < 0) { + return -3; } - bool updated_config = false; - - if (cur->ws_info->fhss_bc_channel_function != channel_function) { - cur->ws_info->fhss_bc_channel_function = channel_function; - updated_config = true; - } - - if (cur->ws_info->fhss_bc_channel_function == WS_FIXED_CHANNEL) { - if (cur->ws_info->fhss_bc_fixed_channel != fixed_channel) { - cur->ws_info->fhss_bc_fixed_channel = fixed_channel; - updated_config = true; - } - } else { - cur->ws_info->fhss_bc_fixed_channel = 0xffff; - } - - if (dwell_interval > 0 && cur->ws_info->fhss_bc_dwell_interval != dwell_interval) { - cur->ws_info->fhss_bc_dwell_interval = dwell_interval; - updated_config = true; - } - - if (broadcast_interval > 0 && cur->ws_info->fhss_bc_interval != broadcast_interval) { - cur->ws_info->fhss_bc_interval = broadcast_interval; - updated_config = true; - } - - // if settings change reset_restart for the settings needed - if (updated_config && (cur->lowpan_info & INTERFACE_NWK_ACTIVE)) { - // bootstrap active need to restart - ws_bootstrap_restart(interface_id); - } return 0; - } + +int ws_management_fhss_broadcast_channel_function_get( + int8_t interface_id, + uint8_t *channel_function, + uint16_t *fixed_channel, + uint8_t *dwell_interval, + uint32_t *broadcast_interval) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + if (!channel_function || !fixed_channel || !dwell_interval) { + return -2; + } + + ws_fhss_cfg_t cfg; + if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + return -2; + } + + *dwell_interval = cfg.fhss_bc_dwell_interval; + *broadcast_interval = cfg.fhss_bc_interval; + *channel_function = cfg.fhss_bc_channel_function; + *fixed_channel = cfg.fhss_bc_fixed_channel; + + return 0; +} + +int ws_management_fhss_broadcast_channel_function_validate( + int8_t interface_id, + uint8_t channel_function, + uint16_t fixed_channel, + uint8_t dwell_interval, + uint32_t broadcast_interval) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + + ws_fhss_cfg_t cfg; + if (ws_cfg_fhss_get(&cfg, NULL) < 0) { + return -2; + } + + cfg.fhss_bc_dwell_interval = dwell_interval; + cfg.fhss_bc_interval = broadcast_interval; + cfg.fhss_bc_channel_function = channel_function; + cfg.fhss_bc_fixed_channel = fixed_channel; + + if (ws_cfg_fhss_validate(NULL, &cfg) < 0) { + return -4; + } + + return 0; +} + +int ws_management_timing_parameters_set( + int8_t interface_id, + uint16_t disc_trickle_imin, + uint16_t disc_trickle_imax, + uint8_t disc_trickle_k, + uint16_t pan_timeout) +{ + protocol_interface_info_entry_t *cur; + + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + + ws_timing_cfg_t cfg; + if (ws_cfg_timing_get(&cfg, NULL) < 0) { + return -2; + } + + if (disc_trickle_imin > 0) { + cfg.disc_trickle_imin = disc_trickle_imin; + } + if (disc_trickle_imax > 0) { + cfg.disc_trickle_imax = disc_trickle_imax; + } + if (disc_trickle_k > 0) { + cfg.disc_trickle_k = disc_trickle_k; + } + if (pan_timeout > 0) { + cfg.pan_timeout = pan_timeout; + } + + if (ws_cfg_timing_set(cur, NULL, &cfg, 0) < 0) { + return -3; + } + + return 0; +} + +int ws_management_timing_parameters_get( + int8_t interface_id, + uint16_t *disc_trickle_imin, + uint16_t *disc_trickle_imax, + uint8_t *disc_trickle_k, + uint16_t *pan_timeout) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + if (!disc_trickle_imin || !disc_trickle_imax || !disc_trickle_k || !pan_timeout) { + return -2; + } + + ws_timing_cfg_t cfg; + if (ws_cfg_timing_get(&cfg, NULL) < 0) { + return -2; + } + + *disc_trickle_imin = cfg.disc_trickle_imin; + *disc_trickle_imax = cfg.disc_trickle_imax; + *disc_trickle_k = cfg.disc_trickle_k; + *pan_timeout = cfg.pan_timeout; + + return 0; +} + +int ws_management_timing_parameters_validate( + int8_t interface_id, + uint16_t disc_trickle_imin, + uint16_t disc_trickle_imax, + uint8_t disc_trickle_k, + uint16_t pan_timeout) +{ + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (interface_id >= 0 && (!cur || !ws_info(cur))) { + return -1; + } + + ws_timing_cfg_t cfg; + if (ws_cfg_timing_get(&cfg, NULL) < 0) { + return -2; + } + + cfg.disc_trickle_imin = disc_trickle_imin; + cfg.disc_trickle_imax = disc_trickle_imax; + cfg.disc_trickle_k = disc_trickle_k; + cfg.pan_timeout = pan_timeout; + + if (ws_cfg_timing_validate(NULL, &cfg) < 0) { + return -4; + } + + return 0; +} + #endif // HAVE_WS diff --git a/source/6LoWPAN/ws/ws_neighbor_class.c b/source/6LoWPAN/ws/ws_neighbor_class.c index 8eda4fcc63..7e4e7eedc0 100644 --- a/source/6LoWPAN/ws/ws_neighbor_class.c +++ b/source/6LoWPAN/ws/ws_neighbor_class.c @@ -21,6 +21,7 @@ #include "ns_list.h" #include "ns_trace.h" #include "nsdynmemLIB.h" +#include "common_functions.h" #include "fhss_config.h" #include "6LoWPAN/ws/ws_config.h" #include "6LoWPAN/ws/ws_neighbor_class.h" @@ -94,6 +95,121 @@ void ws_neighbor_class_neighbor_unicast_time_info_update(ws_neighbor_class_entry ws_neighbor->fhss_data.uc_timing_info.ufsi = ws_utt->ufsi; } +static void ws_neighbour_channel_list_enable_all(ws_channel_mask_t *channel_info, uint16_t number_of_channels) +{ + uint32_t mask; + channel_info->channel_count = number_of_channels; + for (uint8_t n = 0; n < 8; n++) { + if (number_of_channels >= 32) { + mask = 0xffffffff; + number_of_channels -= 32; + } else if (number_of_channels) { + mask = 0; + //Start bit enable to MSB + for (uint16_t i = 0; i < (number_of_channels % 32); i++) { + mask |= 1 << i; + } + number_of_channels = 0; + } else { + mask = 0; + } + channel_info->channel_mask[n] = mask; + } +} + +static void ws_neighbour_excluded_mask_by_range(ws_channel_mask_t *channel_info, ws_excluded_channel_range_t *range_info, uint16_t number_of_channels) +{ + uint16_t range_start, range_stop; + uint8_t mask_index = 0; + uint32_t compare_mask_bit; + uint8_t *range_ptr = range_info->range_start; + while (range_info->number_of_range) { + range_start = common_read_16_bit_inverse(range_ptr); + range_ptr += 2; + range_stop = common_read_16_bit_inverse(range_ptr); + range_ptr += 2; + range_info->number_of_range--; + for (uint16_t channel = 0; channel < number_of_channels; channel++) { + + if (channel >= range_start && channel <= range_stop) { + //Cut channel + compare_mask_bit = 1 << (channel % 32); + mask_index = 0 + (channel / 32); + + if (channel_info->channel_mask[mask_index] & compare_mask_bit) { + channel_info->channel_mask[mask_index] ^= compare_mask_bit; + channel_info->channel_count--; + } + } else if (channel > range_stop) { + break; + } + } + } +} + +static uint32_t ws_reserve_order_32_bit(uint32_t value) +{ + uint32_t ret_val = 0; + for (uint8_t i = 0; i < 32; i++) { + if ((value & (1 << i))) { + ret_val |= 1 << ((32 - 1) - i); + } + } + return ret_val; +} + +static void ws_neighbour_excluded_mask_by_mask(ws_channel_mask_t *channel_info, ws_excluded_channel_mask_t *mask_info, uint16_t number_of_channels) +{ + if (mask_info->mask_len_inline == 0) { + return; + } + + uint16_t channel_at_mask; + uint8_t mask_index = 0; + uint32_t channel_compare_mask, compare_mask_bit; + uint8_t *mask_ptr = mask_info->channel_mask; + + channel_at_mask = mask_info->mask_len_inline * 8; + + for (uint16_t channel = 0; channel < number_of_channels; channel += 32) { + if (channel) { + mask_index++; + mask_ptr += 4; + } + + //Read allaways 32-bit + if (channel_at_mask >= 32) { + channel_compare_mask = common_read_32_bit(mask_ptr); + channel_at_mask -= 32; + } else { + //Read Rest bytes seprately + channel_compare_mask = 0; + uint8_t move_mask = 0; + //Convert 8-24bit to 32-bit + while (channel_at_mask) { + channel_compare_mask |= (uint32_t)(*mask_ptr++ << (24 - move_mask)); + channel_at_mask -= 8; + move_mask += 8; + } + } + //Reserve bit order for compare + channel_compare_mask = ws_reserve_order_32_bit(channel_compare_mask); + //Compare now 32-bit mask's bits one by one + for (uint8_t i = 0; i < 32; i++) { + //Start from MSB + compare_mask_bit = 1 << (i); + if ((channel_compare_mask & compare_mask_bit) && (channel_info->channel_mask[mask_index] & compare_mask_bit)) { + channel_info->channel_mask[mask_index] ^= compare_mask_bit; + channel_info->channel_count--; + } + } + //Stop compare if all bits in line are compared + if (channel_at_mask == 0) { + break; + } + } +} + void ws_neighbor_class_neighbor_unicast_schedule_set(ws_neighbor_class_entry_t *ws_neighbor, ws_us_ie_t *ws_us) { ws_neighbor->fhss_data.uc_timing_info.unicast_channel_function = ws_us->channel_function; @@ -105,9 +221,21 @@ void ws_neighbor_class_neighbor_unicast_schedule_set(ws_neighbor_class_entry_t * ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels = ws_common_channel_number_calc(ws_us->plan.zero.regulator_domain, ws_us->plan.zero.operation_class); } else if (ws_us->channel_plan == 1) { ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels = ws_us->plan.one.number_of_channel; - } else { - ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels = 0; } + + //Handle excluded channel and generate activate channel list + if (ws_us->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_RANGE) { + ws_neighbour_channel_list_enable_all(&ws_neighbor->fhss_data.uc_channel_list, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels); + ws_neighbour_excluded_mask_by_range(&ws_neighbor->fhss_data.uc_channel_list, &ws_us->excluded_channels.range, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels); + } else if (ws_us->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_BITMASK) { + ws_neighbour_channel_list_enable_all(&ws_neighbor->fhss_data.uc_channel_list, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels); + ws_neighbour_excluded_mask_by_mask(&ws_neighbor->fhss_data.uc_channel_list, &ws_us->excluded_channels.mask, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels); + } else if (ws_us->excluded_channel_ctrl == WS_EXC_CHAN_CTRL_NONE) { + if (ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels != ws_neighbor->fhss_data.uc_channel_list.channel_count) { + ws_neighbour_channel_list_enable_all(&ws_neighbor->fhss_data.uc_channel_list, ws_neighbor->fhss_data.uc_timing_info.unicast_number_of_channels); + } + } + } ws_neighbor->fhss_data.uc_timing_info.unicast_dwell_interval = ws_us->dwell_interval; } diff --git a/source/6LoWPAN/ws/ws_pae_auth.c b/source/6LoWPAN/ws/ws_pae_auth.c index 01ffea5603..df50aea726 100644 --- a/source/6LoWPAN/ws/ws_pae_auth.c +++ b/source/6LoWPAN/ws/ws_pae_auth.c @@ -23,12 +23,14 @@ #include "ns_trace.h" #include "nsdynmemLIB.h" #include "fhss_config.h" +#include "ws_management_api.h" #include "eventOS_event.h" #include "eventOS_scheduler.h" #include "eventOS_event_timer.h" #include "ns_address.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/kmp/kmp_socket_if.h" @@ -39,6 +41,7 @@ #include "Security/protocols/tls_sec_prot/tls_sec_prot.h" #include "Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.h" #include "Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" #include "6LoWPAN/ws/ws_pae_controller.h" #include "6LoWPAN/ws/ws_pae_timers.h" #include "6LoWPAN/ws/ws_pae_auth.h" @@ -56,8 +59,6 @@ // Wait for for supplicant to indicate activity (e.g. to send a message) #define WAIT_FOR_AUTHENTICATION_TICKS 5 * 60 * 10 // 5 minutes -// Maximum number of simultaneous EAP-TLS negotiations -#define MAX_SIMULTANEOUS_EAP_TLS_NEGOTIATIONS 3 /* If EAP-TLS is delayed due to simultaneous negotiations limit, defines how long to wait for previous negotiation to complete */ @@ -86,7 +87,8 @@ typedef struct { sec_prot_gtk_keys_t *gtks; /**< GTKs */ sec_prot_gtk_keys_t *next_gtks; /**< Next GTKs */ const sec_prot_certs_t *certs; /**< Certificates */ - timer_settings_t *timer_settings; /**< Timer settings */ + sec_timer_cfg_t *sec_timer_cfg; /**< Timer configuration */ + sec_prot_cfg_t *sec_prot_cfg; /**< Protocol Configuration */ uint16_t supp_max_number; /**< Max number of stored supplicants */ uint16_t slow_timer_seconds; /**< Slow timer seconds */ bool timer_running : 1; /**< Timer is running */ @@ -117,13 +119,13 @@ static void ws_pae_auth_kmp_api_create_indication(kmp_api_t *kmp, kmp_type_e typ static void ws_pae_auth_kmp_api_finished_indication(kmp_api_t *kmp, kmp_result_e result, kmp_sec_keys_t *sec_keys); static void ws_pae_auth_next_kmp_trigger(pae_auth_t *pae_auth, supp_entry_t *supp_entry); static kmp_type_e ws_pae_auth_next_protocol_get(pae_auth_t *pae_auth, supp_entry_t *supp_entry); -static kmp_api_t *ws_pae_auth_kmp_create_and_start(kmp_service_t *service, kmp_type_e type, supp_entry_t *supp_entry); +static kmp_api_t *ws_pae_auth_kmp_create_and_start(kmp_service_t *service, kmp_type_e type, supp_entry_t *supp_entry, sec_prot_cfg_t *cfg); static void ws_pae_auth_kmp_api_finished(kmp_api_t *kmp); static int8_t tasklet_id = -1; static NS_LIST_DEFINE(pae_auth_list, pae_auth_t, link); -int8_t ws_pae_auth_init(protocol_interface_info_entry_t *interface_ptr, sec_prot_gtk_keys_t *gtks, sec_prot_gtk_keys_t *next_gtks, const sec_prot_certs_t *certs, timer_settings_t *timer_settings) +int8_t ws_pae_auth_init(protocol_interface_info_entry_t *interface_ptr, sec_prot_gtk_keys_t *gtks, sec_prot_gtk_keys_t *next_gtks, const sec_prot_certs_t *certs, sec_timer_cfg_t *sec_timer_cfg, sec_prot_cfg_t *sec_prot_cfg) { if (!interface_ptr || !gtks || !certs) { return -1; @@ -150,7 +152,8 @@ int8_t ws_pae_auth_init(protocol_interface_info_entry_t *interface_ptr, sec_prot pae_auth->gtks = gtks; pae_auth->next_gtks = next_gtks; pae_auth->certs = certs; - pae_auth->timer_settings = timer_settings; + pae_auth->sec_timer_cfg = sec_timer_cfg; + pae_auth->sec_prot_cfg = sec_prot_cfg; pae_auth->supp_max_number = SUPPLICANT_MAX_NUMBER; pae_auth->slow_timer_seconds = 0; @@ -215,14 +218,6 @@ error: return -1; } -int8_t ws_pae_auth_timing_adjust(uint8_t timing) -{ - auth_gkh_sec_prot_timing_adjust(timing); - auth_fwh_sec_prot_timing_adjust(timing); - auth_eap_tls_sec_prot_timing_adjust(timing); - return 0; -} - int8_t ws_pae_auth_addresses_set(protocol_interface_info_entry_t *interface_ptr, uint16_t local_port, const uint8_t *remote_addr, uint16_t remote_port) { if (!interface_ptr || !remote_addr) { @@ -387,7 +382,7 @@ int8_t ws_pae_auth_node_access_revoke_start(protocol_interface_info_entry_t *int // As default removes other keys than active int8_t not_removed_index = active_index; - uint32_t revocation_lifetime = ws_pae_timers_gtk_revocation_lifetime_get(pae_auth->timer_settings); + uint32_t revocation_lifetime = ws_pae_timers_gtk_revocation_lifetime_get(pae_auth->sec_timer_cfg); uint32_t active_lifetime = sec_prot_keys_gtk_lifetime_get(pae_auth->gtks, active_index); @@ -608,7 +603,7 @@ void ws_pae_auth_slow_timer(uint16_t seconds) uint32_t timer_seconds = sec_prot_keys_gtk_lifetime_decrement(pae_auth->gtks, i, seconds); if (active_index == i) { if (!pae_auth->gtk_new_inst_req_exp) { - pae_auth->gtk_new_inst_req_exp = ws_pae_timers_gtk_new_install_required(pae_auth->timer_settings, timer_seconds); + pae_auth->gtk_new_inst_req_exp = ws_pae_timers_gtk_new_install_required(pae_auth->sec_timer_cfg, timer_seconds); if (pae_auth->gtk_new_inst_req_exp) { int8_t second_index = sec_prot_keys_gtk_install_order_second_index_get(pae_auth->gtks); if (second_index < 0) { @@ -622,7 +617,7 @@ void ws_pae_auth_slow_timer(uint16_t seconds) } if (!pae_auth->gtk_new_act_time_exp) { - pae_auth->gtk_new_act_time_exp = ws_pae_timers_gtk_new_activation_time(pae_auth->timer_settings, timer_seconds); + pae_auth->gtk_new_act_time_exp = ws_pae_timers_gtk_new_activation_time(pae_auth->sec_timer_cfg, timer_seconds); if (pae_auth->gtk_new_act_time_exp) { int8_t new_active_index = ws_pae_auth_new_gtk_activate(pae_auth); tr_info("GTK new activation time active index: %i, time: %"PRIu32", new index: %i, system time: %"PRIu32"", active_index, timer_seconds, new_active_index, protocol_core_monotonic_time / 10); @@ -644,8 +639,8 @@ void ws_pae_auth_slow_timer(uint16_t seconds) pae_auth->slow_timer_seconds += seconds; if (pae_auth->slow_timer_seconds > 60) { - ws_pae_lib_supp_list_slow_timer_update(&pae_auth->active_supp_list, pae_auth->timer_settings, pae_auth->slow_timer_seconds); - ws_pae_lib_supp_list_slow_timer_update(&pae_auth->inactive_supp_list, pae_auth->timer_settings, pae_auth->slow_timer_seconds); + ws_pae_lib_supp_list_slow_timer_update(&pae_auth->active_supp_list, pae_auth->sec_timer_cfg, pae_auth->slow_timer_seconds); + ws_pae_lib_supp_list_slow_timer_update(&pae_auth->inactive_supp_list, pae_auth->sec_timer_cfg, pae_auth->slow_timer_seconds); pae_auth->slow_timer_seconds = 0; } } @@ -675,7 +670,7 @@ static void ws_pae_auth_gtk_key_insert(pae_auth_t *pae_auth) } // Gets latest installed key lifetime and adds GTK expire offset to it - uint32_t lifetime = pae_auth->timer_settings->gtk_expire_offset; + uint32_t lifetime = pae_auth->sec_timer_cfg->gtk_expire_offset; int8_t last_index = sec_prot_keys_gtk_install_order_last_index_get(pae_auth->gtks); if (last_index >= 0) { lifetime += sec_prot_keys_gtk_lifetime_get(pae_auth->gtks, last_index); @@ -838,7 +833,7 @@ static kmp_api_t *ws_pae_auth_kmp_incoming_ind(kmp_service_t *service, kmp_type_ } // Create a new KMP for initial eapol-key - kmp = kmp_api_create(service, type + IEEE_802_1X_INITIAL_KEY); + kmp = kmp_api_create(service, type + IEEE_802_1X_INITIAL_KEY, pae_auth->sec_prot_cfg); if (!kmp) { return 0; @@ -944,7 +939,7 @@ static void ws_pae_auth_next_kmp_trigger(pae_auth_t *pae_auth, supp_entry_t *sup supplicant. Otherwise supplicant must re-send initial EAPOL-Key to try again using its trickle schedule */ uint16_t ongoing_eap_tls_cnt = ws_pae_lib_supp_list_kmp_count(&pae_auth->active_supp_list, IEEE_802_1X_MKA); - if (ongoing_eap_tls_cnt >= MAX_SIMULTANEOUS_EAP_TLS_NEGOTIATIONS) { + if (ongoing_eap_tls_cnt >= pae_auth->sec_prot_cfg->sec_max_ongoing_authentication) { supp_entry->retry_ticks = EAP_TLS_NEGOTIATION_TRIGGER_TIMEOUT; tr_info("EAP-TLS max ongoing reached, count %i, delayed: eui-64: %s", ongoing_eap_tls_cnt, trace_array(supp_entry->addr.eui_64, 8)); return; @@ -952,7 +947,7 @@ static void ws_pae_auth_next_kmp_trigger(pae_auth_t *pae_auth, supp_entry_t *sup } // Create new instance - kmp_api_t *new_kmp = ws_pae_auth_kmp_create_and_start(pae_auth->kmp_service, next_type, supp_entry); + kmp_api_t *new_kmp = ws_pae_auth_kmp_create_and_start(pae_auth->kmp_service, next_type, supp_entry, pae_auth->sec_prot_cfg); if (!new_kmp) { return; } @@ -965,7 +960,7 @@ static void ws_pae_auth_next_kmp_trigger(pae_auth_t *pae_auth, supp_entry_t *sup return; } // Create TLS instance */ - if (ws_pae_auth_kmp_create_and_start(pae_auth->kmp_service, TLS_PROT, supp_entry) == NULL) { + if (ws_pae_auth_kmp_create_and_start(pae_auth->kmp_service, TLS_PROT, supp_entry, pae_auth->sec_prot_cfg) == NULL) { ws_pae_lib_kmp_list_delete(&supp_entry->kmp_list, new_kmp); return; } @@ -1009,7 +1004,7 @@ static kmp_type_e ws_pae_auth_next_protocol_get(pae_auth_t *pae_auth, supp_entry * has been, trigger 4WH to update also the PTK. This prevents writing multiple * GTK keys to same index using same PTK. */ - if (pae_auth->timer_settings->gtk_expire_offset > SHORT_GTK_LIFETIME && + if (pae_auth->sec_timer_cfg->gtk_expire_offset > SHORT_GTK_LIFETIME && sec_prot_keys_ptk_installed_gtk_hash_mismatch_check(sec_keys, gtk_index)) { // start 4WH towards supplicant next_type = IEEE_802_11_4WH; @@ -1033,10 +1028,10 @@ static kmp_type_e ws_pae_auth_next_protocol_get(pae_auth_t *pae_auth, supp_entry } -static kmp_api_t *ws_pae_auth_kmp_create_and_start(kmp_service_t *service, kmp_type_e type, supp_entry_t *supp_entry) +static kmp_api_t *ws_pae_auth_kmp_create_and_start(kmp_service_t *service, kmp_type_e type, supp_entry_t *supp_entry, sec_prot_cfg_t *cfg) { // Create KMP instance for new authentication - kmp_api_t *kmp = kmp_api_create(service, type); + kmp_api_t *kmp = kmp_api_create(service, type, cfg); if (!kmp) { return NULL; diff --git a/source/6LoWPAN/ws/ws_pae_auth.h b/source/6LoWPAN/ws/ws_pae_auth.h index 04bd157d78..5bf680f4ab 100644 --- a/source/6LoWPAN/ws/ws_pae_auth.h +++ b/source/6LoWPAN/ws/ws_pae_auth.h @@ -47,34 +47,14 @@ * \param next_gtks next group keys to be used * \param cert_chain certificate chain * \param timer_settings timer settings + * \param sec_timer_cfg timer configuration + * \param sec_prot_cfg protocol configuration * * \return < 0 failure * \return >= 0 success * */ -int8_t ws_pae_auth_init(protocol_interface_info_entry_t *interface_ptr, sec_prot_gtk_keys_t *gtks, sec_prot_gtk_keys_t *next_gtks, const sec_prot_certs_t *certs, timer_settings_t *timer_settings); - -/** - * ws_pae_auth_timing_adjust Adjust retries and timings of the security protocols - * - * Timing value is a generic number between 0 to 32 that goes from fast and - * reactive network to low bandwidth and long latency. - * - * example value definitions: - * 0-8 very fast network - * 9-16 medium network - * 16-24 slow network - * 25-32 extremely slow network - * - * There is no need to have lots variations in every layer if protocol is not very active in any case. - * - * \param timing Timing value. - * - * \return < 0 failure - * \return >= 0 success - * - */ -int8_t ws_pae_auth_timing_adjust(uint8_t timing); +int8_t ws_pae_auth_init(protocol_interface_info_entry_t *interface_ptr, sec_prot_gtk_keys_t *gtks, sec_prot_gtk_keys_t *next_gtks, const sec_prot_certs_t *certs, sec_timer_cfg_t *sec_timer_cfg, sec_prot_cfg_t *sec_prot_cfg); /** * ws_pae_auth_addresses_set set relay addresses @@ -231,7 +211,7 @@ void ws_pae_auth_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_ #else -#define ws_pae_auth_init(interface_ptr, gtks, next_gtks, certs, timer_settings) 1 +#define ws_pae_auth_init(interface_ptr, gtks, next_gtks, certs, sec_timer_cfg, sec_prot_cfg) 1 #define ws_pae_auth_timing_adjust(timing) #define ws_pae_auth_addresses_set(interface_ptr, local_port, remote_addr, remote_port) 1 #define ws_pae_auth_delete NULL diff --git a/source/6LoWPAN/ws/ws_pae_controller.c b/source/6LoWPAN/ws/ws_pae_controller.c index f5bc4dba92..cf73b0a9da 100644 --- a/source/6LoWPAN/ws/ws_pae_controller.c +++ b/source/6LoWPAN/ws/ws_pae_controller.c @@ -23,9 +23,12 @@ #include "nsdynmemLIB.h" #include "fhss_config.h" #include "ns_address.h" +#include "ws_management_api.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" #include "6LoWPAN/ws/ws_pae_controller.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/protocols/sec_prot_certs.h" #include "Security/protocols/sec_prot_keys.h" #include "6LoWPAN/ws/ws_pae_timers.h" @@ -67,7 +70,8 @@ typedef struct { char *network_name; /**< Network name for GAK generation */ uint16_t frame_cnt_store_timer; /**< Timer for storing frame counter value */ frame_counters_t frame_counters; /**< Frame counters */ - timer_settings_t timer_settings; /**< Timer settings */ + sec_timer_cfg_t sec_timer_cfg; /**< Timer configuration (configuration set values) */ + sec_prot_cfg_t sec_prot_cfg; /**< Configuration */ protocol_interface_info_entry_t *interface_ptr; /**< List link entry */ ws_pae_controller_auth_completed *auth_completed; /**< Authentication completed callback, continue bootstrap */ ws_pae_controller_nw_key_set *nw_key_set; /**< Key set callback */ @@ -576,6 +580,8 @@ int8_t ws_pae_controller_init(protocol_interface_info_entry_t *interface_ptr) controller->nw_frame_counter_set = NULL; controller->pan_ver_increment = NULL; controller->pae_nvm_buffer = pae_nvm_buffer; + memset(&controller->sec_timer_cfg, 0, sizeof(ws_sec_timer_cfg_t)); + memset(&controller->sec_prot_cfg, 0, sizeof(sec_prot_cfg_t)); ws_pae_controller_data_init(controller); @@ -584,6 +590,30 @@ int8_t ws_pae_controller_init(protocol_interface_info_entry_t *interface_ptr) return 0; } +int8_t ws_pae_controller_configure(protocol_interface_info_entry_t *interface_ptr, struct ws_sec_timer_cfg_s *sec_timer_cfg, struct ws_sec_prot_cfg_s *sec_prot_cfg) +{ + pae_controller_t *controller = ws_pae_controller_get(interface_ptr); + if (controller == NULL) { + return 0; + } + + if (sec_prot_cfg) { + controller->sec_prot_cfg.sec_prot_trickle_params.Imin = sec_prot_cfg->sec_prot_trickle_imin * 10; + controller->sec_prot_cfg.sec_prot_trickle_params.Imax = sec_prot_cfg->sec_prot_trickle_imax * 10; + controller->sec_prot_cfg.sec_prot_trickle_params.k = 0; + controller->sec_prot_cfg.sec_prot_trickle_params.TimerExpirations = sec_prot_cfg->sec_prot_trickle_timer_exp; + controller->sec_prot_cfg.sec_prot_retry_timeout = sec_prot_cfg->sec_prot_retry_timeout * 10; + controller->sec_prot_cfg.sec_max_ongoing_authentication = sec_prot_cfg->sec_max_ongoing_authentication; + } + + if (sec_timer_cfg) { + ws_pae_timers_settings_init(&controller->sec_timer_cfg, sec_timer_cfg); + } + + return 0; +} + + static void ws_pae_controller_data_init(pae_controller_t *controller) { memset(controller->target_eui_64, 0, 8); @@ -616,7 +646,6 @@ static void ws_pae_controller_data_init(pae_controller_t *controller) sec_prot_keys_gtks_init(&controller->next_gtks); sec_prot_certs_init(&controller->certs); sec_prot_certs_ext_certificate_validation_set(&controller->certs, pae_controller_config.ext_cert_valid_enabled); - ws_pae_timers_settings_init(&controller->timer_settings); } static void ws_pae_controller_frame_counter_read(pae_controller_t *controller) @@ -667,7 +696,7 @@ int8_t ws_pae_controller_supp_init(protocol_interface_info_entry_t *interface_pt return -1; } - if (ws_pae_supp_init(controller->interface_ptr, &controller->certs, &controller->timer_settings) < 0) { + if (ws_pae_supp_init(controller->interface_ptr, &controller->certs, &controller->sec_timer_cfg, &controller->sec_prot_cfg) < 0) { return -1; } @@ -693,7 +722,7 @@ int8_t ws_pae_controller_auth_init(protocol_interface_info_entry_t *interface_pt return -1; } - if (ws_pae_auth_init(controller->interface_ptr, &controller->gtks, &controller->next_gtks, &controller->certs, &controller->timer_settings) < 0) { + if (ws_pae_auth_init(controller->interface_ptr, &controller->gtks, &controller->next_gtks, &controller->certs, &controller->sec_timer_cfg, &controller->sec_prot_cfg) < 0) { return -1; } @@ -752,13 +781,6 @@ int8_t ws_pae_controller_delete(protocol_interface_info_entry_t *interface_ptr) return 0; } -int8_t ws_pae_controller_timing_adjust(uint8_t timing) -{ - ws_pae_supp_timing_adjust(timing); - ws_pae_auth_timing_adjust(timing); - return 0; -} - int8_t ws_pae_controller_certificate_chain_set(const arm_certificate_chain_entry_s *new_chain) { if (!new_chain) { @@ -998,7 +1020,7 @@ int8_t ws_pae_controller_gtk_update(int8_t interface_id, uint8_t *gtk[GTK_NUM]) for (uint8_t i = 0; i < GTK_NUM; i++) { if (gtk[i]) { uint32_t lifetime = sec_prot_keys_gtk_install_order_last_lifetime_get(&controller->gtks); - lifetime += controller->timer_settings.gtk_expire_offset; + lifetime += controller->sec_timer_cfg.gtk_expire_offset; if (sec_prot_keys_gtk_set(&controller->gtks, i, gtk[i], lifetime) >= 0) { controller->gtks_set = true; tr_info("GTK set index: %i, lifetime %"PRIu32", system time: %"PRIu32"", i, lifetime, protocol_core_monotonic_time / 10); @@ -1053,30 +1075,6 @@ int8_t ws_pae_controller_active_key_update(int8_t interface_id, uint8_t index) return 0; } -int8_t ws_pae_controller_key_lifetime_update(int8_t interface_id, uint32_t gtk_lifetime, uint32_t pmk_lifetime, uint32_t ptk_lifetime) -{ - pae_controller_t *controller = ws_pae_controller_get_or_create(interface_id); - if (!controller) { - return -1; - } - - ws_pae_timers_lifetime_set(&controller->timer_settings, gtk_lifetime, pmk_lifetime, ptk_lifetime); - - return 0; -} - -int8_t ws_pae_controller_gtk_time_settings_update(int8_t interface_id, uint8_t revocat_lifetime_reduct, uint8_t new_activation_time, uint8_t new_install_req, uint32_t max_mismatch) -{ - pae_controller_t *controller = ws_pae_controller_get_or_create(interface_id); - if (!controller) { - return -1; - } - - ws_pae_timers_gtk_time_settings_set(&controller->timer_settings, revocat_lifetime_reduct, new_activation_time, new_install_req, max_mismatch); - - return 0; -} - int8_t ws_pae_controller_node_keys_remove(int8_t interface_id, uint8_t *eui_64) { #ifndef HAVE_PAE_AUTH diff --git a/source/6LoWPAN/ws/ws_pae_controller.h b/source/6LoWPAN/ws/ws_pae_controller.h index eb58253976..9a16b769d1 100644 --- a/source/6LoWPAN/ws/ws_pae_controller.h +++ b/source/6LoWPAN/ws/ws_pae_controller.h @@ -28,6 +28,8 @@ typedef enum { } auth_result_e; struct nvm_tlv_entry; +struct ws_sec_timer_cfg_s; +struct ws_sec_prot_cfg_s; /** * ws_pae_controller_set_target sets EAPOL target for PAE supplicant @@ -89,6 +91,19 @@ int8_t ws_pae_controller_authenticator_start(protocol_interface_info_entry_t *in */ int8_t ws_pae_controller_init(protocol_interface_info_entry_t *interface_ptr); +/** + * ws_pae_controller_config_set sets PAE controller configuration + * + * \param interface_ptr interface + * \param sec_timer_cfg timer configuration or NULL if not set + * \param sec_prot_cfg protocol configuration or NULL if not set + * + * \return < 0 failure + * \return >= 0 success + * + */ +int8_t ws_pae_controller_configure(protocol_interface_info_entry_t *interface_ptr, struct ws_sec_timer_cfg_s *sec_timer_cfg, struct ws_sec_prot_cfg_s *sec_prot_cfg); + /** * ws_pae_controller_init initializes PAE supplicant * @@ -133,28 +148,6 @@ int8_t ws_pae_controller_stop(protocol_interface_info_entry_t *interface_ptr); */ int8_t ws_pae_controller_delete(protocol_interface_info_entry_t *interface_ptr); -/** - * ws_pae_controller_timing_adjust Adjust retries and timings of the security protocols - * - * Timing value is a generic number between 0 to 32 that goes from fast and - * reactive network to low bandwidth and long latency. - * - * example value definitions: - * 0-8 very fast network - * 9-16 medium network - * 16-24 slow network - * 25-32 extremely slow network - * - * There is no need to have lots variations in every layer if protocol is not very active in any case. - * - * \param timing Timing value. - * - * \return < 0 failure - * \return >= 0 success - * - */ -int8_t ws_pae_controller_timing_adjust(uint8_t timing); - /** * ws_pae_controller_certificate_chain_set set certificate chain * diff --git a/source/6LoWPAN/ws/ws_pae_lib.c b/source/6LoWPAN/ws/ws_pae_lib.c index 455ba76f64..4394ee1dc8 100644 --- a/source/6LoWPAN/ws/ws_pae_lib.c +++ b/source/6LoWPAN/ws/ws_pae_lib.c @@ -22,13 +22,16 @@ #include "ns_trace.h" #include "nsdynmemLIB.h" #include "fhss_config.h" +#include "ws_management_api.h" #include "NWK_INTERFACE/Include/protocol.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" #include "6LoWPAN/ws/ws_config.h" +#include "6LoWPAN/ws/ws_pae_timers.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/protocols/sec_prot_certs.h" #include "Security/protocols/sec_prot_keys.h" -#include "6LoWPAN/ws/ws_pae_timers.h" #include "6LoWPAN/ws/ws_pae_lib.h" #ifdef HAVE_WS @@ -228,7 +231,7 @@ bool ws_pae_lib_supp_list_timer_update(supp_list_t *active_supp_list, supp_list_ return timer_running; } -void ws_pae_lib_supp_list_slow_timer_update(supp_list_t *supp_list, timer_settings_t *timer_settings, uint16_t seconds) +void ws_pae_lib_supp_list_slow_timer_update(supp_list_t *supp_list, sec_timer_cfg_t *timer_settings, uint16_t seconds) { ns_list_foreach(supp_entry_t, entry, supp_list) { if (sec_prot_keys_pmk_lifetime_decrement(&entry->sec_keys, timer_settings->pmk_lifetime, seconds)) { diff --git a/source/6LoWPAN/ws/ws_pae_lib.h b/source/6LoWPAN/ws/ws_pae_lib.h index 3ee6f10d0f..b045fd00fd 100644 --- a/source/6LoWPAN/ws/ws_pae_lib.h +++ b/source/6LoWPAN/ws/ws_pae_lib.h @@ -233,7 +233,7 @@ bool ws_pae_lib_supp_list_timer_update(supp_list_t *active_supp_list, supp_list_ * \param seconds seconds * */ -void ws_pae_lib_supp_list_slow_timer_update(supp_list_t *supp_list, timer_settings_t *timer_settings, uint16_t seconds); +void ws_pae_lib_supp_list_slow_timer_update(supp_list_t *supp_list, sec_timer_cfg_t *timer_settings, uint16_t seconds); /** * ws_pae_lib_supp_list_timer_update updates supplicant timers diff --git a/source/6LoWPAN/ws/ws_pae_supp.c b/source/6LoWPAN/ws/ws_pae_supp.c index db891dc6e4..a9e955366e 100644 --- a/source/6LoWPAN/ws/ws_pae_supp.c +++ b/source/6LoWPAN/ws/ws_pae_supp.c @@ -23,6 +23,7 @@ #include "ns_trace.h" #include "nsdynmemLIB.h" #include "fhss_config.h" +#include "ws_management_api.h" #include "eventOS_event.h" #include "eventOS_scheduler.h" #include "eventOS_event_timer.h" @@ -32,6 +33,7 @@ #include "RPL/rpl_control.h" #include "RPL/rpl_data.h" #include "6LoWPAN/ws/ws_config.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/protocols/sec_prot_certs.h" @@ -41,6 +43,7 @@ #include "Security/protocols/tls_sec_prot/tls_sec_prot.h" #include "Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.h" #include "Security/protocols/gkh_sec_prot/supp_gkh_sec_prot.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" #include "6LoWPAN/ws/ws_pae_controller.h" #include "6LoWPAN/ws/ws_pae_timers.h" #include "6LoWPAN/ws/ws_pae_supp.h" @@ -101,7 +104,8 @@ typedef struct { sec_prot_gtk_keys_t gtks; /**< GTKs */ uint8_t new_br_eui_64[8]; /**< Border router EUI-64 indicated by bootstrap */ sec_prot_keys_nw_info_t sec_keys_nw_info; /**< Security keys network information */ - timer_settings_t *timer_settings; /**< Timer settings */ + sec_timer_cfg_t *sec_timer_cfg; /**< Timer configuration */ + sec_prot_cfg_t *sec_prot_cfg; /**< Protocol Configuration */ uint8_t nw_keys_used_cnt; /**< How many times bootstrap has been tried with current keys */ uint8_t initial_key_retry_cnt; /**< initial EAPOL-Key retry counter */ bool auth_trickle_running : 1; /**< Initial EAPOL-Key Trickle timer running */ @@ -370,7 +374,7 @@ int8_t ws_pae_supp_gtk_hash_update(protocol_interface_info_entry_t *interface_pt // Starts supplicant timer ws_pae_supp_timer_start(pae_supp); - tr_info("GTK update start imin: %i, imax: %i, max mismatch: %i, tr time: %i", pae_supp->timer_settings->gtk_request_imin, pae_supp->timer_settings->gtk_request_imax, pae_supp->timer_settings->gtk_max_mismatch, pae_supp->auth_trickle_timer.t); + tr_info("GTK update start imin: %i, imax: %i, max mismatch: %i, tr time: %i", pae_supp->sec_timer_cfg->gtk_request_imin, pae_supp->sec_timer_cfg->gtk_request_imax, pae_supp->sec_timer_cfg->gtk_max_mismatch, pae_supp->auth_trickle_timer.t); } } @@ -618,7 +622,7 @@ void ws_pae_supp_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_ pae_supp->gtk_hash_ptr_get = gtk_hash_ptr_get; } -int8_t ws_pae_supp_init(protocol_interface_info_entry_t *interface_ptr, const sec_prot_certs_t *certs, timer_settings_t *timer_settings) +int8_t ws_pae_supp_init(protocol_interface_info_entry_t *interface_ptr, const sec_prot_certs_t *certs, sec_timer_cfg_t *sec_timer_cfg, sec_prot_cfg_t *sec_prot_cfg) { if (!interface_ptr) { return -1; @@ -641,8 +645,9 @@ int8_t ws_pae_supp_init(protocol_interface_info_entry_t *interface_ptr, const se pae_supp->initial_key_timer = 0; pae_supp->initial_key_retry_timer = 0; pae_supp->nw_keys_used_cnt = 0; - pae_supp->timer_settings = timer_settings; pae_supp->initial_key_retry_cnt = INITIAL_KEY_RETRY_COUNT; + pae_supp->sec_timer_cfg = sec_timer_cfg; + pae_supp->sec_prot_cfg = sec_prot_cfg; pae_supp->auth_trickle_running = false; pae_supp->auth_requested = false; pae_supp->timer_running = false; @@ -744,14 +749,6 @@ int8_t ws_pae_supp_delete(protocol_interface_info_entry_t *interface_ptr) return 0; } -int8_t ws_pae_supp_timing_adjust(uint8_t timing) -{ - timing_value = timing; - supp_fwh_sec_prot_timing_adjust(timing); - supp_eap_sec_prot_timing_adjust(timing); - return 0; -} - static void ws_pae_supp_free(pae_supp_t *pae_supp) { if (!pae_supp) { @@ -998,8 +995,8 @@ static void ws_pae_supp_initial_last_interval_trickle_timer_start(pae_supp_t *pa static void ws_pae_supp_initial_key_update_trickle_timer_start(pae_supp_t *pae_supp, uint8_t timer_expirations) { // Starts trickle for the key update - pae_supp->auth_trickle_params.Imin = pae_supp->timer_settings->gtk_request_imin; - pae_supp->auth_trickle_params.Imax = pae_supp->timer_settings->gtk_request_imax; + pae_supp->auth_trickle_params.Imin = pae_supp->sec_timer_cfg->gtk_request_imin; + pae_supp->auth_trickle_params.Imax = pae_supp->sec_timer_cfg->gtk_request_imax; pae_supp->auth_trickle_params.k = 0; pae_supp->auth_trickle_params.TimerExpirations = timer_expirations; @@ -1216,7 +1213,7 @@ static kmp_api_t *ws_pae_supp_kmp_incoming_ind(kmp_service_t *service, kmp_type_ static kmp_api_t *ws_pae_supp_kmp_create_and_start(kmp_service_t *service, kmp_type_e type, pae_supp_t *pae_supp) { // Create new instance - kmp_api_t *kmp = kmp_api_create(service, type); + kmp_api_t *kmp = kmp_api_create(service, type, pae_supp->sec_prot_cfg); if (!kmp) { return NULL; } diff --git a/source/6LoWPAN/ws/ws_pae_supp.h b/source/6LoWPAN/ws/ws_pae_supp.h index 458ed7bf9e..3bfbc095c5 100644 --- a/source/6LoWPAN/ws/ws_pae_supp.h +++ b/source/6LoWPAN/ws/ws_pae_supp.h @@ -38,13 +38,14 @@ * * \param interface_ptr interface * \param cert_chain certificate chain - * \param timer_settings timer settings + * \param sec_timer_cfg timer configuration + * \param sec_prot_cfg protocol configuration * * \return < 0 failure * \return >= 0 success * */ -int8_t ws_pae_supp_init(protocol_interface_info_entry_t *interface_ptr, const sec_prot_certs_t *certs, timer_settings_t *timer_settings); +int8_t ws_pae_supp_init(protocol_interface_info_entry_t *interface_ptr, const sec_prot_certs_t *certs, sec_timer_cfg_t *sec_timer_cfg, sec_prot_cfg_t *sec_prot_cfg); /** * ws_pae_supp_delete deletes PAE supplicant @@ -57,29 +58,6 @@ int8_t ws_pae_supp_init(protocol_interface_info_entry_t *interface_ptr, const se */ int8_t ws_pae_supp_delete(protocol_interface_info_entry_t *interface_ptr); - -/** - * ws_pae_supp_timing_adjust Adjust retries and timings of the 4WH protocol - * - * Timing value is a generic number between 0 to 32 that goes from fast and - * reactive network to low bandwidth and long latency. - * - * example value definitions: - * 0-8 very fast network - * 9-16 medium network - * 16-24 slow network - * 25-32 extremely slow network - * - * There is no need to have lots variations in every layer if protocol is not very active in any case. - * - * \param timing Timing value. - * - * \return < 0 failure - * \return >= 0 success - * - */ -int8_t ws_pae_supp_timing_adjust(uint8_t timing); - /** * ws_pae_supp_fast_timer PAE supplicant fast timer call * @@ -259,7 +237,7 @@ void ws_pae_supp_cb_register(protocol_interface_info_entry_t *interface_ptr, ws_ #else -#define ws_pae_supp_init(interface_ptr, certs, timer_settings) 1 +#define ws_pae_supp_init(interface_ptr, certs, sec_timer_cfg, sec_prot_cfg) 1 #define ws_pae_supp_delete NULL #define ws_pae_supp_timing_adjust(timing) 1 #define ws_pae_supp_cb_register(interface_ptr, completed, nw_key_insert, nw_key_index_set) diff --git a/source/6LoWPAN/ws/ws_pae_timers.c b/source/6LoWPAN/ws/ws_pae_timers.c index d73dc70e21..fd3f02e621 100644 --- a/source/6LoWPAN/ws/ws_pae_timers.c +++ b/source/6LoWPAN/ws/ws_pae_timers.c @@ -22,44 +22,43 @@ #include "ns_trace.h" #include "nsdynmemLIB.h" #include "fhss_config.h" +#include "ws_management_api.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" #include "6LoWPAN/ws/ws_pae_timers.h" #ifdef HAVE_WS #define TRACE_GROUP "wspt" -#define SECONDS_IN_DAY 24 * 60 * 60 -#define SECONDS_IN_MONTH 30 * SECONDS_IN_DAY #define SECONDS_IN_MINUTE 60 -#define DEFAULT_GTK_EXPIRE_OFFSET 43200 // 30 days -#define DEFAULT_PMK_LIFETIME 4 // 4 months -#define DEFAULT_PTK_LIFETIME 2 // 2 months -#define DEFAULT_GTK_NEW_ACTIVATION_TIME 720 // default 1/720 * 30 days --> 60 minutes -#define DEFAULT_REVOCATION_LIFETIME_REDUCTION 30 // default 1/30 * 30 days --> 1 day #define DEFAULT_GTK_REQUEST_IMIN 4 // 4 minutes #define DEFAULT_GTK_REQUEST_IMAX 64 // 64 minutes -#define DEFAULT_GTK_MAX_MISMATCH 64 // 64 minutes -#define DEFAULT_GTK_NEW_INSTALL_REQUIRED 80 // 80 percent of GTK lifetime --> 24 days -static void ws_pae_timers_calculate(timer_settings_t *timer_settings); +static void ws_pae_timers_calculate(sec_timer_cfg_t *timer_settings); -void ws_pae_timers_settings_init(timer_settings_t *timer_settings) +void ws_pae_timers_settings_init(sec_timer_cfg_t *timer_settings, ws_sec_timer_cfg_t *new_timer_settings) { - timer_settings->gtk_expire_offset = DEFAULT_GTK_EXPIRE_OFFSET * SECONDS_IN_MINUTE; - timer_settings->pmk_lifetime = DEFAULT_PMK_LIFETIME * SECONDS_IN_MONTH; - timer_settings->ptk_lifetime = DEFAULT_PTK_LIFETIME * SECONDS_IN_MONTH; - timer_settings->gtk_new_act_time = DEFAULT_GTK_NEW_ACTIVATION_TIME; - timer_settings->revocat_lifetime_reduct = DEFAULT_REVOCATION_LIFETIME_REDUCTION; - timer_settings->gtk_request_imin = DEFAULT_GTK_REQUEST_IMIN * SECONDS_IN_MINUTE; - timer_settings->gtk_request_imax = DEFAULT_GTK_REQUEST_IMAX * SECONDS_IN_MINUTE; - timer_settings->gtk_max_mismatch = DEFAULT_GTK_MAX_MISMATCH * SECONDS_IN_MINUTE; - timer_settings->gtk_new_install_req = DEFAULT_GTK_NEW_INSTALL_REQUIRED; + if (timer_settings == NULL || new_timer_settings == NULL) { + return; + } + + timer_settings->gtk_expire_offset = new_timer_settings->gtk_expire_offset * SECONDS_IN_MINUTE; + timer_settings->pmk_lifetime = new_timer_settings->pmk_lifetime * SECONDS_IN_MINUTE; + timer_settings->ptk_lifetime = new_timer_settings->ptk_lifetime * SECONDS_IN_MINUTE; + timer_settings->gtk_new_act_time = new_timer_settings->gtk_new_act_time; + timer_settings->revocat_lifetime_reduct = new_timer_settings->revocat_lifetime_reduct; + timer_settings->gtk_request_imin = new_timer_settings->gtk_request_imin * SECONDS_IN_MINUTE; + timer_settings->gtk_request_imax = new_timer_settings->gtk_request_imax * SECONDS_IN_MINUTE; + timer_settings->gtk_max_mismatch = new_timer_settings->gtk_max_mismatch * SECONDS_IN_MINUTE; + timer_settings->gtk_new_install_req = new_timer_settings->gtk_new_install_req; + + ws_pae_timers_calculate(timer_settings); } -void ws_pae_timers_lifetime_set(timer_settings_t *timer_settings, uint32_t gtk_lifetime, uint32_t pmk_lifetime, uint32_t ptk_lifetime) +void ws_pae_timers_lifetime_set(sec_timer_cfg_t *timer_settings, uint32_t gtk_lifetime, uint32_t pmk_lifetime, uint32_t ptk_lifetime) { if (gtk_lifetime) { timer_settings->gtk_expire_offset = gtk_lifetime * 60; @@ -73,7 +72,7 @@ void ws_pae_timers_lifetime_set(timer_settings_t *timer_settings, uint32_t gtk_l ws_pae_timers_calculate(timer_settings); } -void ws_pae_timers_gtk_time_settings_set(timer_settings_t *timer_settings, uint8_t revocat_lifetime_reduct, uint8_t new_activation_time, uint8_t new_install_req, uint32_t max_mismatch) +void ws_pae_timers_gtk_time_settings_set(sec_timer_cfg_t *timer_settings, uint8_t revocat_lifetime_reduct, uint8_t new_activation_time, uint8_t new_install_req, uint32_t max_mismatch) { if (revocat_lifetime_reduct) { timer_settings->revocat_lifetime_reduct = revocat_lifetime_reduct; @@ -90,7 +89,7 @@ void ws_pae_timers_gtk_time_settings_set(timer_settings_t *timer_settings, uint8 ws_pae_timers_calculate(timer_settings); } -static void ws_pae_timers_calculate(timer_settings_t *timer_settings) +static void ws_pae_timers_calculate(sec_timer_cfg_t *timer_settings) { // Calculate GTK_NEW_INSTALL_REQUIRED < 100 * (1 - 1 / REVOCATION_LIFETIME_REDUCTION) uint8_t calc_gtk_new_install_req = 100 - (100 / timer_settings->revocat_lifetime_reduct); @@ -106,9 +105,6 @@ static void ws_pae_timers_calculate(timer_settings_t *timer_settings) } // Verify that GTK request Imin and Imax are sensible when compared to revocation lifetime - timer_settings->gtk_request_imin = DEFAULT_GTK_REQUEST_IMIN * SECONDS_IN_MINUTE; - timer_settings->gtk_request_imax = DEFAULT_GTK_REQUEST_IMAX * SECONDS_IN_MINUTE; - uint32_t gtk_revocation_lifetime = timer_settings->gtk_expire_offset / timer_settings->revocat_lifetime_reduct; uint32_t new_activation_time = timer_settings->gtk_expire_offset / timer_settings->gtk_new_act_time; @@ -147,7 +143,7 @@ static void ws_pae_timers_calculate(timer_settings_t *timer_settings) } } -bool ws_pae_timers_gtk_new_install_required(timer_settings_t *timer_settings, uint32_t seconds) +bool ws_pae_timers_gtk_new_install_required(sec_timer_cfg_t *timer_settings, uint32_t seconds) { uint32_t gtk_new_install_req_seconds = timer_settings->gtk_expire_offset - timer_settings->gtk_new_install_req * timer_settings->gtk_expire_offset / 100; @@ -158,7 +154,7 @@ bool ws_pae_timers_gtk_new_install_required(timer_settings_t *timer_settings, ui } } -bool ws_pae_timers_gtk_new_activation_time(timer_settings_t *timer_settings, uint32_t seconds) +bool ws_pae_timers_gtk_new_activation_time(sec_timer_cfg_t *timer_settings, uint32_t seconds) { uint32_t gtk_gtk_new_activation_time_seconds = timer_settings->gtk_expire_offset / timer_settings->gtk_new_act_time; @@ -169,7 +165,7 @@ bool ws_pae_timers_gtk_new_activation_time(timer_settings_t *timer_settings, uin } } -uint32_t ws_pae_timers_gtk_revocation_lifetime_get(timer_settings_t *timer_settings) +uint32_t ws_pae_timers_gtk_revocation_lifetime_get(sec_timer_cfg_t *timer_settings) { return timer_settings->gtk_expire_offset / timer_settings->revocat_lifetime_reduct; } diff --git a/source/6LoWPAN/ws/ws_pae_timers.h b/source/6LoWPAN/ws/ws_pae_timers.h index 55b80a4d52..ec792996a0 100644 --- a/source/6LoWPAN/ws/ws_pae_timers.h +++ b/source/6LoWPAN/ws/ws_pae_timers.h @@ -18,25 +18,26 @@ #ifndef WS_PAE_TIMERS_H_ #define WS_PAE_TIMERS_H_ -typedef struct { - uint32_t gtk_expire_offset; // GTK lifetime; GTK_EXPIRE_OFFSET (seconds) - uint32_t pmk_lifetime; // PMK lifetime (seconds) - uint32_t ptk_lifetime; // PTK lifetime (seconds) - uint16_t gtk_new_act_time; // GTK_NEW_ACTIVATION_TIME (1/X of expire offset) - uint16_t revocat_lifetime_reduct; // REVOCATION_LIFETIME_REDUCTION (reduction of lifetime) - uint16_t gtk_request_imin; // GTK_REQUEST_IMIN (seconds) - uint16_t gtk_request_imax; // GTK_REQUEST_IMAX (seconds) - uint16_t gtk_max_mismatch; // GTK_MAX_MISMATCH (seconds) - uint8_t gtk_new_install_req; // GTK_NEW_INSTALL_REQUIRED (percent of GTK lifetime) -} timer_settings_t; +typedef struct sec_timer_cfg_s { + uint32_t gtk_expire_offset; /* GTK lifetime; GTK_EXPIRE_OFFSET (seconds) */ + uint32_t pmk_lifetime; /* PMK lifetime (seconds) */ + uint32_t ptk_lifetime; /* PTK lifetime (seconds) */ + uint16_t gtk_new_act_time; /* GTK_NEW_ACTIVATION_TIME (1/X of expire offset) */ + uint16_t revocat_lifetime_reduct; /* REVOCATION_LIFETIME_REDUCTION (reduction of lifetime) */ + uint16_t gtk_request_imin; /* GTK_REQUEST_IMIN (seconds) */ + uint16_t gtk_request_imax; /* GTK_REQUEST_IMAX (seconds) */ + uint16_t gtk_max_mismatch; /* GTK_MAX_MISMATCH (seconds) */ + uint8_t gtk_new_install_req; /* GTK_NEW_INSTALL_REQUIRED (percent of GTK lifetime) */ +} sec_timer_cfg_t; /** * ws_pae_timers_settings_init initializes timer settings structure * * \param timer_settings timer settings + * \param new_timer_settings new timer settings * */ -void ws_pae_timers_settings_init(timer_settings_t *timer_settings); +void ws_pae_timers_settings_init(sec_timer_cfg_t *timer_settings, ws_sec_timer_cfg_t *new_timer_settings); /** * ws_pae_timers_lifetime_set sets GTK, PTK and PTK lifetimes @@ -47,7 +48,7 @@ void ws_pae_timers_settings_init(timer_settings_t *timer_settings); * \param ptk_lifetime PTK lifetime * */ -void ws_pae_timers_lifetime_set(timer_settings_t *timer_settings, uint32_t gtk_lifetime, uint32_t pmk_lifetime, uint32_t ptk_lifetime); +void ws_pae_timers_lifetime_set(sec_timer_cfg_t *timer_settings, uint32_t gtk_lifetime, uint32_t pmk_lifetime, uint32_t ptk_lifetime); /** * ws_pae_timers_gtk_time_settings_set sets GTK, PTK and PTK lifetimes @@ -59,7 +60,7 @@ void ws_pae_timers_lifetime_set(timer_settings_t *timer_settings, uint32_t gtk_l * \param max_mismatch max mismatch * */ -void ws_pae_timers_gtk_time_settings_set(timer_settings_t *timer_settings, uint8_t revocat_lifetime_reduct, uint8_t new_activation_time, uint8_t new_install_req, uint32_t max_mismatch); +void ws_pae_timers_gtk_time_settings_set(sec_timer_cfg_t *timer_settings, uint8_t revocat_lifetime_reduct, uint8_t new_activation_time, uint8_t new_install_req, uint32_t max_mismatch); /** * ws_pae_timers_gtk_new_install_required GTK new install required check @@ -71,7 +72,7 @@ void ws_pae_timers_gtk_time_settings_set(timer_settings_t *timer_settings, uint8 * \return false GTK install not required * */ -bool ws_pae_timers_gtk_new_install_required(timer_settings_t *timer_settings, uint32_t seconds); +bool ws_pae_timers_gtk_new_install_required(sec_timer_cfg_t *timer_settings, uint32_t seconds); /** * ws_pae_timers_gtk_new_activation_time GTK new activation time @@ -83,7 +84,7 @@ bool ws_pae_timers_gtk_new_install_required(timer_settings_t *timer_settings, ui * \return false GTK new activation time not expired * */ -bool ws_pae_timers_gtk_new_activation_time(timer_settings_t *timer_settings, uint32_t seconds); +bool ws_pae_timers_gtk_new_activation_time(sec_timer_cfg_t *timer_settings, uint32_t seconds); /** * ws_pae_timers_gtk_revocation_lifetime_get GTK revocation lifetime get @@ -93,6 +94,6 @@ bool ws_pae_timers_gtk_new_activation_time(timer_settings_t *timer_settings, uin * \return GTK revocation lifetime * */ -uint32_t ws_pae_timers_gtk_revocation_lifetime_get(timer_settings_t *timer_settings); +uint32_t ws_pae_timers_gtk_revocation_lifetime_get(sec_timer_cfg_t *timer_settings); #endif /* WS_PAE_TIMERS_H_ */ diff --git a/source/6LoWPAN/ws/ws_test_api.c b/source/6LoWPAN/ws/ws_test_api.c index 09a749b1bb..f7ea71de08 100644 --- a/source/6LoWPAN/ws/ws_test_api.c +++ b/source/6LoWPAN/ws/ws_test_api.c @@ -21,11 +21,14 @@ #include #include #include +#include "fhss_config.h" +#include "ws_management_api.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" #include "6LoWPAN/ws/ws_common.h" #include "6LoWPAN/ws/ws_bbr_api_internal.h" #include "6LoWPAN/ws/ws_pae_controller.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" #include "randLIB.h" #include "ns_trace.h" @@ -74,24 +77,67 @@ int ws_test_active_key_set(int8_t interface_id, uint8_t index) int ws_test_key_lifetime_set(int8_t interface_id, uint32_t gtk_lifetime, uint32_t pmk_lifetime, uint32_t ptk_lifetime) { - (void) interface_id; - (void) gtk_lifetime; - (void) pmk_lifetime; - (void) ptk_lifetime; + protocol_interface_info_entry_t *cur; - return ws_pae_controller_key_lifetime_update(interface_id, gtk_lifetime, pmk_lifetime, ptk_lifetime); + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (!cur || !ws_info(cur)) { + return -1; + } + + ws_sec_timer_cfg_t cfg; + if (ws_cfg_sec_timer_get(&cfg, NULL) < 0) { + return -2; + } + + if (gtk_lifetime > 0) { + cfg.gtk_expire_offset = gtk_lifetime; + } + if (pmk_lifetime > 0) { + cfg.pmk_lifetime = pmk_lifetime; + } + if (ptk_lifetime > 0) { + cfg.ptk_lifetime = ptk_lifetime; + } + + if (ws_cfg_sec_timer_set(cur, NULL, &cfg, NULL) < 0) { + return -3; + } + + return 0; } int ws_test_gtk_time_settings_set(int8_t interface_id, uint8_t revocat_lifetime_reduct, uint8_t new_activation_time, uint8_t new_install_req, uint32_t max_mismatch) { - (void) interface_id; - (void) revocat_lifetime_reduct; - (void) new_activation_time; - (void) new_install_req; - (void) max_mismatch; + protocol_interface_info_entry_t *cur; + cur = protocol_stack_interface_info_get_by_id(interface_id); + if (!cur || !ws_info(cur)) { + return -1; + } - return ws_pae_controller_gtk_time_settings_update(interface_id, revocat_lifetime_reduct, new_activation_time, new_install_req, max_mismatch); + ws_sec_timer_cfg_t cfg; + if (ws_cfg_sec_timer_get(&cfg, NULL) < 0) { + return -2; + } + + if (revocat_lifetime_reduct > 0) { + cfg.revocat_lifetime_reduct = revocat_lifetime_reduct; + } + if (new_activation_time > 0) { + cfg.gtk_new_act_time = new_activation_time; + } + if (new_install_req > 0) { + cfg.gtk_new_install_req = new_install_req; + } + if (max_mismatch > 0) { + cfg.gtk_max_mismatch = max_mismatch; + } + + if (ws_cfg_sec_timer_set(cur, NULL, &cfg, NULL) < 0) { + return -3; + } + + return 0; } int ws_test_next_gtk_set(int8_t interface_id, uint8_t *gtk[4]) diff --git a/source/BorderRouter/border_router.c b/source/BorderRouter/border_router.c index ec1bcaa0ff..dd12919d02 100644 --- a/source/BorderRouter/border_router.c +++ b/source/BorderRouter/border_router.c @@ -201,7 +201,7 @@ int8_t arm_nwk_6lowpan_border_router_context_update(int8_t interface_id, uint8_t if (cur->border_router_setup->nd_nwk) { nd_router_setup_t *routerSetup = cur->border_router_setup->nd_border_router_configure; - if (!lowpan_contex_get_by_id(&routerSetup->context_list, (c_id_flags & LOWPAN_CONTEXT_CID_MASK))) { + if (!lowpan_context_get_by_id(&routerSetup->context_list, (c_id_flags & LOWPAN_CONTEXT_CID_MASK))) { if (ns_list_count(&routerSetup->context_list) >= ND_MAX_PROXY_CONTEXT_COUNT) { return -1; } @@ -245,7 +245,7 @@ int8_t arm_nwk_6lowpan_border_router_nd_context_load(int8_t interface_id, uint8_ contex_data += 2; //Now Pointer Indicate to prefix //Check first is current ID at list - if (!lowpan_contex_get_by_id(&nd_router_setup->context_list, (c_id & LOWPAN_CONTEXT_CID_MASK))) { + if (!lowpan_context_get_by_id(&nd_router_setup->context_list, (c_id & LOWPAN_CONTEXT_CID_MASK))) { if (ns_list_count(&nd_router_setup->context_list) >= ND_MAX_PROXY_CONTEXT_COUNT) { tr_debug("All Contexts are allocated"); return -1; @@ -305,7 +305,7 @@ int8_t arm_nwk_6lowpan_border_router_context_remove_by_id(int8_t interface_id, u nd_router_configuration = cur_interface->border_router_setup->nd_border_router_configure; - entry = lowpan_contex_get_by_id(&nd_router_configuration->context_list, c_id); + entry = lowpan_context_get_by_id(&nd_router_configuration->context_list, c_id); if (entry) { ns_list_remove(&nd_router_configuration->context_list, entry); ns_dyn_mem_free(entry); @@ -333,7 +333,7 @@ int8_t arm_nwk_6lowpan_border_router_context_parameter_update(int8_t interface_i nd_router_configuration = cur_interface->border_router_setup->nd_border_router_configure; - entry = lowpan_contex_get_by_id(&nd_router_configuration->context_list, c_id); + entry = lowpan_context_get_by_id(&nd_router_configuration->context_list, c_id); if (entry) { uint8_t cid_flag = entry->cid; entry->compression = compress_mode; diff --git a/source/Common_Protocols/icmpv6.c b/source/Common_Protocols/icmpv6.c index f0b3dc59ea..b94b55d52a 100644 --- a/source/Common_Protocols/icmpv6.c +++ b/source/Common_Protocols/icmpv6.c @@ -1377,6 +1377,7 @@ void ack_remove_neighbour_cb(struct buffer *buffer_ptr, uint8_t status) static void icmpv6_aro_cb(buffer_t *buf, uint8_t status) { + (void)status; uint8_t ll_address[16]; if (buf->dst_sa.addr_type == ADDR_IPV6) { /*Full IPv6 address*/ @@ -1387,8 +1388,8 @@ static void icmpv6_aro_cb(buffer_t *buf, uint8_t status) memcpy(ll_address + 8, &buf->dst_sa.address[2], 8); ll_address[8] ^= 2; } - rpl_control_address_register_done(buf->interface, ll_address, status); - if (status != SOCKET_TX_DONE) { + if (rpl_control_address_register_done(buf->interface, ll_address, status)) { + // When RPL returns true neighbor should be blacklisted ws_common_aro_failure(buf->interface, ll_address); } } diff --git a/source/Core/include/ns_error_types.h b/source/Core/include/ns_error_types.h index c1f12cd0b0..31d15d3f32 100644 --- a/source/Core/include/ns_error_types.h +++ b/source/Core/include/ns_error_types.h @@ -22,11 +22,11 @@ * \enum error_t * \brief System generic error. */ -typedef enum error_t { +typedef enum { eOK = 0, /*!< no error */ eFALSE = 1, /*!< no result */ eBUSY = 2, /*!< resource busy */ eSYSTEM /*!< error code readable in sys_error */ -} error_t; +} socket_error_t; #endif /* NS_ERROR_TYPES_H_ */ diff --git a/source/Core/include/ns_socket.h b/source/Core/include/ns_socket.h index 5e1c566e20..941c7403da 100644 --- a/source/Core/include/ns_socket.h +++ b/source/Core/include/ns_socket.h @@ -190,7 +190,7 @@ extern void socket_init(void); extern int8_t socket_event_handler_id_get(void); extern bool socket_data_queued_event_push(socket_t *socket); extern void socket_event_push(uint8_t sock_event, socket_t *socket, int8_t interface_id, void *session_ptr, uint16_t length); -extern error_t socket_create(socket_family_t family, socket_type_t type, uint8_t protocol, int8_t *sid, uint16_t port, void (*passed_fptr)(void *), bool buffer_type); +extern socket_error_t socket_create(socket_family_t family, socket_type_t type, uint8_t protocol, int8_t *sid, uint16_t port, void (*passed_fptr)(void *), bool buffer_type); extern socket_t *socket_new_incoming_connection(socket_t *listen_socket); void socket_connection_abandoned(socket_t *socket, int8_t interface_id, uint8_t reason); void socket_connection_complete(socket_t *socket, int8_t interface_id); @@ -201,8 +201,8 @@ extern void socket_id_detach(int8_t sid); extern buffer_t *socket_buffer_read(socket_t *socket); extern socket_t *socket_lookup(socket_family_t family, uint8_t protocol, const sockaddr_t *local_addr, const sockaddr_t *remote_addr); extern socket_t *socket_lookup_ipv6(uint8_t protocol, const sockaddr_t *local_addr, const sockaddr_t *remote_addr, bool allow_wildcards); -extern error_t socket_port_validate(uint16_t port, uint8_t protocol); -extern error_t socket_up(buffer_t *buf); +extern socket_error_t socket_port_validate(uint16_t port, uint8_t protocol); +extern socket_error_t socket_up(buffer_t *buf); extern bool socket_message_validate_iov(const struct ns_msghdr *msg, uint16_t *length_out); extern int16_t socket_buffer_sendmsg(int8_t sid, buffer_t *buf, const struct ns_msghdr *msg, int flags); extern socket_t *socket_pointer_get(int8_t socket); diff --git a/source/Core/ns_socket.c b/source/Core/ns_socket.c index 05961ccb5b..e0fbffd724 100644 --- a/source/Core/ns_socket.c +++ b/source/Core/ns_socket.c @@ -342,7 +342,7 @@ static void socket_free(socket_t *socket) ns_dyn_mem_free(socket); } -error_t socket_port_validate(uint16_t port, uint8_t protocol) +socket_error_t socket_port_validate(uint16_t port, uint8_t protocol) { ns_list_foreach(socket_t, socket, &socket_list) { if (!socket_is_ipv6(socket)) { @@ -497,7 +497,7 @@ socket_t *socket_dereference(socket_t *socket_ptr) * \return eFALSE no free sockets * \return eBUSY port reserved */ -error_t socket_create(socket_family_t family, socket_type_t type, uint8_t protocol, int8_t *sid, uint16_t port, void (*passed_fptr)(void *), bool buffer_type) +socket_error_t socket_create(socket_family_t family, socket_type_t type, uint8_t protocol, int8_t *sid, uint16_t port, void (*passed_fptr)(void *), bool buffer_type) { if (sid) { *sid = -1; @@ -850,7 +850,7 @@ socket_t *socket_lookup(socket_family_t family, uint8_t protocol, const sockaddr * \return eFALSE no socket found * \return eBUSY socket full */ -error_t socket_up(buffer_t *buf) +socket_error_t socket_up(buffer_t *buf) { socket_t *socket = buf->socket; diff --git a/source/MAC/IEEE802_15_4/mac_defines.h b/source/MAC/IEEE802_15_4/mac_defines.h index acc45a6788..28c2e62cfe 100644 --- a/source/MAC/IEEE802_15_4/mac_defines.h +++ b/source/MAC/IEEE802_15_4/mac_defines.h @@ -225,6 +225,8 @@ typedef struct protocol_interface_rf_mac_setup { uint8_t aUnitBackoffPeriod; uint8_t number_of_csma_ca_periods; /**< Number of CSMA-CA periods */ uint16_t multi_cca_interval; /**< Length of the additional CSMA-CA period(s) in microseconds */ + uint16_t phy_mtu_size; + phy_802_15_4_mode_t current_mac_mode; /* Indirect queue parameters */ struct mac_pre_build_frame *indirect_pd_data_request_queue; struct mac_pre_build_frame enhanced_ack_buffer; diff --git a/source/MAC/IEEE802_15_4/mac_header_helper_functions.c b/source/MAC/IEEE802_15_4/mac_header_helper_functions.c index 5f8273bb6b..65f6e05f6b 100644 --- a/source/MAC/IEEE802_15_4/mac_header_helper_functions.c +++ b/source/MAC/IEEE802_15_4/mac_header_helper_functions.c @@ -32,7 +32,7 @@ static uint8_t *mcps_mac_security_aux_header_start_pointer_get(const mac_pre_par static uint8_t *mac_header_information_elements_write(const mac_pre_build_frame_t *buffer, uint8_t *ptr); -static uint8_t mac_fcf_lenght(const mac_fcf_sequence_t *header) +static uint8_t mac_fcf_length(const mac_fcf_sequence_t *header) { uint8_t length; if (header->frameVersion == MAC_FRAME_VERSION_2015) { @@ -298,7 +298,7 @@ static uint8_t *mac_header_write_fcf_dsn(const mac_fcf_sequence_t *header, uint8 uint16_t mac_header_off_set_to_aux_header(const mac_fcf_sequence_t *fcf) { //Skip first FCF & address field - uint16_t offset = mac_fcf_lenght(fcf);//Skip FCF + DSN + uint16_t offset = mac_fcf_length(fcf);//Skip FCF + DSN offset += mac_dst_address_length_with_panid(fcf); offset += mac_address_length(fcf->SrcAddrMode); if (fcf->SrcPanPresents) { @@ -351,7 +351,7 @@ static bool mac_header_pan_full_compressed(const mac_fcf_sequence_t *header) static uint16_t mac_header_read_src_pan(const mac_fcf_sequence_t *header, const uint8_t *ptr) { - ptr += mac_fcf_lenght(header);//Skip FCF + DSN + ptr += mac_fcf_length(header);//Skip FCF + DSN ptr += mac_dst_address_length_with_panid(header); //Skip Dst panID & Address @@ -360,7 +360,7 @@ static uint16_t mac_header_read_src_pan(const mac_fcf_sequence_t *header, const static uint16_t mac_header_read_dst_pan(const mac_fcf_sequence_t *header, const uint8_t *ptr) { - ptr += mac_fcf_lenght(header);//Skip FCF + DSN + ptr += mac_fcf_length(header);//Skip FCF + DSN return common_read_16_bit_inverse(ptr); } @@ -403,7 +403,7 @@ void mac_header_get_src_address(const mac_fcf_sequence_t *header, const uint8_t return; } - ptr += mac_fcf_lenght(header);//Skip FCF + DSN + ptr += mac_fcf_length(header);//Skip FCF + DSN ptr += mac_dst_address_length_with_panid(header); @@ -430,7 +430,7 @@ void mac_header_get_dst_address(const mac_fcf_sequence_t *header, const uint8_t } uint8_t address_len, address_index, i; - ptr += mac_fcf_lenght(header);//Skip FCF + DSN + ptr += mac_fcf_length(header);//Skip FCF + DSN address_len = mac_address_length(header->DstAddrMode); diff --git a/source/MAC/IEEE802_15_4/mac_mcps_sap.c b/source/MAC/IEEE802_15_4/mac_mcps_sap.c index 6442290a48..d7c9aa9ef8 100644 --- a/source/MAC/IEEE802_15_4/mac_mcps_sap.c +++ b/source/MAC/IEEE802_15_4/mac_mcps_sap.c @@ -228,8 +228,8 @@ void mcps_sap_data_req_handler_ext(protocol_interface_rf_mac_setup_s *rf_mac_set goto verify_status; } - if ((data_req->msduLength + ie_header_length + ie_payload_length) > rf_mac_setup->dev_driver->phy_driver->phy_MTU - MAC_DATA_PACKET_MIN_HEADER_LENGTH) { - tr_debug("packet %u, %u", data_req->msduLength, rf_mac_setup->dev_driver->phy_driver->phy_MTU); + if ((data_req->msduLength + ie_header_length + ie_payload_length) > rf_mac_setup->phy_mtu_size - MAC_DATA_PACKET_MIN_HEADER_LENGTH) { + tr_debug("packet %u, %u", data_req->msduLength, rf_mac_setup->phy_mtu_size); status = MLME_FRAME_TOO_LONG; goto verify_status; } @@ -358,7 +358,7 @@ verify_status: static int8_t mac_virtual_data_req_handler(protocol_interface_rf_mac_setup_s *rf_mac_setup, const uint8_t *data_ptr, uint16_t data_length) { - if (!rf_mac_setup->macUpState || data_length > rf_mac_setup->dev_driver->phy_driver->phy_MTU) { + if (!rf_mac_setup->macUpState || data_length > rf_mac_setup->phy_mtu_size) { return -1; } @@ -1576,7 +1576,7 @@ static int8_t mcps_generic_packet_build(protocol_interface_rf_mac_setup_s *rf_pt uint16_t mac_payload_length = frame_length; if (mac_payload_length > MAC_IEEE_802_15_4_MAX_MAC_SAFE_PAYLOAD_SIZE && - dev_driver->phy_MTU == MAC_IEEE_802_15_4_MAX_PHY_PACKET_SIZE) { + rf_ptr->phy_mtu_size == MAC_IEEE_802_15_4_MAX_PHY_PACKET_SIZE) { /* IEEE 802.15.4-2003 only allowed unsecured payloads up to 102 bytes * (always leaving room for maximum MAC overhead). * IEEE 802.15.4-2006 allows bigger if MAC header is small enough, but @@ -1596,8 +1596,8 @@ static int8_t mcps_generic_packet_build(protocol_interface_rf_mac_setup_s *rf_pt //Add MHR length to total length frame_length += buffer->mac_header_length_with_security + buffer->security_mic_len; - if ((frame_length) > dev_driver->phy_MTU - 2) { - tr_debug("Too Long %u, %u pa %u header %u mic %u", frame_length, mac_payload_length, buffer->mac_header_length_with_security, buffer->security_mic_len, dev_driver->phy_MTU); + if ((frame_length) > rf_ptr->phy_mtu_size - 2) { + tr_debug("Too Long %u, %u pa %u header %u mic %u", frame_length, mac_payload_length, buffer->mac_header_length_with_security, buffer->security_mic_len, rf_ptr->phy_mtu_size); buffer->status = MLME_FRAME_TOO_LONG; //decrement security counter if (key_desc) { @@ -1745,8 +1745,8 @@ int8_t mcps_generic_ack_build(protocol_interface_rf_mac_setup_s *rf_ptr, bool in //Add MHR length to total length frame_length += buffer->mac_header_length_with_security + buffer->security_mic_len; uint16_t ack_mtu_size; - if (ENHANCED_ACK_MAX_LENGTH > dev_driver->phy_MTU) { - ack_mtu_size = dev_driver->phy_MTU; + if (ENHANCED_ACK_MAX_LENGTH > rf_ptr->phy_mtu_size) { + ack_mtu_size = rf_ptr->phy_mtu_size; } else { ack_mtu_size = ENHANCED_ACK_MAX_LENGTH; } diff --git a/source/MAC/IEEE802_15_4/mac_mlme.c b/source/MAC/IEEE802_15_4/mac_mlme.c index b091da2a85..8ea8f3355c 100644 --- a/source/MAC/IEEE802_15_4/mac_mlme.c +++ b/source/MAC/IEEE802_15_4/mac_mlme.c @@ -69,6 +69,7 @@ static void mac_mlme_timer_cb(int8_t timer_id, uint16_t slots); static void mac_mlme_start_confirm_handler(protocol_interface_rf_mac_setup_s *rf_ptr, const mlme_start_conf_t *conf); static void mac_mlme_scan_confirm_handler(protocol_interface_rf_mac_setup_s *rf_ptr, const mlme_scan_conf_t *conf); static int mac_mlme_set_symbol_rate(protocol_interface_rf_mac_setup_s *rf_mac_setup); +static int mac_mlme_allocate_tx_buffers(protocol_interface_rf_mac_setup_s *rf_mac_setup, arm_device_driver_list_s *dev_driver, uint16_t mtu_size); static void mac_mlme_energy_scan_start(protocol_interface_rf_mac_setup_s *rf_mac_setup, uint8_t channel) { @@ -767,6 +768,29 @@ int8_t mac_mlme_set_req(protocol_interface_rf_mac_setup_s *rf_mac_setup, const m memcpy(rf_mac_setup->coord_long_address, set_req->value_pointer, 8); } return 0; + case mac802_15_4Mode: + pu8 = (uint8_t *) set_req->value_pointer; + if (rf_mac_setup->current_mac_mode == *pu8) { + return -1; + } + rf_mac_setup->current_mac_mode = *pu8; + rf_mac_setup->dev_driver->phy_driver->extension(PHY_EXTENSION_SET_802_15_4_MODE, pu8); + uint16_t new_mtu_size = MAC_IEEE_802_15_4_MAX_PHY_PACKET_SIZE; + if (*pu8 == IEEE_802_15_4G_2012) { + new_mtu_size = MAC_IEEE_802_15_4G_MAX_PHY_PACKET_SIZE; + } + mac_api_t *mac_api = get_sw_mac_api(rf_mac_setup); + if (rf_mac_setup->dev_driver->phy_driver->phy_MTU > new_mtu_size) { + mac_api->phyMTU = rf_mac_setup->phy_mtu_size = new_mtu_size; + } else { + mac_api->phyMTU = rf_mac_setup->phy_mtu_size = rf_mac_setup->dev_driver->phy_driver->phy_MTU; + } + if (mac_mlme_allocate_tx_buffers(rf_mac_setup, rf_mac_setup->dev_driver, rf_mac_setup->phy_mtu_size)) { + tr_err("Failed to reallocate TX buffers"); + return -1; + } + tr_debug("Set MAC mode to %s, MTU size: %u", *pu8 == IEEE_802_15_4G_2012 ? "IEEE 802.15.4G-2012" : "IEEE 802.15.4-2011", rf_mac_setup->phy_mtu_size); + return 0; case macTXPower: pu8 = (uint8_t *) set_req->value_pointer; rf_mac_setup->dev_driver->phy_driver->extension(PHY_EXTENSION_SET_TX_POWER, pu8); @@ -1067,9 +1091,29 @@ static int mac_mlme_set_symbol_rate(protocol_interface_rf_mac_setup_s *rf_mac_se return -1; } -protocol_interface_rf_mac_setup_s *mac_mlme_data_base_allocate(uint8_t *mac64, arm_device_driver_list_s *dev_driver, mac_description_storage_size_t *storage_sizes) +static int mac_mlme_allocate_tx_buffers(protocol_interface_rf_mac_setup_s *rf_mac_setup, arm_device_driver_list_s *dev_driver, uint16_t mtu_size) { + ns_dyn_mem_free(rf_mac_setup->dev_driver_tx_buffer.buf); + ns_dyn_mem_free(rf_mac_setup->mac_beacon_payload); uint16_t total_length = 0; + //Allocate tx buffer by given MTU + header + tail + total_length = mtu_size; + total_length += (dev_driver->phy_driver->phy_header_length + dev_driver->phy_driver->phy_tail_length); + rf_mac_setup->dev_driver_tx_buffer.buf = ns_dyn_mem_alloc(total_length); + if (!rf_mac_setup->dev_driver_tx_buffer.buf) { + return -1; + } + //allocate Beacon Payload buffer + rf_mac_setup->max_beacon_payload_length = mtu_size - MAC_IEEE_802_15_4_MAX_BEACON_OVERHEAD; + rf_mac_setup->mac_beacon_payload = ns_dyn_mem_alloc(rf_mac_setup->max_beacon_payload_length); + if (!rf_mac_setup->mac_beacon_payload) { + return -1; + } + return 0; +} + +protocol_interface_rf_mac_setup_s *mac_mlme_data_base_allocate(uint8_t *mac64, arm_device_driver_list_s *dev_driver, mac_description_storage_size_t *storage_sizes, uint16_t mtu_size) +{ //allocate security if (!dev_driver || !mac64 || !dev_driver->phy_driver || !storage_sizes) { return NULL; @@ -1102,20 +1146,9 @@ protocol_interface_rf_mac_setup_s *mac_mlme_data_base_allocate(uint8_t *mac64, a mac_mlme_data_base_deallocate(entry); return NULL; } + entry->phy_mtu_size = mtu_size; - //Allocate tx buffer by given MTU + header + tail - total_length = dev_driver->phy_driver->phy_MTU; - total_length += (dev_driver->phy_driver->phy_header_length + dev_driver->phy_driver->phy_tail_length); - entry->dev_driver_tx_buffer.buf = ns_dyn_mem_alloc(total_length); - if (!entry->dev_driver_tx_buffer.buf) { - mac_mlme_data_base_deallocate(entry); - return NULL; - } - - //allocate Beacon Payload buffer - entry->max_beacon_payload_length = dev_driver->phy_driver->phy_MTU - MAC_IEEE_802_15_4_MAX_BEACON_OVERHEAD; - entry->mac_beacon_payload = ns_dyn_mem_alloc(entry->max_beacon_payload_length); - if (!entry->mac_beacon_payload) { + if (mac_mlme_allocate_tx_buffers(entry, dev_driver, mtu_size)) { mac_mlme_data_base_deallocate(entry); return NULL; } diff --git a/source/MAC/IEEE802_15_4/mac_mlme.h b/source/MAC/IEEE802_15_4/mac_mlme.h index fb251c8000..2cf6a79a70 100644 --- a/source/MAC/IEEE802_15_4/mac_mlme.h +++ b/source/MAC/IEEE802_15_4/mac_mlme.h @@ -106,7 +106,7 @@ void mac_mlme_event_cb(void *mac_ptr); void mac_mlme_set_active_state(struct protocol_interface_rf_mac_setup *entry, bool new_state); -struct protocol_interface_rf_mac_setup *mac_mlme_data_base_allocate(uint8_t *mac64, struct arm_device_driver_list *dev_driver, struct mac_description_storage_size_s *storage_sizes); +struct protocol_interface_rf_mac_setup *mac_mlme_data_base_allocate(uint8_t *mac64, struct arm_device_driver_list *dev_driver, struct mac_description_storage_size_s *storage_sizes, uint16_t mtu_size); void mac_mlme_data_base_deallocate(struct protocol_interface_rf_mac_setup *rf_mac); uint8_t mac_mlme_set_new_sqn(struct protocol_interface_rf_mac_setup *rf_setup); diff --git a/source/MAC/IEEE802_15_4/mac_pd_sap.c b/source/MAC/IEEE802_15_4/mac_pd_sap.c index 1b8eda1229..09952b9b10 100644 --- a/source/MAC/IEEE802_15_4/mac_pd_sap.c +++ b/source/MAC/IEEE802_15_4/mac_pd_sap.c @@ -111,7 +111,7 @@ uint32_t mac_csma_backoff_get(protocol_interface_rf_mac_setup_s *rf_mac_setup) backoff_in_us += ((rf_mac_setup->multi_cca_interval * (rf_mac_setup->number_of_csma_ca_periods - 1)) - backoff_in_us); } if (rf_mac_setup->mac_tx_retry) { - backoff_in_us += rf_mac_setup->fhss_api->get_retry_period(rf_mac_setup->fhss_api, rf_mac_setup->active_pd_data_request->DstAddr, rf_mac_setup->dev_driver->phy_driver->phy_MTU); + backoff_in_us += rf_mac_setup->fhss_api->get_retry_period(rf_mac_setup->fhss_api, rf_mac_setup->active_pd_data_request->DstAddr, rf_mac_setup->phy_mtu_size); } } return backoff_in_us; diff --git a/source/MAC/IEEE802_15_4/mac_security_mib.c b/source/MAC/IEEE802_15_4/mac_security_mib.c index 27de7e89cb..abe65d668b 100644 --- a/source/MAC/IEEE802_15_4/mac_security_mib.c +++ b/source/MAC/IEEE802_15_4/mac_security_mib.c @@ -90,7 +90,7 @@ static int mac_sec_mib_frame_counter_key_buffer_allocate(protocol_interface_rf_m mlme_key_descriptor_t *key_descriptor_list = rf_mac_setup->key_description_table; uint32_t *frame_counter_pointer = rf_mac_setup->key_device_frame_counter_list_buffer; for (uint8_t i = 0; i < rf_mac_setup->key_description_table_size; i++) { - key_descriptor_list->KeyDeviceFrameCouterList = frame_counter_pointer; + key_descriptor_list->KeyDeviceFrameCounterList = frame_counter_pointer; key_descriptor_list->KeyFrameCounterPerKey = true; key_descriptor_list->KeyFrameCounter = 0; //Update Pointers @@ -105,7 +105,7 @@ static void mac_sec_mib_frame_counter_key_buffer_free(protocol_interface_rf_mac_ { mlme_key_descriptor_t *key_descriptor_list = rf_mac_setup->key_description_table; for (uint8_t i = 0; i < rf_mac_setup->key_description_table_size; i++) { - key_descriptor_list->KeyDeviceFrameCouterList = NULL; + key_descriptor_list->KeyDeviceFrameCounterList = NULL; key_descriptor_list->KeyFrameCounterPerKey = false; //Update Pointers key_descriptor_list++; @@ -368,7 +368,7 @@ int8_t mac_sec_mib_key_description_set(uint8_t atribute_index, mlme_key_descript key_ptr->KeyFrameCounter = 0; if (key_ptr->KeyDeviceListEntries == 0) { //Clear all frame counters from old possible user's - uint32_t *counter_ptr = key_ptr->KeyDeviceFrameCouterList; + uint32_t *counter_ptr = key_ptr->KeyDeviceFrameCounterList; for (int i = 0; i < rf_mac_setup->device_description_table_size; i++) { *counter_ptr++ = 0; } @@ -613,7 +613,7 @@ void mac_sec_mib_key_outgoing_frame_counter_decrement(struct protocol_interface_ void mac_sec_mib_key_device_frame_counter_set(mlme_key_descriptor_t *key_descpription_table, mlme_device_descriptor_t *device_info, uint32_t frame_counter, uint8_t attribute_index) { if (key_descpription_table->KeyFrameCounterPerKey) { - uint32_t *counter_ptr = key_descpription_table->KeyDeviceFrameCouterList + attribute_index; + uint32_t *counter_ptr = key_descpription_table->KeyDeviceFrameCounterList + attribute_index; *counter_ptr = frame_counter; } else { device_info->FrameCounter = frame_counter; @@ -623,7 +623,7 @@ void mac_sec_mib_key_device_frame_counter_set(mlme_key_descriptor_t *key_descpri uint32_t mac_mib_key_device_frame_counter_get(mlme_key_descriptor_t *key_descpription_table, mlme_device_descriptor_t *device_info, uint8_t attribute_index) { if (key_descpription_table->KeyFrameCounterPerKey) { - uint32_t *counter_ptr = key_descpription_table->KeyDeviceFrameCouterList + attribute_index; + uint32_t *counter_ptr = key_descpription_table->KeyDeviceFrameCounterList + attribute_index; return *counter_ptr; } return device_info->FrameCounter; diff --git a/source/MAC/IEEE802_15_4/mac_security_mib.h b/source/MAC/IEEE802_15_4/mac_security_mib.h index 86648e7f5c..150d8ea64a 100644 --- a/source/MAC/IEEE802_15_4/mac_security_mib.h +++ b/source/MAC/IEEE802_15_4/mac_security_mib.h @@ -27,7 +27,7 @@ typedef struct mlme_key_descriptor_s { mlme_key_id_lookup_descriptor_t *KeyIdLookupList; mlme_key_device_descriptor_t *KeyDeviceList; mlme_key_usage_descriptor_t *KeyUsageList; - uint32_t *KeyDeviceFrameCouterList; + uint32_t *KeyDeviceFrameCounterList; uint32_t KeyFrameCounter; uint8_t Key[16]; uint8_t KeyDeviceListSize; diff --git a/source/MAC/IEEE802_15_4/sw_mac.c b/source/MAC/IEEE802_15_4/sw_mac.c index a5b679eb28..67e5884227 100644 --- a/source/MAC/IEEE802_15_4/sw_mac.c +++ b/source/MAC/IEEE802_15_4/sw_mac.c @@ -31,6 +31,9 @@ #include "mac_fhss_callbacks.h" #include "eventOS_callback_timer.h" #include "common_functions.h" +#include "ns_trace.h" + +#define TRACE_GROUP "swm" //TODO: create linked list of created MACs @@ -96,13 +99,28 @@ mac_api_t *ns_sw_mac_create(int8_t rf_driver_id, mac_description_storage_size_t memset(this, 0, sizeof(mac_api_t)); this->parent_id = -1; mac_store.dev_driver = driver; - mac_store.setup = mac_mlme_data_base_allocate(mac_store.dev_driver->phy_driver->PHY_MAC, mac_store.dev_driver, storage_sizes); + + // Set default MTU size to 127 unless it is too much for PHY driver + if (driver->phy_driver->phy_MTU > MAC_IEEE_802_15_4_MAX_PHY_PACKET_SIZE) { + this->phyMTU = MAC_IEEE_802_15_4_MAX_PHY_PACKET_SIZE; + } else { + this->phyMTU = driver->phy_driver->phy_MTU; + } + + mac_store.setup = mac_mlme_data_base_allocate(mac_store.dev_driver->phy_driver->PHY_MAC, mac_store.dev_driver, storage_sizes, this->phyMTU); if (!mac_store.setup) { ns_dyn_mem_free(this); return NULL; } + // Set MAC mode to PHY driver + mac_store.setup->current_mac_mode = IEEE_802_15_4_2011; + if (mac_store.setup->dev_driver->phy_driver->extension) { + mac_store.setup->dev_driver->phy_driver->extension(PHY_EXTENSION_SET_802_15_4_MODE, (uint8_t *) &mac_store.setup->current_mac_mode); + } + tr_debug("Set MAC mode to %s, MTU size: %u", "IEEE 802.15.4-2011", mac_store.setup->phy_mtu_size); + arm_net_phy_init(driver->phy_driver, &sw_mac_net_phy_rx, &sw_mac_net_phy_tx_done); arm_net_virtual_config_rx_cb_set(driver->phy_driver, &sw_mac_net_phy_config_parser); arm_net_virtual_confirmation_rx_cb_set(driver->phy_driver, &mac_mlme_virtual_confirmation_handle); @@ -116,10 +134,8 @@ mac_api_t *ns_sw_mac_create(int8_t rf_driver_id, mac_description_storage_size_t this->mac64_get = &macext_mac64_address_get; this->mac64_set = &macext_mac64_address_set; this->mac_storage_sizes_get = &sw_mac_storage_decription_sizes_get; - this->phyMTU = driver->phy_driver->phy_MTU; mac_store.mac_api = this; - mac_store.virtual_driver = NULL; return this; } @@ -279,8 +295,8 @@ static int8_t ns_sw_mac_api_enable_mcps_ext(mac_api_t *api, mcps_data_indication ns_dyn_mem_free(mac_store.setup->dev_driver_tx_buffer.enhanced_ack_buf); uint16_t total_length; - if (ENHANCED_ACK_MAX_LENGTH > dev_driver->phy_driver->phy_MTU) { - total_length = dev_driver->phy_driver->phy_MTU; + if (ENHANCED_ACK_MAX_LENGTH > mac_store.setup->phy_mtu_size) { + total_length = mac_store.setup->phy_mtu_size; } else { total_length = ENHANCED_ACK_MAX_LENGTH; } diff --git a/source/NWK_INTERFACE/Include/protocol.h b/source/NWK_INTERFACE/Include/protocol.h index 6173d0a36a..2a1b3fbbf9 100644 --- a/source/NWK_INTERFACE/Include/protocol.h +++ b/source/NWK_INTERFACE/Include/protocol.h @@ -375,6 +375,7 @@ struct protocol_interface_info_entry { trickle_params_t mpl_control_trickle_params; uint16_t mpl_seed_set_entry_lifetime; uint8_t mpl_seed_id[16]; + struct mpl_domain *mpl_domain; #endif if_6lowpan_dad_entry_t if_6lowpan_dad_process; lowpan_context_list_t lowpan_contexts; diff --git a/source/RPL/rpl_control.c b/source/RPL/rpl_control.c index b17dce381e..d555eb8124 100644 --- a/source/RPL/rpl_control.c +++ b/source/RPL/rpl_control.c @@ -181,11 +181,19 @@ void rpl_control_set_dio_multicast_min_config_advertisment_count(uint8_t min_cou rpl_policy_set_dio_multicast_config_advertisment_min_count(min_count); } +void rpl_control_set_address_registration_timeout(uint16_t timeout_in_minutes) +{ + rpl_policy_set_address_registration_timeout(timeout_in_minutes); +} + void rpl_control_set_dao_retry_count(uint8_t count) { rpl_policy_set_dao_retry_count(count); } - +void rpl_control_set_minimum_dao_target_refresh(uint16_t seconds) +{ + rpl_policy_set_minimum_dao_target_refresh(seconds); +} void rpl_control_set_initial_dao_ack_wait(uint16_t timeout_in_ms) { rpl_policy_set_initial_dao_ack_wait(timeout_in_ms); @@ -198,6 +206,9 @@ void rpl_control_set_mrhof_parent_set_size(uint16_t parent_set_size) /* Send address registration to either specified address, or to non-registered address */ void rpl_control_register_address(protocol_interface_info_entry_t *interface, const uint8_t addr[16]) { + if (!interface->rpl_domain) { + return; + } if (!rpl_policy_parent_confirmation_requested()) { return; } @@ -206,21 +217,23 @@ void rpl_control_register_address(protocol_interface_info_entry_t *interface, co } } -void rpl_control_address_register_done(protocol_interface_info_entry_t *interface, const uint8_t ll_addr[16], uint8_t status) +bool rpl_control_address_register_done(protocol_interface_info_entry_t *interface, const uint8_t ll_addr[16], uint8_t status) { + bool blacklist_neighbour = false; if (!interface->rpl_domain) { - return; + return false; } if (!rpl_policy_parent_confirmation_requested()) { - return; + return false; } ns_list_foreach(struct rpl_instance, instance, &interface->rpl_domain->instances) { rpl_neighbour_t *neighbour = rpl_lookup_neighbour_by_ll_address(instance, ll_addr, interface->id); if (neighbour) { - rpl_instance_address_registration_done(interface, instance, neighbour, status); + blacklist_neighbour = blacklist_neighbour || rpl_instance_address_registration_done(interface, instance, neighbour, status); } } + return blacklist_neighbour; } bool rpl_control_is_dodag_parent(protocol_interface_info_entry_t *interface, const uint8_t ll_addr[16]) @@ -673,6 +686,14 @@ void rpl_control_force_leaf(rpl_domain_t *domain, bool leaf) } } } + +void rpl_control_dao_timeout(rpl_domain_t *domain, uint16_t seconds) +{ + ns_list_foreach(rpl_instance_t, instance, &domain->instances) { + rpl_instance_dao_timeout(instance, seconds); + } +} + void rpl_control_process_routes(rpl_domain_t *domain, bool process_routes) { domain->process_routes = process_routes; diff --git a/source/RPL/rpl_control.h b/source/RPL/rpl_control.h index 464e5c2a83..613d47eb05 100644 --- a/source/RPL/rpl_control.h +++ b/source/RPL/rpl_control.h @@ -145,6 +145,9 @@ void rpl_control_process_routes(rpl_domain_t *domain, bool process_routes); /* Manually send poison on all existing instances a few times */ void rpl_control_poison(rpl_domain_t *domain, uint8_t poison_count); +/* force DAO to verify connections before given time*/ +void rpl_control_dao_timeout(rpl_domain_t *domain, uint16_t seconds); + /* APIs to create domains and map them to interfaces */ rpl_domain_t *rpl_control_create_domain(void); void rpl_control_delete_domain(rpl_domain_t *domain); @@ -170,11 +173,13 @@ bool rpl_control_find_worst_neighbor(struct protocol_interface_info_entry *inter /* Parent link confirmation API extension */ void rpl_control_request_parent_link_confirmation(bool requested); void rpl_control_set_dio_multicast_min_config_advertisment_count(uint8_t min_count); +void rpl_control_set_address_registration_timeout(uint16_t timeout_in_minutes); void rpl_control_set_dao_retry_count(uint8_t count); +void rpl_control_set_minimum_dao_target_refresh(uint16_t seconds); void rpl_control_set_initial_dao_ack_wait(uint16_t timeout_in_ms); void rpl_control_set_mrhof_parent_set_size(uint16_t parent_set_size); void rpl_control_register_address(struct protocol_interface_info_entry *interface, const uint8_t addr[16]); -void rpl_control_address_register_done(struct protocol_interface_info_entry *interface, const uint8_t ll_addr[16], uint8_t status); +bool rpl_control_address_register_done(struct protocol_interface_info_entry *interface, const uint8_t ll_addr[16], uint8_t status); /* Configure and return the routing lookup predicate for a specified RPL instance ID */ ipv6_route_predicate_fn_t *rpl_control_get_route_predicate(rpl_domain_t *domain, uint8_t instance_id, const uint8_t src[16], const uint8_t dst[16]); @@ -198,10 +203,9 @@ uint8_t rpl_policy_mrhof_parent_set_size_get(const rpl_domain_t *domain); #define rpl_control_remove_domain_from_interface(cur) ((void) 0) #define rpl_control_free_domain_instances_from_interface(cur) ((void) 0) #define rpl_control_register_address(interface, addr) ((void) 0) -#define rpl_control_address_register_done(interface, ll_addr, status) ((void) 0) +#define rpl_control_address_register_done(interface, ll_addr, status) (false) #define rpl_policy_mrhof_parent_set_size_get(domain) (0) #define rpl_control_set_mrhof_parent_set_size(parent_set_size) - #endif /* HAVE_RPL */ #endif /* RPL_CONTROL_H_ */ diff --git a/source/RPL/rpl_downward.c b/source/RPL/rpl_downward.c index 6f7a5dbfcb..34ca3cf6b7 100644 --- a/source/RPL/rpl_downward.c +++ b/source/RPL/rpl_downward.c @@ -109,8 +109,6 @@ static void rpl_downward_topo_sort_invalidate(rpl_instance_t *instance); #define DEFAULT_DAO_DELAY 10 /* *100ms ticks = 1s */ -//#define MINIMUM_DAO_TARGET_REFRESH (5*60) /* seconds */ - /* Bit of the PC mask */ #define PCBIT(n) (UINT8_C(0x80) >> (n)) @@ -184,7 +182,7 @@ static bool rpl_instance_parent_selection_ready(rpl_instance_t *instance) { rpl_neighbour_t *neighbour = ns_list_get_first(&instance->candidate_neighbours); if (neighbour && neighbour->dodag_parent && neighbour->dao_path_control) { - //We have a Primary parent with Dao patha control + //We have a Primary parent with Dao path control return true; } return false; @@ -1603,11 +1601,10 @@ void rpl_instance_dao_acked(rpl_instance_t *instance, const uint8_t src[16], int } else { t = 0xFFFFFFFF; } -#ifdef MINIMUM_DAO_TARGET_REFRESH - if (t > MINIMUM_DAO_TARGET_REFRESH) { - t = randLIB_randomise_base(MINIMUM_DAO_TARGET_REFRESH, 0x7333, 0x8CCD); /* +/- 10% */ + if (rpl_policy_minimum_dao_target_refresh() && t > rpl_policy_minimum_dao_target_refresh()) { + // set the minimum target refresh time ranging from 25% to 10% below the value + t = randLIB_randomise_base(rpl_policy_minimum_dao_target_refresh(), 0x6000, 0x7333); } -#endif target->info.non_root.refresh_timer = t; tr_debug("set rfr to %"PRIu32, t); } @@ -1639,6 +1636,21 @@ void rpl_instance_dao_request(struct rpl_instance *instance, struct rpl_neighbou rpl_instance_dao_trigger(instance, 0); } +void rpl_instance_dao_timeout(struct rpl_instance *instance, uint16_t seconds) +{ + // Forces DAO timeout to happen before given time distributed in given time + ns_list_foreach(rpl_dao_target_t, target, &instance->dao_targets) { + if (!target->published || target->info.non_root.refresh_timer == 0) { + continue; + } + if (target->info.non_root.refresh_timer < seconds) { + continue; + } + // Shorten the timeout + target->info.non_root.refresh_timer = randLIB_get_random_in_range(1, seconds); + } +} + void rpl_downward_dao_slow_timer(rpl_instance_t *instance, uint16_t seconds) { @@ -1771,8 +1783,11 @@ static bool rpl_instance_push_address_registration(protocol_interface_info_entry aro.status = ARO_SUCCESS; aro.present = true; - aro.lifetime = (addr->valid_lifetime / 60) + 1; memcpy(aro.eui64, interface->mac, 8); + aro.lifetime = rpl_policy_address_registration_timeout(); + if (!aro.lifetime) { + aro.lifetime = (addr->valid_lifetime / 60) + 1; + } buffer_t *buf = icmpv6_build_ns(interface, neighbour->ll_address, addr->address, true, false, &aro); if (!buf) { @@ -1807,6 +1822,13 @@ static void rpl_instance_address_registration_cancel(rpl_instance_t *instance) instance->dao_retry_timer = 0; } +static void rpl_instance_address_registration_retry(rpl_dao_target_t *dao_target) +{ + dao_target->active_confirmation_state = true; // Active timer is set true so the response_wait_time runs out + dao_target->trig_confirmation_state = true; + dao_target->response_wait_time = 20; // Wait 20 seconds before retry +} + void rpl_instance_parent_address_reg_timer_update(rpl_instance_t *instance, uint16_t seconds) { if (!instance->pending_neighbour_confirmation) { @@ -1861,7 +1883,6 @@ void rpl_instance_parent_address_reg_timer_update(rpl_instance_t *instance, uint return; } - if (rpl_instance_push_address_registration(interface, neighbour, address)) { instance->wait_response = neighbour; dao_target->response_wait_time = 5; @@ -1869,33 +1890,41 @@ void rpl_instance_parent_address_reg_timer_update(rpl_instance_t *instance, uint } -void rpl_instance_address_registration_done(protocol_interface_info_entry_t *interface, rpl_instance_t *instance, rpl_neighbour_t *neighbour, uint8_t status) +bool rpl_instance_address_registration_done(protocol_interface_info_entry_t *interface, rpl_instance_t *instance, rpl_neighbour_t *neighbour, uint8_t status) { - if (!instance->pending_neighbour_confirmation) { - return; + return false; } rpl_dao_target_t *dao_target = rpl_instance_get_active_target_confirmation(instance); if (!dao_target || instance->wait_response != neighbour) { - return; + return false; } tr_debug("Address %s register to %s", trace_ipv6(dao_target->prefix), trace_ipv6(neighbour->ll_address)); - if (status == SOCKET_TX_DONE) { - /* State_timer is 1/10 s. Set renewal to 75-85% of lifetime */ - if_address_entry_t *address = rpl_interface_addr_get(interface, dao_target->prefix); - if (address && address->source != ADDR_SOURCE_DHCP) { - address->state_timer = (address->preferred_lifetime * randLIB_get_random_in_range(75, 85) / 10); + if (status != SOCKET_TX_DONE) { + if (neighbour->addr_reg_failures > 0) { + // Neighbor should be blacklisted after this. + tr_error("Address registration failed delete neighbor"); + rpl_instance_address_registration_cancel(instance); + rpl_delete_neighbour(instance, neighbour); + return true; } - neighbour->confirmed = true; - dao_target->response_wait_time = 6; - } else { - tr_error("Address registration failed"); - rpl_delete_neighbour(instance, neighbour); - rpl_instance_address_registration_cancel(instance); + tr_warn("Address registration ACK fail retry selection"); + neighbour->addr_reg_failures++; + rpl_instance_address_registration_retry(dao_target); + return false; } + /* State_timer is 1/10 s. Set renewal to 75-85% of lifetime */ + if_address_entry_t *address = rpl_interface_addr_get(interface, dao_target->prefix); + if (address && address->source != ADDR_SOURCE_DHCP) { + address->state_timer = (address->preferred_lifetime * randLIB_get_random_in_range(75, 85) / 10); + } + neighbour->addr_reg_failures = 0; + neighbour->confirmed = true; + dao_target->response_wait_time = 6; + return false; } #endif /* HAVE_RPL */ diff --git a/source/RPL/rpl_downward.h b/source/RPL/rpl_downward.h index a8c66a79b7..b2b8faa5c8 100644 --- a/source/RPL/rpl_downward.h +++ b/source/RPL/rpl_downward.h @@ -38,11 +38,12 @@ void rpl_instance_delete_published_dao_target(struct rpl_instance *instance, con struct rpl_dao_target *rpl_instance_match_dao_target(struct rpl_instance *instance, const uint8_t *prefix, uint8_t prefix_len); void rpl_instance_dao_request(struct rpl_instance *instance, struct rpl_neighbour *neighbour); +void rpl_instance_dao_timeout(struct rpl_instance *instance, uint16_t seconds); void rpl_instance_dao_trigger(struct rpl_instance *instance, uint16_t delay); void rpl_instance_dao_acked(struct rpl_instance *instance, const uint8_t src[16], int8_t interface_id, uint8_t dao_sequence, uint8_t status); void rpl_instance_parent_address_reg_timer_update(struct rpl_instance *instance, uint16_t seconds); void rpl_instance_send_address_registration(rpl_instance_t *instance, const uint8_t addr[16]); -void rpl_instance_address_registration_done(protocol_interface_info_entry_t *interface, rpl_instance_t *instance, rpl_neighbour_t *neighbour, uint8_t status); +bool rpl_instance_address_registration_done(protocol_interface_info_entry_t *interface, rpl_instance_t *instance, rpl_neighbour_t *neighbour, uint8_t status); struct rpl_dao_target *rpl_instance_get_active_target_confirmation(struct rpl_instance *instance); #ifdef HAVE_RPL_DAO_HANDLING diff --git a/source/RPL/rpl_policy.c b/source/RPL/rpl_policy.c index f8b25d86f1..5e6b7258d4 100644 --- a/source/RPL/rpl_policy.c +++ b/source/RPL/rpl_policy.c @@ -21,7 +21,7 @@ #include "ns_types.h" #include "ns_trace.h" - +#include "randLIB.h" #include "net_interface.h" #include "Core/include/ns_address_internal.h" @@ -34,12 +34,19 @@ #define TRACE_GROUP "RPLy" +typedef enum { + RPL_POLICY_FORWARD, + RPL_POLICY_DROP +} rpl_forward_policy_t; + static bool rpl_policy_parent_confirmation_req = false; static int8_t rpl_policy_dao_retry_count_conf = 0; static int16_t rpl_policy_dao_initial_timeout_conf = 20; // Default is 2 seconds 100ms ticks static uint16_t rpl_policy_dio_validity_period_hysteresis = 0x0180; //Fixed Point 1.5 static uint8_t rpl_policy_multicast_config_min_advertisment_count = 0; static uint8_t rpl_policy_mrhof_parent_set_size_conf = 3; // default parent set size +static uint16_t rpl_policy_minimum_dao_target_refresh_conf = 0; // by default follow the configuration +static uint16_t rpl_policy_address_registration_timeout_value = 0; // Address registration timeouts in minutes 0 use address lifetime /* TODO - application API to control when to join new instances / DODAGs * @@ -115,6 +122,16 @@ void rpl_policy_set_initial_dao_ack_wait(uint16_t timeout_in_ms) rpl_policy_dao_initial_timeout_conf = timeout_in_ms; } +void rpl_policy_set_minimum_dao_target_refresh(uint16_t seconds) +{ + rpl_policy_minimum_dao_target_refresh_conf = seconds; +} + +uint16_t rpl_policy_minimum_dao_target_refresh(void) +{ + return rpl_policy_minimum_dao_target_refresh_conf; +} + uint16_t rpl_policy_initial_dao_ack_wait(const rpl_domain_t *domain, uint8_t mop) { (void)mop; @@ -144,6 +161,46 @@ int8_t rpl_policy_dao_retry_count() return rpl_policy_dao_retry_count_conf; } +//Default Optimistic value is ETX < 2.5 +static uint16_t rpl_policy_etx_full_forward = 0x280; +//Total Drop limit default is 8.0 etx +static uint16_t rpl_policy_etx_full_drop = 0x800; + +//Scale 100 % to bigger are to get more random resolution +#define MAX_DROP_COMPARE (100 * 256) + +int rpl_policy_forward_link_etx_threshold_set(uint16_t etx_full_forward, uint16_t etx_full_drop) +{ + if (etx_full_forward > etx_full_drop) { + return -1; + } + + rpl_policy_etx_full_forward = etx_full_forward; + rpl_policy_etx_full_drop = etx_full_drop; + + return 0; +} + +static rpl_forward_policy_t rpl_policy_link_forward_policy(uint16_t link_etx) +{ + if (link_etx >= rpl_policy_etx_full_drop) { + return RPL_POLICY_DROP; + } + + if (link_etx <= rpl_policy_etx_full_forward) { + return RPL_POLICY_FORWARD; + } + + // The multiplication could overflow 16-bit, even though the final result will be 16-bit + uint16_t drop_prob = (uint32_t) MAX_DROP_COMPARE * (link_etx - rpl_policy_etx_full_forward) / (rpl_policy_etx_full_drop - rpl_policy_etx_full_forward); + + if (randLIB_get_random_in_range(0, 25599) < drop_prob) { + return RPL_POLICY_DROP; + } + + return RPL_POLICY_FORWARD; +} + /* Given the next-hop address from a source routing header, which interface, * if any, should we assume that next hop is on? */ @@ -162,7 +219,9 @@ int8_t rpl_policy_srh_next_hop_interface(rpl_domain_t *domain, int8_t if_id, con } uint16_t etx = ipv6_map_ip_to_ll_and_call_ll_addr_handler(NULL, if_id, n, next_hop, etx_read); - if (etx > ETX_SRH_THRESHOLD) { + + //Validate Link ETX and play poker game if ETX is over optimistic value + if (rpl_policy_link_forward_policy(etx) == RPL_POLICY_DROP) { tr_warn("Rejecting SRH to %s: etx = %x", trace_ipv6(next_hop), etx); goto reject; } @@ -381,6 +440,16 @@ void rpl_policy_set_dio_multicast_config_advertisment_min_count(uint8_t min_coun rpl_policy_multicast_config_min_advertisment_count = min_count; } +uint16_t rpl_policy_address_registration_timeout() +{ + return rpl_policy_address_registration_timeout_value; +} + +void rpl_policy_set_address_registration_timeout(uint16_t timeout_in_minutes) +{ + rpl_policy_address_registration_timeout_value = timeout_in_minutes; +} + #ifdef RPL_STRUCTURES_H_ #error "rpl_structures.h should not be included by rpl_policy.c" diff --git a/source/RPL/rpl_policy.h b/source/RPL/rpl_policy.h index 13e25c492c..ac9ca67a1f 100644 --- a/source/RPL/rpl_policy.h +++ b/source/RPL/rpl_policy.h @@ -29,9 +29,14 @@ bool rpl_policy_request_dao_acks(const rpl_domain_t *domain, uint8_t mop); uint16_t rpl_policy_initial_dao_ack_wait(const rpl_domain_t *domain, uint8_t mop); void rpl_policy_set_initial_dao_ack_wait(uint16_t timeout_in_ms); +void rpl_policy_set_minimum_dao_target_refresh(uint16_t seconds); +uint16_t rpl_policy_minimum_dao_target_refresh(void); + void rpl_policy_set_dao_retry_count(uint8_t count); int8_t rpl_policy_dao_retry_count(); +int rpl_policy_forward_link_etx_threshold_set(uint16_t etx_full_forward, uint16_t etx_full_drop); + int8_t rpl_policy_srh_next_hop_interface(rpl_domain_t *domain, int8_t if_id, const uint8_t *next_hop); uint16_t rpl_policy_modify_downward_cost_to_root_neighbour(rpl_domain_t *domain, int8_t if_id, const uint8_t *next_hop, uint16_t cost); @@ -68,5 +73,7 @@ bool rpl_policy_parent_confirmation_requested(void); void rpl_policy_set_parent_confirmation_request(bool confirmation_requested); uint8_t rpl_policy_dio_multicast_config_advertisment_min_count(void); void rpl_policy_set_dio_multicast_config_advertisment_min_count(uint8_t min_count); +uint16_t rpl_policy_address_registration_timeout(); +void rpl_policy_set_address_registration_timeout(uint16_t timeout_in_minutes); #endif /* RPL_POLICY_H_ */ diff --git a/source/RPL/rpl_structures.h b/source/RPL/rpl_structures.h index aadbc60c28..56463cb5ee 100644 --- a/source/RPL/rpl_structures.h +++ b/source/RPL/rpl_structures.h @@ -52,6 +52,7 @@ struct rpl_neighbour { unsigned dodag_pref: 4; // Preference indication for DODAG parents (0=best) uint8_t dao_path_control; // Path control bit assignments for DAO parent uint8_t old_dao_path_control; + uint8_t addr_reg_failures; // Address registration failure count (missing ACK) int8_t interface_id; uint8_t g_mop_prf; uint8_t dtsn; diff --git a/source/RPL/rpl_upward.c b/source/RPL/rpl_upward.c index 99377e6150..7ee3a56520 100644 --- a/source/RPL/rpl_upward.c +++ b/source/RPL/rpl_upward.c @@ -444,6 +444,7 @@ rpl_neighbour_t *rpl_create_neighbour(rpl_dodag_version_t *version, const uint8_ neighbour->dtsn = dtsn; neighbour->dao_path_control = 0; neighbour->confirmed = 0; + neighbour->addr_reg_failures = 0; /* Need to limit number of neighbours here - chucking worst neighbour */ diff --git a/source/Security/kmp/kmp_api.c b/source/Security/kmp/kmp_api.c index a95802ec4d..345e9ba9fc 100644 --- a/source/Security/kmp/kmp_api.c +++ b/source/Security/kmp/kmp_api.c @@ -25,6 +25,7 @@ #include "Common_Protocols/ipv6_constants.h" #include "socket_api.h" #include "6LoWPAN/ws/ws_config.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/kmp/kmp_socket_if.h" @@ -98,7 +99,7 @@ static void kmp_sec_prot_receive_disable(sec_prot_t *prot); #define kmp_api_get_from_prot(prot) (kmp_api_t *)(((uint8_t *)prot) - offsetof(kmp_api_t, sec_prot)); -kmp_api_t *kmp_api_create(kmp_service_t *service, kmp_type_e type) +kmp_api_t *kmp_api_create(kmp_service_t *service, kmp_type_e type, sec_prot_cfg_t *cfg) { if (!service) { return 0; @@ -150,6 +151,7 @@ kmp_api_t *kmp_api_create(kmp_service_t *service, kmp_type_e type) kmp->sec_prot.addr_get = kmp_sec_prot_eui64_addr_get; kmp->sec_prot.type_get = kmp_sec_prot_by_type_get; kmp->sec_prot.receive_disable = kmp_sec_prot_receive_disable; + kmp->sec_prot.cfg = cfg; if (sec_prot->init(&kmp->sec_prot) < 0) { ns_dyn_mem_free(kmp); diff --git a/source/Security/kmp/kmp_api.h b/source/Security/kmp/kmp_api.h index 411d982bb2..062b36b4ad 100644 --- a/source/Security/kmp/kmp_api.h +++ b/source/Security/kmp/kmp_api.h @@ -61,6 +61,8 @@ typedef struct sec_prot_s sec_prot_t; typedef struct kmp_api_s kmp_api_t; typedef struct kmp_service_s kmp_service_t; +struct ws_cfg_settings_s; + /** * kmp_api_create_request KMP-CREATE.request * @@ -123,11 +125,12 @@ typedef void kmp_api_finished(kmp_api_t *kmp); * * \param service KMP service * \param type KMP type + * \param cfg configuration * * \return KMP instance or NULL * */ -kmp_api_t *kmp_api_create(kmp_service_t *service, kmp_type_e type); +kmp_api_t *kmp_api_create(kmp_service_t *service, kmp_type_e type, sec_prot_cfg_t *cfg); /** * kmp_api_start start KMP api diff --git a/source/Security/kmp/kmp_eapol_pdu_if.c b/source/Security/kmp/kmp_eapol_pdu_if.c index 2b8a6616d4..6cf5c8f064 100644 --- a/source/Security/kmp/kmp_eapol_pdu_if.c +++ b/source/Security/kmp/kmp_eapol_pdu_if.c @@ -23,6 +23,7 @@ #include "nsdynmemLIB.h" #include "6LoWPAN/ws/ws_config.h" #include "NWK_INTERFACE/Include/protocol.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/kmp/kmp_eapol_pdu_if.h" diff --git a/source/Security/kmp/kmp_socket_if.c b/source/Security/kmp/kmp_socket_if.c index 6b905d5791..79aca99ee6 100644 --- a/source/Security/kmp/kmp_socket_if.c +++ b/source/Security/kmp/kmp_socket_if.c @@ -29,6 +29,7 @@ #include "Common_Protocols/ipv6_constants.h" #include "socket_api.h" #include "6LoWPAN/ws/ws_config.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/kmp/kmp_socket_if.h" diff --git a/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c b/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c index bc61ab1ac6..e8118585ad 100644 --- a/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c +++ b/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c @@ -24,6 +24,8 @@ #include "fhss_config.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/PANA/pana_eap_header.h" @@ -77,22 +79,6 @@ typedef struct { bool send_pending: 1; /**< TLS data is not yet send to network */ } eap_tls_sec_prot_int_t; -/*Small network setup*/ -#define EAP_TLS_SMALL_IMIN 300 // retries done in 30 seconds -#define EAP_TLS_SMALL_IMAX 900 // Largest value 90 seconds - -/* Large network setup*/ -#define EAP_TLS_LARGE_IMIN 600 // retries done in 60 seconds -#define EAP_TLS_LARGE_IMAX 2400 // Largest value 240 seconds - - -static trickle_params_t eap_tls_trickle_params = { - .Imin = EAP_TLS_SMALL_IMIN, /* ticks are 100ms */ - .Imax = EAP_TLS_SMALL_IMAX, /* ticks are 100ms */ - .k = 0, /* infinity - no consistency checking */ - .TimerExpirations = 2 -}; - static uint16_t auth_eap_tls_sec_prot_size(void); static int8_t auth_eap_tls_sec_prot_init(sec_prot_t *prot); @@ -126,19 +112,6 @@ int8_t auth_eap_tls_sec_prot_register(kmp_service_t *service) return 0; } -int8_t auth_eap_tls_sec_prot_timing_adjust(uint8_t timing) -{ - - if (timing < 16) { - eap_tls_trickle_params.Imin = EAP_TLS_SMALL_IMIN; - eap_tls_trickle_params.Imax = EAP_TLS_SMALL_IMAX; - } else { - eap_tls_trickle_params.Imin = EAP_TLS_LARGE_IMIN; - eap_tls_trickle_params.Imax = EAP_TLS_LARGE_IMAX; - } - return 0; -} - static uint16_t auth_eap_tls_sec_prot_size(void) { return sizeof(eap_tls_sec_prot_int_t); @@ -216,7 +189,7 @@ static int8_t auth_eap_tls_sec_prot_receive(sec_prot_t *prot, void *pdu, uint16_ // Call state machine prot->state_machine(prot); // Resets trickle timer to give time for supplicant to answer - sec_prot_timer_trickle_start(&data->common, &eap_tls_trickle_params); + sec_prot_timer_trickle_start(&data->common, &prot->cfg->sec_prot_trickle_params); data->init_key_cnt++; } // Filters repeated initial EAPOL-key messages @@ -323,7 +296,8 @@ static void auth_eap_tls_sec_prot_timer_timeout(sec_prot_t *prot, uint16_t ticks data->burst_filt_timer = 0; } - sec_prot_timer_timeout_handle(prot, &data->common, &eap_tls_trickle_params, ticks); + sec_prot_timer_timeout_handle(prot, &data->common, + &prot->cfg->sec_prot_trickle_params, ticks); } static void auth_eap_tls_sec_prot_tls_create_indication(sec_prot_t *tls_prot) @@ -447,7 +421,7 @@ static void auth_eap_tls_sec_prot_state_machine(sec_prot_t *prot) auth_eap_tls_sec_prot_message_send(prot, EAP_REQ, EAP_IDENTITY, EAP_TLS_EXCHANGE_NONE); // Start trickle timer to re-send if no response - sec_prot_timer_trickle_start(&data->common, &eap_tls_trickle_params); + sec_prot_timer_trickle_start(&data->common, &prot->cfg->sec_prot_trickle_params); sec_prot_state_set(prot, &data->common, EAP_TLS_STATE_RESPONSE_ID); break; @@ -471,7 +445,7 @@ static void auth_eap_tls_sec_prot_state_machine(sec_prot_t *prot) auth_eap_tls_sec_prot_message_send(prot, EAP_REQ, EAP_TLS, EAP_TLS_EXCHANGE_START); // Start trickle timer to re-send if no response - sec_prot_timer_trickle_start(&data->common, &eap_tls_trickle_params); + sec_prot_timer_trickle_start(&data->common, &prot->cfg->sec_prot_trickle_params); sec_prot_state_set(prot, &data->common, EAP_TLS_STATE_RESPONSE_START); break; @@ -553,7 +527,7 @@ static void auth_eap_tls_sec_prot_state_machine(sec_prot_t *prot) auth_eap_tls_sec_prot_message_send(prot, EAP_REQ, EAP_TLS, EAP_TLS_EXCHANGE_ONGOING); // Start trickle timer to re-send if no response - sec_prot_timer_trickle_start(&data->common, &eap_tls_trickle_params); + sec_prot_timer_trickle_start(&data->common, &prot->cfg->sec_prot_trickle_params); } else { // TLS done, indicate success to peer if (data->tls_result == EAP_TLS_RESULT_HANDSHAKE_OVER) { diff --git a/source/Security/protocols/eap_tls_sec_prot/eap_tls_sec_prot_lib.c b/source/Security/protocols/eap_tls_sec_prot/eap_tls_sec_prot_lib.c index d6ca43c18d..1513f99cb0 100644 --- a/source/Security/protocols/eap_tls_sec_prot/eap_tls_sec_prot_lib.c +++ b/source/Security/protocols/eap_tls_sec_prot/eap_tls_sec_prot_lib.c @@ -25,6 +25,7 @@ #include "fhss_config.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/PANA/pana_eap_header.h" diff --git a/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c b/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c index bac7ecceb4..c7c935242d 100644 --- a/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c +++ b/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c @@ -24,6 +24,7 @@ #include "fhss_config.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/PANA/pana_eap_header.h" @@ -75,8 +76,6 @@ typedef struct { #define EAP_TLS_RETRY_TIMEOUT_SMALL 330*10 // retry timeout for small network additional 30 seconds for authenticator delay #define EAP_TLS_RETRY_TIMEOUT_LARGE 750*10 // retry timeout for large network additional 30 seconds for authenticator delay -static uint16_t retry_timeout = EAP_TLS_RETRY_TIMEOUT_SMALL; - static uint16_t supp_eap_tls_sec_prot_size(void); static int8_t supp_eap_tls_sec_prot_init(sec_prot_t *prot); @@ -110,17 +109,6 @@ int8_t supp_eap_tls_sec_prot_register(kmp_service_t *service) return 0; } -int8_t supp_eap_sec_prot_timing_adjust(uint8_t timing) -{ - if (timing < 16) { - retry_timeout = EAP_TLS_RETRY_TIMEOUT_SMALL; - } else { - retry_timeout = EAP_TLS_RETRY_TIMEOUT_LARGE; - } - return 0; -} - - static uint16_t supp_eap_tls_sec_prot_size(void) { return sizeof(eap_tls_sec_prot_int_t); @@ -416,7 +404,7 @@ static void supp_eap_tls_sec_prot_state_machine(sec_prot_t *prot) } // Set retry timeout based on network size - data->common.ticks = retry_timeout; + data->common.ticks = prot->cfg->sec_prot_retry_timeout; // Store sequence ID supp_eap_tls_sec_prot_seq_id_update(prot); @@ -461,7 +449,7 @@ static void supp_eap_tls_sec_prot_state_machine(sec_prot_t *prot) supp_eap_tls_sec_prot_seq_id_update(prot); sec_prot_state_set(prot, &data->common, EAP_TLS_STATE_REQUEST); - data->common.ticks = retry_timeout; + data->common.ticks = prot->cfg->sec_prot_retry_timeout; // Initialize TLS protocol if (supp_eap_tls_sec_prot_init_tls(prot) < 0) { @@ -495,7 +483,7 @@ static void supp_eap_tls_sec_prot_state_machine(sec_prot_t *prot) // Store sequence ID if (supp_eap_tls_sec_prot_seq_id_update(prot)) { // When receiving a new sequence number, adds more time for re-send if no response - data->common.ticks = retry_timeout; + data->common.ticks = prot->cfg->sec_prot_retry_timeout; } // All fragments received for a message diff --git a/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.h b/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.h index 2b1dded5e8..78ececd7bc 100644 --- a/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.h +++ b/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.h @@ -33,27 +33,5 @@ */ int8_t supp_eap_tls_sec_prot_register(kmp_service_t *service); -/** - * supp_eap_sec_prot_timing_adjust Adjust retries and timings of the 4WH protocol - * - * Timing value is a generic number between 0 to 32 that goes from fast and - * reactive network to low bandwidth and long latency. - * - * example value definitions: - * 0-8 very fast network - * 9-16 medium network - * 16-24 slow network - * 25-32 extremely slow network - * - * There is no need to have lots variations in every layer if protocol is not very active in any case. - * - * \param timing Timing value. - * - * \return < 0 failure - * \return >= 0 success - * - */ -int8_t supp_eap_sec_prot_timing_adjust(uint8_t timing); - #endif /* SUPP_EAP_TLS_SEC_PROT_H_ */ diff --git a/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c b/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c index 02b32b729f..b43ca5e58f 100644 --- a/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c +++ b/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c @@ -24,6 +24,8 @@ #include "fhss_config.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/PANA/pana_eap_header.h" @@ -68,21 +70,6 @@ typedef struct { uint16_t recv_size; /**< received pdu size */ } fwh_sec_prot_int_t; -/*Small network setup*/ -#define FWH_SMALL_IMIN 300 // retries done in 30 seconds -#define FWH_SMALL_IMAX 900 // Largest value 90 seconds - -/* Large network setup*/ -#define FWH_LARGE_IMIN 600 // retries done in 60 seconds -#define FWH_LARGE_IMAX 2400 // Largest value 240 seconds - -static trickle_params_t fwh_trickle_params = { - .Imin = FWH_SMALL_IMIN, /* ticks are 100ms */ - .Imax = FWH_SMALL_IMAX, /* ticks are 100ms */ - .k = 0, /* infinity - no consistency checking */ - .TimerExpirations = 2 -}; - static uint16_t auth_fwh_sec_prot_size(void); static int8_t auth_fwh_sec_prot_init(sec_prot_t *prot); @@ -113,18 +100,6 @@ int8_t auth_fwh_sec_prot_register(kmp_service_t *service) return 0; } -int8_t auth_fwh_sec_prot_timing_adjust(uint8_t timing) -{ - if (timing < 16) { - fwh_trickle_params.Imin = FWH_SMALL_IMIN; - fwh_trickle_params.Imax = FWH_SMALL_IMAX; - } else { - fwh_trickle_params.Imin = FWH_LARGE_IMIN; - fwh_trickle_params.Imax = FWH_LARGE_IMAX; - } - return 0; -} - static uint16_t auth_fwh_sec_prot_size(void) { return sizeof(fwh_sec_prot_int_t); @@ -331,7 +306,7 @@ static int8_t auth_fwh_sec_prot_message_send(sec_prot_t *prot, fwh_sec_prot_msg_ static void auth_fwh_sec_prot_timer_timeout(sec_prot_t *prot, uint16_t ticks) { fwh_sec_prot_int_t *data = fwh_sec_prot_get(prot); - sec_prot_timer_timeout_handle(prot, &data->common, &fwh_trickle_params, ticks); + sec_prot_timer_timeout_handle(prot, &data->common, &prot->cfg->sec_prot_trickle_params, ticks); } static void auth_fwh_sec_prot_state_machine(sec_prot_t *prot) @@ -368,7 +343,7 @@ static void auth_fwh_sec_prot_state_machine(sec_prot_t *prot) auth_fwh_sec_prot_message_send(prot, FWH_MESSAGE_1); // Start trickle timer to re-send if no response - sec_prot_timer_trickle_start(&data->common, &fwh_trickle_params); + sec_prot_timer_trickle_start(&data->common, &prot->cfg->sec_prot_trickle_params); sec_prot_state_set(prot, &data->common, FWH_STATE_MESSAGE_2); break; @@ -396,7 +371,7 @@ static void auth_fwh_sec_prot_state_machine(sec_prot_t *prot) auth_fwh_sec_prot_message_send(prot, FWH_MESSAGE_3); // Start trickle timer to re-send if no response - sec_prot_timer_trickle_start(&data->common, &fwh_trickle_params); + sec_prot_timer_trickle_start(&data->common, &prot->cfg->sec_prot_trickle_params); sec_prot_state_set(prot, &data->common, FWH_STATE_MESSAGE_4); } diff --git a/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.c b/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.c index ee44df03cf..e5a44e18b8 100644 --- a/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.c +++ b/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.c @@ -24,6 +24,7 @@ #include "fhss_config.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/PANA/pana_eap_header.h" @@ -82,11 +83,6 @@ typedef struct { bool recv_replay_cnt_set : 1; /**< received replay counter set */ } fwh_sec_prot_int_t; -#define FWH_RETRY_TIMEOUT_SMALL 300*10 // retry timeout for small network -#define FWH_RETRY_TIMEOUT_LARGE 720*10 // retry timeout for large network - -static uint16_t retry_timeout = FWH_RETRY_TIMEOUT_SMALL; - static uint16_t supp_fwh_sec_prot_size(void); static int8_t supp_fwh_sec_prot_init(sec_prot_t *prot); @@ -124,15 +120,6 @@ int8_t supp_fwh_sec_prot_register(kmp_service_t *service) return 0; } -int8_t supp_fwh_sec_prot_timing_adjust(uint8_t timing) -{ - if (timing < 16) { - retry_timeout = FWH_RETRY_TIMEOUT_SMALL; - } else { - retry_timeout = FWH_RETRY_TIMEOUT_LARGE; - } - return 0; -} static uint16_t supp_fwh_sec_prot_size(void) { @@ -152,7 +139,7 @@ static int8_t supp_fwh_sec_prot_init(sec_prot_t *prot) sec_prot_init(&data->common); sec_prot_state_set(prot, &data->common, FWH_STATE_INIT); - data->common.ticks = retry_timeout; + data->common.ticks = prot->cfg->sec_prot_retry_timeout; data->msg3_received = false; data->msg3_retry_wait = false; data->recv_replay_cnt = 0; @@ -350,7 +337,7 @@ static void supp_fwh_sec_prot_state_machine(sec_prot_t *prot) if (sec_prot_result_ok_check(&data->common)) { // Send 4WH message 2 supp_fwh_sec_prot_message_send(prot, FWH_MESSAGE_2); - data->common.ticks = retry_timeout; + data->common.ticks = prot->cfg->sec_prot_retry_timeout; sec_prot_state_set(prot, &data->common, FWH_STATE_MESSAGE_3); } else { // Ready to be deleted @@ -378,7 +365,7 @@ static void supp_fwh_sec_prot_state_machine(sec_prot_t *prot) // Send 4WH message 2 supp_fwh_sec_prot_message_send(prot, FWH_MESSAGE_2); - data->common.ticks = retry_timeout; + data->common.ticks = prot->cfg->sec_prot_retry_timeout; return; } else if (data->recv_msg != FWH_MESSAGE_3) { return; @@ -405,7 +392,7 @@ static void supp_fwh_sec_prot_state_machine(sec_prot_t *prot) // Sends 4WH Message 4 supp_fwh_sec_prot_message_send(prot, FWH_MESSAGE_4); - data->common.ticks = retry_timeout; + data->common.ticks = prot->cfg->sec_prot_retry_timeout; sec_prot_state_set(prot, &data->common, FWH_STATE_FINISH); break; diff --git a/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.h b/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.h index 8369625847..2cb2284e3c 100644 --- a/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.h +++ b/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.h @@ -34,26 +34,4 @@ */ int8_t supp_fwh_sec_prot_register(kmp_service_t *service); -/** - * supp_fwh_sec_prot_timing_adjust Adjust retries and timings of the 4WH protocol - * - * Timing value is a generic number between 0 to 32 that goes from fast and - * reactive network to low bandwidth and long latency. - * - * example value definitions: - * 0-8 very fast network - * 9-16 medium network - * 16-24 slow network - * 25-32 extremely slow network - * - * There is no need to have lots variations in every layer if protocol is not very active in any case. - * - * \param timing Timing value. - * - * \return < 0 failure - * \return >= 0 success - * - */ -int8_t supp_fwh_sec_prot_timing_adjust(uint8_t timing); - #endif /* SUPP_FWH_SEC_PROT_H_ */ diff --git a/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c b/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c index b4206f69b4..9c1b47d01d 100644 --- a/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c +++ b/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c @@ -24,6 +24,8 @@ #include "fhss_config.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" +#include "6LoWPAN/ws/ws_cfg_settings.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/PANA/pana_eap_header.h" @@ -60,21 +62,6 @@ typedef struct { uint16_t recv_size; /**< Received pdu size */ } gkh_sec_prot_int_t; -/*Small network setup*/ -#define GKH_SMALL_IMIN 300 // retries done in 30 seconds -#define GKH_SMALL_IMAX 900 // Largest value 90 seconds - -/* Large network setup*/ -#define GKH_LARGE_IMIN 600 // retries done in 60 seconds -#define GKH_LARGE_IMAX 2400 // Largest value 240 seconds - -static trickle_params_t gkh_trickle_params = { - .Imin = GKH_SMALL_IMIN, /* ticks are 100ms */ - .Imax = GKH_SMALL_IMAX, /* ticks are 100ms */ - .k = 0, /* infinity - no consistency checking */ - .TimerExpirations = 2 -}; - static uint16_t auth_gkh_sec_prot_size(void); static int8_t auth_gkh_sec_prot_init(sec_prot_t *prot); @@ -103,18 +90,6 @@ int8_t auth_gkh_sec_prot_register(kmp_service_t *service) return 0; } -int8_t auth_gkh_sec_prot_timing_adjust(uint8_t timing) -{ - if (timing < 16) { - gkh_trickle_params.Imin = GKH_SMALL_IMIN; - gkh_trickle_params.Imax = GKH_SMALL_IMAX; - } else { - gkh_trickle_params.Imin = GKH_LARGE_IMIN; - gkh_trickle_params.Imax = GKH_LARGE_IMAX; - } - return 0; -} - static uint16_t auth_gkh_sec_prot_size(void) { return sizeof(gkh_sec_prot_int_t); @@ -283,7 +258,7 @@ static int8_t auth_gkh_sec_prot_message_send(sec_prot_t *prot, gkh_sec_prot_msg_ static void auth_gkh_sec_prot_timer_timeout(sec_prot_t *prot, uint16_t ticks) { gkh_sec_prot_int_t *data = gkh_sec_prot_get(prot); - sec_prot_timer_timeout_handle(prot, &data->common, &gkh_trickle_params, ticks); + sec_prot_timer_timeout_handle(prot, &data->common, &prot->cfg->sec_prot_trickle_params, ticks); } static void auth_gkh_sec_prot_state_machine(sec_prot_t *prot) @@ -312,7 +287,7 @@ static void auth_gkh_sec_prot_state_machine(sec_prot_t *prot) auth_gkh_sec_prot_message_send(prot, GKH_MESSAGE_1); // Start trickle timer to re-send if no response - sec_prot_timer_trickle_start(&data->common, &gkh_trickle_params); + sec_prot_timer_trickle_start(&data->common, &prot->cfg->sec_prot_trickle_params); sec_prot_state_set(prot, &data->common, GKH_STATE_MESSAGE_2); diff --git a/source/Security/protocols/gkh_sec_prot/supp_gkh_sec_prot.c b/source/Security/protocols/gkh_sec_prot/supp_gkh_sec_prot.c index ccd2890ec9..064f2bec76 100644 --- a/source/Security/protocols/gkh_sec_prot/supp_gkh_sec_prot.c +++ b/source/Security/protocols/gkh_sec_prot/supp_gkh_sec_prot.c @@ -24,6 +24,7 @@ #include "fhss_config.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/PANA/pana_eap_header.h" diff --git a/source/Security/protocols/key_sec_prot/key_sec_prot.c b/source/Security/protocols/key_sec_prot/key_sec_prot.c index 409546c3dc..daa07af371 100644 --- a/source/Security/protocols/key_sec_prot/key_sec_prot.c +++ b/source/Security/protocols/key_sec_prot/key_sec_prot.c @@ -24,6 +24,7 @@ #include "fhss_config.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/PANA/pana_eap_header.h" diff --git a/source/Security/protocols/sec_prot.h b/source/Security/protocols/sec_prot.h index 49d28f7d1e..556d769f6b 100644 --- a/source/Security/protocols/sec_prot.h +++ b/source/Security/protocols/sec_prot.h @@ -268,6 +268,7 @@ struct sec_prot_s { sec_prot_receive_disable *receive_disable; /**< Disable receiving of messages */ sec_prot_keys_t *sec_keys; /**< Security keys storage pointer */ + sec_prot_cfg_t *cfg; /**< Configuration pointer */ uint8_t header_size; /**< Header size */ sec_prot_int_data_t *data; /**< Protocol internal data */ }; diff --git a/source/Security/protocols/sec_prot_cfg.h b/source/Security/protocols/sec_prot_cfg.h new file mode 100644 index 0000000000..fa2a88dafb --- /dev/null +++ b/source/Security/protocols/sec_prot_cfg.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2020, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SEC_PROT_CFG_H_ +#define SEC_PROT_CFG_H_ + +/* Security protocol configuration settings */ + +typedef struct sec_prot_cfg_s { + trickle_params_t sec_prot_trickle_params; + uint16_t sec_prot_retry_timeout; + uint16_t sec_max_ongoing_authentication; +} sec_prot_cfg_t; + +#endif /* SEC_PROT_CONF_H_ */ diff --git a/source/Security/protocols/sec_prot_keys.c b/source/Security/protocols/sec_prot_keys.c index cdcc31de32..c420a5823f 100644 --- a/source/Security/protocols/sec_prot_keys.c +++ b/source/Security/protocols/sec_prot_keys.c @@ -25,6 +25,7 @@ #include "Common_Protocols/ipv6_constants.h" #include "socket_api.h" #include "6LoWPAN/ws/ws_config.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/PANA/pana_eap_header.h" diff --git a/source/Security/protocols/sec_prot_lib.c b/source/Security/protocols/sec_prot_lib.c index 29268529d3..0987054d6b 100644 --- a/source/Security/protocols/sec_prot_lib.c +++ b/source/Security/protocols/sec_prot_lib.c @@ -26,6 +26,7 @@ #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" #include "Service_Libs/Trickle/trickle.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/PANA/pana_eap_header.h" diff --git a/source/Security/protocols/tls_sec_prot/tls_sec_prot.c b/source/Security/protocols/tls_sec_prot/tls_sec_prot.c index beff5f5bae..ad07fd1ca1 100644 --- a/source/Security/protocols/tls_sec_prot/tls_sec_prot.c +++ b/source/Security/protocols/tls_sec_prot/tls_sec_prot.c @@ -22,8 +22,10 @@ #include "ns_trace.h" #include "nsdynmemLIB.h" #include "fhss_config.h" +#include "Service_Libs/Trickle/trickle.h" #include "NWK_INTERFACE/Include/protocol.h" #include "6LoWPAN/ws/ws_config.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/kmp/kmp_addr.h" #include "Security/kmp/kmp_api.h" #include "Security/PANA/pana_eap_header.h" diff --git a/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c b/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c index 6f236bcf1f..de1d86b515 100644 --- a/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c +++ b/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c @@ -24,7 +24,7 @@ #include MBEDTLS_CONFIG_FILE #endif -#if defined(MBEDTLS_SSL_TLS_C) && defined(MBEDTLS_X509_CRT_PARSE_C) +#if defined(MBEDTLS_SSL_TLS_C) && defined(MBEDTLS_X509_CRT_PARSE_C) && defined(MBEDTLS_SSL_EXPORT_KEYS) /* EXPORT_KEYS not supported by mbedtls baremetal yet */ #define WS_MBEDTLS_SECURITY_ENABLED #endif @@ -35,10 +35,14 @@ #include "ns_trace.h" #include "nsdynmemLIB.h" #include "common_functions.h" +#include "Service_Libs/Trickle/trickle.h" +#include "Security/protocols/sec_prot_cfg.h" #include "Security/protocols/sec_prot_certs.h" #include "Security/protocols/tls_sec_prot/tls_sec_prot_lib.h" +#if defined(MBEDTLS_SSL_TLS_C) && defined(MBEDTLS_X509_CRT_PARSE_C) && defined(MBEDTLS_SSL_EXPORT_KEYS) /* EXPORT_KEYS not supported by mbedtls baremetal yet */ #ifdef WS_MBEDTLS_SECURITY_ENABLED +#endif #include "mbedtls/sha256.h" #include "mbedtls/error.h" @@ -51,8 +55,6 @@ #include "mbedtls/debug.h" #include "mbedtls/oid.h" -#include "mbedtls/ssl_internal.h" - #define TRACE_GROUP "tlsl" #define TLS_HANDSHAKE_TIMEOUT_MIN 25000 @@ -327,8 +329,10 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p return -1; } +#if !defined(MBEDTLS_SSL_CONF_RNG) // Configure random number generator mbedtls_ssl_conf_rng(&sec->conf, mbedtls_ctr_drbg_random, &sec->ctr_drbg); +#endif #ifdef MBEDTLS_ECP_RESTARTABLE // Set ECC calculation maximum operations (affects only client) @@ -340,9 +344,22 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p return -1; } + // Defines MBEDTLS_SSL_CONF_RECV/SEND/RECV_TIMEOUT define global functions which should be the same for all + // callers of mbedtls_ssl_set_bio_ctx and there should be only one ssl context. If these rules don't apply, + // these defines can't be used. +#if !defined(MBEDTLS_SSL_CONF_RECV) && !defined(MBEDTLS_SSL_CONF_SEND) && !defined(MBEDTLS_SSL_CONF_RECV_TIMEOUT) // Set calbacks mbedtls_ssl_set_bio(&sec->ssl, sec, tls_sec_prot_lib_ssl_send, tls_sec_prot_lib_ssl_recv, NULL); +#else + mbedtls_ssl_set_bio_ctx(&sec->ssl, sec); +#endif /* !defined(MBEDTLS_SSL_CONF_RECV) && !defined(MBEDTLS_SSL_CONF_SEND) && !defined(MBEDTLS_SSL_CONF_RECV_TIMEOUT) */ + +// Defines MBEDTLS_SSL_CONF_SET_TIMER/GET_TIMER define global functions which should be the same for all +// callers of mbedtls_ssl_set_timer_cb and there should be only one ssl context. If these rules don't apply, +// these defines can't be used. +#if !defined(MBEDTLS_SSL_CONF_SET_TIMER) && !defined(MBEDTLS_SSL_CONF_GET_TIMER) mbedtls_ssl_set_timer_cb(&sec->ssl, sec, tls_sec_prot_lib_ssl_set_timer, tls_sec_prot_lib_ssl_get_timer); +#endif /* !defined(MBEDTLS_SSL_CONF_SET_TIMER) && !defined(MBEDTLS_SSL_CONF_GET_TIMER) */ // Configure certificates, keys and certificate revocation list if (tls_sec_prot_lib_configure_certificates(sec, certs) != 0) { @@ -350,6 +367,7 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p return -1; } +#if !defined(MBEDTLS_SSL_CONF_SINGLE_CIPHERSUITE) // Configure ciphersuites static const int sec_suites[] = { MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8, @@ -358,6 +376,7 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p 0 }; mbedtls_ssl_conf_ciphersuites(&sec->conf, sec_suites); +#endif /* !defined(MBEDTLS_SSL_CONF_SINGLE_CIPHERSUITE) */ #ifdef TLS_SEC_PROT_LIB_TLS_DEBUG mbedtls_ssl_conf_dbg(&sec->conf, tls_sec_prot_lib_debug, sec); @@ -367,19 +386,23 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p // Export keys callback mbedtls_ssl_conf_export_keys_ext_cb(&sec->conf, tls_sec_prot_lib_ssl_export_keys, sec); +#if !defined(MBEDTLS_SSL_CONF_MIN_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MIN_MAJOR_VER) mbedtls_ssl_conf_min_version(&sec->conf, MBEDTLS_SSL_MAJOR_VERSION_3, MBEDTLS_SSL_MAJOR_VERSION_3); +#endif /* !defined(MBEDTLS_SSL_CONF_MIN_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MIN_MAJOR_VER) */ + +#if !defined(MBEDTLS_SSL_CONF_MAX_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MAX_MAJOR_VER) mbedtls_ssl_conf_max_version(&sec->conf, MBEDTLS_SSL_MAJOR_VERSION_3, MBEDTLS_SSL_MAJOR_VERSION_3); +#endif /* !defined(MBEDTLS_SSL_CONF_MAX_MINOR_VER) || !defined(MBEDTLS_SSL_CONF_MAX_MAJOR_VER) */ // Set certificate verify callback mbedtls_ssl_set_verify(&sec->ssl, tls_sec_prot_lib_x509_crt_verify, sec); -#ifdef MBEDTLS_ECP_RESTARTABLE - if (is_server_is_set) { - // Temporary to enable non blocking ECC */ - sec->ssl.handshake->ecrs_enabled = 1; - } -#endif - + /* Currently assuming we are running fast enough HW that ECC calculations are not blocking any normal operation. + * + * If there is a problem with ECC calculations and those are taking too long in border router + * MBEDTLS_ECP_RESTARTABLE feature needs to be enabled and public API is needed to allow it in border router + * enabling should be done here. + */ return 0; } @@ -550,7 +573,7 @@ static int tls_sec_prot_lib_x509_crt_idevid_ldevid_verify(tls_security_t *sec, m // For both IDevID and LDevId both subject alternative name or extended key usage must be valid if (tls_sec_prot_lib_subject_alternative_name_validate(crt) < 0 || tls_sec_prot_lib_extended_key_usage_validate(crt) < 0) { - tr_error("invalid cert"); + tr_info("no wisun fields on cert"); if (sec->ext_cert_valid) { *flags |= MBEDTLS_X509_BADCERT_OTHER; return MBEDTLS_ERR_X509_CERT_VERIFY_FAILED; @@ -570,7 +593,7 @@ static int tls_sec_prot_lib_x509_crt_server_verify(tls_security_t *sec, mbedtls_ if (sane_res >= 0 || ext_key_res >= 0) { // Then both subject alternative name and extended key usage must be valid if (sane_res < 0 || ext_key_res < 0) { - tr_error("invalid cert"); + tr_info("no wisun fields on cert"); if (sec->ext_cert_valid) { *flags |= MBEDTLS_X509_BADCERT_OTHER; return MBEDTLS_ERR_X509_CERT_VERIFY_FAILED; diff --git a/source/Service_Libs/fhss/fhss_common.h b/source/Service_Libs/fhss/fhss_common.h index 4d10667924..724351d029 100644 --- a/source/Service_Libs/fhss/fhss_common.h +++ b/source/Service_Libs/fhss/fhss_common.h @@ -40,6 +40,7 @@ struct fhss_structure { int8_t fhss_event_timer; uint8_t active_fhss_events; uint16_t number_of_channels; + uint16_t number_of_uc_channels; uint16_t optimal_packet_length; fhss_states fhss_state; uint32_t fhss_timeout; diff --git a/source/Service_Libs/fhss/fhss_ws.c b/source/Service_Libs/fhss/fhss_ws.c index d5272250f8..1d29e70c2a 100644 --- a/source/Service_Libs/fhss/fhss_ws.c +++ b/source/Service_Libs/fhss/fhss_ws.c @@ -122,6 +122,8 @@ fhss_structure_t *fhss_ws_enable(fhss_api_t *fhss_api, const fhss_ws_configurati return NULL; } int channel_count = channel_list_count_channels(fhss_configuration->channel_mask); + int uc_channel_count = channel_list_count_channels(fhss_configuration->unicast_channel_mask); + if (channel_count <= 0) { // There must be at least one configured channel in channel list return NULL; @@ -145,7 +147,15 @@ fhss_structure_t *fhss_ws_enable(fhss_api_t *fhss_api, const fhss_ws_configurati fhss_struct->fhss_event_timer = eventOS_callback_timer_register(fhss_event_timer_cb); fhss_struct->ws->fhss_configuration = *fhss_configuration; + if (uc_channel_count == 0) { + //If Unicast channel is empty use Domain mask + for (uint8_t i = 0; i < 8; i++) { + fhss_struct->ws->fhss_configuration.unicast_channel_mask[i] = fhss_configuration->channel_mask[i]; + } + uc_channel_count = channel_count; + } fhss_struct->number_of_channels = channel_count; + fhss_struct->number_of_uc_channels = uc_channel_count; fhss_struct->optimal_packet_length = OPTIMAL_PACKET_LENGTH; fhss_ws_set_hop_count(fhss_struct, 0xff); fhss_struct->rx_channel = fhss_configuration->unicast_fixed_channel; @@ -371,7 +381,7 @@ static uint32_t fhss_ws_calculate_ufsi(fhss_structure_t *fhss_structure, uint32_ uint8_t dwell_time = fhss_structure->ws->fhss_configuration.fhss_uc_dwell_interval; uint16_t cur_slot = fhss_structure->ws->uc_slot; if (cur_slot == 0) { - cur_slot = fhss_structure->number_of_channels; + cur_slot = fhss_structure->number_of_uc_channels; } cur_slot--; uint32_t remaining_time_ms = US_TO_MS(get_remaining_slots_us(fhss_structure, fhss_unicast_handler, MS_TO_US(fhss_structure->ws->fhss_configuration.fhss_uc_dwell_interval))); @@ -383,8 +393,8 @@ static uint32_t fhss_ws_calculate_ufsi(fhss_structure_t *fhss_structure, uint32_ uint64_t ms_since_seq_start = (cur_slot * dwell_time) + (dwell_time - remaining_time_ms) + time_to_tx; uint32_t seq_length = 0x10000; if (fhss_structure->ws->fhss_configuration.ws_uc_channel_function == WS_TR51CF) { - ms_since_seq_start %= (dwell_time * fhss_structure->number_of_channels); - seq_length = fhss_structure->number_of_channels; + ms_since_seq_start %= (dwell_time * fhss_structure->number_of_uc_channels); + seq_length = fhss_structure->number_of_uc_channels; } return own_floor((float)(ms_since_seq_start * DEF_2E24) / (seq_length * dwell_time)); } @@ -467,16 +477,16 @@ static void fhss_ws_update_uc_channel_callback(fhss_structure_t *fhss_structure) if (fhss_structure->ws->fhss_configuration.ws_uc_channel_function == WS_FIXED_CHANNEL) { return; } else if (fhss_structure->ws->fhss_configuration.ws_uc_channel_function == WS_TR51CF) { - next_channel = fhss_structure->rx_channel = tr51_get_uc_channel_index(fhss_structure->ws->tr51_channel_table, fhss_structure->ws->tr51_output_table, fhss_structure->ws->uc_slot, mac_address, fhss_structure->number_of_channels, NULL); - if (++fhss_structure->ws->uc_slot == fhss_structure->number_of_channels) { + next_channel = fhss_structure->rx_channel = tr51_get_uc_channel_index(fhss_structure->ws->tr51_channel_table, fhss_structure->ws->tr51_output_table, fhss_structure->ws->uc_slot, mac_address, fhss_structure->number_of_uc_channels, NULL); + if (++fhss_structure->ws->uc_slot == fhss_structure->number_of_uc_channels) { fhss_structure->ws->uc_slot = 0; } } else if (fhss_structure->ws->fhss_configuration.ws_uc_channel_function == WS_DH1CF) { - next_channel = fhss_structure->rx_channel = dh1cf_get_uc_channel_index(fhss_structure->ws->uc_slot, mac_address, fhss_structure->number_of_channels); + next_channel = fhss_structure->rx_channel = dh1cf_get_uc_channel_index(fhss_structure->ws->uc_slot, mac_address, fhss_structure->number_of_uc_channels); fhss_structure->ws->uc_slot++; } else if (fhss_structure->ws->fhss_configuration.ws_uc_channel_function == WS_VENDOR_DEF_CF) { if (fhss_structure->ws->fhss_configuration.vendor_defined_cf) { - next_channel = fhss_structure->rx_channel = fhss_structure->ws->fhss_configuration.vendor_defined_cf(fhss_structure->fhss_api, fhss_structure->ws->bc_slot, mac_address, fhss_structure->ws->fhss_configuration.bsi, fhss_structure->number_of_channels); + next_channel = fhss_structure->rx_channel = fhss_structure->ws->fhss_configuration.vendor_defined_cf(fhss_structure->fhss_api, fhss_structure->ws->bc_slot, mac_address, fhss_structure->ws->fhss_configuration.bsi, fhss_structure->number_of_uc_channels); } } // Do not switch unicast channel when broadcast channel is active. @@ -521,16 +531,17 @@ static int fhss_ws_tx_handle_callback(const fhss_api_t *api, bool is_broadcast_a fhss_stats_update(fhss_structure, STATS_FHSS_UNKNOWN_NEIGHBOR, 1); return -2; } - // TODO: WS bootstrap has to store neighbors number of channels + if (neighbor_timing_info->uc_timing_info.unicast_number_of_channels == 0) { - neighbor_timing_info->uc_timing_info.unicast_number_of_channels = fhss_structure->number_of_channels; + return -1; } + uint16_t destination_slot = fhss_ws_calculate_destination_slot(neighbor_timing_info, tx_time); int32_t tx_channel = neighbor_timing_info->uc_timing_info.fixed_channel; if (neighbor_timing_info->uc_timing_info.unicast_channel_function == WS_TR51CF) { tx_channel = tr51_get_uc_channel_index(fhss_structure->ws->tr51_channel_table, fhss_structure->ws->tr51_output_table, destination_slot, destination_address, neighbor_timing_info->uc_timing_info.unicast_number_of_channels, NULL); } else if (neighbor_timing_info->uc_timing_info.unicast_channel_function == WS_DH1CF) { - tx_channel = dh1cf_get_uc_channel_index(destination_slot, destination_address, neighbor_timing_info->uc_timing_info.unicast_number_of_channels); + tx_channel = dh1cf_get_uc_channel_index(destination_slot, destination_address, neighbor_timing_info->uc_channel_list.channel_count); } else if (neighbor_timing_info->uc_timing_info.unicast_channel_function == WS_VENDOR_DEF_CF) { if (fhss_structure->ws->fhss_configuration.vendor_defined_cf) { tx_channel = fhss_structure->ws->fhss_configuration.vendor_defined_cf(fhss_structure->fhss_api, fhss_structure->ws->bc_slot, destination_address, fhss_structure->ws->fhss_configuration.bsi, neighbor_timing_info->uc_timing_info.unicast_number_of_channels); @@ -951,6 +962,7 @@ int fhss_ws_remove_parent(fhss_structure_t *fhss_structure, const uint8_t eui64[ int fhss_ws_configuration_set(fhss_structure_t *fhss_structure, const fhss_ws_configuration_t *fhss_configuration) { int channel_count = channel_list_count_channels(fhss_configuration->channel_mask); + int channel_count_uc = channel_list_count_channels(fhss_configuration->unicast_channel_mask); if (channel_count <= 0) { return -1; } @@ -968,17 +980,27 @@ int fhss_ws_configuration_set(fhss_structure_t *fhss_structure, const fhss_ws_co fhss_structure->ws->unicast_timer_running = true; } fhss_structure->ws->fhss_configuration = *fhss_configuration; + if (channel_count_uc == 0) { + //If Unicast channel is empty use Domain mask + for (uint8_t i = 0; i < 8; i++) { + fhss_structure->ws->fhss_configuration.unicast_channel_mask[i] = fhss_configuration->channel_mask[i]; + } + channel_count_uc = channel_count; + } + fhss_structure->number_of_channels = channel_count; + fhss_structure->number_of_uc_channels = channel_count_uc; if (fhss_configuration->ws_uc_channel_function == WS_FIXED_CHANNEL) { fhss_structure->rx_channel = fhss_configuration->unicast_fixed_channel; } platform_exit_critical(); - tr_info("fhss Configuration set, UC channel: %d, BC channel: %d, UC CF: %d, BC CF: %d, channels: %d, uc dwell: %d, bc dwell: %d, bc interval: %"PRIu32", bsi:%d", + tr_info("fhss Configuration set, UC channel: %d, BC channel: %d, UC CF: %d, BC CF: %d, channels: BC %d UC %d, uc dwell: %d, bc dwell: %d, bc interval: %"PRIu32", bsi:%d", fhss_structure->ws->fhss_configuration.unicast_fixed_channel, fhss_structure->ws->fhss_configuration.broadcast_fixed_channel, fhss_structure->ws->fhss_configuration.ws_uc_channel_function, fhss_structure->ws->fhss_configuration.ws_bc_channel_function, fhss_structure->number_of_channels, + fhss_structure->number_of_uc_channels, fhss_structure->ws->fhss_configuration.fhss_uc_dwell_interval, fhss_structure->ws->fhss_configuration.fhss_bc_dwell_interval, fhss_structure->ws->fhss_configuration.fhss_broadcast_interval, diff --git a/source/libNET/src/socket_api.c b/source/libNET/src/socket_api.c index 2cf27829c5..105c8579aa 100644 --- a/source/libNET/src/socket_api.c +++ b/source/libNET/src/socket_api.c @@ -39,10 +39,14 @@ #include "Common_Protocols/ipv6_flow.h" #include "Common_Protocols/tcp.h" #include "Common_Protocols/udp.h" +#include "6LoWPAN/Bootstraps/protocol_6lowpan.h" #include "common_functions.h" #define TRACE_GROUP "sckA" +/* Data already written to space provided */ +#define GETSOCKOPT_DATA_READY 1 + const uint8_t ns_in6addr_any[16] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; int8_t socket_open(uint8_t protocol, uint16_t identifier, void (*passed_fptr)(void *)) @@ -1010,12 +1014,35 @@ int8_t socket_setsockopt(int8_t socket, uint8_t level, uint8_t opt_name, const v } } +static bool socket_latency_get(const uint8_t dest_addr[static 16], uint32_t *latency) +{ + ipv6_route_t *route = ipv6_route_choose_next_hop(dest_addr, -1, NULL); + if (!route) { + return false; + } + + return protocol_6lowpan_latency_estimate_get(route->info.interface_id, latency); +} + +static bool socket_stagger_value_get(const uint8_t dest_addr[static 16], uint32_t data_amount, uint16_t *stagger_min, uint16_t *stagger_max, uint16_t *stagger_rand) +{ + ipv6_route_t *route = ipv6_route_choose_next_hop(dest_addr, -1, NULL); + if (!route) { + // No route found, return 0 + return false; + } + + return protocol_6lowpan_stagger_estimate_get(route->info.interface_id, data_amount, stagger_min, stagger_max, stagger_rand); +} + static union { int8_t s8; uint16_t u16; int16_t s16; uint32_t u32; int32_t s32; + uint64_t u64; + int64_t s64; bool boolean; } opt_temp; @@ -1130,7 +1157,41 @@ static int8_t ipv6_getsockopt(const socket_t *socket_ptr, uint8_t opt_name, cons *value = &opt_temp.boolean; *len = sizeof(bool); break; + case SOCKET_LATENCY: { + ns_ipv6_latency_t *ns_ipv6_latency = (ns_ipv6_latency_t *)*value; + if (*len < sizeof(ns_ipv6_latency_t)) { + return -1; + } + if (socket_latency_get(ns_ipv6_latency->dest_addr, &ns_ipv6_latency->latency)) { + *len = sizeof(ns_ipv6_latency_t); + return GETSOCKOPT_DATA_READY; + } + return -3; + /* break; */ + } + case SOCKET_STAGGER: { + ns_ipv6_stagger_t *ns_ipv6_stagger = (ns_ipv6_stagger_t *)*value; + uint16_t stagger_min, stagger_max, stagger_rand; + bool retval; + + if (*len < sizeof(ns_ipv6_stagger_t)) { + return -1; + } + retval = socket_stagger_value_get(ns_ipv6_stagger->dest_addr, + ns_ipv6_stagger->data_amount, + &stagger_min, &stagger_max, &stagger_rand); + if (retval) { + ns_ipv6_stagger->stagger_min = stagger_min; + ns_ipv6_stagger->stagger_max = stagger_max; + ns_ipv6_stagger->stagger_rand = stagger_rand; + *len = sizeof(ns_ipv6_stagger_t); + return GETSOCKOPT_DATA_READY; + } + + return -3; + /* break; */ + } default: return -2; } @@ -1145,12 +1206,15 @@ int8_t socket_getsockopt(int8_t socket, uint8_t level, uint8_t opt_name, void *o return -1; } - const void *value; - uint16_t len; + const void *value = opt_value; + uint16_t len = *opt_len; if (level == SOCKET_IPPROTO_IPV6 && socket_is_ipv6(socket_ptr)) { int8_t ret = ipv6_getsockopt(socket_ptr, opt_name, &value, &len); if (ret != 0) { + if (ret == GETSOCKOPT_DATA_READY) { + ret = 0; + } return ret; } } else if (level == SOCKET_SOL_SOCKET) { @@ -1198,4 +1262,3 @@ ns_cmsghdr_t *NS_CMSG_NXTHDR(const ns_msghdr_t *msgh, const ns_cmsghdr_t *cmsg) } return (ns_cmsghdr_t *) start_of_next_header; } - diff --git a/sources.mk b/sources.mk index 840c51105d..3998833c3b 100644 --- a/sources.mk +++ b/sources.mk @@ -40,6 +40,7 @@ SRCS += \ source/6LoWPAN/ws/ws_eapol_relay_lib.c \ source/6LoWPAN/ws/ws_eapol_pdu.c \ source/6LoWPAN/ws/ws_stats.c \ + source/6LoWPAN/ws/ws_cfg_settings.c \ source/BorderRouter/border_router.c \ source/Common_Protocols/icmpv6.c \ source/Common_Protocols/icmpv6_prefix.c \ From 30c16c15ebfcd5a678bbbf1e79c0776185072cd9 Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Fri, 3 Apr 2020 15:33:08 +0300 Subject: [PATCH 48/49] Update S2LP 802.15.4 RF driver Update driver to version 1.0.2 --- .../source/NanostackRfPhys2lp.cpp | 111 ++++++++---------- .../stm-s2lp-rf-driver/NanostackRfPhys2lp.h | 74 ++++++------ 2 files changed, 85 insertions(+), 100 deletions(-) diff --git a/components/802.15.4_RF/stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp b/components/802.15.4_RF/stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp index b65e1ebdd4..1ed861eb16 100644 --- a/components/802.15.4_RF/stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp +++ b/components/802.15.4_RF/stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp @@ -49,16 +49,16 @@ using namespace rtos; #endif #ifdef TEST_GPIOS_ENABLED -#define TEST_TX_STARTED rf->TEST1 = 1; -#define TEST_TX_DONE rf->TEST1 = 0; -#define TEST_RX_STARTED rf->TEST2 = 1; -#define TEST_RX_DONE rf->TEST2 = 0; -#define TEST_ACK_TX_STARTED rf->TEST3 = 1; -#define TEST_ACK_TX_DONE rf->TEST3 = 0; -#define TEST1_ON rf->TEST4 = 1; -#define TEST1_OFF rf->TEST4 = 0; -#define TEST2_ON rf->TEST5 = 1; -#define TEST2_OFF rf->TEST5 = 0; +#define TEST_TX_STARTED test_pins->TEST1 = 1; +#define TEST_TX_DONE test_pins->TEST1 = 0; +#define TEST_RX_STARTED test_pins->TEST2 = 1; +#define TEST_RX_DONE test_pins->TEST2 = 0; +#define TEST_CSMA_STARTED test_pins->TEST3 = 1; +#define TEST_CSMA_DONE test_pins->TEST3 = 0; +#define TEST_SPARE_1_ON test_pins->TEST4 = 1; +#define TEST_SPARE_1_OFF test_pins->TEST4 = 0; +#define TEST_SPARE_2_ON test_pins->TEST5 = 1; +#define TEST_SPARE_2_OFF test_pins->TEST5 = 0; extern void (*fhss_uc_switch)(void); extern void (*fhss_bc_switch)(void); #else //TEST_GPIOS_ENABLED @@ -66,12 +66,12 @@ extern void (*fhss_bc_switch)(void); #define TEST_TX_DONE #define TEST_RX_STARTED #define TEST_RX_DONE -#define TEST_ACK_TX_STARTED -#define TEST_ACK_TX_DONE -#define TEST1_ON -#define TEST1_OFF -#define TEST2_ON -#define TEST2_OFF +#define TEST_CSMA_STARTED +#define TEST_CSMA_DONE +#define TEST_SPARE_1_ON +#define TEST_SPARE_1_OFF +#define TEST_SPARE_2_ON +#define TEST_SPARE_2_OFF #endif //TEST_GPIOS_ENABLED #define MAC_FRAME_TYPE_MASK 0x07 @@ -116,21 +116,11 @@ class RFPins { public: RFPins(PinName spi_sdi, PinName spi_sdo, PinName spi_sclk, PinName spi_cs, PinName spi_sdn, -#ifdef TEST_GPIOS_ENABLED - PinName spi_test1, PinName spi_test2, PinName spi_test3, PinName spi_test4, PinName spi_test5, -#endif //TEST_GPIOS_ENABLED PinName spi_gpio0, PinName spi_gpio1, PinName spi_gpio2, PinName spi_gpio3); UnlockedSPI spi; DigitalOut CS; DigitalOut SDN; -#ifdef TEST_GPIOS_ENABLED - DigitalOut TEST1; - DigitalOut TEST2; - DigitalOut TEST3; - DigitalOut TEST4; - DigitalOut TEST5; -#endif //TEST_GPIOS_ENABLED InterruptIn RF_S2LP_GPIO0; InterruptIn RF_S2LP_GPIO1; InterruptIn RF_S2LP_GPIO2; @@ -145,21 +135,11 @@ public: RFPins::RFPins(PinName spi_sdi, PinName spi_sdo, PinName spi_sclk, PinName spi_cs, PinName spi_sdn, -#ifdef TEST_GPIOS_ENABLED - PinName spi_test1, PinName spi_test2, PinName spi_test3, PinName spi_test4, PinName spi_test5, -#endif //TEST_GPIOS_ENABLED PinName spi_gpio0, PinName spi_gpio1, PinName spi_gpio2, PinName spi_gpio3) : spi(spi_sdi, spi_sdo, spi_sclk), CS(spi_cs), SDN(spi_sdn), -#ifdef TEST_GPIOS_ENABLED - TEST1(spi_test1), - TEST2(spi_test2), - TEST3(spi_test3), - TEST4(spi_test4), - TEST5(spi_test5), -#endif //TEST_GPIOS_ENABLED RF_S2LP_GPIO0(spi_gpio0), RF_S2LP_GPIO1(spi_gpio1), RF_S2LP_GPIO2(spi_gpio2), @@ -169,6 +149,25 @@ RFPins::RFPins(PinName spi_sdi, PinName spi_sdo, irq_thread.start(mbed::callback(this, &RFPins::rf_irq_task)); } +class TestPins_S2LP { +public: + TestPins_S2LP(PinName test_pin_1, PinName test_pin_2, PinName test_pin_3, PinName test_pin_4, PinName test_pin_5); + DigitalOut TEST1; + DigitalOut TEST2; + DigitalOut TEST3; + DigitalOut TEST4; + DigitalOut TEST5; +}; + +TestPins_S2LP::TestPins_S2LP(PinName test_pin_1, PinName test_pin_2, PinName test_pin_3, PinName test_pin_4, PinName test_pin_5) + : TEST1(test_pin_1), + TEST2(test_pin_2), + TEST3(test_pin_3), + TEST4(test_pin_4), + TEST5(test_pin_5) +{ +} + static uint8_t rf_read_register(uint8_t addr); static s2lp_states_e rf_read_state(void); static void rf_write_register(uint8_t addr, uint8_t data); @@ -183,6 +182,7 @@ static bool rf_rx_filter(uint8_t *mac_header, uint8_t *mac_64bit_addr, uint8_t * static void rf_cca_timer_start(uint32_t slots); static RFPins *rf; +static TestPins_S2LP *test_pins; static phy_device_driver_s device_driver; static int8_t rf_radio_driver_id = -1; static uint8_t *tx_data_ptr; @@ -246,20 +246,20 @@ static void rf_irq_task_process_irq(); #define ACK_SENDING_TIME (uint32_t)(8000000/phy_subghz.datarate)*ACK_FRAME_LENGTH + PACKET_SENDING_EXTRA_TIME #ifdef TEST_GPIOS_ENABLED -void test1_toggle(void) +static void test1_toggle(void) { - if (rf->TEST4) { - rf->TEST4 = 0; + if (test_pins->TEST4) { + test_pins->TEST4 = 0; } else { - rf->TEST4 = 1; + test_pins->TEST4 = 1; } } -void test2_toggle(void) +static void test2_toggle(void) { - if (rf->TEST5) { - rf->TEST5 = 0; + if (test_pins->TEST5) { + test_pins->TEST5 = 0; } else { - rf->TEST5 = 1; + test_pins->TEST5 = 1; } } #endif //TEST_GPIOS_ENABLED @@ -749,19 +749,18 @@ static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_ static void rf_tx_sent_handler(void) { + TEST_TX_DONE rf_backup_timer_stop(); rf_disable_interrupt(TX_DATA_SENT); if (rf_state != RF_TX_ACK) { tx_finnish_time = rf_get_timestamp(); rf_update_tx_active_time(); - TEST_TX_DONE rf_state = RF_IDLE; rf_receive(rf_rx_channel); if (device_driver.phy_tx_done_cb) { device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 0, 0); } } else { - TEST_ACK_TX_DONE rf_receive(rf_rx_channel); } } @@ -807,6 +806,7 @@ static int rf_cca_check(void) static void rf_cca_timer_interrupt(void) { + TEST_CSMA_DONE int8_t status = device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_PREPARE, 0, 0); if (status == PHY_TX_NOT_ALLOWED) { rf_flush_tx_fifo(); @@ -851,12 +851,14 @@ static void rf_cca_timer_interrupt(void) static void rf_cca_timer_stop(void) { + TEST_CSMA_DONE rf->cca_timer.detach(); } static void rf_cca_timer_start(uint32_t slots) { rf->cca_timer.attach_us(rf_cca_timer_signal, slots); + TEST_CSMA_STARTED } static void rf_backup_timer_interrupt(void) @@ -941,7 +943,7 @@ static void rf_send_ack(uint8_t seq) rf_write_packet_length(sizeof(ack_frame) + 4); tx_data_ptr = NULL; rf_start_tx(); - TEST_ACK_TX_STARTED + TEST_TX_STARTED rf_backup_timer_start(ACK_SENDING_TIME); if (device_driver.phy_rf_statistics) { device_driver.phy_rf_statistics->tx_bytes += sizeof(ack_frame); @@ -1278,6 +1280,7 @@ int8_t NanostackRfPhys2lp::rf_register() } rf = _rf; + test_pins = _test_pins; int8_t radio_id = rf_device_register(_mac_addr); if (radio_id < 0) { @@ -1300,9 +1303,6 @@ void NanostackRfPhys2lp::rf_unregister() } NanostackRfPhys2lp::NanostackRfPhys2lp(PinName spi_sdi, PinName spi_sdo, PinName spi_sclk, PinName spi_cs, PinName spi_sdn -#ifdef TEST_GPIOS_ENABLED - ,PinName spi_test1, PinName spi_test2, PinName spi_test3, PinName spi_test4, PinName spi_test5 -#endif //TEST_GPIOS_ENABLED ,PinName spi_gpio0, PinName spi_gpio1, PinName spi_gpio2, PinName spi_gpio3 #ifdef AT24MAC ,PinName i2c_sda, PinName i2c_scl @@ -1314,16 +1314,12 @@ NanostackRfPhys2lp::NanostackRfPhys2lp(PinName spi_sdi, PinName spi_sdo, PinName #endif //AT24MAC _mac_addr(), _rf(NULL), _mac_set(false), _spi_sdi(spi_sdi), _spi_sdo(spi_sdo), _spi_sclk(spi_sclk), _spi_cs(spi_cs), _spi_sdn(spi_sdn), -#ifdef TEST_GPIOS_ENABLED - _spi_test1(spi_test1), _spi_test2(spi_test2), _spi_test3(spi_test3), _spi_test4(spi_test4), _spi_test5(spi_test5), -#endif //TEST_GPIOS_ENABLED _spi_gpio0(spi_gpio0), _spi_gpio1(spi_gpio1), _spi_gpio2(spi_gpio2), _spi_gpio3(spi_gpio3) { - _rf = new RFPins(_spi_sdi, _spi_sdo, _spi_sclk, _spi_cs, _spi_sdn, + _rf = new RFPins(_spi_sdi, _spi_sdo, _spi_sclk, _spi_cs, _spi_sdn, _spi_gpio0, _spi_gpio1, _spi_gpio2, _spi_gpio3); #ifdef TEST_GPIOS_ENABLED - _spi_test1, _spi_test2, _spi_test3, _spi_test4, _spi_test5, + _test_pins = new TestPins_S2LP(TEST_PIN_TX, TEST_PIN_RX, TEST_PIN_CSMA, TEST_PIN_SPARE_1, TEST_PIN_SPARE_2); #endif //TEST_GPIOS_ENABLED - _spi_gpio0, _spi_gpio1, _spi_gpio2, _spi_gpio3); } NanostackRfPhys2lp::~NanostackRfPhys2lp() @@ -1428,9 +1424,6 @@ static bool rf_rx_filter(uint8_t *mac_header, uint8_t *mac_64bit_addr, uint8_t * NanostackRfPhy &NanostackRfPhy::get_default_instance() { static NanostackRfPhys2lp rf_phy(S2LP_SPI_SDI, S2LP_SPI_SDO, S2LP_SPI_SCLK, S2LP_SPI_CS, S2LP_SPI_SDN -#ifdef TEST_GPIOS_ENABLED - ,S2LP_SPI_TEST1, S2LP_SPI_TEST2, S2LP_SPI_TEST3, S2LP_SPI_TEST4, S2LP_SPI_TEST5 -#endif //TEST_GPIOS_ENABLED ,S2LP_SPI_GPIO0, S2LP_SPI_GPIO1, S2LP_SPI_GPIO2, S2LP_SPI_GPIO3 #ifdef AT24MAC ,S2LP_I2C_SDA, S2LP_I2C_SCL diff --git a/components/802.15.4_RF/stm-s2lp-rf-driver/stm-s2lp-rf-driver/NanostackRfPhys2lp.h b/components/802.15.4_RF/stm-s2lp-rf-driver/stm-s2lp-rf-driver/NanostackRfPhys2lp.h index 66e0701174..2b9038a84e 100644 --- a/components/802.15.4_RF/stm-s2lp-rf-driver/stm-s2lp-rf-driver/NanostackRfPhys2lp.h +++ b/components/802.15.4_RF/stm-s2lp-rf-driver/stm-s2lp-rf-driver/NanostackRfPhys2lp.h @@ -26,98 +26,96 @@ #include "SPI.h" // Uncomment to use testing gpios attached to TX/RX processes -//#define TEST_GPIOS_ENABLED +// #define TEST_GPIOS_ENABLED #if defined(TARGET_MTB_STM_S2LP) #if !defined(S2LP_SPI_SDI) -#define S2LP_SPI_SDI PA_7 +#define S2LP_SPI_SDI PA_7 #endif #if !defined(S2LP_SPI_SDO) -#define S2LP_SPI_SDO PA_6 +#define S2LP_SPI_SDO PA_6 #endif #if !defined(S2LP_SPI_SCLK) -#define S2LP_SPI_SCLK PA_5 +#define S2LP_SPI_SCLK PA_5 #endif #if !defined(S2LP_SPI_CS) -#define S2LP_SPI_CS PC_0 +#define S2LP_SPI_CS PC_0 #endif #if !defined(S2LP_SPI_SDN) -#define S2LP_SPI_SDN PF_13 +#define S2LP_SPI_SDN PF_13 #endif #if !defined(S2LP_SPI_GPIO0) -#define S2LP_SPI_GPIO0 PA_3 +#define S2LP_SPI_GPIO0 PA_3 #endif #if !defined(S2LP_SPI_GPIO1) -#define S2LP_SPI_GPIO1 PC_3 +#define S2LP_SPI_GPIO1 PC_3 #endif #if !defined(S2LP_SPI_GPIO2) -#define S2LP_SPI_GPIO2 PF_3 +#define S2LP_SPI_GPIO2 PF_3 #endif #if !defined(S2LP_SPI_GPIO3) -#define S2LP_SPI_GPIO3 PF_10 +#define S2LP_SPI_GPIO3 PF_10 #endif #if !defined(S2LP_I2C_SDA) -#define S2LP_I2C_SDA PB_7 +#define S2LP_I2C_SDA PB_7 #endif #if !defined(S2LP_I2C_SCL) -#define S2LP_I2C_SCL PB_6 +#define S2LP_I2C_SCL PB_6 #endif #define AT24MAC #else #if !defined(S2LP_SPI_SDI) -#define S2LP_SPI_SDI D11 +#define S2LP_SPI_SDI D11 #endif #if !defined(S2LP_SPI_SDO) -#define S2LP_SPI_SDO D12 +#define S2LP_SPI_SDO D12 #endif #if !defined(S2LP_SPI_SCLK) -#define S2LP_SPI_SCLK D13 +#define S2LP_SPI_SCLK D13 #endif #if !defined(S2LP_SPI_CS) -#define S2LP_SPI_CS A1 +#define S2LP_SPI_CS A1 #endif #if !defined(S2LP_SPI_SDN) -#define S2LP_SPI_SDN D7 +#define S2LP_SPI_SDN D7 #endif -#if !defined(S2LP_SPI_TEST1) -#define S2LP_SPI_TEST1 D6 +#if !defined(TEST_PIN_TX) +#define TEST_PIN_TX D6 #endif -#if !defined(S2LP_SPI_TEST2) -#define S2LP_SPI_TEST2 D5 +#if !defined(TEST_PIN_RX) +#define TEST_PIN_RX D5 #endif -#if !defined(S2LP_SPI_TEST3) -#define S2LP_SPI_TEST3 D4 +#if !defined(TEST_PIN_CSMA) +#define TEST_PIN_CSMA D4 #endif -#if !defined(S2LP_SPI_TEST4) -#define S2LP_SPI_TEST4 D2 +#if !defined(TEST_PIN_SPARE_1) +#define TEST_PIN_SPARE_1 D2 #endif -#if !defined(S2LP_SPI_TEST5) -#define S2LP_SPI_TEST5 D8 +#if !defined(TEST_PIN_SPARE_2) +#define TEST_PIN_SPARE_2 D8 #endif #if !defined(S2LP_SPI_GPIO0) -#define S2LP_SPI_GPIO0 A0 +#define S2LP_SPI_GPIO0 A0 #endif #if !defined(S2LP_SPI_GPIO1) -#define S2LP_SPI_GPIO1 A2 +#define S2LP_SPI_GPIO1 A2 #endif #if !defined(S2LP_SPI_GPIO2) -#define S2LP_SPI_GPIO2 A3 +#define S2LP_SPI_GPIO2 A3 #endif #if !defined(S2LP_SPI_GPIO3) -#define S2LP_SPI_GPIO3 A5 +#define S2LP_SPI_GPIO3 A5 #endif #endif #include "at24mac_s2lp.h" class RFPins; +class TestPins_S2LP; class NanostackRfPhys2lp : public NanostackRfPhy { public: NanostackRfPhys2lp(PinName spi_sdi, PinName spi_sdo, PinName spi_sclk, PinName spi_cs, PinName spi_sdn -#ifdef TEST_GPIOS_ENABLED - ,PinName spi_test1, PinName spi_test2, PinName spi_test3, PinName spi_test4, PinName spi_test5 -#endif //TEST_GPIOS_ENABLED ,PinName spi_gpio0, PinName spi_gpio1, PinName spi_gpio2, PinName spi_gpio3 #ifdef AT24MAC ,PinName i2c_sda, PinName i2c_scl @@ -135,6 +133,7 @@ private: #endif //AT24MAC uint8_t _mac_addr[8]; RFPins *_rf; + TestPins_S2LP *_test_pins; bool _mac_set; const PinName _spi_sdi; @@ -142,13 +141,6 @@ private: const PinName _spi_sclk; const PinName _spi_cs; const PinName _spi_sdn; -#ifdef TEST_GPIOS_ENABLED - const PinName _spi_test1; - const PinName _spi_test2; - const PinName _spi_test3; - const PinName _spi_test4; - const PinName _spi_test5; -#endif //TEST_GPIOS_ENABLED const PinName _spi_gpio0; const PinName _spi_gpio1; const PinName _spi_gpio2; From 13f5df4b8b59db83d9b7d566674585aa04827e05 Mon Sep 17 00:00:00 2001 From: Arto Kinnunen Date: Fri, 3 Apr 2020 15:23:11 +0300 Subject: [PATCH 49/49] Update Atmel 802.15.4 RF driver Update to version v3.1.0. --- .../atmel-rf-driver/NanostackRfPhyAtmel.h | 46 + .../atmel-rf-driver/source/AT86RF215Reg.h | 262 ++++ .../atmel-rf-driver/source/AT86RFReg.h | 1 + .../source/NanostackRfPhyAT86RF215.cpp | 1103 +++++++++++++++++ .../source/NanostackRfPhyAtmel.cpp | 87 +- .../atmel-rf-driver/source/rfbits.h | 73 ++ 6 files changed, 1536 insertions(+), 36 deletions(-) create mode 100644 components/802.15.4_RF/atmel-rf-driver/source/AT86RF215Reg.h create mode 100644 components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAT86RF215.cpp create mode 100644 components/802.15.4_RF/atmel-rf-driver/source/rfbits.h diff --git a/components/802.15.4_RF/atmel-rf-driver/atmel-rf-driver/NanostackRfPhyAtmel.h b/components/802.15.4_RF/atmel-rf-driver/atmel-rf-driver/NanostackRfPhyAtmel.h index a5e6baa70e..028663f63e 100644 --- a/components/802.15.4_RF/atmel-rf-driver/atmel-rf-driver/NanostackRfPhyAtmel.h +++ b/components/802.15.4_RF/atmel-rf-driver/atmel-rf-driver/NanostackRfPhyAtmel.h @@ -24,6 +24,9 @@ #include "NanostackRfPhy.h" +// Uncomment to use testing gpios attached to TX/RX processes +// #define TEST_GPIOS_ENABLED + // Arduino pin defaults for convenience #if !defined(ATMEL_SPI_MOSI) #define ATMEL_SPI_MOSI D11 @@ -52,8 +55,24 @@ #if !defined(ATMEL_I2C_SCL) #define ATMEL_I2C_SCL D15 #endif +#if !defined(TEST_PIN_TX) +#define TEST_PIN_TX D6 +#endif +#if !defined(TEST_PIN_RX) +#define TEST_PIN_RX D3 +#endif +#if !defined(TEST_PIN_CSMA) +#define TEST_PIN_CSMA D4 +#endif +#if !defined(TEST_PIN_SPARE_1) +#define TEST_PIN_SPARE_1 D2 +#endif +#if !defined(TEST_PIN_SPARE_2) +#define TEST_PIN_SPARE_2 D8 +#endif class RFBits; +class TestPins; class NanostackRfPhyAtmel : public NanostackRfPhy { public: @@ -70,6 +89,7 @@ private: AT24Mac _mac; uint8_t _mac_addr[8]; RFBits *_rf; + TestPins *_test_pins; bool _mac_set; const PinName _spi_mosi; @@ -81,5 +101,31 @@ private: const PinName _spi_irq; }; +#ifdef TEST_GPIOS_ENABLED +#define TEST_TX_STARTED test_pins->TEST1 = 1; +#define TEST_TX_DONE test_pins->TEST1 = 0; +#define TEST_RX_STARTED test_pins->TEST2 = 1; +#define TEST_RX_DONE test_pins->TEST2 = 0; +#define TEST_CSMA_STARTED test_pins->TEST3 = 1; +#define TEST_CSMA_DONE test_pins->TEST3 = 0; +#define TEST_SPARE_1_ON test_pins->TEST4 = 1; +#define TEST_SPARE_1_OFF test_pins->TEST4 = 0; +#define TEST_SPARE_2_ON test_pins->TEST5 = 1; +#define TEST_SPARE_2_OFF test_pins->TEST5 = 0; +extern void (*fhss_uc_switch)(void); +extern void (*fhss_bc_switch)(void); +#else +#define TEST_TX_STARTED +#define TEST_TX_DONE +#define TEST_RX_STARTED +#define TEST_RX_DONE +#define TEST_CSMA_STARTED +#define TEST_CSMA_DONE +#define TEST_SPARE_1_ON +#define TEST_SPARE_1_OFF +#define TEST_SPARE_2_ON +#define TEST_SPARE_2_OFF +#endif //TEST_GPIOS_ENABLED + #endif /* MBED_CONF_NANOSTACK_CONFIGURATION */ #endif /* NANOSTACK_RF_PHY_ATMEL_H_ */ diff --git a/components/802.15.4_RF/atmel-rf-driver/source/AT86RF215Reg.h b/components/802.15.4_RF/atmel-rf-driver/source/AT86RF215Reg.h new file mode 100644 index 0000000000..5463570f14 --- /dev/null +++ b/components/802.15.4_RF/atmel-rf-driver/source/AT86RF215Reg.h @@ -0,0 +1,262 @@ +/* + * Copyright (c) 2020 ARM Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef AT86RF215REG_H_ +#define AT86RF215REG_H_ +#ifdef __cplusplus +extern "C" { +#endif + + +/*Register addresses*/ +#define RF09_IRQS 0x00 +#define RF24_IRQS 0x01 +#define BBC0_IRQS 0x02 +#define BBC1_IRQS 0x03 +#define RF_CFG 0x06 +#define RF_IQIFC1 0x0B +#define RF_PN 0x0D +#define RF_VN 0x0E +#define RF_IRQM 0x00 +#define RF_STATE 0x02 +#define RF_CMD 0x03 +#define RF_CS 0x04 +#define RF_CCF0L 0x05 +#define RF_CCF0H 0x06 +#define RF_CNL 0x07 +#define RF_CNM 0x08 +#define RF_RXBWC 0x09 +#define RF_RXDFE 0x0A +#define RF_AGCC 0x0B +#define RF_AGCS 0x0C +#define RF_RSSI 0x0D +#define RF_EDC 0x0E +#define RF_EDV 0x10 +#define RF_TXCUTC 0x12 +#define RF_TXDFE 0x13 +#define BBC_IRQM 0x00 +#define BBC_PC 0x01 +#define BBC_RXFLL 0x04 +#define BBC_RXFLH 0x05 +#define BBC_TXFLL 0x06 +#define BBC_TXFLH 0x07 +#define BBC_FBLL 0x08 +#define BBC_FBLH 0x09 +#define BBC_OQPSKC0 0x10 +#define BBC_OQPSKC1 0x11 +#define BBC_OQPSKC2 0x12 +#define BBC_OQPSKC3 0x13 +#define BBC_OQPSKPHRTX 0x14 +#define BBC_OQPSKPHRRX 0x15 +#define BBC_AFC0 0x20 +#define BBC_AFFTM 0x22 +#define BBC_MACEA0 0x25 +#define BBC_MACPID0F0 0x2D +#define BBC_MACSHA0F0 0x2F +#define BBC_AMCS 0x40 +#define BBC_AMEDT 0x41 +#define BBC_AMAACKTL 0x43 +#define BBC_AMAACKTH 0x44 +#define BBC_FSKC0 0x60 +#define BBC_FSKC1 0x61 +#define BBC_FSKC2 0x62 +#define BBC_FSKC3 0x63 +#define BBC_FSKPLL 0x65 +#define BBC_FSKPHRTX 0x6A +#define BBC_FSKPHRRX 0x6B +#define BBC0_FBRXS 0x2000 +#define BBC0_FBTXS 0x2800 +#define BBC1_FBRXS 0x3000 +#define BBC1_FBTXS 0x3800 + +// RF_AGCC +#define AGCI (1 << 6) +#define AVGS 0x30 +#define AVGS_8_SAMPLES (0 << 4) + +// RF_AGCS +#define TGT 0xE0 +#define TGT_1 (1 << 5) + + +// RF_RXBWC +#define BW 0x0F +#define RF_BW2000KHZ_IF2000KHZ (11 << 0) +#define RF_BW1600KHZ_IF2000KHZ (10 << 0) +#define RF_BW1250KHZ_IF2000KHZ (9 << 0) +#define RF_BW1000KHZ_IF1000KHZ (8 << 0) +#define RF_BW800KHZ_IF1000KHZ (7 << 0) +#define RF_BW630KHZ_IF1000KHZ (6 << 0) +#define RF_BW500KHZ_IF500KHZ (5 << 0) +#define RF_BW400KHZ_IF500KHZ (4 << 0) +#define RF_BW320KHZ_IF500KHZ (3 << 0) +#define RF_BW250KHZ_IF250KHZ (2 << 0) +#define RF_BW200KHZ_IF250KHZ (1 << 0) +#define RF_BW160KHZ_IF250KHZ (0 << 0) +#define IFS (1 << 4) + +// RF_TXCUTC +#define PARAMP 0xC0 +#define RF_PARAMP32U (3 << 6) +#define RF_PARAMP16U (2 << 6) +#define RF_PARAMP8U (1 << 6) +#define RF_PARAMP4U (0 << 6) +#define LPFCUT 0x0F +#define RF_FLC80KHZ (0 << 0) +#define RF_FLC100KHZ (1 << 0) +#define RF_FLC125KHZ (2 << 0) +#define RF_FLC160KHZ (3 << 0) +#define RF_FLC200KHZ (4 << 0) +#define RF_FLC250KHZ (5 << 0) +#define RF_FLC315KHZ (6 << 0) +#define RF_FLC400KHZ (7 << 0) +#define RF_FLC500KHZ (8 << 0) +#define RF_FLC625KHZ (9 << 0) +#define RF_FLC800KHZ (10 << 0) +#define RF_FLC1000KHZ (11 << 0) + +// RF_TXDFE, RF_RXDFE +#define RCUT 0xE0 +#define RCUT_4 (4 << 5) +#define RCUT_2 (2 << 5) +#define RCUT_1 (1 << 5) +#define RCUT_0 (0 << 5) +#define SR 0x0F +#define SR_10 (10 << 0) +#define SR_8 (8 << 0) +#define SR_6 (6 << 0) +#define SR_5 (5 << 0) +#define SR_4 (4 << 0) +#define SR_3 (3 << 0) +#define SR_2 (2 << 0) +#define SR_1 (1 << 0) + +// BBC_FSKC0 +#define BT 0xC0 +#define BT_20 (3 << 6) +#define BT_10 (1 << 6) +#define MIDXS 0x30 +#define MIDXS_0 (0 << 4) +#define MIDX 0x0E +#define MIDX_10 (3 << 1) +#define MIDX_075 (2 << 1) +#define MIDX_05 (1 << 1) +#define MIDX_0375 (0 << 1) + +// BBC_FSKC1 +#define SRATE 0x0F +#define SRATE_400KHZ (5 << 0) +#define SRATE_300KHZ (4 << 0) +#define SRATE_200KHZ (3 << 0) +#define SRATE_150KHZ (2 << 0) +#define SRATE_100KHZ (1 << 0) +#define SRATE_50KHZ (0 << 0) + +// BBC_FSKC2 +#define RXO 0x60 +#define RXO_DIS (0 << 5) +#define FECIE (1 << 0) + +// BBC_FSKC3 +#define SFDT 0xF0 +#define PDT 0x0F +#define PDT_6 (6 << 0) + +// BBC_AFFTM +#define TYPE_2 (1 << 2) + +// BBC_AFC0 +#define PM (1 << 4) +#define AFEN3 (1 << 3) +#define AFEN2 (1 << 2) +#define AFEN1 (1 << 1) +#define AFEN0 (1 << 0) + +// BBC_OQPSKPHRTX +#define LEG (1 << 0) + +// BBC_OQPSKC0 +#define FCHIP 0x03 +#define BB_FCHIP100 (0 << 0) +#define BB_FCHIP200 (1 << 0) +#define BB_FCHIP1000 (2 << 0) +#define BB_FCHIP2000 (3 << 0) + +// BBC_OQPSKC2 +#define FCSTLEG 0x04 +#define RXM 0x03 +#define FCS_16 (1 << 2) +#define RXM_2 (2 << 0) + +// BBC_IRQS, BBC_IRQM +#define FBLI (1 << 7) +#define AGCR (1 << 6) +#define AGCH (1 << 5) +#define TXFE (1 << 4) +#define RXEM (1 << 3) +#define RXAM (1 << 2) +#define RXFE (1 << 1) +#define RXFS (1 << 0) + +//BBC_PC +#define BBEN (1 << 2) +#define PT 0x03 +#define BB_PHYOFF (0 << 0) +#define BB_MRFSK (1 << 0) +#define BB_MROFDM (2 << 0) +#define BB_MROQPSK (3 << 0) +#define FCSOK (1 << 5) +#define TXAFCS (1 << 4) +#define FCST (1 << 3) +#define FCSFE (1 << 6) + +//BBC_AMCS +#define AACKFT (1 << 7) +#define AACK (1 << 3) +#define CCAED (1 << 2) + +// RF_IQIFC1 +#define CHPM 0x70 +#define RF_MODE_BBRF (0 << 4) +#define RF_MODE_RF (1 << 4) +#define RF_MODE_BBRF09 (4 << 4) +#define RF_MODE_BBRF24 (5 << 4) + +/*RF_CFG bits*/ +#define IRQMM 0x08 +#define IRQP 0x04 + +/*RFn_IRQM bits*/ +#define TRXRDY (1 << 1) +#define EDC (1 << 2) + +/*RFn_EDC bits*/ +#define EDM 0x03 +#define RF_EDAUTO (0 << 0) +#define RF_EDSINGLE (1 << 0) +#define RF_EDCONT (2 << 0) +#define RF_EDOFF (3 << 0) + +/*Masks*/ +#define CNH 0x01 +#define EDM 0x03 +#define CHPM 0x70 + +#ifdef __cplusplus +} +#endif + +#endif /* AT86RF215REG_H_ */ diff --git a/components/802.15.4_RF/atmel-rf-driver/source/AT86RFReg.h b/components/802.15.4_RF/atmel-rf-driver/source/AT86RFReg.h index a1b9c24870..c53d9fe922 100644 --- a/components/802.15.4_RF/atmel-rf-driver/source/AT86RFReg.h +++ b/components/802.15.4_RF/atmel-rf-driver/source/AT86RFReg.h @@ -47,6 +47,7 @@ extern "C" { #define PART_AT86RF231 0x03 #define PART_AT86RF212 0x07 #define PART_AT86RF233 0x0B +#define PART_AT86RF215 0x34 #define VERSION_AT86RF212 0x01 #define VERSION_AT86RF212B 0x03 diff --git a/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAT86RF215.cpp b/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAT86RF215.cpp new file mode 100644 index 0000000000..09c3180010 --- /dev/null +++ b/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAT86RF215.cpp @@ -0,0 +1,1103 @@ +/* + * Copyright (c) 2020 ARM Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#if defined(MBED_CONF_NANOSTACK_CONFIGURATION) && DEVICE_SPI && DEVICE_INTERRUPTIN && defined(MBED_CONF_RTOS_PRESENT) + +#include "ns_types.h" +#include "platform/arm_hal_interrupt.h" +#include "platform/mbed_wait_api.h" +#include "nanostack/platform/arm_hal_phy.h" +#include "NanostackRfPhyAtmel.h" +#include "AT86RF215Reg.h" +#include "mbed_trace.h" +#include "common_functions.h" +#include +#include "Timeout.h" +#include "SPI.h" + +#define TRACE_GROUP "AtRF" + +#define RF_MTU_15_4_2011 127 +#define RF_MTU_15_4G_2012 2047 + +namespace { + +typedef enum { + RF_NOP = 0x00, + RF_SLEEP = 0x01, + RF_TRX_OFF = 0x02, + RF_TXPREP = 0x03, + RF_TX = 0x04, + RF_RX = 0x05, + RF_TRANSITION = 0x06, + RF_RESET = 0x07 +} rf_command_e; + +typedef enum { + COMMON = 0x00, + RF_09 = 0x01, + RF_24 = 0x02, + BBC0 = 0x03, + BBC1 = 0x04 +} rf_modules_e; + +typedef enum { + RF_IDLE, + RF_CSMA_STARTED, + RF_CSMA_WHILE_RX, + RF_TX_STARTED, + RF_RX_STARTED +} rf_states_e; + +} // anonymous namespace + +static void rf_init(void); +static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr); +static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr); +static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel); +static int8_t rf_start_csma_ca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol); +static void rf_init_registers(rf_modules_e module); +static void rf_spi_exchange(const void *tx, size_t tx_len, void *rx, size_t rx_len); +static uint8_t rf_read_rf_register(uint8_t addr, rf_modules_e module); +static void rf_write_rf_register(uint8_t addr, rf_modules_e module, uint8_t data); +static void rf_write_rf_register_field(uint8_t addr, rf_modules_e module, uint8_t field, uint8_t value); +static void rf_write_tx_packet_length(uint16_t packet_length, rf_modules_e module); +static uint16_t rf_read_rx_frame_length(rf_modules_e module); +static void rf_write_tx_buffer(uint8_t *data, uint16_t len, rf_modules_e module); +static int rf_read_rx_buffer(uint16_t length, rf_modules_e module); +static void rf_irq_rf_enable(uint8_t irq, rf_modules_e module); +static void rf_irq_rf_disable(uint8_t irq, rf_modules_e module); +static void rf_irq_bbc_enable(uint8_t irq, rf_modules_e module); +static void rf_irq_bbc_disable(uint8_t irq, rf_modules_e module); +static rf_command_e rf_read_state(rf_modules_e module); +static void rf_poll_state_change(rf_command_e state, rf_modules_e module); +static void rf_change_state(rf_command_e state, rf_modules_e module); +static void rf_receive(uint16_t rx_channel, rf_modules_e module); +static void rf_interrupt_handler(void); +static void rf_irq_task_process_irq(void); +static void rf_handle_cca_ed_done(void); +static void rf_start_tx(void); +static void rf_backup_timer_interrupt(void); +static void rf_backup_timer_stop(void); +static uint32_t rf_backup_timer_start(uint16_t bytes, uint32_t time_us); +static int rf_set_channel(uint16_t channel, rf_modules_e module); +static int rf_set_ch0_frequency(uint32_t frequency, rf_modules_e module); +static int rf_set_channel_spacing(uint32_t channel_spacing, rf_modules_e module); +static int rf_set_fsk_symbol_rate_configuration(uint32_t symbol_rate, rf_modules_e module); +static void rf_calculate_symbol_rate(uint32_t baudrate, phy_modulation_e modulation); +static void rf_conf_set_cca_threshold(uint8_t percent); +// Defined register read/write functions +#define rf_read_bbc_register(x, y) rf_read_rf_register(x, (rf_modules_e)(y + 2)) +#define rf_read_common_register(x) rf_read_rf_register(x, COMMON) +#define rf_write_bbc_register(x, y, z) rf_write_rf_register(x, (rf_modules_e)(y + 2), z) +#define rf_write_common_register(x, z) rf_write_rf_register(x, COMMON, z) +#define rf_write_bbc_register_field(v, x, y, z) rf_write_rf_register_field(v, (rf_modules_e)(x + 2), y, z) +#define rf_write_common_register_field(v, y, z) rf_write_rf_register_field(v, COMMON, y, z) + +static int8_t rf_radio_driver_id = -1; +static phy_device_driver_s device_driver; +static uint8_t rf_version_num = 0; +static rf_modules_e rf_module = RF_24; +static phy_802_15_4_mode_t mac_mode = IEEE_802_15_4_2011; +static uint8_t mac_tx_handle = 0; +static rf_states_e rf_state = RF_IDLE; +static bool receiver_enabled = false; +static int8_t cca_prepare_status = PHY_TX_NOT_ALLOWED; +static uint8_t rx_buffer[RF_MTU_15_4G_2012]; +static uint8_t rf_rx_channel; +static uint16_t tx_sequence = 0xffff; +static uint16_t cur_tx_packet_len = 0xffff; +static uint16_t cur_rx_packet_len = 0xffff; +static uint32_t cur_rx_stop_time = 0; +static uint32_t tx_time = 0; +static uint32_t rx_time = 0; +static uint8_t rf09_irq_mask = 0; +static uint8_t rf24_irq_mask = 0; +static uint8_t bbc0_irq_mask = 0; +static uint8_t bbc1_irq_mask = 0; + +static bool rf_update_config = false; +static int8_t cca_threshold = -80; +static bool cca_enabled = true; +static uint32_t rf_symbol_rate; + +/* Channel configurations for 2.4 and sub-GHz */ +static const phy_rf_channel_configuration_s phy_24ghz = {.channel_0_center_frequency = 2350000000U, + .channel_spacing = 5000000U, + .datarate = 250000U, + .number_of_channels = 16U, + .modulation = M_OQPSK + }; +static const phy_rf_channel_configuration_s phy_subghz = {.channel_0_center_frequency = 868300000U, + .channel_spacing = 2000000U, + .datarate = 250000U, + .number_of_channels = 11U, + .modulation = M_OQPSK + }; + +static phy_rf_channel_configuration_s phy_current_config; + +static const phy_device_channel_page_s phy_channel_pages[] = { + { CHANNEL_PAGE_0, &phy_24ghz}, + { CHANNEL_PAGE_2, &phy_subghz}, + { CHANNEL_PAGE_0, NULL} +}; + +using namespace mbed; +using namespace rtos; + +#include "rfbits.h" +static RFBits *rf; +static TestPins *test_pins; + +#define MAC_FRAME_TYPE_MASK 0x07 +#define MAC_TYPE_ACK (2) +#define MAC_DATA_PENDING 0x10 +#define FC_AR 0x20 +#define VERSION_FIELD_MASK 0x30 +#define SHIFT_VERSION_FIELD (4) + +#define SIG_RADIO 1 +#define SIG_TIMER_BACKUP 2 +#define SIG_TIMER_CCA 4 +#define SIG_TIMERS (SIG_TIMER_BACKUP|SIG_TIMER_CCA) +#define SIG_ALL (SIG_RADIO|SIG_TIMERS) + +#define ACK_FRAME_LENGTH 3 +#define PACKET_PROCESSING_TIME 5000 +#define MAX_STATE_TRANSITION_TIME_US 1000 +#define CCA_BACKUP_TIMEOUT 1000 +#define MAX_TRANSMISSION_TIME 1000000 + +#define MIN_CCA_THRESHOLD -117 +#define MAX_CCA_THRESHOLD -5 + +static uint32_t rf_get_timestamp(void) +{ + return (uint32_t)rf->tx_timer.read_us(); +} + +static void rf_lock(void) +{ + platform_enter_critical(); +} + +static void rf_unlock(void) +{ + platform_exit_critical(); +} + +static int8_t rf_device_register(const uint8_t *mac_addr) +{ + rf_init(); + device_driver.PHY_MAC = (uint8_t *)mac_addr; + device_driver.driver_description = (char *)"ATMEL_MAC"; + device_driver.link_type = PHY_LINK_15_4_2_4GHZ_TYPE; + device_driver.phy_channel_pages = phy_channel_pages; + device_driver.phy_MTU = RF_MTU_15_4G_2012; + device_driver.phy_header_length = 0; + device_driver.phy_tail_length = 0; + device_driver.address_write = &rf_address_write; + device_driver.extension = &rf_extension; + device_driver.state_control = &rf_interface_state_control; + device_driver.tx = &rf_start_csma_ca; + device_driver.phy_rx_cb = NULL; + device_driver.phy_tx_done_cb = NULL; + rf_radio_driver_id = arm_net_phy_register(&device_driver); + rf_update_config = true; + return rf_radio_driver_id; +} + +static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address_ptr) +{ + uint8_t rf_address = 0, addr_size = 0; + switch (address_type) { + case PHY_MAC_48BIT: + break; + case PHY_MAC_64BIT: + rf_address = BBC_MACEA0; + addr_size = 8; + break; + case PHY_MAC_16BIT: + rf_address = BBC_MACSHA0F0; + addr_size = 2; + break; + case PHY_MAC_PANID: + rf_address = BBC_MACPID0F0; + addr_size = 2; + break; + } + for (uint8_t i = 0; i < addr_size; i++) { + rf_write_bbc_register(rf_address++, rf_module, address_ptr[(addr_size - 1) - i]); + } + return 0; +} + +static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_ptr) +{ + phy_csma_params_t *csma_params; + uint32_t *timer_value; + switch (extension_type) { + case PHY_EXTENSION_SET_CHANNEL: + if (rf_state == RF_IDLE || (rf_state == RF_CSMA_STARTED && !(rf_read_rf_register(RF_EDC, rf_module) & RF_EDSINGLE))) { + rf_receive(*data_ptr, rf_module); + } else { + return -1; + } + break; + case PHY_EXTENSION_READ_RX_TIME: + common_write_32_bit(rx_time, data_ptr); + break; + case PHY_EXTENSION_GET_TIMESTAMP: + timer_value = (uint32_t *)data_ptr; + *timer_value = rf_get_timestamp(); + break; + case PHY_EXTENSION_SET_CSMA_PARAMETERS: + csma_params = (phy_csma_params_t *)data_ptr; + if (csma_params->backoff_time == 0) { + TEST_CSMA_DONE + rf->cca_timer.detach(); + if (rf_state == RF_TX_STARTED) { + rf_state = RF_IDLE; + rf_receive(rf_rx_channel, rf_module); + } + tx_time = 0; + } else { + tx_time = csma_params->backoff_time; + cca_enabled = csma_params->cca_enabled; + } + break; + case PHY_EXTENSION_GET_SYMBOLS_PER_SECOND: + timer_value = (uint32_t *)data_ptr; + *timer_value = rf_symbol_rate; + break; + case PHY_EXTENSION_DYNAMIC_RF_SUPPORTED: + *data_ptr = true; + break; + case PHY_EXTENSION_SET_RF_CONFIGURATION: + memcpy(&phy_current_config, data_ptr, sizeof(phy_rf_channel_configuration_s)); + rf_calculate_symbol_rate(phy_current_config.datarate, phy_current_config.modulation); + rf_update_config = true; + if (rf_state == RF_IDLE) { + rf_receive(rf_rx_channel, rf_module); + } + break; + case PHY_EXTENSION_SET_CCA_THRESHOLD: + rf_conf_set_cca_threshold(*data_ptr); + break; + case PHY_EXTENSION_SET_802_15_4_MODE: + mac_mode = (phy_802_15_4_mode_t) *data_ptr; // *NOPAD* + if (mac_mode == IEEE_802_15_4_2011) { + rf_module = RF_24; + } else if (mac_mode == IEEE_802_15_4G_2012) { + rf_module = RF_09; + } + break; + default: + break; + } + return 0; +} + +static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_t rf_channel) +{ + int8_t ret_val = 0; + switch (new_state) { + case PHY_INTERFACE_RESET: + break; + case PHY_INTERFACE_DOWN: + break; + case PHY_INTERFACE_UP: + rf_receive(rf_channel, rf_module); + break; + case PHY_INTERFACE_RX_ENERGY_STATE: + break; + case PHY_INTERFACE_SNIFFER_STATE: + break; + } + return ret_val; +} + +#ifdef TEST_GPIOS_ENABLED +static void test1_toggle(void) +{ + if (test_pins->TEST4) { + test_pins->TEST4 = 0; + } else { + test_pins->TEST4 = 1; + } +} +static void test2_toggle(void) +{ + if (test_pins->TEST5) { + test_pins->TEST5 = 0; + } else { + test_pins->TEST5 = 1; + } +} +#endif //TEST_GPIOS_ENABLED + +static void rf_init(void) +{ +#ifdef TEST_GPIOS_ENABLED + fhss_bc_switch = test1_toggle; + fhss_uc_switch = test2_toggle; +#endif //TEST_GPIOS_ENABLED + rf_lock(); + // Disable interrupts + rf_write_rf_register(RF_IRQM, RF_09, 0); + rf_write_rf_register(RF_IRQM, RF_24, 0); + // Ensure basebands enabled, I/Q IF's disabled + rf_write_rf_register_field(RF_IQIFC1, COMMON, CHPM, RF_MODE_BBRF); + rf_change_state(RF_TRX_OFF, RF_09); + rf_change_state(RF_TRX_OFF, RF_24); + memcpy(&phy_current_config, &phy_24ghz, sizeof(phy_rf_channel_configuration_s)); + rf_calculate_symbol_rate(phy_current_config.datarate, phy_current_config.modulation); + rf_init_registers(RF_24); + rf->IRQ.rise(&rf_interrupt_handler); + rf->IRQ.enable_irq(); + rf->tx_timer.start(); + rf_unlock(); +} + +static void rf_init_registers(rf_modules_e module) +{ + // O-QPSK configuration using IEEE Std 802.15.4-2011 + // FSK configuration using IEEE Std 802.15.4g-2012 + if (mac_mode == IEEE_802_15_4_2011) { + device_driver.link_type = PHY_LINK_15_4_2_4GHZ_TYPE; + // 16-bit FCS + rf_write_bbc_register_field(BBC_PC, module, FCST, FCST); + // Enable O-QPSK + rf_write_bbc_register_field(BBC_PC, module, PT, BB_MROQPSK); + // Chip frequency 2000kchip/s + rf_write_bbc_register_field(BBC_OQPSKC0, module, FCHIP, BB_FCHIP2000); + // FCS type legacy O-QPSK is 16-bit + rf_write_bbc_register_field(BBC_OQPSKC2, module, FCSTLEG, FCS_16); + // Listen for both MR-O-QPSK and legacy O-QPSK PHY + rf_write_bbc_register_field(BBC_OQPSKC2, module, RXM, RXM_2); + // PHY type Legacy O-QPSK + rf_write_bbc_register_field(BBC_OQPSKPHRTX, module, LEG, LEG); + // Low pass filter cut-off frequency to 1000 kHz + rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC1000KHZ); + // Set TX filter to sample frequency / 2 + rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_4); + // Enable auto ack + rf_write_bbc_register_field(BBC_AMCS, module, AACK, AACK); + // Enable address filter unit 0 + rf_write_bbc_register_field(BBC_AFC0, module, AFEN0, AFEN0); + // Allow Ack frame type with address filter + rf_write_bbc_register_field(BBC_AFFTM, module, TYPE_2, TYPE_2); + } else if (mac_mode == IEEE_802_15_4G_2012) { + device_driver.link_type = PHY_LINK_15_4_SUBGHZ_TYPE; + // Enable FSK + rf_write_bbc_register_field(BBC_PC, module, PT, BB_MRFSK); + // Disable auto ack + rf_write_bbc_register_field(BBC_AMCS, module, AACK, 0); + // Disable address filter unit 0 + rf_write_bbc_register_field(BBC_AFC0, module, AFEN0, 0); + // Set bandwidth time product + rf_write_bbc_register_field(BBC_FSKC0, module, BT, BT_20); + // Disable interleaving + rf_write_bbc_register_field(BBC_FSKC2, module, FECIE, 0); + // Disable receiver override + rf_write_bbc_register_field(BBC_FSKC2, module, RXO, RXO_DIS); + // Set modulation index + if (phy_current_config.modulation_index == MODULATION_INDEX_0_5) { + rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_05); + rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_0); + } else { + rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_10); + rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_4); + } + // Set Gain control settings + rf_write_rf_register_field(RF_AGCC, module, AVGS, AVGS_8_SAMPLES); + rf_write_rf_register_field(RF_AGCS, module, TGT, TGT_1); + // Set symbol rate and related configurations + rf_set_fsk_symbol_rate_configuration(phy_current_config.datarate, module); + // Set preamble length + uint8_t preamble_len = 24; + if (phy_current_config.datarate < 150000) { + preamble_len = 8; + } else if (phy_current_config.datarate < 300000) { + preamble_len = 12; + } + rf_write_bbc_register(BBC_FSKPLL, module, preamble_len); + rf_write_bbc_register_field(BBC_FSKC3, module, PDT, PDT_6); + } + // Disable filtering FCS + rf_write_bbc_register_field(BBC_PC, module, FCSFE, 0); + // Set channel spacing + rf_set_channel_spacing(phy_current_config.channel_spacing, module); + // Set channel 0 center frequency + rf_set_ch0_frequency(phy_current_config.channel_0_center_frequency, module); + // Set channel (must be called after frequency change) + rf_set_channel(rf_rx_channel, module); +} + +static void rf_csma_ca_timer_interrupt(void) +{ + cca_prepare_status = device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_PREPARE, 0, 0); + if (cca_prepare_status == PHY_TX_NOT_ALLOWED) { + if (rf_state == RF_CSMA_STARTED) { + rf_state = RF_IDLE; + } else if (rf_state == RF_CSMA_WHILE_RX) { + rf_state = RF_RX_STARTED; + } + TEST_CSMA_DONE + return; + } + rf_irq_rf_enable(EDC, RF_09); + rf_irq_rf_enable(EDC, rf_module); + rf_write_rf_register_field(RF_EDC, rf_module, EDM, RF_EDSINGLE); + rf_backup_timer_start(0, CCA_BACKUP_TIMEOUT); +} + +static void rf_csma_ca_timer_signal(void) +{ + rf->irq_thread_215.flags_set(SIG_TIMER_CCA); +} + +static int8_t rf_start_csma_ca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_handle, data_protocol_e data_protocol) +{ + rf_lock(); + if (rf_state != RF_IDLE) { + rf_unlock(); + return -1; + } + rf_state = RF_CSMA_STARTED; + + // If Ack is requested, store the MAC sequence. This will be compared with received Ack. + uint8_t version = ((*(data_ptr + 1) & VERSION_FIELD_MASK) >> SHIFT_VERSION_FIELD); + if ((version != MAC_FRAME_VERSION_2) && (*data_ptr & FC_AR)) { + tx_sequence = *(data_ptr + 2); + } + rf_write_tx_buffer(data_ptr, data_length, rf_module); + if (phy_current_config.modulation == M_OQPSK) { + data_length += 2; + } else if (phy_current_config.modulation == M_2FSK) { + data_length += 4; + } + rf_write_tx_packet_length(data_length, rf_module); + mac_tx_handle = tx_handle; + + if (tx_time) { + uint32_t backoff_time = tx_time - rf_get_timestamp(); + // Max. time to TX can be 65ms, otherwise time has passed already -> send immediately + if (backoff_time <= 65000) { + rf->cca_timer.attach_us(rf_csma_ca_timer_signal, backoff_time); + TEST_CSMA_STARTED + rf_unlock(); + return 0; + } + } + // Short timeout to start CCA immediately. + rf->cca_timer.attach_us(rf_csma_ca_timer_signal, 1); + TEST_CSMA_STARTED + rf_unlock(); + return 0; +} + +static void rf_handle_cca_ed_done(void) +{ + TEST_CSMA_DONE + rf_backup_timer_stop(); + rf_irq_rf_disable(EDC, RF_09); + rf_irq_rf_disable(EDC, rf_module); + if (rf_state == RF_CSMA_WHILE_RX) { + rf_state = RF_RX_STARTED; + } + + if ((cca_enabled == true) && (rf_state == RF_RX_STARTED)) { + uint32_t backup_time = cur_rx_stop_time - rf_get_timestamp(); + if (backup_time > MAX_TRANSMISSION_TIME) { + backup_time = 0; + } + rf_backup_timer_start(0, backup_time + PACKET_PROCESSING_TIME); + device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 0, 0); + return; + } + if ((cca_enabled == true) && (((int8_t) rf_read_rf_register(RF_EDV, rf_module) > cca_threshold))) { + rf_state = RF_IDLE; + device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 0, 0); + return; + } + if (cca_prepare_status == PHY_RESTART_CSMA) { + device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_OK, 0, 0); + if (tx_time) { + uint32_t backoff_time = tx_time - rf_get_timestamp(); + // Max. time to TX can be 65ms, otherwise time has passed already -> send immediately + if (backoff_time > 65000) { + backoff_time = 1; + } + rf->cca_timer.attach_us(rf_csma_ca_timer_signal, backoff_time); + TEST_CSMA_STARTED + } + return; + } + rf_irq_bbc_disable(RXFE, rf_module); + rf_start_tx(); +} + +static void rf_handle_tx_done(void) +{ + rf_backup_timer_stop(); + TEST_TX_DONE + rf_irq_bbc_disable(TXFE, rf_module); + rf_state = RF_IDLE; + rf_receive(rf_rx_channel, rf_module); + device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 0, 0); +} + +static void rf_start_tx(void) +{ + receiver_enabled = false; + rf_change_state(RF_TXPREP, rf_module); + rf_irq_bbc_enable(TXFE, rf_module); + rf_change_state(RF_TX, rf_module); + rf_state = RF_TX_STARTED; + TEST_TX_STARTED + rf_backup_timer_start(cur_tx_packet_len, 0); +} + +static void rf_handle_ack(uint8_t seq_number, uint8_t pending) +{ + phy_link_tx_status_e phy_status; + if (tx_sequence == (uint16_t)seq_number) { + if (pending) { + phy_status = PHY_LINK_TX_DONE_PENDING; + } else { + phy_status = PHY_LINK_TX_DONE; + } + // No CCA attempts done, just waited Ack + device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, phy_status, 0, 0); + // Clear TX sequence when Ack is received to avoid duplicate Acks + tx_sequence = 0xffff; + } +} + +static void rf_handle_rx_done(void) +{ + receiver_enabled = false; + TEST_RX_DONE + rf_backup_timer_stop(); + if (rf_state == RF_CSMA_WHILE_RX) { + rf_state = RF_CSMA_STARTED; + uint32_t backup_time = tx_time - rf_get_timestamp(); + // Next TX start event must occur in less than 65ms + if (backup_time > 65000) { + backup_time = 0; + } + rf_backup_timer_start(0, backup_time + CCA_BACKUP_TIMEOUT); + } else if (rf_state == RF_RX_STARTED) { + rf_state = RF_IDLE; + } + if (rf_read_bbc_register(BBC_PC, rf_module) & FCSOK) { + if (!rf_read_rx_buffer(cur_rx_packet_len, rf_module)) { + uint8_t version = ((rx_buffer[1] & VERSION_FIELD_MASK) >> SHIFT_VERSION_FIELD); + if (((rx_buffer[0] & MAC_FRAME_TYPE_MASK) == MAC_TYPE_ACK) && (version < MAC_FRAME_VERSION_2)) { + rf_handle_ack(rx_buffer[2], rx_buffer[0] & MAC_DATA_PENDING); + } else { + int8_t rssi = (int8_t) rf_read_rf_register(RF_EDV, rf_module); + if (phy_current_config.modulation == M_OQPSK) { + cur_rx_packet_len -= 2; + } else if (phy_current_config.modulation == M_2FSK) { + cur_rx_packet_len -= 4; + } + device_driver.phy_rx_cb(rx_buffer, cur_rx_packet_len, 0xf0, rssi, rf_radio_driver_id); + // If auto ack used, must wait until RF returns to RF_TXPREP state + if ((version != MAC_FRAME_VERSION_2) && (rx_buffer[0] & FC_AR)) { + wait_us(100); + rf_poll_state_change(RF_TXPREP, rf_module); + } + } + } + } else { + if (device_driver.phy_rf_statistics) { + device_driver.phy_rf_statistics->crc_fails++; + } + device_driver.phy_rx_cb(NULL, 0, 0, 0, rf_radio_driver_id); + } + rf_receive(rf_rx_channel, rf_module); +} + +static void rf_handle_rx_start(void) +{ + rx_time = rf_get_timestamp(); + cur_rx_packet_len = rf_read_rx_frame_length(rf_module); + if (!cur_rx_packet_len || cur_rx_packet_len > device_driver.phy_MTU) { + return; + } + if (rf_state == RF_CSMA_STARTED) { + rf_backup_timer_stop(); + rf_state = RF_CSMA_WHILE_RX; + } else { + rf_state = RF_RX_STARTED; + } + TEST_RX_STARTED + cur_rx_stop_time = rf_backup_timer_start(cur_rx_packet_len, 0); +} + +static void rf_receive(uint16_t rx_channel, rf_modules_e module) +{ + if ((receiver_enabled == true) && (rf_update_config == false) && (rx_channel == rf_rx_channel)) { + return; + } + TEST_RX_DONE + rf_lock(); + if (rf_update_config == true) { + rf_update_config = false; + rf_change_state(RF_TRX_OFF, module); + rf_init_registers(module); + rf_change_state(RF_TXPREP, module); + } + if (rx_channel != rf_rx_channel) { + rf_change_state(RF_TXPREP, module); + rf_set_channel(rx_channel, module); + rf_rx_channel = rx_channel; + } + rf_change_state(RF_RX, module); + rf_irq_bbc_enable(RXFS, module); + rf_irq_bbc_enable(RXFE, module); + receiver_enabled = true; + rf_unlock(); + +} + +static void rf_interrupt_handler(void) +{ + rf->irq_thread_215.flags_set(SIG_RADIO); +} + +static void rf_irq_task_process_irq(void) +{ + uint8_t irq_rf09_status = 0, irq_bbc0_status = 0, irq_rf24_status = 0, irq_bbc1_status = 0; + if (rf09_irq_mask) { + irq_rf09_status = rf_read_common_register(RF09_IRQS); + irq_rf09_status &= rf09_irq_mask; + } + if (bbc0_irq_mask) { + irq_bbc0_status = rf_read_common_register(BBC0_IRQS); + irq_bbc0_status &= bbc0_irq_mask; + } + if (rf24_irq_mask) { + irq_rf24_status = rf_read_common_register(RF24_IRQS); + irq_rf24_status &= rf24_irq_mask; + } + if (bbc1_irq_mask) { + irq_bbc1_status = rf_read_common_register(BBC1_IRQS); + irq_bbc1_status &= bbc1_irq_mask; + } + if ((rf_state == RF_CSMA_STARTED) || (rf_state == RF_CSMA_WHILE_RX) || (rf_state == RF_RX_STARTED)) { + if ((irq_rf09_status & EDC) || (irq_rf24_status & EDC)) { + rf_handle_cca_ed_done(); + } + } + if (rf_state == RF_TX_STARTED) { + if ((irq_bbc0_status & TXFE) || (irq_bbc1_status & TXFE)) { + rf_handle_tx_done(); + } + } + if ((rf_state == RF_IDLE) || (rf_state == RF_CSMA_STARTED)) { + if ((irq_bbc0_status & RXFS) || (irq_bbc1_status & RXFS)) { + rf_handle_rx_start(); + } + } + if ((rf_state == RF_RX_STARTED) || (rf_state == RF_CSMA_WHILE_RX)) { + if ((irq_bbc0_status & RXFE) || (irq_bbc1_status & RXFE)) { + rf_handle_rx_done(); + } + } +} + +static void rf_write_tx_packet_length(uint16_t packet_length, rf_modules_e module) +{ + if (packet_length > device_driver.phy_MTU) { + return; + } + if ((uint8_t)(cur_tx_packet_len >> 8) != (packet_length / 256)) { + rf_write_bbc_register(BBC_TXFLH, module, packet_length / 256); + } + if ((uint8_t)cur_tx_packet_len != (packet_length % 256)) { + rf_write_bbc_register(BBC_TXFLL, module, packet_length % 256); + } + cur_tx_packet_len = packet_length; +} + +static uint16_t rf_read_rx_frame_length(rf_modules_e module) +{ + const uint8_t tx[2] = { static_cast(module + 2), static_cast(BBC_RXFLL) }; + uint8_t rx[2]; + rf->CS = 0; + rf_spi_exchange(tx, 2, NULL, 0); + rf_spi_exchange(NULL, 0, rx, 2); + rf->CS = 1; + return (uint16_t)((rx[1] << 8) | rx[0]); +} + +static void rf_write_tx_buffer(uint8_t *data, uint16_t len, rf_modules_e module) +{ + uint16_t buffer_addr = BBC0_FBTXS + (0x1000 * (module - 1)); + const uint8_t tx[2] = { static_cast(0x80 | (buffer_addr >> 8)), static_cast(buffer_addr) }; + rf->CS = 0; + rf_spi_exchange(tx, 2, NULL, 0); + rf_spi_exchange(data, len, NULL, 0); + rf->CS = 1; +} + +static int rf_read_rx_buffer(uint16_t length, rf_modules_e module) +{ + if (length > device_driver.phy_MTU) { + return -1; + } + uint8_t *ptr = rx_buffer; + uint16_t buffer_addr = BBC0_FBRXS + (0x1000 * (module - 1)); + const uint8_t tx[2] = { static_cast(buffer_addr >> 8), static_cast(buffer_addr) }; + rf->CS = 0; + rf_spi_exchange(tx, 2, NULL, 0); + rf_spi_exchange(NULL, 0, ptr, length); + rf->CS = 1; + return 0; +} + +static void rf_irq_rf_enable(uint8_t irq, rf_modules_e module) +{ + if ((module == RF_09) && !(rf09_irq_mask & irq)) { + rf_write_rf_register_field(RF_IRQM, module, irq, irq); + rf09_irq_mask |= irq; + } else if ((module == RF_24) && !(rf24_irq_mask & irq)) { + rf_write_rf_register_field(RF_IRQM, module, irq, irq); + rf24_irq_mask |= irq; + } +} + +static void rf_irq_rf_disable(uint8_t irq, rf_modules_e module) +{ + if ((module == RF_09) && (rf09_irq_mask & irq)) { + rf_write_rf_register_field(RF_IRQM, module, irq, 0); + rf09_irq_mask &= ~irq; + } else if ((module == RF_24) && (rf24_irq_mask & irq)) { + rf_write_rf_register_field(RF_IRQM, module, irq, 0); + rf24_irq_mask &= ~irq; + } +} + +static void rf_irq_bbc_enable(uint8_t irq, rf_modules_e module) +{ + if ((module == RF_09) && !(bbc0_irq_mask & irq)) { + rf_write_bbc_register_field(BBC_IRQM, module, irq, irq); + bbc0_irq_mask |= irq; + } else if ((module == RF_24) && !(bbc1_irq_mask & irq)) { + rf_write_bbc_register_field(BBC_IRQM, module, irq, irq); + bbc1_irq_mask |= irq; + } +} + +static void rf_irq_bbc_disable(uint8_t irq, rf_modules_e module) +{ + if ((module == RF_09) && (bbc0_irq_mask & irq)) { + rf_write_bbc_register_field(BBC_IRQM, module, irq, 0); + bbc0_irq_mask &= ~irq; + } else if ((module == RF_24) && (bbc1_irq_mask & irq)) { + rf_write_bbc_register_field(BBC_IRQM, module, irq, 0); + bbc1_irq_mask &= ~irq; + } +} + +static rf_command_e rf_read_state(rf_modules_e module) +{ + return (rf_command_e) rf_read_rf_register(RF_STATE, module); +} + +static void rf_poll_state_change(rf_command_e state, rf_modules_e module) +{ + uint32_t transition_start_time = rf_get_timestamp(); + while (rf_read_state(module) != state) { + if (rf_get_timestamp() > (transition_start_time + MAX_STATE_TRANSITION_TIME_US)) { + tr_err("Failed to change module %u state from %x to: %x", module, rf_read_state(module), state); + break; + } + } +} + +static void rf_change_state(rf_command_e state, rf_modules_e module) +{ + rf_write_rf_register(RF_CMD, module, state); + return rf_poll_state_change(state, module); +} + +static void rf_spi_exchange(const void *tx, size_t tx_len, void *rx, size_t rx_len) +{ + rf->spi.write(static_cast(tx), tx_len, static_cast(rx), rx_len); +} + +static uint8_t rf_read_rf_register(uint8_t addr, rf_modules_e module) +{ + const uint8_t tx[2] = { static_cast(module), static_cast(addr) }; + uint8_t rx[3]; + rf->CS = 0; + rf_spi_exchange(tx, 2, rx, 3); + rf->CS = 1; + return rx[2]; +} + +static void rf_write_rf_register(uint8_t addr, rf_modules_e module, uint8_t data) +{ + const uint8_t tx[3] = { static_cast(0x80 | module), static_cast(addr), static_cast(data) }; + uint8_t rx[2]; + rf->CS = 0; + rf_spi_exchange(tx, 3, rx, 2); + rf->CS = 1; +} + +static void rf_write_rf_register_field(uint8_t addr, rf_modules_e module, uint8_t field, uint8_t value) +{ + uint8_t reg_tmp = rf_read_rf_register(addr, module); + reg_tmp &= ~field; + reg_tmp |= value; + rf_write_rf_register(addr, module, reg_tmp); +} + +static void rf_backup_timer_interrupt(void) +{ + receiver_enabled = false; + rf_read_common_register(RF09_IRQS); + rf_read_common_register(RF24_IRQS); + rf_read_common_register(BBC0_IRQS); + rf_read_common_register(BBC1_IRQS); + rf_irq_rf_disable(EDC, RF_09); + rf_irq_rf_disable(EDC, RF_24); + if (rf_state == RF_RX_STARTED) { + if (device_driver.phy_rf_statistics) { + device_driver.phy_rf_statistics->rx_timeouts++; + } + } else { + if (device_driver.phy_rf_statistics) { + device_driver.phy_rf_statistics->tx_timeouts++; + } + } + if (rf_state == RF_TX_STARTED) { + device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_TX_SUCCESS, 0, 0); + } + if ((rf_state == RF_CSMA_STARTED) || (rf_state == RF_CSMA_WHILE_RX)) { + TEST_CSMA_DONE + device_driver.phy_tx_done_cb(rf_radio_driver_id, mac_tx_handle, PHY_LINK_CCA_FAIL, 0, 0); + } + TEST_TX_DONE + TEST_RX_DONE + rf_state = RF_IDLE; + rf_receive(rf_rx_channel, rf_module); +} + +static void rf_backup_timer_signal(void) +{ + rf->irq_thread_215.flags_set(SIG_TIMER_BACKUP); +} + +static void rf_backup_timer_stop(void) +{ + rf->cal_timer.detach(); +} + +static uint32_t rf_backup_timer_start(uint16_t bytes, uint32_t time_us) +{ + if (!time_us) { + time_us = (uint32_t)(8000000 / phy_current_config.datarate) * bytes + PACKET_PROCESSING_TIME; + } + // Using cal_timer as backup timer + rf->cal_timer.attach_us(rf_backup_timer_signal, time_us); + + return (rf_get_timestamp() + time_us); +} + +static int rf_set_channel(uint16_t channel, rf_modules_e module) +{ + rf_write_rf_register(RF_CNL, module, (uint8_t) channel); + rf_write_rf_register_field(RF_CNM, module, CNH, (uint8_t)(channel >> 8)); + return 0; +} + +static int rf_set_ch0_frequency(uint32_t frequency, rf_modules_e module) +{ + if (module == RF_24) { + frequency -= 1500000000; + } + frequency /= 25000; + rf_write_rf_register(RF_CCF0L, module, (uint8_t)frequency); + rf_write_rf_register(RF_CCF0H, module, (uint8_t)(frequency >> 8)); + return 0; +} + +static int rf_set_channel_spacing(uint32_t channel_spacing, rf_modules_e module) +{ + channel_spacing /= 25000; + rf_write_rf_register(RF_CS, module, channel_spacing); + return 0; +} + +static int rf_set_fsk_symbol_rate_configuration(uint32_t symbol_rate, rf_modules_e module) +{ + if (symbol_rate == 50000) { + rf_write_bbc_register_field(BBC_FSKC1, module, SRATE, SRATE_50KHZ); + if (rf_version_num == 1) { + rf_write_rf_register_field(RF_TXDFE, module, SR, SR_10); + } else { + rf_write_rf_register_field(RF_TXDFE, module, SR, SR_8); + } + rf_write_rf_register_field(RF_RXDFE, module, SR, SR_10); + if (phy_current_config.modulation_index == MODULATION_INDEX_0_5) { + rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_0); + } else { + rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_1); + } + rf_write_rf_register_field(RF_TXCUTC, module, PARAMP, RF_PARAMP32U); + rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC80KHZ); + rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW160KHZ_IF250KHZ); + rf_write_rf_register_field(RF_RXBWC, module, IFS, 0); + } else if (symbol_rate == 100000) { + rf_write_bbc_register_field(BBC_FSKC1, module, SRATE, SRATE_100KHZ); + if (rf_version_num == 1) { + rf_write_rf_register_field(RF_TXDFE, module, SR, SR_5); + } else { + rf_write_rf_register_field(RF_TXDFE, module, SR, SR_4); + } + rf_write_rf_register_field(RF_RXDFE, module, SR, SR_5); + rf_write_rf_register_field(RF_TXCUTC, module, PARAMP, RF_PARAMP16U); + if (phy_current_config.modulation_index == MODULATION_INDEX_0_5) { + rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_0); + rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC100KHZ); + rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW200KHZ_IF250KHZ); + } else { + rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_1); + rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC160KHZ); + rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW320KHZ_IF500KHZ); + } + rf_write_rf_register_field(RF_RXBWC, module, IFS, 0); + } else if (symbol_rate == 150000) { + rf_write_bbc_register_field(BBC_FSKC1, module, SRATE, SRATE_150KHZ); + rf_write_rf_register_field(RF_TXDFE, module, SR, SR_2); + rf_write_rf_register_field(RF_RXDFE, module, SR, SR_4); + rf_write_rf_register_field(RF_TXCUTC, module, PARAMP, RF_PARAMP16U); + if (phy_current_config.modulation_index == MODULATION_INDEX_0_5) { + rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_0); + rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC160KHZ); + rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW320KHZ_IF500KHZ); + } else { + rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_1); + rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC250KHZ); + rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW400KHZ_IF500KHZ); + } + rf_write_rf_register_field(RF_RXBWC, module, IFS, 0); + } else if (symbol_rate == 200000) { + rf_write_bbc_register_field(BBC_FSKC1, module, SRATE, SRATE_200KHZ); + rf_write_rf_register_field(RF_TXDFE, module, SR, SR_2); + rf_write_rf_register_field(RF_RXDFE, module, SR, SR_4); + rf_write_rf_register_field(RF_TXCUTC, module, PARAMP, RF_PARAMP16U); + if (phy_current_config.modulation_index == MODULATION_INDEX_0_5) { + rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_1); + rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC200KHZ); + rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW320KHZ_IF500KHZ); + rf_write_rf_register_field(RF_RXBWC, module, IFS, 0); + } else { + rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_2); + rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC315KHZ); + rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW500KHZ_IF500KHZ); + rf_write_rf_register_field(RF_RXBWC, module, IFS, IFS); + } + } else if (symbol_rate == 300000) { + rf_write_bbc_register_field(BBC_FSKC1, module, SRATE, SRATE_300KHZ); + rf_write_rf_register_field(RF_TXDFE, module, SR, SR_1); + rf_write_rf_register_field(RF_RXDFE, module, SR, SR_2); + rf_write_rf_register_field(RF_TXCUTC, module, PARAMP, RF_PARAMP8U); + if (phy_current_config.modulation_index == MODULATION_INDEX_0_5) { + rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_0); + rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC315KHZ); + rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW500KHZ_IF500KHZ); + rf_write_rf_register_field(RF_RXBWC, module, IFS, IFS); + } else { + rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_1); + rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC500KHZ); + rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW630KHZ_IF1000KHZ); + rf_write_rf_register_field(RF_RXBWC, module, IFS, 0); + } + } else if (symbol_rate == 400000) { + rf_write_bbc_register_field(BBC_FSKC1, module, SRATE, SRATE_400KHZ); + rf_write_rf_register_field(RF_TXDFE, module, SR, SR_1); + rf_write_rf_register_field(RF_RXDFE, module, SR, SR_2); + rf_write_rf_register_field(RF_TXCUTC, module, PARAMP, RF_PARAMP8U); + if (phy_current_config.modulation_index == MODULATION_INDEX_0_5) { + rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_0); + rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC400KHZ); + rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW630KHZ_IF1000KHZ); + rf_write_rf_register_field(RF_RXBWC, module, IFS, 0); + } else { + rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_1); + rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC625KHZ); + rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW1000KHZ_IF1000KHZ); + rf_write_rf_register_field(RF_RXBWC, module, IFS, IFS); + } + } + return 0; +} + +static void rf_conf_set_cca_threshold(uint8_t percent) +{ + uint8_t step = (MAX_CCA_THRESHOLD - MIN_CCA_THRESHOLD); + cca_threshold = MIN_CCA_THRESHOLD + (step * percent) / 100; +} + +static void rf_calculate_symbol_rate(uint32_t baudrate, phy_modulation_e modulation) +{ + uint8_t bits_in_symbols = 4; + if (modulation == M_2FSK) { + bits_in_symbols = 1; + } + rf_symbol_rate = baudrate / bits_in_symbols; +} + +void RFBits::rf_irq_task(void) +{ + for (;;) { + uint32_t flags = ThisThread::flags_wait_any(SIG_ALL); + rf_lock(); + if (flags & SIG_RADIO) { + rf_irq_task_process_irq(); + } + if (flags & SIG_TIMER_CCA) { + rf_csma_ca_timer_interrupt(); + } + if (flags & SIG_TIMER_BACKUP) { + rf_backup_timer_interrupt(); + } + rf_unlock(); + } +} + +int RFBits::init_215_driver(RFBits *_rf, TestPins *_test_pins, const uint8_t mac[8], uint8_t *rf_part_num) +{ + rf = _rf; + test_pins = _test_pins; + irq_thread_215.start(mbed::callback(this, &RFBits::rf_irq_task)); + rf->spi.frequency(25000000); + *rf_part_num = rf_read_common_register(RF_PN); + rf_version_num = rf_read_common_register(RF_VN); + tr_info("RF version number: %x", rf_version_num); + return rf_device_register(mac); +} + +#endif // MBED_CONF_NANOSTACK_CONFIGURATION && DEVICE_SPI && DEVICE_INTERRUPTIN && defined(MBED_CONF_RTOS_PRESENT) diff --git a/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp b/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp index be59a4afcd..e747af742d 100644 --- a/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp +++ b/components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp @@ -23,6 +23,7 @@ #include "NanostackRfPhyAtmel.h" #include "randLIB.h" #include "AT86RFReg.h" +#include "AT86RF215Reg.h" #include "nanostack/platform/arm_hal_phy.h" #include "mbed_trace.h" #include "mbed_toolchain.h" @@ -244,34 +245,8 @@ static void rf_if_irq_task_process_irq(); #endif // HW pins to RF chip +#include "rfbits.h" -class UnlockedSPI : public SPI { -public: - UnlockedSPI(PinName mosi, PinName miso, PinName sclk) : - SPI(mosi, miso, sclk) { } - virtual void lock() { } - virtual void unlock() { } -}; - -class RFBits { -public: - RFBits(PinName spi_mosi, PinName spi_miso, - PinName spi_sclk, PinName spi_cs, - PinName spi_rst, PinName spi_slp, PinName spi_irq); - UnlockedSPI spi; - DigitalOut CS; - DigitalOut RST; - DigitalOut SLP_TR; - InterruptIn IRQ; - Timeout ack_timer; - Timeout cal_timer; - Timeout cca_timer; -#ifdef MBED_CONF_RTOS_PRESENT - Thread irq_thread; - Mutex mutex; - void rf_if_irq_task(); -#endif -}; RFBits::RFBits(PinName spi_mosi, PinName spi_miso, PinName spi_sclk, PinName spi_cs, @@ -282,7 +257,8 @@ RFBits::RFBits(PinName spi_mosi, PinName spi_miso, SLP_TR(spi_slp), IRQ(spi_irq) #ifdef MBED_CONF_RTOS_PRESENT - , irq_thread(osPriorityRealtime, MBED_CONF_ATMEL_RF_IRQ_THREAD_STACK_SIZE, NULL, "atmel_irq_thread") + , irq_thread(osPriorityRealtime, MBED_CONF_ATMEL_RF_IRQ_THREAD_STACK_SIZE, NULL, "atmel_irq_thread"), + irq_thread_215(osPriorityRealtime, MBED_CONF_ATMEL_RF_IRQ_THREAD_STACK_SIZE, NULL, "atmel_215_irq_thread") #endif { #ifdef MBED_CONF_RTOS_PRESENT @@ -290,7 +266,17 @@ RFBits::RFBits(PinName spi_mosi, PinName spi_miso, #endif } +TestPins::TestPins(PinName test_pin_1, PinName test_pin_2, PinName test_pin_3, PinName test_pin_4, PinName test_pin_5) + : TEST1(test_pin_1), + TEST2(test_pin_2), + TEST3(test_pin_3), + TEST4(test_pin_4), + TEST5(test_pin_5) +{ +} + static RFBits *rf; +static TestPins *test_pins; static uint8_t rf_part_num = 0; /*TODO: RSSI Base value setting*/ static int8_t rf_rssi_base_val = -91; @@ -652,6 +638,10 @@ static void rf_if_write_set_tx_power_register(uint8_t value) */ static uint8_t rf_if_read_part_num(void) { + // Part number is already set + if (rf_part_num) { + return rf_part_num; + } return rf_if_read_register(PART_NUM); } @@ -664,9 +654,6 @@ static uint8_t rf_if_read_part_num(void) */ static void rf_if_write_rf_settings(void) { - /*Reset RF module*/ - rf_if_reset_radio(); - rf_part_num = rf_if_read_part_num(); rf_if_write_register(XAH_CTRL_0, 0); @@ -675,7 +662,9 @@ static void rf_if_write_rf_settings(void) rf_if_write_register(TRX_CTRL_1, TX_AUTO_CRC_ON | SPI_CMD_MODE_TRX_STATUS); rf_if_write_register(IRQ_MASK, CCA_ED_DONE | TRX_END | TRX_UR); - +#ifdef TEST_GPIOS_ENABLED + rf_if_set_bit(IRQ_MASK, RX_START, RX_START); +#endif xah_ctrl_1 = rf_if_read_register(XAH_CTRL_1); /*Read transceiver PART_NUM*/ @@ -1024,6 +1013,11 @@ static void rf_if_interrupt_handler(void) /*Read and clear interrupt flag, and pick up trx_status*/ irq_status = rf_if_read_register_with_status(IRQ_STATUS, &full_trx_status); +#ifdef TEST_GPIOS_ENABLED + if (irq_status & RX_START) { + TEST_RX_STARTED + } +#endif /*Frame end interrupt (RX and TX)*/ if (irq_status & TRX_END) { rf_trx_states_t trx_status = rf_if_trx_status_from_full(full_trx_status); @@ -1384,7 +1378,6 @@ static void rf_channel_set(uint8_t ch) rf_if_unlock(); } - /* * \brief Function initialises the radio driver and resets the radio. * @@ -1526,6 +1519,7 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h rf_tx_length = data_length; /*Start CCA timeout*/ rf_cca_timer_start(RF_CCA_BASE_BACKOFF + randLIB_get_random_in_range(0, RF_CCA_RANDOM_BACKOFF)); + TEST_CSMA_STARTED /*Store TX handle*/ mac_tx_handle = tx_handle; rf_if_unlock(); @@ -1544,6 +1538,7 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h */ static void rf_cca_abort(void) { + TEST_CSMA_DONE rf_cca_timer_stop(); rf_flags_clear(RFF_CCA); } @@ -1585,6 +1580,7 @@ static bool rf_start_tx() rf_flags_set(RFF_TX); /*RF state change: SLP_TR pulse triggers PLL_ON->BUSY_TX*/ rf_if_enable_slptr(); + TEST_TX_STARTED /*Chip permits us to write frame buffer while it is transmitting*/ /*As long as first byte of data is in within 176us of TX start, we're good */ rf_if_write_frame_buffer(rf_tx_data, rf_tx_length); @@ -1601,6 +1597,7 @@ static bool rf_start_tx() */ static void rf_receive(rf_trx_states_t trx_status) { + TEST_RX_DONE uint16_t while_counter = 0; if (rf_flags_check(RFF_ON) == 0) { rf_on(); @@ -1765,6 +1762,7 @@ static void rf_handle_ack(uint8_t seq_number, uint8_t data_pending) */ static void rf_handle_rx_end(rf_trx_states_t trx_status) { + TEST_RX_DONE /*Frame received interrupt*/ if (!rf_flags_check(RFF_RX)) { return; @@ -1827,6 +1825,7 @@ static void rf_shutdown(void) */ static void rf_handle_tx_end(rf_trx_states_t trx_status) { + TEST_TX_DONE rf_rx_mode = 0; /*If ACK is needed for this transmission*/ if ((rf_tx_data[0] & 0x20) && rf_flags_check(RFF_TX)) { @@ -1853,6 +1852,7 @@ static void rf_handle_tx_end(rf_trx_states_t trx_status) */ static void rf_handle_cca_ed_done(uint8_t full_trx_status) { + TEST_CSMA_DONE if (!rf_flags_check(RFF_CCA)) { return; } @@ -2168,11 +2168,14 @@ static uint8_t rf_scale_lqi(int8_t rssi) NanostackRfPhyAtmel::NanostackRfPhyAtmel(PinName spi_mosi, PinName spi_miso, PinName spi_sclk, PinName spi_cs, PinName spi_rst, PinName spi_slp, PinName spi_irq, PinName i2c_sda, PinName i2c_scl) - : _mac(i2c_sda, i2c_scl), _mac_addr(), _rf(NULL), _mac_set(false), + : _mac(i2c_sda, i2c_scl), _mac_addr(), _rf(NULL), _test_pins(NULL), _mac_set(false), _spi_mosi(spi_mosi), _spi_miso(spi_miso), _spi_sclk(spi_sclk), _spi_cs(spi_cs), _spi_rst(spi_rst), _spi_slp(spi_slp), _spi_irq(spi_irq) { _rf = new RFBits(_spi_mosi, _spi_miso, _spi_sclk, _spi_cs, _spi_rst, _spi_slp, _spi_irq); +#ifdef TEST_GPIOS_ENABLED + _test_pins = new TestPins(TEST_PIN_TX, TEST_PIN_RX, TEST_PIN_CSMA, TEST_PIN_SPARE_1, TEST_PIN_SPARE_2); +#endif } NanostackRfPhyAtmel::~NanostackRfPhyAtmel() @@ -2196,6 +2199,7 @@ int8_t NanostackRfPhyAtmel::rf_register() // Read the mac address if it hasn't been set by a user rf = _rf; + test_pins = _test_pins; if (!_mac_set) { int ret = _mac.read_eui64((void *)_mac_addr); if (ret < 0) { @@ -2204,9 +2208,20 @@ int8_t NanostackRfPhyAtmel::rf_register() return -1; } } - - int8_t radio_id = rf_device_register(_mac_addr); + /*Reset RF module*/ + rf_if_reset_radio(); + rf_part_num = rf_if_read_part_num(); + int8_t radio_id = -1; + if (rf_part_num != PART_AT86RF231 && rf_part_num != PART_AT86RF233 && rf_part_num != PART_AT86RF212) { + // Register RF type 215. Jumps to AT86RF215 driver. + radio_id = rf->init_215_driver(_rf, _test_pins, _mac_addr, &rf_part_num); + } else { + // Register other RF types. + radio_id = rf_device_register(_mac_addr); + } + tr_info("RF part number: %x", rf_part_num); if (radio_id < 0) { + tr_err("RF registration failed"); rf = NULL; } diff --git a/components/802.15.4_RF/atmel-rf-driver/source/rfbits.h b/components/802.15.4_RF/atmel-rf-driver/source/rfbits.h new file mode 100644 index 0000000000..94143e6a8b --- /dev/null +++ b/components/802.15.4_RF/atmel-rf-driver/source/rfbits.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2020 ARM Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef RFBITS_H_ +#define RFBITS_H_ + +#include "DigitalIn.h" +#include "DigitalOut.h" +#include "InterruptIn.h" +#include "SPI.h" +#include +#include "Timeout.h" +#include "rtos.h" + +using namespace mbed; +using namespace rtos; + +class UnlockedSPI : public SPI { +public: + UnlockedSPI(PinName mosi, PinName miso, PinName sclk) : + SPI(mosi, miso, sclk) { } + virtual void lock() { } + virtual void unlock() { } +}; + +class RFBits { +public: + RFBits(PinName spi_mosi, PinName spi_miso, + PinName spi_sclk, PinName spi_cs, + PinName spi_rst, PinName spi_slp, PinName spi_irq); + UnlockedSPI spi; + DigitalOut CS; + DigitalOut RST; + DigitalOut SLP_TR; + InterruptIn IRQ; + Timeout ack_timer; + Timeout cal_timer; + Timeout cca_timer; + Timer tx_timer; + int init_215_driver(RFBits *_rf, TestPins *_test_pins, const uint8_t mac[8], uint8_t *rf_part_num); +#ifdef MBED_CONF_RTOS_PRESENT + Thread irq_thread; + Thread irq_thread_215; + Mutex mutex; + void rf_if_irq_task(); + void rf_irq_task(); +#endif +}; + +class TestPins { +public: + TestPins(PinName test_pin_1, PinName test_pin_2, PinName test_pin_3, PinName test_pin_4, PinName test_pin_5); + DigitalOut TEST1; + DigitalOut TEST2; + DigitalOut TEST3; + DigitalOut TEST4; + DigitalOut TEST5; +}; + +#endif /* RFBITS_H_ */