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M487: Refine the WKT resolution to WDT reset from PD 

1. Rephrase the comment
2. Pass WDT reset reason test
pull/14567/head
Chun-Chieh Li 2021-04-22 11:46:20 +08:00
parent 7db85490e6
commit e38b691541
3 changed files with 21 additions and 15 deletions
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5
targets/TARGET_NUVOTON/TARGET_M480/device/startup_M480.c
View File

@ -392,10 +392,7 @@ void Reset_Handler_1(void)
{
/* Disable register write-protection function */
SYS_UnlockReg();
/* Disable Power-on Reset function */
SYS_DISABLE_POR();
/**
* NOTE 1: Some register accesses require unlock.
* NOTE 2: Because EBI (external SRAM) init is done in SystemInit(), SystemInit() must be called at the very start.

13
targets/TARGET_NUVOTON/TARGET_M480/mbed_overrides.c
View File

@ -72,29 +72,22 @@ void mbed_sdk_init(void)
/* Lock protected registers */
SYS_LockReg();
/* Get around h/w issue with reset from deep power-down mode
*
* When UART interrupt enabled and WDT reset from power-down mode, in the next
* cycle, UART interrupt keeps breaking in and cannot block unless via NVIC. To
* get around it, we make up a signal of wake-up from deep power-down mode in the
* start of boot process on detecting WDT reset.
*/
/* Get around h/w limit with WDT reset from PD */
if (SYS_IS_WDT_RST()) {
/* Re-unlock protected clock setting */
SYS_UnlockReg();
/* Set up DPD power down mode */
CLK->PMUSTS |= CLK_PMUSTS_CLRWK_Msk;
CLK->PMUSTS |= CLK_PMUSTS_TMRWK_Msk;
CLK->PMUSTS |= CLK_PMUSTS_TMRWK_Msk;
CLK_SetPowerDownMode(CLK_PMUCTL_PDMSEL_DPD);
/* Set up PMU wakeup timer, wakeup interval must be WKTMRIS_256 25.6 ms at least */
CLK_SET_WKTMR_INTERVAL(CLK_PMUCTL_WKTMRIS_256);
CLK_ENABLE_WKTMR();
CLK_PowerDown();
/* Lock protected registers */
SYS_LockReg();
}
}

18
targets/TARGET_NUVOTON/TARGET_M480/reset_reason.c
View File

@ -39,6 +39,12 @@ reset_reason_t hal_reset_reason_get(void)
reset_reason_t reset_reason_cast;
uint32_t reset_reason_count = 0;
/* Get around h/w limit with WDT reset from PD */
if (CLK->PMUSTS & CLK_PMUSTS_TMRWK_Msk) {
/* Per test, these reset reason flags will set with WKT reset. Clear them for this resolution. */
SYS_CLEAR_RST_SOURCE(SYS_RSTSTS_PINRF_Msk | SYS_RSTSTS_PORF_Msk);
}
if (SYS_IS_POR_RST()) {
reset_reason_cast = RESET_REASON_POWER_ON;
reset_reason_count ++;
@ -49,7 +55,8 @@ reset_reason_t hal_reset_reason_get(void)
reset_reason_count ++;
}
if (SYS_IS_WDT_RST()) {
/* Get around h/w limit with WDT reset from PD */
if (SYS_IS_WDT_RST() || (CLK->PMUSTS & CLK_PMUSTS_TMRWK_Msk)) {
reset_reason_cast = RESET_REASON_WATCHDOG;
reset_reason_count ++;
}
@ -103,6 +110,15 @@ uint32_t hal_reset_reason_get_raw(void)
void hal_reset_reason_clear(void)
{
SYS_CLEAR_RST_SOURCE(SYS->RSTSTS);
/* Re-unlock protected clock setting */
SYS_UnlockReg();
/* Get around h/w limit with WDT reset from PD */
CLK->PMUSTS |= (CLK_PMUSTS_CLRWK_Msk | CLK_PMUSTS_TMRWK_Msk);
/* Lock protected registers */
SYS_LockReg();
}
#endif