mirror of https://github.com/ARMmbed/mbed-os.git
Add missing PWM_12 and update map and system files to be in line with latest official version.
bcostm
parent
ded07a59b5
commit
e2b37fc68d
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f401xc.h
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* @author MCD Application Team
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* @version V2.3.0
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* @date 02-March-2015
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* @version V2.3.2
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* @date 26-June-2015
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* @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File.
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*
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* This file contains:
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@ -665,15 +665,12 @@ USB_OTG_HostChannelTypeDef;
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#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
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#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
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#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
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#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
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#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
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#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
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#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
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#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
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#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
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#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
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#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
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#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
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#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
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#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
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#define FLASH_END ((uint32_t)0x0803FFFF) /*!< FLASH end address */
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/* Legacy defines */
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@ -2447,7 +2444,6 @@ USB_OTG_HostChannelTypeDef;
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#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
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#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
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#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
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#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
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#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
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#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
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@ -2643,7 +2639,7 @@ USB_OTG_HostChannelTypeDef;
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/******************** Bits definition for RTC_PRER register *****************/
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#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
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#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
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#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
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/******************** Bits definition for RTC_WUTR register *****************/
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#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f4xx.h
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* @author MCD Application Team
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* @version V2.3.0
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* @date 02-March-2015
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* @version V2.3.2
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* @date 26-June-2015
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* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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@ -107,11 +107,11 @@
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number V2.3.0
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* @brief CMSIS Device version number V2.3.2
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*/
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
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|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file system_stm32f4xx.h
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* @author MCD Application Team
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* @version V2.3.0
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* @date 02-March-2015
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* @version V2.3.2
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* @date 26-June-2015
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* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
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******************************************************************************
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* @attention
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f429xx.h
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* @author MCD Application Team
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* @version V2.3.0
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* @date 02-March-2015
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* @version V2.3.2
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* @date 26-June-2015
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* @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File.
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*
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* This file contains:
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@ -1060,12 +1060,11 @@ USB_OTG_HostChannelTypeDef;
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#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
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#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
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#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
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#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
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#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
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#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
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#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
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#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
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#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */
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#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
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#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
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#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
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#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
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#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
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@ -6112,7 +6111,7 @@ USB_OTG_HostChannelTypeDef;
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/******************** Bits definition for RTC_PRER register *****************/
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#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
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#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
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#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
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/******************** Bits definition for RTC_WUTR register *****************/
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#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
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@ -6517,7 +6516,7 @@ USB_OTG_HostChannelTypeDef;
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#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
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#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
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#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
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#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
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#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
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/****************** Bit definition for SAI_xCLRFR register ******************/
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#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f4xx.h
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* @author MCD Application Team
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* @version V2.3.0
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* @date 02-March-2015
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* @version V2.3.2
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* @date 26-June-2015
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* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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@ -107,11 +107,11 @@
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number V2.3.0
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* @brief CMSIS Device version number V2.3.2
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*/
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
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|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file system_stm32f4xx.h
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* @author MCD Application Team
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* @version V2.3.0
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* @date 02-March-2015
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* @version V2.3.2
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* @date 26-June-2015
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* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
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******************************************************************************
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* @attention
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f411xe.h
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* @author MCD Application Team
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* @version V2.3.0
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* @date 02-March-2015
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* @version V2.3.2
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* @date 26-June-2015
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* @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
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*
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* This file contains:
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@ -667,15 +667,12 @@ USB_OTG_HostChannelTypeDef;
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#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
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#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
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#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
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#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
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#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
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#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
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#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
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#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
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#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
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#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
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#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
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#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
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#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
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#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
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#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
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/* Legacy defines */
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@ -2456,7 +2453,6 @@ USB_OTG_HostChannelTypeDef;
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#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
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#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
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#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
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#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
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#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
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#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
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@ -2663,7 +2659,7 @@ USB_OTG_HostChannelTypeDef;
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/******************** Bits definition for RTC_PRER register *****************/
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#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
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#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
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#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
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/******************** Bits definition for RTC_WUTR register *****************/
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#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f4xx.h
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* @author MCD Application Team
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* @version V2.3.0
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* @date 02-March-2015
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* @version V2.3.2
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* @date 26-June-2015
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* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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@ -107,11 +107,11 @@
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number V2.3.0
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* @brief CMSIS Device version number V2.3.2
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*/
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
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|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file system_stm32f4xx.h
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* @author MCD Application Team
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* @version V2.3.0
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* @date 02-March-2015
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* @version V2.3.2
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* @date 26-June-2015
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* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
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******************************************************************************
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* @attention
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@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f405xx.h
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* @author MCD Application Team
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* @version V2.3.0
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* @date 02-March-2015
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* @version V2.3.2
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* @date 26-June-2015
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* @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File.
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*
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* This file contains:
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@ -843,16 +843,13 @@ USB_OTG_HostChannelTypeDef;
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#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
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#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
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#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
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#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
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#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
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#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
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#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
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#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
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#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
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#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
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#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
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#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
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#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
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#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
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#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
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#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
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#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
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#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
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#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
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#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
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#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
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#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
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#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
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#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
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#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
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#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
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#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
||||
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3441,11 +3442,15 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||||
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||||
|
||||
#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
||||
#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
|
||||
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
||||
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3482,11 +3487,15 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||||
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||||
|
||||
#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
||||
#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
|
||||
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
||||
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3523,11 +3532,15 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||||
#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||||
|
||||
#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
||||
#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
|
||||
#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
||||
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3564,11 +3577,15 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||||
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||||
|
||||
#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
||||
#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
|
||||
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
||||
#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3605,11 +3622,15 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||||
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||||
|
||||
#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
||||
#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
|
||||
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
||||
#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3646,11 +3667,15 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||||
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||||
|
||||
#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
||||
#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
|
||||
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
||||
#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3692,6 +3717,10 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
||||
#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -4957,7 +4986,6 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
|
||||
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
|
||||
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
|
||||
#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
|
||||
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
|
||||
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
|
||||
#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
|
||||
|
|
@ -5186,7 +5214,7 @@ USB_OTG_HostChannelTypeDef;
|
|||
|
||||
/******************** Bits definition for RTC_PRER register *****************/
|
||||
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
|
||||
#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
|
||||
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
|
||||
|
||||
/******************** Bits definition for RTC_WUTR register *****************/
|
||||
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -107,11 +107,11 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.3.0
|
||||
* @brief CMSIS Device version number V2.3.2
|
||||
*/
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,9 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.1
|
||||
* @date 13-March-2015
|
||||
* @brief HAL configuration file
|
||||
* @version V1.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32f4xx_hal_conf.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
|
|
@ -54,18 +56,19 @@
|
|||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_CAN_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_CEC_MODULE_ENABLED
|
||||
#define HAL_CRYP_MODULE_ENABLED
|
||||
#define HAL_DAC_MODULE_ENABLED
|
||||
#define HAL_DCMI_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
/* #define HAL_DMA2D_MODULE_ENABLED */
|
||||
#define HAL_DMA2D_MODULE_ENABLED
|
||||
#define HAL_ETH_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_NAND_MODULE_ENABLED
|
||||
#define HAL_NOR_MODULE_ENABLED
|
||||
#define HAL_PCCARD_MODULE_ENABLED
|
||||
#define HAL_SRAM_MODULE_ENABLED
|
||||
/* #define HAL_SDRAM_MODULE_ENABLED */
|
||||
#define HAL_SDRAM_MODULE_ENABLED
|
||||
#define HAL_HASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
|
|
@ -73,10 +76,11 @@
|
|||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_LTDC_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_QSPI_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RNG_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
/* #define HAL_SAI_MODULE_ENABLED */
|
||||
#define HAL_SAI_MODULE_ENABLED
|
||||
#define HAL_SD_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
|
|
@ -88,6 +92,8 @@
|
|||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_HCD_MODULE_ENABLED
|
||||
#define HAL_FMPI2C_MODULE_ENABLED
|
||||
#define HAL_SPDIFRX_MODULE_ENABLED
|
||||
|
||||
|
||||
/* ########################## HSE/HSI Values adaptation ##################### */
|
||||
|
|
@ -117,7 +123,7 @@
|
|||
* @brief Internal Low Speed oscillator (LSI) value.
|
||||
*/
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE ((uint32_t)32000)
|
||||
#define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature.*/
|
||||
|
|
@ -378,6 +384,22 @@
|
|||
#include "stm32f4xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_qspi.h"
|
||||
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FMPI2C_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_fmpi2c.h"
|
||||
#endif /* HAL_FMPI2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32f4xx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
|
|
@ -396,7 +418,6 @@
|
|||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f411xe.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -667,15 +667,12 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
|
||||
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
|
||||
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
|
||||
#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
|
||||
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
|
||||
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
||||
#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
||||
#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -2456,7 +2453,6 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
|
||||
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
|
||||
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
|
||||
#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
|
||||
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
|
||||
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
|
||||
|
||||
|
|
@ -2663,7 +2659,7 @@ USB_OTG_HostChannelTypeDef;
|
|||
|
||||
/******************** Bits definition for RTC_PRER register *****************/
|
||||
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
|
||||
#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
|
||||
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
|
||||
|
||||
/******************** Bits definition for RTC_WUTR register *****************/
|
||||
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -107,11 +107,11 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.3.0
|
||||
* @brief CMSIS Device version number V2.3.2
|
||||
*/
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f401xe.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -665,15 +665,12 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
|
||||
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
|
||||
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
|
||||
#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
|
||||
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
|
||||
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
||||
#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
||||
#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -2447,7 +2444,6 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
|
||||
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
|
||||
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
|
||||
#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
|
||||
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
|
||||
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
|
||||
|
||||
|
|
@ -2643,7 +2639,7 @@ USB_OTG_HostChannelTypeDef;
|
|||
|
||||
/******************** Bits definition for RTC_PRER register *****************/
|
||||
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
|
||||
#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
|
||||
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
|
||||
|
||||
/******************** Bits definition for RTC_WUTR register *****************/
|
||||
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -107,11 +107,11 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.3.0
|
||||
* @brief CMSIS Device version number V2.3.2
|
||||
*/
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f411xe.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -667,15 +667,12 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
|
||||
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
|
||||
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
|
||||
#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
|
||||
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
|
||||
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
||||
#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
||||
#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
|
||||
|
||||
/* Legacy defines */
|
||||
|
|
@ -2456,7 +2453,6 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
|
||||
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
|
||||
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
|
||||
#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
|
||||
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
|
||||
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
|
||||
|
||||
|
|
@ -2663,7 +2659,7 @@ USB_OTG_HostChannelTypeDef;
|
|||
|
||||
/******************** Bits definition for RTC_PRER register *****************/
|
||||
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
|
||||
#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
|
||||
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
|
||||
|
||||
/******************** Bits definition for RTC_WUTR register *****************/
|
||||
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -107,11 +107,11 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.3.0
|
||||
* @brief CMSIS Device version number V2.3.2
|
||||
*/
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f407xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -937,16 +937,13 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
|
||||
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
|
||||
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
|
||||
#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
|
||||
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
|
||||
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
|
||||
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
||||
#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
||||
#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
|
||||
#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
|
||||
|
||||
|
|
@ -3556,11 +3553,15 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||||
#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||||
|
||||
#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
||||
#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
|
||||
#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
||||
#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3597,11 +3598,15 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||||
#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||||
|
||||
#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
||||
#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
|
||||
#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
||||
#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3638,11 +3643,15 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||||
#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||||
|
||||
#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
||||
#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
|
||||
#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
||||
#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3684,6 +3693,10 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
||||
#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3720,11 +3733,15 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||||
#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||||
|
||||
#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
||||
#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
|
||||
#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
||||
#define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3761,11 +3778,15 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||||
#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||||
|
||||
#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
||||
#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
|
||||
#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
||||
#define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3802,11 +3823,15 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
||||
#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
||||
|
||||
#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
||||
#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [7:0] bits (Data-phase duration) */
|
||||
#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
||||
#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
||||
#define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -3848,6 +3873,10 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
||||
#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
||||
#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
||||
#define FSMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
||||
#define FSMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
||||
#define FSMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
||||
#define FSMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
||||
|
||||
#define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
||||
#define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
|
|
@ -5120,7 +5149,6 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
|
||||
#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
|
||||
#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
|
||||
#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
|
||||
#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
|
||||
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
|
||||
#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
|
||||
|
|
@ -5354,7 +5382,7 @@ USB_OTG_HostChannelTypeDef;
|
|||
|
||||
/******************** Bits definition for RTC_PRER register *****************/
|
||||
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
|
||||
#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
|
||||
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
|
||||
|
||||
/******************** Bits definition for RTC_WUTR register *****************/
|
||||
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -107,11 +107,11 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.3.0
|
||||
* @brief CMSIS Device version number V2.3.2
|
||||
*/
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f439xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS STM32F439xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* This file contains:
|
||||
|
|
@ -1129,12 +1129,11 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
||||
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
|
||||
#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
|
||||
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
|
||||
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
|
||||
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
|
||||
#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
|
||||
#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
||||
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
||||
#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
||||
#define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
|
||||
#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
|
||||
|
||||
|
|
@ -5292,17 +5291,27 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define HASH_CR_LKEY ((uint32_t)0x00010000)
|
||||
|
||||
/****************** Bits definition for HASH_STR register *******************/
|
||||
#define HASH_STR_NBW ((uint32_t)0x0000001F)
|
||||
#define HASH_STR_NBW_0 ((uint32_t)0x00000001)
|
||||
#define HASH_STR_NBW_1 ((uint32_t)0x00000002)
|
||||
#define HASH_STR_NBW_2 ((uint32_t)0x00000004)
|
||||
#define HASH_STR_NBW_3 ((uint32_t)0x00000008)
|
||||
#define HASH_STR_NBW_4 ((uint32_t)0x00000010)
|
||||
#define HASH_STR_NBLW ((uint32_t)0x0000001F)
|
||||
#define HASH_STR_NBLW_0 ((uint32_t)0x00000001)
|
||||
#define HASH_STR_NBLW_1 ((uint32_t)0x00000002)
|
||||
#define HASH_STR_NBLW_2 ((uint32_t)0x00000004)
|
||||
#define HASH_STR_NBLW_3 ((uint32_t)0x00000008)
|
||||
#define HASH_STR_NBLW_4 ((uint32_t)0x00000010)
|
||||
#define HASH_STR_DCAL ((uint32_t)0x00000100)
|
||||
/* Aliases for HASH_STR register */
|
||||
#define HASH_STR_NBW HASH_STR_NBLW
|
||||
#define HASH_STR_NBW_0 HASH_STR_NBLW_0
|
||||
#define HASH_STR_NBW_1 HASH_STR_NBLW_1
|
||||
#define HASH_STR_NBW_2 HASH_STR_NBLW_2
|
||||
#define HASH_STR_NBW_3 HASH_STR_NBLW_3
|
||||
#define HASH_STR_NBW_4 HASH_STR_NBLW_4
|
||||
|
||||
/****************** Bits definition for HASH_IMR register *******************/
|
||||
#define HASH_IMR_DINIM ((uint32_t)0x00000001)
|
||||
#define HASH_IMR_DCIM ((uint32_t)0x00000002)
|
||||
#define HASH_IMR_DINIE ((uint32_t)0x00000001)
|
||||
#define HASH_IMR_DCIE ((uint32_t)0x00000002)
|
||||
/* Aliases for HASH_IMR register */
|
||||
#define HASH_IMR_DINIM HASH_IMR_DINIE
|
||||
#define HASH_IMR_DCIM HASH_IMR_DCIE
|
||||
|
||||
/****************** Bits definition for HASH_SR register ********************/
|
||||
#define HASH_SR_DINIS ((uint32_t)0x00000001)
|
||||
|
|
@ -6292,7 +6301,7 @@ USB_OTG_HostChannelTypeDef;
|
|||
|
||||
/******************** Bits definition for RTC_PRER register *****************/
|
||||
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
|
||||
#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
|
||||
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
|
||||
|
||||
/******************** Bits definition for RTC_WUTR register *****************/
|
||||
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
|
||||
|
|
@ -6697,7 +6706,7 @@ USB_OTG_HostChannelTypeDef;
|
|||
#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
|
||||
#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
||||
#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
||||
#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
|
||||
#define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
||||
|
||||
/****************** Bit definition for SAI_xCLRFR register ******************/
|
||||
#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -107,11 +107,11 @@
|
|||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.3.0
|
||||
* @brief CMSIS Device version number V2.3.2
|
||||
*/
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.3.0
|
||||
* @date 02-March-2015
|
||||
* @version V2.3.2
|
||||
* @date 26-June-2015
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
|
|
|
|||
|
|
@ -80,6 +80,7 @@ typedef enum {
|
|||
PWM_9 = (int)TIM9_BASE,
|
||||
PWM_10 = (int)TIM10_BASE,
|
||||
PWM_11 = (int)TIM11_BASE,
|
||||
PWM_12 = (int)TIM12_BASE,
|
||||
PWM_13 = (int)TIM13_BASE,
|
||||
PWM_14 = (int)TIM14_BASE
|
||||
} PWMName;
|
||||
|
|
|
|||
|
|
@ -87,6 +87,7 @@ typedef enum {
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PWM_9 = (int)TIM9_BASE,
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PWM_10 = (int)TIM10_BASE,
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PWM_11 = (int)TIM11_BASE,
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PWM_12 = (int)TIM12_BASE,
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PWM_13 = (int)TIM13_BASE,
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PWM_14 = (int)TIM14_BASE
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} PWMName;
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|
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@ -82,6 +82,7 @@ typedef enum {
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PWM_9 = (int)TIM9_BASE,
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PWM_10 = (int)TIM10_BASE,
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PWM_11 = (int)TIM11_BASE,
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||||
PWM_12 = (int)TIM12_BASE,
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||||
PWM_13 = (int)TIM13_BASE,
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PWM_14 = (int)TIM14_BASE
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} PWMName;
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|
|
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|||
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@ -86,6 +86,7 @@ typedef enum {
|
|||
PWM_9 = (int)TIM9_BASE,
|
||||
PWM_10 = (int)TIM10_BASE,
|
||||
PWM_11 = (int)TIM11_BASE,
|
||||
PWM_12 = (int)TIM12_BASE,
|
||||
PWM_13 = (int)TIM13_BASE,
|
||||
PWM_14 = (int)TIM14_BASE
|
||||
} PWMName;
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||||
|
|
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|
@ -61,6 +61,9 @@ void pwmout_init(pwmout_t* obj, PinName pin)
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if (obj->pwm == PWM_9) __HAL_RCC_TIM9_CLK_ENABLE();
|
||||
if (obj->pwm == PWM_10) __HAL_RCC_TIM10_CLK_ENABLE();
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||||
if (obj->pwm == PWM_11) __HAL_RCC_TIM11_CLK_ENABLE();
|
||||
#if defined(TIM12_BASE)
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||||
if (obj->pwm == PWM_12) __HAL_RCC_TIM12_CLK_ENABLE();
|
||||
#endif
|
||||
#if defined(TIM13_BASE)
|
||||
if (obj->pwm == PWM_13) __HAL_RCC_TIM13_CLK_ENABLE();
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue