mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #14291 from harmut01/baremetal_freescale
Add bare metal support to freescale targetspull/14367/head
Martin Kojtal
GitHub
commit
e2a5f8f8ba
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@ -1,52 +0,0 @@
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#! armcc -E
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#if !defined(MBED_APP_START)
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#define MBED_APP_START 0x00000000
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#endif
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#if !defined(MBED_APP_SIZE)
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#define MBED_APP_SIZE 0x20000
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#endif
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#if !defined(MBED_RAM_START)
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#define MBED_RAM_START 1FFFF000
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#endif
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#if !defined(MBED_RAM_SIZE)
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#define MBED_RAM_SIZE 0x4000
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#endif
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#define MBED_RAM1_START (MBED_RAM_START+VECTOR_SIZE)
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#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
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# if defined(MBED_BOOT_STACK_SIZE)
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# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
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# else
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# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
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# endif
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#endif
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; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
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#define VECTOR_SIZE 0xC0
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#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE+VECTOR_SIZE)
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM1 MBED_RAM1_START (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
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.ANY (+RW +ZI)
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}
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ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM1_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
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}
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ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; stack
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}
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}
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@ -1,328 +0,0 @@
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;/*****************************************************************************
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; * @file: startup_MKL25Z4.s
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; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
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; * MKL25Z4
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; * @version: 1.1
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; * @date: 2012-6-21
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; *
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; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
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; *****************************************************************************/
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
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DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
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DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
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DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
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DCD Reserved20_IRQHandler ; Reserved interrupt 20
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DCD FTFA_IRQHandler ; FTFA interrupt
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DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
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DCD LLW_IRQHandler ; Low Leakage Wakeup
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DCD I2C0_IRQHandler ; I2C0 interrupt
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DCD I2C1_IRQHandler ; I2C0 interrupt 25
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DCD SPI0_IRQHandler ; SPI0 interrupt
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DCD SPI1_IRQHandler ; SPI1 interrupt
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DCD UART0_IRQHandler ; UART0 status/error interrupt
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DCD UART1_IRQHandler ; UART1 status/error interrupt
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DCD UART2_IRQHandler ; UART2 status/error interrupt
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DCD ADC0_IRQHandler ; ADC0 interrupt
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DCD CMP0_IRQHandler ; CMP0 interrupt
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DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
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DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
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DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
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DCD RTC_IRQHandler ; RTC interrupt
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DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
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DCD PIT_IRQHandler ; PIT timer interrupt
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DCD Reserved39_IRQHandler ; Reserved interrupt 39
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DCD USB0_IRQHandler ; USB0 interrupt
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DCD DAC0_IRQHandler ; DAC interrupt
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DCD TSI0_IRQHandler ; TSI0 interrupt
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DCD MCG_IRQHandler ; MCG interrupt
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DCD LPTimer_IRQHandler ; LPTimer interrupt
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DCD Reserved45_IRQHandler ; Reserved interrupt 45
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DCD PORTA_IRQHandler ; Port A interrupt
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DCD PORTD_IRQHandler ; Port D interrupt
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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; <h> Flash Configuration
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; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
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; <i> and security information that allows the MCU to restrict acces to the FTFL module.
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; <h> Backdoor Comparison Key
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; <o0> Backdoor Key 0 <0x0-0xFF:2>
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; <o1> Backdoor Key 1 <0x0-0xFF:2>
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; <o2> Backdoor Key 2 <0x0-0xFF:2>
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; <o3> Backdoor Key 3 <0x0-0xFF:2>
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; <o4> Backdoor Key 4 <0x0-0xFF:2>
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; <o5> Backdoor Key 5 <0x0-0xFF:2>
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; <o6> Backdoor Key 6 <0x0-0xFF:2>
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; <o7> Backdoor Key 7 <0x0-0xFF:2>
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BackDoorK0 EQU 0xFF
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BackDoorK1 EQU 0xFF
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BackDoorK2 EQU 0xFF
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BackDoorK3 EQU 0xFF
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BackDoorK4 EQU 0xFF
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BackDoorK5 EQU 0xFF
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BackDoorK6 EQU 0xFF
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BackDoorK7 EQU 0xFF
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; </h>
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; <h> Program flash protection bytes (FPROT)
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; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
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; <i> Each bit protects a 1/32 region of the program flash memory.
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; <h> FPROT0
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; <i> Program flash protection bytes
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; <i> 1/32 - 8/32 region
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; <o.0> FPROT0.0
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; <o.1> FPROT0.1
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; <o.2> FPROT0.2
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; <o.3> FPROT0.3
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; <o.4> FPROT0.4
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; <o.5> FPROT0.5
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; <o.6> FPROT0.6
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; <o.7> FPROT0.7
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nFPROT0 EQU 0x00
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FPROT0 EQU nFPROT0:EOR:0xFF
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; </h>
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; <h> FPROT1
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; <i> Program Flash Region Protect Register 1
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; <i> 9/32 - 16/32 region
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; <o.0> FPROT1.0
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; <o.1> FPROT1.1
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; <o.2> FPROT1.2
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; <o.3> FPROT1.3
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; <o.4> FPROT1.4
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; <o.5> FPROT1.5
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; <o.6> FPROT1.6
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; <o.7> FPROT1.7
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nFPROT1 EQU 0x00
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FPROT1 EQU nFPROT1:EOR:0xFF
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; </h>
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; <h> FPROT2
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; <i> Program Flash Region Protect Register 2
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; <i> 17/32 - 24/32 region
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; <o.0> FPROT2.0
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; <o.1> FPROT2.1
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; <o.2> FPROT2.2
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; <o.3> FPROT2.3
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; <o.4> FPROT2.4
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; <o.5> FPROT2.5
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; <o.6> FPROT2.6
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; <o.7> FPROT2.7
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nFPROT2 EQU 0x00
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FPROT2 EQU nFPROT2:EOR:0xFF
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; </h>
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; <h> FPROT3
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; <i> Program Flash Region Protect Register 3
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; <i> 25/32 - 32/32 region
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; <o.0> FPROT3.0
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; <o.1> FPROT3.1
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; <o.2> FPROT3.2
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; <o.3> FPROT3.3
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; <o.4> FPROT3.4
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; <o.5> FPROT3.5
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; <o.6> FPROT3.6
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; <o.7> FPROT3.7
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nFPROT3 EQU 0x00
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FPROT3 EQU nFPROT3:EOR:0xFF
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; </h>
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; </h>
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; </h>
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; <h> Flash nonvolatile option byte (FOPT)
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; <i> Allows the user to customize the operation of the MCU at boot time.
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; <o.0> LPBOOT0
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; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
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; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
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; <o.4> LPBOOT1
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; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
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; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
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; <o.2> NMI_DIS
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; <0=> NMI interrupts are always blocked
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; <1=> NMI pin/interrupts reset default to enabled
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; <o.3> RESET_PIN_CFG
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; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
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; <1=> RESET pin is dedicated
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; <o.3> FAST_INIT
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; <0=> Slower initialization
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; <1=> Fast Initialization
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FOPT EQU 0xFF
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; </h>
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; <h> Flash security byte (FSEC)
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; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
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; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
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; <o.0..1> SEC
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; <2=> MCU security status is unsecure
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; <3=> MCU security status is secure
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; <i> Flash Security
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; <i> This bits define the security state of the MCU.
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; <o.2..3> FSLACC
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; <2=> Freescale factory access denied
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; <3=> Freescale factory access granted
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; <i> Freescale Failure Analysis Access Code
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; <i> This bits define the security state of the MCU.
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; <o.4..5> MEEN
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; <2=> Mass erase is disabled
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; <3=> Mass erase is enabled
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; <i> Mass Erase Enable Bits
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; <i> Enables and disables mass erase capability of the FTFL module
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; <o.6..7> KEYEN
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; <2=> Backdoor key access enabled
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; <3=> Backdoor key access disabled
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; <i> Backdoor key Security Enable
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; <i> These bits enable and disable backdoor key access to the FTFL module.
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FSEC EQU 0xFE
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; </h>
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IF :LNOT::DEF:RAM_TARGET
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AREA |.ARM.__at_0x400|, CODE, READONLY
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DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
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DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
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DCB FPROT0, FPROT1, FPROT2, FPROT3
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DCB FSEC, FOPT, 0xFF, 0xFF
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ENDIF
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT DMA0_IRQHandler [WEAK]
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EXPORT DMA1_IRQHandler [WEAK]
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EXPORT DMA2_IRQHandler [WEAK]
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EXPORT DMA3_IRQHandler [WEAK]
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EXPORT Reserved20_IRQHandler [WEAK]
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EXPORT FTFA_IRQHandler [WEAK]
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EXPORT LVD_LVW_IRQHandler [WEAK]
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EXPORT LLW_IRQHandler [WEAK]
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EXPORT I2C0_IRQHandler [WEAK]
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EXPORT I2C1_IRQHandler [WEAK]
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EXPORT SPI0_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT UART2_IRQHandler [WEAK]
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EXPORT ADC0_IRQHandler [WEAK]
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EXPORT CMP0_IRQHandler [WEAK]
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EXPORT TPM0_IRQHandler [WEAK]
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EXPORT TPM1_IRQHandler [WEAK]
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EXPORT TPM2_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT RTC_Seconds_IRQHandler [WEAK]
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EXPORT PIT_IRQHandler [WEAK]
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EXPORT Reserved39_IRQHandler [WEAK]
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EXPORT USB0_IRQHandler [WEAK]
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EXPORT DAC0_IRQHandler [WEAK]
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EXPORT TSI0_IRQHandler [WEAK]
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EXPORT MCG_IRQHandler [WEAK]
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EXPORT LPTimer_IRQHandler [WEAK]
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EXPORT Reserved45_IRQHandler [WEAK]
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EXPORT PORTA_IRQHandler [WEAK]
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EXPORT PORTD_IRQHandler [WEAK]
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EXPORT DefaultISR [WEAK]
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DMA0_IRQHandler
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DMA1_IRQHandler
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DMA2_IRQHandler
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DMA3_IRQHandler
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Reserved20_IRQHandler
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FTFA_IRQHandler
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LVD_LVW_IRQHandler
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LLW_IRQHandler
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I2C0_IRQHandler
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I2C1_IRQHandler
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SPI0_IRQHandler
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SPI1_IRQHandler
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||||||
UART0_IRQHandler
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||||||
UART1_IRQHandler
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UART2_IRQHandler
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||||||
ADC0_IRQHandler
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||||||
CMP0_IRQHandler
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||||||
TPM0_IRQHandler
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||||||
TPM1_IRQHandler
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TPM2_IRQHandler
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RTC_IRQHandler
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RTC_Seconds_IRQHandler
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|
||||||
PIT_IRQHandler
|
|
||||||
Reserved39_IRQHandler
|
|
||||||
USB0_IRQHandler
|
|
||||||
DAC0_IRQHandler
|
|
||||||
TSI0_IRQHandler
|
|
||||||
MCG_IRQHandler
|
|
||||||
LPTimer_IRQHandler
|
|
||||||
Reserved45_IRQHandler
|
|
||||||
PORTA_IRQHandler
|
|
||||||
PORTD_IRQHandler
|
|
||||||
DefaultISR
|
|
||||||
|
|
||||||
B .
|
|
||||||
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
END
|
|
||||||
|
|
@ -1,5 +1,22 @@
|
||||||
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0plus
|
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0plus
|
||||||
|
|
||||||
|
#if !defined(MBED_APP_START)
|
||||||
|
#define MBED_APP_START 0x00000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(MBED_APP_SIZE)
|
||||||
|
#define MBED_APP_SIZE 0x20000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(MBED_RAM_START)
|
||||||
|
#define MBED_RAM_START 0x1FFFF000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(MBED_RAM_SIZE)
|
||||||
|
#define MBED_RAM_SIZE 0x4000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
|
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
|
||||||
# if defined(MBED_BOOT_STACK_SIZE)
|
# if defined(MBED_BOOT_STACK_SIZE)
|
||||||
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
|
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
|
||||||
|
|
@ -8,25 +25,28 @@
|
||||||
# endif
|
# endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE
|
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
|
||||||
|
#define VECTOR_SIZE 0xC0
|
||||||
|
|
||||||
LR_IROM1 0x00000000 0x20000 { ; load region size_region (32k)
|
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
|
||||||
ER_IROM1 0x00000000 0x20000 { ; load address = execution address
|
|
||||||
|
#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
|
||||||
|
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE)
|
||||||
|
|
||||||
|
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (32k)
|
||||||
|
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
|
||||||
*.o (RESET, +First)
|
*.o (RESET, +First)
|
||||||
*(InRoot$$Sections)
|
*(InRoot$$Sections)
|
||||||
.ANY (+RO)
|
.ANY (+RO)
|
||||||
}
|
}
|
||||||
|
|
||||||
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
|
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE {
|
||||||
; 0x4000 - 0xC0 = 0x3F40
|
|
||||||
RW_IRAM1 0x1FFFF0C0 0x3F40 {
|
|
||||||
.ANY (+RW +ZI)
|
.ANY (+RW +ZI)
|
||||||
}
|
}
|
||||||
|
|
||||||
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x1FFFF000+0x4000-Stack_Size-AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap region growing up
|
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE - RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - MBED_RAM1_START)) { ; Heap region growing up
|
||||||
}
|
}
|
||||||
|
|
||||||
ARM_LIB_STACK 0x1FFFF000+0x4000 EMPTY -Stack_Size { ; Stack region growing down
|
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,21 @@
|
||||||
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0plus
|
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0plus
|
||||||
|
|
||||||
|
#if !defined(MBED_APP_START)
|
||||||
|
#define MBED_APP_START 0x00000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(MBED_APP_SIZE)
|
||||||
|
#define MBED_APP_SIZE 0x40000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(MBED_RAM_START)
|
||||||
|
#define MBED_RAM_START 0x1FFFE000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined(MBED_RAM_SIZE)
|
||||||
|
#define MBED_RAM_SIZE 0x8000
|
||||||
|
#endif
|
||||||
|
|
||||||
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
|
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
|
||||||
# if defined(MBED_BOOT_STACK_SIZE)
|
# if defined(MBED_BOOT_STACK_SIZE)
|
||||||
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
|
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
|
||||||
|
|
@ -8,24 +24,29 @@
|
||||||
# endif
|
# endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE
|
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
|
||||||
|
|
||||||
LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
|
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
|
||||||
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
#define VECTOR_SIZE 0xC0
|
||||||
|
|
||||||
|
#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
|
||||||
|
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE)
|
||||||
|
|
||||||
|
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (256k)
|
||||||
|
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
|
||||||
*.o (RESET, +First)
|
*.o (RESET, +First)
|
||||||
*(InRoot$$Sections)
|
*(InRoot$$Sections)
|
||||||
.ANY (+RO)
|
.ANY (+RO)
|
||||||
}
|
}
|
||||||
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
|
|
||||||
; 0x8000 - 0xC0 = 0x7F40
|
; 0x8000 - 0xC0 = 0x7F40
|
||||||
RW_IRAM1 0x1FFFE0C0 0x7F40 {
|
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE {
|
||||||
.ANY (+RW +ZI)
|
.ANY (+RW +ZI)
|
||||||
}
|
}
|
||||||
|
|
||||||
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x1FFFE000+0x8000-Stack_Size-AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap region growing up
|
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE - RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - MBED_RAM1_START)) { ; Heap region growing up
|
||||||
}
|
}
|
||||||
|
|
||||||
ARM_LIB_STACK 0x1FFFE000+0x8000 EMPTY -Stack_Size { ; Stack region growing down
|
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -459,7 +459,20 @@
|
||||||
"release_versions": [
|
"release_versions": [
|
||||||
"5"
|
"5"
|
||||||
],
|
],
|
||||||
"device_name": "MKL25Z128xxx4"
|
"device_name": "MKL25Z128xxx4",
|
||||||
|
"supported_c_libs": {
|
||||||
|
"arm": [
|
||||||
|
"std",
|
||||||
|
"small"
|
||||||
|
],
|
||||||
|
"gcc_arm": [
|
||||||
|
"std",
|
||||||
|
"small"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"supported_application_profiles": [
|
||||||
|
"full", "bare-metal"
|
||||||
|
]
|
||||||
},
|
},
|
||||||
"KL46Z": {
|
"KL46Z": {
|
||||||
"supported_form_factors": [
|
"supported_form_factors": [
|
||||||
|
|
@ -506,7 +519,20 @@
|
||||||
"5"
|
"5"
|
||||||
],
|
],
|
||||||
"device_name": "MKL46Z256xxx4",
|
"device_name": "MKL46Z256xxx4",
|
||||||
"bootloader_supported": true
|
"bootloader_supported": true,
|
||||||
|
"supported_c_libs": {
|
||||||
|
"arm": [
|
||||||
|
"std",
|
||||||
|
"small"
|
||||||
|
],
|
||||||
|
"gcc_arm": [
|
||||||
|
"std",
|
||||||
|
"small"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"supported_application_profiles": [
|
||||||
|
"full", "bare-metal"
|
||||||
|
]
|
||||||
},
|
},
|
||||||
"MCU_K22F512": {
|
"MCU_K22F512": {
|
||||||
"core": "Cortex-M4F",
|
"core": "Cortex-M4F",
|
||||||
|
|
@ -563,7 +589,20 @@
|
||||||
"USBDEVICE",
|
"USBDEVICE",
|
||||||
"FLASH"
|
"FLASH"
|
||||||
],
|
],
|
||||||
"device_name": "MK22DN512xxx5"
|
"device_name": "MK22DN512xxx5",
|
||||||
|
"supported_c_libs": {
|
||||||
|
"arm": [
|
||||||
|
"std",
|
||||||
|
"small"
|
||||||
|
],
|
||||||
|
"gcc_arm": [
|
||||||
|
"std",
|
||||||
|
"small"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"supported_application_profiles": [
|
||||||
|
"full", "bare-metal"
|
||||||
|
]
|
||||||
},
|
},
|
||||||
"K22F": {
|
"K22F": {
|
||||||
"supported_form_factors": [
|
"supported_form_factors": [
|
||||||
|
|
@ -637,7 +676,20 @@
|
||||||
"release_versions": [
|
"release_versions": [
|
||||||
"5"
|
"5"
|
||||||
],
|
],
|
||||||
"device_name": "MKL43Z256xxx4"
|
"device_name": "MKL43Z256xxx4",
|
||||||
|
"supported_c_libs": {
|
||||||
|
"arm": [
|
||||||
|
"std",
|
||||||
|
"small"
|
||||||
|
],
|
||||||
|
"gcc_arm": [
|
||||||
|
"std",
|
||||||
|
"small"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"supported_application_profiles": [
|
||||||
|
"full", "bare-metal"
|
||||||
|
]
|
||||||
},
|
},
|
||||||
"KW41Z": {
|
"KW41Z": {
|
||||||
"supported_form_factors": [
|
"supported_form_factors": [
|
||||||
|
|
@ -1036,7 +1088,10 @@
|
||||||
"iar": [
|
"iar": [
|
||||||
"std"
|
"std"
|
||||||
]
|
]
|
||||||
}
|
},
|
||||||
|
"supported_application_profiles": [
|
||||||
|
"full", "bare-metal"
|
||||||
|
]
|
||||||
},
|
},
|
||||||
"K82F": {
|
"K82F": {
|
||||||
"supported_form_factors": [
|
"supported_form_factors": [
|
||||||
|
|
@ -1096,7 +1151,20 @@
|
||||||
"release_versions": [
|
"release_versions": [
|
||||||
"5"
|
"5"
|
||||||
],
|
],
|
||||||
"device_name": "MK82FN256xxx15"
|
"device_name": "MK82FN256xxx15",
|
||||||
|
"supported_c_libs": {
|
||||||
|
"arm": [
|
||||||
|
"std",
|
||||||
|
"small"
|
||||||
|
],
|
||||||
|
"gcc_arm": [
|
||||||
|
"std",
|
||||||
|
"small"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
"supported_application_profiles": [
|
||||||
|
"full", "bare-metal"
|
||||||
|
]
|
||||||
},
|
},
|
||||||
"MCU_STM32": {
|
"MCU_STM32": {
|
||||||
"inherits": [
|
"inherits": [
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue