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Define CMSIS_VECTAB_VIRTUAL for M0 targets 

Define CMSIS_VECTAB_VIRTUAL for the M0 targets which have a
corresponding driver. The only M0 target missing this is the LPC4330_M0
which is not part of the 2 or 5 release.
pull/4521/head
Russ Butler 2017-06-08 22:31:41 -05:00 committed by adbridge
parent d5320977ff
commit e155d1a830
1 changed files with 25 additions and 10 deletions
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35
targets/targets.json
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@ -56,6 +56,7 @@
"inherits": ["LPCTarget"], "inherits": ["LPCTarget"],
"core": "Cortex-M0", "core": "Cortex-M0",
"extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11CXX"], "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11CXX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"device_has": ["ANALOGIN", "CAN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "CAN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"device_name": "LPC11C24FBD48/301" "device_name": "LPC11C24FBD48/301"
@ -65,6 +66,7 @@
"core": "Cortex-M0", "core": "Cortex-M0",
"default_toolchain": "uARM", "default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11XX"], "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11XX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"default_lib": "small", "default_lib": "small",
@ -76,6 +78,7 @@
"core": "Cortex-M0", "core": "Cortex-M0",
"default_toolchain": "uARM", "default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX", "LPC11U24_401"], "extra_labels": ["NXP", "LPC11UXX", "LPC11U24_401"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"detect_code": ["1040"], "detect_code": ["1040"],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
@ -94,6 +97,7 @@
"inherits": ["LPCTarget"], "inherits": ["LPCTarget"],
"core": "Cortex-M0", "core": "Cortex-M0",
"extra_labels": ["NXP", "LPC11UXX"], "extra_labels": ["NXP", "LPC11UXX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"device_name": "LPC11U24FHI33/301" "device_name": "LPC11U24FHI33/301"
@ -103,6 +107,7 @@
"core": "Cortex-M0", "core": "Cortex-M0",
"default_toolchain": "uARM", "default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX"], "extra_labels": ["NXP", "LPC11UXX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"], "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small", "default_lib": "small",
@ -120,6 +125,7 @@
"core": "Cortex-M0", "core": "Cortex-M0",
"default_toolchain": "uARM", "default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX"], "extra_labels": ["NXP", "LPC11UXX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"], "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small", "default_lib": "small",
@ -131,6 +137,7 @@
"core": "Cortex-M0", "core": "Cortex-M0",
"default_toolchain": "uARM", "default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"], "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"], "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small", "default_lib": "small",
@ -142,6 +149,7 @@
"core": "Cortex-M0", "core": "Cortex-M0",
"default_toolchain": "uARM", "default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"], "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"], "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small", "default_lib": "small",
@ -155,6 +163,7 @@
"core": "Cortex-M0", "core": "Cortex-M0",
"default_toolchain": "uARM", "default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"], "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"], "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
"default_lib": "small", "default_lib": "small",
@ -165,6 +174,7 @@
"core": "Cortex-M0", "core": "Cortex-M0",
"default_toolchain": "uARM", "default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX"], "extra_labels": ["NXP", "LPC11UXX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"default_lib": "small", "default_lib": "small",
"device_name": "LPC11U37FBD64/501" "device_name": "LPC11U37FBD64/501"
@ -179,6 +189,7 @@
"core": "Cortex-M0", "core": "Cortex-M0",
"default_toolchain": "uARM", "default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX", "LPC11U37_501"], "extra_labels": ["NXP", "LPC11UXX", "LPC11U37_501"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
"inherits": ["LPCTarget"], "inherits": ["LPCTarget"],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"], "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
@ -384,6 +395,7 @@
"core": "Cortex-M0", "core": "Cortex-M0",
"default_toolchain": "uARM", "default_toolchain": "uARM",
"extra_labels": ["NXP", "LPC11UXX"], "extra_labels": ["NXP", "LPC11UXX"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR"],
"inherits": ["LPCTarget"], "inherits": ["LPCTarget"],
"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"], "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
@ -664,7 +676,7 @@
"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
"inherits": ["Target"], "inherits": ["Target"],
"detect_code": ["0725"], "detect_code": ["0725"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"], "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"default_lib": "small", "default_lib": "small",
"release_versions": ["2"], "release_versions": ["2"],
@ -678,7 +690,7 @@
"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
"inherits": ["Target"], "inherits": ["Target"],
"detect_code": ["0791"], "detect_code": ["0791"],
"macros": ["RTC_LSI=1", "TRANSACTION_QUEUE_SIZE_SPI=2"], "macros": ["RTC_LSI=1", "TRANSACTION_QUEUE_SIZE_SPI=2", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"default_lib": "small", "default_lib": "small",
"release_versions": ["2"], "release_versions": ["2"],
@ -692,7 +704,7 @@
"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
"inherits": ["Target"], "inherits": ["Target"],
"detect_code": ["0785"], "detect_code": ["0785"],
"macros": ["RTC_LSI=1", "TRANSACTION_QUEUE_SIZE_SPI=2"], "macros": ["RTC_LSI=1", "TRANSACTION_QUEUE_SIZE_SPI=2", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"default_lib": "small", "default_lib": "small",
"release_versions": ["2"], "release_versions": ["2"],
@ -706,7 +718,7 @@
"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
"inherits": ["Target"], "inherits": ["Target"],
"detect_code": ["0755"], "detect_code": ["0755"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"], "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"release_versions": ["2", "5"], "release_versions": ["2", "5"],
"device_name": "STM32F070RB" "device_name": "STM32F070RB"
@ -719,7 +731,7 @@
"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
"inherits": ["Target"], "inherits": ["Target"],
"detect_code": ["0730"], "detect_code": ["0730"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"], "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"release_versions": ["2", "5"], "release_versions": ["2", "5"],
"device_name": "STM32F072RB" "device_name": "STM32F072RB"
@ -732,7 +744,7 @@
"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
"inherits": ["Target"], "inherits": ["Target"],
"detect_code": ["0750"], "detect_code": ["0750"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"], "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"release_versions": ["2", "5"], "release_versions": ["2", "5"],
"device_name": "STM32F091RC" "device_name": "STM32F091RC"
@ -1186,7 +1198,7 @@
"default_toolchain": "ARM", "default_toolchain": "ARM",
"extra_labels": ["STM", "STM32F0", "STM32F051", "STM32F051R8"], "extra_labels": ["STM", "STM32F0", "STM32F051", "STM32F051R8"],
"supported_toolchains": ["GCC_ARM"], "supported_toolchains": ["GCC_ARM"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"], "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"device_name": "STM32F051R8" "device_name": "STM32F051R8"
}, },
@ -1458,7 +1470,7 @@
"inherits": ["Target"], "inherits": ["Target"],
"core": "Cortex-M0", "core": "Cortex-M0",
"OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex", "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
"macros": ["NRF51", "TARGET_NRF51822"], "macros": ["NRF51", "TARGET_NRF51822", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"MERGE_BOOTLOADER": false, "MERGE_BOOTLOADER": false,
"extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822"], "extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822"],
"OUTPUT_EXT": "hex", "OUTPUT_EXT": "hex",
@ -1870,7 +1882,7 @@
"core": "Cortex-M0", "core": "Cortex-M0",
"supported_toolchains": ["ARM"], "supported_toolchains": ["ARM"],
"extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0"], "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0"],
"macros": ["CMSDK_CM0"], "macros": ["CMSDK_CM0", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"], "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
"release_versions": ["2"] "release_versions": ["2"]
}, },
@ -2545,6 +2557,7 @@
"supported_form_factors": ["ARDUINO"], "supported_form_factors": ["ARDUINO"],
"core": "Cortex-M0", "core": "Cortex-M0",
"extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500"], "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"], "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
"inherits": ["Target"], "inherits": ["Target"],
"device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
@ -2554,6 +2567,7 @@
"supported_form_factors": ["ARDUINO"], "supported_form_factors": ["ARDUINO"],
"core": "Cortex-M0", "core": "Cortex-M0",
"extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500P"], "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500P"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"], "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
"inherits": ["Target"], "inherits": ["Target"],
"device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
@ -2563,6 +2577,7 @@
"inherits": ["Target"], "inherits": ["Target"],
"core": "Cortex-M0", "core": "Cortex-M0",
"extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500ECO"], "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500ECO"],
"macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"], "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
"device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"release_versions": ["2", "5"] "release_versions": ["2", "5"]
@ -2886,7 +2901,7 @@
"default_toolchain": "GCC_ARM", "default_toolchain": "GCC_ARM",
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"], "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
"extra_labels": ["ublox"], "extra_labels": ["ublox"],
"macros": ["TARGET_PROCESSOR_FAMILY_BOUDICA", "BOUDICA_SARA", "NDEBUG=1"], "macros": ["TARGET_PROCESSOR_FAMILY_BOUDICA", "BOUDICA_SARA", "NDEBUG=1", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
"public": false, "public": false,
"target_overrides": { "target_overrides": {
"*": { "*": {