mirror of https://github.com/ARMmbed/mbed-os.git
Updated files used by IAR compiler with those available from STM32CubeF4 package
Rafal Fabich
parent
4394cf7e11
commit
e0dd831b4d
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@ -1,9 +1,9 @@
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;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
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;* File Name : startup_stm32f411xe.s
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;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
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;* File Name : startup_stm32f410rx.s
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;* Author : MCD Application Team
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;* Version : V2.1.0
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;* Date : 19-June-2014
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;* Description : STM32F411xExx devices vector table for EWARM toolchain.
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;* Version : V2.4.1
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;* Date : 09-October-2015
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;* Description : STM32F410Rx devices vector table for EWARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == _iar_program_start,
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@ -113,12 +113,12 @@ __vector_table
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DCD 0 ; Reserved
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DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
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DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
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DCD TIM1_UP_IRQHandler ; TIM1 Update
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DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM4_IRQHandler ; TIM4
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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@ -130,19 +130,19 @@ __vector_table
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DCD 0 ; Reserved
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DCD EXTI15_10_IRQHandler ; External Line[15:10]s
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DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
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DCD 0 ; Reserved
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DCD SDIO_IRQHandler ; SDIO
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DCD 0 ; Reserved
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DCD TIM5_IRQHandler ; TIM5
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DCD SPI3_IRQHandler ; SPI3
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
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DCD 0 ; Reserved
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DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
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DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
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@ -155,13 +155,11 @@ __vector_table
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD OTG_FS_IRQHandler ; USB OTG FS
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DCD 0 ; Reserved
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DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
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DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
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DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
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DCD USART6_IRQHandler ; USART6
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DCD I2C3_EV_IRQHandler ; I2C3 event
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DCD I2C3_ER_IRQHandler ; I2C3 error
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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@ -169,11 +167,25 @@ __vector_table
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD RNG_IRQHandler ; RNG
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DCD FPU_IRQHandler ; FPU
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SPI4_IRQHandler ; SPI4
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DCD 0 ; Reserved
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DCD SPI5_IRQHandler ; SPI5
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event
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DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error
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DCD LPTIM1_IRQHandler ; LP TIM1
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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@ -339,10 +351,10 @@ EXTI9_5_IRQHandler
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TIM1_BRK_TIM9_IRQHandler
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B TIM1_BRK_TIM9_IRQHandler
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PUBWEAK TIM1_UP_TIM10_IRQHandler
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PUBWEAK TIM1_UP_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM1_UP_TIM10_IRQHandler
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B TIM1_UP_TIM10_IRQHandler
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TIM1_UP_IRQHandler
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B TIM1_UP_IRQHandler
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PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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@ -354,21 +366,6 @@ TIM1_TRG_COM_TIM11_IRQHandler
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TIM1_CC_IRQHandler
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B TIM1_CC_IRQHandler
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PUBWEAK TIM2_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM2_IRQHandler
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B TIM2_IRQHandler
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PUBWEAK TIM3_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM3_IRQHandler
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B TIM3_IRQHandler
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PUBWEAK TIM4_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM4_IRQHandler
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B TIM4_IRQHandler
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PUBWEAK I2C1_EV_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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I2C1_EV_IRQHandler
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@ -419,30 +416,20 @@ EXTI15_10_IRQHandler
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RTC_Alarm_IRQHandler
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B RTC_Alarm_IRQHandler
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PUBWEAK OTG_FS_WKUP_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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OTG_FS_WKUP_IRQHandler
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B OTG_FS_WKUP_IRQHandler
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PUBWEAK DMA1_Stream7_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA1_Stream7_IRQHandler
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B DMA1_Stream7_IRQHandler
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PUBWEAK SDIO_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SDIO_IRQHandler
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B SDIO_IRQHandler
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PUBWEAK TIM5_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIM5_IRQHandler
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B TIM5_IRQHandler
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PUBWEAK SPI3_IRQHandler
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PUBWEAK TIM6_DAC_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SPI3_IRQHandler
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B SPI3_IRQHandler
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TIM6_DAC_IRQHandler
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B TIM6_DAC_IRQHandler
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PUBWEAK DMA2_Stream0_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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@ -469,11 +456,6 @@ DMA2_Stream3_IRQHandler
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DMA2_Stream4_IRQHandler
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B DMA2_Stream4_IRQHandler
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PUBWEAK OTG_FS_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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OTG_FS_IRQHandler
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B OTG_FS_IRQHandler
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PUBWEAK DMA2_Stream5_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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DMA2_Stream5_IRQHandler
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@ -494,30 +476,35 @@ DMA2_Stream7_IRQHandler
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USART6_IRQHandler
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B USART6_IRQHandler
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PUBWEAK I2C3_EV_IRQHandler
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PUBWEAK RNG_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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I2C3_EV_IRQHandler
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B I2C3_EV_IRQHandler
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PUBWEAK I2C3_ER_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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I2C3_ER_IRQHandler
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B I2C3_ER_IRQHandler
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RNG_IRQHandler
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B RNG_IRQHandler
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PUBWEAK FPU_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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FPU_IRQHandler
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B FPU_IRQHandler
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PUBWEAK SPI4_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SPI4_IRQHandler
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B SPI4_IRQHandler
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PUBWEAK SPI5_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SPI5_IRQHandler
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B SPI5_IRQHandler
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PUBWEAK FMPI2C1_EV_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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FMPI2C1_EV_IRQHandler
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B FMPI2C1_EV_IRQHandler
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PUBWEAK FMPI2C1_ER_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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FMPI2C1_ER_IRQHandler
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B FMPI2C1_ER_IRQHandler
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PUBWEAK LPTIM1_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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LPTIM1_IRQHandler
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B LPTIM1_IRQHandler
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END
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -0,0 +1,31 @@
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
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/*-Specials-*/
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define symbol __ICFEDIT_intvec_start__ = 0x08000000;
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
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define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_cstack__ = 0x400;
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define symbol __ICFEDIT_size_heap__ = 0x200;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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initialize by copy { readwrite };
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do not initialize { section .noinit };
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place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place in RAM_region { readwrite,
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block CSTACK, block HEAP };
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@ -0,0 +1,31 @@
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
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/*-Specials-*/
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define symbol __ICFEDIT_intvec_start__ = 0x20000000;
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x20003FFF;
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define symbol __ICFEDIT_region_RAM_start__ = 0x20004000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_cstack__ = 0x400;
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define symbol __ICFEDIT_size_heap__ = 0x200;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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initialize by copy { readwrite };
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do not initialize { section .noinit };
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place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place in RAM_region { readwrite,
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block CSTACK, block HEAP };
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@ -1,31 +0,0 @@
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/* [ROM = 128kb = 0x20000] */
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define symbol __intvec_start__ = 0x08000000;
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define symbol __region_ROM_start__ = 0x08000000;
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define symbol __region_ROM_end__ = 0x0801FFFF;
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/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */
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define symbol __NVIC_start__ = 0x20000000;
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define symbol __NVIC_end__ = 0x20000197; /* Aligned on 8 bytes */
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define symbol __region_RAM_start__ = 0x20000198;
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define symbol __region_RAM_end__ = 0x20007FFF;
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/* Memory regions */
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
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define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
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/* Stack and Heap */
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/*Heap 1/4 of ram and stack 1/8*/
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define symbol __size_cstack__ = 0x1000;
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define symbol __size_heap__ = 0x2000;
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define block CSTACK with alignment = 8, size = __size_cstack__ { };
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define block HEAP with alignment = 8, size = __size_heap__ { };
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define block STACKHEAP with fixed order { block HEAP, block CSTACK };
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initialize by copy with packing = zeros { readwrite };
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do not initialize { section .noinit };
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place at address mem:__intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place in RAM_region { readwrite, block STACKHEAP };
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