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STM32G0: align code with CubeUpdate script

pull/15075/head
Jerome Coutant 2021-09-14 16:30:01 +02:00
parent 4cfbea43ca
commit e0877e4077
66 changed files with 360 additions and 467 deletions
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22
targets/TARGET_STM/TARGET_STM32G0/CMakeLists.txt
View File

@ -1,16 +1,21 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(TARGET_STM32G030xx EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32G031xx EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32G041xx EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32G070xx EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32G071xx EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32G081xx EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32G030x8 EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32G031x8 EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32G041x8 EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32G070xB EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32G071xB EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32G081xB EXCLUDE_FROM_ALL)
add_subdirectory(STM32Cube_FW EXCLUDE_FROM_ALL)
add_library(mbed-stm32g0 INTERFACE)
target_include_directories(mbed-stm32g0
INTERFACE
.
)
target_sources(mbed-stm32g0
INTERFACE
analogin_device.c
@ -23,9 +28,4 @@ target_sources(mbed-stm32g0
spi_api.c
)
target_include_directories(mbed-stm32g0
INTERFACE
.
)
target_link_libraries(mbed-stm32g0 INTERFACE mbed-stm mbed-stm32g0cube-fw)

8
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/PeripheralNames.h → targets/TARGET_STM/TARGET_STM32G0/PeripheralNames.h
View File

@ -25,15 +25,21 @@ typedef enum {
ADC_1 = (int)ADC1_BASE
} ADCName;
#if defined DAC_BASE
typedef enum {
DAC_1 = (int)DAC_BASE
} DACName;
#endif
typedef enum {
UART_1 = (int)USART1_BASE,
UART_2 = (int)USART2_BASE,
#if defined USART3_BASE
UART_3 = (int)USART3_BASE,
#endif
#if defined USART4_BASE
UART_4 = (int)USART4_BASE,
#endif
LPUART_1 = (int)LPUART1_BASE
} UARTName;
@ -53,7 +59,9 @@ typedef enum {
PWM_2 = (int)TIM2_BASE,
PWM_3 = (int)TIM3_BASE,
PWM_14 = (int)TIM14_BASE,
#if defined TIM15_BASE
PWM_15 = (int)TIM15_BASE,
#endif
PWM_16 = (int)TIM16_BASE,
PWM_17 = (int)TIM17_BASE
} PWMName;

33
targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/stm32g0xx_hal_conf.h
View File

@ -73,83 +73,63 @@ extern "C" {
#if !defined (USE_HAL_ADC_REGISTER_CALLBACKS)
#define USE_HAL_ADC_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_CEC_REGISTER_CALLBACKS)
#define USE_HAL_CEC_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_COMP_REGISTER_CALLBACKS)
#define USE_HAL_COMP_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_CRYP_REGISTER_CALLBACKS)
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_DAC_REGISTER_CALLBACKS)
#define USE_HAL_DAC_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_FDCAN_REGISTER_CALLBACKS)
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_I2C_REGISTER_CALLBACKS)
#define USE_HAL_I2C_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_I2S_REGISTER_CALLBACKS)
#define USE_HAL_I2S_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_IRDA_REGISTER_CALLBACKS)
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_LPTIM_REGISTER_CALLBACKS)
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_HCD_REGISTER_CALLBACKS)
#define USE_HAL_HCD_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_PCD_REGISTER_CALLBACKS)
#define USE_HAL_PCD_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_RNG_REGISTER_CALLBACKS)
#define USE_HAL_RNG_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_RTC_REGISTER_CALLBACKS)
#define USE_HAL_RTC_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_SMARTCARD_REGISTER_CALLBACKS)
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_SMBUS_REGISTER_CALLBACKS)
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_SPI_REGISTER_CALLBACKS)
#define USE_HAL_SPI_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_TIM_REGISTER_CALLBACKS)
#define USE_HAL_TIM_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_UART_REGISTER_CALLBACKS)
#define USE_HAL_UART_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_USART_REGISTER_CALLBACKS)
#define USE_HAL_USART_REGISTER_CALLBACKS 0u
#endif
#if !defined (USE_HAL_WWDG_REGISTER_CALLBACKS)
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u
#endif
@ -259,6 +239,7 @@ in voltage and temperature.*/
#define USE_HAL_CRYP_SUSPEND_RESUME 1U
#endif
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
@ -394,17 +375,7 @@ in voltage and temperature.*/
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for functions parameters check.
* @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line);
#include "stm32_assert.h" // MBED patch
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */

7
targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/system_stm32g0xx.c
View File

@ -166,15 +166,10 @@
* @param None
* @retval None
*/
void SystemInit(void)
__WEAK void SystemInit(void)
{
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
#include "nvic_addr.h" // MBED
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED
#endif
}
/**

22
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/CMakeLists.txt → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/CMakeLists.txt
View File

@ -3,24 +3,24 @@
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g030xx.S)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g030xx.ld)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g030x8.ld)
elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g030xx.S)
set(LINKER_FILE TOOLCHAIN_ARM/stm32g030xx.sct)
set(LINKER_FILE TOOLCHAIN_ARM/stm32g030x8.sct)
endif()
add_library(mbed-stm32g030xx INTERFACE)
add_library(mbed-stm32g030x8 INTERFACE)
target_sources(mbed-stm32g030xx
INTERFACE
${STARTUP_FILE}
)
target_include_directories(mbed-stm32g030xx
target_include_directories(mbed-stm32g030x8
INTERFACE
.
)
mbed_set_linker_script(mbed-stm32g030xx ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
target_sources(mbed-stm32g030x8
INTERFACE
${STARTUP_FILE}
)
target_link_libraries(mbed-stm32g030xx INTERFACE mbed-stm32g0)
mbed_set_linker_script(mbed-stm32g030x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
target_link_libraries(mbed-stm32g030x8 INTERFACE mbed-stm32g0)

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_ARM/startup_stm32g030xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_ARM/startup_stm32g030xx.S
View File

12
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_ARM/stm32g031xx.sct → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_ARM/stm32g030x8.sct
View File

@ -25,13 +25,13 @@
#define MBED_APP_SIZE MBED_ROM_SIZE
#endif
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#if defined(MBED_BOOT_STACK_SIZE)
#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
#else
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
#endif
#endif
/* Round up VECTORS_SIZE to 8 bytes */

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_GCC_ARM/startup_stm32g030xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_GCC_ARM/startup_stm32g030xx.S
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_GCC_ARM/stm32g030xx.ld → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_GCC_ARM/stm32g030x8.ld
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_IAR/startup_stm32g030xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_IAR/startup_stm32g030xx.S
View File

2
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_IAR/stm32g041xx.icf → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/TOOLCHAIN_IAR/stm32g030x8.icf
View File

@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) {
}
if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
/* This value is normally defined by the tools
/* This value is normally defined by the tools
to 0x1000 for bare metal and 0x400 for RTOS */
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
}

4
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/cmsis_nvic.h → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030x8/cmsis_nvic.h
View File

@ -22,11 +22,7 @@
#endif
#if !defined(MBED_ROM_SIZE)
#if defined (TARGET_NUCLEO_G031K8)
#define MBED_ROM_SIZE 0x10000 // 64 KB
#else
#error "MBED_ROM_SIZE not defined"
#endif
#endif
#if !defined(MBED_RAM_START)

23
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/CMakeLists.txt → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/CMakeLists.txt
View File

@ -5,24 +5,25 @@ add_subdirectory(TARGET_NUCLEO_G031K8 EXCLUDE_FROM_ALL)
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g031xx.S)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g031xx.ld)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g031x8.ld)
elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g031xx.S)
set(LINKER_FILE TOOLCHAIN_ARM/stm32g031xx.sct)
set(LINKER_FILE TOOLCHAIN_ARM/stm32g031x8.sct)
endif()
add_library(mbed-stm32g031xx INTERFACE)
add_library(mbed-stm32g031x8 INTERFACE)
target_sources(mbed-stm32g031xx
INTERFACE
${STARTUP_FILE}
)
target_include_directories(mbed-stm32g031xx
target_include_directories(mbed-stm32g031x8
INTERFACE
.
)
mbed_set_linker_script(mbed-stm32g031xx ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
target_sources(mbed-stm32g031x8
INTERFACE
${STARTUP_FILE}
system_clock.c
)
target_link_libraries(mbed-stm32g031xx INTERFACE mbed-stm32g0)
mbed_set_linker_script(mbed-stm32g031x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
target_link_libraries(mbed-stm32g031x8 INTERFACE mbed-stm32g0)

3
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/CMakeLists.txt → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TARGET_NUCLEO_G031K8/CMakeLists.txt
View File

@ -6,7 +6,6 @@ add_library(mbed-nucleo-g031k8 INTERFACE)
target_sources(mbed-nucleo-g031k8
INTERFACE
PeripheralPins.c
system_clock.c
)
target_include_directories(mbed-nucleo-g031k8
@ -14,4 +13,4 @@ target_include_directories(mbed-nucleo-g031k8
.
)
target_link_libraries(mbed-nucleo-g031k8 INTERFACE mbed-stm32g031xx)
target_link_libraries(mbed-nucleo-g031k8 INTERFACE mbed-stm32g031x8)

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralPins.c → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TARGET_NUCLEO_G031K8/PeripheralPins.c
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TARGET_NUCLEO_G031K8/PinNames.h
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_ARM/startup_stm32g031xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_ARM/startup_stm32g031xx.S
View File

12
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_ARM/stm32g030xx.sct → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_ARM/stm32g031x8.sct
View File

@ -25,13 +25,13 @@
#define MBED_APP_SIZE MBED_ROM_SIZE
#endif
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#if defined(MBED_BOOT_STACK_SIZE)
#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
#else
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
#endif
#endif
/* Round up VECTORS_SIZE to 8 bytes */

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_GCC_ARM/startup_stm32g031xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_GCC_ARM/startup_stm32g031xx.S
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_GCC_ARM/stm32g031xx.ld → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_GCC_ARM/stm32g031x8.ld
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_IAR/startup_stm32g031xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_IAR/startup_stm32g031xx.S
View File

4
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TOOLCHAIN_IAR/stm32g031xx.icf → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/TOOLCHAIN_IAR/stm32g031x8.icf
View File

@ -18,7 +18,7 @@
/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
define symbol VECTORS = 46; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
define symbol HEAP_SIZE = 0x1000;
/* Common - Do not change */
@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) {
}
if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
/* This value is normally defined by the tools
/* This value is normally defined by the tools
to 0x1000 for bare metal and 0x400 for RTOS */
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
}

4
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/cmsis_nvic.h → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/cmsis_nvic.h
View File

@ -22,7 +22,7 @@
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x20000
#define MBED_ROM_SIZE 0x10000 // 64 KB
#endif
#if !defined(MBED_RAM_START)
@ -30,7 +30,7 @@
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x9000
#define MBED_RAM_SIZE 0x2000 // 8 KB
#endif
#define NVIC_NUM_VECTORS 48

28
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031x8/system_clock.c
View File

@ -2,7 +2,7 @@
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
*
* Copyright (c) 2020 STMicroelectronics.
* Copyright (c) 2019-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@ -14,9 +14,11 @@
*/
/**
* This file configures the system clock as follows:
*-----------------------------------------------------------------
* System clock source | USE_PLL_HSI (internal 16 MHz)
* This file configures the system clock depending on config from targets.json:
*-----------------------------------------------------------------------------
* System clock source | 1- USE_PLL_HSE_EXTC (external clock)
* | 2- USE_PLL_HSE_XTAL (external xtal)
* | 3- USE_PLL_HSI (internal 16 MHz)
*-----------------------------------------------------------------
* SYSCLK(MHz) | 64
* AHBCLK (MHz) | 64
@ -28,7 +30,8 @@
#include "stm32g0xx.h"
#include "mbed_error.h"
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
// clock source is selected with CLOCK_SOURCE in json config
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN)
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
#define USE_PLL_HSI 0x2 // Use HSI internal clock
@ -44,12 +47,13 @@ uint8_t SetSysClock_PLL_HSI(void);
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c)
* and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c)
* @param None
* @retval None
*/
void SetSysClock(void)
MBED_WEAK void SetSysClock(void)
{
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
/* 1- Try to start with HSE and external clock */
@ -72,19 +76,15 @@ void SetSysClock(void)
}
}
}
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
}
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
return 0;
return 0; // FAIL
}
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */

58
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralNames.h
View File

@ -1,58 +0,0 @@
/* mbed Microcontroller Library
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
*
* Copyright (c) 2015 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ADC_1 = (int)ADC1_BASE
} ADCName;
typedef enum {
UART_1 = (int)USART1_BASE,
UART_2 = (int)USART2_BASE,
LPUART_1 = (int)LPUART1_BASE
} UARTName;
#define DEVICE_SPI_COUNT 2
typedef enum {
SPI_1 = (int)SPI1_BASE,
SPI_2 = (int)SPI2_BASE
} SPIName;
typedef enum {
I2C_1 = (int)I2C1_BASE,
I2C_2 = (int)I2C2_BASE
} I2CName;
typedef enum {
PWM_1 = (int)TIM1_BASE,
PWM_2 = (int)TIM2_BASE,
PWM_3 = (int)TIM3_BASE,
PWM_14 = (int)TIM14_BASE,
PWM_16 = (int)TIM16_BASE,
PWM_17 = (int)TIM17_BASE
} PWMName;
#ifdef __cplusplus
}
#endif
#endif

22
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/CMakeLists.txt → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/CMakeLists.txt
View File

@ -3,24 +3,24 @@
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g041xx.S)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g041xx.ld)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g041x8.ld)
elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g041xx.S)
set(LINKER_FILE TOOLCHAIN_ARM/stm32g041xx.sct)
set(LINKER_FILE TOOLCHAIN_ARM/stm32g041x8.sct)
endif()
add_library(mbed-stm32g041xx INTERFACE)
add_library(mbed-stm32g041x8 INTERFACE)
target_sources(mbed-stm32g041xx
INTERFACE
${STARTUP_FILE}
)
target_include_directories(mbed-stm32g041xx
target_include_directories(mbed-stm32g041x8
INTERFACE
.
)
mbed_set_linker_script(mbed-stm32g041xx ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
target_sources(mbed-stm32g041x8
INTERFACE
${STARTUP_FILE}
)
target_link_libraries(mbed-stm32g041xx INTERFACE mbed-stm32g0)
mbed_set_linker_script(mbed-stm32g041x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
target_link_libraries(mbed-stm32g041x8 INTERFACE mbed-stm32g0)

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_ARM/startup_stm32g041xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_ARM/startup_stm32g041xx.S
View File

12
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_ARM/stm32g070xx.sct → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_ARM/stm32g041x8.sct
View File

@ -25,13 +25,13 @@
#define MBED_APP_SIZE MBED_ROM_SIZE
#endif
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#if defined(MBED_BOOT_STACK_SIZE)
#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
#else
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
#endif
#endif
/* Round up VECTORS_SIZE to 8 bytes */

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_GCC_ARM/startup_stm32g041xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_GCC_ARM/startup_stm32g041xx.S
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_GCC_ARM/stm32g041xx.ld → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_GCC_ARM/stm32g041x8.ld
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_IAR/startup_stm32g041xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_IAR/startup_stm32g041xx.S
View File

4
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/TOOLCHAIN_IAR/stm32g030xx.icf → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/TOOLCHAIN_IAR/stm32g041x8.icf
View File

@ -18,7 +18,7 @@
/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
define symbol VECTORS = 45; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
define symbol HEAP_SIZE = 0x1000;
/* Common - Do not change */
@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) {
}
if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
/* This value is normally defined by the tools
/* This value is normally defined by the tools
to 0x1000 for bare metal and 0x400 for RTOS */
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
}

6
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/cmsis_nvic.h → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041x8/cmsis_nvic.h
View File

@ -22,7 +22,7 @@
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x20000
#define MBED_ROM_SIZE 0x10000 // 64 KB
#endif
#if !defined(MBED_RAM_START)
@ -30,10 +30,10 @@
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x9000
#define MBED_RAM_SIZE 0x2000 // 8 KB
#endif
#define NVIC_NUM_VECTORS 46
#define NVIC_NUM_VECTORS 48
#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
#endif

41
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/cmsis_nvic.h
View File

@ -1,41 +0,0 @@
/* mbed Microcontroller Library
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016-2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x8000000
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x10000
// 0x10000 STM32G041Y8Yx STM32G041K8Ux STM32G041C8Ux STM32G041C8Tx STM32G041K8Tx STM32G041G8Ux STM32G041F8Px
// 0x8000 STM32G041G6Ux STM32G041K6Tx STM32G041C6Tx STM32G041J6Mx STM32G041K6Ux STM32G041C6Ux STM32G041F6Px
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x2000
#endif
#define NVIC_NUM_VECTORS 48
#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
#endif

22
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/CMakeLists.txt → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/CMakeLists.txt
View File

@ -3,24 +3,24 @@
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g070xx.S)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g070xx.ld)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g070xb.ld)
elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g070xx.S)
set(LINKER_FILE TOOLCHAIN_ARM/stm32g070xx.sct)
set(LINKER_FILE TOOLCHAIN_ARM/stm32g070xb.sct)
endif()
add_library(mbed-stm32g070xx INTERFACE)
add_library(mbed-stm32g070xb INTERFACE)
target_sources(mbed-stm32g070xx
INTERFACE
${STARTUP_FILE}
)
target_include_directories(mbed-stm32g070xx
target_include_directories(mbed-stm32g070xb
INTERFACE
.
)
mbed_set_linker_script(mbed-stm32g070xx ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
target_sources(mbed-stm32g070xb
INTERFACE
${STARTUP_FILE}
)
target_link_libraries(mbed-stm32g070xx INTERFACE mbed-stm32g0)
mbed_set_linker_script(mbed-stm32g070xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
target_link_libraries(mbed-stm32g070xb INTERFACE mbed-stm32g0)

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_ARM/startup_stm32g070xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_ARM/startup_stm32g070xx.S
View File

12
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/TOOLCHAIN_ARM/stm32g041xx.sct → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_ARM/stm32g070xb.sct
View File

@ -25,13 +25,13 @@
#define MBED_APP_SIZE MBED_ROM_SIZE
#endif
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#if defined(MBED_BOOT_STACK_SIZE)
#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
#else
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
#endif
#endif
/* Round up VECTORS_SIZE to 8 bytes */

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_GCC_ARM/startup_stm32g070xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_GCC_ARM/startup_stm32g070xx.S
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_GCC_ARM/stm32g070xx.ld → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_GCC_ARM/stm32g070xb.ld
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_IAR/startup_stm32g070xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_IAR/startup_stm32g070xx.S
View File

2
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_IAR/stm32g081xx.icf → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/TOOLCHAIN_IAR/stm32g070xb.icf
View File

@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) {
}
if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
/* This value is normally defined by the tools
/* This value is normally defined by the tools
to 0x1000 for bare metal and 0x400 for RTOS */
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
}

8
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/cmsis_nvic.h → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xB/cmsis_nvic.h
View File

@ -22,9 +22,7 @@
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x10000
// 0x10000 STM32G030K8Tx STM32G030C8Tx
// 0x8000 STM32G030F6Px STM32G030K6Tx STM32G030C6Tx STM32G030J6Mx
#define MBED_ROM_SIZE 0x20000 // 128 KB
#endif
#if !defined(MBED_RAM_START)
@ -32,10 +30,10 @@
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x2000
#define MBED_RAM_SIZE 0x9000 // 36 KB
#endif
#define NVIC_NUM_VECTORS 45
#define NVIC_NUM_VECTORS 48
#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
#endif

23
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/CMakeLists.txt → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/CMakeLists.txt
View File

@ -5,24 +5,25 @@ add_subdirectory(TARGET_NUCLEO_G071RB EXCLUDE_FROM_ALL)
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g071xx.S)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g071xx.ld)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g071xb.ld)
elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g071xx.S)
set(LINKER_FILE TOOLCHAIN_ARM/stm32g071xx.sct)
set(LINKER_FILE TOOLCHAIN_ARM/stm32g071xb.sct)
endif()
add_library(mbed-stm32g071xx INTERFACE)
add_library(mbed-stm32g071xb INTERFACE)
target_sources(mbed-stm32g071xx
INTERFACE
${STARTUP_FILE}
)
target_include_directories(mbed-stm32g071xx
target_include_directories(mbed-stm32g071xb
INTERFACE
.
)
mbed_set_linker_script(mbed-stm32g071xx ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
target_sources(mbed-stm32g071xb
INTERFACE
${STARTUP_FILE}
system_clock.c
)
target_link_libraries(mbed-stm32g071xx INTERFACE mbed-stm32g0)
mbed_set_linker_script(mbed-stm32g071xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
target_link_libraries(mbed-stm32g071xb INTERFACE mbed-stm32g0)

3
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/CMakeLists.txt → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TARGET_NUCLEO_G071RB/CMakeLists.txt
View File

@ -6,7 +6,6 @@ add_library(mbed-nucleo-g071rb INTERFACE)
target_sources(mbed-nucleo-g071rb
INTERFACE
PeripheralPins.c
system_clock.c
)
target_include_directories(mbed-nucleo-g071rb
@ -14,4 +13,4 @@ target_include_directories(mbed-nucleo-g071rb
.
)
target_link_libraries(mbed-nucleo-g071rb INTERFACE mbed-stm32g071xx)
target_link_libraries(mbed-nucleo-g071rb INTERFACE mbed-stm32g071xb)

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/PeripheralPins.c → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TARGET_NUCLEO_G071RB/PeripheralPins.c
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/PinNames.h → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TARGET_NUCLEO_G071RB/PinNames.h
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_ARM/startup_stm32g071xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_ARM/startup_stm32g071xx.S
View File

57
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_ARM/stm32g071xb.sct Normal file
View File

@ -0,0 +1,57 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; Scatter-Loading Description File
;
; SPDX-License-Identifier: BSD-3-Clause
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2016-2020 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
#include "../cmsis_nvic.h"
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#if defined(MBED_BOOT_STACK_SIZE)
#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
#else
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
#endif
#endif
/* Round up VECTORS_SIZE to 8 bytes */
#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
}
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
}
}

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_GCC_ARM/startup_stm32g071xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_GCC_ARM/startup_stm32g071xx.S
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_GCC_ARM/stm32g071xx.ld → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_GCC_ARM/stm32g071xb.ld
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_IAR/startup_stm32g071xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_IAR/startup_stm32g071xx.S
View File

4
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G070xx/TOOLCHAIN_IAR/stm32g070xx.icf → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/TOOLCHAIN_IAR/stm32g071xb.icf
View File

@ -18,7 +18,7 @@
/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
define symbol VECTORS = 46; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
define symbol HEAP_SIZE = 0x2000;
/* Common - Do not change */
@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) {
}
if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
/* This value is normally defined by the tools
/* This value is normally defined by the tools
to 0x1000 for bare metal and 0x400 for RTOS */
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
}

39
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/cmsis_nvic.h Normal file
View File

@ -0,0 +1,39 @@
/* mbed Microcontroller Library
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016-2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x8000000
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x20000 // 128 KB
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x9000 // 36 KB
#endif
#define NVIC_NUM_VECTORS 48
#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
#endif

32
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xB/system_clock.c
View File

@ -2,7 +2,7 @@
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
*
* Copyright (c) 2019 STMicroelectronics.
* Copyright (c) 2019-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
@ -14,10 +14,10 @@
*/
/**
* This file configures the system clock as follows:
*-----------------------------------------------------------------
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
* This file configures the system clock depending on config from targets.json:
*-----------------------------------------------------------------------------
* System clock source | 1- USE_PLL_HSE_EXTC (external clock)
* | 2- USE_PLL_HSE_XTAL (external xtal)
* | 3- USE_PLL_HSI (internal 16 MHz)
*-----------------------------------------------------------------
* SYSCLK(MHz) | 64
@ -30,13 +30,8 @@
#include "stm32g0xx.h"
#include "mbed_error.h"
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
This value must be a multiple of 0x100. */
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
// clock source is selected with CLOCK_SOURCE in json config
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN)
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
#define USE_PLL_HSI 0x2 // Use HSI internal clock
@ -52,12 +47,13 @@ uint8_t SetSysClock_PLL_HSI(void);
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c)
* and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c)
* @param None
* @retval None
*/
void SetSysClock(void)
MBED_WEAK void SetSysClock(void)
{
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
/* 1- Try to start with HSE and external clock */
@ -80,17 +76,13 @@ void SetSysClock(void)
}
}
}
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
}
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

57
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_ARM/stm32g071xx.sct
View File

@ -1,57 +0,0 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; Scatter-Loading Description File
;
; SPDX-License-Identifier: BSD-3-Clause
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2016-2020 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
#include "../cmsis_nvic.h"
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#endif
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
#endif
/* Round up VECTORS_SIZE to 8 bytes */
#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
}
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
}
}

46
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h
View File

@ -1,46 +0,0 @@
/* mbed Microcontroller Library
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016-2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x8000000
#endif
#if !defined(MBED_ROM_SIZE)
#if defined (TARGET_NUCLEO_G071RB)
#define MBED_ROM_SIZE 0x20000
#else
// 0x10000 STM32G071C8Ux STM32G071K8TxN STM32G071R8Tx STM32G071K8Ux STM32G071G8UxN STM32G071C8Tx STM32G071K8Tx STM32G071K8UxN STM32G071G8Ux
// 0x8000 STM32G071K6Tx STM32G071G6Ux STM32G071C6Tx STM32G071K6Ux STM32G071R6Tx STM32G071C6Ux
// 0x20000 STM32G071GBUxN STM32G071CBUx STM32G071KBTx STM32G071KBUxN STM32G071RBTx STM32G071EBYx STM32G071GBUx STM32G071CBTx STM32G071KBUx STM32G071RBIx STM32G071KBTxN
#error "MBED_ROM_SIZE not defined"
#endif
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x9000
#endif
#define NVIC_NUM_VECTORS 48
#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
#endif

22
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/CMakeLists.txt → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/CMakeLists.txt
View File

@ -3,24 +3,24 @@
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32g081xx.S)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g081xx.ld)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32g081xb.ld)
elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32g081xx.S)
set(LINKER_FILE TOOLCHAIN_ARM/stm32g081xx.sct)
set(LINKER_FILE TOOLCHAIN_ARM/stm32g081xb.sct)
endif()
add_library(mbed-stm32g081xx INTERFACE)
add_library(mbed-stm32g081xb INTERFACE)
target_sources(mbed-stm32g081xx
INTERFACE
${STARTUP_FILE}
)
target_include_directories(mbed-stm32g081xx
target_include_directories(mbed-stm32g081xb
INTERFACE
.
)
mbed_set_linker_script(mbed-stm32g081xx ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
target_sources(mbed-stm32g081xb
INTERFACE
${STARTUP_FILE}
)
target_link_libraries(mbed-stm32g081xx INTERFACE mbed-stm32g0)
mbed_set_linker_script(mbed-stm32g081xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
target_link_libraries(mbed-stm32g081xb INTERFACE mbed-stm32g0)

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_ARM/startup_stm32g081xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_ARM/startup_stm32g081xx.S
View File

57
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_ARM/stm32g081xb.sct Normal file
View File

@ -0,0 +1,57 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; Scatter-Loading Description File
;
; SPDX-License-Identifier: BSD-3-Clause
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2016-2020 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
#include "../cmsis_nvic.h"
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#if defined(MBED_BOOT_STACK_SIZE)
#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
#else
#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
#endif
#endif
/* Round up VECTORS_SIZE to 8 bytes */
#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
}
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
}
}

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_GCC_ARM/startup_stm32g081xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_GCC_ARM/startup_stm32g081xx.S
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_GCC_ARM/stm32g081xx.ld → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_GCC_ARM/stm32g081xb.ld
View File

0
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_IAR/startup_stm32g081xx.S → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_IAR/startup_stm32g081xx.S
View File

4
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TOOLCHAIN_IAR/stm32g071xx.icf → targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/TOOLCHAIN_IAR/stm32g081xb.icf
View File

@ -18,7 +18,7 @@
/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
define symbol VECTORS = 47; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
define symbol HEAP_SIZE = 0x2000;
/* Common - Do not change */
@ -32,7 +32,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) {
}
if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
/* This value is normally defined by the tools
/* This value is normally defined by the tools
to 0x1000 for bare metal and 0x400 for RTOS */
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
}

39
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xB/cmsis_nvic.h Normal file
View File

@ -0,0 +1,39 @@
/* mbed Microcontroller Library
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016-2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x8000000
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x20000 // 128 KB
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x9000 // 36 KB
#endif
#define NVIC_NUM_VECTORS 48
#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START
#endif

57
targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G081xx/TOOLCHAIN_ARM/stm32g081xx.sct
View File

@ -1,57 +0,0 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
; Scatter-Loading Description File
;
; SPDX-License-Identifier: BSD-3-Clause
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2016-2020 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
#include "../cmsis_nvic.h"
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#endif
/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
# if defined(MBED_BOOT_STACK_SIZE)
# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
# else
# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
# endif
#endif
/* Round up VECTORS_SIZE to 8 bytes */
#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE {
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
}
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
}
}

16
targets/targets.json
View File

@ -2632,7 +2632,7 @@
"MPU"
]
},
"MCU_STM32G031xx": {
"MCU_STM32G031x8": {
"inherits": [
"MCU_STM32G0"
],
@ -2644,7 +2644,7 @@
"bare-metal"
],
"extra_labels_add": [
"STM32G031xx"
"STM32G031x8"
],
"macros_add": [
"STM32G031xx"
@ -2652,20 +2652,20 @@
},
"NUCLEO_G031K8": {
"inherits": [
"MCU_STM32G031xx"
"MCU_STM32G031x8"
],
"detect_code": [
"0852"
],
"device_name": "STM32G031K8Tx"
},
"MCU_STM32G070xx": {
"MCU_STM32G070xB": {
"inherits": [
"MCU_STM32G0"
],
"public": false,
"extra_labels_add": [
"STM32G070xx"
"STM32G070xB"
],
"macros_add": [
"STM32G070xx"
@ -2679,13 +2679,13 @@
"lpticker_lptim": "0"
}
},
"MCU_STM32G071xx": {
"MCU_STM32G071xB": {
"inherits": [
"MCU_STM32G0"
],
"public": false,
"extra_labels_add": [
"STM32G071xx"
"STM32G071xB"
],
"macros_add": [
"STM32G071xx"
@ -2696,7 +2696,7 @@
},
"NUCLEO_G071RB": {
"inherits": [
"MCU_STM32G071xx"
"MCU_STM32G071xB"
],
"supported_form_factors": [
"ARDUINO_UNO"