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[LPC1549] initial commit

pull/182/head
ytsuboi 2014-02-11 15:54:38 +09:00
parent 281fcc76b6
commit e06e842221
19 changed files with 3277 additions and 1 deletions
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1715
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/LPC15xx.h Normal file
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libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/LPC15xx.sct Normal file
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LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100
; 36kB(0x9000) - 0x100 = 0x8F00
RW_IRAM1 (0x02000000+0x100) (0x9000-0x100) {
.ANY (+RW +ZI)
}

316
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/startup_LPC15xx.s Normal file
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;/**************************************************************************//**
; * @file startup_LPC15xx.s
; * @brief CMSIS Cortex-M3 Core Device Startup File for
; * NXP LPC15xx Device Series
; * @version V1.00
; * @date 17. July 2013
; *
; * @note
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WDT_IRQHandler ; 16+ 0 Windowed watchdog timer interrupt
DCD BOD_IRQHandler ; 16+ 1 BOD interrupt
DCD FLASH_IRQHandler ; 16+ 2 Flash controller interrupt
DCD EE_IRQHandler ; 16+ 3 EEPROM controller interrupt
DCD DMA_IRQHandler ; 16+ 4 DMA interrupt
DCD GINT0_IRQHandler ; 16+ 5 GPIO group0 interrupt
DCD GINT1_IRQHandler ; 16+ 6 GPIO group1 interrupt
DCD PIN_INT0_IRQHandler ; 16+ 7 Pin interrupt 0 or pattern match engine slice 0 interrupt
DCD PIN_INT1_IRQHandler ; 16+ 8 Pin interrupt 1 or pattern match engine slice 1 interrupt
DCD PIN_INT2_IRQHandler ; 16+ 9 Pin interrupt 2 or pattern match engine slice 2 interrupt
DCD PIN_INT3_IRQHandler ; 16+10 Pin interrupt 3 or pattern match engine slice 3 interrupt
DCD PIN_INT4_IRQHandler ; 16+11 Pin interrupt 4 or pattern match engine slice 4 interrupt
DCD PIN_INT5_IRQHandler ; 16+12 Pin interrupt 5 or pattern match engine slice 5 interrupt
DCD PIN_INT6_IRQHandler ; 16+13 Pin interrupt 6 or pattern match engine slice 6 interrupt
DCD PIN_INT7_IRQHandler ; 16+14 Pin interrupt 7 or pattern match engine slice 7 interrupt
DCD RIT_IRQHandler ; 16+15 RIT interrupt
DCD SCT0_IRQHandler ; 16+16 State configurable timer interrupt
DCD SCT1_IRQHandler ; 16+17 State configurable timer interrupt
DCD SCT2_IRQHandler ; 16+18 State configurable timer interrupt
DCD SCT3_IRQHandler ; 16+19 State configurable timer interrupt
DCD MRT_IRQHandler ; 16+20 Multi-rate timer interrupt
DCD UART0_IRQHandler ; 16+21 USART0 interrupt
DCD UART1_IRQHandler ; 16+22 USART1 interrupt
DCD UART2_IRQHandler ; 16+23 USART2 interrupt
DCD I2C0_IRQHandler ; 16+24 I2C0 interrupt
DCD SPI0_IRQHandler ; 16+25 SPI0 interrupt
DCD SPI1_IRQHandler ; 16+26 SPI1 interrupt
DCD C_CAN0_IRQHandler ; 16+27 C_CAN0 interrupt
DCD USB_IRQ_IRQHandler ; 16+28 USB interrupt
DCD USB_FIQ_IRQHandler ; 16+29 USB interrupt
DCD USBWAKEUP_IRQHandler ; 16+30 USB wake-up interrupt
DCD ADC0_SEQA_IRQHandler ; 16+31 ADC0 sequence A completion.
DCD ADC0_SEQB_IRQHandler ; 16+32 ADC0 sequence B completion.
DCD ADC0_THCMP_IRQHandler ; 16+33 ADC0 threshold compare
DCD ADC0_OVR_IRQHandler ; 16+34 ADC0 overrun
DCD ADC1_SEQA_IRQHandler ; 16+35 ADC1 sequence A completion.
DCD ADC1_SEQB_IRQHandler ; 16+36 ADC1 sequence B completion.
DCD ADC1_THCMP_IRQHandler ; 16+37 ADC1 threshold compare
DCD ADC1_OVR_IRQHandler ; 16+38 ADC1 overrun
DCD DAC_IRQHandler ; 16+39 DAC interrupt
DCD CMP0_IRQHandler ; 16+40 Analog comparator 0 interrupt (ACMP0)
DCD CMP1_IRQHandler ; 16+41 Analog comparator 1 interrupt (ACMP1)
DCD CMP2_IRQHandler ; 16+42 Analog comparator 2 interrupt (ACMP2)
DCD CMP3_IRQHandler ; 16+43 Analog comparator 3 interrupt (ACMP3)
DCD QEI_IRQHandler ; 16+44 QEI interrupt
DCD RTC_ALARM_IRQHandler ; 16+45 RTC alarm interrupt
DCD RTC_WAKE_IRQHandler ; 16+46 RTC wake-up interrut
; <h> Code Read Protection
; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
; <0x12345678=>CRP Level 1
; <0x87654321=>CRP Level 2
; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
; <0x4E697370=>NO ISP (ARE YOU SURE?)
; </h>
IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
DCD 0xFFFFFFFF
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
;--- enable SRAM1 and SRAM2 memory
LDR R0, =0x400740C4 ; SYSAHBCLKCTRL0 register addr
LDR R2, [R0] ; read SYSAHBCLKCTRL0
ORR R2, R2, #0x18 ; enable SRAM1, SRAM2
STR R2, [R0] ; store SYSAHBCLKCTRL0
;---
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WDT_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT EE_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT RIT_IRQHandler [WEAK]
EXPORT SCT0_IRQHandler [WEAK]
EXPORT SCT1_IRQHandler [WEAK]
EXPORT SCT2_IRQHandler [WEAK]
EXPORT SCT3_IRQHandler [WEAK]
EXPORT MRT_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT C_CAN0_IRQHandler [WEAK]
EXPORT USB_IRQ_IRQHandler [WEAK]
EXPORT USB_FIQ_IRQHandler [WEAK]
EXPORT USBWAKEUP_IRQHandler [WEAK]
EXPORT ADC0_SEQA_IRQHandler [WEAK]
EXPORT ADC0_SEQB_IRQHandler [WEAK]
EXPORT ADC0_THCMP_IRQHandler [WEAK]
EXPORT ADC0_OVR_IRQHandler [WEAK]
EXPORT ADC1_SEQA_IRQHandler [WEAK]
EXPORT ADC1_SEQB_IRQHandler [WEAK]
EXPORT ADC1_THCMP_IRQHandler [WEAK]
EXPORT ADC1_OVR_IRQHandler [WEAK]
EXPORT DAC_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT CMP1_IRQHandler [WEAK]
EXPORT CMP2_IRQHandler [WEAK]
EXPORT CMP3_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
EXPORT RTC_ALARM_IRQHandler [WEAK]
EXPORT RTC_WAKE_IRQHandler [WEAK]
WDT_IRQHandler
BOD_IRQHandler
FLASH_IRQHandler
EE_IRQHandler
DMA_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
RIT_IRQHandler
SCT0_IRQHandler
SCT1_IRQHandler
SCT2_IRQHandler
SCT3_IRQHandler
MRT_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
I2C0_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
C_CAN0_IRQHandler
USB_IRQ_IRQHandler
USB_FIQ_IRQHandler
USBWAKEUP_IRQHandler
ADC0_SEQA_IRQHandler
ADC0_SEQB_IRQHandler
ADC0_THCMP_IRQHandler
ADC0_OVR_IRQHandler
ADC1_SEQA_IRQHandler
ADC1_SEQB_IRQHandler
ADC1_THCMP_IRQHandler
ADC1_OVR_IRQHandler
DAC_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
CMP2_IRQHandler
CMP3_IRQHandler
QEI_IRQHandler
RTC_ALARM_IRQHandler
RTC_WAKE_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
END

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libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/sys.cpp Normal file
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/* mbed Microcontroller Library - stackheap
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

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libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis.h Normal file
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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC8xx specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "LPC15xx.h"
#include "cmsis_nvic.h"
#endif

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libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.c Normal file
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/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
* Copyright (c) 2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x02000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}

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libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/cmsis_nvic.h Normal file
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/* mbed Microcontroller Library - cmsis_nvic
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 47) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c Normal file
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/**************************************************************************//**
* @file system_LPC15xx.c
* @brief CMSIS Cortex-M3 Device System Source File for
* NXP LPC15xx Device Series
* @version V1.00
* @date 19. July 2013
*
* @note
* Copyright (C) 2013 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include "LPC15xx.h"
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*- SystemCoreClock Configuration -------------------------------------------*/
// <e0> SystemCoreClock Configuration
#define CLOCK_SETUP 1
//
// <h> System Oscillator Control (SYSOSCCTRL)
// <o.0> BYPASS: System Oscillator Bypass Enable
// <i> If enabled then PLL input (sys_osc_clk) is fed
// <i> directly from XTALIN and XTALOUT pins.
// <o.1> FREQRANGE: System Oscillator Frequency Range
// <i> Determines frequency range for Low-power oscillator.
// <0=> 1 - 20 MHz
// <1=> 15 - 25 MHz
// </h>
#define SYSOSCCTRL_Val 0x00000000 // Reset value: 0x000
//
// <o.0..1> System PLL Clock Source Select (SYSPLLCLKSEL)
// <0=> IRC Oscillator
// <1=> Crystal Oscillator (SYSOSC)
#define SYSPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
//
// <e> Clock Configuration (Manual)
#define CLOCK_SETUP_REG 1
//
// <o.0..1> Main Clock Source Select A (MAINCLKSELA)
// <0=> IRC Oscillator
// <1=> System Oscillator
// <2=> WD Oscillator
#define MAINCLKSELA_Val 0x00000001 // Reset value: 0x000
//
// <o.0..1> Main Clock Source Select B (MAINCLKSELB)
// <0=> MAINCLKSELA
// <1=> System PLL Input
// <2=> System PLL Output
// <3=> RTC Oscillator
#define MAINCLKSELB_Val 0x00000002 // Reset value: 0x000
//
// <h> System PLL Setting (SYSPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o.0..5> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o.5..7> PSEL: Post Divider Selection
// <i> Post divider ratio P. Division ratio is 2 * P
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
#define SYSPLLCTRL_Val 0x00000005 // Reset value: 0x000
//
// <o.0..7> System AHB Clock Divider (SYSAHBCLKDIV.DIV)
// <i> Divides main clock to provide system clock to core, memories, and peripherals.
// <i> 0 = is disabled
// <0-255>
#define SYSAHBCLKDIV_Val 0x00000001 // Reset value: 0x001
// </e>
//
// <e> Clock Configuration (via ROM PLL API)
#define CLOCK_SETUP_API 0
//
// <o> PLL API Mode Select
// <0=> Exact
// <1=> Less than or equal
// <2=> Greater than or equal
// <3=> As close as possible
#define PLL_API_MODE_Val 0
//
// <o> CPU Frequency [Hz] <1000000-72000000:1000>
#define PLL_API_FREQ_Val 72000000
// </e>
//
// <e> USB Clock Configuration
#define USB_CLOCK_SETUP 0
// <h> USB PLL Control (USBPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o.0..5> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o.7..6> PSEL: Post Divider Selection
// <i> Post divider ratio P. Division ratio is 2 * P
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
#define USBPLLCTRL_Val 0x00000023 // Reset value: 0x000
//
// <o.0..1> USB PLL Clock Source Select (USBPLLCLKSEL.SEL)
// <0=> IRC Oscillator
// <1=> System Oscillator
#define USBPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
//
// <o.0..1> USB Clock Source Select (USBCLKSEL.SEL)
// <0=> IRC Oscillator
// <1=> System Oscillator
// <2=> USB PLL out
// <3=> Main clock
#define USBCLKSEL_Val 0x00000002 // Reset value: 0x000
//
// <o.0..7> USB Clock Divider (USBCLKDIV.DIV)
// <i> Divides USB clock to 48 MHz.
// <i> 0 = is disabled
// <0-255>
#define USBCLKDIV_Val 0x00000001 // Reset Value: 0x001
// </e>
//
// <e> SCT Clock Configuration
#define SCT_CLOCK_SETUP 0
// <h> SCT PLL Control (SCTPLLCTRL)
// <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
// <i> F_clkin must be in the range of 10 MHz to 25 MHz
// <i> F_CCO must be in the range of 156 MHz to 320 MHz
// <o.0..5> MSEL: Feedback Divider Selection
// <i> M = MSEL + 1
// <0-31>
// <o.7..6> PSEL: Post Divider Selection
// <i> Post divider ratio P. Division ratio is 2 * P
// <0=> P = 1
// <1=> P = 2
// <2=> P = 4
// <3=> P = 8
// </h>
#define SCTPLLCTRL_Val 0x00000023 // Reset value: 0x000
//
// <o.0..1> SCT PLL Clock Source Select (SCTPLLCLKSEL.SEL)
// <0=> IRC Oscillator
// <1=> System Oscillator
#define SCTPLLCLKSEL_Val 0x00000001 // Reset value: 0x000
// </e>
//
// </e>
//
// <o0>System Oscillator (XTAL) Frequency [Hz] <1000000-25000000>
// <i> XTAL frequency must be in the range of 1 MHz to 25 MHz
//
#define XTAL_CLK_Val 12000000
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL_CLK ( XTAL_CLK_Val) /* Oscillator freq */
#define __SYS_OSC_CLK ( __XTAL_CLK) /* System oscillator freq */
#define __IRC_OSC_CLK ( 12000000UL) /* Internal RC oscillator freq */
#define __RTC_OSC_CLK ( 32768UL) /* RTC oscillator freq */
#define __WDT_OSC_CLK ( 503000UL) /* WDT oscillator freq */
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
#if (CHECK_RANGE((SYSOSCCTRL_Val), 0, 1))
#error "SYSOSCCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
#error "SYSPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000000FF))
#error "SYSPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((MAINCLKSELA_Val), 0, 2))
#error "MAINCLKSELA: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((MAINCLKSELB_Val), ~0x00000003))
#error "MAINCLKSELB: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
#error "SYSAHBCLKDIV: Value out of range!"
#endif
#if ( CLOCK_SETUP_REG == CLOCK_SETUP_API )
#error "You must select either manual or API based Clock Configuration!"
#endif
#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
#error "USBPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x00000FF))
#error "USBPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((USBCLKSEL_Val), 0, 3))
#error "USBCLKSEL: Value out of range!"
#endif
#if (CHECK_RANGE((USBCLKDIV_Val), 0, 255))
#error "USBCLKDIV: Value out of range!"
#endif
#if (CHECK_RANGE((SCTPLLCLKSEL_Val), 0, 1))
#error "SCTPLLCLKSEL: Value out of range!"
#endif
#if (CHECK_RSVD((SCTPLLCTRL_Val), ~0x00000FF))
#error "SCTPLLCTRL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE(XTAL_CLK_Val, 1000000, 25000000))
#error "XTAL frequency is out of bounds"
#endif
#if (CHECK_RANGE(PLL_API_MODE_Val, 0, 3))
#error "PLL API Mode Select not valid"
#endif
#if (CHECK_RANGE(PLL_API_FREQ_Val, 1000000, 72000000))
#error "CPU Frequency (API mode) not valid"
#endif
/*----------------------------------------------------------------------------
Calculate system core clock
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP) /* Clock Setup */
/* sys_pllclkin calculation */
#if ((SYSPLLCLKSEL_Val & 0x03) == 0)
#define __SYS_PLLCLKIN (__IRC_OSC_CLK)
#elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
#define __SYS_PLLCLKIN (__SYS_OSC_CLK)
#else
#error "Oops"
#endif
#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
#if ((MAINCLKSELA_Val & 0x03) == 0)
#define __MAINA_CLOCK (__IRC_OSC_CLK)
#elif ((MAINCLKSELA_Val & 0x03) == 1)
#define __MAINA_CLOCK (__SYS_OSC_CLK)
#elif ((MAINCLKSELA_Val & 0x03) == 2)
#define __MAINA_CLOCK (__WDT_OSC_CLK)
#else
#error "Oops"
#endif
#define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
/* main clock calculation */
#if ((MAINCLKSELB_Val & 0x03) == 0)
#define __MAINB_CLOCK (__MAINA_CLOCK)
#elif ((MAINCLKSELB_Val & 0x03) == 1)
#define __MAINB_CLOCK (__SYS_PLLCLKIN)
#elif ((MAINCLKSELB_Val & 0x03) == 2)
#define __MAINB_CLOCK (__SYS_PLLCLKOUT)
#elif ((MAINCLKSELB_Val & 0x03) == 3)
#define __MAINB_CLOCK (__RTC_OSC_CLK)
#else
#error "Oops"
#endif
#define __SYSTEM_CLOCK (__MAINB_CLOCK / SYSAHBCLKDIV_Val)
#endif /* Clock Setup via Register */
#if (CLOCK_SETUP_API == 1) /* Clock Setup via ROM API */
#define __SYSTEM_CLOCK (PLL_API_FREQ_Val)
#endif /* Clock Setup via PLL API */
#else
#define __SYSTEM_CLOCK (__IRC_OSC_CLK)
#endif /* CLOCK_SETUP */
#if ((CLOCK_SETUP == 1) && (CLOCK_SETUP_API == 1)) /* PLL Setup via PLL API */
#include "power_api.h"
typedef struct _ROM {
const unsigned p_dev0;
const unsigned p_dev1;
const unsigned p_dev2;
const PWRD * pPWRD; /* ROM Power Management API */
const unsigned p_dev4;
const unsigned p_dev5;
const unsigned p_dev6;
const unsigned p_dev7;
} ROM;
/*----------------------------------------------------------------------------
PLL API Function
*----------------------------------------------------------------------------*/
static void setPLL(const uint32_t pllMode, const uint32_t pllInFreq, const uint32_t reqCpuFreq)
{
uint32_t cmd[5], res[5];
ROM ** rom = (ROM **) 0x03000200; /* pointer to power API calls */
cmd[0] = pllInFreq; /* PLL's input freq in KHz */
cmd[1] = reqCpuFreq; /* requested CPU freq in KHz */
cmd[2] = pllMode;
cmd[3] = 0; /* no timeout for PLL to lock */
/* Execute API call */
(*rom)->pPWRD->set_pll(cmd, res); /* call API function */
if ((res[0] != PLL_CMD_SUCCESS)){ /* in case of an error ... */
while(1); /* ... stay here */
}
}
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /* System Clock Frequency */
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* Determine clock frequency according to clock register values */
switch (LPC_SYSCON->MAINCLKSELB & 0x03) {
case 0: /* MAINCLKSELA clock sel */
switch (LPC_SYSCON->MAINCLKSELA & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK;
break;
case 2: /* Watchdog oscillator */
SystemCoreClock = __WDT_OSC_CLK;
break;
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
case 1: /* Input Clock to System PLL */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK;
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK;
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
case 2: /* System PLL Clock Out */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
case 1: /* System oscillator */
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
case 2: /* Reserved */
case 3: /* Reserved */
SystemCoreClock = 0;
break;
}
break;
case 3: /* WDT Oscillator */
SystemCoreClock = __WDT_OSC_CLK;
break;
}
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
*/
void SystemInit (void) {
#if (CLOCK_SETUP)
volatile uint32_t i;
#endif
#if (CLOCK_SETUP) /* Clock Setup */
#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
#endif
LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
#if (CLOCK_SETUP_REG == 1) /* Clock Setup via Register */
#if (((MAINCLKSELA_Val & 0x03) == 1) )
LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 21); /* Power-up sysosc */
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
#endif
#if (((MAINCLKSELA_Val & 0x03) == 2) )
LPC_SYSCON->PDRUNCFG &= ~(1 << 20); /* Power-up WDT Clock */
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
#endif
#if ((MAINCLKSELB_Val & 0x03) == 3)
LPC_SYSCON->RTCOSCCTRL = (1 << 0); /* Enable 32 kHz output */
for (i = 0; i < 200; i++) __NOP(); /* Wait for osc to stabilize */
#endif
LPC_SYSCON->MAINCLKSELA = MAINCLKSELA_Val; /* select MAINCLKA clock */
#if ((MAINCLKSELB_Val & 0x03) == 2) /* Main Clock is PLL Out */
LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
LPC_SYSCON->PDRUNCFG &= ~(1 << 22); /* Power-up SYSPLL */
while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
#endif
LPC_SYSCON->MAINCLKSELB = MAINCLKSELB_Val; /* select Main clock */
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
#endif /* Clock Setup via Register */
#if (CLOCK_SETUP_API == 1) /* Clock Setup via PLL API */
// LPC_SYSCON->SYSPLLCLKSEL = 0x00; /* Use IRC */
LPC_SYSCON->MAINCLKSELB = (1 << 2); /* Select System PLL output */
LPC_SYSCON->SYSAHBCLKDIV = 1;
setPLL(PLL_API_MODE_Val, __SYS_PLLCLKIN / 1000, PLL_API_FREQ_Val / 1000);
#endif /* Clock Setup via PLL API */
#if (USB_CLOCK_SETUP == 1) /* USB clock is used */
LPC_SYSCON->PDRUNCFG &= ~(1 << 9); /* Power-up USB PHY */
#if ((USBCLKSEL_Val & 0x003) == 2) /* USB clock is USB PLL out */
LPC_SYSCON->PDRUNCFG &= ~(1 << 23); /* Power-up USB PLL */
LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
LPC_SYSCON->USBCLKSEL = 0x02; /* Select USB PLL */
#endif
LPC_SYSCON->USBCLKSEL = USBCLKSEL_Val; /* Select USB Clock */
LPC_SYSCON->USBCLKDIV = USBCLKDIV_Val; /* Set USB clock divider */
#else /* USB clock is not used */
LPC_SYSCON->PDRUNCFG |= (1 << 9); /* Power-down USB PHY */
LPC_SYSCON->PDRUNCFG |= (1 << 23); /* Power-down USB PLL */
#endif
#if (SCT_CLOCK_SETUP == 1) /* SCT clock is used */
LPC_SYSCON->PDRUNCFG &= ~(1 << 24); /* Power-up SCT PLL */
LPC_SYSCON->SCTPLLCLKSEL = SCTPLLCLKSEL_Val; /* Select PLL Input */
LPC_SYSCON->USBPLLCTRL = SCTPLLCTRL_Val;
while (!(LPC_SYSCON->SCTPLLSTAT & 0x01)); /* Wait Until PLL Locked */
#else /* SCT clock is not used */
LPC_SYSCON->PDRUNCFG |= (1 << 24); /* Power-down SCT PLL */
#endif
#endif /* Clock Setup */
}

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/**************************************************************************//**
* @file system_LPC15xx.h
* @brief CMSIS Cortex-M3 Device System Header File for
* NXP LPC15xx Device Series
* @version V1.00
* @date 19. July 2013
*
* @note
* Copyright (C) 2013 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_LPC15xx_H
#define __SYSTEM_LPC15xx_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/** @addtogroup LPC15xx_System
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /* __SYSTEM_LPC15xx_H */

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/PeripheralNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/PinNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC Pin Names
P0_0 = 0,
P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12,
// mbed original LED naming
LED1 = P0_1,
LED2 = P0_3,
LED3 = P0_25,
LED4 = P0_25,
LED_RED = P0_2,
// Serial to USB pins
USBTX = P0_4,
USBRX = P0_0,
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4
} PinMode;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
typedef struct {
unsigned char n;
unsigned char offset;
} SWM_Map;
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/PortNames.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0,
Port1 = 1,
Port2 = 2
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/device.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_PORTIN 0
#define DEVICE_PORTOUT 0
#define DEVICE_PORTINOUT 0
#define DEVICE_INTERRUPTIN 0
#define DEVICE_ANALOGIN 0
#define DEVICE_ANALOGOUT 0
#define DEVICE_SERIAL 0
#define DEVICE_SERIAL_FC 0
#define DEVICE_I2C 0
#define DEVICE_I2CSLAVE 0
#define DEVICE_SPI 0
#define DEVICE_SPISLAVE 0
#define DEVICE_CAN 0
#define DEVICE_RTC 0
#define DEVICE_ETHERNET 0
#define DEVICE_PWMOUT 0
#define DEVICE_SEMIHOST 0
#define DEVICE_LOCALFILESYSTEM 0
#define DEVICE_SLEEP 0
#define DEVICE_DEBUG_AWARENESS 0
#define DEVICE_STDIO_MESSAGES 0
#define DEVICE_ERROR_RED 0
#include "objects.h"
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_api.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "pinmap.h"
static int gpio_enabled = 0;
static void gpio_enable(void) {
gpio_enabled = 1;
/* Enable AHB clock to the GPIO domain. */
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1<<14);
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1<<15);
LPC_SYSCON->SYSAHBCLKCTRL0 |= (1<<16);
/* Peripheral reset control to GPIO and GPIO INT, a "1" bring it out of reset. */
LPC_SYSCON->PRESETCTRL0 &= ~(0x1<<14);
LPC_SYSCON->PRESETCTRL0 |= (0x1<<14);
LPC_SYSCON->PRESETCTRL0 &= ~(0x1<<15);
LPC_SYSCON->PRESETCTRL0 |= (0x1<<15);
LPC_SYSCON->PRESETCTRL0 &= ~(0x1<<16);
LPC_SYSCON->PRESETCTRL0 |= (0x1<<16);
}
uint32_t gpio_set(PinName pin) {
int f = 0;
if (!gpio_enabled)
gpio_enable();
pin_function(pin, f);
return (1 << ((int)pin & 0x1F));
}
void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
if(pin == NC) return;
obj->pin = pin;
obj->mask = gpio_set(pin);
unsigned int port = (unsigned int)pin >> PORT_SHIFT;
obj->reg_set = &LPC_GPIO_PORT->SET[port];
obj->reg_clr = &LPC_GPIO_PORT->CLR[port];
obj->reg_in = &LPC_GPIO_PORT->PIN[port];
obj->reg_dir = &LPC_GPIO_PORT->DIR[port];
gpio_dir(obj, direction);
switch (direction) {
case PIN_OUTPUT: pin_mode(pin, PullNone); break;
case PIN_INPUT : pin_mode(pin, PullDown); break;
}
}
void gpio_mode(gpio_t *obj, PinMode mode) {
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction) {
switch (direction) {
case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
}
}

48
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/gpio_object.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
uint32_t mask;
__IO uint32_t *reg_dir;
__IO uint32_t *reg_set;
__IO uint32_t *reg_clr;
__I uint32_t *reg_in;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value) {
if (value)
*obj->reg_set = obj->mask;
else
*obj->reg_clr = obj->mask;
}
static inline int gpio_read(gpio_t *obj) {
return ((*obj->reg_in & obj->mask) ? 1 : 0);
}
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/objects.h Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
uint32_t ch;
};
struct serial_s {
LPC_USART0_Type *uart;
unsigned char index;
};
struct i2c_s {
LPC_I2C0_Type *i2c;
};
struct spi_s {
LPC_SPI0_Type *spi;
unsigned char spi_n;
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

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libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/pinmap.c Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "pinmap.h"
#include "error.h"
__IO uint32_t* IOCON_REGISTERS[76] = {
&LPC_IOCON->PIO0_0 , &LPC_IOCON->PIO0_1 , &LPC_IOCON->PIO0_2 ,
&LPC_IOCON->PIO0_3 , &LPC_IOCON->PIO0_4 , &LPC_IOCON->PIO0_5 ,
&LPC_IOCON->PIO0_6 , &LPC_IOCON->PIO0_7 , &LPC_IOCON->PIO0_8 ,
&LPC_IOCON->PIO0_9 , &LPC_IOCON->PIO0_10, &LPC_IOCON->PIO0_11,
&LPC_IOCON->PIO0_12, &LPC_IOCON->PIO0_13, &LPC_IOCON->PIO0_14,
&LPC_IOCON->PIO0_15, &LPC_IOCON->PIO0_16, &LPC_IOCON->PIO0_17,
&LPC_IOCON->PIO0_18, &LPC_IOCON->PIO0_19, &LPC_IOCON->PIO0_20,
&LPC_IOCON->PIO0_21, &LPC_IOCON->PIO0_22, &LPC_IOCON->PIO0_23,
&LPC_IOCON->PIO0_24, &LPC_IOCON->PIO0_25, &LPC_IOCON->PIO0_26,
&LPC_IOCON->PIO0_27, &LPC_IOCON->PIO0_28, &LPC_IOCON->PIO0_29,
&LPC_IOCON->PIO0_30, &LPC_IOCON->PIO0_31,
&LPC_IOCON->PIO1_0 , &LPC_IOCON->PIO1_1 , &LPC_IOCON->PIO1_2 ,
&LPC_IOCON->PIO1_3 , &LPC_IOCON->PIO1_4 , &LPC_IOCON->PIO1_5 ,
&LPC_IOCON->PIO1_6 , &LPC_IOCON->PIO1_7 , &LPC_IOCON->PIO1_8 ,
&LPC_IOCON->PIO1_9 , &LPC_IOCON->PIO1_10, &LPC_IOCON->PIO1_11,
&LPC_IOCON->PIO1_12, &LPC_IOCON->PIO1_13, &LPC_IOCON->PIO1_14,
&LPC_IOCON->PIO1_15, &LPC_IOCON->PIO1_16, &LPC_IOCON->PIO1_17,
&LPC_IOCON->PIO1_18, &LPC_IOCON->PIO1_19, &LPC_IOCON->PIO1_20,
&LPC_IOCON->PIO1_21, &LPC_IOCON->PIO1_22, &LPC_IOCON->PIO1_23,
&LPC_IOCON->PIO1_24, &LPC_IOCON->PIO1_25, &LPC_IOCON->PIO1_26,
&LPC_IOCON->PIO1_27, &LPC_IOCON->PIO1_28, &LPC_IOCON->PIO1_29,
&LPC_IOCON->PIO1_30, &LPC_IOCON->PIO1_31,
&LPC_IOCON->PIO2_0 , &LPC_IOCON->PIO2_1 , &LPC_IOCON->PIO2_2 ,
&LPC_IOCON->PIO2_3 , &LPC_IOCON->PIO2_4 , &LPC_IOCON->PIO2_5 ,
&LPC_IOCON->PIO2_6 , &LPC_IOCON->PIO2_7 , &LPC_IOCON->PIO2_8 ,
&LPC_IOCON->PIO2_9 , &LPC_IOCON->PIO2_10, &LPC_IOCON->PIO2_11,
};
void pin_function(PinName pin, int function) {
}
void pin_mode(PinName pin, PinMode mode) {
if (pin == (uint32_t)NC) { return; }
if ((pin == 22) || (pin == 23)) {
// The true open-drain pins PIO0_22 and PIO0_23 can be configured for different I2C-bus speeds.
return;
}
__IO uint32_t *reg = IOCON_REGISTERS[pin];
if (mode == OpenDrain) {
*reg |= (1 << 10);
} else {
uint32_t tmp = *reg;
tmp &= ~(0x3 << 3);
tmp |= (mode & 0x3) << 3;
*reg = tmp;
}
}

93
libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC15XX/us_ticker.c Normal file
View File

@ -0,0 +1,93 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#define US_TICKER_TIMER_IRQn SCT0_IRQn
int us_ticker_inited = 0;
void us_ticker_init(void) {
if (us_ticker_inited) return;
us_ticker_inited = 1;
// Enable the SCT0 clock
LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << 3);
// Clear peripheral reset the SCT0:
LPC_SYSCON->PRESETCTRL1 |= (1 << 2);
// Unified counter (32 bits)
LPC_SCT0->CONFIG |= 1;
// halt and clear the counter
LPC_SCT0->CTRL |= (1 << 2) | (1 << 3);
// System Clock (12)MHz -> us_ticker (1)MHz
LPC_SCT0->CTRL |= ((SystemCoreClock/1000000 - 1) << 5);
// unhalt the counter:
// - clearing bit 2 of the CTRL register
LPC_SCT0->CTRL &= ~(1 << 2);
NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}
uint32_t us_ticker_read() {
if (!us_ticker_inited)
us_ticker_init();
return LPC_SCT0->COUNT;
}
void us_ticker_set_interrupt(unsigned int timestamp) {
// halt the counter:
// - setting bit 2 of the CTRL register
LPC_SCT0->CTRL |= (1 << 2);
// set timestamp in compare register
LPC_SCT0->MATCH0 = timestamp;
// unhalt the counter:
// - clearing bit 2 of the CTRL register
LPC_SCT0->CTRL &= ~(1 << 2);
// if events are not enabled, enable them
if (!(LPC_SCT0->EVEN & 0x01)) {
// comb mode = match only
LPC_SCT0->EV0_CTRL = (1 << 12);
// ref manual:
// In simple applications that do not
// use states, write 0x01 to this
// register to enable an event
LPC_SCT0->EV0_STATE |= 0x1;
// enable events
LPC_SCT0->EVEN |= 0x1;
}
}
void us_ticker_disable_interrupt(void) {
LPC_SCT0->EVEN &= ~1;
}
void us_ticker_clear_interrupt(void) {
LPC_SCT0->EVFLAG = 1;
}

12
workspace_tools/targets.py
View File

@ -389,6 +389,15 @@ class UBLOX_C027(Target):
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "GCC_CS", "GCC_CR", "IAR"]
class LPC1549(Target):
def __init__(self):
Target.__init__(self)
self.core = "Cortex-M3"
self.extra_labels = ['NXP', 'LPC15XX']
self.supported_toolchains = ["uARM"]
# Get a single instance for each target
TARGETS = [
@ -415,7 +424,8 @@ TARGETS = [
LPC11C24(),
LPC11U35_401(),
NRF51822(),
UBLOX_C027()
UBLOX_C027(),
LPC1549()
]
# Map each target name to its unique instance